xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td (revision 13ec1e3155c7e9bf037b12af186351b7fa9b9450) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11def A2_abs : HInst<
12(outs IntRegs:$Rd32),
13(ins IntRegs:$Rs32),
14"$Rd32 = abs($Rs32)",
15tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
16let Inst{13-5} = 0b000000100;
17let Inst{31-21} = 0b10001100100;
18let hasNewValue = 1;
19let opNewValue = 0;
20let prefersSlot3 = 1;
21}
22def A2_absp : HInst<
23(outs DoubleRegs:$Rdd32),
24(ins DoubleRegs:$Rss32),
25"$Rdd32 = abs($Rss32)",
26tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
27let Inst{13-5} = 0b000000110;
28let Inst{31-21} = 0b10000000100;
29let prefersSlot3 = 1;
30}
31def A2_abssat : HInst<
32(outs IntRegs:$Rd32),
33(ins IntRegs:$Rs32),
34"$Rd32 = abs($Rs32):sat",
35tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
36let Inst{13-5} = 0b000000101;
37let Inst{31-21} = 0b10001100100;
38let hasNewValue = 1;
39let opNewValue = 0;
40let prefersSlot3 = 1;
41let Defs = [USR_OVF];
42}
43def A2_add : HInst<
44(outs IntRegs:$Rd32),
45(ins IntRegs:$Rs32, IntRegs:$Rt32),
46"$Rd32 = add($Rs32,$Rt32)",
47tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
48let Inst{7-5} = 0b000;
49let Inst{13-13} = 0b0;
50let Inst{31-21} = 0b11110011000;
51let hasNewValue = 1;
52let opNewValue = 0;
53let BaseOpcode = "A2_add";
54let CextOpcode = "A2_add";
55let InputType = "reg";
56let isCommutable = 1;
57let isPredicable = 1;
58}
59def A2_addh_h16_hh : HInst<
60(outs IntRegs:$Rd32),
61(ins IntRegs:$Rt32, IntRegs:$Rs32),
62"$Rd32 = add($Rt32.h,$Rs32.h):<<16",
63tc_01d44cb2, TypeALU64>, Enc_bd6011 {
64let Inst{7-5} = 0b011;
65let Inst{13-13} = 0b0;
66let Inst{31-21} = 0b11010101010;
67let hasNewValue = 1;
68let opNewValue = 0;
69let prefersSlot3 = 1;
70}
71def A2_addh_h16_hl : HInst<
72(outs IntRegs:$Rd32),
73(ins IntRegs:$Rt32, IntRegs:$Rs32),
74"$Rd32 = add($Rt32.h,$Rs32.l):<<16",
75tc_01d44cb2, TypeALU64>, Enc_bd6011 {
76let Inst{7-5} = 0b010;
77let Inst{13-13} = 0b0;
78let Inst{31-21} = 0b11010101010;
79let hasNewValue = 1;
80let opNewValue = 0;
81let prefersSlot3 = 1;
82}
83def A2_addh_h16_lh : HInst<
84(outs IntRegs:$Rd32),
85(ins IntRegs:$Rt32, IntRegs:$Rs32),
86"$Rd32 = add($Rt32.l,$Rs32.h):<<16",
87tc_01d44cb2, TypeALU64>, Enc_bd6011 {
88let Inst{7-5} = 0b001;
89let Inst{13-13} = 0b0;
90let Inst{31-21} = 0b11010101010;
91let hasNewValue = 1;
92let opNewValue = 0;
93let prefersSlot3 = 1;
94}
95def A2_addh_h16_ll : HInst<
96(outs IntRegs:$Rd32),
97(ins IntRegs:$Rt32, IntRegs:$Rs32),
98"$Rd32 = add($Rt32.l,$Rs32.l):<<16",
99tc_01d44cb2, TypeALU64>, Enc_bd6011 {
100let Inst{7-5} = 0b000;
101let Inst{13-13} = 0b0;
102let Inst{31-21} = 0b11010101010;
103let hasNewValue = 1;
104let opNewValue = 0;
105let prefersSlot3 = 1;
106}
107def A2_addh_h16_sat_hh : HInst<
108(outs IntRegs:$Rd32),
109(ins IntRegs:$Rt32, IntRegs:$Rs32),
110"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16",
111tc_8a825db2, TypeALU64>, Enc_bd6011 {
112let Inst{7-5} = 0b111;
113let Inst{13-13} = 0b0;
114let Inst{31-21} = 0b11010101010;
115let hasNewValue = 1;
116let opNewValue = 0;
117let prefersSlot3 = 1;
118let Defs = [USR_OVF];
119}
120def A2_addh_h16_sat_hl : HInst<
121(outs IntRegs:$Rd32),
122(ins IntRegs:$Rt32, IntRegs:$Rs32),
123"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16",
124tc_8a825db2, TypeALU64>, Enc_bd6011 {
125let Inst{7-5} = 0b110;
126let Inst{13-13} = 0b0;
127let Inst{31-21} = 0b11010101010;
128let hasNewValue = 1;
129let opNewValue = 0;
130let prefersSlot3 = 1;
131let Defs = [USR_OVF];
132}
133def A2_addh_h16_sat_lh : HInst<
134(outs IntRegs:$Rd32),
135(ins IntRegs:$Rt32, IntRegs:$Rs32),
136"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16",
137tc_8a825db2, TypeALU64>, Enc_bd6011 {
138let Inst{7-5} = 0b101;
139let Inst{13-13} = 0b0;
140let Inst{31-21} = 0b11010101010;
141let hasNewValue = 1;
142let opNewValue = 0;
143let prefersSlot3 = 1;
144let Defs = [USR_OVF];
145}
146def A2_addh_h16_sat_ll : HInst<
147(outs IntRegs:$Rd32),
148(ins IntRegs:$Rt32, IntRegs:$Rs32),
149"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16",
150tc_8a825db2, TypeALU64>, Enc_bd6011 {
151let Inst{7-5} = 0b100;
152let Inst{13-13} = 0b0;
153let Inst{31-21} = 0b11010101010;
154let hasNewValue = 1;
155let opNewValue = 0;
156let prefersSlot3 = 1;
157let Defs = [USR_OVF];
158}
159def A2_addh_l16_hl : HInst<
160(outs IntRegs:$Rd32),
161(ins IntRegs:$Rt32, IntRegs:$Rs32),
162"$Rd32 = add($Rt32.l,$Rs32.h)",
163tc_f34c1c21, TypeALU64>, Enc_bd6011 {
164let Inst{7-5} = 0b010;
165let Inst{13-13} = 0b0;
166let Inst{31-21} = 0b11010101000;
167let hasNewValue = 1;
168let opNewValue = 0;
169let prefersSlot3 = 1;
170}
171def A2_addh_l16_ll : HInst<
172(outs IntRegs:$Rd32),
173(ins IntRegs:$Rt32, IntRegs:$Rs32),
174"$Rd32 = add($Rt32.l,$Rs32.l)",
175tc_f34c1c21, TypeALU64>, Enc_bd6011 {
176let Inst{7-5} = 0b000;
177let Inst{13-13} = 0b0;
178let Inst{31-21} = 0b11010101000;
179let hasNewValue = 1;
180let opNewValue = 0;
181let prefersSlot3 = 1;
182}
183def A2_addh_l16_sat_hl : HInst<
184(outs IntRegs:$Rd32),
185(ins IntRegs:$Rt32, IntRegs:$Rs32),
186"$Rd32 = add($Rt32.l,$Rs32.h):sat",
187tc_8a825db2, TypeALU64>, Enc_bd6011 {
188let Inst{7-5} = 0b110;
189let Inst{13-13} = 0b0;
190let Inst{31-21} = 0b11010101000;
191let hasNewValue = 1;
192let opNewValue = 0;
193let prefersSlot3 = 1;
194let Defs = [USR_OVF];
195}
196def A2_addh_l16_sat_ll : HInst<
197(outs IntRegs:$Rd32),
198(ins IntRegs:$Rt32, IntRegs:$Rs32),
199"$Rd32 = add($Rt32.l,$Rs32.l):sat",
200tc_8a825db2, TypeALU64>, Enc_bd6011 {
201let Inst{7-5} = 0b100;
202let Inst{13-13} = 0b0;
203let Inst{31-21} = 0b11010101000;
204let hasNewValue = 1;
205let opNewValue = 0;
206let prefersSlot3 = 1;
207let Defs = [USR_OVF];
208}
209def A2_addi : HInst<
210(outs IntRegs:$Rd32),
211(ins IntRegs:$Rs32, s32_0Imm:$Ii),
212"$Rd32 = add($Rs32,#$Ii)",
213tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel {
214let Inst{31-28} = 0b1011;
215let hasNewValue = 1;
216let opNewValue = 0;
217let BaseOpcode = "A2_addi";
218let CextOpcode = "A2_add";
219let InputType = "imm";
220let isAdd = 1;
221let isPredicable = 1;
222let isExtendable = 1;
223let opExtendable = 2;
224let isExtentSigned = 1;
225let opExtentBits = 16;
226let opExtentAlign = 0;
227}
228def A2_addp : HInst<
229(outs DoubleRegs:$Rdd32),
230(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
231"$Rdd32 = add($Rss32,$Rtt32)",
232tc_5da50c4b, TypeALU64>, Enc_a56825 {
233let Inst{7-5} = 0b111;
234let Inst{13-13} = 0b0;
235let Inst{31-21} = 0b11010011000;
236let isAdd = 1;
237let isCommutable = 1;
238}
239def A2_addpsat : HInst<
240(outs DoubleRegs:$Rdd32),
241(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
242"$Rdd32 = add($Rss32,$Rtt32):sat",
243tc_8a825db2, TypeALU64>, Enc_a56825 {
244let Inst{7-5} = 0b101;
245let Inst{13-13} = 0b0;
246let Inst{31-21} = 0b11010011011;
247let prefersSlot3 = 1;
248let Defs = [USR_OVF];
249let isCommutable = 1;
250}
251def A2_addsat : HInst<
252(outs IntRegs:$Rd32),
253(ins IntRegs:$Rs32, IntRegs:$Rt32),
254"$Rd32 = add($Rs32,$Rt32):sat",
255tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
256let Inst{7-5} = 0b000;
257let Inst{13-13} = 0b0;
258let Inst{31-21} = 0b11110110010;
259let hasNewValue = 1;
260let opNewValue = 0;
261let prefersSlot3 = 1;
262let Defs = [USR_OVF];
263let InputType = "reg";
264let isCommutable = 1;
265}
266def A2_addsp : HInst<
267(outs DoubleRegs:$Rdd32),
268(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
269"$Rdd32 = add($Rs32,$Rtt32)",
270tc_01d44cb2, TypeALU64> {
271let isPseudo = 1;
272}
273def A2_addsph : HInst<
274(outs DoubleRegs:$Rdd32),
275(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
276"$Rdd32 = add($Rss32,$Rtt32):raw:hi",
277tc_01d44cb2, TypeALU64>, Enc_a56825 {
278let Inst{7-5} = 0b111;
279let Inst{13-13} = 0b0;
280let Inst{31-21} = 0b11010011011;
281let prefersSlot3 = 1;
282}
283def A2_addspl : HInst<
284(outs DoubleRegs:$Rdd32),
285(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
286"$Rdd32 = add($Rss32,$Rtt32):raw:lo",
287tc_01d44cb2, TypeALU64>, Enc_a56825 {
288let Inst{7-5} = 0b110;
289let Inst{13-13} = 0b0;
290let Inst{31-21} = 0b11010011011;
291let prefersSlot3 = 1;
292}
293def A2_and : HInst<
294(outs IntRegs:$Rd32),
295(ins IntRegs:$Rs32, IntRegs:$Rt32),
296"$Rd32 = and($Rs32,$Rt32)",
297tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
298let Inst{7-5} = 0b000;
299let Inst{13-13} = 0b0;
300let Inst{31-21} = 0b11110001000;
301let hasNewValue = 1;
302let opNewValue = 0;
303let BaseOpcode = "A2_and";
304let CextOpcode = "A2_and";
305let InputType = "reg";
306let isCommutable = 1;
307let isPredicable = 1;
308}
309def A2_andir : HInst<
310(outs IntRegs:$Rd32),
311(ins IntRegs:$Rs32, s32_0Imm:$Ii),
312"$Rd32 = and($Rs32,#$Ii)",
313tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
314let Inst{31-22} = 0b0111011000;
315let hasNewValue = 1;
316let opNewValue = 0;
317let CextOpcode = "A2_and";
318let InputType = "imm";
319let isExtendable = 1;
320let opExtendable = 2;
321let isExtentSigned = 1;
322let opExtentBits = 10;
323let opExtentAlign = 0;
324}
325def A2_andp : HInst<
326(outs DoubleRegs:$Rdd32),
327(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
328"$Rdd32 = and($Rss32,$Rtt32)",
329tc_5da50c4b, TypeALU64>, Enc_a56825 {
330let Inst{7-5} = 0b000;
331let Inst{13-13} = 0b0;
332let Inst{31-21} = 0b11010011111;
333let isCommutable = 1;
334}
335def A2_aslh : HInst<
336(outs IntRegs:$Rd32),
337(ins IntRegs:$Rs32),
338"$Rd32 = aslh($Rs32)",
339tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
340let Inst{13-5} = 0b000000000;
341let Inst{31-21} = 0b01110000000;
342let hasNewValue = 1;
343let opNewValue = 0;
344let BaseOpcode = "A2_aslh";
345let isPredicable = 1;
346}
347def A2_asrh : HInst<
348(outs IntRegs:$Rd32),
349(ins IntRegs:$Rs32),
350"$Rd32 = asrh($Rs32)",
351tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
352let Inst{13-5} = 0b000000000;
353let Inst{31-21} = 0b01110000001;
354let hasNewValue = 1;
355let opNewValue = 0;
356let BaseOpcode = "A2_asrh";
357let isPredicable = 1;
358}
359def A2_combine_hh : HInst<
360(outs IntRegs:$Rd32),
361(ins IntRegs:$Rt32, IntRegs:$Rs32),
362"$Rd32 = combine($Rt32.h,$Rs32.h)",
363tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
364let Inst{7-5} = 0b000;
365let Inst{13-13} = 0b0;
366let Inst{31-21} = 0b11110011100;
367let hasNewValue = 1;
368let opNewValue = 0;
369let InputType = "reg";
370}
371def A2_combine_hl : HInst<
372(outs IntRegs:$Rd32),
373(ins IntRegs:$Rt32, IntRegs:$Rs32),
374"$Rd32 = combine($Rt32.h,$Rs32.l)",
375tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
376let Inst{7-5} = 0b000;
377let Inst{13-13} = 0b0;
378let Inst{31-21} = 0b11110011101;
379let hasNewValue = 1;
380let opNewValue = 0;
381let InputType = "reg";
382}
383def A2_combine_lh : HInst<
384(outs IntRegs:$Rd32),
385(ins IntRegs:$Rt32, IntRegs:$Rs32),
386"$Rd32 = combine($Rt32.l,$Rs32.h)",
387tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
388let Inst{7-5} = 0b000;
389let Inst{13-13} = 0b0;
390let Inst{31-21} = 0b11110011110;
391let hasNewValue = 1;
392let opNewValue = 0;
393let InputType = "reg";
394}
395def A2_combine_ll : HInst<
396(outs IntRegs:$Rd32),
397(ins IntRegs:$Rt32, IntRegs:$Rs32),
398"$Rd32 = combine($Rt32.l,$Rs32.l)",
399tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
400let Inst{7-5} = 0b000;
401let Inst{13-13} = 0b0;
402let Inst{31-21} = 0b11110011111;
403let hasNewValue = 1;
404let opNewValue = 0;
405let InputType = "reg";
406}
407def A2_combineii : HInst<
408(outs DoubleRegs:$Rdd32),
409(ins s32_0Imm:$Ii, s8_0Imm:$II),
410"$Rdd32 = combine(#$Ii,#$II)",
411tc_713b66bf, TypeALU32_2op>, Enc_18c338 {
412let Inst{31-23} = 0b011111000;
413let isAsCheapAsAMove = 1;
414let isMoveImm = 1;
415let isReMaterializable = 1;
416let isExtendable = 1;
417let opExtendable = 1;
418let isExtentSigned = 1;
419let opExtentBits = 8;
420let opExtentAlign = 0;
421}
422def A2_combinew : HInst<
423(outs DoubleRegs:$Rdd32),
424(ins IntRegs:$Rs32, IntRegs:$Rt32),
425"$Rdd32 = combine($Rs32,$Rt32)",
426tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel {
427let Inst{7-5} = 0b000;
428let Inst{13-13} = 0b0;
429let Inst{31-21} = 0b11110101000;
430let BaseOpcode = "A2_combinew";
431let InputType = "reg";
432let isPredicable = 1;
433}
434def A2_max : HInst<
435(outs IntRegs:$Rd32),
436(ins IntRegs:$Rs32, IntRegs:$Rt32),
437"$Rd32 = max($Rs32,$Rt32)",
438tc_8a825db2, TypeALU64>, Enc_5ab2be {
439let Inst{7-5} = 0b000;
440let Inst{13-13} = 0b0;
441let Inst{31-21} = 0b11010101110;
442let hasNewValue = 1;
443let opNewValue = 0;
444let prefersSlot3 = 1;
445}
446def A2_maxp : HInst<
447(outs DoubleRegs:$Rdd32),
448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
449"$Rdd32 = max($Rss32,$Rtt32)",
450tc_8a825db2, TypeALU64>, Enc_a56825 {
451let Inst{7-5} = 0b100;
452let Inst{13-13} = 0b0;
453let Inst{31-21} = 0b11010011110;
454let prefersSlot3 = 1;
455}
456def A2_maxu : HInst<
457(outs IntRegs:$Rd32),
458(ins IntRegs:$Rs32, IntRegs:$Rt32),
459"$Rd32 = maxu($Rs32,$Rt32)",
460tc_8a825db2, TypeALU64>, Enc_5ab2be {
461let Inst{7-5} = 0b100;
462let Inst{13-13} = 0b0;
463let Inst{31-21} = 0b11010101110;
464let hasNewValue = 1;
465let opNewValue = 0;
466let prefersSlot3 = 1;
467}
468def A2_maxup : HInst<
469(outs DoubleRegs:$Rdd32),
470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
471"$Rdd32 = maxu($Rss32,$Rtt32)",
472tc_8a825db2, TypeALU64>, Enc_a56825 {
473let Inst{7-5} = 0b101;
474let Inst{13-13} = 0b0;
475let Inst{31-21} = 0b11010011110;
476let prefersSlot3 = 1;
477}
478def A2_min : HInst<
479(outs IntRegs:$Rd32),
480(ins IntRegs:$Rt32, IntRegs:$Rs32),
481"$Rd32 = min($Rt32,$Rs32)",
482tc_8a825db2, TypeALU64>, Enc_bd6011 {
483let Inst{7-5} = 0b000;
484let Inst{13-13} = 0b0;
485let Inst{31-21} = 0b11010101101;
486let hasNewValue = 1;
487let opNewValue = 0;
488let prefersSlot3 = 1;
489}
490def A2_minp : HInst<
491(outs DoubleRegs:$Rdd32),
492(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
493"$Rdd32 = min($Rtt32,$Rss32)",
494tc_8a825db2, TypeALU64>, Enc_ea23e4 {
495let Inst{7-5} = 0b110;
496let Inst{13-13} = 0b0;
497let Inst{31-21} = 0b11010011101;
498let prefersSlot3 = 1;
499}
500def A2_minu : HInst<
501(outs IntRegs:$Rd32),
502(ins IntRegs:$Rt32, IntRegs:$Rs32),
503"$Rd32 = minu($Rt32,$Rs32)",
504tc_8a825db2, TypeALU64>, Enc_bd6011 {
505let Inst{7-5} = 0b100;
506let Inst{13-13} = 0b0;
507let Inst{31-21} = 0b11010101101;
508let hasNewValue = 1;
509let opNewValue = 0;
510let prefersSlot3 = 1;
511}
512def A2_minup : HInst<
513(outs DoubleRegs:$Rdd32),
514(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
515"$Rdd32 = minu($Rtt32,$Rss32)",
516tc_8a825db2, TypeALU64>, Enc_ea23e4 {
517let Inst{7-5} = 0b111;
518let Inst{13-13} = 0b0;
519let Inst{31-21} = 0b11010011101;
520let prefersSlot3 = 1;
521}
522def A2_neg : HInst<
523(outs IntRegs:$Rd32),
524(ins IntRegs:$Rs32),
525"$Rd32 = neg($Rs32)",
526tc_c57d9f39, TypeALU32_2op> {
527let hasNewValue = 1;
528let opNewValue = 0;
529let isPseudo = 1;
530let isCodeGenOnly = 1;
531}
532def A2_negp : HInst<
533(outs DoubleRegs:$Rdd32),
534(ins DoubleRegs:$Rss32),
535"$Rdd32 = neg($Rss32)",
536tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
537let Inst{13-5} = 0b000000101;
538let Inst{31-21} = 0b10000000100;
539}
540def A2_negsat : HInst<
541(outs IntRegs:$Rd32),
542(ins IntRegs:$Rs32),
543"$Rd32 = neg($Rs32):sat",
544tc_d61dfdc3, TypeS_2op>, Enc_5e2823 {
545let Inst{13-5} = 0b000000110;
546let Inst{31-21} = 0b10001100100;
547let hasNewValue = 1;
548let opNewValue = 0;
549let prefersSlot3 = 1;
550let Defs = [USR_OVF];
551}
552def A2_nop : HInst<
553(outs),
554(ins),
555"nop",
556tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 {
557let Inst{13-0} = 0b00000000000000;
558let Inst{31-16} = 0b0111111100000000;
559}
560def A2_not : HInst<
561(outs IntRegs:$Rd32),
562(ins IntRegs:$Rs32),
563"$Rd32 = not($Rs32)",
564tc_c57d9f39, TypeALU32_2op> {
565let hasNewValue = 1;
566let opNewValue = 0;
567let isPseudo = 1;
568let isCodeGenOnly = 1;
569}
570def A2_notp : HInst<
571(outs DoubleRegs:$Rdd32),
572(ins DoubleRegs:$Rss32),
573"$Rdd32 = not($Rss32)",
574tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
575let Inst{13-5} = 0b000000100;
576let Inst{31-21} = 0b10000000100;
577}
578def A2_or : HInst<
579(outs IntRegs:$Rd32),
580(ins IntRegs:$Rs32, IntRegs:$Rt32),
581"$Rd32 = or($Rs32,$Rt32)",
582tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel {
583let Inst{7-5} = 0b000;
584let Inst{13-13} = 0b0;
585let Inst{31-21} = 0b11110001001;
586let hasNewValue = 1;
587let opNewValue = 0;
588let BaseOpcode = "A2_or";
589let CextOpcode = "A2_or";
590let InputType = "reg";
591let isCommutable = 1;
592let isPredicable = 1;
593}
594def A2_orir : HInst<
595(outs IntRegs:$Rd32),
596(ins IntRegs:$Rs32, s32_0Imm:$Ii),
597"$Rd32 = or($Rs32,#$Ii)",
598tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel {
599let Inst{31-22} = 0b0111011010;
600let hasNewValue = 1;
601let opNewValue = 0;
602let CextOpcode = "A2_or";
603let InputType = "imm";
604let isExtendable = 1;
605let opExtendable = 2;
606let isExtentSigned = 1;
607let opExtentBits = 10;
608let opExtentAlign = 0;
609}
610def A2_orp : HInst<
611(outs DoubleRegs:$Rdd32),
612(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
613"$Rdd32 = or($Rss32,$Rtt32)",
614tc_5da50c4b, TypeALU64>, Enc_a56825 {
615let Inst{7-5} = 0b010;
616let Inst{13-13} = 0b0;
617let Inst{31-21} = 0b11010011111;
618let isCommutable = 1;
619}
620def A2_paddf : HInst<
621(outs IntRegs:$Rd32),
622(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
623"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)",
624tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
625let Inst{7-7} = 0b1;
626let Inst{13-13} = 0b0;
627let Inst{31-21} = 0b11111011000;
628let isPredicated = 1;
629let isPredicatedFalse = 1;
630let hasNewValue = 1;
631let opNewValue = 0;
632let BaseOpcode = "A2_add";
633let CextOpcode = "A2_add";
634let InputType = "reg";
635}
636def A2_paddfnew : HInst<
637(outs IntRegs:$Rd32),
638(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
639"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)",
640tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
641let Inst{7-7} = 0b1;
642let Inst{13-13} = 0b1;
643let Inst{31-21} = 0b11111011000;
644let isPredicated = 1;
645let isPredicatedFalse = 1;
646let hasNewValue = 1;
647let opNewValue = 0;
648let isPredicatedNew = 1;
649let BaseOpcode = "A2_add";
650let CextOpcode = "A2_add";
651let InputType = "reg";
652}
653def A2_paddif : HInst<
654(outs IntRegs:$Rd32),
655(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
656"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)",
657tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
658let Inst{13-13} = 0b0;
659let Inst{31-23} = 0b011101001;
660let isPredicated = 1;
661let isPredicatedFalse = 1;
662let hasNewValue = 1;
663let opNewValue = 0;
664let BaseOpcode = "A2_addi";
665let CextOpcode = "A2_add";
666let InputType = "imm";
667let isExtendable = 1;
668let opExtendable = 3;
669let isExtentSigned = 1;
670let opExtentBits = 8;
671let opExtentAlign = 0;
672}
673def A2_paddifnew : HInst<
674(outs IntRegs:$Rd32),
675(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
676"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)",
677tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
678let Inst{13-13} = 0b1;
679let Inst{31-23} = 0b011101001;
680let isPredicated = 1;
681let isPredicatedFalse = 1;
682let hasNewValue = 1;
683let opNewValue = 0;
684let isPredicatedNew = 1;
685let BaseOpcode = "A2_addi";
686let CextOpcode = "A2_add";
687let InputType = "imm";
688let isExtendable = 1;
689let opExtendable = 3;
690let isExtentSigned = 1;
691let opExtentBits = 8;
692let opExtentAlign = 0;
693}
694def A2_paddit : HInst<
695(outs IntRegs:$Rd32),
696(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
697"if ($Pu4) $Rd32 = add($Rs32,#$Ii)",
698tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
699let Inst{13-13} = 0b0;
700let Inst{31-23} = 0b011101000;
701let isPredicated = 1;
702let hasNewValue = 1;
703let opNewValue = 0;
704let BaseOpcode = "A2_addi";
705let CextOpcode = "A2_add";
706let InputType = "imm";
707let isExtendable = 1;
708let opExtendable = 3;
709let isExtentSigned = 1;
710let opExtentBits = 8;
711let opExtentAlign = 0;
712}
713def A2_padditnew : HInst<
714(outs IntRegs:$Rd32),
715(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
716"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)",
717tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel {
718let Inst{13-13} = 0b1;
719let Inst{31-23} = 0b011101000;
720let isPredicated = 1;
721let hasNewValue = 1;
722let opNewValue = 0;
723let isPredicatedNew = 1;
724let BaseOpcode = "A2_addi";
725let CextOpcode = "A2_add";
726let InputType = "imm";
727let isExtendable = 1;
728let opExtendable = 3;
729let isExtentSigned = 1;
730let opExtentBits = 8;
731let opExtentAlign = 0;
732}
733def A2_paddt : HInst<
734(outs IntRegs:$Rd32),
735(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
736"if ($Pu4) $Rd32 = add($Rs32,$Rt32)",
737tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
738let Inst{7-7} = 0b0;
739let Inst{13-13} = 0b0;
740let Inst{31-21} = 0b11111011000;
741let isPredicated = 1;
742let hasNewValue = 1;
743let opNewValue = 0;
744let BaseOpcode = "A2_add";
745let CextOpcode = "A2_add";
746let InputType = "reg";
747}
748def A2_paddtnew : HInst<
749(outs IntRegs:$Rd32),
750(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
751"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)",
752tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel {
753let Inst{7-7} = 0b0;
754let Inst{13-13} = 0b1;
755let Inst{31-21} = 0b11111011000;
756let isPredicated = 1;
757let hasNewValue = 1;
758let opNewValue = 0;
759let isPredicatedNew = 1;
760let BaseOpcode = "A2_add";
761let CextOpcode = "A2_add";
762let InputType = "reg";
763}
764def A2_pandf : HInst<
765(outs IntRegs:$Rd32),
766(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
767"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)",
768tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
769let Inst{7-7} = 0b1;
770let Inst{13-13} = 0b0;
771let Inst{31-21} = 0b11111001000;
772let isPredicated = 1;
773let isPredicatedFalse = 1;
774let hasNewValue = 1;
775let opNewValue = 0;
776let BaseOpcode = "A2_and";
777}
778def A2_pandfnew : HInst<
779(outs IntRegs:$Rd32),
780(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
781"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)",
782tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
783let Inst{7-7} = 0b1;
784let Inst{13-13} = 0b1;
785let Inst{31-21} = 0b11111001000;
786let isPredicated = 1;
787let isPredicatedFalse = 1;
788let hasNewValue = 1;
789let opNewValue = 0;
790let isPredicatedNew = 1;
791let BaseOpcode = "A2_and";
792}
793def A2_pandt : HInst<
794(outs IntRegs:$Rd32),
795(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
796"if ($Pu4) $Rd32 = and($Rs32,$Rt32)",
797tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
798let Inst{7-7} = 0b0;
799let Inst{13-13} = 0b0;
800let Inst{31-21} = 0b11111001000;
801let isPredicated = 1;
802let hasNewValue = 1;
803let opNewValue = 0;
804let BaseOpcode = "A2_and";
805}
806def A2_pandtnew : HInst<
807(outs IntRegs:$Rd32),
808(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
809"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)",
810tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
811let Inst{7-7} = 0b0;
812let Inst{13-13} = 0b1;
813let Inst{31-21} = 0b11111001000;
814let isPredicated = 1;
815let hasNewValue = 1;
816let opNewValue = 0;
817let isPredicatedNew = 1;
818let BaseOpcode = "A2_and";
819}
820def A2_porf : HInst<
821(outs IntRegs:$Rd32),
822(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
823"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)",
824tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
825let Inst{7-7} = 0b1;
826let Inst{13-13} = 0b0;
827let Inst{31-21} = 0b11111001001;
828let isPredicated = 1;
829let isPredicatedFalse = 1;
830let hasNewValue = 1;
831let opNewValue = 0;
832let BaseOpcode = "A2_or";
833}
834def A2_porfnew : HInst<
835(outs IntRegs:$Rd32),
836(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
837"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)",
838tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
839let Inst{7-7} = 0b1;
840let Inst{13-13} = 0b1;
841let Inst{31-21} = 0b11111001001;
842let isPredicated = 1;
843let isPredicatedFalse = 1;
844let hasNewValue = 1;
845let opNewValue = 0;
846let isPredicatedNew = 1;
847let BaseOpcode = "A2_or";
848}
849def A2_port : HInst<
850(outs IntRegs:$Rd32),
851(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
852"if ($Pu4) $Rd32 = or($Rs32,$Rt32)",
853tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
854let Inst{7-7} = 0b0;
855let Inst{13-13} = 0b0;
856let Inst{31-21} = 0b11111001001;
857let isPredicated = 1;
858let hasNewValue = 1;
859let opNewValue = 0;
860let BaseOpcode = "A2_or";
861}
862def A2_portnew : HInst<
863(outs IntRegs:$Rd32),
864(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
865"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)",
866tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
867let Inst{7-7} = 0b0;
868let Inst{13-13} = 0b1;
869let Inst{31-21} = 0b11111001001;
870let isPredicated = 1;
871let hasNewValue = 1;
872let opNewValue = 0;
873let isPredicatedNew = 1;
874let BaseOpcode = "A2_or";
875}
876def A2_psubf : HInst<
877(outs IntRegs:$Rd32),
878(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
879"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)",
880tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
881let Inst{7-7} = 0b1;
882let Inst{13-13} = 0b0;
883let Inst{31-21} = 0b11111011001;
884let isPredicated = 1;
885let isPredicatedFalse = 1;
886let hasNewValue = 1;
887let opNewValue = 0;
888let BaseOpcode = "A2_sub";
889}
890def A2_psubfnew : HInst<
891(outs IntRegs:$Rd32),
892(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
893"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
894tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
895let Inst{7-7} = 0b1;
896let Inst{13-13} = 0b1;
897let Inst{31-21} = 0b11111011001;
898let isPredicated = 1;
899let isPredicatedFalse = 1;
900let hasNewValue = 1;
901let opNewValue = 0;
902let isPredicatedNew = 1;
903let BaseOpcode = "A2_sub";
904}
905def A2_psubt : HInst<
906(outs IntRegs:$Rd32),
907(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
908"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)",
909tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
910let Inst{7-7} = 0b0;
911let Inst{13-13} = 0b0;
912let Inst{31-21} = 0b11111011001;
913let isPredicated = 1;
914let hasNewValue = 1;
915let opNewValue = 0;
916let BaseOpcode = "A2_sub";
917}
918def A2_psubtnew : HInst<
919(outs IntRegs:$Rd32),
920(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32),
921"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)",
922tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel {
923let Inst{7-7} = 0b0;
924let Inst{13-13} = 0b1;
925let Inst{31-21} = 0b11111011001;
926let isPredicated = 1;
927let hasNewValue = 1;
928let opNewValue = 0;
929let isPredicatedNew = 1;
930let BaseOpcode = "A2_sub";
931}
932def A2_pxorf : HInst<
933(outs IntRegs:$Rd32),
934(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
935"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)",
936tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
937let Inst{7-7} = 0b1;
938let Inst{13-13} = 0b0;
939let Inst{31-21} = 0b11111001011;
940let isPredicated = 1;
941let isPredicatedFalse = 1;
942let hasNewValue = 1;
943let opNewValue = 0;
944let BaseOpcode = "A2_xor";
945}
946def A2_pxorfnew : HInst<
947(outs IntRegs:$Rd32),
948(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
949"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
950tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
951let Inst{7-7} = 0b1;
952let Inst{13-13} = 0b1;
953let Inst{31-21} = 0b11111001011;
954let isPredicated = 1;
955let isPredicatedFalse = 1;
956let hasNewValue = 1;
957let opNewValue = 0;
958let isPredicatedNew = 1;
959let BaseOpcode = "A2_xor";
960}
961def A2_pxort : HInst<
962(outs IntRegs:$Rd32),
963(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
964"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)",
965tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
966let Inst{7-7} = 0b0;
967let Inst{13-13} = 0b0;
968let Inst{31-21} = 0b11111001011;
969let isPredicated = 1;
970let hasNewValue = 1;
971let opNewValue = 0;
972let BaseOpcode = "A2_xor";
973}
974def A2_pxortnew : HInst<
975(outs IntRegs:$Rd32),
976(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
977"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)",
978tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel {
979let Inst{7-7} = 0b0;
980let Inst{13-13} = 0b1;
981let Inst{31-21} = 0b11111001011;
982let isPredicated = 1;
983let hasNewValue = 1;
984let opNewValue = 0;
985let isPredicatedNew = 1;
986let BaseOpcode = "A2_xor";
987}
988def A2_roundsat : HInst<
989(outs IntRegs:$Rd32),
990(ins DoubleRegs:$Rss32),
991"$Rd32 = round($Rss32):sat",
992tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
993let Inst{13-5} = 0b000000001;
994let Inst{31-21} = 0b10001000110;
995let hasNewValue = 1;
996let opNewValue = 0;
997let prefersSlot3 = 1;
998let Defs = [USR_OVF];
999}
1000def A2_sat : HInst<
1001(outs IntRegs:$Rd32),
1002(ins DoubleRegs:$Rss32),
1003"$Rd32 = sat($Rss32)",
1004tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
1005let Inst{13-5} = 0b000000000;
1006let Inst{31-21} = 0b10001000110;
1007let hasNewValue = 1;
1008let opNewValue = 0;
1009let Defs = [USR_OVF];
1010}
1011def A2_satb : HInst<
1012(outs IntRegs:$Rd32),
1013(ins IntRegs:$Rs32),
1014"$Rd32 = satb($Rs32)",
1015tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1016let Inst{13-5} = 0b000000111;
1017let Inst{31-21} = 0b10001100110;
1018let hasNewValue = 1;
1019let opNewValue = 0;
1020let Defs = [USR_OVF];
1021}
1022def A2_sath : HInst<
1023(outs IntRegs:$Rd32),
1024(ins IntRegs:$Rs32),
1025"$Rd32 = sath($Rs32)",
1026tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1027let Inst{13-5} = 0b000000100;
1028let Inst{31-21} = 0b10001100110;
1029let hasNewValue = 1;
1030let opNewValue = 0;
1031let Defs = [USR_OVF];
1032}
1033def A2_satub : HInst<
1034(outs IntRegs:$Rd32),
1035(ins IntRegs:$Rs32),
1036"$Rd32 = satub($Rs32)",
1037tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1038let Inst{13-5} = 0b000000110;
1039let Inst{31-21} = 0b10001100110;
1040let hasNewValue = 1;
1041let opNewValue = 0;
1042let Defs = [USR_OVF];
1043}
1044def A2_satuh : HInst<
1045(outs IntRegs:$Rd32),
1046(ins IntRegs:$Rs32),
1047"$Rd32 = satuh($Rs32)",
1048tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1049let Inst{13-5} = 0b000000101;
1050let Inst{31-21} = 0b10001100110;
1051let hasNewValue = 1;
1052let opNewValue = 0;
1053let Defs = [USR_OVF];
1054}
1055def A2_sub : HInst<
1056(outs IntRegs:$Rd32),
1057(ins IntRegs:$Rt32, IntRegs:$Rs32),
1058"$Rd32 = sub($Rt32,$Rs32)",
1059tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel {
1060let Inst{7-5} = 0b000;
1061let Inst{13-13} = 0b0;
1062let Inst{31-21} = 0b11110011001;
1063let hasNewValue = 1;
1064let opNewValue = 0;
1065let BaseOpcode = "A2_sub";
1066let CextOpcode = "A2_sub";
1067let InputType = "reg";
1068let isPredicable = 1;
1069}
1070def A2_subh_h16_hh : HInst<
1071(outs IntRegs:$Rd32),
1072(ins IntRegs:$Rt32, IntRegs:$Rs32),
1073"$Rd32 = sub($Rt32.h,$Rs32.h):<<16",
1074tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1075let Inst{7-5} = 0b011;
1076let Inst{13-13} = 0b0;
1077let Inst{31-21} = 0b11010101011;
1078let hasNewValue = 1;
1079let opNewValue = 0;
1080let prefersSlot3 = 1;
1081}
1082def A2_subh_h16_hl : HInst<
1083(outs IntRegs:$Rd32),
1084(ins IntRegs:$Rt32, IntRegs:$Rs32),
1085"$Rd32 = sub($Rt32.h,$Rs32.l):<<16",
1086tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1087let Inst{7-5} = 0b010;
1088let Inst{13-13} = 0b0;
1089let Inst{31-21} = 0b11010101011;
1090let hasNewValue = 1;
1091let opNewValue = 0;
1092let prefersSlot3 = 1;
1093}
1094def A2_subh_h16_lh : HInst<
1095(outs IntRegs:$Rd32),
1096(ins IntRegs:$Rt32, IntRegs:$Rs32),
1097"$Rd32 = sub($Rt32.l,$Rs32.h):<<16",
1098tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1099let Inst{7-5} = 0b001;
1100let Inst{13-13} = 0b0;
1101let Inst{31-21} = 0b11010101011;
1102let hasNewValue = 1;
1103let opNewValue = 0;
1104let prefersSlot3 = 1;
1105}
1106def A2_subh_h16_ll : HInst<
1107(outs IntRegs:$Rd32),
1108(ins IntRegs:$Rt32, IntRegs:$Rs32),
1109"$Rd32 = sub($Rt32.l,$Rs32.l):<<16",
1110tc_01d44cb2, TypeALU64>, Enc_bd6011 {
1111let Inst{7-5} = 0b000;
1112let Inst{13-13} = 0b0;
1113let Inst{31-21} = 0b11010101011;
1114let hasNewValue = 1;
1115let opNewValue = 0;
1116let prefersSlot3 = 1;
1117}
1118def A2_subh_h16_sat_hh : HInst<
1119(outs IntRegs:$Rd32),
1120(ins IntRegs:$Rt32, IntRegs:$Rs32),
1121"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16",
1122tc_8a825db2, TypeALU64>, Enc_bd6011 {
1123let Inst{7-5} = 0b111;
1124let Inst{13-13} = 0b0;
1125let Inst{31-21} = 0b11010101011;
1126let hasNewValue = 1;
1127let opNewValue = 0;
1128let prefersSlot3 = 1;
1129let Defs = [USR_OVF];
1130}
1131def A2_subh_h16_sat_hl : HInst<
1132(outs IntRegs:$Rd32),
1133(ins IntRegs:$Rt32, IntRegs:$Rs32),
1134"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16",
1135tc_8a825db2, TypeALU64>, Enc_bd6011 {
1136let Inst{7-5} = 0b110;
1137let Inst{13-13} = 0b0;
1138let Inst{31-21} = 0b11010101011;
1139let hasNewValue = 1;
1140let opNewValue = 0;
1141let prefersSlot3 = 1;
1142let Defs = [USR_OVF];
1143}
1144def A2_subh_h16_sat_lh : HInst<
1145(outs IntRegs:$Rd32),
1146(ins IntRegs:$Rt32, IntRegs:$Rs32),
1147"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16",
1148tc_8a825db2, TypeALU64>, Enc_bd6011 {
1149let Inst{7-5} = 0b101;
1150let Inst{13-13} = 0b0;
1151let Inst{31-21} = 0b11010101011;
1152let hasNewValue = 1;
1153let opNewValue = 0;
1154let prefersSlot3 = 1;
1155let Defs = [USR_OVF];
1156}
1157def A2_subh_h16_sat_ll : HInst<
1158(outs IntRegs:$Rd32),
1159(ins IntRegs:$Rt32, IntRegs:$Rs32),
1160"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16",
1161tc_8a825db2, TypeALU64>, Enc_bd6011 {
1162let Inst{7-5} = 0b100;
1163let Inst{13-13} = 0b0;
1164let Inst{31-21} = 0b11010101011;
1165let hasNewValue = 1;
1166let opNewValue = 0;
1167let prefersSlot3 = 1;
1168let Defs = [USR_OVF];
1169}
1170def A2_subh_l16_hl : HInst<
1171(outs IntRegs:$Rd32),
1172(ins IntRegs:$Rt32, IntRegs:$Rs32),
1173"$Rd32 = sub($Rt32.l,$Rs32.h)",
1174tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1175let Inst{7-5} = 0b010;
1176let Inst{13-13} = 0b0;
1177let Inst{31-21} = 0b11010101001;
1178let hasNewValue = 1;
1179let opNewValue = 0;
1180let prefersSlot3 = 1;
1181}
1182def A2_subh_l16_ll : HInst<
1183(outs IntRegs:$Rd32),
1184(ins IntRegs:$Rt32, IntRegs:$Rs32),
1185"$Rd32 = sub($Rt32.l,$Rs32.l)",
1186tc_f34c1c21, TypeALU64>, Enc_bd6011 {
1187let Inst{7-5} = 0b000;
1188let Inst{13-13} = 0b0;
1189let Inst{31-21} = 0b11010101001;
1190let hasNewValue = 1;
1191let opNewValue = 0;
1192let prefersSlot3 = 1;
1193}
1194def A2_subh_l16_sat_hl : HInst<
1195(outs IntRegs:$Rd32),
1196(ins IntRegs:$Rt32, IntRegs:$Rs32),
1197"$Rd32 = sub($Rt32.l,$Rs32.h):sat",
1198tc_8a825db2, TypeALU64>, Enc_bd6011 {
1199let Inst{7-5} = 0b110;
1200let Inst{13-13} = 0b0;
1201let Inst{31-21} = 0b11010101001;
1202let hasNewValue = 1;
1203let opNewValue = 0;
1204let prefersSlot3 = 1;
1205let Defs = [USR_OVF];
1206}
1207def A2_subh_l16_sat_ll : HInst<
1208(outs IntRegs:$Rd32),
1209(ins IntRegs:$Rt32, IntRegs:$Rs32),
1210"$Rd32 = sub($Rt32.l,$Rs32.l):sat",
1211tc_8a825db2, TypeALU64>, Enc_bd6011 {
1212let Inst{7-5} = 0b100;
1213let Inst{13-13} = 0b0;
1214let Inst{31-21} = 0b11010101001;
1215let hasNewValue = 1;
1216let opNewValue = 0;
1217let prefersSlot3 = 1;
1218let Defs = [USR_OVF];
1219}
1220def A2_subp : HInst<
1221(outs DoubleRegs:$Rdd32),
1222(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1223"$Rdd32 = sub($Rtt32,$Rss32)",
1224tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
1225let Inst{7-5} = 0b111;
1226let Inst{13-13} = 0b0;
1227let Inst{31-21} = 0b11010011001;
1228}
1229def A2_subri : HInst<
1230(outs IntRegs:$Rd32),
1231(ins s32_0Imm:$Ii, IntRegs:$Rs32),
1232"$Rd32 = sub(#$Ii,$Rs32)",
1233tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel {
1234let Inst{31-22} = 0b0111011001;
1235let hasNewValue = 1;
1236let opNewValue = 0;
1237let CextOpcode = "A2_sub";
1238let InputType = "imm";
1239let isExtendable = 1;
1240let opExtendable = 1;
1241let isExtentSigned = 1;
1242let opExtentBits = 10;
1243let opExtentAlign = 0;
1244}
1245def A2_subsat : HInst<
1246(outs IntRegs:$Rd32),
1247(ins IntRegs:$Rt32, IntRegs:$Rs32),
1248"$Rd32 = sub($Rt32,$Rs32):sat",
1249tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1250let Inst{7-5} = 0b000;
1251let Inst{13-13} = 0b0;
1252let Inst{31-21} = 0b11110110110;
1253let hasNewValue = 1;
1254let opNewValue = 0;
1255let prefersSlot3 = 1;
1256let Defs = [USR_OVF];
1257let InputType = "reg";
1258}
1259def A2_svaddh : HInst<
1260(outs IntRegs:$Rd32),
1261(ins IntRegs:$Rs32, IntRegs:$Rt32),
1262"$Rd32 = vaddh($Rs32,$Rt32)",
1263tc_713b66bf, TypeALU32_3op>, Enc_5ab2be {
1264let Inst{7-5} = 0b000;
1265let Inst{13-13} = 0b0;
1266let Inst{31-21} = 0b11110110000;
1267let hasNewValue = 1;
1268let opNewValue = 0;
1269let InputType = "reg";
1270let isCommutable = 1;
1271}
1272def A2_svaddhs : HInst<
1273(outs IntRegs:$Rd32),
1274(ins IntRegs:$Rs32, IntRegs:$Rt32),
1275"$Rd32 = vaddh($Rs32,$Rt32):sat",
1276tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1277let Inst{7-5} = 0b000;
1278let Inst{13-13} = 0b0;
1279let Inst{31-21} = 0b11110110001;
1280let hasNewValue = 1;
1281let opNewValue = 0;
1282let prefersSlot3 = 1;
1283let Defs = [USR_OVF];
1284let InputType = "reg";
1285let isCommutable = 1;
1286}
1287def A2_svadduhs : HInst<
1288(outs IntRegs:$Rd32),
1289(ins IntRegs:$Rs32, IntRegs:$Rt32),
1290"$Rd32 = vadduh($Rs32,$Rt32):sat",
1291tc_95a33176, TypeALU32_3op>, Enc_5ab2be {
1292let Inst{7-5} = 0b000;
1293let Inst{13-13} = 0b0;
1294let Inst{31-21} = 0b11110110011;
1295let hasNewValue = 1;
1296let opNewValue = 0;
1297let prefersSlot3 = 1;
1298let Defs = [USR_OVF];
1299let InputType = "reg";
1300let isCommutable = 1;
1301}
1302def A2_svavgh : HInst<
1303(outs IntRegs:$Rd32),
1304(ins IntRegs:$Rs32, IntRegs:$Rt32),
1305"$Rd32 = vavgh($Rs32,$Rt32)",
1306tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be {
1307let Inst{7-5} = 0b000;
1308let Inst{13-13} = 0b0;
1309let Inst{31-21} = 0b11110111000;
1310let hasNewValue = 1;
1311let opNewValue = 0;
1312let prefersSlot3 = 1;
1313let InputType = "reg";
1314let isCommutable = 1;
1315}
1316def A2_svavghs : HInst<
1317(outs IntRegs:$Rd32),
1318(ins IntRegs:$Rs32, IntRegs:$Rt32),
1319"$Rd32 = vavgh($Rs32,$Rt32):rnd",
1320tc_84a7500d, TypeALU32_3op>, Enc_5ab2be {
1321let Inst{7-5} = 0b000;
1322let Inst{13-13} = 0b0;
1323let Inst{31-21} = 0b11110111001;
1324let hasNewValue = 1;
1325let opNewValue = 0;
1326let prefersSlot3 = 1;
1327let InputType = "reg";
1328let isCommutable = 1;
1329}
1330def A2_svnavgh : HInst<
1331(outs IntRegs:$Rd32),
1332(ins IntRegs:$Rt32, IntRegs:$Rs32),
1333"$Rd32 = vnavgh($Rt32,$Rs32)",
1334tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 {
1335let Inst{7-5} = 0b000;
1336let Inst{13-13} = 0b0;
1337let Inst{31-21} = 0b11110111011;
1338let hasNewValue = 1;
1339let opNewValue = 0;
1340let prefersSlot3 = 1;
1341let InputType = "reg";
1342}
1343def A2_svsubh : HInst<
1344(outs IntRegs:$Rd32),
1345(ins IntRegs:$Rt32, IntRegs:$Rs32),
1346"$Rd32 = vsubh($Rt32,$Rs32)",
1347tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
1348let Inst{7-5} = 0b000;
1349let Inst{13-13} = 0b0;
1350let Inst{31-21} = 0b11110110100;
1351let hasNewValue = 1;
1352let opNewValue = 0;
1353let InputType = "reg";
1354}
1355def A2_svsubhs : HInst<
1356(outs IntRegs:$Rd32),
1357(ins IntRegs:$Rt32, IntRegs:$Rs32),
1358"$Rd32 = vsubh($Rt32,$Rs32):sat",
1359tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1360let Inst{7-5} = 0b000;
1361let Inst{13-13} = 0b0;
1362let Inst{31-21} = 0b11110110101;
1363let hasNewValue = 1;
1364let opNewValue = 0;
1365let prefersSlot3 = 1;
1366let Defs = [USR_OVF];
1367let InputType = "reg";
1368}
1369def A2_svsubuhs : HInst<
1370(outs IntRegs:$Rd32),
1371(ins IntRegs:$Rt32, IntRegs:$Rs32),
1372"$Rd32 = vsubuh($Rt32,$Rs32):sat",
1373tc_95a33176, TypeALU32_3op>, Enc_bd6011 {
1374let Inst{7-5} = 0b000;
1375let Inst{13-13} = 0b0;
1376let Inst{31-21} = 0b11110110111;
1377let hasNewValue = 1;
1378let opNewValue = 0;
1379let prefersSlot3 = 1;
1380let Defs = [USR_OVF];
1381let InputType = "reg";
1382}
1383def A2_swiz : HInst<
1384(outs IntRegs:$Rd32),
1385(ins IntRegs:$Rs32),
1386"$Rd32 = swiz($Rs32)",
1387tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
1388let Inst{13-5} = 0b000000111;
1389let Inst{31-21} = 0b10001100100;
1390let hasNewValue = 1;
1391let opNewValue = 0;
1392}
1393def A2_sxtb : HInst<
1394(outs IntRegs:$Rd32),
1395(ins IntRegs:$Rs32),
1396"$Rd32 = sxtb($Rs32)",
1397tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1398let Inst{13-5} = 0b000000000;
1399let Inst{31-21} = 0b01110000101;
1400let hasNewValue = 1;
1401let opNewValue = 0;
1402let BaseOpcode = "A2_sxtb";
1403let isPredicable = 1;
1404}
1405def A2_sxth : HInst<
1406(outs IntRegs:$Rd32),
1407(ins IntRegs:$Rs32),
1408"$Rd32 = sxth($Rs32)",
1409tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1410let Inst{13-5} = 0b000000000;
1411let Inst{31-21} = 0b01110000111;
1412let hasNewValue = 1;
1413let opNewValue = 0;
1414let BaseOpcode = "A2_sxth";
1415let isPredicable = 1;
1416}
1417def A2_sxtw : HInst<
1418(outs DoubleRegs:$Rdd32),
1419(ins IntRegs:$Rs32),
1420"$Rdd32 = sxtw($Rs32)",
1421tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
1422let Inst{13-5} = 0b000000000;
1423let Inst{31-21} = 0b10000100010;
1424}
1425def A2_tfr : HInst<
1426(outs IntRegs:$Rd32),
1427(ins IntRegs:$Rs32),
1428"$Rd32 = $Rs32",
1429tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
1430let Inst{13-5} = 0b000000000;
1431let Inst{31-21} = 0b01110000011;
1432let hasNewValue = 1;
1433let opNewValue = 0;
1434let BaseOpcode = "A2_tfr";
1435let InputType = "reg";
1436let isPredicable = 1;
1437}
1438def A2_tfrcrr : HInst<
1439(outs IntRegs:$Rd32),
1440(ins CtrRegs:$Cs32),
1441"$Rd32 = $Cs32",
1442tc_7476d766, TypeCR>, Enc_0cb018 {
1443let Inst{13-5} = 0b000000000;
1444let Inst{31-21} = 0b01101010000;
1445let hasNewValue = 1;
1446let opNewValue = 0;
1447}
1448def A2_tfrf : HInst<
1449(outs IntRegs:$Rd32),
1450(ins PredRegs:$Pu4, IntRegs:$Rs32),
1451"if (!$Pu4) $Rd32 = $Rs32",
1452tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1453let isPredicated = 1;
1454let isPredicatedFalse = 1;
1455let hasNewValue = 1;
1456let opNewValue = 0;
1457let BaseOpcode = "A2_tfr";
1458let CextOpcode = "A2_tfr";
1459let InputType = "reg";
1460let isPseudo = 1;
1461let isCodeGenOnly = 1;
1462}
1463def A2_tfrfnew : HInst<
1464(outs IntRegs:$Rd32),
1465(ins PredRegs:$Pu4, IntRegs:$Rs32),
1466"if (!$Pu4.new) $Rd32 = $Rs32",
1467tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1468let isPredicated = 1;
1469let isPredicatedFalse = 1;
1470let hasNewValue = 1;
1471let opNewValue = 0;
1472let isPredicatedNew = 1;
1473let BaseOpcode = "A2_tfr";
1474let CextOpcode = "A2_tfr";
1475let InputType = "reg";
1476let isPseudo = 1;
1477let isCodeGenOnly = 1;
1478}
1479def A2_tfrih : HInst<
1480(outs IntRegs:$Rx32),
1481(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1482"$Rx32.h = #$Ii",
1483tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1484let Inst{21-21} = 0b1;
1485let Inst{31-24} = 0b01110010;
1486let hasNewValue = 1;
1487let opNewValue = 0;
1488let Constraints = "$Rx32 = $Rx32in";
1489}
1490def A2_tfril : HInst<
1491(outs IntRegs:$Rx32),
1492(ins IntRegs:$Rx32in, u16_0Imm:$Ii),
1493"$Rx32.l = #$Ii",
1494tc_713b66bf, TypeALU32_2op>, Enc_51436c {
1495let Inst{21-21} = 0b1;
1496let Inst{31-24} = 0b01110001;
1497let hasNewValue = 1;
1498let opNewValue = 0;
1499let Constraints = "$Rx32 = $Rx32in";
1500}
1501def A2_tfrp : HInst<
1502(outs DoubleRegs:$Rdd32),
1503(ins DoubleRegs:$Rss32),
1504"$Rdd32 = $Rss32",
1505tc_713b66bf, TypeALU32_2op>, PredNewRel {
1506let BaseOpcode = "A2_tfrp";
1507let isPredicable = 1;
1508let isPseudo = 1;
1509}
1510def A2_tfrpf : HInst<
1511(outs DoubleRegs:$Rdd32),
1512(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1513"if (!$Pu4) $Rdd32 = $Rss32",
1514tc_713b66bf, TypeALU32_2op>, PredNewRel {
1515let isPredicated = 1;
1516let isPredicatedFalse = 1;
1517let BaseOpcode = "A2_tfrp";
1518let isPseudo = 1;
1519}
1520def A2_tfrpfnew : HInst<
1521(outs DoubleRegs:$Rdd32),
1522(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1523"if (!$Pu4.new) $Rdd32 = $Rss32",
1524tc_86173609, TypeALU32_2op>, PredNewRel {
1525let isPredicated = 1;
1526let isPredicatedFalse = 1;
1527let isPredicatedNew = 1;
1528let BaseOpcode = "A2_tfrp";
1529let isPseudo = 1;
1530}
1531def A2_tfrpi : HInst<
1532(outs DoubleRegs:$Rdd32),
1533(ins s8_0Imm:$Ii),
1534"$Rdd32 = #$Ii",
1535tc_713b66bf, TypeALU64> {
1536let isAsCheapAsAMove = 1;
1537let isMoveImm = 1;
1538let isReMaterializable = 1;
1539let isPseudo = 1;
1540}
1541def A2_tfrpt : HInst<
1542(outs DoubleRegs:$Rdd32),
1543(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1544"if ($Pu4) $Rdd32 = $Rss32",
1545tc_713b66bf, TypeALU32_2op>, PredNewRel {
1546let isPredicated = 1;
1547let BaseOpcode = "A2_tfrp";
1548let isPseudo = 1;
1549}
1550def A2_tfrptnew : HInst<
1551(outs DoubleRegs:$Rdd32),
1552(ins PredRegs:$Pu4, DoubleRegs:$Rss32),
1553"if ($Pu4.new) $Rdd32 = $Rss32",
1554tc_86173609, TypeALU32_2op>, PredNewRel {
1555let isPredicated = 1;
1556let isPredicatedNew = 1;
1557let BaseOpcode = "A2_tfrp";
1558let isPseudo = 1;
1559}
1560def A2_tfrrcr : HInst<
1561(outs CtrRegs:$Cd32),
1562(ins IntRegs:$Rs32),
1563"$Cd32 = $Rs32",
1564tc_49fdfd4b, TypeCR>, Enc_bd811a {
1565let Inst{13-5} = 0b000000000;
1566let Inst{31-21} = 0b01100010001;
1567let hasNewValue = 1;
1568let opNewValue = 0;
1569}
1570def A2_tfrsi : HInst<
1571(outs IntRegs:$Rd32),
1572(ins s32_0Imm:$Ii),
1573"$Rd32 = #$Ii",
1574tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel {
1575let Inst{21-21} = 0b0;
1576let Inst{31-24} = 0b01111000;
1577let hasNewValue = 1;
1578let opNewValue = 0;
1579let BaseOpcode = "A2_tfrsi";
1580let CextOpcode = "A2_tfr";
1581let InputType = "imm";
1582let isAsCheapAsAMove = 1;
1583let isMoveImm = 1;
1584let isPredicable = 1;
1585let isReMaterializable = 1;
1586let isExtendable = 1;
1587let opExtendable = 1;
1588let isExtentSigned = 1;
1589let opExtentBits = 16;
1590let opExtentAlign = 0;
1591}
1592def A2_tfrt : HInst<
1593(outs IntRegs:$Rd32),
1594(ins PredRegs:$Pu4, IntRegs:$Rs32),
1595"if ($Pu4) $Rd32 = $Rs32",
1596tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel {
1597let isPredicated = 1;
1598let hasNewValue = 1;
1599let opNewValue = 0;
1600let BaseOpcode = "A2_tfr";
1601let CextOpcode = "A2_tfr";
1602let InputType = "reg";
1603let isPseudo = 1;
1604let isCodeGenOnly = 1;
1605}
1606def A2_tfrtnew : HInst<
1607(outs IntRegs:$Rd32),
1608(ins PredRegs:$Pu4, IntRegs:$Rs32),
1609"if ($Pu4.new) $Rd32 = $Rs32",
1610tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel {
1611let isPredicated = 1;
1612let hasNewValue = 1;
1613let opNewValue = 0;
1614let isPredicatedNew = 1;
1615let BaseOpcode = "A2_tfr";
1616let CextOpcode = "A2_tfr";
1617let InputType = "reg";
1618let isPseudo = 1;
1619let isCodeGenOnly = 1;
1620}
1621def A2_vabsh : HInst<
1622(outs DoubleRegs:$Rdd32),
1623(ins DoubleRegs:$Rss32),
1624"$Rdd32 = vabsh($Rss32)",
1625tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1626let Inst{13-5} = 0b000000100;
1627let Inst{31-21} = 0b10000000010;
1628let prefersSlot3 = 1;
1629}
1630def A2_vabshsat : HInst<
1631(outs DoubleRegs:$Rdd32),
1632(ins DoubleRegs:$Rss32),
1633"$Rdd32 = vabsh($Rss32):sat",
1634tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1635let Inst{13-5} = 0b000000101;
1636let Inst{31-21} = 0b10000000010;
1637let prefersSlot3 = 1;
1638let Defs = [USR_OVF];
1639}
1640def A2_vabsw : HInst<
1641(outs DoubleRegs:$Rdd32),
1642(ins DoubleRegs:$Rss32),
1643"$Rdd32 = vabsw($Rss32)",
1644tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1645let Inst{13-5} = 0b000000110;
1646let Inst{31-21} = 0b10000000010;
1647let prefersSlot3 = 1;
1648}
1649def A2_vabswsat : HInst<
1650(outs DoubleRegs:$Rdd32),
1651(ins DoubleRegs:$Rss32),
1652"$Rdd32 = vabsw($Rss32):sat",
1653tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1654let Inst{13-5} = 0b000000111;
1655let Inst{31-21} = 0b10000000010;
1656let prefersSlot3 = 1;
1657let Defs = [USR_OVF];
1658}
1659def A2_vaddb_map : HInst<
1660(outs DoubleRegs:$Rdd32),
1661(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1662"$Rdd32 = vaddb($Rss32,$Rtt32)",
1663tc_5da50c4b, TypeMAPPING> {
1664let isPseudo = 1;
1665let isCodeGenOnly = 1;
1666}
1667def A2_vaddh : HInst<
1668(outs DoubleRegs:$Rdd32),
1669(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1670"$Rdd32 = vaddh($Rss32,$Rtt32)",
1671tc_5da50c4b, TypeALU64>, Enc_a56825 {
1672let Inst{7-5} = 0b010;
1673let Inst{13-13} = 0b0;
1674let Inst{31-21} = 0b11010011000;
1675}
1676def A2_vaddhs : HInst<
1677(outs DoubleRegs:$Rdd32),
1678(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1679"$Rdd32 = vaddh($Rss32,$Rtt32):sat",
1680tc_8a825db2, TypeALU64>, Enc_a56825 {
1681let Inst{7-5} = 0b011;
1682let Inst{13-13} = 0b0;
1683let Inst{31-21} = 0b11010011000;
1684let prefersSlot3 = 1;
1685let Defs = [USR_OVF];
1686}
1687def A2_vaddub : HInst<
1688(outs DoubleRegs:$Rdd32),
1689(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1690"$Rdd32 = vaddub($Rss32,$Rtt32)",
1691tc_5da50c4b, TypeALU64>, Enc_a56825 {
1692let Inst{7-5} = 0b000;
1693let Inst{13-13} = 0b0;
1694let Inst{31-21} = 0b11010011000;
1695}
1696def A2_vaddubs : HInst<
1697(outs DoubleRegs:$Rdd32),
1698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1699"$Rdd32 = vaddub($Rss32,$Rtt32):sat",
1700tc_8a825db2, TypeALU64>, Enc_a56825 {
1701let Inst{7-5} = 0b001;
1702let Inst{13-13} = 0b0;
1703let Inst{31-21} = 0b11010011000;
1704let prefersSlot3 = 1;
1705let Defs = [USR_OVF];
1706}
1707def A2_vadduhs : HInst<
1708(outs DoubleRegs:$Rdd32),
1709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1710"$Rdd32 = vadduh($Rss32,$Rtt32):sat",
1711tc_8a825db2, TypeALU64>, Enc_a56825 {
1712let Inst{7-5} = 0b100;
1713let Inst{13-13} = 0b0;
1714let Inst{31-21} = 0b11010011000;
1715let prefersSlot3 = 1;
1716let Defs = [USR_OVF];
1717}
1718def A2_vaddw : HInst<
1719(outs DoubleRegs:$Rdd32),
1720(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1721"$Rdd32 = vaddw($Rss32,$Rtt32)",
1722tc_5da50c4b, TypeALU64>, Enc_a56825 {
1723let Inst{7-5} = 0b101;
1724let Inst{13-13} = 0b0;
1725let Inst{31-21} = 0b11010011000;
1726}
1727def A2_vaddws : HInst<
1728(outs DoubleRegs:$Rdd32),
1729(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1730"$Rdd32 = vaddw($Rss32,$Rtt32):sat",
1731tc_8a825db2, TypeALU64>, Enc_a56825 {
1732let Inst{7-5} = 0b110;
1733let Inst{13-13} = 0b0;
1734let Inst{31-21} = 0b11010011000;
1735let prefersSlot3 = 1;
1736let Defs = [USR_OVF];
1737}
1738def A2_vavgh : HInst<
1739(outs DoubleRegs:$Rdd32),
1740(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1741"$Rdd32 = vavgh($Rss32,$Rtt32)",
1742tc_f098b237, TypeALU64>, Enc_a56825 {
1743let Inst{7-5} = 0b010;
1744let Inst{13-13} = 0b0;
1745let Inst{31-21} = 0b11010011010;
1746let prefersSlot3 = 1;
1747}
1748def A2_vavghcr : HInst<
1749(outs DoubleRegs:$Rdd32),
1750(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1751"$Rdd32 = vavgh($Rss32,$Rtt32):crnd",
1752tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1753let Inst{7-5} = 0b100;
1754let Inst{13-13} = 0b0;
1755let Inst{31-21} = 0b11010011010;
1756let prefersSlot3 = 1;
1757}
1758def A2_vavghr : HInst<
1759(outs DoubleRegs:$Rdd32),
1760(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1761"$Rdd32 = vavgh($Rss32,$Rtt32):rnd",
1762tc_20131976, TypeALU64>, Enc_a56825 {
1763let Inst{7-5} = 0b011;
1764let Inst{13-13} = 0b0;
1765let Inst{31-21} = 0b11010011010;
1766let prefersSlot3 = 1;
1767}
1768def A2_vavgub : HInst<
1769(outs DoubleRegs:$Rdd32),
1770(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1771"$Rdd32 = vavgub($Rss32,$Rtt32)",
1772tc_f098b237, TypeALU64>, Enc_a56825 {
1773let Inst{7-5} = 0b000;
1774let Inst{13-13} = 0b0;
1775let Inst{31-21} = 0b11010011010;
1776let prefersSlot3 = 1;
1777}
1778def A2_vavgubr : HInst<
1779(outs DoubleRegs:$Rdd32),
1780(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1781"$Rdd32 = vavgub($Rss32,$Rtt32):rnd",
1782tc_20131976, TypeALU64>, Enc_a56825 {
1783let Inst{7-5} = 0b001;
1784let Inst{13-13} = 0b0;
1785let Inst{31-21} = 0b11010011010;
1786let prefersSlot3 = 1;
1787}
1788def A2_vavguh : HInst<
1789(outs DoubleRegs:$Rdd32),
1790(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1791"$Rdd32 = vavguh($Rss32,$Rtt32)",
1792tc_f098b237, TypeALU64>, Enc_a56825 {
1793let Inst{7-5} = 0b101;
1794let Inst{13-13} = 0b0;
1795let Inst{31-21} = 0b11010011010;
1796let prefersSlot3 = 1;
1797}
1798def A2_vavguhr : HInst<
1799(outs DoubleRegs:$Rdd32),
1800(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1801"$Rdd32 = vavguh($Rss32,$Rtt32):rnd",
1802tc_20131976, TypeALU64>, Enc_a56825 {
1803let Inst{7-5} = 0b110;
1804let Inst{13-13} = 0b0;
1805let Inst{31-21} = 0b11010011010;
1806let prefersSlot3 = 1;
1807}
1808def A2_vavguw : HInst<
1809(outs DoubleRegs:$Rdd32),
1810(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1811"$Rdd32 = vavguw($Rss32,$Rtt32)",
1812tc_f098b237, TypeALU64>, Enc_a56825 {
1813let Inst{7-5} = 0b011;
1814let Inst{13-13} = 0b0;
1815let Inst{31-21} = 0b11010011011;
1816let prefersSlot3 = 1;
1817}
1818def A2_vavguwr : HInst<
1819(outs DoubleRegs:$Rdd32),
1820(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1821"$Rdd32 = vavguw($Rss32,$Rtt32):rnd",
1822tc_20131976, TypeALU64>, Enc_a56825 {
1823let Inst{7-5} = 0b100;
1824let Inst{13-13} = 0b0;
1825let Inst{31-21} = 0b11010011011;
1826let prefersSlot3 = 1;
1827}
1828def A2_vavgw : HInst<
1829(outs DoubleRegs:$Rdd32),
1830(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1831"$Rdd32 = vavgw($Rss32,$Rtt32)",
1832tc_f098b237, TypeALU64>, Enc_a56825 {
1833let Inst{7-5} = 0b000;
1834let Inst{13-13} = 0b0;
1835let Inst{31-21} = 0b11010011011;
1836let prefersSlot3 = 1;
1837}
1838def A2_vavgwcr : HInst<
1839(outs DoubleRegs:$Rdd32),
1840(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1841"$Rdd32 = vavgw($Rss32,$Rtt32):crnd",
1842tc_0dfac0a7, TypeALU64>, Enc_a56825 {
1843let Inst{7-5} = 0b010;
1844let Inst{13-13} = 0b0;
1845let Inst{31-21} = 0b11010011011;
1846let prefersSlot3 = 1;
1847}
1848def A2_vavgwr : HInst<
1849(outs DoubleRegs:$Rdd32),
1850(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1851"$Rdd32 = vavgw($Rss32,$Rtt32):rnd",
1852tc_20131976, TypeALU64>, Enc_a56825 {
1853let Inst{7-5} = 0b001;
1854let Inst{13-13} = 0b0;
1855let Inst{31-21} = 0b11010011011;
1856let prefersSlot3 = 1;
1857}
1858def A2_vcmpbeq : HInst<
1859(outs PredRegs:$Pd4),
1860(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1861"$Pd4 = vcmpb.eq($Rss32,$Rtt32)",
1862tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1863let Inst{7-2} = 0b110000;
1864let Inst{13-13} = 0b0;
1865let Inst{31-21} = 0b11010010000;
1866}
1867def A2_vcmpbgtu : HInst<
1868(outs PredRegs:$Pd4),
1869(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1870"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)",
1871tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1872let Inst{7-2} = 0b111000;
1873let Inst{13-13} = 0b0;
1874let Inst{31-21} = 0b11010010000;
1875}
1876def A2_vcmpheq : HInst<
1877(outs PredRegs:$Pd4),
1878(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1879"$Pd4 = vcmph.eq($Rss32,$Rtt32)",
1880tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1881let Inst{7-2} = 0b011000;
1882let Inst{13-13} = 0b0;
1883let Inst{31-21} = 0b11010010000;
1884}
1885def A2_vcmphgt : HInst<
1886(outs PredRegs:$Pd4),
1887(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1888"$Pd4 = vcmph.gt($Rss32,$Rtt32)",
1889tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1890let Inst{7-2} = 0b100000;
1891let Inst{13-13} = 0b0;
1892let Inst{31-21} = 0b11010010000;
1893}
1894def A2_vcmphgtu : HInst<
1895(outs PredRegs:$Pd4),
1896(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1897"$Pd4 = vcmph.gtu($Rss32,$Rtt32)",
1898tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1899let Inst{7-2} = 0b101000;
1900let Inst{13-13} = 0b0;
1901let Inst{31-21} = 0b11010010000;
1902}
1903def A2_vcmpweq : HInst<
1904(outs PredRegs:$Pd4),
1905(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1906"$Pd4 = vcmpw.eq($Rss32,$Rtt32)",
1907tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1908let Inst{7-2} = 0b000000;
1909let Inst{13-13} = 0b0;
1910let Inst{31-21} = 0b11010010000;
1911}
1912def A2_vcmpwgt : HInst<
1913(outs PredRegs:$Pd4),
1914(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1915"$Pd4 = vcmpw.gt($Rss32,$Rtt32)",
1916tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1917let Inst{7-2} = 0b001000;
1918let Inst{13-13} = 0b0;
1919let Inst{31-21} = 0b11010010000;
1920}
1921def A2_vcmpwgtu : HInst<
1922(outs PredRegs:$Pd4),
1923(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
1924"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)",
1925tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
1926let Inst{7-2} = 0b010000;
1927let Inst{13-13} = 0b0;
1928let Inst{31-21} = 0b11010010000;
1929}
1930def A2_vconj : HInst<
1931(outs DoubleRegs:$Rdd32),
1932(ins DoubleRegs:$Rss32),
1933"$Rdd32 = vconj($Rss32):sat",
1934tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb {
1935let Inst{13-5} = 0b000000111;
1936let Inst{31-21} = 0b10000000100;
1937let prefersSlot3 = 1;
1938let Defs = [USR_OVF];
1939}
1940def A2_vmaxb : HInst<
1941(outs DoubleRegs:$Rdd32),
1942(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1943"$Rdd32 = vmaxb($Rtt32,$Rss32)",
1944tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1945let Inst{7-5} = 0b110;
1946let Inst{13-13} = 0b0;
1947let Inst{31-21} = 0b11010011110;
1948let prefersSlot3 = 1;
1949}
1950def A2_vmaxh : HInst<
1951(outs DoubleRegs:$Rdd32),
1952(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1953"$Rdd32 = vmaxh($Rtt32,$Rss32)",
1954tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1955let Inst{7-5} = 0b001;
1956let Inst{13-13} = 0b0;
1957let Inst{31-21} = 0b11010011110;
1958let prefersSlot3 = 1;
1959}
1960def A2_vmaxub : HInst<
1961(outs DoubleRegs:$Rdd32),
1962(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1963"$Rdd32 = vmaxub($Rtt32,$Rss32)",
1964tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1965let Inst{7-5} = 0b000;
1966let Inst{13-13} = 0b0;
1967let Inst{31-21} = 0b11010011110;
1968let prefersSlot3 = 1;
1969}
1970def A2_vmaxuh : HInst<
1971(outs DoubleRegs:$Rdd32),
1972(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1973"$Rdd32 = vmaxuh($Rtt32,$Rss32)",
1974tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1975let Inst{7-5} = 0b010;
1976let Inst{13-13} = 0b0;
1977let Inst{31-21} = 0b11010011110;
1978let prefersSlot3 = 1;
1979}
1980def A2_vmaxuw : HInst<
1981(outs DoubleRegs:$Rdd32),
1982(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1983"$Rdd32 = vmaxuw($Rtt32,$Rss32)",
1984tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1985let Inst{7-5} = 0b101;
1986let Inst{13-13} = 0b0;
1987let Inst{31-21} = 0b11010011101;
1988let prefersSlot3 = 1;
1989}
1990def A2_vmaxw : HInst<
1991(outs DoubleRegs:$Rdd32),
1992(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
1993"$Rdd32 = vmaxw($Rtt32,$Rss32)",
1994tc_8a825db2, TypeALU64>, Enc_ea23e4 {
1995let Inst{7-5} = 0b011;
1996let Inst{13-13} = 0b0;
1997let Inst{31-21} = 0b11010011110;
1998let prefersSlot3 = 1;
1999}
2000def A2_vminb : HInst<
2001(outs DoubleRegs:$Rdd32),
2002(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2003"$Rdd32 = vminb($Rtt32,$Rss32)",
2004tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2005let Inst{7-5} = 0b111;
2006let Inst{13-13} = 0b0;
2007let Inst{31-21} = 0b11010011110;
2008let prefersSlot3 = 1;
2009}
2010def A2_vminh : HInst<
2011(outs DoubleRegs:$Rdd32),
2012(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2013"$Rdd32 = vminh($Rtt32,$Rss32)",
2014tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2015let Inst{7-5} = 0b001;
2016let Inst{13-13} = 0b0;
2017let Inst{31-21} = 0b11010011101;
2018let prefersSlot3 = 1;
2019}
2020def A2_vminub : HInst<
2021(outs DoubleRegs:$Rdd32),
2022(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2023"$Rdd32 = vminub($Rtt32,$Rss32)",
2024tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2025let Inst{7-5} = 0b000;
2026let Inst{13-13} = 0b0;
2027let Inst{31-21} = 0b11010011101;
2028let prefersSlot3 = 1;
2029}
2030def A2_vminuh : HInst<
2031(outs DoubleRegs:$Rdd32),
2032(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2033"$Rdd32 = vminuh($Rtt32,$Rss32)",
2034tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2035let Inst{7-5} = 0b010;
2036let Inst{13-13} = 0b0;
2037let Inst{31-21} = 0b11010011101;
2038let prefersSlot3 = 1;
2039}
2040def A2_vminuw : HInst<
2041(outs DoubleRegs:$Rdd32),
2042(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2043"$Rdd32 = vminuw($Rtt32,$Rss32)",
2044tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2045let Inst{7-5} = 0b100;
2046let Inst{13-13} = 0b0;
2047let Inst{31-21} = 0b11010011101;
2048let prefersSlot3 = 1;
2049}
2050def A2_vminw : HInst<
2051(outs DoubleRegs:$Rdd32),
2052(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2053"$Rdd32 = vminw($Rtt32,$Rss32)",
2054tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2055let Inst{7-5} = 0b011;
2056let Inst{13-13} = 0b0;
2057let Inst{31-21} = 0b11010011101;
2058let prefersSlot3 = 1;
2059}
2060def A2_vnavgh : HInst<
2061(outs DoubleRegs:$Rdd32),
2062(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2063"$Rdd32 = vnavgh($Rtt32,$Rss32)",
2064tc_f098b237, TypeALU64>, Enc_ea23e4 {
2065let Inst{7-5} = 0b000;
2066let Inst{13-13} = 0b0;
2067let Inst{31-21} = 0b11010011100;
2068let prefersSlot3 = 1;
2069}
2070def A2_vnavghcr : HInst<
2071(outs DoubleRegs:$Rdd32),
2072(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2073"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat",
2074tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2075let Inst{7-5} = 0b010;
2076let Inst{13-13} = 0b0;
2077let Inst{31-21} = 0b11010011100;
2078let prefersSlot3 = 1;
2079let Defs = [USR_OVF];
2080}
2081def A2_vnavghr : HInst<
2082(outs DoubleRegs:$Rdd32),
2083(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2084"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat",
2085tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2086let Inst{7-5} = 0b001;
2087let Inst{13-13} = 0b0;
2088let Inst{31-21} = 0b11010011100;
2089let prefersSlot3 = 1;
2090let Defs = [USR_OVF];
2091}
2092def A2_vnavgw : HInst<
2093(outs DoubleRegs:$Rdd32),
2094(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2095"$Rdd32 = vnavgw($Rtt32,$Rss32)",
2096tc_f098b237, TypeALU64>, Enc_ea23e4 {
2097let Inst{7-5} = 0b011;
2098let Inst{13-13} = 0b0;
2099let Inst{31-21} = 0b11010011100;
2100let prefersSlot3 = 1;
2101}
2102def A2_vnavgwcr : HInst<
2103(outs DoubleRegs:$Rdd32),
2104(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2105"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat",
2106tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2107let Inst{7-5} = 0b110;
2108let Inst{13-13} = 0b0;
2109let Inst{31-21} = 0b11010011100;
2110let prefersSlot3 = 1;
2111let Defs = [USR_OVF];
2112}
2113def A2_vnavgwr : HInst<
2114(outs DoubleRegs:$Rdd32),
2115(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2116"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat",
2117tc_0dfac0a7, TypeALU64>, Enc_ea23e4 {
2118let Inst{7-5} = 0b100;
2119let Inst{13-13} = 0b0;
2120let Inst{31-21} = 0b11010011100;
2121let prefersSlot3 = 1;
2122let Defs = [USR_OVF];
2123}
2124def A2_vraddub : HInst<
2125(outs DoubleRegs:$Rdd32),
2126(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2127"$Rdd32 = vraddub($Rss32,$Rtt32)",
2128tc_c21d7447, TypeM>, Enc_a56825 {
2129let Inst{7-5} = 0b001;
2130let Inst{13-13} = 0b0;
2131let Inst{31-21} = 0b11101000010;
2132let prefersSlot3 = 1;
2133}
2134def A2_vraddub_acc : HInst<
2135(outs DoubleRegs:$Rxx32),
2136(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2137"$Rxx32 += vraddub($Rss32,$Rtt32)",
2138tc_7f8ae742, TypeM>, Enc_88c16c {
2139let Inst{7-5} = 0b001;
2140let Inst{13-13} = 0b0;
2141let Inst{31-21} = 0b11101010010;
2142let prefersSlot3 = 1;
2143let Constraints = "$Rxx32 = $Rxx32in";
2144}
2145def A2_vrsadub : HInst<
2146(outs DoubleRegs:$Rdd32),
2147(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2148"$Rdd32 = vrsadub($Rss32,$Rtt32)",
2149tc_c21d7447, TypeM>, Enc_a56825 {
2150let Inst{7-5} = 0b010;
2151let Inst{13-13} = 0b0;
2152let Inst{31-21} = 0b11101000010;
2153let prefersSlot3 = 1;
2154}
2155def A2_vrsadub_acc : HInst<
2156(outs DoubleRegs:$Rxx32),
2157(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2158"$Rxx32 += vrsadub($Rss32,$Rtt32)",
2159tc_7f8ae742, TypeM>, Enc_88c16c {
2160let Inst{7-5} = 0b010;
2161let Inst{13-13} = 0b0;
2162let Inst{31-21} = 0b11101010010;
2163let prefersSlot3 = 1;
2164let Constraints = "$Rxx32 = $Rxx32in";
2165}
2166def A2_vsubb_map : HInst<
2167(outs DoubleRegs:$Rdd32),
2168(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2169"$Rdd32 = vsubb($Rss32,$Rtt32)",
2170tc_5da50c4b, TypeMAPPING> {
2171let isPseudo = 1;
2172let isCodeGenOnly = 1;
2173}
2174def A2_vsubh : HInst<
2175(outs DoubleRegs:$Rdd32),
2176(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2177"$Rdd32 = vsubh($Rtt32,$Rss32)",
2178tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2179let Inst{7-5} = 0b010;
2180let Inst{13-13} = 0b0;
2181let Inst{31-21} = 0b11010011001;
2182}
2183def A2_vsubhs : HInst<
2184(outs DoubleRegs:$Rdd32),
2185(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2186"$Rdd32 = vsubh($Rtt32,$Rss32):sat",
2187tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2188let Inst{7-5} = 0b011;
2189let Inst{13-13} = 0b0;
2190let Inst{31-21} = 0b11010011001;
2191let prefersSlot3 = 1;
2192let Defs = [USR_OVF];
2193}
2194def A2_vsubub : HInst<
2195(outs DoubleRegs:$Rdd32),
2196(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2197"$Rdd32 = vsubub($Rtt32,$Rss32)",
2198tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2199let Inst{7-5} = 0b000;
2200let Inst{13-13} = 0b0;
2201let Inst{31-21} = 0b11010011001;
2202}
2203def A2_vsububs : HInst<
2204(outs DoubleRegs:$Rdd32),
2205(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2206"$Rdd32 = vsubub($Rtt32,$Rss32):sat",
2207tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2208let Inst{7-5} = 0b001;
2209let Inst{13-13} = 0b0;
2210let Inst{31-21} = 0b11010011001;
2211let prefersSlot3 = 1;
2212let Defs = [USR_OVF];
2213}
2214def A2_vsubuhs : HInst<
2215(outs DoubleRegs:$Rdd32),
2216(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2217"$Rdd32 = vsubuh($Rtt32,$Rss32):sat",
2218tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2219let Inst{7-5} = 0b100;
2220let Inst{13-13} = 0b0;
2221let Inst{31-21} = 0b11010011001;
2222let prefersSlot3 = 1;
2223let Defs = [USR_OVF];
2224}
2225def A2_vsubw : HInst<
2226(outs DoubleRegs:$Rdd32),
2227(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2228"$Rdd32 = vsubw($Rtt32,$Rss32)",
2229tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2230let Inst{7-5} = 0b101;
2231let Inst{13-13} = 0b0;
2232let Inst{31-21} = 0b11010011001;
2233}
2234def A2_vsubws : HInst<
2235(outs DoubleRegs:$Rdd32),
2236(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2237"$Rdd32 = vsubw($Rtt32,$Rss32):sat",
2238tc_8a825db2, TypeALU64>, Enc_ea23e4 {
2239let Inst{7-5} = 0b110;
2240let Inst{13-13} = 0b0;
2241let Inst{31-21} = 0b11010011001;
2242let prefersSlot3 = 1;
2243let Defs = [USR_OVF];
2244}
2245def A2_xor : HInst<
2246(outs IntRegs:$Rd32),
2247(ins IntRegs:$Rs32, IntRegs:$Rt32),
2248"$Rd32 = xor($Rs32,$Rt32)",
2249tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel {
2250let Inst{7-5} = 0b000;
2251let Inst{13-13} = 0b0;
2252let Inst{31-21} = 0b11110001011;
2253let hasNewValue = 1;
2254let opNewValue = 0;
2255let BaseOpcode = "A2_xor";
2256let InputType = "reg";
2257let isCommutable = 1;
2258let isPredicable = 1;
2259}
2260def A2_xorp : HInst<
2261(outs DoubleRegs:$Rdd32),
2262(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2263"$Rdd32 = xor($Rss32,$Rtt32)",
2264tc_5da50c4b, TypeALU64>, Enc_a56825 {
2265let Inst{7-5} = 0b100;
2266let Inst{13-13} = 0b0;
2267let Inst{31-21} = 0b11010011111;
2268let isCommutable = 1;
2269}
2270def A2_zxtb : HInst<
2271(outs IntRegs:$Rd32),
2272(ins IntRegs:$Rs32),
2273"$Rd32 = zxtb($Rs32)",
2274tc_713b66bf, TypeALU32_2op>, PredNewRel {
2275let hasNewValue = 1;
2276let opNewValue = 0;
2277let BaseOpcode = "A2_zxtb";
2278let isPredicable = 1;
2279let isPseudo = 1;
2280let isCodeGenOnly = 1;
2281}
2282def A2_zxth : HInst<
2283(outs IntRegs:$Rd32),
2284(ins IntRegs:$Rs32),
2285"$Rd32 = zxth($Rs32)",
2286tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel {
2287let Inst{13-5} = 0b000000000;
2288let Inst{31-21} = 0b01110000110;
2289let hasNewValue = 1;
2290let opNewValue = 0;
2291let BaseOpcode = "A2_zxth";
2292let isPredicable = 1;
2293}
2294def A4_addp_c : HInst<
2295(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
2296(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
2297"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry",
2298tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
2299let Inst{7-7} = 0b0;
2300let Inst{13-13} = 0b0;
2301let Inst{31-21} = 0b11000010110;
2302let isPredicateLate = 1;
2303let Constraints = "$Px4 = $Px4in";
2304}
2305def A4_andn : HInst<
2306(outs IntRegs:$Rd32),
2307(ins IntRegs:$Rt32, IntRegs:$Rs32),
2308"$Rd32 = and($Rt32,~$Rs32)",
2309tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2310let Inst{7-5} = 0b000;
2311let Inst{13-13} = 0b0;
2312let Inst{31-21} = 0b11110001100;
2313let hasNewValue = 1;
2314let opNewValue = 0;
2315let InputType = "reg";
2316}
2317def A4_andnp : HInst<
2318(outs DoubleRegs:$Rdd32),
2319(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2320"$Rdd32 = and($Rtt32,~$Rss32)",
2321tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2322let Inst{7-5} = 0b001;
2323let Inst{13-13} = 0b0;
2324let Inst{31-21} = 0b11010011111;
2325}
2326def A4_bitsplit : HInst<
2327(outs DoubleRegs:$Rdd32),
2328(ins IntRegs:$Rs32, IntRegs:$Rt32),
2329"$Rdd32 = bitsplit($Rs32,$Rt32)",
2330tc_f34c1c21, TypeALU64>, Enc_be32a5 {
2331let Inst{7-5} = 0b000;
2332let Inst{13-13} = 0b0;
2333let Inst{31-21} = 0b11010100001;
2334let prefersSlot3 = 1;
2335}
2336def A4_bitspliti : HInst<
2337(outs DoubleRegs:$Rdd32),
2338(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2339"$Rdd32 = bitsplit($Rs32,#$Ii)",
2340tc_f34c1c21, TypeS_2op>, Enc_311abd {
2341let Inst{7-5} = 0b100;
2342let Inst{13-13} = 0b0;
2343let Inst{31-21} = 0b10001000110;
2344let prefersSlot3 = 1;
2345}
2346def A4_boundscheck : HInst<
2347(outs PredRegs:$Pd4),
2348(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
2349"$Pd4 = boundscheck($Rs32,$Rtt32)",
2350tc_4a55d03c, TypeALU64> {
2351let isPseudo = 1;
2352}
2353def A4_boundscheck_hi : HInst<
2354(outs PredRegs:$Pd4),
2355(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2356"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi",
2357tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2358let Inst{7-2} = 0b101000;
2359let Inst{13-13} = 0b1;
2360let Inst{31-21} = 0b11010010000;
2361}
2362def A4_boundscheck_lo : HInst<
2363(outs PredRegs:$Pd4),
2364(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
2365"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo",
2366tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
2367let Inst{7-2} = 0b100000;
2368let Inst{13-13} = 0b1;
2369let Inst{31-21} = 0b11010010000;
2370}
2371def A4_cmpbeq : HInst<
2372(outs PredRegs:$Pd4),
2373(ins IntRegs:$Rs32, IntRegs:$Rt32),
2374"$Pd4 = cmpb.eq($Rs32,$Rt32)",
2375tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2376let Inst{7-2} = 0b110000;
2377let Inst{13-13} = 0b0;
2378let Inst{31-21} = 0b11000111110;
2379let CextOpcode = "A4_cmpbeq";
2380let InputType = "reg";
2381let isCommutable = 1;
2382let isCompare = 1;
2383}
2384def A4_cmpbeqi : HInst<
2385(outs PredRegs:$Pd4),
2386(ins IntRegs:$Rs32, u8_0Imm:$Ii),
2387"$Pd4 = cmpb.eq($Rs32,#$Ii)",
2388tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2389let Inst{4-2} = 0b000;
2390let Inst{13-13} = 0b0;
2391let Inst{31-21} = 0b11011101000;
2392let CextOpcode = "A4_cmpbeq";
2393let InputType = "imm";
2394let isCommutable = 1;
2395let isCompare = 1;
2396}
2397def A4_cmpbgt : HInst<
2398(outs PredRegs:$Pd4),
2399(ins IntRegs:$Rs32, IntRegs:$Rt32),
2400"$Pd4 = cmpb.gt($Rs32,$Rt32)",
2401tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2402let Inst{7-2} = 0b010000;
2403let Inst{13-13} = 0b0;
2404let Inst{31-21} = 0b11000111110;
2405let CextOpcode = "A4_cmpbgt";
2406let InputType = "reg";
2407let isCompare = 1;
2408}
2409def A4_cmpbgti : HInst<
2410(outs PredRegs:$Pd4),
2411(ins IntRegs:$Rs32, s8_0Imm:$Ii),
2412"$Pd4 = cmpb.gt($Rs32,#$Ii)",
2413tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2414let Inst{4-2} = 0b000;
2415let Inst{13-13} = 0b0;
2416let Inst{31-21} = 0b11011101001;
2417let CextOpcode = "A4_cmpbgt";
2418let InputType = "imm";
2419let isCompare = 1;
2420}
2421def A4_cmpbgtu : HInst<
2422(outs PredRegs:$Pd4),
2423(ins IntRegs:$Rs32, IntRegs:$Rt32),
2424"$Pd4 = cmpb.gtu($Rs32,$Rt32)",
2425tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2426let Inst{7-2} = 0b111000;
2427let Inst{13-13} = 0b0;
2428let Inst{31-21} = 0b11000111110;
2429let CextOpcode = "A4_cmpbgtu";
2430let InputType = "reg";
2431let isCompare = 1;
2432}
2433def A4_cmpbgtui : HInst<
2434(outs PredRegs:$Pd4),
2435(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2436"$Pd4 = cmpb.gtu($Rs32,#$Ii)",
2437tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2438let Inst{4-2} = 0b000;
2439let Inst{13-12} = 0b00;
2440let Inst{31-21} = 0b11011101010;
2441let CextOpcode = "A4_cmpbgtu";
2442let InputType = "imm";
2443let isCompare = 1;
2444let isExtendable = 1;
2445let opExtendable = 2;
2446let isExtentSigned = 0;
2447let opExtentBits = 7;
2448let opExtentAlign = 0;
2449}
2450def A4_cmpheq : HInst<
2451(outs PredRegs:$Pd4),
2452(ins IntRegs:$Rs32, IntRegs:$Rt32),
2453"$Pd4 = cmph.eq($Rs32,$Rt32)",
2454tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2455let Inst{7-2} = 0b011000;
2456let Inst{13-13} = 0b0;
2457let Inst{31-21} = 0b11000111110;
2458let CextOpcode = "A4_cmpheq";
2459let InputType = "reg";
2460let isCommutable = 1;
2461let isCompare = 1;
2462}
2463def A4_cmpheqi : HInst<
2464(outs PredRegs:$Pd4),
2465(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2466"$Pd4 = cmph.eq($Rs32,#$Ii)",
2467tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2468let Inst{4-2} = 0b010;
2469let Inst{13-13} = 0b0;
2470let Inst{31-21} = 0b11011101000;
2471let CextOpcode = "A4_cmpheq";
2472let InputType = "imm";
2473let isCommutable = 1;
2474let isCompare = 1;
2475let isExtendable = 1;
2476let opExtendable = 2;
2477let isExtentSigned = 1;
2478let opExtentBits = 8;
2479let opExtentAlign = 0;
2480}
2481def A4_cmphgt : HInst<
2482(outs PredRegs:$Pd4),
2483(ins IntRegs:$Rs32, IntRegs:$Rt32),
2484"$Pd4 = cmph.gt($Rs32,$Rt32)",
2485tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2486let Inst{7-2} = 0b100000;
2487let Inst{13-13} = 0b0;
2488let Inst{31-21} = 0b11000111110;
2489let CextOpcode = "A4_cmphgt";
2490let InputType = "reg";
2491let isCompare = 1;
2492}
2493def A4_cmphgti : HInst<
2494(outs PredRegs:$Pd4),
2495(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2496"$Pd4 = cmph.gt($Rs32,#$Ii)",
2497tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel {
2498let Inst{4-2} = 0b010;
2499let Inst{13-13} = 0b0;
2500let Inst{31-21} = 0b11011101001;
2501let CextOpcode = "A4_cmphgt";
2502let InputType = "imm";
2503let isCompare = 1;
2504let isExtendable = 1;
2505let opExtendable = 2;
2506let isExtentSigned = 1;
2507let opExtentBits = 8;
2508let opExtentAlign = 0;
2509}
2510def A4_cmphgtu : HInst<
2511(outs PredRegs:$Pd4),
2512(ins IntRegs:$Rs32, IntRegs:$Rt32),
2513"$Pd4 = cmph.gtu($Rs32,$Rt32)",
2514tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel {
2515let Inst{7-2} = 0b101000;
2516let Inst{13-13} = 0b0;
2517let Inst{31-21} = 0b11000111110;
2518let CextOpcode = "A4_cmphgtu";
2519let InputType = "reg";
2520let isCompare = 1;
2521}
2522def A4_cmphgtui : HInst<
2523(outs PredRegs:$Pd4),
2524(ins IntRegs:$Rs32, u32_0Imm:$Ii),
2525"$Pd4 = cmph.gtu($Rs32,#$Ii)",
2526tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel {
2527let Inst{4-2} = 0b010;
2528let Inst{13-12} = 0b00;
2529let Inst{31-21} = 0b11011101010;
2530let CextOpcode = "A4_cmphgtu";
2531let InputType = "imm";
2532let isCompare = 1;
2533let isExtendable = 1;
2534let opExtendable = 2;
2535let isExtentSigned = 0;
2536let opExtentBits = 7;
2537let opExtentAlign = 0;
2538}
2539def A4_combineii : HInst<
2540(outs DoubleRegs:$Rdd32),
2541(ins s8_0Imm:$Ii, u32_0Imm:$II),
2542"$Rdd32 = combine(#$Ii,#$II)",
2543tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 {
2544let Inst{31-21} = 0b01111100100;
2545let isExtendable = 1;
2546let opExtendable = 2;
2547let isExtentSigned = 0;
2548let opExtentBits = 6;
2549let opExtentAlign = 0;
2550}
2551def A4_combineir : HInst<
2552(outs DoubleRegs:$Rdd32),
2553(ins s32_0Imm:$Ii, IntRegs:$Rs32),
2554"$Rdd32 = combine(#$Ii,$Rs32)",
2555tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2556let Inst{13-13} = 0b1;
2557let Inst{31-21} = 0b01110011001;
2558let isExtendable = 1;
2559let opExtendable = 1;
2560let isExtentSigned = 1;
2561let opExtentBits = 8;
2562let opExtentAlign = 0;
2563}
2564def A4_combineri : HInst<
2565(outs DoubleRegs:$Rdd32),
2566(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2567"$Rdd32 = combine($Rs32,#$Ii)",
2568tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 {
2569let Inst{13-13} = 0b1;
2570let Inst{31-21} = 0b01110011000;
2571let isExtendable = 1;
2572let opExtendable = 2;
2573let isExtentSigned = 1;
2574let opExtentBits = 8;
2575let opExtentAlign = 0;
2576}
2577def A4_cround_ri : HInst<
2578(outs IntRegs:$Rd32),
2579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
2580"$Rd32 = cround($Rs32,#$Ii)",
2581tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
2582let Inst{7-5} = 0b000;
2583let Inst{13-13} = 0b0;
2584let Inst{31-21} = 0b10001100111;
2585let hasNewValue = 1;
2586let opNewValue = 0;
2587let prefersSlot3 = 1;
2588}
2589def A4_cround_rr : HInst<
2590(outs IntRegs:$Rd32),
2591(ins IntRegs:$Rs32, IntRegs:$Rt32),
2592"$Rd32 = cround($Rs32,$Rt32)",
2593tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
2594let Inst{7-5} = 0b000;
2595let Inst{13-13} = 0b0;
2596let Inst{31-21} = 0b11000110110;
2597let hasNewValue = 1;
2598let opNewValue = 0;
2599let prefersSlot3 = 1;
2600}
2601def A4_ext : HInst<
2602(outs),
2603(ins u26_6Imm:$Ii),
2604"immext(#$Ii)",
2605tc_112d30d6, TypeEXTENDER>, Enc_2b518f {
2606let Inst{31-28} = 0b0000;
2607}
2608def A4_modwrapu : HInst<
2609(outs IntRegs:$Rd32),
2610(ins IntRegs:$Rs32, IntRegs:$Rt32),
2611"$Rd32 = modwrap($Rs32,$Rt32)",
2612tc_8a825db2, TypeALU64>, Enc_5ab2be {
2613let Inst{7-5} = 0b111;
2614let Inst{13-13} = 0b0;
2615let Inst{31-21} = 0b11010011111;
2616let hasNewValue = 1;
2617let opNewValue = 0;
2618let prefersSlot3 = 1;
2619}
2620def A4_orn : HInst<
2621(outs IntRegs:$Rd32),
2622(ins IntRegs:$Rt32, IntRegs:$Rs32),
2623"$Rd32 = or($Rt32,~$Rs32)",
2624tc_713b66bf, TypeALU32_3op>, Enc_bd6011 {
2625let Inst{7-5} = 0b000;
2626let Inst{13-13} = 0b0;
2627let Inst{31-21} = 0b11110001101;
2628let hasNewValue = 1;
2629let opNewValue = 0;
2630let InputType = "reg";
2631}
2632def A4_ornp : HInst<
2633(outs DoubleRegs:$Rdd32),
2634(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
2635"$Rdd32 = or($Rtt32,~$Rss32)",
2636tc_5da50c4b, TypeALU64>, Enc_ea23e4 {
2637let Inst{7-5} = 0b011;
2638let Inst{13-13} = 0b0;
2639let Inst{31-21} = 0b11010011111;
2640}
2641def A4_paslhf : HInst<
2642(outs IntRegs:$Rd32),
2643(ins PredRegs:$Pu4, IntRegs:$Rs32),
2644"if (!$Pu4) $Rd32 = aslh($Rs32)",
2645tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2646let Inst{7-5} = 0b000;
2647let Inst{13-10} = 0b1010;
2648let Inst{31-21} = 0b01110000000;
2649let isPredicated = 1;
2650let isPredicatedFalse = 1;
2651let hasNewValue = 1;
2652let opNewValue = 0;
2653let BaseOpcode = "A2_aslh";
2654}
2655def A4_paslhfnew : HInst<
2656(outs IntRegs:$Rd32),
2657(ins PredRegs:$Pu4, IntRegs:$Rs32),
2658"if (!$Pu4.new) $Rd32 = aslh($Rs32)",
2659tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2660let Inst{7-5} = 0b000;
2661let Inst{13-10} = 0b1011;
2662let Inst{31-21} = 0b01110000000;
2663let isPredicated = 1;
2664let isPredicatedFalse = 1;
2665let hasNewValue = 1;
2666let opNewValue = 0;
2667let isPredicatedNew = 1;
2668let BaseOpcode = "A2_aslh";
2669}
2670def A4_paslht : HInst<
2671(outs IntRegs:$Rd32),
2672(ins PredRegs:$Pu4, IntRegs:$Rs32),
2673"if ($Pu4) $Rd32 = aslh($Rs32)",
2674tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2675let Inst{7-5} = 0b000;
2676let Inst{13-10} = 0b1000;
2677let Inst{31-21} = 0b01110000000;
2678let isPredicated = 1;
2679let hasNewValue = 1;
2680let opNewValue = 0;
2681let BaseOpcode = "A2_aslh";
2682}
2683def A4_paslhtnew : HInst<
2684(outs IntRegs:$Rd32),
2685(ins PredRegs:$Pu4, IntRegs:$Rs32),
2686"if ($Pu4.new) $Rd32 = aslh($Rs32)",
2687tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2688let Inst{7-5} = 0b000;
2689let Inst{13-10} = 0b1001;
2690let Inst{31-21} = 0b01110000000;
2691let isPredicated = 1;
2692let hasNewValue = 1;
2693let opNewValue = 0;
2694let isPredicatedNew = 1;
2695let BaseOpcode = "A2_aslh";
2696}
2697def A4_pasrhf : HInst<
2698(outs IntRegs:$Rd32),
2699(ins PredRegs:$Pu4, IntRegs:$Rs32),
2700"if (!$Pu4) $Rd32 = asrh($Rs32)",
2701tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2702let Inst{7-5} = 0b000;
2703let Inst{13-10} = 0b1010;
2704let Inst{31-21} = 0b01110000001;
2705let isPredicated = 1;
2706let isPredicatedFalse = 1;
2707let hasNewValue = 1;
2708let opNewValue = 0;
2709let BaseOpcode = "A2_asrh";
2710}
2711def A4_pasrhfnew : HInst<
2712(outs IntRegs:$Rd32),
2713(ins PredRegs:$Pu4, IntRegs:$Rs32),
2714"if (!$Pu4.new) $Rd32 = asrh($Rs32)",
2715tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2716let Inst{7-5} = 0b000;
2717let Inst{13-10} = 0b1011;
2718let Inst{31-21} = 0b01110000001;
2719let isPredicated = 1;
2720let isPredicatedFalse = 1;
2721let hasNewValue = 1;
2722let opNewValue = 0;
2723let isPredicatedNew = 1;
2724let BaseOpcode = "A2_asrh";
2725}
2726def A4_pasrht : HInst<
2727(outs IntRegs:$Rd32),
2728(ins PredRegs:$Pu4, IntRegs:$Rs32),
2729"if ($Pu4) $Rd32 = asrh($Rs32)",
2730tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2731let Inst{7-5} = 0b000;
2732let Inst{13-10} = 0b1000;
2733let Inst{31-21} = 0b01110000001;
2734let isPredicated = 1;
2735let hasNewValue = 1;
2736let opNewValue = 0;
2737let BaseOpcode = "A2_asrh";
2738}
2739def A4_pasrhtnew : HInst<
2740(outs IntRegs:$Rd32),
2741(ins PredRegs:$Pu4, IntRegs:$Rs32),
2742"if ($Pu4.new) $Rd32 = asrh($Rs32)",
2743tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2744let Inst{7-5} = 0b000;
2745let Inst{13-10} = 0b1001;
2746let Inst{31-21} = 0b01110000001;
2747let isPredicated = 1;
2748let hasNewValue = 1;
2749let opNewValue = 0;
2750let isPredicatedNew = 1;
2751let BaseOpcode = "A2_asrh";
2752}
2753def A4_psxtbf : HInst<
2754(outs IntRegs:$Rd32),
2755(ins PredRegs:$Pu4, IntRegs:$Rs32),
2756"if (!$Pu4) $Rd32 = sxtb($Rs32)",
2757tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2758let Inst{7-5} = 0b000;
2759let Inst{13-10} = 0b1010;
2760let Inst{31-21} = 0b01110000101;
2761let isPredicated = 1;
2762let isPredicatedFalse = 1;
2763let hasNewValue = 1;
2764let opNewValue = 0;
2765let BaseOpcode = "A2_sxtb";
2766}
2767def A4_psxtbfnew : HInst<
2768(outs IntRegs:$Rd32),
2769(ins PredRegs:$Pu4, IntRegs:$Rs32),
2770"if (!$Pu4.new) $Rd32 = sxtb($Rs32)",
2771tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2772let Inst{7-5} = 0b000;
2773let Inst{13-10} = 0b1011;
2774let Inst{31-21} = 0b01110000101;
2775let isPredicated = 1;
2776let isPredicatedFalse = 1;
2777let hasNewValue = 1;
2778let opNewValue = 0;
2779let isPredicatedNew = 1;
2780let BaseOpcode = "A2_sxtb";
2781}
2782def A4_psxtbt : HInst<
2783(outs IntRegs:$Rd32),
2784(ins PredRegs:$Pu4, IntRegs:$Rs32),
2785"if ($Pu4) $Rd32 = sxtb($Rs32)",
2786tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2787let Inst{7-5} = 0b000;
2788let Inst{13-10} = 0b1000;
2789let Inst{31-21} = 0b01110000101;
2790let isPredicated = 1;
2791let hasNewValue = 1;
2792let opNewValue = 0;
2793let BaseOpcode = "A2_sxtb";
2794}
2795def A4_psxtbtnew : HInst<
2796(outs IntRegs:$Rd32),
2797(ins PredRegs:$Pu4, IntRegs:$Rs32),
2798"if ($Pu4.new) $Rd32 = sxtb($Rs32)",
2799tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2800let Inst{7-5} = 0b000;
2801let Inst{13-10} = 0b1001;
2802let Inst{31-21} = 0b01110000101;
2803let isPredicated = 1;
2804let hasNewValue = 1;
2805let opNewValue = 0;
2806let isPredicatedNew = 1;
2807let BaseOpcode = "A2_sxtb";
2808}
2809def A4_psxthf : HInst<
2810(outs IntRegs:$Rd32),
2811(ins PredRegs:$Pu4, IntRegs:$Rs32),
2812"if (!$Pu4) $Rd32 = sxth($Rs32)",
2813tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2814let Inst{7-5} = 0b000;
2815let Inst{13-10} = 0b1010;
2816let Inst{31-21} = 0b01110000111;
2817let isPredicated = 1;
2818let isPredicatedFalse = 1;
2819let hasNewValue = 1;
2820let opNewValue = 0;
2821let BaseOpcode = "A2_sxth";
2822}
2823def A4_psxthfnew : HInst<
2824(outs IntRegs:$Rd32),
2825(ins PredRegs:$Pu4, IntRegs:$Rs32),
2826"if (!$Pu4.new) $Rd32 = sxth($Rs32)",
2827tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2828let Inst{7-5} = 0b000;
2829let Inst{13-10} = 0b1011;
2830let Inst{31-21} = 0b01110000111;
2831let isPredicated = 1;
2832let isPredicatedFalse = 1;
2833let hasNewValue = 1;
2834let opNewValue = 0;
2835let isPredicatedNew = 1;
2836let BaseOpcode = "A2_sxth";
2837}
2838def A4_psxtht : HInst<
2839(outs IntRegs:$Rd32),
2840(ins PredRegs:$Pu4, IntRegs:$Rs32),
2841"if ($Pu4) $Rd32 = sxth($Rs32)",
2842tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2843let Inst{7-5} = 0b000;
2844let Inst{13-10} = 0b1000;
2845let Inst{31-21} = 0b01110000111;
2846let isPredicated = 1;
2847let hasNewValue = 1;
2848let opNewValue = 0;
2849let BaseOpcode = "A2_sxth";
2850}
2851def A4_psxthtnew : HInst<
2852(outs IntRegs:$Rd32),
2853(ins PredRegs:$Pu4, IntRegs:$Rs32),
2854"if ($Pu4.new) $Rd32 = sxth($Rs32)",
2855tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2856let Inst{7-5} = 0b000;
2857let Inst{13-10} = 0b1001;
2858let Inst{31-21} = 0b01110000111;
2859let isPredicated = 1;
2860let hasNewValue = 1;
2861let opNewValue = 0;
2862let isPredicatedNew = 1;
2863let BaseOpcode = "A2_sxth";
2864}
2865def A4_pzxtbf : HInst<
2866(outs IntRegs:$Rd32),
2867(ins PredRegs:$Pu4, IntRegs:$Rs32),
2868"if (!$Pu4) $Rd32 = zxtb($Rs32)",
2869tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2870let Inst{7-5} = 0b000;
2871let Inst{13-10} = 0b1010;
2872let Inst{31-21} = 0b01110000100;
2873let isPredicated = 1;
2874let isPredicatedFalse = 1;
2875let hasNewValue = 1;
2876let opNewValue = 0;
2877let BaseOpcode = "A2_zxtb";
2878}
2879def A4_pzxtbfnew : HInst<
2880(outs IntRegs:$Rd32),
2881(ins PredRegs:$Pu4, IntRegs:$Rs32),
2882"if (!$Pu4.new) $Rd32 = zxtb($Rs32)",
2883tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2884let Inst{7-5} = 0b000;
2885let Inst{13-10} = 0b1011;
2886let Inst{31-21} = 0b01110000100;
2887let isPredicated = 1;
2888let isPredicatedFalse = 1;
2889let hasNewValue = 1;
2890let opNewValue = 0;
2891let isPredicatedNew = 1;
2892let BaseOpcode = "A2_zxtb";
2893}
2894def A4_pzxtbt : HInst<
2895(outs IntRegs:$Rd32),
2896(ins PredRegs:$Pu4, IntRegs:$Rs32),
2897"if ($Pu4) $Rd32 = zxtb($Rs32)",
2898tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2899let Inst{7-5} = 0b000;
2900let Inst{13-10} = 0b1000;
2901let Inst{31-21} = 0b01110000100;
2902let isPredicated = 1;
2903let hasNewValue = 1;
2904let opNewValue = 0;
2905let BaseOpcode = "A2_zxtb";
2906}
2907def A4_pzxtbtnew : HInst<
2908(outs IntRegs:$Rd32),
2909(ins PredRegs:$Pu4, IntRegs:$Rs32),
2910"if ($Pu4.new) $Rd32 = zxtb($Rs32)",
2911tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2912let Inst{7-5} = 0b000;
2913let Inst{13-10} = 0b1001;
2914let Inst{31-21} = 0b01110000100;
2915let isPredicated = 1;
2916let hasNewValue = 1;
2917let opNewValue = 0;
2918let isPredicatedNew = 1;
2919let BaseOpcode = "A2_zxtb";
2920}
2921def A4_pzxthf : HInst<
2922(outs IntRegs:$Rd32),
2923(ins PredRegs:$Pu4, IntRegs:$Rs32),
2924"if (!$Pu4) $Rd32 = zxth($Rs32)",
2925tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2926let Inst{7-5} = 0b000;
2927let Inst{13-10} = 0b1010;
2928let Inst{31-21} = 0b01110000110;
2929let isPredicated = 1;
2930let isPredicatedFalse = 1;
2931let hasNewValue = 1;
2932let opNewValue = 0;
2933let BaseOpcode = "A2_zxth";
2934}
2935def A4_pzxthfnew : HInst<
2936(outs IntRegs:$Rd32),
2937(ins PredRegs:$Pu4, IntRegs:$Rs32),
2938"if (!$Pu4.new) $Rd32 = zxth($Rs32)",
2939tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2940let Inst{7-5} = 0b000;
2941let Inst{13-10} = 0b1011;
2942let Inst{31-21} = 0b01110000110;
2943let isPredicated = 1;
2944let isPredicatedFalse = 1;
2945let hasNewValue = 1;
2946let opNewValue = 0;
2947let isPredicatedNew = 1;
2948let BaseOpcode = "A2_zxth";
2949}
2950def A4_pzxtht : HInst<
2951(outs IntRegs:$Rd32),
2952(ins PredRegs:$Pu4, IntRegs:$Rs32),
2953"if ($Pu4) $Rd32 = zxth($Rs32)",
2954tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2955let Inst{7-5} = 0b000;
2956let Inst{13-10} = 0b1000;
2957let Inst{31-21} = 0b01110000110;
2958let isPredicated = 1;
2959let hasNewValue = 1;
2960let opNewValue = 0;
2961let BaseOpcode = "A2_zxth";
2962}
2963def A4_pzxthtnew : HInst<
2964(outs IntRegs:$Rd32),
2965(ins PredRegs:$Pu4, IntRegs:$Rs32),
2966"if ($Pu4.new) $Rd32 = zxth($Rs32)",
2967tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel {
2968let Inst{7-5} = 0b000;
2969let Inst{13-10} = 0b1001;
2970let Inst{31-21} = 0b01110000110;
2971let isPredicated = 1;
2972let hasNewValue = 1;
2973let opNewValue = 0;
2974let isPredicatedNew = 1;
2975let BaseOpcode = "A2_zxth";
2976}
2977def A4_rcmpeq : HInst<
2978(outs IntRegs:$Rd32),
2979(ins IntRegs:$Rs32, IntRegs:$Rt32),
2980"$Rd32 = cmp.eq($Rs32,$Rt32)",
2981tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
2982let Inst{7-5} = 0b000;
2983let Inst{13-13} = 0b0;
2984let Inst{31-21} = 0b11110011010;
2985let hasNewValue = 1;
2986let opNewValue = 0;
2987let CextOpcode = "A4_rcmpeq";
2988let InputType = "reg";
2989let isCommutable = 1;
2990}
2991def A4_rcmpeqi : HInst<
2992(outs IntRegs:$Rd32),
2993(ins IntRegs:$Rs32, s32_0Imm:$Ii),
2994"$Rd32 = cmp.eq($Rs32,#$Ii)",
2995tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
2996let Inst{13-13} = 0b1;
2997let Inst{31-21} = 0b01110011010;
2998let hasNewValue = 1;
2999let opNewValue = 0;
3000let CextOpcode = "A4_rcmpeqi";
3001let InputType = "imm";
3002let isExtendable = 1;
3003let opExtendable = 2;
3004let isExtentSigned = 1;
3005let opExtentBits = 8;
3006let opExtentAlign = 0;
3007}
3008def A4_rcmpneq : HInst<
3009(outs IntRegs:$Rd32),
3010(ins IntRegs:$Rs32, IntRegs:$Rt32),
3011"$Rd32 = !cmp.eq($Rs32,$Rt32)",
3012tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel {
3013let Inst{7-5} = 0b000;
3014let Inst{13-13} = 0b0;
3015let Inst{31-21} = 0b11110011011;
3016let hasNewValue = 1;
3017let opNewValue = 0;
3018let CextOpcode = "A4_rcmpneq";
3019let InputType = "reg";
3020let isCommutable = 1;
3021}
3022def A4_rcmpneqi : HInst<
3023(outs IntRegs:$Rd32),
3024(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3025"$Rd32 = !cmp.eq($Rs32,#$Ii)",
3026tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel {
3027let Inst{13-13} = 0b1;
3028let Inst{31-21} = 0b01110011011;
3029let hasNewValue = 1;
3030let opNewValue = 0;
3031let CextOpcode = "A4_rcmpeqi";
3032let InputType = "imm";
3033let isExtendable = 1;
3034let opExtendable = 2;
3035let isExtentSigned = 1;
3036let opExtentBits = 8;
3037let opExtentAlign = 0;
3038}
3039def A4_round_ri : HInst<
3040(outs IntRegs:$Rd32),
3041(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3042"$Rd32 = round($Rs32,#$Ii)",
3043tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3044let Inst{7-5} = 0b100;
3045let Inst{13-13} = 0b0;
3046let Inst{31-21} = 0b10001100111;
3047let hasNewValue = 1;
3048let opNewValue = 0;
3049let prefersSlot3 = 1;
3050}
3051def A4_round_ri_sat : HInst<
3052(outs IntRegs:$Rd32),
3053(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3054"$Rd32 = round($Rs32,#$Ii):sat",
3055tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
3056let Inst{7-5} = 0b110;
3057let Inst{13-13} = 0b0;
3058let Inst{31-21} = 0b10001100111;
3059let hasNewValue = 1;
3060let opNewValue = 0;
3061let prefersSlot3 = 1;
3062let Defs = [USR_OVF];
3063}
3064def A4_round_rr : HInst<
3065(outs IntRegs:$Rd32),
3066(ins IntRegs:$Rs32, IntRegs:$Rt32),
3067"$Rd32 = round($Rs32,$Rt32)",
3068tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3069let Inst{7-5} = 0b100;
3070let Inst{13-13} = 0b0;
3071let Inst{31-21} = 0b11000110110;
3072let hasNewValue = 1;
3073let opNewValue = 0;
3074let prefersSlot3 = 1;
3075}
3076def A4_round_rr_sat : HInst<
3077(outs IntRegs:$Rd32),
3078(ins IntRegs:$Rs32, IntRegs:$Rt32),
3079"$Rd32 = round($Rs32,$Rt32):sat",
3080tc_0dfac0a7, TypeS_3op>, Enc_5ab2be {
3081let Inst{7-5} = 0b110;
3082let Inst{13-13} = 0b0;
3083let Inst{31-21} = 0b11000110110;
3084let hasNewValue = 1;
3085let opNewValue = 0;
3086let prefersSlot3 = 1;
3087let Defs = [USR_OVF];
3088}
3089def A4_subp_c : HInst<
3090(outs DoubleRegs:$Rdd32, PredRegs:$Px4),
3091(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in),
3092"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry",
3093tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 {
3094let Inst{7-7} = 0b0;
3095let Inst{13-13} = 0b0;
3096let Inst{31-21} = 0b11000010111;
3097let isPredicateLate = 1;
3098let Constraints = "$Px4 = $Px4in";
3099}
3100def A4_tfrcpp : HInst<
3101(outs DoubleRegs:$Rdd32),
3102(ins CtrRegs64:$Css32),
3103"$Rdd32 = $Css32",
3104tc_7476d766, TypeCR>, Enc_667b39 {
3105let Inst{13-5} = 0b000000000;
3106let Inst{31-21} = 0b01101000000;
3107}
3108def A4_tfrpcp : HInst<
3109(outs CtrRegs64:$Cdd32),
3110(ins DoubleRegs:$Rss32),
3111"$Cdd32 = $Rss32",
3112tc_49fdfd4b, TypeCR>, Enc_0ed752 {
3113let Inst{13-5} = 0b000000000;
3114let Inst{31-21} = 0b01100011001;
3115}
3116def A4_tlbmatch : HInst<
3117(outs PredRegs:$Pd4),
3118(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3119"$Pd4 = tlbmatch($Rss32,$Rt32)",
3120tc_d68dca5c, TypeALU64>, Enc_03833b {
3121let Inst{7-2} = 0b011000;
3122let Inst{13-13} = 0b1;
3123let Inst{31-21} = 0b11010010000;
3124let isPredicateLate = 1;
3125}
3126def A4_vcmpbeq_any : HInst<
3127(outs PredRegs:$Pd4),
3128(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3129"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))",
3130tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3131let Inst{7-2} = 0b000000;
3132let Inst{13-13} = 0b1;
3133let Inst{31-21} = 0b11010010000;
3134}
3135def A4_vcmpbeqi : HInst<
3136(outs PredRegs:$Pd4),
3137(ins DoubleRegs:$Rss32, u8_0Imm:$Ii),
3138"$Pd4 = vcmpb.eq($Rss32,#$Ii)",
3139tc_a1297125, TypeALU64>, Enc_0d8adb {
3140let Inst{4-2} = 0b000;
3141let Inst{13-13} = 0b0;
3142let Inst{31-21} = 0b11011100000;
3143}
3144def A4_vcmpbgt : HInst<
3145(outs PredRegs:$Pd4),
3146(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3147"$Pd4 = vcmpb.gt($Rss32,$Rtt32)",
3148tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3149let Inst{7-2} = 0b010000;
3150let Inst{13-13} = 0b1;
3151let Inst{31-21} = 0b11010010000;
3152}
3153def A4_vcmpbgti : HInst<
3154(outs PredRegs:$Pd4),
3155(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3156"$Pd4 = vcmpb.gt($Rss32,#$Ii)",
3157tc_a1297125, TypeALU64>, Enc_0d8adb {
3158let Inst{4-2} = 0b000;
3159let Inst{13-13} = 0b0;
3160let Inst{31-21} = 0b11011100001;
3161}
3162def A4_vcmpbgtui : HInst<
3163(outs PredRegs:$Pd4),
3164(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3165"$Pd4 = vcmpb.gtu($Rss32,#$Ii)",
3166tc_a1297125, TypeALU64>, Enc_3680c2 {
3167let Inst{4-2} = 0b000;
3168let Inst{13-12} = 0b00;
3169let Inst{31-21} = 0b11011100010;
3170}
3171def A4_vcmpheqi : HInst<
3172(outs PredRegs:$Pd4),
3173(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3174"$Pd4 = vcmph.eq($Rss32,#$Ii)",
3175tc_a1297125, TypeALU64>, Enc_0d8adb {
3176let Inst{4-2} = 0b010;
3177let Inst{13-13} = 0b0;
3178let Inst{31-21} = 0b11011100000;
3179}
3180def A4_vcmphgti : HInst<
3181(outs PredRegs:$Pd4),
3182(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3183"$Pd4 = vcmph.gt($Rss32,#$Ii)",
3184tc_a1297125, TypeALU64>, Enc_0d8adb {
3185let Inst{4-2} = 0b010;
3186let Inst{13-13} = 0b0;
3187let Inst{31-21} = 0b11011100001;
3188}
3189def A4_vcmphgtui : HInst<
3190(outs PredRegs:$Pd4),
3191(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3192"$Pd4 = vcmph.gtu($Rss32,#$Ii)",
3193tc_a1297125, TypeALU64>, Enc_3680c2 {
3194let Inst{4-2} = 0b010;
3195let Inst{13-12} = 0b00;
3196let Inst{31-21} = 0b11011100010;
3197}
3198def A4_vcmpweqi : HInst<
3199(outs PredRegs:$Pd4),
3200(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3201"$Pd4 = vcmpw.eq($Rss32,#$Ii)",
3202tc_a1297125, TypeALU64>, Enc_0d8adb {
3203let Inst{4-2} = 0b100;
3204let Inst{13-13} = 0b0;
3205let Inst{31-21} = 0b11011100000;
3206}
3207def A4_vcmpwgti : HInst<
3208(outs PredRegs:$Pd4),
3209(ins DoubleRegs:$Rss32, s8_0Imm:$Ii),
3210"$Pd4 = vcmpw.gt($Rss32,#$Ii)",
3211tc_a1297125, TypeALU64>, Enc_0d8adb {
3212let Inst{4-2} = 0b100;
3213let Inst{13-13} = 0b0;
3214let Inst{31-21} = 0b11011100001;
3215}
3216def A4_vcmpwgtui : HInst<
3217(outs PredRegs:$Pd4),
3218(ins DoubleRegs:$Rss32, u7_0Imm:$Ii),
3219"$Pd4 = vcmpw.gtu($Rss32,#$Ii)",
3220tc_a1297125, TypeALU64>, Enc_3680c2 {
3221let Inst{4-2} = 0b100;
3222let Inst{13-12} = 0b00;
3223let Inst{31-21} = 0b11011100010;
3224}
3225def A4_vrmaxh : HInst<
3226(outs DoubleRegs:$Rxx32),
3227(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3228"$Rxx32 = vrmaxh($Rss32,$Ru32)",
3229tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3230let Inst{7-5} = 0b001;
3231let Inst{13-13} = 0b0;
3232let Inst{31-21} = 0b11001011001;
3233let prefersSlot3 = 1;
3234let Constraints = "$Rxx32 = $Rxx32in";
3235}
3236def A4_vrmaxuh : HInst<
3237(outs DoubleRegs:$Rxx32),
3238(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3239"$Rxx32 = vrmaxuh($Rss32,$Ru32)",
3240tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3241let Inst{7-5} = 0b001;
3242let Inst{13-13} = 0b1;
3243let Inst{31-21} = 0b11001011001;
3244let prefersSlot3 = 1;
3245let Constraints = "$Rxx32 = $Rxx32in";
3246}
3247def A4_vrmaxuw : HInst<
3248(outs DoubleRegs:$Rxx32),
3249(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3250"$Rxx32 = vrmaxuw($Rss32,$Ru32)",
3251tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3252let Inst{7-5} = 0b010;
3253let Inst{13-13} = 0b1;
3254let Inst{31-21} = 0b11001011001;
3255let prefersSlot3 = 1;
3256let Constraints = "$Rxx32 = $Rxx32in";
3257}
3258def A4_vrmaxw : HInst<
3259(outs DoubleRegs:$Rxx32),
3260(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3261"$Rxx32 = vrmaxw($Rss32,$Ru32)",
3262tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3263let Inst{7-5} = 0b010;
3264let Inst{13-13} = 0b0;
3265let Inst{31-21} = 0b11001011001;
3266let prefersSlot3 = 1;
3267let Constraints = "$Rxx32 = $Rxx32in";
3268}
3269def A4_vrminh : HInst<
3270(outs DoubleRegs:$Rxx32),
3271(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3272"$Rxx32 = vrminh($Rss32,$Ru32)",
3273tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3274let Inst{7-5} = 0b101;
3275let Inst{13-13} = 0b0;
3276let Inst{31-21} = 0b11001011001;
3277let prefersSlot3 = 1;
3278let Constraints = "$Rxx32 = $Rxx32in";
3279}
3280def A4_vrminuh : HInst<
3281(outs DoubleRegs:$Rxx32),
3282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3283"$Rxx32 = vrminuh($Rss32,$Ru32)",
3284tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3285let Inst{7-5} = 0b101;
3286let Inst{13-13} = 0b1;
3287let Inst{31-21} = 0b11001011001;
3288let prefersSlot3 = 1;
3289let Constraints = "$Rxx32 = $Rxx32in";
3290}
3291def A4_vrminuw : HInst<
3292(outs DoubleRegs:$Rxx32),
3293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3294"$Rxx32 = vrminuw($Rss32,$Ru32)",
3295tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3296let Inst{7-5} = 0b110;
3297let Inst{13-13} = 0b1;
3298let Inst{31-21} = 0b11001011001;
3299let prefersSlot3 = 1;
3300let Constraints = "$Rxx32 = $Rxx32in";
3301}
3302def A4_vrminw : HInst<
3303(outs DoubleRegs:$Rxx32),
3304(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32),
3305"$Rxx32 = vrminw($Rss32,$Ru32)",
3306tc_788b1d09, TypeS_3op>, Enc_412ff0 {
3307let Inst{7-5} = 0b110;
3308let Inst{13-13} = 0b0;
3309let Inst{31-21} = 0b11001011001;
3310let prefersSlot3 = 1;
3311let Constraints = "$Rxx32 = $Rxx32in";
3312}
3313def A5_ACS : HInst<
3314(outs DoubleRegs:$Rxx32, PredRegs:$Pe4),
3315(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3316"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)",
3317tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> {
3318let Inst{7-7} = 0b0;
3319let Inst{13-13} = 0b0;
3320let Inst{31-21} = 0b11101010101;
3321let isPredicateLate = 1;
3322let prefersSlot3 = 1;
3323let Defs = [USR_OVF];
3324let Constraints = "$Rxx32 = $Rxx32in";
3325}
3326def A5_vaddhubs : HInst<
3327(outs IntRegs:$Rd32),
3328(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3329"$Rd32 = vaddhub($Rss32,$Rtt32):sat",
3330tc_0dfac0a7, TypeS_3op>, Enc_d2216a {
3331let Inst{7-5} = 0b001;
3332let Inst{13-13} = 0b0;
3333let Inst{31-21} = 0b11000001010;
3334let hasNewValue = 1;
3335let opNewValue = 0;
3336let prefersSlot3 = 1;
3337let Defs = [USR_OVF];
3338}
3339def A6_vcmpbeq_notany : HInst<
3340(outs PredRegs:$Pd4),
3341(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3342"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))",
3343tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> {
3344let Inst{7-2} = 0b001000;
3345let Inst{13-13} = 0b1;
3346let Inst{31-21} = 0b11010010000;
3347}
3348def A6_vminub_RdP : HInst<
3349(outs DoubleRegs:$Rdd32, PredRegs:$Pe4),
3350(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
3351"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)",
3352tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> {
3353let Inst{7-7} = 0b0;
3354let Inst{13-13} = 0b0;
3355let Inst{31-21} = 0b11101010111;
3356let isPredicateLate = 1;
3357let prefersSlot3 = 1;
3358}
3359def A7_clip : HInst<
3360(outs IntRegs:$Rd32),
3361(ins IntRegs:$Rs32, u5_0Imm:$Ii),
3362"$Rd32 = clip($Rs32,#$Ii)",
3363tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> {
3364let Inst{7-5} = 0b101;
3365let Inst{13-13} = 0b0;
3366let Inst{31-21} = 0b10001000110;
3367let hasNewValue = 1;
3368let opNewValue = 0;
3369}
3370def A7_croundd_ri : HInst<
3371(outs DoubleRegs:$Rdd32),
3372(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
3373"$Rdd32 = cround($Rss32,#$Ii)",
3374tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> {
3375let Inst{7-5} = 0b010;
3376let Inst{31-21} = 0b10001100111;
3377let prefersSlot3 = 1;
3378}
3379def A7_croundd_rr : HInst<
3380(outs DoubleRegs:$Rdd32),
3381(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
3382"$Rdd32 = cround($Rss32,$Rt32)",
3383tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> {
3384let Inst{7-5} = 0b010;
3385let Inst{13-13} = 0b0;
3386let Inst{31-21} = 0b11000110110;
3387let prefersSlot3 = 1;
3388}
3389def A7_vclip : HInst<
3390(outs DoubleRegs:$Rdd32),
3391(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
3392"$Rdd32 = vclip($Rss32,#$Ii)",
3393tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> {
3394let Inst{7-5} = 0b110;
3395let Inst{13-13} = 0b0;
3396let Inst{31-21} = 0b10001000110;
3397}
3398def C2_all8 : HInst<
3399(outs PredRegs:$Pd4),
3400(ins PredRegs:$Ps4),
3401"$Pd4 = all8($Ps4)",
3402tc_151bf368, TypeCR>, Enc_65d691 {
3403let Inst{13-2} = 0b000000000000;
3404let Inst{31-18} = 0b01101011101000;
3405}
3406def C2_and : HInst<
3407(outs PredRegs:$Pd4),
3408(ins PredRegs:$Pt4, PredRegs:$Ps4),
3409"$Pd4 = and($Pt4,$Ps4)",
3410tc_651cbe02, TypeCR>, Enc_454a26 {
3411let Inst{7-2} = 0b000000;
3412let Inst{13-10} = 0b0000;
3413let Inst{31-18} = 0b01101011000000;
3414}
3415def C2_andn : HInst<
3416(outs PredRegs:$Pd4),
3417(ins PredRegs:$Pt4, PredRegs:$Ps4),
3418"$Pd4 = and($Pt4,!$Ps4)",
3419tc_651cbe02, TypeCR>, Enc_454a26 {
3420let Inst{7-2} = 0b000000;
3421let Inst{13-10} = 0b0000;
3422let Inst{31-18} = 0b01101011011000;
3423}
3424def C2_any8 : HInst<
3425(outs PredRegs:$Pd4),
3426(ins PredRegs:$Ps4),
3427"$Pd4 = any8($Ps4)",
3428tc_151bf368, TypeCR>, Enc_65d691 {
3429let Inst{13-2} = 0b000000000000;
3430let Inst{31-18} = 0b01101011100000;
3431}
3432def C2_bitsclr : HInst<
3433(outs PredRegs:$Pd4),
3434(ins IntRegs:$Rs32, IntRegs:$Rt32),
3435"$Pd4 = bitsclr($Rs32,$Rt32)",
3436tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3437let Inst{7-2} = 0b000000;
3438let Inst{13-13} = 0b0;
3439let Inst{31-21} = 0b11000111100;
3440}
3441def C2_bitsclri : HInst<
3442(outs PredRegs:$Pd4),
3443(ins IntRegs:$Rs32, u6_0Imm:$Ii),
3444"$Pd4 = bitsclr($Rs32,#$Ii)",
3445tc_a1297125, TypeS_2op>, Enc_5d6c34 {
3446let Inst{7-2} = 0b000000;
3447let Inst{31-21} = 0b10000101100;
3448}
3449def C2_bitsset : HInst<
3450(outs PredRegs:$Pd4),
3451(ins IntRegs:$Rs32, IntRegs:$Rt32),
3452"$Pd4 = bitsset($Rs32,$Rt32)",
3453tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
3454let Inst{7-2} = 0b000000;
3455let Inst{13-13} = 0b0;
3456let Inst{31-21} = 0b11000111010;
3457}
3458def C2_ccombinewf : HInst<
3459(outs DoubleRegs:$Rdd32),
3460(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3461"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3462tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3463let Inst{7-7} = 0b1;
3464let Inst{13-13} = 0b0;
3465let Inst{31-21} = 0b11111101000;
3466let isPredicated = 1;
3467let isPredicatedFalse = 1;
3468let BaseOpcode = "A2_combinew";
3469}
3470def C2_ccombinewnewf : HInst<
3471(outs DoubleRegs:$Rdd32),
3472(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3473"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3474tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3475let Inst{7-7} = 0b1;
3476let Inst{13-13} = 0b1;
3477let Inst{31-21} = 0b11111101000;
3478let isPredicated = 1;
3479let isPredicatedFalse = 1;
3480let isPredicatedNew = 1;
3481let BaseOpcode = "A2_combinew";
3482}
3483def C2_ccombinewnewt : HInst<
3484(outs DoubleRegs:$Rdd32),
3485(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3486"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)",
3487tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3488let Inst{7-7} = 0b0;
3489let Inst{13-13} = 0b1;
3490let Inst{31-21} = 0b11111101000;
3491let isPredicated = 1;
3492let isPredicatedNew = 1;
3493let BaseOpcode = "A2_combinew";
3494}
3495def C2_ccombinewt : HInst<
3496(outs DoubleRegs:$Rdd32),
3497(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3498"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)",
3499tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel {
3500let Inst{7-7} = 0b0;
3501let Inst{13-13} = 0b0;
3502let Inst{31-21} = 0b11111101000;
3503let isPredicated = 1;
3504let BaseOpcode = "A2_combinew";
3505}
3506def C2_cmoveif : HInst<
3507(outs IntRegs:$Rd32),
3508(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3509"if (!$Pu4) $Rd32 = #$Ii",
3510tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3511let Inst{13-13} = 0b0;
3512let Inst{20-20} = 0b0;
3513let Inst{31-23} = 0b011111101;
3514let isPredicated = 1;
3515let isPredicatedFalse = 1;
3516let hasNewValue = 1;
3517let opNewValue = 0;
3518let BaseOpcode = "A2_tfrsi";
3519let CextOpcode = "A2_tfr";
3520let InputType = "imm";
3521let isMoveImm = 1;
3522let isExtendable = 1;
3523let opExtendable = 2;
3524let isExtentSigned = 1;
3525let opExtentBits = 12;
3526let opExtentAlign = 0;
3527}
3528def C2_cmoveit : HInst<
3529(outs IntRegs:$Rd32),
3530(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3531"if ($Pu4) $Rd32 = #$Ii",
3532tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3533let Inst{13-13} = 0b0;
3534let Inst{20-20} = 0b0;
3535let Inst{31-23} = 0b011111100;
3536let isPredicated = 1;
3537let hasNewValue = 1;
3538let opNewValue = 0;
3539let BaseOpcode = "A2_tfrsi";
3540let CextOpcode = "A2_tfr";
3541let InputType = "imm";
3542let isMoveImm = 1;
3543let isExtendable = 1;
3544let opExtendable = 2;
3545let isExtentSigned = 1;
3546let opExtentBits = 12;
3547let opExtentAlign = 0;
3548}
3549def C2_cmovenewif : HInst<
3550(outs IntRegs:$Rd32),
3551(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3552"if (!$Pu4.new) $Rd32 = #$Ii",
3553tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3554let Inst{13-13} = 0b1;
3555let Inst{20-20} = 0b0;
3556let Inst{31-23} = 0b011111101;
3557let isPredicated = 1;
3558let isPredicatedFalse = 1;
3559let hasNewValue = 1;
3560let opNewValue = 0;
3561let isPredicatedNew = 1;
3562let BaseOpcode = "A2_tfrsi";
3563let CextOpcode = "A2_tfr";
3564let InputType = "imm";
3565let isMoveImm = 1;
3566let isExtendable = 1;
3567let opExtendable = 2;
3568let isExtentSigned = 1;
3569let opExtentBits = 12;
3570let opExtentAlign = 0;
3571}
3572def C2_cmovenewit : HInst<
3573(outs IntRegs:$Rd32),
3574(ins PredRegs:$Pu4, s32_0Imm:$Ii),
3575"if ($Pu4.new) $Rd32 = #$Ii",
3576tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel {
3577let Inst{13-13} = 0b1;
3578let Inst{20-20} = 0b0;
3579let Inst{31-23} = 0b011111100;
3580let isPredicated = 1;
3581let hasNewValue = 1;
3582let opNewValue = 0;
3583let isPredicatedNew = 1;
3584let BaseOpcode = "A2_tfrsi";
3585let CextOpcode = "A2_tfr";
3586let InputType = "imm";
3587let isMoveImm = 1;
3588let isExtendable = 1;
3589let opExtendable = 2;
3590let isExtentSigned = 1;
3591let opExtentBits = 12;
3592let opExtentAlign = 0;
3593}
3594def C2_cmpeq : HInst<
3595(outs PredRegs:$Pd4),
3596(ins IntRegs:$Rs32, IntRegs:$Rt32),
3597"$Pd4 = cmp.eq($Rs32,$Rt32)",
3598tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3599let Inst{7-2} = 0b000000;
3600let Inst{13-13} = 0b0;
3601let Inst{31-21} = 0b11110010000;
3602let CextOpcode = "C2_cmpeq";
3603let InputType = "reg";
3604let isCommutable = 1;
3605let isCompare = 1;
3606}
3607def C2_cmpeqi : HInst<
3608(outs PredRegs:$Pd4),
3609(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3610"$Pd4 = cmp.eq($Rs32,#$Ii)",
3611tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3612let Inst{4-2} = 0b000;
3613let Inst{31-22} = 0b0111010100;
3614let CextOpcode = "C2_cmpeq";
3615let InputType = "imm";
3616let isCompare = 1;
3617let isExtendable = 1;
3618let opExtendable = 2;
3619let isExtentSigned = 1;
3620let opExtentBits = 10;
3621let opExtentAlign = 0;
3622}
3623def C2_cmpeqp : HInst<
3624(outs PredRegs:$Pd4),
3625(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3626"$Pd4 = cmp.eq($Rss32,$Rtt32)",
3627tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3628let Inst{7-2} = 0b000000;
3629let Inst{13-13} = 0b0;
3630let Inst{31-21} = 0b11010010100;
3631let isCommutable = 1;
3632let isCompare = 1;
3633}
3634def C2_cmpgei : HInst<
3635(outs PredRegs:$Pd4),
3636(ins IntRegs:$Rs32, s8_0Imm:$Ii),
3637"$Pd4 = cmp.ge($Rs32,#$Ii)",
3638tc_d33e5eee, TypeALU32_2op> {
3639let isCompare = 1;
3640let isPseudo = 1;
3641}
3642def C2_cmpgeui : HInst<
3643(outs PredRegs:$Pd4),
3644(ins IntRegs:$Rs32, u8_0Imm:$Ii),
3645"$Pd4 = cmp.geu($Rs32,#$Ii)",
3646tc_d33e5eee, TypeALU32_2op> {
3647let isCompare = 1;
3648let isPseudo = 1;
3649}
3650def C2_cmpgt : HInst<
3651(outs PredRegs:$Pd4),
3652(ins IntRegs:$Rs32, IntRegs:$Rt32),
3653"$Pd4 = cmp.gt($Rs32,$Rt32)",
3654tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3655let Inst{7-2} = 0b000000;
3656let Inst{13-13} = 0b0;
3657let Inst{31-21} = 0b11110010010;
3658let CextOpcode = "C2_cmpgt";
3659let InputType = "reg";
3660let isCompare = 1;
3661}
3662def C2_cmpgti : HInst<
3663(outs PredRegs:$Pd4),
3664(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3665"$Pd4 = cmp.gt($Rs32,#$Ii)",
3666tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3667let Inst{4-2} = 0b000;
3668let Inst{31-22} = 0b0111010101;
3669let CextOpcode = "C2_cmpgt";
3670let InputType = "imm";
3671let isCompare = 1;
3672let isExtendable = 1;
3673let opExtendable = 2;
3674let isExtentSigned = 1;
3675let opExtentBits = 10;
3676let opExtentAlign = 0;
3677}
3678def C2_cmpgtp : HInst<
3679(outs PredRegs:$Pd4),
3680(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3681"$Pd4 = cmp.gt($Rss32,$Rtt32)",
3682tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3683let Inst{7-2} = 0b010000;
3684let Inst{13-13} = 0b0;
3685let Inst{31-21} = 0b11010010100;
3686let isCompare = 1;
3687}
3688def C2_cmpgtu : HInst<
3689(outs PredRegs:$Pd4),
3690(ins IntRegs:$Rs32, IntRegs:$Rt32),
3691"$Pd4 = cmp.gtu($Rs32,$Rt32)",
3692tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3693let Inst{7-2} = 0b000000;
3694let Inst{13-13} = 0b0;
3695let Inst{31-21} = 0b11110010011;
3696let CextOpcode = "C2_cmpgtu";
3697let InputType = "reg";
3698let isCompare = 1;
3699}
3700def C2_cmpgtui : HInst<
3701(outs PredRegs:$Pd4),
3702(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3703"$Pd4 = cmp.gtu($Rs32,#$Ii)",
3704tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3705let Inst{4-2} = 0b000;
3706let Inst{31-21} = 0b01110101100;
3707let CextOpcode = "C2_cmpgtu";
3708let InputType = "imm";
3709let isCompare = 1;
3710let isExtendable = 1;
3711let opExtendable = 2;
3712let isExtentSigned = 0;
3713let opExtentBits = 9;
3714let opExtentAlign = 0;
3715}
3716def C2_cmpgtup : HInst<
3717(outs PredRegs:$Pd4),
3718(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3719"$Pd4 = cmp.gtu($Rss32,$Rtt32)",
3720tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
3721let Inst{7-2} = 0b100000;
3722let Inst{13-13} = 0b0;
3723let Inst{31-21} = 0b11010010100;
3724let isCompare = 1;
3725}
3726def C2_cmplt : HInst<
3727(outs PredRegs:$Pd4),
3728(ins IntRegs:$Rs32, IntRegs:$Rt32),
3729"$Pd4 = cmp.lt($Rs32,$Rt32)",
3730tc_d33e5eee, TypeALU32_3op> {
3731let isCompare = 1;
3732let isPseudo = 1;
3733let isCodeGenOnly = 1;
3734}
3735def C2_cmpltu : HInst<
3736(outs PredRegs:$Pd4),
3737(ins IntRegs:$Rs32, IntRegs:$Rt32),
3738"$Pd4 = cmp.ltu($Rs32,$Rt32)",
3739tc_d33e5eee, TypeALU32_3op> {
3740let isCompare = 1;
3741let isPseudo = 1;
3742let isCodeGenOnly = 1;
3743}
3744def C2_mask : HInst<
3745(outs DoubleRegs:$Rdd32),
3746(ins PredRegs:$Pt4),
3747"$Rdd32 = mask($Pt4)",
3748tc_9f6cd987, TypeS_2op>, Enc_78e566 {
3749let Inst{7-5} = 0b000;
3750let Inst{13-10} = 0b0000;
3751let Inst{31-16} = 0b1000011000000000;
3752}
3753def C2_mux : HInst<
3754(outs IntRegs:$Rd32),
3755(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32),
3756"$Rd32 = mux($Pu4,$Rs32,$Rt32)",
3757tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 {
3758let Inst{7-7} = 0b0;
3759let Inst{13-13} = 0b0;
3760let Inst{31-21} = 0b11110100000;
3761let hasNewValue = 1;
3762let opNewValue = 0;
3763let InputType = "reg";
3764}
3765def C2_muxii : HInst<
3766(outs IntRegs:$Rd32),
3767(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II),
3768"$Rd32 = mux($Pu4,#$Ii,#$II)",
3769tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d {
3770let Inst{31-25} = 0b0111101;
3771let hasNewValue = 1;
3772let opNewValue = 0;
3773let isExtendable = 1;
3774let opExtendable = 2;
3775let isExtentSigned = 1;
3776let opExtentBits = 8;
3777let opExtentAlign = 0;
3778}
3779def C2_muxir : HInst<
3780(outs IntRegs:$Rd32),
3781(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii),
3782"$Rd32 = mux($Pu4,$Rs32,#$Ii)",
3783tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3784let Inst{13-13} = 0b0;
3785let Inst{31-23} = 0b011100110;
3786let hasNewValue = 1;
3787let opNewValue = 0;
3788let InputType = "imm";
3789let isExtendable = 1;
3790let opExtendable = 3;
3791let isExtentSigned = 1;
3792let opExtentBits = 8;
3793let opExtentAlign = 0;
3794}
3795def C2_muxri : HInst<
3796(outs IntRegs:$Rd32),
3797(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32),
3798"$Rd32 = mux($Pu4,#$Ii,$Rs32)",
3799tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f {
3800let Inst{13-13} = 0b0;
3801let Inst{31-23} = 0b011100111;
3802let hasNewValue = 1;
3803let opNewValue = 0;
3804let InputType = "imm";
3805let isExtendable = 1;
3806let opExtendable = 2;
3807let isExtentSigned = 1;
3808let opExtentBits = 8;
3809let opExtentAlign = 0;
3810}
3811def C2_not : HInst<
3812(outs PredRegs:$Pd4),
3813(ins PredRegs:$Ps4),
3814"$Pd4 = not($Ps4)",
3815tc_151bf368, TypeCR>, Enc_65d691 {
3816let Inst{13-2} = 0b000000000000;
3817let Inst{31-18} = 0b01101011110000;
3818}
3819def C2_or : HInst<
3820(outs PredRegs:$Pd4),
3821(ins PredRegs:$Pt4, PredRegs:$Ps4),
3822"$Pd4 = or($Pt4,$Ps4)",
3823tc_651cbe02, TypeCR>, Enc_454a26 {
3824let Inst{7-2} = 0b000000;
3825let Inst{13-10} = 0b0000;
3826let Inst{31-18} = 0b01101011001000;
3827}
3828def C2_orn : HInst<
3829(outs PredRegs:$Pd4),
3830(ins PredRegs:$Pt4, PredRegs:$Ps4),
3831"$Pd4 = or($Pt4,!$Ps4)",
3832tc_651cbe02, TypeCR>, Enc_454a26 {
3833let Inst{7-2} = 0b000000;
3834let Inst{13-10} = 0b0000;
3835let Inst{31-18} = 0b01101011111000;
3836}
3837def C2_pxfer_map : HInst<
3838(outs PredRegs:$Pd4),
3839(ins PredRegs:$Ps4),
3840"$Pd4 = $Ps4",
3841tc_651cbe02, TypeMAPPING> {
3842let isPseudo = 1;
3843let isCodeGenOnly = 1;
3844}
3845def C2_tfrpr : HInst<
3846(outs IntRegs:$Rd32),
3847(ins PredRegs:$Ps4),
3848"$Rd32 = $Ps4",
3849tc_9f6cd987, TypeS_2op>, Enc_f5e933 {
3850let Inst{13-5} = 0b000000000;
3851let Inst{31-18} = 0b10001001010000;
3852let hasNewValue = 1;
3853let opNewValue = 0;
3854}
3855def C2_tfrrp : HInst<
3856(outs PredRegs:$Pd4),
3857(ins IntRegs:$Rs32),
3858"$Pd4 = $Rs32",
3859tc_55b33fda, TypeS_2op>, Enc_48b75f {
3860let Inst{13-2} = 0b000000000000;
3861let Inst{31-21} = 0b10000101010;
3862}
3863def C2_vitpack : HInst<
3864(outs IntRegs:$Rd32),
3865(ins PredRegs:$Ps4, PredRegs:$Pt4),
3866"$Rd32 = vitpack($Ps4,$Pt4)",
3867tc_f34c1c21, TypeS_2op>, Enc_527412 {
3868let Inst{7-5} = 0b000;
3869let Inst{13-10} = 0b0000;
3870let Inst{31-18} = 0b10001001000000;
3871let hasNewValue = 1;
3872let opNewValue = 0;
3873let prefersSlot3 = 1;
3874}
3875def C2_vmux : HInst<
3876(outs DoubleRegs:$Rdd32),
3877(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
3878"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)",
3879tc_6fc5dbea, TypeALU64>, Enc_329361 {
3880let Inst{7-7} = 0b0;
3881let Inst{13-13} = 0b0;
3882let Inst{31-21} = 0b11010001000;
3883}
3884def C2_xor : HInst<
3885(outs PredRegs:$Pd4),
3886(ins PredRegs:$Ps4, PredRegs:$Pt4),
3887"$Pd4 = xor($Ps4,$Pt4)",
3888tc_651cbe02, TypeCR>, Enc_284ebb {
3889let Inst{7-2} = 0b000000;
3890let Inst{13-10} = 0b0000;
3891let Inst{31-18} = 0b01101011010000;
3892}
3893def C4_addipc : HInst<
3894(outs IntRegs:$Rd32),
3895(ins u32_0Imm:$Ii),
3896"$Rd32 = add(pc,#$Ii)",
3897tc_3edca78f, TypeCR>, Enc_607661 {
3898let Inst{6-5} = 0b00;
3899let Inst{13-13} = 0b0;
3900let Inst{31-16} = 0b0110101001001001;
3901let hasNewValue = 1;
3902let opNewValue = 0;
3903let isExtendable = 1;
3904let opExtendable = 1;
3905let isExtentSigned = 0;
3906let opExtentBits = 6;
3907let opExtentAlign = 0;
3908}
3909def C4_and_and : HInst<
3910(outs PredRegs:$Pd4),
3911(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3912"$Pd4 = and($Ps4,and($Pt4,$Pu4))",
3913tc_a7a13fac, TypeCR>, Enc_9ac432 {
3914let Inst{5-2} = 0b0000;
3915let Inst{13-10} = 0b0000;
3916let Inst{31-18} = 0b01101011000100;
3917}
3918def C4_and_andn : HInst<
3919(outs PredRegs:$Pd4),
3920(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3921"$Pd4 = and($Ps4,and($Pt4,!$Pu4))",
3922tc_a7a13fac, TypeCR>, Enc_9ac432 {
3923let Inst{5-2} = 0b0000;
3924let Inst{13-10} = 0b0000;
3925let Inst{31-18} = 0b01101011100100;
3926}
3927def C4_and_or : HInst<
3928(outs PredRegs:$Pd4),
3929(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3930"$Pd4 = and($Ps4,or($Pt4,$Pu4))",
3931tc_a7a13fac, TypeCR>, Enc_9ac432 {
3932let Inst{5-2} = 0b0000;
3933let Inst{13-10} = 0b0000;
3934let Inst{31-18} = 0b01101011001100;
3935}
3936def C4_and_orn : HInst<
3937(outs PredRegs:$Pd4),
3938(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
3939"$Pd4 = and($Ps4,or($Pt4,!$Pu4))",
3940tc_a7a13fac, TypeCR>, Enc_9ac432 {
3941let Inst{5-2} = 0b0000;
3942let Inst{13-10} = 0b0000;
3943let Inst{31-18} = 0b01101011101100;
3944}
3945def C4_cmplte : HInst<
3946(outs PredRegs:$Pd4),
3947(ins IntRegs:$Rs32, IntRegs:$Rt32),
3948"$Pd4 = !cmp.gt($Rs32,$Rt32)",
3949tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3950let Inst{7-2} = 0b000100;
3951let Inst{13-13} = 0b0;
3952let Inst{31-21} = 0b11110010010;
3953let CextOpcode = "C4_cmplte";
3954let InputType = "reg";
3955let isCompare = 1;
3956}
3957def C4_cmpltei : HInst<
3958(outs PredRegs:$Pd4),
3959(ins IntRegs:$Rs32, s32_0Imm:$Ii),
3960"$Pd4 = !cmp.gt($Rs32,#$Ii)",
3961tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
3962let Inst{4-2} = 0b100;
3963let Inst{31-22} = 0b0111010101;
3964let CextOpcode = "C4_cmplte";
3965let InputType = "imm";
3966let isCompare = 1;
3967let isExtendable = 1;
3968let opExtendable = 2;
3969let isExtentSigned = 1;
3970let opExtentBits = 10;
3971let opExtentAlign = 0;
3972}
3973def C4_cmplteu : HInst<
3974(outs PredRegs:$Pd4),
3975(ins IntRegs:$Rs32, IntRegs:$Rt32),
3976"$Pd4 = !cmp.gtu($Rs32,$Rt32)",
3977tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
3978let Inst{7-2} = 0b000100;
3979let Inst{13-13} = 0b0;
3980let Inst{31-21} = 0b11110010011;
3981let CextOpcode = "C4_cmplteu";
3982let InputType = "reg";
3983let isCompare = 1;
3984}
3985def C4_cmplteui : HInst<
3986(outs PredRegs:$Pd4),
3987(ins IntRegs:$Rs32, u32_0Imm:$Ii),
3988"$Pd4 = !cmp.gtu($Rs32,#$Ii)",
3989tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel {
3990let Inst{4-2} = 0b100;
3991let Inst{31-21} = 0b01110101100;
3992let CextOpcode = "C4_cmplteu";
3993let InputType = "imm";
3994let isCompare = 1;
3995let isExtendable = 1;
3996let opExtendable = 2;
3997let isExtentSigned = 0;
3998let opExtentBits = 9;
3999let opExtentAlign = 0;
4000}
4001def C4_cmpneq : HInst<
4002(outs PredRegs:$Pd4),
4003(ins IntRegs:$Rs32, IntRegs:$Rt32),
4004"$Pd4 = !cmp.eq($Rs32,$Rt32)",
4005tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel {
4006let Inst{7-2} = 0b000100;
4007let Inst{13-13} = 0b0;
4008let Inst{31-21} = 0b11110010000;
4009let CextOpcode = "C4_cmpneq";
4010let InputType = "reg";
4011let isCommutable = 1;
4012let isCompare = 1;
4013}
4014def C4_cmpneqi : HInst<
4015(outs PredRegs:$Pd4),
4016(ins IntRegs:$Rs32, s32_0Imm:$Ii),
4017"$Pd4 = !cmp.eq($Rs32,#$Ii)",
4018tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel {
4019let Inst{4-2} = 0b100;
4020let Inst{31-22} = 0b0111010100;
4021let CextOpcode = "C4_cmpneq";
4022let InputType = "imm";
4023let isCompare = 1;
4024let isExtendable = 1;
4025let opExtendable = 2;
4026let isExtentSigned = 1;
4027let opExtentBits = 10;
4028let opExtentAlign = 0;
4029}
4030def C4_fastcorner9 : HInst<
4031(outs PredRegs:$Pd4),
4032(ins PredRegs:$Ps4, PredRegs:$Pt4),
4033"$Pd4 = fastcorner9($Ps4,$Pt4)",
4034tc_651cbe02, TypeCR>, Enc_284ebb {
4035let Inst{7-2} = 0b100100;
4036let Inst{13-10} = 0b1000;
4037let Inst{31-18} = 0b01101011000000;
4038}
4039def C4_fastcorner9_not : HInst<
4040(outs PredRegs:$Pd4),
4041(ins PredRegs:$Ps4, PredRegs:$Pt4),
4042"$Pd4 = !fastcorner9($Ps4,$Pt4)",
4043tc_651cbe02, TypeCR>, Enc_284ebb {
4044let Inst{7-2} = 0b100100;
4045let Inst{13-10} = 0b1000;
4046let Inst{31-18} = 0b01101011000100;
4047}
4048def C4_nbitsclr : HInst<
4049(outs PredRegs:$Pd4),
4050(ins IntRegs:$Rs32, IntRegs:$Rt32),
4051"$Pd4 = !bitsclr($Rs32,$Rt32)",
4052tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4053let Inst{7-2} = 0b000000;
4054let Inst{13-13} = 0b0;
4055let Inst{31-21} = 0b11000111101;
4056}
4057def C4_nbitsclri : HInst<
4058(outs PredRegs:$Pd4),
4059(ins IntRegs:$Rs32, u6_0Imm:$Ii),
4060"$Pd4 = !bitsclr($Rs32,#$Ii)",
4061tc_a1297125, TypeS_2op>, Enc_5d6c34 {
4062let Inst{7-2} = 0b000000;
4063let Inst{31-21} = 0b10000101101;
4064}
4065def C4_nbitsset : HInst<
4066(outs PredRegs:$Pd4),
4067(ins IntRegs:$Rs32, IntRegs:$Rt32),
4068"$Pd4 = !bitsset($Rs32,$Rt32)",
4069tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4070let Inst{7-2} = 0b000000;
4071let Inst{13-13} = 0b0;
4072let Inst{31-21} = 0b11000111011;
4073}
4074def C4_or_and : HInst<
4075(outs PredRegs:$Pd4),
4076(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4077"$Pd4 = or($Ps4,and($Pt4,$Pu4))",
4078tc_a7a13fac, TypeCR>, Enc_9ac432 {
4079let Inst{5-2} = 0b0000;
4080let Inst{13-10} = 0b0000;
4081let Inst{31-18} = 0b01101011010100;
4082}
4083def C4_or_andn : HInst<
4084(outs PredRegs:$Pd4),
4085(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4086"$Pd4 = or($Ps4,and($Pt4,!$Pu4))",
4087tc_a7a13fac, TypeCR>, Enc_9ac432 {
4088let Inst{5-2} = 0b0000;
4089let Inst{13-10} = 0b0000;
4090let Inst{31-18} = 0b01101011110100;
4091}
4092def C4_or_or : HInst<
4093(outs PredRegs:$Pd4),
4094(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4095"$Pd4 = or($Ps4,or($Pt4,$Pu4))",
4096tc_a7a13fac, TypeCR>, Enc_9ac432 {
4097let Inst{5-2} = 0b0000;
4098let Inst{13-10} = 0b0000;
4099let Inst{31-18} = 0b01101011011100;
4100}
4101def C4_or_orn : HInst<
4102(outs PredRegs:$Pd4),
4103(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4),
4104"$Pd4 = or($Ps4,or($Pt4,!$Pu4))",
4105tc_a7a13fac, TypeCR>, Enc_9ac432 {
4106let Inst{5-2} = 0b0000;
4107let Inst{13-10} = 0b0000;
4108let Inst{31-18} = 0b01101011111100;
4109}
4110def F2_conv_d2df : HInst<
4111(outs DoubleRegs:$Rdd32),
4112(ins DoubleRegs:$Rss32),
4113"$Rdd32 = convert_d2df($Rss32)",
4114tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4115let Inst{13-5} = 0b000000011;
4116let Inst{31-21} = 0b10000000111;
4117let isFP = 1;
4118let Uses = [USR];
4119}
4120def F2_conv_d2sf : HInst<
4121(outs IntRegs:$Rd32),
4122(ins DoubleRegs:$Rss32),
4123"$Rd32 = convert_d2sf($Rss32)",
4124tc_9783714b, TypeS_2op>, Enc_90cd8b {
4125let Inst{13-5} = 0b000000001;
4126let Inst{31-21} = 0b10001000010;
4127let hasNewValue = 1;
4128let opNewValue = 0;
4129let isFP = 1;
4130let Uses = [USR];
4131}
4132def F2_conv_df2d : HInst<
4133(outs DoubleRegs:$Rdd32),
4134(ins DoubleRegs:$Rss32),
4135"$Rdd32 = convert_df2d($Rss32)",
4136tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4137let Inst{13-5} = 0b000000000;
4138let Inst{31-21} = 0b10000000111;
4139let isFP = 1;
4140let Uses = [USR];
4141}
4142def F2_conv_df2d_chop : HInst<
4143(outs DoubleRegs:$Rdd32),
4144(ins DoubleRegs:$Rss32),
4145"$Rdd32 = convert_df2d($Rss32):chop",
4146tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4147let Inst{13-5} = 0b000000110;
4148let Inst{31-21} = 0b10000000111;
4149let isFP = 1;
4150let Uses = [USR];
4151}
4152def F2_conv_df2sf : HInst<
4153(outs IntRegs:$Rd32),
4154(ins DoubleRegs:$Rss32),
4155"$Rd32 = convert_df2sf($Rss32)",
4156tc_9783714b, TypeS_2op>, Enc_90cd8b {
4157let Inst{13-5} = 0b000000001;
4158let Inst{31-21} = 0b10001000000;
4159let hasNewValue = 1;
4160let opNewValue = 0;
4161let isFP = 1;
4162let Uses = [USR];
4163}
4164def F2_conv_df2ud : HInst<
4165(outs DoubleRegs:$Rdd32),
4166(ins DoubleRegs:$Rss32),
4167"$Rdd32 = convert_df2ud($Rss32)",
4168tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4169let Inst{13-5} = 0b000000001;
4170let Inst{31-21} = 0b10000000111;
4171let isFP = 1;
4172let Uses = [USR];
4173}
4174def F2_conv_df2ud_chop : HInst<
4175(outs DoubleRegs:$Rdd32),
4176(ins DoubleRegs:$Rss32),
4177"$Rdd32 = convert_df2ud($Rss32):chop",
4178tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4179let Inst{13-5} = 0b000000111;
4180let Inst{31-21} = 0b10000000111;
4181let isFP = 1;
4182let Uses = [USR];
4183}
4184def F2_conv_df2uw : HInst<
4185(outs IntRegs:$Rd32),
4186(ins DoubleRegs:$Rss32),
4187"$Rd32 = convert_df2uw($Rss32)",
4188tc_9783714b, TypeS_2op>, Enc_90cd8b {
4189let Inst{13-5} = 0b000000001;
4190let Inst{31-21} = 0b10001000011;
4191let hasNewValue = 1;
4192let opNewValue = 0;
4193let isFP = 1;
4194let Uses = [USR];
4195}
4196def F2_conv_df2uw_chop : HInst<
4197(outs IntRegs:$Rd32),
4198(ins DoubleRegs:$Rss32),
4199"$Rd32 = convert_df2uw($Rss32):chop",
4200tc_9783714b, TypeS_2op>, Enc_90cd8b {
4201let Inst{13-5} = 0b000000001;
4202let Inst{31-21} = 0b10001000101;
4203let hasNewValue = 1;
4204let opNewValue = 0;
4205let isFP = 1;
4206let Uses = [USR];
4207}
4208def F2_conv_df2w : HInst<
4209(outs IntRegs:$Rd32),
4210(ins DoubleRegs:$Rss32),
4211"$Rd32 = convert_df2w($Rss32)",
4212tc_9783714b, TypeS_2op>, Enc_90cd8b {
4213let Inst{13-5} = 0b000000001;
4214let Inst{31-21} = 0b10001000100;
4215let hasNewValue = 1;
4216let opNewValue = 0;
4217let isFP = 1;
4218let Uses = [USR];
4219}
4220def F2_conv_df2w_chop : HInst<
4221(outs IntRegs:$Rd32),
4222(ins DoubleRegs:$Rss32),
4223"$Rd32 = convert_df2w($Rss32):chop",
4224tc_9783714b, TypeS_2op>, Enc_90cd8b {
4225let Inst{13-5} = 0b000000001;
4226let Inst{31-21} = 0b10001000111;
4227let hasNewValue = 1;
4228let opNewValue = 0;
4229let isFP = 1;
4230let Uses = [USR];
4231}
4232def F2_conv_sf2d : HInst<
4233(outs DoubleRegs:$Rdd32),
4234(ins IntRegs:$Rs32),
4235"$Rdd32 = convert_sf2d($Rs32)",
4236tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4237let Inst{13-5} = 0b000000100;
4238let Inst{31-21} = 0b10000100100;
4239let isFP = 1;
4240let Uses = [USR];
4241}
4242def F2_conv_sf2d_chop : HInst<
4243(outs DoubleRegs:$Rdd32),
4244(ins IntRegs:$Rs32),
4245"$Rdd32 = convert_sf2d($Rs32):chop",
4246tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4247let Inst{13-5} = 0b000000110;
4248let Inst{31-21} = 0b10000100100;
4249let isFP = 1;
4250let Uses = [USR];
4251}
4252def F2_conv_sf2df : HInst<
4253(outs DoubleRegs:$Rdd32),
4254(ins IntRegs:$Rs32),
4255"$Rdd32 = convert_sf2df($Rs32)",
4256tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4257let Inst{13-5} = 0b000000000;
4258let Inst{31-21} = 0b10000100100;
4259let isFP = 1;
4260let Uses = [USR];
4261}
4262def F2_conv_sf2ud : HInst<
4263(outs DoubleRegs:$Rdd32),
4264(ins IntRegs:$Rs32),
4265"$Rdd32 = convert_sf2ud($Rs32)",
4266tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4267let Inst{13-5} = 0b000000011;
4268let Inst{31-21} = 0b10000100100;
4269let isFP = 1;
4270let Uses = [USR];
4271}
4272def F2_conv_sf2ud_chop : HInst<
4273(outs DoubleRegs:$Rdd32),
4274(ins IntRegs:$Rs32),
4275"$Rdd32 = convert_sf2ud($Rs32):chop",
4276tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4277let Inst{13-5} = 0b000000101;
4278let Inst{31-21} = 0b10000100100;
4279let isFP = 1;
4280let Uses = [USR];
4281}
4282def F2_conv_sf2uw : HInst<
4283(outs IntRegs:$Rd32),
4284(ins IntRegs:$Rs32),
4285"$Rd32 = convert_sf2uw($Rs32)",
4286tc_9783714b, TypeS_2op>, Enc_5e2823 {
4287let Inst{13-5} = 0b000000000;
4288let Inst{31-21} = 0b10001011011;
4289let hasNewValue = 1;
4290let opNewValue = 0;
4291let isFP = 1;
4292let Uses = [USR];
4293}
4294def F2_conv_sf2uw_chop : HInst<
4295(outs IntRegs:$Rd32),
4296(ins IntRegs:$Rs32),
4297"$Rd32 = convert_sf2uw($Rs32):chop",
4298tc_9783714b, TypeS_2op>, Enc_5e2823 {
4299let Inst{13-5} = 0b000000001;
4300let Inst{31-21} = 0b10001011011;
4301let hasNewValue = 1;
4302let opNewValue = 0;
4303let isFP = 1;
4304let Uses = [USR];
4305}
4306def F2_conv_sf2w : HInst<
4307(outs IntRegs:$Rd32),
4308(ins IntRegs:$Rs32),
4309"$Rd32 = convert_sf2w($Rs32)",
4310tc_9783714b, TypeS_2op>, Enc_5e2823 {
4311let Inst{13-5} = 0b000000000;
4312let Inst{31-21} = 0b10001011100;
4313let hasNewValue = 1;
4314let opNewValue = 0;
4315let isFP = 1;
4316let Uses = [USR];
4317}
4318def F2_conv_sf2w_chop : HInst<
4319(outs IntRegs:$Rd32),
4320(ins IntRegs:$Rs32),
4321"$Rd32 = convert_sf2w($Rs32):chop",
4322tc_9783714b, TypeS_2op>, Enc_5e2823 {
4323let Inst{13-5} = 0b000000001;
4324let Inst{31-21} = 0b10001011100;
4325let hasNewValue = 1;
4326let opNewValue = 0;
4327let isFP = 1;
4328let Uses = [USR];
4329}
4330def F2_conv_ud2df : HInst<
4331(outs DoubleRegs:$Rdd32),
4332(ins DoubleRegs:$Rss32),
4333"$Rdd32 = convert_ud2df($Rss32)",
4334tc_9783714b, TypeS_2op>, Enc_b9c5fb {
4335let Inst{13-5} = 0b000000010;
4336let Inst{31-21} = 0b10000000111;
4337let isFP = 1;
4338let Uses = [USR];
4339}
4340def F2_conv_ud2sf : HInst<
4341(outs IntRegs:$Rd32),
4342(ins DoubleRegs:$Rss32),
4343"$Rd32 = convert_ud2sf($Rss32)",
4344tc_9783714b, TypeS_2op>, Enc_90cd8b {
4345let Inst{13-5} = 0b000000001;
4346let Inst{31-21} = 0b10001000001;
4347let hasNewValue = 1;
4348let opNewValue = 0;
4349let isFP = 1;
4350let Uses = [USR];
4351}
4352def F2_conv_uw2df : HInst<
4353(outs DoubleRegs:$Rdd32),
4354(ins IntRegs:$Rs32),
4355"$Rdd32 = convert_uw2df($Rs32)",
4356tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4357let Inst{13-5} = 0b000000001;
4358let Inst{31-21} = 0b10000100100;
4359let isFP = 1;
4360let Uses = [USR];
4361}
4362def F2_conv_uw2sf : HInst<
4363(outs IntRegs:$Rd32),
4364(ins IntRegs:$Rs32),
4365"$Rd32 = convert_uw2sf($Rs32)",
4366tc_9783714b, TypeS_2op>, Enc_5e2823 {
4367let Inst{13-5} = 0b000000000;
4368let Inst{31-21} = 0b10001011001;
4369let hasNewValue = 1;
4370let opNewValue = 0;
4371let isFP = 1;
4372let Uses = [USR];
4373}
4374def F2_conv_w2df : HInst<
4375(outs DoubleRegs:$Rdd32),
4376(ins IntRegs:$Rs32),
4377"$Rdd32 = convert_w2df($Rs32)",
4378tc_9783714b, TypeS_2op>, Enc_3a3d62 {
4379let Inst{13-5} = 0b000000010;
4380let Inst{31-21} = 0b10000100100;
4381let isFP = 1;
4382let Uses = [USR];
4383}
4384def F2_conv_w2sf : HInst<
4385(outs IntRegs:$Rd32),
4386(ins IntRegs:$Rs32),
4387"$Rd32 = convert_w2sf($Rs32)",
4388tc_9783714b, TypeS_2op>, Enc_5e2823 {
4389let Inst{13-5} = 0b000000000;
4390let Inst{31-21} = 0b10001011010;
4391let hasNewValue = 1;
4392let opNewValue = 0;
4393let isFP = 1;
4394let Uses = [USR];
4395}
4396def F2_dfadd : HInst<
4397(outs DoubleRegs:$Rdd32),
4398(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4399"$Rdd32 = dfadd($Rss32,$Rtt32)",
4400tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4401let Inst{7-5} = 0b011;
4402let Inst{13-13} = 0b0;
4403let Inst{31-21} = 0b11101000000;
4404let isFP = 1;
4405let Uses = [USR];
4406}
4407def F2_dfclass : HInst<
4408(outs PredRegs:$Pd4),
4409(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
4410"$Pd4 = dfclass($Rss32,#$Ii)",
4411tc_a1297125, TypeALU64>, Enc_1f19b5 {
4412let Inst{4-2} = 0b100;
4413let Inst{13-10} = 0b0000;
4414let Inst{31-21} = 0b11011100100;
4415let isFP = 1;
4416let Uses = [USR];
4417}
4418def F2_dfcmpeq : HInst<
4419(outs PredRegs:$Pd4),
4420(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4421"$Pd4 = dfcmp.eq($Rss32,$Rtt32)",
4422tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4423let Inst{7-2} = 0b000000;
4424let Inst{13-13} = 0b0;
4425let Inst{31-21} = 0b11010010111;
4426let isFP = 1;
4427let Uses = [USR];
4428let isCompare = 1;
4429}
4430def F2_dfcmpge : HInst<
4431(outs PredRegs:$Pd4),
4432(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4433"$Pd4 = dfcmp.ge($Rss32,$Rtt32)",
4434tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4435let Inst{7-2} = 0b010000;
4436let Inst{13-13} = 0b0;
4437let Inst{31-21} = 0b11010010111;
4438let isFP = 1;
4439let Uses = [USR];
4440let isCompare = 1;
4441}
4442def F2_dfcmpgt : HInst<
4443(outs PredRegs:$Pd4),
4444(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4445"$Pd4 = dfcmp.gt($Rss32,$Rtt32)",
4446tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4447let Inst{7-2} = 0b001000;
4448let Inst{13-13} = 0b0;
4449let Inst{31-21} = 0b11010010111;
4450let isFP = 1;
4451let Uses = [USR];
4452let isCompare = 1;
4453}
4454def F2_dfcmpuo : HInst<
4455(outs PredRegs:$Pd4),
4456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4457"$Pd4 = dfcmp.uo($Rss32,$Rtt32)",
4458tc_4a55d03c, TypeALU64>, Enc_fcf7a7 {
4459let Inst{7-2} = 0b011000;
4460let Inst{13-13} = 0b0;
4461let Inst{31-21} = 0b11010010111;
4462let isFP = 1;
4463let Uses = [USR];
4464let isCompare = 1;
4465}
4466def F2_dfimm_n : HInst<
4467(outs DoubleRegs:$Rdd32),
4468(ins u10_0Imm:$Ii),
4469"$Rdd32 = dfmake(#$Ii):neg",
4470tc_65279839, TypeALU64>, Enc_e6c957 {
4471let Inst{20-16} = 0b00000;
4472let Inst{31-22} = 0b1101100101;
4473let prefersSlot3 = 1;
4474}
4475def F2_dfimm_p : HInst<
4476(outs DoubleRegs:$Rdd32),
4477(ins u10_0Imm:$Ii),
4478"$Rdd32 = dfmake(#$Ii):pos",
4479tc_65279839, TypeALU64>, Enc_e6c957 {
4480let Inst{20-16} = 0b00000;
4481let Inst{31-22} = 0b1101100100;
4482let prefersSlot3 = 1;
4483}
4484def F2_dfmax : HInst<
4485(outs DoubleRegs:$Rdd32),
4486(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4487"$Rdd32 = dfmax($Rss32,$Rtt32)",
4488tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4489let Inst{7-5} = 0b011;
4490let Inst{13-13} = 0b0;
4491let Inst{31-21} = 0b11101000001;
4492let isFP = 1;
4493let prefersSlot3 = 1;
4494let Uses = [USR];
4495}
4496def F2_dfmin : HInst<
4497(outs DoubleRegs:$Rdd32),
4498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4499"$Rdd32 = dfmin($Rss32,$Rtt32)",
4500tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> {
4501let Inst{7-5} = 0b011;
4502let Inst{13-13} = 0b0;
4503let Inst{31-21} = 0b11101000110;
4504let isFP = 1;
4505let prefersSlot3 = 1;
4506let Uses = [USR];
4507}
4508def F2_dfmpyfix : HInst<
4509(outs DoubleRegs:$Rdd32),
4510(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4511"$Rdd32 = dfmpyfix($Rss32,$Rtt32)",
4512tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> {
4513let Inst{7-5} = 0b011;
4514let Inst{13-13} = 0b0;
4515let Inst{31-21} = 0b11101000010;
4516let isFP = 1;
4517let Uses = [USR];
4518}
4519def F2_dfmpyhh : HInst<
4520(outs DoubleRegs:$Rxx32),
4521(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4522"$Rxx32 += dfmpyhh($Rss32,$Rtt32)",
4523tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4524let Inst{7-5} = 0b011;
4525let Inst{13-13} = 0b0;
4526let Inst{31-21} = 0b11101010100;
4527let isFP = 1;
4528let Uses = [USR];
4529let Constraints = "$Rxx32 = $Rxx32in";
4530}
4531def F2_dfmpylh : HInst<
4532(outs DoubleRegs:$Rxx32),
4533(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4534"$Rxx32 += dfmpylh($Rss32,$Rtt32)",
4535tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> {
4536let Inst{7-5} = 0b011;
4537let Inst{13-13} = 0b0;
4538let Inst{31-21} = 0b11101010000;
4539let prefersSlot3 = 1;
4540let Constraints = "$Rxx32 = $Rxx32in";
4541}
4542def F2_dfmpyll : HInst<
4543(outs DoubleRegs:$Rdd32),
4544(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4545"$Rdd32 = dfmpyll($Rss32,$Rtt32)",
4546tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> {
4547let Inst{7-5} = 0b011;
4548let Inst{13-13} = 0b0;
4549let Inst{31-21} = 0b11101000101;
4550let prefersSlot3 = 1;
4551}
4552def F2_dfsub : HInst<
4553(outs DoubleRegs:$Rdd32),
4554(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
4555"$Rdd32 = dfsub($Rss32,$Rtt32)",
4556tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> {
4557let Inst{7-5} = 0b011;
4558let Inst{13-13} = 0b0;
4559let Inst{31-21} = 0b11101000100;
4560let isFP = 1;
4561let Uses = [USR];
4562}
4563def F2_sfadd : HInst<
4564(outs IntRegs:$Rd32),
4565(ins IntRegs:$Rs32, IntRegs:$Rt32),
4566"$Rd32 = sfadd($Rs32,$Rt32)",
4567tc_02fe1c65, TypeM>, Enc_5ab2be {
4568let Inst{7-5} = 0b000;
4569let Inst{13-13} = 0b0;
4570let Inst{31-21} = 0b11101011000;
4571let hasNewValue = 1;
4572let opNewValue = 0;
4573let isFP = 1;
4574let Uses = [USR];
4575let isCommutable = 1;
4576}
4577def F2_sfclass : HInst<
4578(outs PredRegs:$Pd4),
4579(ins IntRegs:$Rs32, u5_0Imm:$Ii),
4580"$Pd4 = sfclass($Rs32,#$Ii)",
4581tc_a1297125, TypeS_2op>, Enc_83ee64 {
4582let Inst{7-2} = 0b000000;
4583let Inst{13-13} = 0b0;
4584let Inst{31-21} = 0b10000101111;
4585let isFP = 1;
4586let Uses = [USR];
4587}
4588def F2_sfcmpeq : HInst<
4589(outs PredRegs:$Pd4),
4590(ins IntRegs:$Rs32, IntRegs:$Rt32),
4591"$Pd4 = sfcmp.eq($Rs32,$Rt32)",
4592tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4593let Inst{7-2} = 0b011000;
4594let Inst{13-13} = 0b0;
4595let Inst{31-21} = 0b11000111111;
4596let isFP = 1;
4597let Uses = [USR];
4598let isCompare = 1;
4599}
4600def F2_sfcmpge : HInst<
4601(outs PredRegs:$Pd4),
4602(ins IntRegs:$Rs32, IntRegs:$Rt32),
4603"$Pd4 = sfcmp.ge($Rs32,$Rt32)",
4604tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4605let Inst{7-2} = 0b000000;
4606let Inst{13-13} = 0b0;
4607let Inst{31-21} = 0b11000111111;
4608let isFP = 1;
4609let Uses = [USR];
4610let isCompare = 1;
4611}
4612def F2_sfcmpgt : HInst<
4613(outs PredRegs:$Pd4),
4614(ins IntRegs:$Rs32, IntRegs:$Rt32),
4615"$Pd4 = sfcmp.gt($Rs32,$Rt32)",
4616tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4617let Inst{7-2} = 0b100000;
4618let Inst{13-13} = 0b0;
4619let Inst{31-21} = 0b11000111111;
4620let isFP = 1;
4621let Uses = [USR];
4622let isCompare = 1;
4623}
4624def F2_sfcmpuo : HInst<
4625(outs PredRegs:$Pd4),
4626(ins IntRegs:$Rs32, IntRegs:$Rt32),
4627"$Pd4 = sfcmp.uo($Rs32,$Rt32)",
4628tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
4629let Inst{7-2} = 0b001000;
4630let Inst{13-13} = 0b0;
4631let Inst{31-21} = 0b11000111111;
4632let isFP = 1;
4633let Uses = [USR];
4634let isCompare = 1;
4635}
4636def F2_sffixupd : HInst<
4637(outs IntRegs:$Rd32),
4638(ins IntRegs:$Rs32, IntRegs:$Rt32),
4639"$Rd32 = sffixupd($Rs32,$Rt32)",
4640tc_02fe1c65, TypeM>, Enc_5ab2be {
4641let Inst{7-5} = 0b001;
4642let Inst{13-13} = 0b0;
4643let Inst{31-21} = 0b11101011110;
4644let hasNewValue = 1;
4645let opNewValue = 0;
4646let isFP = 1;
4647}
4648def F2_sffixupn : HInst<
4649(outs IntRegs:$Rd32),
4650(ins IntRegs:$Rs32, IntRegs:$Rt32),
4651"$Rd32 = sffixupn($Rs32,$Rt32)",
4652tc_02fe1c65, TypeM>, Enc_5ab2be {
4653let Inst{7-5} = 0b000;
4654let Inst{13-13} = 0b0;
4655let Inst{31-21} = 0b11101011110;
4656let hasNewValue = 1;
4657let opNewValue = 0;
4658let isFP = 1;
4659}
4660def F2_sffixupr : HInst<
4661(outs IntRegs:$Rd32),
4662(ins IntRegs:$Rs32),
4663"$Rd32 = sffixupr($Rs32)",
4664tc_9783714b, TypeS_2op>, Enc_5e2823 {
4665let Inst{13-5} = 0b000000000;
4666let Inst{31-21} = 0b10001011101;
4667let hasNewValue = 1;
4668let opNewValue = 0;
4669let isFP = 1;
4670}
4671def F2_sffma : HInst<
4672(outs IntRegs:$Rx32),
4673(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4674"$Rx32 += sfmpy($Rs32,$Rt32)",
4675tc_9e72dc89, TypeM>, Enc_2ae154 {
4676let Inst{7-5} = 0b100;
4677let Inst{13-13} = 0b0;
4678let Inst{31-21} = 0b11101111000;
4679let hasNewValue = 1;
4680let opNewValue = 0;
4681let isFP = 1;
4682let Uses = [USR];
4683let Constraints = "$Rx32 = $Rx32in";
4684}
4685def F2_sffma_lib : HInst<
4686(outs IntRegs:$Rx32),
4687(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4688"$Rx32 += sfmpy($Rs32,$Rt32):lib",
4689tc_9e72dc89, TypeM>, Enc_2ae154 {
4690let Inst{7-5} = 0b110;
4691let Inst{13-13} = 0b0;
4692let Inst{31-21} = 0b11101111000;
4693let hasNewValue = 1;
4694let opNewValue = 0;
4695let isFP = 1;
4696let Uses = [USR];
4697let Constraints = "$Rx32 = $Rx32in";
4698}
4699def F2_sffma_sc : HInst<
4700(outs IntRegs:$Rx32),
4701(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4),
4702"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale",
4703tc_9edb7c77, TypeM>, Enc_437f33 {
4704let Inst{7-7} = 0b1;
4705let Inst{13-13} = 0b0;
4706let Inst{31-21} = 0b11101111011;
4707let hasNewValue = 1;
4708let opNewValue = 0;
4709let isFP = 1;
4710let Uses = [USR];
4711let Constraints = "$Rx32 = $Rx32in";
4712}
4713def F2_sffms : HInst<
4714(outs IntRegs:$Rx32),
4715(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4716"$Rx32 -= sfmpy($Rs32,$Rt32)",
4717tc_9e72dc89, TypeM>, Enc_2ae154 {
4718let Inst{7-5} = 0b101;
4719let Inst{13-13} = 0b0;
4720let Inst{31-21} = 0b11101111000;
4721let hasNewValue = 1;
4722let opNewValue = 0;
4723let isFP = 1;
4724let Uses = [USR];
4725let Constraints = "$Rx32 = $Rx32in";
4726}
4727def F2_sffms_lib : HInst<
4728(outs IntRegs:$Rx32),
4729(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4730"$Rx32 -= sfmpy($Rs32,$Rt32):lib",
4731tc_9e72dc89, TypeM>, Enc_2ae154 {
4732let Inst{7-5} = 0b111;
4733let Inst{13-13} = 0b0;
4734let Inst{31-21} = 0b11101111000;
4735let hasNewValue = 1;
4736let opNewValue = 0;
4737let isFP = 1;
4738let Uses = [USR];
4739let Constraints = "$Rx32 = $Rx32in";
4740}
4741def F2_sfimm_n : HInst<
4742(outs IntRegs:$Rd32),
4743(ins u10_0Imm:$Ii),
4744"$Rd32 = sfmake(#$Ii):neg",
4745tc_65279839, TypeALU64>, Enc_6c9440 {
4746let Inst{20-16} = 0b00000;
4747let Inst{31-22} = 0b1101011001;
4748let hasNewValue = 1;
4749let opNewValue = 0;
4750let prefersSlot3 = 1;
4751}
4752def F2_sfimm_p : HInst<
4753(outs IntRegs:$Rd32),
4754(ins u10_0Imm:$Ii),
4755"$Rd32 = sfmake(#$Ii):pos",
4756tc_65279839, TypeALU64>, Enc_6c9440 {
4757let Inst{20-16} = 0b00000;
4758let Inst{31-22} = 0b1101011000;
4759let hasNewValue = 1;
4760let opNewValue = 0;
4761let prefersSlot3 = 1;
4762}
4763def F2_sfinvsqrta : HInst<
4764(outs IntRegs:$Rd32, PredRegs:$Pe4),
4765(ins IntRegs:$Rs32),
4766"$Rd32,$Pe4 = sfinvsqrta($Rs32)",
4767tc_7f7f45f5, TypeS_2op>, Enc_890909 {
4768let Inst{13-7} = 0b0000000;
4769let Inst{31-21} = 0b10001011111;
4770let hasNewValue = 1;
4771let opNewValue = 0;
4772let isFP = 1;
4773let isPredicateLate = 1;
4774}
4775def F2_sfmax : HInst<
4776(outs IntRegs:$Rd32),
4777(ins IntRegs:$Rs32, IntRegs:$Rt32),
4778"$Rd32 = sfmax($Rs32,$Rt32)",
4779tc_c20701f0, TypeM>, Enc_5ab2be {
4780let Inst{7-5} = 0b000;
4781let Inst{13-13} = 0b0;
4782let Inst{31-21} = 0b11101011100;
4783let hasNewValue = 1;
4784let opNewValue = 0;
4785let isFP = 1;
4786let prefersSlot3 = 1;
4787let Uses = [USR];
4788}
4789def F2_sfmin : HInst<
4790(outs IntRegs:$Rd32),
4791(ins IntRegs:$Rs32, IntRegs:$Rt32),
4792"$Rd32 = sfmin($Rs32,$Rt32)",
4793tc_c20701f0, TypeM>, Enc_5ab2be {
4794let Inst{7-5} = 0b001;
4795let Inst{13-13} = 0b0;
4796let Inst{31-21} = 0b11101011100;
4797let hasNewValue = 1;
4798let opNewValue = 0;
4799let isFP = 1;
4800let prefersSlot3 = 1;
4801let Uses = [USR];
4802}
4803def F2_sfmpy : HInst<
4804(outs IntRegs:$Rd32),
4805(ins IntRegs:$Rs32, IntRegs:$Rt32),
4806"$Rd32 = sfmpy($Rs32,$Rt32)",
4807tc_02fe1c65, TypeM>, Enc_5ab2be {
4808let Inst{7-5} = 0b000;
4809let Inst{13-13} = 0b0;
4810let Inst{31-21} = 0b11101011010;
4811let hasNewValue = 1;
4812let opNewValue = 0;
4813let isFP = 1;
4814let Uses = [USR];
4815let isCommutable = 1;
4816}
4817def F2_sfrecipa : HInst<
4818(outs IntRegs:$Rd32, PredRegs:$Pe4),
4819(ins IntRegs:$Rs32, IntRegs:$Rt32),
4820"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)",
4821tc_f7569068, TypeM>, Enc_a94f3b {
4822let Inst{7-7} = 0b1;
4823let Inst{13-13} = 0b0;
4824let Inst{31-21} = 0b11101011111;
4825let hasNewValue = 1;
4826let opNewValue = 0;
4827let isFP = 1;
4828let isPredicateLate = 1;
4829}
4830def F2_sfsub : HInst<
4831(outs IntRegs:$Rd32),
4832(ins IntRegs:$Rs32, IntRegs:$Rt32),
4833"$Rd32 = sfsub($Rs32,$Rt32)",
4834tc_02fe1c65, TypeM>, Enc_5ab2be {
4835let Inst{7-5} = 0b001;
4836let Inst{13-13} = 0b0;
4837let Inst{31-21} = 0b11101011000;
4838let hasNewValue = 1;
4839let opNewValue = 0;
4840let isFP = 1;
4841let Uses = [USR];
4842}
4843def G4_tfrgcpp : HInst<
4844(outs DoubleRegs:$Rdd32),
4845(ins GuestRegs64:$Gss32),
4846"$Rdd32 = $Gss32",
4847tc_fae9dfa5, TypeCR>, Enc_0aa344 {
4848let Inst{13-5} = 0b000000000;
4849let Inst{31-21} = 0b01101000001;
4850}
4851def G4_tfrgcrr : HInst<
4852(outs IntRegs:$Rd32),
4853(ins GuestRegs:$Gs32),
4854"$Rd32 = $Gs32",
4855tc_fae9dfa5, TypeCR>, Enc_44271f {
4856let Inst{13-5} = 0b000000000;
4857let Inst{31-21} = 0b01101010001;
4858let hasNewValue = 1;
4859let opNewValue = 0;
4860}
4861def G4_tfrgpcp : HInst<
4862(outs GuestRegs64:$Gdd32),
4863(ins DoubleRegs:$Rss32),
4864"$Gdd32 = $Rss32",
4865tc_6ae3426b, TypeCR>, Enc_ed5027 {
4866let Inst{13-5} = 0b000000000;
4867let Inst{31-21} = 0b01100011000;
4868let hasNewValue = 1;
4869let opNewValue = 0;
4870}
4871def G4_tfrgrcr : HInst<
4872(outs GuestRegs:$Gd32),
4873(ins IntRegs:$Rs32),
4874"$Gd32 = $Rs32",
4875tc_6ae3426b, TypeCR>, Enc_621fba {
4876let Inst{13-5} = 0b000000000;
4877let Inst{31-21} = 0b01100010000;
4878let hasNewValue = 1;
4879let opNewValue = 0;
4880}
4881def J2_call : HInst<
4882(outs),
4883(ins a30_2Imm:$Ii),
4884"call $Ii",
4885tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel {
4886let Inst{0-0} = 0b0;
4887let Inst{31-25} = 0b0101101;
4888let isCall = 1;
4889let prefersSlot3 = 1;
4890let cofRelax2 = 1;
4891let cofMax1 = 1;
4892let Uses = [R29];
4893let Defs = [PC, R31];
4894let BaseOpcode = "J2_call";
4895let hasSideEffects = 1;
4896let isPredicable = 1;
4897let isExtendable = 1;
4898let opExtendable = 0;
4899let isExtentSigned = 1;
4900let opExtentBits = 24;
4901let opExtentAlign = 2;
4902}
4903def J2_callf : HInst<
4904(outs),
4905(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4906"if (!$Pu4) call $Ii",
4907tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4908let Inst{0-0} = 0b0;
4909let Inst{12-10} = 0b000;
4910let Inst{21-21} = 0b1;
4911let Inst{31-24} = 0b01011101;
4912let isPredicated = 1;
4913let isPredicatedFalse = 1;
4914let isCall = 1;
4915let prefersSlot3 = 1;
4916let cofRelax1 = 1;
4917let cofRelax2 = 1;
4918let cofMax1 = 1;
4919let Uses = [R29];
4920let Defs = [PC, R31];
4921let BaseOpcode = "J2_call";
4922let hasSideEffects = 1;
4923let isTaken = Inst{12};
4924let isExtendable = 1;
4925let opExtendable = 1;
4926let isExtentSigned = 1;
4927let opExtentBits = 17;
4928let opExtentAlign = 2;
4929}
4930def J2_callr : HInst<
4931(outs),
4932(ins IntRegs:$Rs32),
4933"callr $Rs32",
4934tc_362b0be2, TypeJ>, Enc_ecbcc8 {
4935let Inst{13-0} = 0b00000000000000;
4936let Inst{31-21} = 0b01010000101;
4937let isCall = 1;
4938let prefersSlot3 = 1;
4939let cofMax1 = 1;
4940let Uses = [R29];
4941let Defs = [PC, R31];
4942let hasSideEffects = 1;
4943}
4944def J2_callrf : HInst<
4945(outs),
4946(ins PredRegs:$Pu4, IntRegs:$Rs32),
4947"if (!$Pu4) callr $Rs32",
4948tc_dc51281d, TypeJ>, Enc_88d4d9 {
4949let Inst{7-0} = 0b00000000;
4950let Inst{13-10} = 0b0000;
4951let Inst{31-21} = 0b01010001001;
4952let isPredicated = 1;
4953let isPredicatedFalse = 1;
4954let isCall = 1;
4955let prefersSlot3 = 1;
4956let cofMax1 = 1;
4957let Uses = [R29];
4958let Defs = [PC, R31];
4959let hasSideEffects = 1;
4960let isTaken = Inst{12};
4961}
4962def J2_callrt : HInst<
4963(outs),
4964(ins PredRegs:$Pu4, IntRegs:$Rs32),
4965"if ($Pu4) callr $Rs32",
4966tc_dc51281d, TypeJ>, Enc_88d4d9 {
4967let Inst{7-0} = 0b00000000;
4968let Inst{13-10} = 0b0000;
4969let Inst{31-21} = 0b01010001000;
4970let isPredicated = 1;
4971let isCall = 1;
4972let prefersSlot3 = 1;
4973let cofMax1 = 1;
4974let Uses = [R29];
4975let Defs = [PC, R31];
4976let hasSideEffects = 1;
4977let isTaken = Inst{12};
4978}
4979def J2_callt : HInst<
4980(outs),
4981(ins PredRegs:$Pu4, a30_2Imm:$Ii),
4982"if ($Pu4) call $Ii",
4983tc_69bfb303, TypeJ>, Enc_daea09, PredRel {
4984let Inst{0-0} = 0b0;
4985let Inst{12-10} = 0b000;
4986let Inst{21-21} = 0b0;
4987let Inst{31-24} = 0b01011101;
4988let isPredicated = 1;
4989let isCall = 1;
4990let prefersSlot3 = 1;
4991let cofRelax1 = 1;
4992let cofRelax2 = 1;
4993let cofMax1 = 1;
4994let Uses = [R29];
4995let Defs = [PC, R31];
4996let BaseOpcode = "J2_call";
4997let hasSideEffects = 1;
4998let isTaken = Inst{12};
4999let isExtendable = 1;
5000let opExtendable = 1;
5001let isExtentSigned = 1;
5002let opExtentBits = 17;
5003let opExtentAlign = 2;
5004}
5005def J2_endloop0 : HInst<
5006(outs),
5007(ins),
5008"endloop0",
5009tc_23708a21, TypeJ> {
5010let Uses = [LC0, SA0];
5011let Defs = [LC0, P3, PC, USR];
5012let isBranch = 1;
5013let isTerminator = 1;
5014let isPseudo = 1;
5015}
5016def J2_endloop01 : HInst<
5017(outs),
5018(ins),
5019"endloop01",
5020tc_23708a21, TypeJ> {
5021let Uses = [LC0, LC1, SA0, SA1];
5022let Defs = [LC0, LC1, P3, PC, USR];
5023let isPseudo = 1;
5024}
5025def J2_endloop1 : HInst<
5026(outs),
5027(ins),
5028"endloop1",
5029tc_23708a21, TypeJ> {
5030let Uses = [LC1, SA1];
5031let Defs = [LC1, PC];
5032let isBranch = 1;
5033let isTerminator = 1;
5034let isPseudo = 1;
5035}
5036def J2_jump : HInst<
5037(outs),
5038(ins b30_2Imm:$Ii),
5039"jump $Ii",
5040tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel {
5041let Inst{0-0} = 0b0;
5042let Inst{31-25} = 0b0101100;
5043let isTerminator = 1;
5044let isBranch = 1;
5045let cofRelax2 = 1;
5046let cofMax1 = 1;
5047let Defs = [PC];
5048let BaseOpcode = "J2_jump";
5049let InputType = "imm";
5050let isBarrier = 1;
5051let isPredicable = 1;
5052let isExtendable = 1;
5053let opExtendable = 0;
5054let isExtentSigned = 1;
5055let opExtentBits = 24;
5056let opExtentAlign = 2;
5057}
5058def J2_jumpf : HInst<
5059(outs),
5060(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5061"if (!$Pu4) jump:nt $Ii",
5062tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5063let Inst{0-0} = 0b0;
5064let Inst{12-10} = 0b000;
5065let Inst{21-21} = 0b1;
5066let Inst{31-24} = 0b01011100;
5067let isPredicated = 1;
5068let isPredicatedFalse = 1;
5069let isTerminator = 1;
5070let isBranch = 1;
5071let cofRelax1 = 1;
5072let cofRelax2 = 1;
5073let cofMax1 = 1;
5074let Defs = [PC];
5075let BaseOpcode = "J2_jump";
5076let InputType = "imm";
5077let isTaken = Inst{12};
5078let isExtendable = 1;
5079let opExtendable = 1;
5080let isExtentSigned = 1;
5081let opExtentBits = 17;
5082let opExtentAlign = 2;
5083}
5084def J2_jumpf_nopred_map : HInst<
5085(outs),
5086(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5087"if (!$Pu4) jump $Ii",
5088tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5089let isPseudo = 1;
5090let isCodeGenOnly = 1;
5091}
5092def J2_jumpfnew : HInst<
5093(outs),
5094(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5095"if (!$Pu4.new) jump:nt $Ii",
5096tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5097let Inst{0-0} = 0b0;
5098let Inst{12-10} = 0b010;
5099let Inst{21-21} = 0b1;
5100let Inst{31-24} = 0b01011100;
5101let isPredicated = 1;
5102let isPredicatedFalse = 1;
5103let isTerminator = 1;
5104let isBranch = 1;
5105let isPredicatedNew = 1;
5106let cofRelax1 = 1;
5107let cofRelax2 = 1;
5108let cofMax1 = 1;
5109let Defs = [PC];
5110let BaseOpcode = "J2_jump";
5111let InputType = "imm";
5112let isTaken = Inst{12};
5113let isExtendable = 1;
5114let opExtendable = 1;
5115let isExtentSigned = 1;
5116let opExtentBits = 17;
5117let opExtentAlign = 2;
5118}
5119def J2_jumpfnewpt : HInst<
5120(outs),
5121(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5122"if (!$Pu4.new) jump:t $Ii",
5123tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5124let Inst{0-0} = 0b0;
5125let Inst{12-10} = 0b110;
5126let Inst{21-21} = 0b1;
5127let Inst{31-24} = 0b01011100;
5128let isPredicated = 1;
5129let isPredicatedFalse = 1;
5130let isTerminator = 1;
5131let isBranch = 1;
5132let isPredicatedNew = 1;
5133let cofRelax1 = 1;
5134let cofRelax2 = 1;
5135let cofMax1 = 1;
5136let Defs = [PC];
5137let BaseOpcode = "J2_jump";
5138let InputType = "imm";
5139let isTaken = Inst{12};
5140let isExtendable = 1;
5141let opExtendable = 1;
5142let isExtentSigned = 1;
5143let opExtentBits = 17;
5144let opExtentAlign = 2;
5145}
5146def J2_jumpfpt : HInst<
5147(outs),
5148(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5149"if (!$Pu4) jump:t $Ii",
5150tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5151let Inst{0-0} = 0b0;
5152let Inst{12-10} = 0b100;
5153let Inst{21-21} = 0b1;
5154let Inst{31-24} = 0b01011100;
5155let isPredicated = 1;
5156let isPredicatedFalse = 1;
5157let isTerminator = 1;
5158let isBranch = 1;
5159let cofRelax1 = 1;
5160let cofRelax2 = 1;
5161let cofMax1 = 1;
5162let Defs = [PC];
5163let BaseOpcode = "J2_jump";
5164let InputType = "imm";
5165let isTaken = Inst{12};
5166let isExtendable = 1;
5167let opExtendable = 1;
5168let isExtentSigned = 1;
5169let opExtentBits = 17;
5170let opExtentAlign = 2;
5171}
5172def J2_jumpr : HInst<
5173(outs),
5174(ins IntRegs:$Rs32),
5175"jumpr $Rs32",
5176tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel {
5177let Inst{13-0} = 0b00000000000000;
5178let Inst{31-21} = 0b01010010100;
5179let isTerminator = 1;
5180let isIndirectBranch = 1;
5181let isBranch = 1;
5182let cofMax1 = 1;
5183let Defs = [PC];
5184let BaseOpcode = "J2_jumpr";
5185let InputType = "reg";
5186let isBarrier = 1;
5187let isPredicable = 1;
5188}
5189def J2_jumprf : HInst<
5190(outs),
5191(ins PredRegs:$Pu4, IntRegs:$Rs32),
5192"if (!$Pu4) jumpr:nt $Rs32",
5193tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5194let Inst{7-0} = 0b00000000;
5195let Inst{13-10} = 0b0000;
5196let Inst{31-21} = 0b01010011011;
5197let isPredicated = 1;
5198let isPredicatedFalse = 1;
5199let isTerminator = 1;
5200let isIndirectBranch = 1;
5201let isBranch = 1;
5202let cofMax1 = 1;
5203let Defs = [PC];
5204let BaseOpcode = "J2_jumpr";
5205let InputType = "reg";
5206let isTaken = Inst{12};
5207}
5208def J2_jumprf_nopred_map : HInst<
5209(outs),
5210(ins PredRegs:$Pu4, IntRegs:$Rs32),
5211"if (!$Pu4) jumpr $Rs32",
5212tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5213let isPseudo = 1;
5214let isCodeGenOnly = 1;
5215}
5216def J2_jumprfnew : HInst<
5217(outs),
5218(ins PredRegs:$Pu4, IntRegs:$Rs32),
5219"if (!$Pu4.new) jumpr:nt $Rs32",
5220tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5221let Inst{7-0} = 0b00000000;
5222let Inst{13-10} = 0b0010;
5223let Inst{31-21} = 0b01010011011;
5224let isPredicated = 1;
5225let isPredicatedFalse = 1;
5226let isTerminator = 1;
5227let isIndirectBranch = 1;
5228let isBranch = 1;
5229let isPredicatedNew = 1;
5230let cofMax1 = 1;
5231let Defs = [PC];
5232let BaseOpcode = "J2_jumpr";
5233let InputType = "reg";
5234let isTaken = Inst{12};
5235}
5236def J2_jumprfnewpt : HInst<
5237(outs),
5238(ins PredRegs:$Pu4, IntRegs:$Rs32),
5239"if (!$Pu4.new) jumpr:t $Rs32",
5240tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5241let Inst{7-0} = 0b00000000;
5242let Inst{13-10} = 0b0110;
5243let Inst{31-21} = 0b01010011011;
5244let isPredicated = 1;
5245let isPredicatedFalse = 1;
5246let isTerminator = 1;
5247let isIndirectBranch = 1;
5248let isBranch = 1;
5249let isPredicatedNew = 1;
5250let cofMax1 = 1;
5251let Defs = [PC];
5252let BaseOpcode = "J2_jumpr";
5253let InputType = "reg";
5254let isTaken = Inst{12};
5255}
5256def J2_jumprfpt : HInst<
5257(outs),
5258(ins PredRegs:$Pu4, IntRegs:$Rs32),
5259"if (!$Pu4) jumpr:t $Rs32",
5260tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5261let Inst{7-0} = 0b00000000;
5262let Inst{13-10} = 0b0100;
5263let Inst{31-21} = 0b01010011011;
5264let isPredicated = 1;
5265let isPredicatedFalse = 1;
5266let isTerminator = 1;
5267let isIndirectBranch = 1;
5268let isBranch = 1;
5269let cofMax1 = 1;
5270let Defs = [PC];
5271let BaseOpcode = "J2_jumpr";
5272let InputType = "reg";
5273let isTaken = Inst{12};
5274}
5275def J2_jumprgtez : HInst<
5276(outs),
5277(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5278"if ($Rs32>=#0) jump:nt $Ii",
5279tc_57a55b54, TypeCR>, Enc_0fa531 {
5280let Inst{0-0} = 0b0;
5281let Inst{12-12} = 0b0;
5282let Inst{31-22} = 0b0110000101;
5283let isPredicated = 1;
5284let isTerminator = 1;
5285let isBranch = 1;
5286let isPredicatedNew = 1;
5287let cofRelax1 = 1;
5288let cofRelax2 = 1;
5289let cofMax1 = 1;
5290let Defs = [PC];
5291let isTaken = Inst{12};
5292}
5293def J2_jumprgtezpt : HInst<
5294(outs),
5295(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5296"if ($Rs32>=#0) jump:t $Ii",
5297tc_57a55b54, TypeCR>, Enc_0fa531 {
5298let Inst{0-0} = 0b0;
5299let Inst{12-12} = 0b1;
5300let Inst{31-22} = 0b0110000101;
5301let isPredicated = 1;
5302let isTerminator = 1;
5303let isBranch = 1;
5304let isPredicatedNew = 1;
5305let cofRelax1 = 1;
5306let cofRelax2 = 1;
5307let cofMax1 = 1;
5308let Defs = [PC];
5309let isTaken = Inst{12};
5310}
5311def J2_jumprltez : HInst<
5312(outs),
5313(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5314"if ($Rs32<=#0) jump:nt $Ii",
5315tc_57a55b54, TypeCR>, Enc_0fa531 {
5316let Inst{0-0} = 0b0;
5317let Inst{12-12} = 0b0;
5318let Inst{31-22} = 0b0110000111;
5319let isPredicated = 1;
5320let isTerminator = 1;
5321let isBranch = 1;
5322let isPredicatedNew = 1;
5323let cofRelax1 = 1;
5324let cofRelax2 = 1;
5325let cofMax1 = 1;
5326let Defs = [PC];
5327let isTaken = Inst{12};
5328}
5329def J2_jumprltezpt : HInst<
5330(outs),
5331(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5332"if ($Rs32<=#0) jump:t $Ii",
5333tc_57a55b54, TypeCR>, Enc_0fa531 {
5334let Inst{0-0} = 0b0;
5335let Inst{12-12} = 0b1;
5336let Inst{31-22} = 0b0110000111;
5337let isPredicated = 1;
5338let isTerminator = 1;
5339let isBranch = 1;
5340let isPredicatedNew = 1;
5341let cofRelax1 = 1;
5342let cofRelax2 = 1;
5343let cofMax1 = 1;
5344let Defs = [PC];
5345let isTaken = Inst{12};
5346}
5347def J2_jumprnz : HInst<
5348(outs),
5349(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5350"if ($Rs32==#0) jump:nt $Ii",
5351tc_57a55b54, TypeCR>, Enc_0fa531 {
5352let Inst{0-0} = 0b0;
5353let Inst{12-12} = 0b0;
5354let Inst{31-22} = 0b0110000110;
5355let isPredicated = 1;
5356let isTerminator = 1;
5357let isBranch = 1;
5358let isPredicatedNew = 1;
5359let cofRelax1 = 1;
5360let cofRelax2 = 1;
5361let cofMax1 = 1;
5362let Defs = [PC];
5363let isTaken = Inst{12};
5364}
5365def J2_jumprnzpt : HInst<
5366(outs),
5367(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5368"if ($Rs32==#0) jump:t $Ii",
5369tc_57a55b54, TypeCR>, Enc_0fa531 {
5370let Inst{0-0} = 0b0;
5371let Inst{12-12} = 0b1;
5372let Inst{31-22} = 0b0110000110;
5373let isPredicated = 1;
5374let isTerminator = 1;
5375let isBranch = 1;
5376let isPredicatedNew = 1;
5377let cofRelax1 = 1;
5378let cofRelax2 = 1;
5379let cofMax1 = 1;
5380let Defs = [PC];
5381let isTaken = Inst{12};
5382}
5383def J2_jumprt : HInst<
5384(outs),
5385(ins PredRegs:$Pu4, IntRegs:$Rs32),
5386"if ($Pu4) jumpr:nt $Rs32",
5387tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel {
5388let Inst{7-0} = 0b00000000;
5389let Inst{13-10} = 0b0000;
5390let Inst{31-21} = 0b01010011010;
5391let isPredicated = 1;
5392let isTerminator = 1;
5393let isIndirectBranch = 1;
5394let isBranch = 1;
5395let cofMax1 = 1;
5396let Defs = [PC];
5397let BaseOpcode = "J2_jumpr";
5398let InputType = "reg";
5399let isTaken = Inst{12};
5400}
5401def J2_jumprt_nopred_map : HInst<
5402(outs),
5403(ins PredRegs:$Pu4, IntRegs:$Rs32),
5404"if ($Pu4) jumpr $Rs32",
5405tc_2f573607, TypeMAPPING>, Requires<[HasV60]> {
5406let isPseudo = 1;
5407let isCodeGenOnly = 1;
5408}
5409def J2_jumprtnew : HInst<
5410(outs),
5411(ins PredRegs:$Pu4, IntRegs:$Rs32),
5412"if ($Pu4.new) jumpr:nt $Rs32",
5413tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5414let Inst{7-0} = 0b00000000;
5415let Inst{13-10} = 0b0010;
5416let Inst{31-21} = 0b01010011010;
5417let isPredicated = 1;
5418let isTerminator = 1;
5419let isIndirectBranch = 1;
5420let isBranch = 1;
5421let isPredicatedNew = 1;
5422let cofMax1 = 1;
5423let Defs = [PC];
5424let BaseOpcode = "J2_jumpr";
5425let InputType = "reg";
5426let isTaken = Inst{12};
5427}
5428def J2_jumprtnewpt : HInst<
5429(outs),
5430(ins PredRegs:$Pu4, IntRegs:$Rs32),
5431"if ($Pu4.new) jumpr:t $Rs32",
5432tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel {
5433let Inst{7-0} = 0b00000000;
5434let Inst{13-10} = 0b0110;
5435let Inst{31-21} = 0b01010011010;
5436let isPredicated = 1;
5437let isTerminator = 1;
5438let isIndirectBranch = 1;
5439let isBranch = 1;
5440let isPredicatedNew = 1;
5441let cofMax1 = 1;
5442let Defs = [PC];
5443let BaseOpcode = "J2_jumpr";
5444let InputType = "reg";
5445let isTaken = Inst{12};
5446}
5447def J2_jumprtpt : HInst<
5448(outs),
5449(ins PredRegs:$Pu4, IntRegs:$Rs32),
5450"if ($Pu4) jumpr:t $Rs32",
5451tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel {
5452let Inst{7-0} = 0b00000000;
5453let Inst{13-10} = 0b0100;
5454let Inst{31-21} = 0b01010011010;
5455let isPredicated = 1;
5456let isTerminator = 1;
5457let isIndirectBranch = 1;
5458let isBranch = 1;
5459let cofMax1 = 1;
5460let Defs = [PC];
5461let BaseOpcode = "J2_jumpr";
5462let InputType = "reg";
5463let isTaken = Inst{12};
5464}
5465def J2_jumprz : HInst<
5466(outs),
5467(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5468"if ($Rs32!=#0) jump:nt $Ii",
5469tc_57a55b54, TypeCR>, Enc_0fa531 {
5470let Inst{0-0} = 0b0;
5471let Inst{12-12} = 0b0;
5472let Inst{31-22} = 0b0110000100;
5473let isPredicated = 1;
5474let isTerminator = 1;
5475let isBranch = 1;
5476let isPredicatedNew = 1;
5477let cofRelax1 = 1;
5478let cofRelax2 = 1;
5479let cofMax1 = 1;
5480let Defs = [PC];
5481let isTaken = Inst{12};
5482}
5483def J2_jumprzpt : HInst<
5484(outs),
5485(ins IntRegs:$Rs32, b13_2Imm:$Ii),
5486"if ($Rs32!=#0) jump:t $Ii",
5487tc_57a55b54, TypeCR>, Enc_0fa531 {
5488let Inst{0-0} = 0b0;
5489let Inst{12-12} = 0b1;
5490let Inst{31-22} = 0b0110000100;
5491let isPredicated = 1;
5492let isTerminator = 1;
5493let isBranch = 1;
5494let isPredicatedNew = 1;
5495let cofRelax1 = 1;
5496let cofRelax2 = 1;
5497let cofMax1 = 1;
5498let Defs = [PC];
5499let isTaken = Inst{12};
5500}
5501def J2_jumpt : HInst<
5502(outs),
5503(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5504"if ($Pu4) jump:nt $Ii",
5505tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel {
5506let Inst{0-0} = 0b0;
5507let Inst{12-10} = 0b000;
5508let Inst{21-21} = 0b0;
5509let Inst{31-24} = 0b01011100;
5510let isPredicated = 1;
5511let isTerminator = 1;
5512let isBranch = 1;
5513let cofRelax1 = 1;
5514let cofRelax2 = 1;
5515let cofMax1 = 1;
5516let Defs = [PC];
5517let BaseOpcode = "J2_jump";
5518let InputType = "imm";
5519let isTaken = Inst{12};
5520let isExtendable = 1;
5521let opExtendable = 1;
5522let isExtentSigned = 1;
5523let opExtentBits = 17;
5524let opExtentAlign = 2;
5525}
5526def J2_jumpt_nopred_map : HInst<
5527(outs),
5528(ins PredRegs:$Pu4, b15_2Imm:$Ii),
5529"if ($Pu4) jump $Ii",
5530tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> {
5531let isPseudo = 1;
5532let isCodeGenOnly = 1;
5533}
5534def J2_jumptnew : HInst<
5535(outs),
5536(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5537"if ($Pu4.new) jump:nt $Ii",
5538tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5539let Inst{0-0} = 0b0;
5540let Inst{12-10} = 0b010;
5541let Inst{21-21} = 0b0;
5542let Inst{31-24} = 0b01011100;
5543let isPredicated = 1;
5544let isTerminator = 1;
5545let isBranch = 1;
5546let isPredicatedNew = 1;
5547let cofRelax1 = 1;
5548let cofRelax2 = 1;
5549let cofMax1 = 1;
5550let Defs = [PC];
5551let BaseOpcode = "J2_jump";
5552let InputType = "imm";
5553let isTaken = Inst{12};
5554let isExtendable = 1;
5555let opExtendable = 1;
5556let isExtentSigned = 1;
5557let opExtentBits = 17;
5558let opExtentAlign = 2;
5559}
5560def J2_jumptnewpt : HInst<
5561(outs),
5562(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5563"if ($Pu4.new) jump:t $Ii",
5564tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel {
5565let Inst{0-0} = 0b0;
5566let Inst{12-10} = 0b110;
5567let Inst{21-21} = 0b0;
5568let Inst{31-24} = 0b01011100;
5569let isPredicated = 1;
5570let isTerminator = 1;
5571let isBranch = 1;
5572let isPredicatedNew = 1;
5573let cofRelax1 = 1;
5574let cofRelax2 = 1;
5575let cofMax1 = 1;
5576let Defs = [PC];
5577let BaseOpcode = "J2_jump";
5578let InputType = "imm";
5579let isTaken = Inst{12};
5580let isExtendable = 1;
5581let opExtendable = 1;
5582let isExtentSigned = 1;
5583let opExtentBits = 17;
5584let opExtentAlign = 2;
5585}
5586def J2_jumptpt : HInst<
5587(outs),
5588(ins PredRegs:$Pu4, b30_2Imm:$Ii),
5589"if ($Pu4) jump:t $Ii",
5590tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel {
5591let Inst{0-0} = 0b0;
5592let Inst{12-10} = 0b100;
5593let Inst{21-21} = 0b0;
5594let Inst{31-24} = 0b01011100;
5595let isPredicated = 1;
5596let isTerminator = 1;
5597let isBranch = 1;
5598let cofRelax1 = 1;
5599let cofRelax2 = 1;
5600let cofMax1 = 1;
5601let Defs = [PC];
5602let BaseOpcode = "J2_jump";
5603let InputType = "imm";
5604let isTaken = Inst{12};
5605let isExtendable = 1;
5606let opExtendable = 1;
5607let isExtentSigned = 1;
5608let opExtentBits = 17;
5609let opExtentAlign = 2;
5610}
5611def J2_loop0i : HInst<
5612(outs),
5613(ins b30_2Imm:$Ii, u10_0Imm:$II),
5614"loop0($Ii,#$II)",
5615tc_1248597c, TypeCR>, Enc_4dc228 {
5616let Inst{2-2} = 0b0;
5617let Inst{13-13} = 0b0;
5618let Inst{31-21} = 0b01101001000;
5619let cofRelax1 = 1;
5620let cofRelax2 = 1;
5621let Defs = [LC0, SA0, USR];
5622let isExtendable = 1;
5623let opExtendable = 0;
5624let isExtentSigned = 1;
5625let opExtentBits = 9;
5626let opExtentAlign = 2;
5627}
5628def J2_loop0r : HInst<
5629(outs),
5630(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5631"loop0($Ii,$Rs32)",
5632tc_9406230a, TypeCR>, Enc_864a5a {
5633let Inst{2-0} = 0b000;
5634let Inst{7-5} = 0b000;
5635let Inst{13-13} = 0b0;
5636let Inst{31-21} = 0b01100000000;
5637let cofRelax1 = 1;
5638let cofRelax2 = 1;
5639let Defs = [LC0, SA0, USR];
5640let isExtendable = 1;
5641let opExtendable = 0;
5642let isExtentSigned = 1;
5643let opExtentBits = 9;
5644let opExtentAlign = 2;
5645}
5646def J2_loop1i : HInst<
5647(outs),
5648(ins b30_2Imm:$Ii, u10_0Imm:$II),
5649"loop1($Ii,#$II)",
5650tc_1248597c, TypeCR>, Enc_4dc228 {
5651let Inst{2-2} = 0b0;
5652let Inst{13-13} = 0b0;
5653let Inst{31-21} = 0b01101001001;
5654let cofRelax1 = 1;
5655let cofRelax2 = 1;
5656let Defs = [LC1, SA1];
5657let isExtendable = 1;
5658let opExtendable = 0;
5659let isExtentSigned = 1;
5660let opExtentBits = 9;
5661let opExtentAlign = 2;
5662}
5663def J2_loop1r : HInst<
5664(outs),
5665(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5666"loop1($Ii,$Rs32)",
5667tc_9406230a, TypeCR>, Enc_864a5a {
5668let Inst{2-0} = 0b000;
5669let Inst{7-5} = 0b000;
5670let Inst{13-13} = 0b0;
5671let Inst{31-21} = 0b01100000001;
5672let cofRelax1 = 1;
5673let cofRelax2 = 1;
5674let Defs = [LC1, SA1];
5675let isExtendable = 1;
5676let opExtendable = 0;
5677let isExtentSigned = 1;
5678let opExtentBits = 9;
5679let opExtentAlign = 2;
5680}
5681def J2_pause : HInst<
5682(outs),
5683(ins u8_0Imm:$Ii),
5684"pause(#$Ii)",
5685tc_d57d649c, TypeJ>, Enc_a51a9a {
5686let Inst{1-0} = 0b00;
5687let Inst{7-5} = 0b000;
5688let Inst{13-13} = 0b0;
5689let Inst{31-16} = 0b0101010001000000;
5690let isSolo = 1;
5691}
5692def J2_ploop1si : HInst<
5693(outs),
5694(ins b30_2Imm:$Ii, u10_0Imm:$II),
5695"p3 = sp1loop0($Ii,#$II)",
5696tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5697let Inst{2-2} = 0b0;
5698let Inst{13-13} = 0b0;
5699let Inst{31-21} = 0b01101001101;
5700let isPredicateLate = 1;
5701let cofRelax1 = 1;
5702let cofRelax2 = 1;
5703let Defs = [LC0, P3, SA0, USR];
5704let isExtendable = 1;
5705let opExtendable = 0;
5706let isExtentSigned = 1;
5707let opExtentBits = 9;
5708let opExtentAlign = 2;
5709}
5710def J2_ploop1sr : HInst<
5711(outs),
5712(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5713"p3 = sp1loop0($Ii,$Rs32)",
5714tc_6d861a95, TypeCR>, Enc_864a5a {
5715let Inst{2-0} = 0b000;
5716let Inst{7-5} = 0b000;
5717let Inst{13-13} = 0b0;
5718let Inst{31-21} = 0b01100000101;
5719let isPredicateLate = 1;
5720let cofRelax1 = 1;
5721let cofRelax2 = 1;
5722let Defs = [LC0, P3, SA0, USR];
5723let isExtendable = 1;
5724let opExtendable = 0;
5725let isExtentSigned = 1;
5726let opExtentBits = 9;
5727let opExtentAlign = 2;
5728}
5729def J2_ploop2si : HInst<
5730(outs),
5731(ins b30_2Imm:$Ii, u10_0Imm:$II),
5732"p3 = sp2loop0($Ii,#$II)",
5733tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5734let Inst{2-2} = 0b0;
5735let Inst{13-13} = 0b0;
5736let Inst{31-21} = 0b01101001110;
5737let isPredicateLate = 1;
5738let cofRelax1 = 1;
5739let cofRelax2 = 1;
5740let Defs = [LC0, P3, SA0, USR];
5741let isExtendable = 1;
5742let opExtendable = 0;
5743let isExtentSigned = 1;
5744let opExtentBits = 9;
5745let opExtentAlign = 2;
5746}
5747def J2_ploop2sr : HInst<
5748(outs),
5749(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5750"p3 = sp2loop0($Ii,$Rs32)",
5751tc_6d861a95, TypeCR>, Enc_864a5a {
5752let Inst{2-0} = 0b000;
5753let Inst{7-5} = 0b000;
5754let Inst{13-13} = 0b0;
5755let Inst{31-21} = 0b01100000110;
5756let isPredicateLate = 1;
5757let cofRelax1 = 1;
5758let cofRelax2 = 1;
5759let Defs = [LC0, P3, SA0, USR];
5760let isExtendable = 1;
5761let opExtendable = 0;
5762let isExtentSigned = 1;
5763let opExtentBits = 9;
5764let opExtentAlign = 2;
5765}
5766def J2_ploop3si : HInst<
5767(outs),
5768(ins b30_2Imm:$Ii, u10_0Imm:$II),
5769"p3 = sp3loop0($Ii,#$II)",
5770tc_4abdbdc6, TypeCR>, Enc_4dc228 {
5771let Inst{2-2} = 0b0;
5772let Inst{13-13} = 0b0;
5773let Inst{31-21} = 0b01101001111;
5774let isPredicateLate = 1;
5775let cofRelax1 = 1;
5776let cofRelax2 = 1;
5777let Defs = [LC0, P3, SA0, USR];
5778let isExtendable = 1;
5779let opExtendable = 0;
5780let isExtentSigned = 1;
5781let opExtentBits = 9;
5782let opExtentAlign = 2;
5783}
5784def J2_ploop3sr : HInst<
5785(outs),
5786(ins b30_2Imm:$Ii, IntRegs:$Rs32),
5787"p3 = sp3loop0($Ii,$Rs32)",
5788tc_6d861a95, TypeCR>, Enc_864a5a {
5789let Inst{2-0} = 0b000;
5790let Inst{7-5} = 0b000;
5791let Inst{13-13} = 0b0;
5792let Inst{31-21} = 0b01100000111;
5793let isPredicateLate = 1;
5794let cofRelax1 = 1;
5795let cofRelax2 = 1;
5796let Defs = [LC0, P3, SA0, USR];
5797let isExtendable = 1;
5798let opExtendable = 0;
5799let isExtentSigned = 1;
5800let opExtentBits = 9;
5801let opExtentAlign = 2;
5802}
5803def J2_trap0 : HInst<
5804(outs),
5805(ins u8_0Imm:$Ii),
5806"trap0(#$Ii)",
5807tc_45f9d1be, TypeJ>, Enc_a51a9a {
5808let Inst{1-0} = 0b00;
5809let Inst{7-5} = 0b000;
5810let Inst{13-13} = 0b0;
5811let Inst{31-16} = 0b0101010000000000;
5812let isSolo = 1;
5813let hasSideEffects = 1;
5814}
5815def J2_trap1 : HInst<
5816(outs IntRegs:$Rx32),
5817(ins IntRegs:$Rx32in, u8_0Imm:$Ii),
5818"trap1($Rx32,#$Ii)",
5819tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> {
5820let Inst{1-0} = 0b00;
5821let Inst{7-5} = 0b000;
5822let Inst{13-13} = 0b0;
5823let Inst{31-21} = 0b01010100100;
5824let hasNewValue = 1;
5825let opNewValue = 0;
5826let isSolo = 1;
5827let Uses = [GOSP];
5828let Defs = [GOSP, PC];
5829let hasSideEffects = 1;
5830let Constraints = "$Rx32 = $Rx32in";
5831}
5832def J2_trap1_noregmap : HInst<
5833(outs),
5834(ins u8_0Imm:$Ii),
5835"trap1(#$Ii)",
5836tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> {
5837let hasSideEffects = 1;
5838let isPseudo = 1;
5839let isCodeGenOnly = 1;
5840}
5841def J4_cmpeq_f_jumpnv_nt : HInst<
5842(outs),
5843(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5844"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
5845tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5846let Inst{0-0} = 0b0;
5847let Inst{13-13} = 0b0;
5848let Inst{19-19} = 0b0;
5849let Inst{31-22} = 0b0010000001;
5850let isPredicated = 1;
5851let isPredicatedFalse = 1;
5852let isTerminator = 1;
5853let isBranch = 1;
5854let isNewValue = 1;
5855let cofMax1 = 1;
5856let isRestrictNoSlot1Store = 1;
5857let Defs = [PC];
5858let BaseOpcode = "J4_cmpeqr";
5859let isTaken = Inst{13};
5860let isExtendable = 1;
5861let opExtendable = 2;
5862let isExtentSigned = 1;
5863let opExtentBits = 11;
5864let opExtentAlign = 2;
5865let opNewValue = 0;
5866}
5867def J4_cmpeq_f_jumpnv_t : HInst<
5868(outs),
5869(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
5870"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
5871tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
5872let Inst{0-0} = 0b0;
5873let Inst{13-13} = 0b1;
5874let Inst{19-19} = 0b0;
5875let Inst{31-22} = 0b0010000001;
5876let isPredicated = 1;
5877let isPredicatedFalse = 1;
5878let isTerminator = 1;
5879let isBranch = 1;
5880let isNewValue = 1;
5881let cofMax1 = 1;
5882let isRestrictNoSlot1Store = 1;
5883let Defs = [PC];
5884let BaseOpcode = "J4_cmpeqr";
5885let isTaken = Inst{13};
5886let isExtendable = 1;
5887let opExtendable = 2;
5888let isExtentSigned = 1;
5889let opExtentBits = 11;
5890let opExtentAlign = 2;
5891let opNewValue = 0;
5892}
5893def J4_cmpeq_fp0_jump_nt : HInst<
5894(outs),
5895(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5896"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
5897tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5898let Inst{0-0} = 0b0;
5899let Inst{13-12} = 0b00;
5900let Inst{31-22} = 0b0001010001;
5901let isPredicated = 1;
5902let isPredicatedFalse = 1;
5903let isTerminator = 1;
5904let isBranch = 1;
5905let isPredicatedNew = 1;
5906let cofRelax1 = 1;
5907let cofRelax2 = 1;
5908let cofMax1 = 1;
5909let Uses = [P0];
5910let Defs = [P0, PC];
5911let BaseOpcode = "J4_cmpeqp0";
5912let isTaken = Inst{13};
5913let isExtendable = 1;
5914let opExtendable = 2;
5915let isExtentSigned = 1;
5916let opExtentBits = 11;
5917let opExtentAlign = 2;
5918}
5919def J4_cmpeq_fp0_jump_t : HInst<
5920(outs),
5921(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5922"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
5923tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5924let Inst{0-0} = 0b0;
5925let Inst{13-12} = 0b10;
5926let Inst{31-22} = 0b0001010001;
5927let isPredicated = 1;
5928let isPredicatedFalse = 1;
5929let isTerminator = 1;
5930let isBranch = 1;
5931let isPredicatedNew = 1;
5932let cofRelax1 = 1;
5933let cofRelax2 = 1;
5934let cofMax1 = 1;
5935let Uses = [P0];
5936let Defs = [P0, PC];
5937let BaseOpcode = "J4_cmpeqp0";
5938let isTaken = Inst{13};
5939let isExtendable = 1;
5940let opExtendable = 2;
5941let isExtentSigned = 1;
5942let opExtentBits = 11;
5943let opExtentAlign = 2;
5944}
5945def J4_cmpeq_fp1_jump_nt : HInst<
5946(outs),
5947(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5948"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
5949tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5950let Inst{0-0} = 0b0;
5951let Inst{13-12} = 0b01;
5952let Inst{31-22} = 0b0001010001;
5953let isPredicated = 1;
5954let isPredicatedFalse = 1;
5955let isTerminator = 1;
5956let isBranch = 1;
5957let isPredicatedNew = 1;
5958let cofRelax1 = 1;
5959let cofRelax2 = 1;
5960let cofMax1 = 1;
5961let Uses = [P1];
5962let Defs = [P1, PC];
5963let BaseOpcode = "J4_cmpeqp1";
5964let isTaken = Inst{13};
5965let isExtendable = 1;
5966let opExtendable = 2;
5967let isExtentSigned = 1;
5968let opExtentBits = 11;
5969let opExtentAlign = 2;
5970}
5971def J4_cmpeq_fp1_jump_t : HInst<
5972(outs),
5973(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
5974"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
5975tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
5976let Inst{0-0} = 0b0;
5977let Inst{13-12} = 0b11;
5978let Inst{31-22} = 0b0001010001;
5979let isPredicated = 1;
5980let isPredicatedFalse = 1;
5981let isTerminator = 1;
5982let isBranch = 1;
5983let isPredicatedNew = 1;
5984let cofRelax1 = 1;
5985let cofRelax2 = 1;
5986let cofMax1 = 1;
5987let Uses = [P1];
5988let Defs = [P1, PC];
5989let BaseOpcode = "J4_cmpeqp1";
5990let isTaken = Inst{13};
5991let isExtendable = 1;
5992let opExtendable = 2;
5993let isExtentSigned = 1;
5994let opExtentBits = 11;
5995let opExtentAlign = 2;
5996}
5997def J4_cmpeq_t_jumpnv_nt : HInst<
5998(outs),
5999(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6000"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii",
6001tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6002let Inst{0-0} = 0b0;
6003let Inst{13-13} = 0b0;
6004let Inst{19-19} = 0b0;
6005let Inst{31-22} = 0b0010000000;
6006let isPredicated = 1;
6007let isTerminator = 1;
6008let isBranch = 1;
6009let isNewValue = 1;
6010let cofMax1 = 1;
6011let isRestrictNoSlot1Store = 1;
6012let Defs = [PC];
6013let BaseOpcode = "J4_cmpeqr";
6014let isTaken = Inst{13};
6015let isExtendable = 1;
6016let opExtendable = 2;
6017let isExtentSigned = 1;
6018let opExtentBits = 11;
6019let opExtentAlign = 2;
6020let opNewValue = 0;
6021}
6022def J4_cmpeq_t_jumpnv_t : HInst<
6023(outs),
6024(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6025"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii",
6026tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6027let Inst{0-0} = 0b0;
6028let Inst{13-13} = 0b1;
6029let Inst{19-19} = 0b0;
6030let Inst{31-22} = 0b0010000000;
6031let isPredicated = 1;
6032let isTerminator = 1;
6033let isBranch = 1;
6034let isNewValue = 1;
6035let cofMax1 = 1;
6036let isRestrictNoSlot1Store = 1;
6037let Defs = [PC];
6038let BaseOpcode = "J4_cmpeqr";
6039let isTaken = Inst{13};
6040let isExtendable = 1;
6041let opExtendable = 2;
6042let isExtentSigned = 1;
6043let opExtentBits = 11;
6044let opExtentAlign = 2;
6045let opNewValue = 0;
6046}
6047def J4_cmpeq_tp0_jump_nt : HInst<
6048(outs),
6049(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6050"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6051tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6052let Inst{0-0} = 0b0;
6053let Inst{13-12} = 0b00;
6054let Inst{31-22} = 0b0001010000;
6055let isPredicated = 1;
6056let isTerminator = 1;
6057let isBranch = 1;
6058let isPredicatedNew = 1;
6059let cofRelax1 = 1;
6060let cofRelax2 = 1;
6061let cofMax1 = 1;
6062let Uses = [P0];
6063let Defs = [P0, PC];
6064let BaseOpcode = "J4_cmpeqp0";
6065let isTaken = Inst{13};
6066let isExtendable = 1;
6067let opExtendable = 2;
6068let isExtentSigned = 1;
6069let opExtentBits = 11;
6070let opExtentAlign = 2;
6071}
6072def J4_cmpeq_tp0_jump_t : HInst<
6073(outs),
6074(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6075"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6076tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6077let Inst{0-0} = 0b0;
6078let Inst{13-12} = 0b10;
6079let Inst{31-22} = 0b0001010000;
6080let isPredicated = 1;
6081let isTerminator = 1;
6082let isBranch = 1;
6083let isPredicatedNew = 1;
6084let cofRelax1 = 1;
6085let cofRelax2 = 1;
6086let cofMax1 = 1;
6087let Uses = [P0];
6088let Defs = [P0, PC];
6089let BaseOpcode = "J4_cmpeqp0";
6090let isTaken = Inst{13};
6091let isExtendable = 1;
6092let opExtendable = 2;
6093let isExtentSigned = 1;
6094let opExtentBits = 11;
6095let opExtentAlign = 2;
6096}
6097def J4_cmpeq_tp1_jump_nt : HInst<
6098(outs),
6099(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6100"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
6101tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6102let Inst{0-0} = 0b0;
6103let Inst{13-12} = 0b01;
6104let Inst{31-22} = 0b0001010000;
6105let isPredicated = 1;
6106let isTerminator = 1;
6107let isBranch = 1;
6108let isPredicatedNew = 1;
6109let cofRelax1 = 1;
6110let cofRelax2 = 1;
6111let cofMax1 = 1;
6112let Uses = [P1];
6113let Defs = [P1, PC];
6114let BaseOpcode = "J4_cmpeqp1";
6115let isTaken = Inst{13};
6116let isExtendable = 1;
6117let opExtendable = 2;
6118let isExtentSigned = 1;
6119let opExtentBits = 11;
6120let opExtentAlign = 2;
6121}
6122def J4_cmpeq_tp1_jump_t : HInst<
6123(outs),
6124(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6125"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii",
6126tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6127let Inst{0-0} = 0b0;
6128let Inst{13-12} = 0b11;
6129let Inst{31-22} = 0b0001010000;
6130let isPredicated = 1;
6131let isTerminator = 1;
6132let isBranch = 1;
6133let isPredicatedNew = 1;
6134let cofRelax1 = 1;
6135let cofRelax2 = 1;
6136let cofMax1 = 1;
6137let Uses = [P1];
6138let Defs = [P1, PC];
6139let BaseOpcode = "J4_cmpeqp1";
6140let isTaken = Inst{13};
6141let isExtendable = 1;
6142let opExtendable = 2;
6143let isExtentSigned = 1;
6144let opExtentBits = 11;
6145let opExtentAlign = 2;
6146}
6147def J4_cmpeqi_f_jumpnv_nt : HInst<
6148(outs),
6149(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6150"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6151tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6152let Inst{0-0} = 0b0;
6153let Inst{13-13} = 0b0;
6154let Inst{19-19} = 0b0;
6155let Inst{31-22} = 0b0010010001;
6156let isPredicated = 1;
6157let isPredicatedFalse = 1;
6158let isTerminator = 1;
6159let isBranch = 1;
6160let isNewValue = 1;
6161let cofMax1 = 1;
6162let isRestrictNoSlot1Store = 1;
6163let Defs = [PC];
6164let BaseOpcode = "J4_cmpeqi";
6165let isTaken = Inst{13};
6166let isExtendable = 1;
6167let opExtendable = 2;
6168let isExtentSigned = 1;
6169let opExtentBits = 11;
6170let opExtentAlign = 2;
6171let opNewValue = 0;
6172}
6173def J4_cmpeqi_f_jumpnv_t : HInst<
6174(outs),
6175(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6176"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6177tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6178let Inst{0-0} = 0b0;
6179let Inst{13-13} = 0b1;
6180let Inst{19-19} = 0b0;
6181let Inst{31-22} = 0b0010010001;
6182let isPredicated = 1;
6183let isPredicatedFalse = 1;
6184let isTerminator = 1;
6185let isBranch = 1;
6186let isNewValue = 1;
6187let cofMax1 = 1;
6188let isRestrictNoSlot1Store = 1;
6189let Defs = [PC];
6190let BaseOpcode = "J4_cmpeqi";
6191let isTaken = Inst{13};
6192let isExtendable = 1;
6193let opExtendable = 2;
6194let isExtentSigned = 1;
6195let opExtentBits = 11;
6196let opExtentAlign = 2;
6197let opNewValue = 0;
6198}
6199def J4_cmpeqi_fp0_jump_nt : HInst<
6200(outs),
6201(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6202"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii",
6203tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6204let Inst{0-0} = 0b0;
6205let Inst{13-13} = 0b0;
6206let Inst{31-22} = 0b0001000001;
6207let isPredicated = 1;
6208let isPredicatedFalse = 1;
6209let isTerminator = 1;
6210let isBranch = 1;
6211let isPredicatedNew = 1;
6212let cofRelax1 = 1;
6213let cofRelax2 = 1;
6214let cofMax1 = 1;
6215let Uses = [P0];
6216let Defs = [P0, PC];
6217let BaseOpcode = "J4_cmpeqip0";
6218let isTaken = Inst{13};
6219let isExtendable = 1;
6220let opExtendable = 2;
6221let isExtentSigned = 1;
6222let opExtentBits = 11;
6223let opExtentAlign = 2;
6224}
6225def J4_cmpeqi_fp0_jump_t : HInst<
6226(outs),
6227(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6228"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii",
6229tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6230let Inst{0-0} = 0b0;
6231let Inst{13-13} = 0b1;
6232let Inst{31-22} = 0b0001000001;
6233let isPredicated = 1;
6234let isPredicatedFalse = 1;
6235let isTerminator = 1;
6236let isBranch = 1;
6237let isPredicatedNew = 1;
6238let cofRelax1 = 1;
6239let cofRelax2 = 1;
6240let cofMax1 = 1;
6241let Uses = [P0];
6242let Defs = [P0, PC];
6243let BaseOpcode = "J4_cmpeqip0";
6244let isTaken = Inst{13};
6245let isExtendable = 1;
6246let opExtendable = 2;
6247let isExtentSigned = 1;
6248let opExtentBits = 11;
6249let opExtentAlign = 2;
6250}
6251def J4_cmpeqi_fp1_jump_nt : HInst<
6252(outs),
6253(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6254"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii",
6255tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6256let Inst{0-0} = 0b0;
6257let Inst{13-13} = 0b0;
6258let Inst{31-22} = 0b0001001001;
6259let isPredicated = 1;
6260let isPredicatedFalse = 1;
6261let isTerminator = 1;
6262let isBranch = 1;
6263let isPredicatedNew = 1;
6264let cofRelax1 = 1;
6265let cofRelax2 = 1;
6266let cofMax1 = 1;
6267let Uses = [P1];
6268let Defs = [P1, PC];
6269let BaseOpcode = "J4_cmpeqip1";
6270let isTaken = Inst{13};
6271let isExtendable = 1;
6272let opExtendable = 2;
6273let isExtentSigned = 1;
6274let opExtentBits = 11;
6275let opExtentAlign = 2;
6276}
6277def J4_cmpeqi_fp1_jump_t : HInst<
6278(outs),
6279(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6280"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii",
6281tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6282let Inst{0-0} = 0b0;
6283let Inst{13-13} = 0b1;
6284let Inst{31-22} = 0b0001001001;
6285let isPredicated = 1;
6286let isPredicatedFalse = 1;
6287let isTerminator = 1;
6288let isBranch = 1;
6289let isPredicatedNew = 1;
6290let cofRelax1 = 1;
6291let cofRelax2 = 1;
6292let cofMax1 = 1;
6293let Uses = [P1];
6294let Defs = [P1, PC];
6295let BaseOpcode = "J4_cmpeqip1";
6296let isTaken = Inst{13};
6297let isExtendable = 1;
6298let opExtendable = 2;
6299let isExtentSigned = 1;
6300let opExtentBits = 11;
6301let opExtentAlign = 2;
6302}
6303def J4_cmpeqi_t_jumpnv_nt : HInst<
6304(outs),
6305(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6306"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii",
6307tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6308let Inst{0-0} = 0b0;
6309let Inst{13-13} = 0b0;
6310let Inst{19-19} = 0b0;
6311let Inst{31-22} = 0b0010010000;
6312let isPredicated = 1;
6313let isTerminator = 1;
6314let isBranch = 1;
6315let isNewValue = 1;
6316let cofMax1 = 1;
6317let isRestrictNoSlot1Store = 1;
6318let Defs = [PC];
6319let BaseOpcode = "J4_cmpeqi";
6320let isTaken = Inst{13};
6321let isExtendable = 1;
6322let opExtendable = 2;
6323let isExtentSigned = 1;
6324let opExtentBits = 11;
6325let opExtentAlign = 2;
6326let opNewValue = 0;
6327}
6328def J4_cmpeqi_t_jumpnv_t : HInst<
6329(outs),
6330(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
6331"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii",
6332tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
6333let Inst{0-0} = 0b0;
6334let Inst{13-13} = 0b1;
6335let Inst{19-19} = 0b0;
6336let Inst{31-22} = 0b0010010000;
6337let isPredicated = 1;
6338let isTerminator = 1;
6339let isBranch = 1;
6340let isNewValue = 1;
6341let cofMax1 = 1;
6342let isRestrictNoSlot1Store = 1;
6343let Defs = [PC];
6344let BaseOpcode = "J4_cmpeqi";
6345let isTaken = Inst{13};
6346let isExtendable = 1;
6347let opExtendable = 2;
6348let isExtentSigned = 1;
6349let opExtentBits = 11;
6350let opExtentAlign = 2;
6351let opNewValue = 0;
6352}
6353def J4_cmpeqi_tp0_jump_nt : HInst<
6354(outs),
6355(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6356"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii",
6357tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6358let Inst{0-0} = 0b0;
6359let Inst{13-13} = 0b0;
6360let Inst{31-22} = 0b0001000000;
6361let isPredicated = 1;
6362let isTerminator = 1;
6363let isBranch = 1;
6364let isPredicatedNew = 1;
6365let cofRelax1 = 1;
6366let cofRelax2 = 1;
6367let cofMax1 = 1;
6368let Uses = [P0];
6369let Defs = [P0, PC];
6370let BaseOpcode = "J4_cmpeqip0";
6371let isTaken = Inst{13};
6372let isExtendable = 1;
6373let opExtendable = 2;
6374let isExtentSigned = 1;
6375let opExtentBits = 11;
6376let opExtentAlign = 2;
6377}
6378def J4_cmpeqi_tp0_jump_t : HInst<
6379(outs),
6380(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6381"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii",
6382tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6383let Inst{0-0} = 0b0;
6384let Inst{13-13} = 0b1;
6385let Inst{31-22} = 0b0001000000;
6386let isPredicated = 1;
6387let isTerminator = 1;
6388let isBranch = 1;
6389let isPredicatedNew = 1;
6390let cofRelax1 = 1;
6391let cofRelax2 = 1;
6392let cofMax1 = 1;
6393let Uses = [P0];
6394let Defs = [P0, PC];
6395let BaseOpcode = "J4_cmpeqip0";
6396let isTaken = Inst{13};
6397let isExtendable = 1;
6398let opExtendable = 2;
6399let isExtentSigned = 1;
6400let opExtentBits = 11;
6401let opExtentAlign = 2;
6402}
6403def J4_cmpeqi_tp1_jump_nt : HInst<
6404(outs),
6405(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6406"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii",
6407tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6408let Inst{0-0} = 0b0;
6409let Inst{13-13} = 0b0;
6410let Inst{31-22} = 0b0001001000;
6411let isPredicated = 1;
6412let isTerminator = 1;
6413let isBranch = 1;
6414let isPredicatedNew = 1;
6415let cofRelax1 = 1;
6416let cofRelax2 = 1;
6417let cofMax1 = 1;
6418let Uses = [P1];
6419let Defs = [P1, PC];
6420let BaseOpcode = "J4_cmpeqip1";
6421let isTaken = Inst{13};
6422let isExtendable = 1;
6423let opExtendable = 2;
6424let isExtentSigned = 1;
6425let opExtentBits = 11;
6426let opExtentAlign = 2;
6427}
6428def J4_cmpeqi_tp1_jump_t : HInst<
6429(outs),
6430(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
6431"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii",
6432tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
6433let Inst{0-0} = 0b0;
6434let Inst{13-13} = 0b1;
6435let Inst{31-22} = 0b0001001000;
6436let isPredicated = 1;
6437let isTerminator = 1;
6438let isBranch = 1;
6439let isPredicatedNew = 1;
6440let cofRelax1 = 1;
6441let cofRelax2 = 1;
6442let cofMax1 = 1;
6443let Uses = [P1];
6444let Defs = [P1, PC];
6445let BaseOpcode = "J4_cmpeqip1";
6446let isTaken = Inst{13};
6447let isExtendable = 1;
6448let opExtendable = 2;
6449let isExtentSigned = 1;
6450let opExtentBits = 11;
6451let opExtentAlign = 2;
6452}
6453def J4_cmpeqn1_f_jumpnv_nt : HInst<
6454(outs),
6455(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6456"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6457tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel {
6458let Inst{0-0} = 0b0;
6459let Inst{13-8} = 0b000000;
6460let Inst{19-19} = 0b0;
6461let Inst{31-22} = 0b0010011001;
6462let isPredicated = 1;
6463let isPredicatedFalse = 1;
6464let isTerminator = 1;
6465let isBranch = 1;
6466let isNewValue = 1;
6467let cofMax1 = 1;
6468let isRestrictNoSlot1Store = 1;
6469let Defs = [PC];
6470let BaseOpcode = "J4_cmpeqn1r";
6471let isTaken = Inst{13};
6472let isExtendable = 1;
6473let opExtendable = 2;
6474let isExtentSigned = 1;
6475let opExtentBits = 11;
6476let opExtentAlign = 2;
6477let opNewValue = 0;
6478}
6479def J4_cmpeqn1_f_jumpnv_t : HInst<
6480(outs),
6481(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6482"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6483tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel {
6484let Inst{0-0} = 0b0;
6485let Inst{13-8} = 0b100000;
6486let Inst{19-19} = 0b0;
6487let Inst{31-22} = 0b0010011001;
6488let isPredicated = 1;
6489let isPredicatedFalse = 1;
6490let isTerminator = 1;
6491let isBranch = 1;
6492let isNewValue = 1;
6493let cofMax1 = 1;
6494let isRestrictNoSlot1Store = 1;
6495let Defs = [PC];
6496let BaseOpcode = "J4_cmpeqn1r";
6497let isTaken = Inst{13};
6498let isExtendable = 1;
6499let opExtendable = 2;
6500let isExtentSigned = 1;
6501let opExtentBits = 11;
6502let opExtentAlign = 2;
6503let opNewValue = 0;
6504}
6505def J4_cmpeqn1_fp0_jump_nt : HInst<
6506(outs),
6507(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6508"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
6509tc_24f426ab, TypeCJ>, Enc_1de724, PredRel {
6510let Inst{0-0} = 0b0;
6511let Inst{13-8} = 0b000000;
6512let Inst{31-22} = 0b0001000111;
6513let isPredicated = 1;
6514let isPredicatedFalse = 1;
6515let isTerminator = 1;
6516let isBranch = 1;
6517let isPredicatedNew = 1;
6518let cofRelax1 = 1;
6519let cofRelax2 = 1;
6520let cofMax1 = 1;
6521let Uses = [P0];
6522let Defs = [P0, PC];
6523let BaseOpcode = "J4_cmpeqn1p0";
6524let isTaken = Inst{13};
6525let isExtendable = 1;
6526let opExtendable = 2;
6527let isExtentSigned = 1;
6528let opExtentBits = 11;
6529let opExtentAlign = 2;
6530}
6531def J4_cmpeqn1_fp0_jump_t : HInst<
6532(outs),
6533(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6534"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii",
6535tc_24f426ab, TypeCJ>, Enc_14640c, PredRel {
6536let Inst{0-0} = 0b0;
6537let Inst{13-8} = 0b100000;
6538let Inst{31-22} = 0b0001000111;
6539let isPredicated = 1;
6540let isPredicatedFalse = 1;
6541let isTerminator = 1;
6542let isBranch = 1;
6543let isPredicatedNew = 1;
6544let cofRelax1 = 1;
6545let cofRelax2 = 1;
6546let cofMax1 = 1;
6547let Uses = [P0];
6548let Defs = [P0, PC];
6549let BaseOpcode = "J4_cmpeqn1p0";
6550let isTaken = Inst{13};
6551let isExtendable = 1;
6552let opExtendable = 2;
6553let isExtentSigned = 1;
6554let opExtentBits = 11;
6555let opExtentAlign = 2;
6556}
6557def J4_cmpeqn1_fp1_jump_nt : HInst<
6558(outs),
6559(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6560"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
6561tc_24f426ab, TypeCJ>, Enc_668704, PredRel {
6562let Inst{0-0} = 0b0;
6563let Inst{13-8} = 0b000000;
6564let Inst{31-22} = 0b0001001111;
6565let isPredicated = 1;
6566let isPredicatedFalse = 1;
6567let isTerminator = 1;
6568let isBranch = 1;
6569let isPredicatedNew = 1;
6570let cofRelax1 = 1;
6571let cofRelax2 = 1;
6572let cofMax1 = 1;
6573let Uses = [P1];
6574let Defs = [P1, PC];
6575let BaseOpcode = "J4_cmpeqn1p1";
6576let isTaken = Inst{13};
6577let isExtendable = 1;
6578let opExtendable = 2;
6579let isExtentSigned = 1;
6580let opExtentBits = 11;
6581let opExtentAlign = 2;
6582}
6583def J4_cmpeqn1_fp1_jump_t : HInst<
6584(outs),
6585(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6586"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii",
6587tc_24f426ab, TypeCJ>, Enc_800e04, PredRel {
6588let Inst{0-0} = 0b0;
6589let Inst{13-8} = 0b100000;
6590let Inst{31-22} = 0b0001001111;
6591let isPredicated = 1;
6592let isPredicatedFalse = 1;
6593let isTerminator = 1;
6594let isBranch = 1;
6595let isPredicatedNew = 1;
6596let cofRelax1 = 1;
6597let cofRelax2 = 1;
6598let cofMax1 = 1;
6599let Uses = [P1];
6600let Defs = [P1, PC];
6601let BaseOpcode = "J4_cmpeqn1p1";
6602let isTaken = Inst{13};
6603let isExtendable = 1;
6604let opExtendable = 2;
6605let isExtentSigned = 1;
6606let opExtentBits = 11;
6607let opExtentAlign = 2;
6608}
6609def J4_cmpeqn1_t_jumpnv_nt : HInst<
6610(outs),
6611(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6612"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii",
6613tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel {
6614let Inst{0-0} = 0b0;
6615let Inst{13-8} = 0b000000;
6616let Inst{19-19} = 0b0;
6617let Inst{31-22} = 0b0010011000;
6618let isPredicated = 1;
6619let isTerminator = 1;
6620let isBranch = 1;
6621let isNewValue = 1;
6622let cofMax1 = 1;
6623let isRestrictNoSlot1Store = 1;
6624let Defs = [PC];
6625let BaseOpcode = "J4_cmpeqn1r";
6626let isTaken = Inst{13};
6627let isExtendable = 1;
6628let opExtendable = 2;
6629let isExtentSigned = 1;
6630let opExtentBits = 11;
6631let opExtentAlign = 2;
6632let opNewValue = 0;
6633}
6634def J4_cmpeqn1_t_jumpnv_t : HInst<
6635(outs),
6636(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
6637"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii",
6638tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel {
6639let Inst{0-0} = 0b0;
6640let Inst{13-8} = 0b100000;
6641let Inst{19-19} = 0b0;
6642let Inst{31-22} = 0b0010011000;
6643let isPredicated = 1;
6644let isTerminator = 1;
6645let isBranch = 1;
6646let isNewValue = 1;
6647let cofMax1 = 1;
6648let isRestrictNoSlot1Store = 1;
6649let Defs = [PC];
6650let BaseOpcode = "J4_cmpeqn1r";
6651let isTaken = Inst{13};
6652let isExtendable = 1;
6653let opExtendable = 2;
6654let isExtentSigned = 1;
6655let opExtentBits = 11;
6656let opExtentAlign = 2;
6657let opNewValue = 0;
6658}
6659def J4_cmpeqn1_tp0_jump_nt : HInst<
6660(outs),
6661(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6662"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii",
6663tc_24f426ab, TypeCJ>, Enc_405228, PredRel {
6664let Inst{0-0} = 0b0;
6665let Inst{13-8} = 0b000000;
6666let Inst{31-22} = 0b0001000110;
6667let isPredicated = 1;
6668let isTerminator = 1;
6669let isBranch = 1;
6670let isPredicatedNew = 1;
6671let cofRelax1 = 1;
6672let cofRelax2 = 1;
6673let cofMax1 = 1;
6674let Uses = [P0];
6675let Defs = [P0, PC];
6676let BaseOpcode = "J4_cmpeqn1p0";
6677let isTaken = Inst{13};
6678let isExtendable = 1;
6679let opExtendable = 2;
6680let isExtentSigned = 1;
6681let opExtentBits = 11;
6682let opExtentAlign = 2;
6683}
6684def J4_cmpeqn1_tp0_jump_t : HInst<
6685(outs),
6686(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6687"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii",
6688tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel {
6689let Inst{0-0} = 0b0;
6690let Inst{13-8} = 0b100000;
6691let Inst{31-22} = 0b0001000110;
6692let isPredicated = 1;
6693let isTerminator = 1;
6694let isBranch = 1;
6695let isPredicatedNew = 1;
6696let cofRelax1 = 1;
6697let cofRelax2 = 1;
6698let cofMax1 = 1;
6699let Uses = [P0];
6700let Defs = [P0, PC];
6701let BaseOpcode = "J4_cmpeqn1p0";
6702let isTaken = Inst{13};
6703let isExtendable = 1;
6704let opExtendable = 2;
6705let isExtentSigned = 1;
6706let opExtentBits = 11;
6707let opExtentAlign = 2;
6708}
6709def J4_cmpeqn1_tp1_jump_nt : HInst<
6710(outs),
6711(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6712"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii",
6713tc_24f426ab, TypeCJ>, Enc_736575, PredRel {
6714let Inst{0-0} = 0b0;
6715let Inst{13-8} = 0b000000;
6716let Inst{31-22} = 0b0001001110;
6717let isPredicated = 1;
6718let isTerminator = 1;
6719let isBranch = 1;
6720let isPredicatedNew = 1;
6721let cofRelax1 = 1;
6722let cofRelax2 = 1;
6723let cofMax1 = 1;
6724let Uses = [P1];
6725let Defs = [P1, PC];
6726let BaseOpcode = "J4_cmpeqn1p1";
6727let isTaken = Inst{13};
6728let isExtendable = 1;
6729let opExtendable = 2;
6730let isExtentSigned = 1;
6731let opExtentBits = 11;
6732let opExtentAlign = 2;
6733}
6734def J4_cmpeqn1_tp1_jump_t : HInst<
6735(outs),
6736(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
6737"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii",
6738tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel {
6739let Inst{0-0} = 0b0;
6740let Inst{13-8} = 0b100000;
6741let Inst{31-22} = 0b0001001110;
6742let isPredicated = 1;
6743let isTerminator = 1;
6744let isBranch = 1;
6745let isPredicatedNew = 1;
6746let cofRelax1 = 1;
6747let cofRelax2 = 1;
6748let cofMax1 = 1;
6749let Uses = [P1];
6750let Defs = [P1, PC];
6751let BaseOpcode = "J4_cmpeqn1p1";
6752let isTaken = Inst{13};
6753let isExtendable = 1;
6754let opExtendable = 2;
6755let isExtentSigned = 1;
6756let opExtentBits = 11;
6757let opExtentAlign = 2;
6758}
6759def J4_cmpgt_f_jumpnv_nt : HInst<
6760(outs),
6761(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6762"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6763tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6764let Inst{0-0} = 0b0;
6765let Inst{13-13} = 0b0;
6766let Inst{19-19} = 0b0;
6767let Inst{31-22} = 0b0010000011;
6768let isPredicated = 1;
6769let isPredicatedFalse = 1;
6770let isTerminator = 1;
6771let isBranch = 1;
6772let isNewValue = 1;
6773let cofMax1 = 1;
6774let isRestrictNoSlot1Store = 1;
6775let Defs = [PC];
6776let BaseOpcode = "J4_cmpgtr";
6777let isTaken = Inst{13};
6778let isExtendable = 1;
6779let opExtendable = 2;
6780let isExtentSigned = 1;
6781let opExtentBits = 11;
6782let opExtentAlign = 2;
6783let opNewValue = 0;
6784}
6785def J4_cmpgt_f_jumpnv_t : HInst<
6786(outs),
6787(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6788"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6789tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6790let Inst{0-0} = 0b0;
6791let Inst{13-13} = 0b1;
6792let Inst{19-19} = 0b0;
6793let Inst{31-22} = 0b0010000011;
6794let isPredicated = 1;
6795let isPredicatedFalse = 1;
6796let isTerminator = 1;
6797let isBranch = 1;
6798let isNewValue = 1;
6799let cofMax1 = 1;
6800let isRestrictNoSlot1Store = 1;
6801let Defs = [PC];
6802let BaseOpcode = "J4_cmpgtr";
6803let isTaken = Inst{13};
6804let isExtendable = 1;
6805let opExtendable = 2;
6806let isExtentSigned = 1;
6807let opExtentBits = 11;
6808let opExtentAlign = 2;
6809let opNewValue = 0;
6810}
6811def J4_cmpgt_fp0_jump_nt : HInst<
6812(outs),
6813(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6814"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
6815tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6816let Inst{0-0} = 0b0;
6817let Inst{13-12} = 0b00;
6818let Inst{31-22} = 0b0001010011;
6819let isPredicated = 1;
6820let isPredicatedFalse = 1;
6821let isTerminator = 1;
6822let isBranch = 1;
6823let isPredicatedNew = 1;
6824let cofRelax1 = 1;
6825let cofRelax2 = 1;
6826let cofMax1 = 1;
6827let Uses = [P0];
6828let Defs = [P0, PC];
6829let BaseOpcode = "J4_cmpgtp0";
6830let isTaken = Inst{13};
6831let isExtendable = 1;
6832let opExtendable = 2;
6833let isExtentSigned = 1;
6834let opExtentBits = 11;
6835let opExtentAlign = 2;
6836}
6837def J4_cmpgt_fp0_jump_t : HInst<
6838(outs),
6839(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6840"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
6841tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6842let Inst{0-0} = 0b0;
6843let Inst{13-12} = 0b10;
6844let Inst{31-22} = 0b0001010011;
6845let isPredicated = 1;
6846let isPredicatedFalse = 1;
6847let isTerminator = 1;
6848let isBranch = 1;
6849let isPredicatedNew = 1;
6850let cofRelax1 = 1;
6851let cofRelax2 = 1;
6852let cofMax1 = 1;
6853let Uses = [P0];
6854let Defs = [P0, PC];
6855let BaseOpcode = "J4_cmpgtp0";
6856let isTaken = Inst{13};
6857let isExtendable = 1;
6858let opExtendable = 2;
6859let isExtentSigned = 1;
6860let opExtentBits = 11;
6861let opExtentAlign = 2;
6862}
6863def J4_cmpgt_fp1_jump_nt : HInst<
6864(outs),
6865(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6866"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
6867tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6868let Inst{0-0} = 0b0;
6869let Inst{13-12} = 0b01;
6870let Inst{31-22} = 0b0001010011;
6871let isPredicated = 1;
6872let isPredicatedFalse = 1;
6873let isTerminator = 1;
6874let isBranch = 1;
6875let isPredicatedNew = 1;
6876let cofRelax1 = 1;
6877let cofRelax2 = 1;
6878let cofMax1 = 1;
6879let Uses = [P1];
6880let Defs = [P1, PC];
6881let BaseOpcode = "J4_cmpgtp1";
6882let isTaken = Inst{13};
6883let isExtendable = 1;
6884let opExtendable = 2;
6885let isExtentSigned = 1;
6886let opExtentBits = 11;
6887let opExtentAlign = 2;
6888}
6889def J4_cmpgt_fp1_jump_t : HInst<
6890(outs),
6891(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6892"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
6893tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6894let Inst{0-0} = 0b0;
6895let Inst{13-12} = 0b11;
6896let Inst{31-22} = 0b0001010011;
6897let isPredicated = 1;
6898let isPredicatedFalse = 1;
6899let isTerminator = 1;
6900let isBranch = 1;
6901let isPredicatedNew = 1;
6902let cofRelax1 = 1;
6903let cofRelax2 = 1;
6904let cofMax1 = 1;
6905let Uses = [P1];
6906let Defs = [P1, PC];
6907let BaseOpcode = "J4_cmpgtp1";
6908let isTaken = Inst{13};
6909let isExtendable = 1;
6910let opExtendable = 2;
6911let isExtentSigned = 1;
6912let opExtentBits = 11;
6913let opExtentAlign = 2;
6914}
6915def J4_cmpgt_t_jumpnv_nt : HInst<
6916(outs),
6917(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6918"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii",
6919tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6920let Inst{0-0} = 0b0;
6921let Inst{13-13} = 0b0;
6922let Inst{19-19} = 0b0;
6923let Inst{31-22} = 0b0010000010;
6924let isPredicated = 1;
6925let isTerminator = 1;
6926let isBranch = 1;
6927let isNewValue = 1;
6928let cofMax1 = 1;
6929let isRestrictNoSlot1Store = 1;
6930let Defs = [PC];
6931let BaseOpcode = "J4_cmpgtr";
6932let isTaken = Inst{13};
6933let isExtendable = 1;
6934let opExtendable = 2;
6935let isExtentSigned = 1;
6936let opExtentBits = 11;
6937let opExtentAlign = 2;
6938let opNewValue = 0;
6939}
6940def J4_cmpgt_t_jumpnv_t : HInst<
6941(outs),
6942(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
6943"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii",
6944tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
6945let Inst{0-0} = 0b0;
6946let Inst{13-13} = 0b1;
6947let Inst{19-19} = 0b0;
6948let Inst{31-22} = 0b0010000010;
6949let isPredicated = 1;
6950let isTerminator = 1;
6951let isBranch = 1;
6952let isNewValue = 1;
6953let cofMax1 = 1;
6954let isRestrictNoSlot1Store = 1;
6955let Defs = [PC];
6956let BaseOpcode = "J4_cmpgtr";
6957let isTaken = Inst{13};
6958let isExtendable = 1;
6959let opExtendable = 2;
6960let isExtentSigned = 1;
6961let opExtentBits = 11;
6962let opExtentAlign = 2;
6963let opNewValue = 0;
6964}
6965def J4_cmpgt_tp0_jump_nt : HInst<
6966(outs),
6967(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6968"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
6969tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6970let Inst{0-0} = 0b0;
6971let Inst{13-12} = 0b00;
6972let Inst{31-22} = 0b0001010010;
6973let isPredicated = 1;
6974let isTerminator = 1;
6975let isBranch = 1;
6976let isPredicatedNew = 1;
6977let cofRelax1 = 1;
6978let cofRelax2 = 1;
6979let cofMax1 = 1;
6980let Uses = [P0];
6981let Defs = [P0, PC];
6982let BaseOpcode = "J4_cmpgtp0";
6983let isTaken = Inst{13};
6984let isExtendable = 1;
6985let opExtendable = 2;
6986let isExtentSigned = 1;
6987let opExtentBits = 11;
6988let opExtentAlign = 2;
6989}
6990def J4_cmpgt_tp0_jump_t : HInst<
6991(outs),
6992(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
6993"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii",
6994tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
6995let Inst{0-0} = 0b0;
6996let Inst{13-12} = 0b10;
6997let Inst{31-22} = 0b0001010010;
6998let isPredicated = 1;
6999let isTerminator = 1;
7000let isBranch = 1;
7001let isPredicatedNew = 1;
7002let cofRelax1 = 1;
7003let cofRelax2 = 1;
7004let cofMax1 = 1;
7005let Uses = [P0];
7006let Defs = [P0, PC];
7007let BaseOpcode = "J4_cmpgtp0";
7008let isTaken = Inst{13};
7009let isExtendable = 1;
7010let opExtendable = 2;
7011let isExtentSigned = 1;
7012let opExtentBits = 11;
7013let opExtentAlign = 2;
7014}
7015def J4_cmpgt_tp1_jump_nt : HInst<
7016(outs),
7017(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7018"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7019tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7020let Inst{0-0} = 0b0;
7021let Inst{13-12} = 0b01;
7022let Inst{31-22} = 0b0001010010;
7023let isPredicated = 1;
7024let isTerminator = 1;
7025let isBranch = 1;
7026let isPredicatedNew = 1;
7027let cofRelax1 = 1;
7028let cofRelax2 = 1;
7029let cofMax1 = 1;
7030let Uses = [P1];
7031let Defs = [P1, PC];
7032let BaseOpcode = "J4_cmpgtp1";
7033let isTaken = Inst{13};
7034let isExtendable = 1;
7035let opExtendable = 2;
7036let isExtentSigned = 1;
7037let opExtentBits = 11;
7038let opExtentAlign = 2;
7039}
7040def J4_cmpgt_tp1_jump_t : HInst<
7041(outs),
7042(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7043"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7044tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7045let Inst{0-0} = 0b0;
7046let Inst{13-12} = 0b11;
7047let Inst{31-22} = 0b0001010010;
7048let isPredicated = 1;
7049let isTerminator = 1;
7050let isBranch = 1;
7051let isPredicatedNew = 1;
7052let cofRelax1 = 1;
7053let cofRelax2 = 1;
7054let cofMax1 = 1;
7055let Uses = [P1];
7056let Defs = [P1, PC];
7057let BaseOpcode = "J4_cmpgtp1";
7058let isTaken = Inst{13};
7059let isExtendable = 1;
7060let opExtendable = 2;
7061let isExtentSigned = 1;
7062let opExtentBits = 11;
7063let opExtentAlign = 2;
7064}
7065def J4_cmpgti_f_jumpnv_nt : HInst<
7066(outs),
7067(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7068"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7069tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7070let Inst{0-0} = 0b0;
7071let Inst{13-13} = 0b0;
7072let Inst{19-19} = 0b0;
7073let Inst{31-22} = 0b0010010011;
7074let isPredicated = 1;
7075let isPredicatedFalse = 1;
7076let isTerminator = 1;
7077let isBranch = 1;
7078let isNewValue = 1;
7079let cofMax1 = 1;
7080let isRestrictNoSlot1Store = 1;
7081let Defs = [PC];
7082let BaseOpcode = "J4_cmpgtir";
7083let isTaken = Inst{13};
7084let isExtendable = 1;
7085let opExtendable = 2;
7086let isExtentSigned = 1;
7087let opExtentBits = 11;
7088let opExtentAlign = 2;
7089let opNewValue = 0;
7090}
7091def J4_cmpgti_f_jumpnv_t : HInst<
7092(outs),
7093(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7094"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7095tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7096let Inst{0-0} = 0b0;
7097let Inst{13-13} = 0b1;
7098let Inst{19-19} = 0b0;
7099let Inst{31-22} = 0b0010010011;
7100let isPredicated = 1;
7101let isPredicatedFalse = 1;
7102let isTerminator = 1;
7103let isBranch = 1;
7104let isNewValue = 1;
7105let cofMax1 = 1;
7106let isRestrictNoSlot1Store = 1;
7107let Defs = [PC];
7108let BaseOpcode = "J4_cmpgtir";
7109let isTaken = Inst{13};
7110let isExtendable = 1;
7111let opExtendable = 2;
7112let isExtentSigned = 1;
7113let opExtentBits = 11;
7114let opExtentAlign = 2;
7115let opNewValue = 0;
7116}
7117def J4_cmpgti_fp0_jump_nt : HInst<
7118(outs),
7119(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7120"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii",
7121tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7122let Inst{0-0} = 0b0;
7123let Inst{13-13} = 0b0;
7124let Inst{31-22} = 0b0001000011;
7125let isPredicated = 1;
7126let isPredicatedFalse = 1;
7127let isTerminator = 1;
7128let isBranch = 1;
7129let isPredicatedNew = 1;
7130let cofRelax1 = 1;
7131let cofRelax2 = 1;
7132let cofMax1 = 1;
7133let Uses = [P0];
7134let Defs = [P0, PC];
7135let BaseOpcode = "J4_cmpgtip0";
7136let isTaken = Inst{13};
7137let isExtendable = 1;
7138let opExtendable = 2;
7139let isExtentSigned = 1;
7140let opExtentBits = 11;
7141let opExtentAlign = 2;
7142}
7143def J4_cmpgti_fp0_jump_t : HInst<
7144(outs),
7145(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7146"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii",
7147tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7148let Inst{0-0} = 0b0;
7149let Inst{13-13} = 0b1;
7150let Inst{31-22} = 0b0001000011;
7151let isPredicated = 1;
7152let isPredicatedFalse = 1;
7153let isTerminator = 1;
7154let isBranch = 1;
7155let isPredicatedNew = 1;
7156let cofRelax1 = 1;
7157let cofRelax2 = 1;
7158let cofMax1 = 1;
7159let Uses = [P0];
7160let Defs = [P0, PC];
7161let BaseOpcode = "J4_cmpgtip0";
7162let isTaken = Inst{13};
7163let isExtendable = 1;
7164let opExtendable = 2;
7165let isExtentSigned = 1;
7166let opExtentBits = 11;
7167let opExtentAlign = 2;
7168}
7169def J4_cmpgti_fp1_jump_nt : HInst<
7170(outs),
7171(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7172"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii",
7173tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7174let Inst{0-0} = 0b0;
7175let Inst{13-13} = 0b0;
7176let Inst{31-22} = 0b0001001011;
7177let isPredicated = 1;
7178let isPredicatedFalse = 1;
7179let isTerminator = 1;
7180let isBranch = 1;
7181let isPredicatedNew = 1;
7182let cofRelax1 = 1;
7183let cofRelax2 = 1;
7184let cofMax1 = 1;
7185let Uses = [P1];
7186let Defs = [P1, PC];
7187let BaseOpcode = "J4_cmpgtip1";
7188let isTaken = Inst{13};
7189let isExtendable = 1;
7190let opExtendable = 2;
7191let isExtentSigned = 1;
7192let opExtentBits = 11;
7193let opExtentAlign = 2;
7194}
7195def J4_cmpgti_fp1_jump_t : HInst<
7196(outs),
7197(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7198"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii",
7199tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7200let Inst{0-0} = 0b0;
7201let Inst{13-13} = 0b1;
7202let Inst{31-22} = 0b0001001011;
7203let isPredicated = 1;
7204let isPredicatedFalse = 1;
7205let isTerminator = 1;
7206let isBranch = 1;
7207let isPredicatedNew = 1;
7208let cofRelax1 = 1;
7209let cofRelax2 = 1;
7210let cofMax1 = 1;
7211let Uses = [P1];
7212let Defs = [P1, PC];
7213let BaseOpcode = "J4_cmpgtip1";
7214let isTaken = Inst{13};
7215let isExtendable = 1;
7216let opExtendable = 2;
7217let isExtentSigned = 1;
7218let opExtentBits = 11;
7219let opExtentAlign = 2;
7220}
7221def J4_cmpgti_t_jumpnv_nt : HInst<
7222(outs),
7223(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7224"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii",
7225tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7226let Inst{0-0} = 0b0;
7227let Inst{13-13} = 0b0;
7228let Inst{19-19} = 0b0;
7229let Inst{31-22} = 0b0010010010;
7230let isPredicated = 1;
7231let isTerminator = 1;
7232let isBranch = 1;
7233let isNewValue = 1;
7234let cofMax1 = 1;
7235let isRestrictNoSlot1Store = 1;
7236let Defs = [PC];
7237let BaseOpcode = "J4_cmpgtir";
7238let isTaken = Inst{13};
7239let isExtendable = 1;
7240let opExtendable = 2;
7241let isExtentSigned = 1;
7242let opExtentBits = 11;
7243let opExtentAlign = 2;
7244let opNewValue = 0;
7245}
7246def J4_cmpgti_t_jumpnv_t : HInst<
7247(outs),
7248(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7249"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii",
7250tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7251let Inst{0-0} = 0b0;
7252let Inst{13-13} = 0b1;
7253let Inst{19-19} = 0b0;
7254let Inst{31-22} = 0b0010010010;
7255let isPredicated = 1;
7256let isTerminator = 1;
7257let isBranch = 1;
7258let isNewValue = 1;
7259let cofMax1 = 1;
7260let isRestrictNoSlot1Store = 1;
7261let Defs = [PC];
7262let BaseOpcode = "J4_cmpgtir";
7263let isTaken = Inst{13};
7264let isExtendable = 1;
7265let opExtendable = 2;
7266let isExtentSigned = 1;
7267let opExtentBits = 11;
7268let opExtentAlign = 2;
7269let opNewValue = 0;
7270}
7271def J4_cmpgti_tp0_jump_nt : HInst<
7272(outs),
7273(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7274"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii",
7275tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7276let Inst{0-0} = 0b0;
7277let Inst{13-13} = 0b0;
7278let Inst{31-22} = 0b0001000010;
7279let isPredicated = 1;
7280let isTerminator = 1;
7281let isBranch = 1;
7282let isPredicatedNew = 1;
7283let cofRelax1 = 1;
7284let cofRelax2 = 1;
7285let cofMax1 = 1;
7286let Uses = [P0];
7287let Defs = [P0, PC];
7288let BaseOpcode = "J4_cmpgtip0";
7289let isTaken = Inst{13};
7290let isExtendable = 1;
7291let opExtendable = 2;
7292let isExtentSigned = 1;
7293let opExtentBits = 11;
7294let opExtentAlign = 2;
7295}
7296def J4_cmpgti_tp0_jump_t : HInst<
7297(outs),
7298(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7299"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii",
7300tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7301let Inst{0-0} = 0b0;
7302let Inst{13-13} = 0b1;
7303let Inst{31-22} = 0b0001000010;
7304let isPredicated = 1;
7305let isTerminator = 1;
7306let isBranch = 1;
7307let isPredicatedNew = 1;
7308let cofRelax1 = 1;
7309let cofRelax2 = 1;
7310let cofMax1 = 1;
7311let Uses = [P0];
7312let Defs = [P0, PC];
7313let BaseOpcode = "J4_cmpgtip0";
7314let isTaken = Inst{13};
7315let isExtendable = 1;
7316let opExtendable = 2;
7317let isExtentSigned = 1;
7318let opExtentBits = 11;
7319let opExtentAlign = 2;
7320}
7321def J4_cmpgti_tp1_jump_nt : HInst<
7322(outs),
7323(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7324"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii",
7325tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7326let Inst{0-0} = 0b0;
7327let Inst{13-13} = 0b0;
7328let Inst{31-22} = 0b0001001010;
7329let isPredicated = 1;
7330let isTerminator = 1;
7331let isBranch = 1;
7332let isPredicatedNew = 1;
7333let cofRelax1 = 1;
7334let cofRelax2 = 1;
7335let cofMax1 = 1;
7336let Uses = [P1];
7337let Defs = [P1, PC];
7338let BaseOpcode = "J4_cmpgtip1";
7339let isTaken = Inst{13};
7340let isExtendable = 1;
7341let opExtendable = 2;
7342let isExtentSigned = 1;
7343let opExtentBits = 11;
7344let opExtentAlign = 2;
7345}
7346def J4_cmpgti_tp1_jump_t : HInst<
7347(outs),
7348(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
7349"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii",
7350tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
7351let Inst{0-0} = 0b0;
7352let Inst{13-13} = 0b1;
7353let Inst{31-22} = 0b0001001010;
7354let isPredicated = 1;
7355let isTerminator = 1;
7356let isBranch = 1;
7357let isPredicatedNew = 1;
7358let cofRelax1 = 1;
7359let cofRelax2 = 1;
7360let cofMax1 = 1;
7361let Uses = [P1];
7362let Defs = [P1, PC];
7363let BaseOpcode = "J4_cmpgtip1";
7364let isTaken = Inst{13};
7365let isExtendable = 1;
7366let opExtendable = 2;
7367let isExtentSigned = 1;
7368let opExtentBits = 11;
7369let opExtentAlign = 2;
7370}
7371def J4_cmpgtn1_f_jumpnv_nt : HInst<
7372(outs),
7373(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7374"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7375tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel {
7376let Inst{0-0} = 0b0;
7377let Inst{13-8} = 0b000000;
7378let Inst{19-19} = 0b0;
7379let Inst{31-22} = 0b0010011011;
7380let isPredicated = 1;
7381let isPredicatedFalse = 1;
7382let isTerminator = 1;
7383let isBranch = 1;
7384let isNewValue = 1;
7385let cofMax1 = 1;
7386let isRestrictNoSlot1Store = 1;
7387let Defs = [PC];
7388let BaseOpcode = "J4_cmpgtn1r";
7389let isTaken = Inst{13};
7390let isExtendable = 1;
7391let opExtendable = 2;
7392let isExtentSigned = 1;
7393let opExtentBits = 11;
7394let opExtentAlign = 2;
7395let opNewValue = 0;
7396}
7397def J4_cmpgtn1_f_jumpnv_t : HInst<
7398(outs),
7399(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7400"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7401tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel {
7402let Inst{0-0} = 0b0;
7403let Inst{13-8} = 0b100000;
7404let Inst{19-19} = 0b0;
7405let Inst{31-22} = 0b0010011011;
7406let isPredicated = 1;
7407let isPredicatedFalse = 1;
7408let isTerminator = 1;
7409let isBranch = 1;
7410let isNewValue = 1;
7411let cofMax1 = 1;
7412let isRestrictNoSlot1Store = 1;
7413let Defs = [PC];
7414let BaseOpcode = "J4_cmpgtn1r";
7415let isTaken = Inst{13};
7416let isExtendable = 1;
7417let opExtendable = 2;
7418let isExtentSigned = 1;
7419let opExtentBits = 11;
7420let opExtentAlign = 2;
7421let opNewValue = 0;
7422}
7423def J4_cmpgtn1_fp0_jump_nt : HInst<
7424(outs),
7425(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7426"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii",
7427tc_24f426ab, TypeCJ>, Enc_a42857, PredRel {
7428let Inst{0-0} = 0b0;
7429let Inst{13-8} = 0b000001;
7430let Inst{31-22} = 0b0001000111;
7431let isPredicated = 1;
7432let isPredicatedFalse = 1;
7433let isTerminator = 1;
7434let isBranch = 1;
7435let isPredicatedNew = 1;
7436let cofRelax1 = 1;
7437let cofRelax2 = 1;
7438let cofMax1 = 1;
7439let Uses = [P0];
7440let Defs = [P0, PC];
7441let BaseOpcode = "J4_cmpgtn1p0";
7442let isTaken = Inst{13};
7443let isExtendable = 1;
7444let opExtendable = 2;
7445let isExtentSigned = 1;
7446let opExtentBits = 11;
7447let opExtentAlign = 2;
7448}
7449def J4_cmpgtn1_fp0_jump_t : HInst<
7450(outs),
7451(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7452"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii",
7453tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel {
7454let Inst{0-0} = 0b0;
7455let Inst{13-8} = 0b100001;
7456let Inst{31-22} = 0b0001000111;
7457let isPredicated = 1;
7458let isPredicatedFalse = 1;
7459let isTerminator = 1;
7460let isBranch = 1;
7461let isPredicatedNew = 1;
7462let cofRelax1 = 1;
7463let cofRelax2 = 1;
7464let cofMax1 = 1;
7465let Uses = [P0];
7466let Defs = [P0, PC];
7467let BaseOpcode = "J4_cmpgtn1p0";
7468let isTaken = Inst{13};
7469let isExtendable = 1;
7470let opExtendable = 2;
7471let isExtentSigned = 1;
7472let opExtentBits = 11;
7473let opExtentAlign = 2;
7474}
7475def J4_cmpgtn1_fp1_jump_nt : HInst<
7476(outs),
7477(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7478"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii",
7479tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel {
7480let Inst{0-0} = 0b0;
7481let Inst{13-8} = 0b000001;
7482let Inst{31-22} = 0b0001001111;
7483let isPredicated = 1;
7484let isPredicatedFalse = 1;
7485let isTerminator = 1;
7486let isBranch = 1;
7487let isPredicatedNew = 1;
7488let cofRelax1 = 1;
7489let cofRelax2 = 1;
7490let cofMax1 = 1;
7491let Uses = [P1];
7492let Defs = [P1, PC];
7493let BaseOpcode = "J4_cmpgtn1p1";
7494let isTaken = Inst{13};
7495let isExtendable = 1;
7496let opExtendable = 2;
7497let isExtentSigned = 1;
7498let opExtentBits = 11;
7499let opExtentAlign = 2;
7500}
7501def J4_cmpgtn1_fp1_jump_t : HInst<
7502(outs),
7503(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7504"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii",
7505tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel {
7506let Inst{0-0} = 0b0;
7507let Inst{13-8} = 0b100001;
7508let Inst{31-22} = 0b0001001111;
7509let isPredicated = 1;
7510let isPredicatedFalse = 1;
7511let isTerminator = 1;
7512let isBranch = 1;
7513let isPredicatedNew = 1;
7514let cofRelax1 = 1;
7515let cofRelax2 = 1;
7516let cofMax1 = 1;
7517let Uses = [P1];
7518let Defs = [P1, PC];
7519let BaseOpcode = "J4_cmpgtn1p1";
7520let isTaken = Inst{13};
7521let isExtendable = 1;
7522let opExtendable = 2;
7523let isExtentSigned = 1;
7524let opExtentBits = 11;
7525let opExtentAlign = 2;
7526}
7527def J4_cmpgtn1_t_jumpnv_nt : HInst<
7528(outs),
7529(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7530"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii",
7531tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel {
7532let Inst{0-0} = 0b0;
7533let Inst{13-8} = 0b000000;
7534let Inst{19-19} = 0b0;
7535let Inst{31-22} = 0b0010011010;
7536let isPredicated = 1;
7537let isTerminator = 1;
7538let isBranch = 1;
7539let isNewValue = 1;
7540let cofMax1 = 1;
7541let isRestrictNoSlot1Store = 1;
7542let Defs = [PC];
7543let BaseOpcode = "J4_cmpgtn1r";
7544let isTaken = Inst{13};
7545let isExtendable = 1;
7546let opExtendable = 2;
7547let isExtentSigned = 1;
7548let opExtentBits = 11;
7549let opExtentAlign = 2;
7550let opNewValue = 0;
7551}
7552def J4_cmpgtn1_t_jumpnv_t : HInst<
7553(outs),
7554(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii),
7555"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii",
7556tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel {
7557let Inst{0-0} = 0b0;
7558let Inst{13-8} = 0b100000;
7559let Inst{19-19} = 0b0;
7560let Inst{31-22} = 0b0010011010;
7561let isPredicated = 1;
7562let isTerminator = 1;
7563let isBranch = 1;
7564let isNewValue = 1;
7565let cofMax1 = 1;
7566let isRestrictNoSlot1Store = 1;
7567let Defs = [PC];
7568let BaseOpcode = "J4_cmpgtn1r";
7569let isTaken = Inst{13};
7570let isExtendable = 1;
7571let opExtendable = 2;
7572let isExtentSigned = 1;
7573let opExtentBits = 11;
7574let opExtentAlign = 2;
7575let opNewValue = 0;
7576}
7577def J4_cmpgtn1_tp0_jump_nt : HInst<
7578(outs),
7579(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7580"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii",
7581tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel {
7582let Inst{0-0} = 0b0;
7583let Inst{13-8} = 0b000001;
7584let Inst{31-22} = 0b0001000110;
7585let isPredicated = 1;
7586let isTerminator = 1;
7587let isBranch = 1;
7588let isPredicatedNew = 1;
7589let cofRelax1 = 1;
7590let cofRelax2 = 1;
7591let cofMax1 = 1;
7592let Uses = [P0];
7593let Defs = [P0, PC];
7594let BaseOpcode = "J4_cmpgtn1p0";
7595let isTaken = Inst{13};
7596let isExtendable = 1;
7597let opExtendable = 2;
7598let isExtentSigned = 1;
7599let opExtentBits = 11;
7600let opExtentAlign = 2;
7601}
7602def J4_cmpgtn1_tp0_jump_t : HInst<
7603(outs),
7604(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7605"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii",
7606tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel {
7607let Inst{0-0} = 0b0;
7608let Inst{13-8} = 0b100001;
7609let Inst{31-22} = 0b0001000110;
7610let isPredicated = 1;
7611let isTerminator = 1;
7612let isBranch = 1;
7613let isPredicatedNew = 1;
7614let cofRelax1 = 1;
7615let cofRelax2 = 1;
7616let cofMax1 = 1;
7617let Uses = [P0];
7618let Defs = [P0, PC];
7619let BaseOpcode = "J4_cmpgtn1p0";
7620let isTaken = Inst{13};
7621let isExtendable = 1;
7622let opExtendable = 2;
7623let isExtentSigned = 1;
7624let opExtentBits = 11;
7625let opExtentAlign = 2;
7626}
7627def J4_cmpgtn1_tp1_jump_nt : HInst<
7628(outs),
7629(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7630"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii",
7631tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel {
7632let Inst{0-0} = 0b0;
7633let Inst{13-8} = 0b000001;
7634let Inst{31-22} = 0b0001001110;
7635let isPredicated = 1;
7636let isTerminator = 1;
7637let isBranch = 1;
7638let isPredicatedNew = 1;
7639let cofRelax1 = 1;
7640let cofRelax2 = 1;
7641let cofMax1 = 1;
7642let Uses = [P1];
7643let Defs = [P1, PC];
7644let BaseOpcode = "J4_cmpgtn1p1";
7645let isTaken = Inst{13};
7646let isExtendable = 1;
7647let opExtendable = 2;
7648let isExtentSigned = 1;
7649let opExtentBits = 11;
7650let opExtentAlign = 2;
7651}
7652def J4_cmpgtn1_tp1_jump_t : HInst<
7653(outs),
7654(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii),
7655"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii",
7656tc_24f426ab, TypeCJ>, Enc_178717, PredRel {
7657let Inst{0-0} = 0b0;
7658let Inst{13-8} = 0b100001;
7659let Inst{31-22} = 0b0001001110;
7660let isPredicated = 1;
7661let isTerminator = 1;
7662let isBranch = 1;
7663let isPredicatedNew = 1;
7664let cofRelax1 = 1;
7665let cofRelax2 = 1;
7666let cofMax1 = 1;
7667let Uses = [P1];
7668let Defs = [P1, PC];
7669let BaseOpcode = "J4_cmpgtn1p1";
7670let isTaken = Inst{13};
7671let isExtendable = 1;
7672let opExtendable = 2;
7673let isExtentSigned = 1;
7674let opExtentBits = 11;
7675let opExtentAlign = 2;
7676}
7677def J4_cmpgtu_f_jumpnv_nt : HInst<
7678(outs),
7679(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7680"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7681tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7682let Inst{0-0} = 0b0;
7683let Inst{13-13} = 0b0;
7684let Inst{19-19} = 0b0;
7685let Inst{31-22} = 0b0010000101;
7686let isPredicated = 1;
7687let isPredicatedFalse = 1;
7688let isTerminator = 1;
7689let isBranch = 1;
7690let isNewValue = 1;
7691let cofMax1 = 1;
7692let isRestrictNoSlot1Store = 1;
7693let Defs = [PC];
7694let BaseOpcode = "J4_cmpgtur";
7695let isTaken = Inst{13};
7696let isExtendable = 1;
7697let opExtendable = 2;
7698let isExtentSigned = 1;
7699let opExtentBits = 11;
7700let opExtentAlign = 2;
7701let opNewValue = 0;
7702}
7703def J4_cmpgtu_f_jumpnv_t : HInst<
7704(outs),
7705(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7706"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7707tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7708let Inst{0-0} = 0b0;
7709let Inst{13-13} = 0b1;
7710let Inst{19-19} = 0b0;
7711let Inst{31-22} = 0b0010000101;
7712let isPredicated = 1;
7713let isPredicatedFalse = 1;
7714let isTerminator = 1;
7715let isBranch = 1;
7716let isNewValue = 1;
7717let cofMax1 = 1;
7718let isRestrictNoSlot1Store = 1;
7719let Defs = [PC];
7720let BaseOpcode = "J4_cmpgtur";
7721let isTaken = Inst{13};
7722let isExtendable = 1;
7723let opExtendable = 2;
7724let isExtentSigned = 1;
7725let opExtentBits = 11;
7726let opExtentAlign = 2;
7727let opNewValue = 0;
7728}
7729def J4_cmpgtu_fp0_jump_nt : HInst<
7730(outs),
7731(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7732"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii",
7733tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7734let Inst{0-0} = 0b0;
7735let Inst{13-12} = 0b00;
7736let Inst{31-22} = 0b0001010101;
7737let isPredicated = 1;
7738let isPredicatedFalse = 1;
7739let isTerminator = 1;
7740let isBranch = 1;
7741let isPredicatedNew = 1;
7742let cofRelax1 = 1;
7743let cofRelax2 = 1;
7744let cofMax1 = 1;
7745let Uses = [P0];
7746let Defs = [P0, PC];
7747let BaseOpcode = "J4_cmpgtup0";
7748let isTaken = Inst{13};
7749let isExtendable = 1;
7750let opExtendable = 2;
7751let isExtentSigned = 1;
7752let opExtentBits = 11;
7753let opExtentAlign = 2;
7754}
7755def J4_cmpgtu_fp0_jump_t : HInst<
7756(outs),
7757(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7758"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii",
7759tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7760let Inst{0-0} = 0b0;
7761let Inst{13-12} = 0b10;
7762let Inst{31-22} = 0b0001010101;
7763let isPredicated = 1;
7764let isPredicatedFalse = 1;
7765let isTerminator = 1;
7766let isBranch = 1;
7767let isPredicatedNew = 1;
7768let cofRelax1 = 1;
7769let cofRelax2 = 1;
7770let cofMax1 = 1;
7771let Uses = [P0];
7772let Defs = [P0, PC];
7773let BaseOpcode = "J4_cmpgtup0";
7774let isTaken = Inst{13};
7775let isExtendable = 1;
7776let opExtendable = 2;
7777let isExtentSigned = 1;
7778let opExtentBits = 11;
7779let opExtentAlign = 2;
7780}
7781def J4_cmpgtu_fp1_jump_nt : HInst<
7782(outs),
7783(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7784"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii",
7785tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7786let Inst{0-0} = 0b0;
7787let Inst{13-12} = 0b01;
7788let Inst{31-22} = 0b0001010101;
7789let isPredicated = 1;
7790let isPredicatedFalse = 1;
7791let isTerminator = 1;
7792let isBranch = 1;
7793let isPredicatedNew = 1;
7794let cofRelax1 = 1;
7795let cofRelax2 = 1;
7796let cofMax1 = 1;
7797let Uses = [P1];
7798let Defs = [P1, PC];
7799let BaseOpcode = "J4_cmpgtup1";
7800let isTaken = Inst{13};
7801let isExtendable = 1;
7802let opExtendable = 2;
7803let isExtentSigned = 1;
7804let opExtentBits = 11;
7805let opExtentAlign = 2;
7806}
7807def J4_cmpgtu_fp1_jump_t : HInst<
7808(outs),
7809(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7810"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii",
7811tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7812let Inst{0-0} = 0b0;
7813let Inst{13-12} = 0b11;
7814let Inst{31-22} = 0b0001010101;
7815let isPredicated = 1;
7816let isPredicatedFalse = 1;
7817let isTerminator = 1;
7818let isBranch = 1;
7819let isPredicatedNew = 1;
7820let cofRelax1 = 1;
7821let cofRelax2 = 1;
7822let cofMax1 = 1;
7823let Uses = [P1];
7824let Defs = [P1, PC];
7825let BaseOpcode = "J4_cmpgtup1";
7826let isTaken = Inst{13};
7827let isExtendable = 1;
7828let opExtendable = 2;
7829let isExtentSigned = 1;
7830let opExtentBits = 11;
7831let opExtentAlign = 2;
7832}
7833def J4_cmpgtu_t_jumpnv_nt : HInst<
7834(outs),
7835(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7836"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii",
7837tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7838let Inst{0-0} = 0b0;
7839let Inst{13-13} = 0b0;
7840let Inst{19-19} = 0b0;
7841let Inst{31-22} = 0b0010000100;
7842let isPredicated = 1;
7843let isTerminator = 1;
7844let isBranch = 1;
7845let isNewValue = 1;
7846let cofMax1 = 1;
7847let isRestrictNoSlot1Store = 1;
7848let Defs = [PC];
7849let BaseOpcode = "J4_cmpgtur";
7850let isTaken = Inst{13};
7851let isExtendable = 1;
7852let opExtendable = 2;
7853let isExtentSigned = 1;
7854let opExtentBits = 11;
7855let opExtentAlign = 2;
7856let opNewValue = 0;
7857}
7858def J4_cmpgtu_t_jumpnv_t : HInst<
7859(outs),
7860(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii),
7861"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii",
7862tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel {
7863let Inst{0-0} = 0b0;
7864let Inst{13-13} = 0b1;
7865let Inst{19-19} = 0b0;
7866let Inst{31-22} = 0b0010000100;
7867let isPredicated = 1;
7868let isTerminator = 1;
7869let isBranch = 1;
7870let isNewValue = 1;
7871let cofMax1 = 1;
7872let isRestrictNoSlot1Store = 1;
7873let Defs = [PC];
7874let BaseOpcode = "J4_cmpgtur";
7875let isTaken = Inst{13};
7876let isExtendable = 1;
7877let opExtendable = 2;
7878let isExtentSigned = 1;
7879let opExtentBits = 11;
7880let opExtentAlign = 2;
7881let opNewValue = 0;
7882}
7883def J4_cmpgtu_tp0_jump_nt : HInst<
7884(outs),
7885(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7886"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii",
7887tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7888let Inst{0-0} = 0b0;
7889let Inst{13-12} = 0b00;
7890let Inst{31-22} = 0b0001010100;
7891let isPredicated = 1;
7892let isTerminator = 1;
7893let isBranch = 1;
7894let isPredicatedNew = 1;
7895let cofRelax1 = 1;
7896let cofRelax2 = 1;
7897let cofMax1 = 1;
7898let Uses = [P0];
7899let Defs = [P0, PC];
7900let BaseOpcode = "J4_cmpgtup0";
7901let isTaken = Inst{13};
7902let isExtendable = 1;
7903let opExtendable = 2;
7904let isExtentSigned = 1;
7905let opExtentBits = 11;
7906let opExtentAlign = 2;
7907}
7908def J4_cmpgtu_tp0_jump_t : HInst<
7909(outs),
7910(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7911"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii",
7912tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7913let Inst{0-0} = 0b0;
7914let Inst{13-12} = 0b10;
7915let Inst{31-22} = 0b0001010100;
7916let isPredicated = 1;
7917let isTerminator = 1;
7918let isBranch = 1;
7919let isPredicatedNew = 1;
7920let cofRelax1 = 1;
7921let cofRelax2 = 1;
7922let cofMax1 = 1;
7923let Uses = [P0];
7924let Defs = [P0, PC];
7925let BaseOpcode = "J4_cmpgtup0";
7926let isTaken = Inst{13};
7927let isExtendable = 1;
7928let opExtendable = 2;
7929let isExtentSigned = 1;
7930let opExtentBits = 11;
7931let opExtentAlign = 2;
7932}
7933def J4_cmpgtu_tp1_jump_nt : HInst<
7934(outs),
7935(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7936"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii",
7937tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7938let Inst{0-0} = 0b0;
7939let Inst{13-12} = 0b01;
7940let Inst{31-22} = 0b0001010100;
7941let isPredicated = 1;
7942let isTerminator = 1;
7943let isBranch = 1;
7944let isPredicatedNew = 1;
7945let cofRelax1 = 1;
7946let cofRelax2 = 1;
7947let cofMax1 = 1;
7948let Uses = [P1];
7949let Defs = [P1, PC];
7950let BaseOpcode = "J4_cmpgtup1";
7951let isTaken = Inst{13};
7952let isExtendable = 1;
7953let opExtendable = 2;
7954let isExtentSigned = 1;
7955let opExtentBits = 11;
7956let opExtentAlign = 2;
7957}
7958def J4_cmpgtu_tp1_jump_t : HInst<
7959(outs),
7960(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii),
7961"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii",
7962tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel {
7963let Inst{0-0} = 0b0;
7964let Inst{13-12} = 0b11;
7965let Inst{31-22} = 0b0001010100;
7966let isPredicated = 1;
7967let isTerminator = 1;
7968let isBranch = 1;
7969let isPredicatedNew = 1;
7970let cofRelax1 = 1;
7971let cofRelax2 = 1;
7972let cofMax1 = 1;
7973let Uses = [P1];
7974let Defs = [P1, PC];
7975let BaseOpcode = "J4_cmpgtup1";
7976let isTaken = Inst{13};
7977let isExtendable = 1;
7978let opExtendable = 2;
7979let isExtentSigned = 1;
7980let opExtentBits = 11;
7981let opExtentAlign = 2;
7982}
7983def J4_cmpgtui_f_jumpnv_nt : HInst<
7984(outs),
7985(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
7986"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
7987tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
7988let Inst{0-0} = 0b0;
7989let Inst{13-13} = 0b0;
7990let Inst{19-19} = 0b0;
7991let Inst{31-22} = 0b0010010101;
7992let isPredicated = 1;
7993let isPredicatedFalse = 1;
7994let isTerminator = 1;
7995let isBranch = 1;
7996let isNewValue = 1;
7997let cofMax1 = 1;
7998let isRestrictNoSlot1Store = 1;
7999let Defs = [PC];
8000let BaseOpcode = "J4_cmpgtuir";
8001let isTaken = Inst{13};
8002let isExtendable = 1;
8003let opExtendable = 2;
8004let isExtentSigned = 1;
8005let opExtentBits = 11;
8006let opExtentAlign = 2;
8007let opNewValue = 0;
8008}
8009def J4_cmpgtui_f_jumpnv_t : HInst<
8010(outs),
8011(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8012"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8013tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8014let Inst{0-0} = 0b0;
8015let Inst{13-13} = 0b1;
8016let Inst{19-19} = 0b0;
8017let Inst{31-22} = 0b0010010101;
8018let isPredicated = 1;
8019let isPredicatedFalse = 1;
8020let isTerminator = 1;
8021let isBranch = 1;
8022let isNewValue = 1;
8023let cofMax1 = 1;
8024let isRestrictNoSlot1Store = 1;
8025let Defs = [PC];
8026let BaseOpcode = "J4_cmpgtuir";
8027let isTaken = Inst{13};
8028let isExtendable = 1;
8029let opExtendable = 2;
8030let isExtentSigned = 1;
8031let opExtentBits = 11;
8032let opExtentAlign = 2;
8033let opNewValue = 0;
8034}
8035def J4_cmpgtui_fp0_jump_nt : HInst<
8036(outs),
8037(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8038"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii",
8039tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8040let Inst{0-0} = 0b0;
8041let Inst{13-13} = 0b0;
8042let Inst{31-22} = 0b0001000101;
8043let isPredicated = 1;
8044let isPredicatedFalse = 1;
8045let isTerminator = 1;
8046let isBranch = 1;
8047let isPredicatedNew = 1;
8048let cofRelax1 = 1;
8049let cofRelax2 = 1;
8050let cofMax1 = 1;
8051let Uses = [P0];
8052let Defs = [P0, PC];
8053let BaseOpcode = "J4_cmpgtuip0";
8054let isTaken = Inst{13};
8055let isExtendable = 1;
8056let opExtendable = 2;
8057let isExtentSigned = 1;
8058let opExtentBits = 11;
8059let opExtentAlign = 2;
8060}
8061def J4_cmpgtui_fp0_jump_t : HInst<
8062(outs),
8063(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8064"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii",
8065tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8066let Inst{0-0} = 0b0;
8067let Inst{13-13} = 0b1;
8068let Inst{31-22} = 0b0001000101;
8069let isPredicated = 1;
8070let isPredicatedFalse = 1;
8071let isTerminator = 1;
8072let isBranch = 1;
8073let isPredicatedNew = 1;
8074let cofRelax1 = 1;
8075let cofRelax2 = 1;
8076let cofMax1 = 1;
8077let Uses = [P0];
8078let Defs = [P0, PC];
8079let BaseOpcode = "J4_cmpgtuip0";
8080let isTaken = Inst{13};
8081let isExtendable = 1;
8082let opExtendable = 2;
8083let isExtentSigned = 1;
8084let opExtentBits = 11;
8085let opExtentAlign = 2;
8086}
8087def J4_cmpgtui_fp1_jump_nt : HInst<
8088(outs),
8089(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8090"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii",
8091tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8092let Inst{0-0} = 0b0;
8093let Inst{13-13} = 0b0;
8094let Inst{31-22} = 0b0001001101;
8095let isPredicated = 1;
8096let isPredicatedFalse = 1;
8097let isTerminator = 1;
8098let isBranch = 1;
8099let isPredicatedNew = 1;
8100let cofRelax1 = 1;
8101let cofRelax2 = 1;
8102let cofMax1 = 1;
8103let Uses = [P1];
8104let Defs = [P1, PC];
8105let BaseOpcode = "J4_cmpgtuip1";
8106let isTaken = Inst{13};
8107let isExtendable = 1;
8108let opExtendable = 2;
8109let isExtentSigned = 1;
8110let opExtentBits = 11;
8111let opExtentAlign = 2;
8112}
8113def J4_cmpgtui_fp1_jump_t : HInst<
8114(outs),
8115(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8116"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii",
8117tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8118let Inst{0-0} = 0b0;
8119let Inst{13-13} = 0b1;
8120let Inst{31-22} = 0b0001001101;
8121let isPredicated = 1;
8122let isPredicatedFalse = 1;
8123let isTerminator = 1;
8124let isBranch = 1;
8125let isPredicatedNew = 1;
8126let cofRelax1 = 1;
8127let cofRelax2 = 1;
8128let cofMax1 = 1;
8129let Uses = [P1];
8130let Defs = [P1, PC];
8131let BaseOpcode = "J4_cmpgtuip1";
8132let isTaken = Inst{13};
8133let isExtendable = 1;
8134let opExtendable = 2;
8135let isExtentSigned = 1;
8136let opExtentBits = 11;
8137let opExtentAlign = 2;
8138}
8139def J4_cmpgtui_t_jumpnv_nt : HInst<
8140(outs),
8141(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8142"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii",
8143tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8144let Inst{0-0} = 0b0;
8145let Inst{13-13} = 0b0;
8146let Inst{19-19} = 0b0;
8147let Inst{31-22} = 0b0010010100;
8148let isPredicated = 1;
8149let isTerminator = 1;
8150let isBranch = 1;
8151let isNewValue = 1;
8152let cofMax1 = 1;
8153let isRestrictNoSlot1Store = 1;
8154let Defs = [PC];
8155let BaseOpcode = "J4_cmpgtuir";
8156let isTaken = Inst{13};
8157let isExtendable = 1;
8158let opExtendable = 2;
8159let isExtentSigned = 1;
8160let opExtentBits = 11;
8161let opExtentAlign = 2;
8162let opNewValue = 0;
8163}
8164def J4_cmpgtui_t_jumpnv_t : HInst<
8165(outs),
8166(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii),
8167"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii",
8168tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel {
8169let Inst{0-0} = 0b0;
8170let Inst{13-13} = 0b1;
8171let Inst{19-19} = 0b0;
8172let Inst{31-22} = 0b0010010100;
8173let isPredicated = 1;
8174let isTerminator = 1;
8175let isBranch = 1;
8176let isNewValue = 1;
8177let cofMax1 = 1;
8178let isRestrictNoSlot1Store = 1;
8179let Defs = [PC];
8180let BaseOpcode = "J4_cmpgtuir";
8181let isTaken = Inst{13};
8182let isExtendable = 1;
8183let opExtendable = 2;
8184let isExtentSigned = 1;
8185let opExtentBits = 11;
8186let opExtentAlign = 2;
8187let opNewValue = 0;
8188}
8189def J4_cmpgtui_tp0_jump_nt : HInst<
8190(outs),
8191(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8192"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii",
8193tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8194let Inst{0-0} = 0b0;
8195let Inst{13-13} = 0b0;
8196let Inst{31-22} = 0b0001000100;
8197let isPredicated = 1;
8198let isTerminator = 1;
8199let isBranch = 1;
8200let isPredicatedNew = 1;
8201let cofRelax1 = 1;
8202let cofRelax2 = 1;
8203let cofMax1 = 1;
8204let Uses = [P0];
8205let Defs = [P0, PC];
8206let BaseOpcode = "J4_cmpgtuip0";
8207let isTaken = Inst{13};
8208let isExtendable = 1;
8209let opExtendable = 2;
8210let isExtentSigned = 1;
8211let opExtentBits = 11;
8212let opExtentAlign = 2;
8213}
8214def J4_cmpgtui_tp0_jump_t : HInst<
8215(outs),
8216(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8217"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii",
8218tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8219let Inst{0-0} = 0b0;
8220let Inst{13-13} = 0b1;
8221let Inst{31-22} = 0b0001000100;
8222let isPredicated = 1;
8223let isTerminator = 1;
8224let isBranch = 1;
8225let isPredicatedNew = 1;
8226let cofRelax1 = 1;
8227let cofRelax2 = 1;
8228let cofMax1 = 1;
8229let Uses = [P0];
8230let Defs = [P0, PC];
8231let BaseOpcode = "J4_cmpgtuip0";
8232let isTaken = Inst{13};
8233let isExtendable = 1;
8234let opExtendable = 2;
8235let isExtentSigned = 1;
8236let opExtentBits = 11;
8237let opExtentAlign = 2;
8238}
8239def J4_cmpgtui_tp1_jump_nt : HInst<
8240(outs),
8241(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8242"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii",
8243tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8244let Inst{0-0} = 0b0;
8245let Inst{13-13} = 0b0;
8246let Inst{31-22} = 0b0001001100;
8247let isPredicated = 1;
8248let isTerminator = 1;
8249let isBranch = 1;
8250let isPredicatedNew = 1;
8251let cofRelax1 = 1;
8252let cofRelax2 = 1;
8253let cofMax1 = 1;
8254let Uses = [P1];
8255let Defs = [P1, PC];
8256let BaseOpcode = "J4_cmpgtuip1";
8257let isTaken = Inst{13};
8258let isExtendable = 1;
8259let opExtendable = 2;
8260let isExtentSigned = 1;
8261let opExtentBits = 11;
8262let opExtentAlign = 2;
8263}
8264def J4_cmpgtui_tp1_jump_t : HInst<
8265(outs),
8266(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii),
8267"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii",
8268tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel {
8269let Inst{0-0} = 0b0;
8270let Inst{13-13} = 0b1;
8271let Inst{31-22} = 0b0001001100;
8272let isPredicated = 1;
8273let isTerminator = 1;
8274let isBranch = 1;
8275let isPredicatedNew = 1;
8276let cofRelax1 = 1;
8277let cofRelax2 = 1;
8278let cofMax1 = 1;
8279let Uses = [P1];
8280let Defs = [P1, PC];
8281let BaseOpcode = "J4_cmpgtuip1";
8282let isTaken = Inst{13};
8283let isExtendable = 1;
8284let opExtendable = 2;
8285let isExtentSigned = 1;
8286let opExtentBits = 11;
8287let opExtentAlign = 2;
8288}
8289def J4_cmplt_f_jumpnv_nt : HInst<
8290(outs),
8291(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8292"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8293tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8294let Inst{0-0} = 0b0;
8295let Inst{13-13} = 0b0;
8296let Inst{19-19} = 0b0;
8297let Inst{31-22} = 0b0010000111;
8298let isPredicated = 1;
8299let isPredicatedFalse = 1;
8300let isTerminator = 1;
8301let isBranch = 1;
8302let isNewValue = 1;
8303let cofMax1 = 1;
8304let isRestrictNoSlot1Store = 1;
8305let Defs = [PC];
8306let BaseOpcode = "J4_cmpltr";
8307let isTaken = Inst{13};
8308let isExtendable = 1;
8309let opExtendable = 2;
8310let isExtentSigned = 1;
8311let opExtentBits = 11;
8312let opExtentAlign = 2;
8313let opNewValue = 1;
8314}
8315def J4_cmplt_f_jumpnv_t : HInst<
8316(outs),
8317(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8318"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8319tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8320let Inst{0-0} = 0b0;
8321let Inst{13-13} = 0b1;
8322let Inst{19-19} = 0b0;
8323let Inst{31-22} = 0b0010000111;
8324let isPredicated = 1;
8325let isPredicatedFalse = 1;
8326let isTerminator = 1;
8327let isBranch = 1;
8328let isNewValue = 1;
8329let cofMax1 = 1;
8330let isRestrictNoSlot1Store = 1;
8331let Defs = [PC];
8332let BaseOpcode = "J4_cmpltr";
8333let isTaken = Inst{13};
8334let isExtendable = 1;
8335let opExtendable = 2;
8336let isExtentSigned = 1;
8337let opExtentBits = 11;
8338let opExtentAlign = 2;
8339let opNewValue = 1;
8340}
8341def J4_cmplt_t_jumpnv_nt : HInst<
8342(outs),
8343(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8344"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii",
8345tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8346let Inst{0-0} = 0b0;
8347let Inst{13-13} = 0b0;
8348let Inst{19-19} = 0b0;
8349let Inst{31-22} = 0b0010000110;
8350let isPredicated = 1;
8351let isTerminator = 1;
8352let isBranch = 1;
8353let isNewValue = 1;
8354let cofMax1 = 1;
8355let isRestrictNoSlot1Store = 1;
8356let Defs = [PC];
8357let BaseOpcode = "J4_cmpltr";
8358let isTaken = Inst{13};
8359let isExtendable = 1;
8360let opExtendable = 2;
8361let isExtentSigned = 1;
8362let opExtentBits = 11;
8363let opExtentAlign = 2;
8364let opNewValue = 1;
8365}
8366def J4_cmplt_t_jumpnv_t : HInst<
8367(outs),
8368(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8369"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii",
8370tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8371let Inst{0-0} = 0b0;
8372let Inst{13-13} = 0b1;
8373let Inst{19-19} = 0b0;
8374let Inst{31-22} = 0b0010000110;
8375let isPredicated = 1;
8376let isTerminator = 1;
8377let isBranch = 1;
8378let isNewValue = 1;
8379let cofMax1 = 1;
8380let isRestrictNoSlot1Store = 1;
8381let Defs = [PC];
8382let BaseOpcode = "J4_cmpltr";
8383let isTaken = Inst{13};
8384let isExtendable = 1;
8385let opExtendable = 2;
8386let isExtentSigned = 1;
8387let opExtentBits = 11;
8388let opExtentAlign = 2;
8389let opNewValue = 1;
8390}
8391def J4_cmpltu_f_jumpnv_nt : HInst<
8392(outs),
8393(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8394"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8395tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8396let Inst{0-0} = 0b0;
8397let Inst{13-13} = 0b0;
8398let Inst{19-19} = 0b0;
8399let Inst{31-22} = 0b0010001001;
8400let isPredicated = 1;
8401let isPredicatedFalse = 1;
8402let isTerminator = 1;
8403let isBranch = 1;
8404let isNewValue = 1;
8405let cofMax1 = 1;
8406let isRestrictNoSlot1Store = 1;
8407let Defs = [PC];
8408let BaseOpcode = "J4_cmpltur";
8409let isTaken = Inst{13};
8410let isExtendable = 1;
8411let opExtendable = 2;
8412let isExtentSigned = 1;
8413let opExtentBits = 11;
8414let opExtentAlign = 2;
8415let opNewValue = 1;
8416}
8417def J4_cmpltu_f_jumpnv_t : HInst<
8418(outs),
8419(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8420"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8421tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8422let Inst{0-0} = 0b0;
8423let Inst{13-13} = 0b1;
8424let Inst{19-19} = 0b0;
8425let Inst{31-22} = 0b0010001001;
8426let isPredicated = 1;
8427let isPredicatedFalse = 1;
8428let isTerminator = 1;
8429let isBranch = 1;
8430let isNewValue = 1;
8431let cofMax1 = 1;
8432let isRestrictNoSlot1Store = 1;
8433let Defs = [PC];
8434let BaseOpcode = "J4_cmpltur";
8435let isTaken = Inst{13};
8436let isExtendable = 1;
8437let opExtendable = 2;
8438let isExtentSigned = 1;
8439let opExtentBits = 11;
8440let opExtentAlign = 2;
8441let opNewValue = 1;
8442}
8443def J4_cmpltu_t_jumpnv_nt : HInst<
8444(outs),
8445(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8446"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii",
8447tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8448let Inst{0-0} = 0b0;
8449let Inst{13-13} = 0b0;
8450let Inst{19-19} = 0b0;
8451let Inst{31-22} = 0b0010001000;
8452let isPredicated = 1;
8453let isTerminator = 1;
8454let isBranch = 1;
8455let isNewValue = 1;
8456let cofMax1 = 1;
8457let isRestrictNoSlot1Store = 1;
8458let Defs = [PC];
8459let BaseOpcode = "J4_cmpltur";
8460let isTaken = Inst{13};
8461let isExtendable = 1;
8462let opExtendable = 2;
8463let isExtentSigned = 1;
8464let opExtentBits = 11;
8465let opExtentAlign = 2;
8466let opNewValue = 1;
8467}
8468def J4_cmpltu_t_jumpnv_t : HInst<
8469(outs),
8470(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii),
8471"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii",
8472tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel {
8473let Inst{0-0} = 0b0;
8474let Inst{13-13} = 0b1;
8475let Inst{19-19} = 0b0;
8476let Inst{31-22} = 0b0010001000;
8477let isPredicated = 1;
8478let isTerminator = 1;
8479let isBranch = 1;
8480let isNewValue = 1;
8481let cofMax1 = 1;
8482let isRestrictNoSlot1Store = 1;
8483let Defs = [PC];
8484let BaseOpcode = "J4_cmpltur";
8485let isTaken = Inst{13};
8486let isExtendable = 1;
8487let opExtendable = 2;
8488let isExtentSigned = 1;
8489let opExtentBits = 11;
8490let opExtentAlign = 2;
8491let opNewValue = 1;
8492}
8493def J4_hintjumpr : HInst<
8494(outs),
8495(ins IntRegs:$Rs32),
8496"hintjr($Rs32)",
8497tc_60e324ff, TypeJ>, Enc_ecbcc8 {
8498let Inst{13-0} = 0b00000000000000;
8499let Inst{31-21} = 0b01010010101;
8500let isTerminator = 1;
8501let isIndirectBranch = 1;
8502let isBranch = 1;
8503let cofMax1 = 1;
8504}
8505def J4_jumpseti : HInst<
8506(outs GeneralSubRegs:$Rd16),
8507(ins u6_0Imm:$II, b30_2Imm:$Ii),
8508"$Rd16 = #$II ; jump $Ii",
8509tc_5502c366, TypeCJ>, Enc_9e4c3f {
8510let Inst{0-0} = 0b0;
8511let Inst{31-22} = 0b0001011000;
8512let hasNewValue = 1;
8513let opNewValue = 0;
8514let isTerminator = 1;
8515let isBranch = 1;
8516let cofRelax2 = 1;
8517let cofMax1 = 1;
8518let Defs = [PC];
8519let isExtendable = 1;
8520let opExtendable = 2;
8521let isExtentSigned = 1;
8522let opExtentBits = 11;
8523let opExtentAlign = 2;
8524}
8525def J4_jumpsetr : HInst<
8526(outs GeneralSubRegs:$Rd16),
8527(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8528"$Rd16 = $Rs16 ; jump $Ii",
8529tc_5502c366, TypeCJ>, Enc_66bce1 {
8530let Inst{0-0} = 0b0;
8531let Inst{13-12} = 0b00;
8532let Inst{31-22} = 0b0001011100;
8533let hasNewValue = 1;
8534let opNewValue = 0;
8535let isTerminator = 1;
8536let isBranch = 1;
8537let cofRelax2 = 1;
8538let cofMax1 = 1;
8539let Defs = [PC];
8540let isExtendable = 1;
8541let opExtendable = 2;
8542let isExtentSigned = 1;
8543let opExtentBits = 11;
8544let opExtentAlign = 2;
8545}
8546def J4_tstbit0_f_jumpnv_nt : HInst<
8547(outs),
8548(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8549"if (!tstbit($Ns8.new,#0)) jump:nt $Ii",
8550tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8551let Inst{0-0} = 0b0;
8552let Inst{13-8} = 0b000000;
8553let Inst{19-19} = 0b0;
8554let Inst{31-22} = 0b0010010111;
8555let isPredicated = 1;
8556let isPredicatedFalse = 1;
8557let isTerminator = 1;
8558let isBranch = 1;
8559let isNewValue = 1;
8560let cofMax1 = 1;
8561let isRestrictNoSlot1Store = 1;
8562let Defs = [PC];
8563let isTaken = Inst{13};
8564let isExtendable = 1;
8565let opExtendable = 1;
8566let isExtentSigned = 1;
8567let opExtentBits = 11;
8568let opExtentAlign = 2;
8569let opNewValue = 0;
8570}
8571def J4_tstbit0_f_jumpnv_t : HInst<
8572(outs),
8573(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8574"if (!tstbit($Ns8.new,#0)) jump:t $Ii",
8575tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8576let Inst{0-0} = 0b0;
8577let Inst{13-8} = 0b100000;
8578let Inst{19-19} = 0b0;
8579let Inst{31-22} = 0b0010010111;
8580let isPredicated = 1;
8581let isPredicatedFalse = 1;
8582let isTerminator = 1;
8583let isBranch = 1;
8584let isNewValue = 1;
8585let cofMax1 = 1;
8586let isRestrictNoSlot1Store = 1;
8587let Defs = [PC];
8588let isTaken = Inst{13};
8589let isExtendable = 1;
8590let opExtendable = 1;
8591let isExtentSigned = 1;
8592let opExtentBits = 11;
8593let opExtentAlign = 2;
8594let opNewValue = 0;
8595}
8596def J4_tstbit0_fp0_jump_nt : HInst<
8597(outs),
8598(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8599"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii",
8600tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8601let Inst{0-0} = 0b0;
8602let Inst{13-8} = 0b000011;
8603let Inst{31-22} = 0b0001000111;
8604let isPredicated = 1;
8605let isPredicatedFalse = 1;
8606let isTerminator = 1;
8607let isBranch = 1;
8608let isPredicatedNew = 1;
8609let cofRelax1 = 1;
8610let cofRelax2 = 1;
8611let cofMax1 = 1;
8612let Uses = [P0];
8613let Defs = [P0, PC];
8614let isTaken = Inst{13};
8615let isExtendable = 1;
8616let opExtendable = 1;
8617let isExtentSigned = 1;
8618let opExtentBits = 11;
8619let opExtentAlign = 2;
8620}
8621def J4_tstbit0_fp0_jump_t : HInst<
8622(outs),
8623(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8624"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii",
8625tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8626let Inst{0-0} = 0b0;
8627let Inst{13-8} = 0b100011;
8628let Inst{31-22} = 0b0001000111;
8629let isPredicated = 1;
8630let isPredicatedFalse = 1;
8631let isTerminator = 1;
8632let isBranch = 1;
8633let isPredicatedNew = 1;
8634let cofRelax1 = 1;
8635let cofRelax2 = 1;
8636let cofMax1 = 1;
8637let Uses = [P0];
8638let Defs = [P0, PC];
8639let isTaken = Inst{13};
8640let isExtendable = 1;
8641let opExtendable = 1;
8642let isExtentSigned = 1;
8643let opExtentBits = 11;
8644let opExtentAlign = 2;
8645}
8646def J4_tstbit0_fp1_jump_nt : HInst<
8647(outs),
8648(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8649"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii",
8650tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8651let Inst{0-0} = 0b0;
8652let Inst{13-8} = 0b000011;
8653let Inst{31-22} = 0b0001001111;
8654let isPredicated = 1;
8655let isPredicatedFalse = 1;
8656let isTerminator = 1;
8657let isBranch = 1;
8658let isPredicatedNew = 1;
8659let cofRelax1 = 1;
8660let cofRelax2 = 1;
8661let cofMax1 = 1;
8662let Uses = [P1];
8663let Defs = [P1, PC];
8664let isTaken = Inst{13};
8665let isExtendable = 1;
8666let opExtendable = 1;
8667let isExtentSigned = 1;
8668let opExtentBits = 11;
8669let opExtentAlign = 2;
8670}
8671def J4_tstbit0_fp1_jump_t : HInst<
8672(outs),
8673(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8674"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii",
8675tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8676let Inst{0-0} = 0b0;
8677let Inst{13-8} = 0b100011;
8678let Inst{31-22} = 0b0001001111;
8679let isPredicated = 1;
8680let isPredicatedFalse = 1;
8681let isTerminator = 1;
8682let isBranch = 1;
8683let isPredicatedNew = 1;
8684let cofRelax1 = 1;
8685let cofRelax2 = 1;
8686let cofMax1 = 1;
8687let Uses = [P1];
8688let Defs = [P1, PC];
8689let isTaken = Inst{13};
8690let isExtendable = 1;
8691let opExtendable = 1;
8692let isExtentSigned = 1;
8693let opExtentBits = 11;
8694let opExtentAlign = 2;
8695}
8696def J4_tstbit0_t_jumpnv_nt : HInst<
8697(outs),
8698(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8699"if (tstbit($Ns8.new,#0)) jump:nt $Ii",
8700tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8701let Inst{0-0} = 0b0;
8702let Inst{13-8} = 0b000000;
8703let Inst{19-19} = 0b0;
8704let Inst{31-22} = 0b0010010110;
8705let isPredicated = 1;
8706let isTerminator = 1;
8707let isBranch = 1;
8708let isNewValue = 1;
8709let cofMax1 = 1;
8710let isRestrictNoSlot1Store = 1;
8711let Defs = [PC];
8712let isTaken = Inst{13};
8713let isExtendable = 1;
8714let opExtendable = 1;
8715let isExtentSigned = 1;
8716let opExtentBits = 11;
8717let opExtentAlign = 2;
8718let opNewValue = 0;
8719}
8720def J4_tstbit0_t_jumpnv_t : HInst<
8721(outs),
8722(ins IntRegs:$Ns8, b30_2Imm:$Ii),
8723"if (tstbit($Ns8.new,#0)) jump:t $Ii",
8724tc_7b9187d3, TypeNCJ>, Enc_69d63b {
8725let Inst{0-0} = 0b0;
8726let Inst{13-8} = 0b100000;
8727let Inst{19-19} = 0b0;
8728let Inst{31-22} = 0b0010010110;
8729let isPredicated = 1;
8730let isTerminator = 1;
8731let isBranch = 1;
8732let isNewValue = 1;
8733let cofMax1 = 1;
8734let isRestrictNoSlot1Store = 1;
8735let Defs = [PC];
8736let isTaken = Inst{13};
8737let isExtendable = 1;
8738let opExtendable = 1;
8739let isExtentSigned = 1;
8740let opExtentBits = 11;
8741let opExtentAlign = 2;
8742let opNewValue = 0;
8743}
8744def J4_tstbit0_tp0_jump_nt : HInst<
8745(outs),
8746(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8747"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii",
8748tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8749let Inst{0-0} = 0b0;
8750let Inst{13-8} = 0b000011;
8751let Inst{31-22} = 0b0001000110;
8752let isPredicated = 1;
8753let isTerminator = 1;
8754let isBranch = 1;
8755let isPredicatedNew = 1;
8756let cofRelax1 = 1;
8757let cofRelax2 = 1;
8758let cofMax1 = 1;
8759let Uses = [P0];
8760let Defs = [P0, PC];
8761let isTaken = Inst{13};
8762let isExtendable = 1;
8763let opExtendable = 1;
8764let isExtentSigned = 1;
8765let opExtentBits = 11;
8766let opExtentAlign = 2;
8767}
8768def J4_tstbit0_tp0_jump_t : HInst<
8769(outs),
8770(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8771"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii",
8772tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8773let Inst{0-0} = 0b0;
8774let Inst{13-8} = 0b100011;
8775let Inst{31-22} = 0b0001000110;
8776let isPredicated = 1;
8777let isTerminator = 1;
8778let isBranch = 1;
8779let isPredicatedNew = 1;
8780let cofRelax1 = 1;
8781let cofRelax2 = 1;
8782let cofMax1 = 1;
8783let Uses = [P0];
8784let Defs = [P0, PC];
8785let isTaken = Inst{13};
8786let isExtendable = 1;
8787let opExtendable = 1;
8788let isExtentSigned = 1;
8789let opExtentBits = 11;
8790let opExtentAlign = 2;
8791}
8792def J4_tstbit0_tp1_jump_nt : HInst<
8793(outs),
8794(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8795"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii",
8796tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8797let Inst{0-0} = 0b0;
8798let Inst{13-8} = 0b000011;
8799let Inst{31-22} = 0b0001001110;
8800let isPredicated = 1;
8801let isTerminator = 1;
8802let isBranch = 1;
8803let isPredicatedNew = 1;
8804let cofRelax1 = 1;
8805let cofRelax2 = 1;
8806let cofMax1 = 1;
8807let Uses = [P1];
8808let Defs = [P1, PC];
8809let isTaken = Inst{13};
8810let isExtendable = 1;
8811let opExtendable = 1;
8812let isExtentSigned = 1;
8813let opExtentBits = 11;
8814let opExtentAlign = 2;
8815}
8816def J4_tstbit0_tp1_jump_t : HInst<
8817(outs),
8818(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii),
8819"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii",
8820tc_f999c66e, TypeCJ>, Enc_ad1c74 {
8821let Inst{0-0} = 0b0;
8822let Inst{13-8} = 0b100011;
8823let Inst{31-22} = 0b0001001110;
8824let isPredicated = 1;
8825let isTerminator = 1;
8826let isBranch = 1;
8827let isPredicatedNew = 1;
8828let cofRelax1 = 1;
8829let cofRelax2 = 1;
8830let cofMax1 = 1;
8831let Uses = [P1];
8832let Defs = [P1, PC];
8833let isTaken = Inst{13};
8834let isExtendable = 1;
8835let opExtendable = 1;
8836let isExtentSigned = 1;
8837let opExtentBits = 11;
8838let opExtentAlign = 2;
8839}
8840def L2_deallocframe : HInst<
8841(outs DoubleRegs:$Rdd32),
8842(ins IntRegs:$Rs32),
8843"$Rdd32 = deallocframe($Rs32):raw",
8844tc_e9170fb7, TypeLD>, Enc_3a3d62 {
8845let Inst{13-5} = 0b000000000;
8846let Inst{31-21} = 0b10010000000;
8847let accessSize = DoubleWordAccess;
8848let mayLoad = 1;
8849let Uses = [FRAMEKEY];
8850let Defs = [R29];
8851}
8852def L2_loadalignb_io : HInst<
8853(outs DoubleRegs:$Ryy32),
8854(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii),
8855"$Ryy32 = memb_fifo($Rs32+#$Ii)",
8856tc_fedb7e19, TypeLD>, Enc_a27588 {
8857let Inst{24-21} = 0b0100;
8858let Inst{31-27} = 0b10010;
8859let addrMode = BaseImmOffset;
8860let accessSize = ByteAccess;
8861let mayLoad = 1;
8862let isExtendable = 1;
8863let opExtendable = 3;
8864let isExtentSigned = 1;
8865let opExtentBits = 11;
8866let opExtentAlign = 0;
8867let Constraints = "$Ryy32 = $Ryy32in";
8868}
8869def L2_loadalignb_pbr : HInst<
8870(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8871(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8872"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)",
8873tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8874let Inst{12-5} = 0b00000000;
8875let Inst{31-21} = 0b10011110100;
8876let addrMode = PostInc;
8877let accessSize = ByteAccess;
8878let mayLoad = 1;
8879let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8880}
8881def L2_loadalignb_pci : HInst<
8882(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8883(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
8884"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))",
8885tc_76bb5435, TypeLD>, Enc_74aef2 {
8886let Inst{12-9} = 0b0000;
8887let Inst{31-21} = 0b10011000100;
8888let addrMode = PostInc;
8889let accessSize = ByteAccess;
8890let mayLoad = 1;
8891let Uses = [CS];
8892let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8893}
8894def L2_loadalignb_pcr : HInst<
8895(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8896(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8897"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))",
8898tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8899let Inst{12-5} = 0b00010000;
8900let Inst{31-21} = 0b10011000100;
8901let addrMode = PostInc;
8902let accessSize = ByteAccess;
8903let mayLoad = 1;
8904let Uses = [CS];
8905let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8906}
8907def L2_loadalignb_pi : HInst<
8908(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8909(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii),
8910"$Ryy32 = memb_fifo($Rx32++#$Ii)",
8911tc_1c7522a8, TypeLD>, Enc_6b197f {
8912let Inst{13-9} = 0b00000;
8913let Inst{31-21} = 0b10011010100;
8914let addrMode = PostInc;
8915let accessSize = ByteAccess;
8916let mayLoad = 1;
8917let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8918}
8919def L2_loadalignb_pr : HInst<
8920(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8921(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8922"$Ryy32 = memb_fifo($Rx32++$Mu2)",
8923tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8924let Inst{12-5} = 0b00000000;
8925let Inst{31-21} = 0b10011100100;
8926let addrMode = PostInc;
8927let accessSize = ByteAccess;
8928let mayLoad = 1;
8929let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8930}
8931def L2_loadalignb_zomap : HInst<
8932(outs DoubleRegs:$Ryy32),
8933(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
8934"$Ryy32 = memb_fifo($Rs32)",
8935tc_fedb7e19, TypeMAPPING> {
8936let isPseudo = 1;
8937let isCodeGenOnly = 1;
8938let Constraints = "$Ryy32 = $Ryy32in";
8939}
8940def L2_loadalignh_io : HInst<
8941(outs DoubleRegs:$Ryy32),
8942(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii),
8943"$Ryy32 = memh_fifo($Rs32+#$Ii)",
8944tc_fedb7e19, TypeLD>, Enc_5cd7e9 {
8945let Inst{24-21} = 0b0010;
8946let Inst{31-27} = 0b10010;
8947let addrMode = BaseImmOffset;
8948let accessSize = HalfWordAccess;
8949let mayLoad = 1;
8950let isExtendable = 1;
8951let opExtendable = 3;
8952let isExtentSigned = 1;
8953let opExtentBits = 12;
8954let opExtentAlign = 1;
8955let Constraints = "$Ryy32 = $Ryy32in";
8956}
8957def L2_loadalignh_pbr : HInst<
8958(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8959(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8960"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)",
8961tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8962let Inst{12-5} = 0b00000000;
8963let Inst{31-21} = 0b10011110010;
8964let addrMode = PostInc;
8965let accessSize = HalfWordAccess;
8966let mayLoad = 1;
8967let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8968}
8969def L2_loadalignh_pci : HInst<
8970(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8971(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
8972"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))",
8973tc_76bb5435, TypeLD>, Enc_9e2e1c {
8974let Inst{12-9} = 0b0000;
8975let Inst{31-21} = 0b10011000010;
8976let addrMode = PostInc;
8977let accessSize = HalfWordAccess;
8978let mayLoad = 1;
8979let Uses = [CS];
8980let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8981}
8982def L2_loadalignh_pcr : HInst<
8983(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8984(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
8985"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))",
8986tc_1c7522a8, TypeLD>, Enc_1f5d8f {
8987let Inst{12-5} = 0b00010000;
8988let Inst{31-21} = 0b10011000010;
8989let addrMode = PostInc;
8990let accessSize = HalfWordAccess;
8991let mayLoad = 1;
8992let Uses = [CS];
8993let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
8994}
8995def L2_loadalignh_pi : HInst<
8996(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
8997(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii),
8998"$Ryy32 = memh_fifo($Rx32++#$Ii)",
8999tc_1c7522a8, TypeLD>, Enc_bd1cbc {
9000let Inst{13-9} = 0b00000;
9001let Inst{31-21} = 0b10011010010;
9002let addrMode = PostInc;
9003let accessSize = HalfWordAccess;
9004let mayLoad = 1;
9005let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9006}
9007def L2_loadalignh_pr : HInst<
9008(outs DoubleRegs:$Ryy32, IntRegs:$Rx32),
9009(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2),
9010"$Ryy32 = memh_fifo($Rx32++$Mu2)",
9011tc_1c7522a8, TypeLD>, Enc_1f5d8f {
9012let Inst{12-5} = 0b00000000;
9013let Inst{31-21} = 0b10011100010;
9014let addrMode = PostInc;
9015let accessSize = HalfWordAccess;
9016let mayLoad = 1;
9017let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in";
9018}
9019def L2_loadalignh_zomap : HInst<
9020(outs DoubleRegs:$Ryy32),
9021(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32),
9022"$Ryy32 = memh_fifo($Rs32)",
9023tc_fedb7e19, TypeMAPPING> {
9024let isPseudo = 1;
9025let isCodeGenOnly = 1;
9026let Constraints = "$Ryy32 = $Ryy32in";
9027}
9028def L2_loadbsw2_io : HInst<
9029(outs IntRegs:$Rd32),
9030(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9031"$Rd32 = membh($Rs32+#$Ii)",
9032tc_4222e6bf, TypeLD>, Enc_de0214 {
9033let Inst{24-21} = 0b0001;
9034let Inst{31-27} = 0b10010;
9035let hasNewValue = 1;
9036let opNewValue = 0;
9037let addrMode = BaseImmOffset;
9038let accessSize = HalfWordAccess;
9039let mayLoad = 1;
9040let isExtendable = 1;
9041let opExtendable = 2;
9042let isExtentSigned = 1;
9043let opExtentBits = 12;
9044let opExtentAlign = 1;
9045}
9046def L2_loadbsw2_pbr : HInst<
9047(outs IntRegs:$Rd32, IntRegs:$Rx32),
9048(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9049"$Rd32 = membh($Rx32++$Mu2:brev)",
9050tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9051let Inst{12-5} = 0b00000000;
9052let Inst{31-21} = 0b10011110001;
9053let hasNewValue = 1;
9054let opNewValue = 0;
9055let addrMode = PostInc;
9056let accessSize = HalfWordAccess;
9057let mayLoad = 1;
9058let Constraints = "$Rx32 = $Rx32in";
9059}
9060def L2_loadbsw2_pci : HInst<
9061(outs IntRegs:$Rd32, IntRegs:$Rx32),
9062(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9063"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))",
9064tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9065let Inst{12-9} = 0b0000;
9066let Inst{31-21} = 0b10011000001;
9067let hasNewValue = 1;
9068let opNewValue = 0;
9069let addrMode = PostInc;
9070let accessSize = HalfWordAccess;
9071let mayLoad = 1;
9072let Uses = [CS];
9073let Constraints = "$Rx32 = $Rx32in";
9074}
9075def L2_loadbsw2_pcr : HInst<
9076(outs IntRegs:$Rd32, IntRegs:$Rx32),
9077(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9078"$Rd32 = membh($Rx32++I:circ($Mu2))",
9079tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9080let Inst{12-5} = 0b00010000;
9081let Inst{31-21} = 0b10011000001;
9082let hasNewValue = 1;
9083let opNewValue = 0;
9084let addrMode = PostInc;
9085let accessSize = HalfWordAccess;
9086let mayLoad = 1;
9087let Uses = [CS];
9088let Constraints = "$Rx32 = $Rx32in";
9089}
9090def L2_loadbsw2_pi : HInst<
9091(outs IntRegs:$Rd32, IntRegs:$Rx32),
9092(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9093"$Rd32 = membh($Rx32++#$Ii)",
9094tc_075c8dd8, TypeLD>, Enc_152467 {
9095let Inst{13-9} = 0b00000;
9096let Inst{31-21} = 0b10011010001;
9097let hasNewValue = 1;
9098let opNewValue = 0;
9099let addrMode = PostInc;
9100let accessSize = HalfWordAccess;
9101let mayLoad = 1;
9102let Constraints = "$Rx32 = $Rx32in";
9103}
9104def L2_loadbsw2_pr : HInst<
9105(outs IntRegs:$Rd32, IntRegs:$Rx32),
9106(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9107"$Rd32 = membh($Rx32++$Mu2)",
9108tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9109let Inst{12-5} = 0b00000000;
9110let Inst{31-21} = 0b10011100001;
9111let hasNewValue = 1;
9112let opNewValue = 0;
9113let addrMode = PostInc;
9114let accessSize = HalfWordAccess;
9115let mayLoad = 1;
9116let Constraints = "$Rx32 = $Rx32in";
9117}
9118def L2_loadbsw2_zomap : HInst<
9119(outs IntRegs:$Rd32),
9120(ins IntRegs:$Rs32),
9121"$Rd32 = membh($Rs32)",
9122tc_4222e6bf, TypeMAPPING> {
9123let hasNewValue = 1;
9124let opNewValue = 0;
9125let isPseudo = 1;
9126let isCodeGenOnly = 1;
9127}
9128def L2_loadbsw4_io : HInst<
9129(outs DoubleRegs:$Rdd32),
9130(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9131"$Rdd32 = membh($Rs32+#$Ii)",
9132tc_4222e6bf, TypeLD>, Enc_2d7491 {
9133let Inst{24-21} = 0b0111;
9134let Inst{31-27} = 0b10010;
9135let addrMode = BaseImmOffset;
9136let accessSize = WordAccess;
9137let mayLoad = 1;
9138let isExtendable = 1;
9139let opExtendable = 2;
9140let isExtentSigned = 1;
9141let opExtentBits = 13;
9142let opExtentAlign = 2;
9143}
9144def L2_loadbsw4_pbr : HInst<
9145(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9146(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9147"$Rdd32 = membh($Rx32++$Mu2:brev)",
9148tc_075c8dd8, TypeLD>, Enc_7eee72 {
9149let Inst{12-5} = 0b00000000;
9150let Inst{31-21} = 0b10011110111;
9151let addrMode = PostInc;
9152let accessSize = WordAccess;
9153let mayLoad = 1;
9154let Constraints = "$Rx32 = $Rx32in";
9155}
9156def L2_loadbsw4_pci : HInst<
9157(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9158(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9159"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))",
9160tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9161let Inst{12-9} = 0b0000;
9162let Inst{31-21} = 0b10011000111;
9163let addrMode = PostInc;
9164let accessSize = WordAccess;
9165let mayLoad = 1;
9166let Uses = [CS];
9167let Constraints = "$Rx32 = $Rx32in";
9168}
9169def L2_loadbsw4_pcr : HInst<
9170(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9171(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9172"$Rdd32 = membh($Rx32++I:circ($Mu2))",
9173tc_075c8dd8, TypeLD>, Enc_7eee72 {
9174let Inst{12-5} = 0b00010000;
9175let Inst{31-21} = 0b10011000111;
9176let addrMode = PostInc;
9177let accessSize = WordAccess;
9178let mayLoad = 1;
9179let Uses = [CS];
9180let Constraints = "$Rx32 = $Rx32in";
9181}
9182def L2_loadbsw4_pi : HInst<
9183(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9184(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9185"$Rdd32 = membh($Rx32++#$Ii)",
9186tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9187let Inst{13-9} = 0b00000;
9188let Inst{31-21} = 0b10011010111;
9189let addrMode = PostInc;
9190let accessSize = WordAccess;
9191let mayLoad = 1;
9192let Constraints = "$Rx32 = $Rx32in";
9193}
9194def L2_loadbsw4_pr : HInst<
9195(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9196(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9197"$Rdd32 = membh($Rx32++$Mu2)",
9198tc_075c8dd8, TypeLD>, Enc_7eee72 {
9199let Inst{12-5} = 0b00000000;
9200let Inst{31-21} = 0b10011100111;
9201let addrMode = PostInc;
9202let accessSize = WordAccess;
9203let mayLoad = 1;
9204let Constraints = "$Rx32 = $Rx32in";
9205}
9206def L2_loadbsw4_zomap : HInst<
9207(outs DoubleRegs:$Rdd32),
9208(ins IntRegs:$Rs32),
9209"$Rdd32 = membh($Rs32)",
9210tc_4222e6bf, TypeMAPPING> {
9211let isPseudo = 1;
9212let isCodeGenOnly = 1;
9213}
9214def L2_loadbzw2_io : HInst<
9215(outs IntRegs:$Rd32),
9216(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9217"$Rd32 = memubh($Rs32+#$Ii)",
9218tc_4222e6bf, TypeLD>, Enc_de0214 {
9219let Inst{24-21} = 0b0011;
9220let Inst{31-27} = 0b10010;
9221let hasNewValue = 1;
9222let opNewValue = 0;
9223let addrMode = BaseImmOffset;
9224let accessSize = HalfWordAccess;
9225let mayLoad = 1;
9226let isExtendable = 1;
9227let opExtendable = 2;
9228let isExtentSigned = 1;
9229let opExtentBits = 12;
9230let opExtentAlign = 1;
9231}
9232def L2_loadbzw2_pbr : HInst<
9233(outs IntRegs:$Rd32, IntRegs:$Rx32),
9234(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9235"$Rd32 = memubh($Rx32++$Mu2:brev)",
9236tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9237let Inst{12-5} = 0b00000000;
9238let Inst{31-21} = 0b10011110011;
9239let hasNewValue = 1;
9240let opNewValue = 0;
9241let addrMode = PostInc;
9242let accessSize = HalfWordAccess;
9243let mayLoad = 1;
9244let Constraints = "$Rx32 = $Rx32in";
9245}
9246def L2_loadbzw2_pci : HInst<
9247(outs IntRegs:$Rd32, IntRegs:$Rx32),
9248(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9249"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9250tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9251let Inst{12-9} = 0b0000;
9252let Inst{31-21} = 0b10011000011;
9253let hasNewValue = 1;
9254let opNewValue = 0;
9255let addrMode = PostInc;
9256let accessSize = HalfWordAccess;
9257let mayLoad = 1;
9258let Uses = [CS];
9259let Constraints = "$Rx32 = $Rx32in";
9260}
9261def L2_loadbzw2_pcr : HInst<
9262(outs IntRegs:$Rd32, IntRegs:$Rx32),
9263(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9264"$Rd32 = memubh($Rx32++I:circ($Mu2))",
9265tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9266let Inst{12-5} = 0b00010000;
9267let Inst{31-21} = 0b10011000011;
9268let hasNewValue = 1;
9269let opNewValue = 0;
9270let addrMode = PostInc;
9271let accessSize = HalfWordAccess;
9272let mayLoad = 1;
9273let Uses = [CS];
9274let Constraints = "$Rx32 = $Rx32in";
9275}
9276def L2_loadbzw2_pi : HInst<
9277(outs IntRegs:$Rd32, IntRegs:$Rx32),
9278(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9279"$Rd32 = memubh($Rx32++#$Ii)",
9280tc_075c8dd8, TypeLD>, Enc_152467 {
9281let Inst{13-9} = 0b00000;
9282let Inst{31-21} = 0b10011010011;
9283let hasNewValue = 1;
9284let opNewValue = 0;
9285let addrMode = PostInc;
9286let accessSize = HalfWordAccess;
9287let mayLoad = 1;
9288let Constraints = "$Rx32 = $Rx32in";
9289}
9290def L2_loadbzw2_pr : HInst<
9291(outs IntRegs:$Rd32, IntRegs:$Rx32),
9292(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9293"$Rd32 = memubh($Rx32++$Mu2)",
9294tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9295let Inst{12-5} = 0b00000000;
9296let Inst{31-21} = 0b10011100011;
9297let hasNewValue = 1;
9298let opNewValue = 0;
9299let addrMode = PostInc;
9300let accessSize = HalfWordAccess;
9301let mayLoad = 1;
9302let Constraints = "$Rx32 = $Rx32in";
9303}
9304def L2_loadbzw2_zomap : HInst<
9305(outs IntRegs:$Rd32),
9306(ins IntRegs:$Rs32),
9307"$Rd32 = memubh($Rs32)",
9308tc_4222e6bf, TypeMAPPING> {
9309let hasNewValue = 1;
9310let opNewValue = 0;
9311let isPseudo = 1;
9312let isCodeGenOnly = 1;
9313}
9314def L2_loadbzw4_io : HInst<
9315(outs DoubleRegs:$Rdd32),
9316(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9317"$Rdd32 = memubh($Rs32+#$Ii)",
9318tc_4222e6bf, TypeLD>, Enc_2d7491 {
9319let Inst{24-21} = 0b0101;
9320let Inst{31-27} = 0b10010;
9321let addrMode = BaseImmOffset;
9322let accessSize = WordAccess;
9323let mayLoad = 1;
9324let isExtendable = 1;
9325let opExtendable = 2;
9326let isExtentSigned = 1;
9327let opExtentBits = 13;
9328let opExtentAlign = 2;
9329}
9330def L2_loadbzw4_pbr : HInst<
9331(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9332(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9333"$Rdd32 = memubh($Rx32++$Mu2:brev)",
9334tc_075c8dd8, TypeLD>, Enc_7eee72 {
9335let Inst{12-5} = 0b00000000;
9336let Inst{31-21} = 0b10011110101;
9337let addrMode = PostInc;
9338let accessSize = WordAccess;
9339let mayLoad = 1;
9340let Constraints = "$Rx32 = $Rx32in";
9341}
9342def L2_loadbzw4_pci : HInst<
9343(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9344(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9345"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))",
9346tc_5ceb2f9e, TypeLD>, Enc_70b24b {
9347let Inst{12-9} = 0b0000;
9348let Inst{31-21} = 0b10011000101;
9349let addrMode = PostInc;
9350let accessSize = WordAccess;
9351let mayLoad = 1;
9352let Uses = [CS];
9353let Constraints = "$Rx32 = $Rx32in";
9354}
9355def L2_loadbzw4_pcr : HInst<
9356(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9357(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9358"$Rdd32 = memubh($Rx32++I:circ($Mu2))",
9359tc_075c8dd8, TypeLD>, Enc_7eee72 {
9360let Inst{12-5} = 0b00010000;
9361let Inst{31-21} = 0b10011000101;
9362let addrMode = PostInc;
9363let accessSize = WordAccess;
9364let mayLoad = 1;
9365let Uses = [CS];
9366let Constraints = "$Rx32 = $Rx32in";
9367}
9368def L2_loadbzw4_pi : HInst<
9369(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9370(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9371"$Rdd32 = memubh($Rx32++#$Ii)",
9372tc_075c8dd8, TypeLD>, Enc_71f1b4 {
9373let Inst{13-9} = 0b00000;
9374let Inst{31-21} = 0b10011010101;
9375let addrMode = PostInc;
9376let accessSize = WordAccess;
9377let mayLoad = 1;
9378let Constraints = "$Rx32 = $Rx32in";
9379}
9380def L2_loadbzw4_pr : HInst<
9381(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9382(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9383"$Rdd32 = memubh($Rx32++$Mu2)",
9384tc_075c8dd8, TypeLD>, Enc_7eee72 {
9385let Inst{12-5} = 0b00000000;
9386let Inst{31-21} = 0b10011100101;
9387let addrMode = PostInc;
9388let accessSize = WordAccess;
9389let mayLoad = 1;
9390let Constraints = "$Rx32 = $Rx32in";
9391}
9392def L2_loadbzw4_zomap : HInst<
9393(outs DoubleRegs:$Rdd32),
9394(ins IntRegs:$Rs32),
9395"$Rdd32 = memubh($Rs32)",
9396tc_4222e6bf, TypeMAPPING> {
9397let isPseudo = 1;
9398let isCodeGenOnly = 1;
9399}
9400def L2_loadrb_io : HInst<
9401(outs IntRegs:$Rd32),
9402(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9403"$Rd32 = memb($Rs32+#$Ii)",
9404tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9405let Inst{24-21} = 0b1000;
9406let Inst{31-27} = 0b10010;
9407let hasNewValue = 1;
9408let opNewValue = 0;
9409let addrMode = BaseImmOffset;
9410let accessSize = ByteAccess;
9411let mayLoad = 1;
9412let BaseOpcode = "L2_loadrb_io";
9413let CextOpcode = "L2_loadrb";
9414let isPredicable = 1;
9415let isExtendable = 1;
9416let opExtendable = 2;
9417let isExtentSigned = 1;
9418let opExtentBits = 11;
9419let opExtentAlign = 0;
9420}
9421def L2_loadrb_pbr : HInst<
9422(outs IntRegs:$Rd32, IntRegs:$Rx32),
9423(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9424"$Rd32 = memb($Rx32++$Mu2:brev)",
9425tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9426let Inst{12-5} = 0b00000000;
9427let Inst{31-21} = 0b10011111000;
9428let hasNewValue = 1;
9429let opNewValue = 0;
9430let addrMode = PostInc;
9431let accessSize = ByteAccess;
9432let mayLoad = 1;
9433let Constraints = "$Rx32 = $Rx32in";
9434}
9435def L2_loadrb_pci : HInst<
9436(outs IntRegs:$Rd32, IntRegs:$Rx32),
9437(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9438"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))",
9439tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9440let Inst{12-9} = 0b0000;
9441let Inst{31-21} = 0b10011001000;
9442let hasNewValue = 1;
9443let opNewValue = 0;
9444let addrMode = PostInc;
9445let accessSize = ByteAccess;
9446let mayLoad = 1;
9447let Uses = [CS];
9448let Constraints = "$Rx32 = $Rx32in";
9449}
9450def L2_loadrb_pcr : HInst<
9451(outs IntRegs:$Rd32, IntRegs:$Rx32),
9452(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9453"$Rd32 = memb($Rx32++I:circ($Mu2))",
9454tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9455let Inst{12-5} = 0b00010000;
9456let Inst{31-21} = 0b10011001000;
9457let hasNewValue = 1;
9458let opNewValue = 0;
9459let addrMode = PostInc;
9460let accessSize = ByteAccess;
9461let mayLoad = 1;
9462let Uses = [CS];
9463let Constraints = "$Rx32 = $Rx32in";
9464}
9465def L2_loadrb_pi : HInst<
9466(outs IntRegs:$Rd32, IntRegs:$Rx32),
9467(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9468"$Rd32 = memb($Rx32++#$Ii)",
9469tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9470let Inst{13-9} = 0b00000;
9471let Inst{31-21} = 0b10011011000;
9472let hasNewValue = 1;
9473let opNewValue = 0;
9474let addrMode = PostInc;
9475let accessSize = ByteAccess;
9476let mayLoad = 1;
9477let BaseOpcode = "L2_loadrb_pi";
9478let CextOpcode = "L2_loadrb";
9479let isPredicable = 1;
9480let Constraints = "$Rx32 = $Rx32in";
9481}
9482def L2_loadrb_pr : HInst<
9483(outs IntRegs:$Rd32, IntRegs:$Rx32),
9484(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9485"$Rd32 = memb($Rx32++$Mu2)",
9486tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9487let Inst{12-5} = 0b00000000;
9488let Inst{31-21} = 0b10011101000;
9489let hasNewValue = 1;
9490let opNewValue = 0;
9491let addrMode = PostInc;
9492let accessSize = ByteAccess;
9493let mayLoad = 1;
9494let Constraints = "$Rx32 = $Rx32in";
9495}
9496def L2_loadrb_zomap : HInst<
9497(outs IntRegs:$Rd32),
9498(ins IntRegs:$Rs32),
9499"$Rd32 = memb($Rs32)",
9500tc_4222e6bf, TypeMAPPING> {
9501let hasNewValue = 1;
9502let opNewValue = 0;
9503let isPseudo = 1;
9504let isCodeGenOnly = 1;
9505}
9506def L2_loadrbgp : HInst<
9507(outs IntRegs:$Rd32),
9508(ins u32_0Imm:$Ii),
9509"$Rd32 = memb(gp+#$Ii)",
9510tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9511let Inst{24-21} = 0b1000;
9512let Inst{31-27} = 0b01001;
9513let hasNewValue = 1;
9514let opNewValue = 0;
9515let accessSize = ByteAccess;
9516let mayLoad = 1;
9517let Uses = [GP];
9518let BaseOpcode = "L4_loadrb_abs";
9519let isPredicable = 1;
9520let opExtendable = 1;
9521let isExtentSigned = 0;
9522let opExtentBits = 16;
9523let opExtentAlign = 0;
9524}
9525def L2_loadrd_io : HInst<
9526(outs DoubleRegs:$Rdd32),
9527(ins IntRegs:$Rs32, s29_3Imm:$Ii),
9528"$Rdd32 = memd($Rs32+#$Ii)",
9529tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm {
9530let Inst{24-21} = 0b1110;
9531let Inst{31-27} = 0b10010;
9532let addrMode = BaseImmOffset;
9533let accessSize = DoubleWordAccess;
9534let mayLoad = 1;
9535let BaseOpcode = "L2_loadrd_io";
9536let CextOpcode = "L2_loadrd";
9537let isPredicable = 1;
9538let isExtendable = 1;
9539let opExtendable = 2;
9540let isExtentSigned = 1;
9541let opExtentBits = 14;
9542let opExtentAlign = 3;
9543}
9544def L2_loadrd_pbr : HInst<
9545(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9546(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9547"$Rdd32 = memd($Rx32++$Mu2:brev)",
9548tc_075c8dd8, TypeLD>, Enc_7eee72 {
9549let Inst{12-5} = 0b00000000;
9550let Inst{31-21} = 0b10011111110;
9551let addrMode = PostInc;
9552let accessSize = DoubleWordAccess;
9553let mayLoad = 1;
9554let Constraints = "$Rx32 = $Rx32in";
9555}
9556def L2_loadrd_pci : HInst<
9557(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9558(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2),
9559"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))",
9560tc_5ceb2f9e, TypeLD>, Enc_b05839 {
9561let Inst{12-9} = 0b0000;
9562let Inst{31-21} = 0b10011001110;
9563let addrMode = PostInc;
9564let accessSize = DoubleWordAccess;
9565let mayLoad = 1;
9566let Uses = [CS];
9567let Constraints = "$Rx32 = $Rx32in";
9568}
9569def L2_loadrd_pcr : HInst<
9570(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9571(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9572"$Rdd32 = memd($Rx32++I:circ($Mu2))",
9573tc_075c8dd8, TypeLD>, Enc_7eee72 {
9574let Inst{12-5} = 0b00010000;
9575let Inst{31-21} = 0b10011001110;
9576let addrMode = PostInc;
9577let accessSize = DoubleWordAccess;
9578let mayLoad = 1;
9579let Uses = [CS];
9580let Constraints = "$Rx32 = $Rx32in";
9581}
9582def L2_loadrd_pi : HInst<
9583(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9584(ins IntRegs:$Rx32in, s4_3Imm:$Ii),
9585"$Rdd32 = memd($Rx32++#$Ii)",
9586tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm {
9587let Inst{13-9} = 0b00000;
9588let Inst{31-21} = 0b10011011110;
9589let addrMode = PostInc;
9590let accessSize = DoubleWordAccess;
9591let mayLoad = 1;
9592let BaseOpcode = "L2_loadrd_pi";
9593let CextOpcode = "L2_loadrd";
9594let isPredicable = 1;
9595let Constraints = "$Rx32 = $Rx32in";
9596}
9597def L2_loadrd_pr : HInst<
9598(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
9599(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9600"$Rdd32 = memd($Rx32++$Mu2)",
9601tc_075c8dd8, TypeLD>, Enc_7eee72 {
9602let Inst{12-5} = 0b00000000;
9603let Inst{31-21} = 0b10011101110;
9604let addrMode = PostInc;
9605let accessSize = DoubleWordAccess;
9606let mayLoad = 1;
9607let Constraints = "$Rx32 = $Rx32in";
9608}
9609def L2_loadrd_zomap : HInst<
9610(outs DoubleRegs:$Rdd32),
9611(ins IntRegs:$Rs32),
9612"$Rdd32 = memd($Rs32)",
9613tc_4222e6bf, TypeMAPPING> {
9614let isPseudo = 1;
9615let isCodeGenOnly = 1;
9616}
9617def L2_loadrdgp : HInst<
9618(outs DoubleRegs:$Rdd32),
9619(ins u29_3Imm:$Ii),
9620"$Rdd32 = memd(gp+#$Ii)",
9621tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
9622let Inst{24-21} = 0b1110;
9623let Inst{31-27} = 0b01001;
9624let accessSize = DoubleWordAccess;
9625let mayLoad = 1;
9626let Uses = [GP];
9627let BaseOpcode = "L4_loadrd_abs";
9628let isPredicable = 1;
9629let opExtendable = 1;
9630let isExtentSigned = 0;
9631let opExtentBits = 19;
9632let opExtentAlign = 3;
9633}
9634def L2_loadrh_io : HInst<
9635(outs IntRegs:$Rd32),
9636(ins IntRegs:$Rs32, s31_1Imm:$Ii),
9637"$Rd32 = memh($Rs32+#$Ii)",
9638tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
9639let Inst{24-21} = 0b1010;
9640let Inst{31-27} = 0b10010;
9641let hasNewValue = 1;
9642let opNewValue = 0;
9643let addrMode = BaseImmOffset;
9644let accessSize = HalfWordAccess;
9645let mayLoad = 1;
9646let BaseOpcode = "L2_loadrh_io";
9647let CextOpcode = "L2_loadrh";
9648let isPredicable = 1;
9649let isExtendable = 1;
9650let opExtendable = 2;
9651let isExtentSigned = 1;
9652let opExtentBits = 12;
9653let opExtentAlign = 1;
9654}
9655def L2_loadrh_pbr : HInst<
9656(outs IntRegs:$Rd32, IntRegs:$Rx32),
9657(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9658"$Rd32 = memh($Rx32++$Mu2:brev)",
9659tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9660let Inst{12-5} = 0b00000000;
9661let Inst{31-21} = 0b10011111010;
9662let hasNewValue = 1;
9663let opNewValue = 0;
9664let addrMode = PostInc;
9665let accessSize = HalfWordAccess;
9666let mayLoad = 1;
9667let Constraints = "$Rx32 = $Rx32in";
9668}
9669def L2_loadrh_pci : HInst<
9670(outs IntRegs:$Rd32, IntRegs:$Rx32),
9671(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
9672"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))",
9673tc_5ceb2f9e, TypeLD>, Enc_e83554 {
9674let Inst{12-9} = 0b0000;
9675let Inst{31-21} = 0b10011001010;
9676let hasNewValue = 1;
9677let opNewValue = 0;
9678let addrMode = PostInc;
9679let accessSize = HalfWordAccess;
9680let mayLoad = 1;
9681let Uses = [CS];
9682let Constraints = "$Rx32 = $Rx32in";
9683}
9684def L2_loadrh_pcr : HInst<
9685(outs IntRegs:$Rd32, IntRegs:$Rx32),
9686(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9687"$Rd32 = memh($Rx32++I:circ($Mu2))",
9688tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9689let Inst{12-5} = 0b00010000;
9690let Inst{31-21} = 0b10011001010;
9691let hasNewValue = 1;
9692let opNewValue = 0;
9693let addrMode = PostInc;
9694let accessSize = HalfWordAccess;
9695let mayLoad = 1;
9696let Uses = [CS];
9697let Constraints = "$Rx32 = $Rx32in";
9698}
9699def L2_loadrh_pi : HInst<
9700(outs IntRegs:$Rd32, IntRegs:$Rx32),
9701(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
9702"$Rd32 = memh($Rx32++#$Ii)",
9703tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
9704let Inst{13-9} = 0b00000;
9705let Inst{31-21} = 0b10011011010;
9706let hasNewValue = 1;
9707let opNewValue = 0;
9708let addrMode = PostInc;
9709let accessSize = HalfWordAccess;
9710let mayLoad = 1;
9711let BaseOpcode = "L2_loadrh_pi";
9712let CextOpcode = "L2_loadrh";
9713let isPredicable = 1;
9714let Constraints = "$Rx32 = $Rx32in";
9715}
9716def L2_loadrh_pr : HInst<
9717(outs IntRegs:$Rd32, IntRegs:$Rx32),
9718(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9719"$Rd32 = memh($Rx32++$Mu2)",
9720tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9721let Inst{12-5} = 0b00000000;
9722let Inst{31-21} = 0b10011101010;
9723let hasNewValue = 1;
9724let opNewValue = 0;
9725let addrMode = PostInc;
9726let accessSize = HalfWordAccess;
9727let mayLoad = 1;
9728let Constraints = "$Rx32 = $Rx32in";
9729}
9730def L2_loadrh_zomap : HInst<
9731(outs IntRegs:$Rd32),
9732(ins IntRegs:$Rs32),
9733"$Rd32 = memh($Rs32)",
9734tc_4222e6bf, TypeMAPPING> {
9735let hasNewValue = 1;
9736let opNewValue = 0;
9737let isPseudo = 1;
9738let isCodeGenOnly = 1;
9739}
9740def L2_loadrhgp : HInst<
9741(outs IntRegs:$Rd32),
9742(ins u31_1Imm:$Ii),
9743"$Rd32 = memh(gp+#$Ii)",
9744tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
9745let Inst{24-21} = 0b1010;
9746let Inst{31-27} = 0b01001;
9747let hasNewValue = 1;
9748let opNewValue = 0;
9749let accessSize = HalfWordAccess;
9750let mayLoad = 1;
9751let Uses = [GP];
9752let BaseOpcode = "L4_loadrh_abs";
9753let isPredicable = 1;
9754let opExtendable = 1;
9755let isExtentSigned = 0;
9756let opExtentBits = 17;
9757let opExtentAlign = 1;
9758}
9759def L2_loadri_io : HInst<
9760(outs IntRegs:$Rd32),
9761(ins IntRegs:$Rs32, s30_2Imm:$Ii),
9762"$Rd32 = memw($Rs32+#$Ii)",
9763tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm {
9764let Inst{24-21} = 0b1100;
9765let Inst{31-27} = 0b10010;
9766let hasNewValue = 1;
9767let opNewValue = 0;
9768let addrMode = BaseImmOffset;
9769let accessSize = WordAccess;
9770let mayLoad = 1;
9771let BaseOpcode = "L2_loadri_io";
9772let CextOpcode = "L2_loadri";
9773let isPredicable = 1;
9774let isExtendable = 1;
9775let opExtendable = 2;
9776let isExtentSigned = 1;
9777let opExtentBits = 13;
9778let opExtentAlign = 2;
9779}
9780def L2_loadri_pbr : HInst<
9781(outs IntRegs:$Rd32, IntRegs:$Rx32),
9782(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9783"$Rd32 = memw($Rx32++$Mu2:brev)",
9784tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9785let Inst{12-5} = 0b00000000;
9786let Inst{31-21} = 0b10011111100;
9787let hasNewValue = 1;
9788let opNewValue = 0;
9789let addrMode = PostInc;
9790let accessSize = WordAccess;
9791let mayLoad = 1;
9792let Constraints = "$Rx32 = $Rx32in";
9793}
9794def L2_loadri_pci : HInst<
9795(outs IntRegs:$Rd32, IntRegs:$Rx32),
9796(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2),
9797"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))",
9798tc_5ceb2f9e, TypeLD>, Enc_27fd0e {
9799let Inst{12-9} = 0b0000;
9800let Inst{31-21} = 0b10011001100;
9801let hasNewValue = 1;
9802let opNewValue = 0;
9803let addrMode = PostInc;
9804let accessSize = WordAccess;
9805let mayLoad = 1;
9806let Uses = [CS];
9807let Constraints = "$Rx32 = $Rx32in";
9808}
9809def L2_loadri_pcr : HInst<
9810(outs IntRegs:$Rd32, IntRegs:$Rx32),
9811(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9812"$Rd32 = memw($Rx32++I:circ($Mu2))",
9813tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9814let Inst{12-5} = 0b00010000;
9815let Inst{31-21} = 0b10011001100;
9816let hasNewValue = 1;
9817let opNewValue = 0;
9818let addrMode = PostInc;
9819let accessSize = WordAccess;
9820let mayLoad = 1;
9821let Uses = [CS];
9822let Constraints = "$Rx32 = $Rx32in";
9823}
9824def L2_loadri_pi : HInst<
9825(outs IntRegs:$Rd32, IntRegs:$Rx32),
9826(ins IntRegs:$Rx32in, s4_2Imm:$Ii),
9827"$Rd32 = memw($Rx32++#$Ii)",
9828tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm {
9829let Inst{13-9} = 0b00000;
9830let Inst{31-21} = 0b10011011100;
9831let hasNewValue = 1;
9832let opNewValue = 0;
9833let addrMode = PostInc;
9834let accessSize = WordAccess;
9835let mayLoad = 1;
9836let BaseOpcode = "L2_loadri_pi";
9837let CextOpcode = "L2_loadri";
9838let isPredicable = 1;
9839let Constraints = "$Rx32 = $Rx32in";
9840}
9841def L2_loadri_pr : HInst<
9842(outs IntRegs:$Rd32, IntRegs:$Rx32),
9843(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9844"$Rd32 = memw($Rx32++$Mu2)",
9845tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9846let Inst{12-5} = 0b00000000;
9847let Inst{31-21} = 0b10011101100;
9848let hasNewValue = 1;
9849let opNewValue = 0;
9850let addrMode = PostInc;
9851let accessSize = WordAccess;
9852let mayLoad = 1;
9853let Constraints = "$Rx32 = $Rx32in";
9854}
9855def L2_loadri_zomap : HInst<
9856(outs IntRegs:$Rd32),
9857(ins IntRegs:$Rs32),
9858"$Rd32 = memw($Rs32)",
9859tc_4222e6bf, TypeMAPPING> {
9860let hasNewValue = 1;
9861let opNewValue = 0;
9862let isPseudo = 1;
9863let isCodeGenOnly = 1;
9864}
9865def L2_loadrigp : HInst<
9866(outs IntRegs:$Rd32),
9867(ins u30_2Imm:$Ii),
9868"$Rd32 = memw(gp+#$Ii)",
9869tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
9870let Inst{24-21} = 0b1100;
9871let Inst{31-27} = 0b01001;
9872let hasNewValue = 1;
9873let opNewValue = 0;
9874let accessSize = WordAccess;
9875let mayLoad = 1;
9876let Uses = [GP];
9877let BaseOpcode = "L4_loadri_abs";
9878let isPredicable = 1;
9879let opExtendable = 1;
9880let isExtentSigned = 0;
9881let opExtentBits = 18;
9882let opExtentAlign = 2;
9883}
9884def L2_loadrub_io : HInst<
9885(outs IntRegs:$Rd32),
9886(ins IntRegs:$Rs32, s32_0Imm:$Ii),
9887"$Rd32 = memub($Rs32+#$Ii)",
9888tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm {
9889let Inst{24-21} = 0b1001;
9890let Inst{31-27} = 0b10010;
9891let hasNewValue = 1;
9892let opNewValue = 0;
9893let addrMode = BaseImmOffset;
9894let accessSize = ByteAccess;
9895let mayLoad = 1;
9896let BaseOpcode = "L2_loadrub_io";
9897let CextOpcode = "L2_loadrub";
9898let isPredicable = 1;
9899let isExtendable = 1;
9900let opExtendable = 2;
9901let isExtentSigned = 1;
9902let opExtentBits = 11;
9903let opExtentAlign = 0;
9904}
9905def L2_loadrub_pbr : HInst<
9906(outs IntRegs:$Rd32, IntRegs:$Rx32),
9907(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9908"$Rd32 = memub($Rx32++$Mu2:brev)",
9909tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9910let Inst{12-5} = 0b00000000;
9911let Inst{31-21} = 0b10011111001;
9912let hasNewValue = 1;
9913let opNewValue = 0;
9914let addrMode = PostInc;
9915let accessSize = ByteAccess;
9916let mayLoad = 1;
9917let Constraints = "$Rx32 = $Rx32in";
9918}
9919def L2_loadrub_pci : HInst<
9920(outs IntRegs:$Rd32, IntRegs:$Rx32),
9921(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2),
9922"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))",
9923tc_5ceb2f9e, TypeLD>, Enc_e0a47a {
9924let Inst{12-9} = 0b0000;
9925let Inst{31-21} = 0b10011001001;
9926let hasNewValue = 1;
9927let opNewValue = 0;
9928let addrMode = PostInc;
9929let accessSize = ByteAccess;
9930let mayLoad = 1;
9931let Uses = [CS];
9932let Constraints = "$Rx32 = $Rx32in";
9933}
9934def L2_loadrub_pcr : HInst<
9935(outs IntRegs:$Rd32, IntRegs:$Rx32),
9936(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9937"$Rd32 = memub($Rx32++I:circ($Mu2))",
9938tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9939let Inst{12-5} = 0b00010000;
9940let Inst{31-21} = 0b10011001001;
9941let hasNewValue = 1;
9942let opNewValue = 0;
9943let addrMode = PostInc;
9944let accessSize = ByteAccess;
9945let mayLoad = 1;
9946let Uses = [CS];
9947let Constraints = "$Rx32 = $Rx32in";
9948}
9949def L2_loadrub_pi : HInst<
9950(outs IntRegs:$Rd32, IntRegs:$Rx32),
9951(ins IntRegs:$Rx32in, s4_0Imm:$Ii),
9952"$Rd32 = memub($Rx32++#$Ii)",
9953tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm {
9954let Inst{13-9} = 0b00000;
9955let Inst{31-21} = 0b10011011001;
9956let hasNewValue = 1;
9957let opNewValue = 0;
9958let addrMode = PostInc;
9959let accessSize = ByteAccess;
9960let mayLoad = 1;
9961let BaseOpcode = "L2_loadrub_pi";
9962let CextOpcode = "L2_loadrub";
9963let isPredicable = 1;
9964let Constraints = "$Rx32 = $Rx32in";
9965}
9966def L2_loadrub_pr : HInst<
9967(outs IntRegs:$Rd32, IntRegs:$Rx32),
9968(ins IntRegs:$Rx32in, ModRegs:$Mu2),
9969"$Rd32 = memub($Rx32++$Mu2)",
9970tc_075c8dd8, TypeLD>, Enc_74d4e5 {
9971let Inst{12-5} = 0b00000000;
9972let Inst{31-21} = 0b10011101001;
9973let hasNewValue = 1;
9974let opNewValue = 0;
9975let addrMode = PostInc;
9976let accessSize = ByteAccess;
9977let mayLoad = 1;
9978let Constraints = "$Rx32 = $Rx32in";
9979}
9980def L2_loadrub_zomap : HInst<
9981(outs IntRegs:$Rd32),
9982(ins IntRegs:$Rs32),
9983"$Rd32 = memub($Rs32)",
9984tc_4222e6bf, TypeMAPPING> {
9985let hasNewValue = 1;
9986let opNewValue = 0;
9987let isPseudo = 1;
9988let isCodeGenOnly = 1;
9989}
9990def L2_loadrubgp : HInst<
9991(outs IntRegs:$Rd32),
9992(ins u32_0Imm:$Ii),
9993"$Rd32 = memub(gp+#$Ii)",
9994tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
9995let Inst{24-21} = 0b1001;
9996let Inst{31-27} = 0b01001;
9997let hasNewValue = 1;
9998let opNewValue = 0;
9999let accessSize = ByteAccess;
10000let mayLoad = 1;
10001let Uses = [GP];
10002let BaseOpcode = "L4_loadrub_abs";
10003let isPredicable = 1;
10004let opExtendable = 1;
10005let isExtentSigned = 0;
10006let opExtentBits = 16;
10007let opExtentAlign = 0;
10008}
10009def L2_loadruh_io : HInst<
10010(outs IntRegs:$Rd32),
10011(ins IntRegs:$Rs32, s31_1Imm:$Ii),
10012"$Rd32 = memuh($Rs32+#$Ii)",
10013tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm {
10014let Inst{24-21} = 0b1011;
10015let Inst{31-27} = 0b10010;
10016let hasNewValue = 1;
10017let opNewValue = 0;
10018let addrMode = BaseImmOffset;
10019let accessSize = HalfWordAccess;
10020let mayLoad = 1;
10021let BaseOpcode = "L2_loadruh_io";
10022let CextOpcode = "L2_loadruh";
10023let isPredicable = 1;
10024let isExtendable = 1;
10025let opExtendable = 2;
10026let isExtentSigned = 1;
10027let opExtentBits = 12;
10028let opExtentAlign = 1;
10029}
10030def L2_loadruh_pbr : HInst<
10031(outs IntRegs:$Rd32, IntRegs:$Rx32),
10032(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10033"$Rd32 = memuh($Rx32++$Mu2:brev)",
10034tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10035let Inst{12-5} = 0b00000000;
10036let Inst{31-21} = 0b10011111011;
10037let hasNewValue = 1;
10038let opNewValue = 0;
10039let addrMode = PostInc;
10040let accessSize = HalfWordAccess;
10041let mayLoad = 1;
10042let Constraints = "$Rx32 = $Rx32in";
10043}
10044def L2_loadruh_pci : HInst<
10045(outs IntRegs:$Rd32, IntRegs:$Rx32),
10046(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2),
10047"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))",
10048tc_5ceb2f9e, TypeLD>, Enc_e83554 {
10049let Inst{12-9} = 0b0000;
10050let Inst{31-21} = 0b10011001011;
10051let hasNewValue = 1;
10052let opNewValue = 0;
10053let addrMode = PostInc;
10054let accessSize = HalfWordAccess;
10055let mayLoad = 1;
10056let Uses = [CS];
10057let Constraints = "$Rx32 = $Rx32in";
10058}
10059def L2_loadruh_pcr : HInst<
10060(outs IntRegs:$Rd32, IntRegs:$Rx32),
10061(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10062"$Rd32 = memuh($Rx32++I:circ($Mu2))",
10063tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10064let Inst{12-5} = 0b00010000;
10065let Inst{31-21} = 0b10011001011;
10066let hasNewValue = 1;
10067let opNewValue = 0;
10068let addrMode = PostInc;
10069let accessSize = HalfWordAccess;
10070let mayLoad = 1;
10071let Uses = [CS];
10072let Constraints = "$Rx32 = $Rx32in";
10073}
10074def L2_loadruh_pi : HInst<
10075(outs IntRegs:$Rd32, IntRegs:$Rx32),
10076(ins IntRegs:$Rx32in, s4_1Imm:$Ii),
10077"$Rd32 = memuh($Rx32++#$Ii)",
10078tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm {
10079let Inst{13-9} = 0b00000;
10080let Inst{31-21} = 0b10011011011;
10081let hasNewValue = 1;
10082let opNewValue = 0;
10083let addrMode = PostInc;
10084let accessSize = HalfWordAccess;
10085let mayLoad = 1;
10086let BaseOpcode = "L2_loadruh_pi";
10087let CextOpcode = "L2_loadruh";
10088let isPredicable = 1;
10089let Constraints = "$Rx32 = $Rx32in";
10090}
10091def L2_loadruh_pr : HInst<
10092(outs IntRegs:$Rd32, IntRegs:$Rx32),
10093(ins IntRegs:$Rx32in, ModRegs:$Mu2),
10094"$Rd32 = memuh($Rx32++$Mu2)",
10095tc_075c8dd8, TypeLD>, Enc_74d4e5 {
10096let Inst{12-5} = 0b00000000;
10097let Inst{31-21} = 0b10011101011;
10098let hasNewValue = 1;
10099let opNewValue = 0;
10100let addrMode = PostInc;
10101let accessSize = HalfWordAccess;
10102let mayLoad = 1;
10103let Constraints = "$Rx32 = $Rx32in";
10104}
10105def L2_loadruh_zomap : HInst<
10106(outs IntRegs:$Rd32),
10107(ins IntRegs:$Rs32),
10108"$Rd32 = memuh($Rs32)",
10109tc_4222e6bf, TypeMAPPING> {
10110let hasNewValue = 1;
10111let opNewValue = 0;
10112let isPseudo = 1;
10113let isCodeGenOnly = 1;
10114}
10115def L2_loadruhgp : HInst<
10116(outs IntRegs:$Rd32),
10117(ins u31_1Imm:$Ii),
10118"$Rd32 = memuh(gp+#$Ii)",
10119tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
10120let Inst{24-21} = 0b1011;
10121let Inst{31-27} = 0b01001;
10122let hasNewValue = 1;
10123let opNewValue = 0;
10124let accessSize = HalfWordAccess;
10125let mayLoad = 1;
10126let Uses = [GP];
10127let BaseOpcode = "L4_loadruh_abs";
10128let isPredicable = 1;
10129let opExtendable = 1;
10130let isExtentSigned = 0;
10131let opExtentBits = 17;
10132let opExtentAlign = 1;
10133}
10134def L2_loadw_aq : HInst<
10135(outs IntRegs:$Rd32),
10136(ins IntRegs:$Rs32),
10137"$Rd32 = memw_aq($Rs32)",
10138tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> {
10139let Inst{13-5} = 0b001000000;
10140let Inst{31-21} = 0b10010010000;
10141let hasNewValue = 1;
10142let opNewValue = 0;
10143let accessSize = WordAccess;
10144let mayLoad = 1;
10145}
10146def L2_loadw_locked : HInst<
10147(outs IntRegs:$Rd32),
10148(ins IntRegs:$Rs32),
10149"$Rd32 = memw_locked($Rs32)",
10150tc_64b00d8a, TypeLD>, Enc_5e2823 {
10151let Inst{13-5} = 0b000000000;
10152let Inst{31-21} = 0b10010010000;
10153let hasNewValue = 1;
10154let opNewValue = 0;
10155let accessSize = WordAccess;
10156let mayLoad = 1;
10157let isSoloAX = 1;
10158}
10159def L2_ploadrbf_io : HInst<
10160(outs IntRegs:$Rd32),
10161(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10162"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)",
10163tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10164let Inst{13-13} = 0b0;
10165let Inst{31-21} = 0b01000101000;
10166let isPredicated = 1;
10167let isPredicatedFalse = 1;
10168let hasNewValue = 1;
10169let opNewValue = 0;
10170let addrMode = BaseImmOffset;
10171let accessSize = ByteAccess;
10172let mayLoad = 1;
10173let BaseOpcode = "L2_loadrb_io";
10174let CextOpcode = "L2_loadrb";
10175let isExtendable = 1;
10176let opExtendable = 3;
10177let isExtentSigned = 0;
10178let opExtentBits = 6;
10179let opExtentAlign = 0;
10180}
10181def L2_ploadrbf_pi : HInst<
10182(outs IntRegs:$Rd32, IntRegs:$Rx32),
10183(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10184"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)",
10185tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10186let Inst{13-11} = 0b101;
10187let Inst{31-21} = 0b10011011000;
10188let isPredicated = 1;
10189let isPredicatedFalse = 1;
10190let hasNewValue = 1;
10191let opNewValue = 0;
10192let addrMode = PostInc;
10193let accessSize = ByteAccess;
10194let mayLoad = 1;
10195let BaseOpcode = "L2_loadrb_pi";
10196let Constraints = "$Rx32 = $Rx32in";
10197}
10198def L2_ploadrbf_zomap : HInst<
10199(outs IntRegs:$Rd32),
10200(ins PredRegs:$Pt4, IntRegs:$Rs32),
10201"if (!$Pt4) $Rd32 = memb($Rs32)",
10202tc_fedb7e19, TypeMAPPING> {
10203let hasNewValue = 1;
10204let opNewValue = 0;
10205let isPseudo = 1;
10206let isCodeGenOnly = 1;
10207}
10208def L2_ploadrbfnew_io : HInst<
10209(outs IntRegs:$Rd32),
10210(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10211"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10212tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10213let Inst{13-13} = 0b0;
10214let Inst{31-21} = 0b01000111000;
10215let isPredicated = 1;
10216let isPredicatedFalse = 1;
10217let hasNewValue = 1;
10218let opNewValue = 0;
10219let addrMode = BaseImmOffset;
10220let accessSize = ByteAccess;
10221let isPredicatedNew = 1;
10222let mayLoad = 1;
10223let BaseOpcode = "L2_loadrb_io";
10224let CextOpcode = "L2_loadrb";
10225let isExtendable = 1;
10226let opExtendable = 3;
10227let isExtentSigned = 0;
10228let opExtentBits = 6;
10229let opExtentAlign = 0;
10230}
10231def L2_ploadrbfnew_pi : HInst<
10232(outs IntRegs:$Rd32, IntRegs:$Rx32),
10233(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10234"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10235tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10236let Inst{13-11} = 0b111;
10237let Inst{31-21} = 0b10011011000;
10238let isPredicated = 1;
10239let isPredicatedFalse = 1;
10240let hasNewValue = 1;
10241let opNewValue = 0;
10242let addrMode = PostInc;
10243let accessSize = ByteAccess;
10244let isPredicatedNew = 1;
10245let mayLoad = 1;
10246let BaseOpcode = "L2_loadrb_pi";
10247let Constraints = "$Rx32 = $Rx32in";
10248}
10249def L2_ploadrbfnew_zomap : HInst<
10250(outs IntRegs:$Rd32),
10251(ins PredRegs:$Pt4, IntRegs:$Rs32),
10252"if (!$Pt4.new) $Rd32 = memb($Rs32)",
10253tc_075c8dd8, TypeMAPPING> {
10254let hasNewValue = 1;
10255let opNewValue = 0;
10256let isPseudo = 1;
10257let isCodeGenOnly = 1;
10258}
10259def L2_ploadrbt_io : HInst<
10260(outs IntRegs:$Rd32),
10261(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10262"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)",
10263tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10264let Inst{13-13} = 0b0;
10265let Inst{31-21} = 0b01000001000;
10266let isPredicated = 1;
10267let hasNewValue = 1;
10268let opNewValue = 0;
10269let addrMode = BaseImmOffset;
10270let accessSize = ByteAccess;
10271let mayLoad = 1;
10272let BaseOpcode = "L2_loadrb_io";
10273let CextOpcode = "L2_loadrb";
10274let isExtendable = 1;
10275let opExtendable = 3;
10276let isExtentSigned = 0;
10277let opExtentBits = 6;
10278let opExtentAlign = 0;
10279}
10280def L2_ploadrbt_pi : HInst<
10281(outs IntRegs:$Rd32, IntRegs:$Rx32),
10282(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10283"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)",
10284tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10285let Inst{13-11} = 0b100;
10286let Inst{31-21} = 0b10011011000;
10287let isPredicated = 1;
10288let hasNewValue = 1;
10289let opNewValue = 0;
10290let addrMode = PostInc;
10291let accessSize = ByteAccess;
10292let mayLoad = 1;
10293let BaseOpcode = "L2_loadrb_pi";
10294let Constraints = "$Rx32 = $Rx32in";
10295}
10296def L2_ploadrbt_zomap : HInst<
10297(outs IntRegs:$Rd32),
10298(ins PredRegs:$Pt4, IntRegs:$Rs32),
10299"if ($Pt4) $Rd32 = memb($Rs32)",
10300tc_fedb7e19, TypeMAPPING> {
10301let hasNewValue = 1;
10302let opNewValue = 0;
10303let isPseudo = 1;
10304let isCodeGenOnly = 1;
10305}
10306def L2_ploadrbtnew_io : HInst<
10307(outs IntRegs:$Rd32),
10308(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10309"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)",
10310tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10311let Inst{13-13} = 0b0;
10312let Inst{31-21} = 0b01000011000;
10313let isPredicated = 1;
10314let hasNewValue = 1;
10315let opNewValue = 0;
10316let addrMode = BaseImmOffset;
10317let accessSize = ByteAccess;
10318let isPredicatedNew = 1;
10319let mayLoad = 1;
10320let BaseOpcode = "L2_loadrb_io";
10321let CextOpcode = "L2_loadrb";
10322let isExtendable = 1;
10323let opExtendable = 3;
10324let isExtentSigned = 0;
10325let opExtentBits = 6;
10326let opExtentAlign = 0;
10327}
10328def L2_ploadrbtnew_pi : HInst<
10329(outs IntRegs:$Rd32, IntRegs:$Rx32),
10330(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10331"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)",
10332tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10333let Inst{13-11} = 0b110;
10334let Inst{31-21} = 0b10011011000;
10335let isPredicated = 1;
10336let hasNewValue = 1;
10337let opNewValue = 0;
10338let addrMode = PostInc;
10339let accessSize = ByteAccess;
10340let isPredicatedNew = 1;
10341let mayLoad = 1;
10342let BaseOpcode = "L2_loadrb_pi";
10343let Constraints = "$Rx32 = $Rx32in";
10344}
10345def L2_ploadrbtnew_zomap : HInst<
10346(outs IntRegs:$Rd32),
10347(ins PredRegs:$Pt4, IntRegs:$Rs32),
10348"if ($Pt4.new) $Rd32 = memb($Rs32)",
10349tc_075c8dd8, TypeMAPPING> {
10350let hasNewValue = 1;
10351let opNewValue = 0;
10352let isPseudo = 1;
10353let isCodeGenOnly = 1;
10354}
10355def L2_ploadrdf_io : HInst<
10356(outs DoubleRegs:$Rdd32),
10357(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10358"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10359tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10360let Inst{13-13} = 0b0;
10361let Inst{31-21} = 0b01000101110;
10362let isPredicated = 1;
10363let isPredicatedFalse = 1;
10364let addrMode = BaseImmOffset;
10365let accessSize = DoubleWordAccess;
10366let mayLoad = 1;
10367let BaseOpcode = "L2_loadrd_io";
10368let CextOpcode = "L2_loadrd";
10369let isExtendable = 1;
10370let opExtendable = 3;
10371let isExtentSigned = 0;
10372let opExtentBits = 9;
10373let opExtentAlign = 3;
10374}
10375def L2_ploadrdf_pi : HInst<
10376(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10377(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10378"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10379tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10380let Inst{13-11} = 0b101;
10381let Inst{31-21} = 0b10011011110;
10382let isPredicated = 1;
10383let isPredicatedFalse = 1;
10384let addrMode = PostInc;
10385let accessSize = DoubleWordAccess;
10386let mayLoad = 1;
10387let BaseOpcode = "L2_loadrd_pi";
10388let Constraints = "$Rx32 = $Rx32in";
10389}
10390def L2_ploadrdf_zomap : HInst<
10391(outs DoubleRegs:$Rdd32),
10392(ins PredRegs:$Pt4, IntRegs:$Rs32),
10393"if (!$Pt4) $Rdd32 = memd($Rs32)",
10394tc_fedb7e19, TypeMAPPING> {
10395let isPseudo = 1;
10396let isCodeGenOnly = 1;
10397}
10398def L2_ploadrdfnew_io : HInst<
10399(outs DoubleRegs:$Rdd32),
10400(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10401"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10402tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10403let Inst{13-13} = 0b0;
10404let Inst{31-21} = 0b01000111110;
10405let isPredicated = 1;
10406let isPredicatedFalse = 1;
10407let addrMode = BaseImmOffset;
10408let accessSize = DoubleWordAccess;
10409let isPredicatedNew = 1;
10410let mayLoad = 1;
10411let BaseOpcode = "L2_loadrd_io";
10412let CextOpcode = "L2_loadrd";
10413let isExtendable = 1;
10414let opExtendable = 3;
10415let isExtentSigned = 0;
10416let opExtentBits = 9;
10417let opExtentAlign = 3;
10418}
10419def L2_ploadrdfnew_pi : HInst<
10420(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10421(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10422"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10423tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10424let Inst{13-11} = 0b111;
10425let Inst{31-21} = 0b10011011110;
10426let isPredicated = 1;
10427let isPredicatedFalse = 1;
10428let addrMode = PostInc;
10429let accessSize = DoubleWordAccess;
10430let isPredicatedNew = 1;
10431let mayLoad = 1;
10432let BaseOpcode = "L2_loadrd_pi";
10433let Constraints = "$Rx32 = $Rx32in";
10434}
10435def L2_ploadrdfnew_zomap : HInst<
10436(outs DoubleRegs:$Rdd32),
10437(ins PredRegs:$Pt4, IntRegs:$Rs32),
10438"if (!$Pt4.new) $Rdd32 = memd($Rs32)",
10439tc_075c8dd8, TypeMAPPING> {
10440let isPseudo = 1;
10441let isCodeGenOnly = 1;
10442}
10443def L2_ploadrdt_io : HInst<
10444(outs DoubleRegs:$Rdd32),
10445(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10446"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)",
10447tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10448let Inst{13-13} = 0b0;
10449let Inst{31-21} = 0b01000001110;
10450let isPredicated = 1;
10451let addrMode = BaseImmOffset;
10452let accessSize = DoubleWordAccess;
10453let mayLoad = 1;
10454let BaseOpcode = "L2_loadrd_io";
10455let CextOpcode = "L2_loadrd";
10456let isExtendable = 1;
10457let opExtendable = 3;
10458let isExtentSigned = 0;
10459let opExtentBits = 9;
10460let opExtentAlign = 3;
10461}
10462def L2_ploadrdt_pi : HInst<
10463(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10464(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10465"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)",
10466tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel {
10467let Inst{13-11} = 0b100;
10468let Inst{31-21} = 0b10011011110;
10469let isPredicated = 1;
10470let addrMode = PostInc;
10471let accessSize = DoubleWordAccess;
10472let mayLoad = 1;
10473let BaseOpcode = "L2_loadrd_pi";
10474let Constraints = "$Rx32 = $Rx32in";
10475}
10476def L2_ploadrdt_zomap : HInst<
10477(outs DoubleRegs:$Rdd32),
10478(ins PredRegs:$Pt4, IntRegs:$Rs32),
10479"if ($Pt4) $Rdd32 = memd($Rs32)",
10480tc_fedb7e19, TypeMAPPING> {
10481let isPseudo = 1;
10482let isCodeGenOnly = 1;
10483}
10484def L2_ploadrdtnew_io : HInst<
10485(outs DoubleRegs:$Rdd32),
10486(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii),
10487"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)",
10488tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel {
10489let Inst{13-13} = 0b0;
10490let Inst{31-21} = 0b01000011110;
10491let isPredicated = 1;
10492let addrMode = BaseImmOffset;
10493let accessSize = DoubleWordAccess;
10494let isPredicatedNew = 1;
10495let mayLoad = 1;
10496let BaseOpcode = "L2_loadrd_io";
10497let CextOpcode = "L2_loadrd";
10498let isExtendable = 1;
10499let opExtendable = 3;
10500let isExtentSigned = 0;
10501let opExtentBits = 9;
10502let opExtentAlign = 3;
10503}
10504def L2_ploadrdtnew_pi : HInst<
10505(outs DoubleRegs:$Rdd32, IntRegs:$Rx32),
10506(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii),
10507"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)",
10508tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel {
10509let Inst{13-11} = 0b110;
10510let Inst{31-21} = 0b10011011110;
10511let isPredicated = 1;
10512let addrMode = PostInc;
10513let accessSize = DoubleWordAccess;
10514let isPredicatedNew = 1;
10515let mayLoad = 1;
10516let BaseOpcode = "L2_loadrd_pi";
10517let Constraints = "$Rx32 = $Rx32in";
10518}
10519def L2_ploadrdtnew_zomap : HInst<
10520(outs DoubleRegs:$Rdd32),
10521(ins PredRegs:$Pt4, IntRegs:$Rs32),
10522"if ($Pt4.new) $Rdd32 = memd($Rs32)",
10523tc_075c8dd8, TypeMAPPING> {
10524let isPseudo = 1;
10525let isCodeGenOnly = 1;
10526}
10527def L2_ploadrhf_io : HInst<
10528(outs IntRegs:$Rd32),
10529(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10530"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)",
10531tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10532let Inst{13-13} = 0b0;
10533let Inst{31-21} = 0b01000101010;
10534let isPredicated = 1;
10535let isPredicatedFalse = 1;
10536let hasNewValue = 1;
10537let opNewValue = 0;
10538let addrMode = BaseImmOffset;
10539let accessSize = HalfWordAccess;
10540let mayLoad = 1;
10541let BaseOpcode = "L2_loadrh_io";
10542let CextOpcode = "L2_loadrh";
10543let isExtendable = 1;
10544let opExtendable = 3;
10545let isExtentSigned = 0;
10546let opExtentBits = 7;
10547let opExtentAlign = 1;
10548}
10549def L2_ploadrhf_pi : HInst<
10550(outs IntRegs:$Rd32, IntRegs:$Rx32),
10551(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10552"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)",
10553tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10554let Inst{13-11} = 0b101;
10555let Inst{31-21} = 0b10011011010;
10556let isPredicated = 1;
10557let isPredicatedFalse = 1;
10558let hasNewValue = 1;
10559let opNewValue = 0;
10560let addrMode = PostInc;
10561let accessSize = HalfWordAccess;
10562let mayLoad = 1;
10563let BaseOpcode = "L2_loadrh_pi";
10564let Constraints = "$Rx32 = $Rx32in";
10565}
10566def L2_ploadrhf_zomap : HInst<
10567(outs IntRegs:$Rd32),
10568(ins PredRegs:$Pt4, IntRegs:$Rs32),
10569"if (!$Pt4) $Rd32 = memh($Rs32)",
10570tc_fedb7e19, TypeMAPPING> {
10571let hasNewValue = 1;
10572let opNewValue = 0;
10573let isPseudo = 1;
10574let isCodeGenOnly = 1;
10575}
10576def L2_ploadrhfnew_io : HInst<
10577(outs IntRegs:$Rd32),
10578(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10579"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10580tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10581let Inst{13-13} = 0b0;
10582let Inst{31-21} = 0b01000111010;
10583let isPredicated = 1;
10584let isPredicatedFalse = 1;
10585let hasNewValue = 1;
10586let opNewValue = 0;
10587let addrMode = BaseImmOffset;
10588let accessSize = HalfWordAccess;
10589let isPredicatedNew = 1;
10590let mayLoad = 1;
10591let BaseOpcode = "L2_loadrh_io";
10592let CextOpcode = "L2_loadrh";
10593let isExtendable = 1;
10594let opExtendable = 3;
10595let isExtentSigned = 0;
10596let opExtentBits = 7;
10597let opExtentAlign = 1;
10598}
10599def L2_ploadrhfnew_pi : HInst<
10600(outs IntRegs:$Rd32, IntRegs:$Rx32),
10601(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10602"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10603tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10604let Inst{13-11} = 0b111;
10605let Inst{31-21} = 0b10011011010;
10606let isPredicated = 1;
10607let isPredicatedFalse = 1;
10608let hasNewValue = 1;
10609let opNewValue = 0;
10610let addrMode = PostInc;
10611let accessSize = HalfWordAccess;
10612let isPredicatedNew = 1;
10613let mayLoad = 1;
10614let BaseOpcode = "L2_loadrh_pi";
10615let Constraints = "$Rx32 = $Rx32in";
10616}
10617def L2_ploadrhfnew_zomap : HInst<
10618(outs IntRegs:$Rd32),
10619(ins PredRegs:$Pt4, IntRegs:$Rs32),
10620"if (!$Pt4.new) $Rd32 = memh($Rs32)",
10621tc_075c8dd8, TypeMAPPING> {
10622let hasNewValue = 1;
10623let opNewValue = 0;
10624let isPseudo = 1;
10625let isCodeGenOnly = 1;
10626}
10627def L2_ploadrht_io : HInst<
10628(outs IntRegs:$Rd32),
10629(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10630"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)",
10631tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10632let Inst{13-13} = 0b0;
10633let Inst{31-21} = 0b01000001010;
10634let isPredicated = 1;
10635let hasNewValue = 1;
10636let opNewValue = 0;
10637let addrMode = BaseImmOffset;
10638let accessSize = HalfWordAccess;
10639let mayLoad = 1;
10640let BaseOpcode = "L2_loadrh_io";
10641let CextOpcode = "L2_loadrh";
10642let isExtendable = 1;
10643let opExtendable = 3;
10644let isExtentSigned = 0;
10645let opExtentBits = 7;
10646let opExtentAlign = 1;
10647}
10648def L2_ploadrht_pi : HInst<
10649(outs IntRegs:$Rd32, IntRegs:$Rx32),
10650(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10651"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)",
10652tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
10653let Inst{13-11} = 0b100;
10654let Inst{31-21} = 0b10011011010;
10655let isPredicated = 1;
10656let hasNewValue = 1;
10657let opNewValue = 0;
10658let addrMode = PostInc;
10659let accessSize = HalfWordAccess;
10660let mayLoad = 1;
10661let BaseOpcode = "L2_loadrh_pi";
10662let Constraints = "$Rx32 = $Rx32in";
10663}
10664def L2_ploadrht_zomap : HInst<
10665(outs IntRegs:$Rd32),
10666(ins PredRegs:$Pt4, IntRegs:$Rs32),
10667"if ($Pt4) $Rd32 = memh($Rs32)",
10668tc_fedb7e19, TypeMAPPING> {
10669let hasNewValue = 1;
10670let opNewValue = 0;
10671let isPseudo = 1;
10672let isCodeGenOnly = 1;
10673}
10674def L2_ploadrhtnew_io : HInst<
10675(outs IntRegs:$Rd32),
10676(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
10677"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)",
10678tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
10679let Inst{13-13} = 0b0;
10680let Inst{31-21} = 0b01000011010;
10681let isPredicated = 1;
10682let hasNewValue = 1;
10683let opNewValue = 0;
10684let addrMode = BaseImmOffset;
10685let accessSize = HalfWordAccess;
10686let isPredicatedNew = 1;
10687let mayLoad = 1;
10688let BaseOpcode = "L2_loadrh_io";
10689let CextOpcode = "L2_loadrh";
10690let isExtendable = 1;
10691let opExtendable = 3;
10692let isExtentSigned = 0;
10693let opExtentBits = 7;
10694let opExtentAlign = 1;
10695}
10696def L2_ploadrhtnew_pi : HInst<
10697(outs IntRegs:$Rd32, IntRegs:$Rx32),
10698(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
10699"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)",
10700tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
10701let Inst{13-11} = 0b110;
10702let Inst{31-21} = 0b10011011010;
10703let isPredicated = 1;
10704let hasNewValue = 1;
10705let opNewValue = 0;
10706let addrMode = PostInc;
10707let accessSize = HalfWordAccess;
10708let isPredicatedNew = 1;
10709let mayLoad = 1;
10710let BaseOpcode = "L2_loadrh_pi";
10711let Constraints = "$Rx32 = $Rx32in";
10712}
10713def L2_ploadrhtnew_zomap : HInst<
10714(outs IntRegs:$Rd32),
10715(ins PredRegs:$Pt4, IntRegs:$Rs32),
10716"if ($Pt4.new) $Rd32 = memh($Rs32)",
10717tc_075c8dd8, TypeMAPPING> {
10718let hasNewValue = 1;
10719let opNewValue = 0;
10720let isPseudo = 1;
10721let isCodeGenOnly = 1;
10722}
10723def L2_ploadrif_io : HInst<
10724(outs IntRegs:$Rd32),
10725(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10726"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)",
10727tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10728let Inst{13-13} = 0b0;
10729let Inst{31-21} = 0b01000101100;
10730let isPredicated = 1;
10731let isPredicatedFalse = 1;
10732let hasNewValue = 1;
10733let opNewValue = 0;
10734let addrMode = BaseImmOffset;
10735let accessSize = WordAccess;
10736let mayLoad = 1;
10737let BaseOpcode = "L2_loadri_io";
10738let CextOpcode = "L2_loadri";
10739let isExtendable = 1;
10740let opExtendable = 3;
10741let isExtentSigned = 0;
10742let opExtentBits = 8;
10743let opExtentAlign = 2;
10744}
10745def L2_ploadrif_pi : HInst<
10746(outs IntRegs:$Rd32, IntRegs:$Rx32),
10747(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10748"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)",
10749tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10750let Inst{13-11} = 0b101;
10751let Inst{31-21} = 0b10011011100;
10752let isPredicated = 1;
10753let isPredicatedFalse = 1;
10754let hasNewValue = 1;
10755let opNewValue = 0;
10756let addrMode = PostInc;
10757let accessSize = WordAccess;
10758let mayLoad = 1;
10759let BaseOpcode = "L2_loadri_pi";
10760let Constraints = "$Rx32 = $Rx32in";
10761}
10762def L2_ploadrif_zomap : HInst<
10763(outs IntRegs:$Rd32),
10764(ins PredRegs:$Pt4, IntRegs:$Rs32),
10765"if (!$Pt4) $Rd32 = memw($Rs32)",
10766tc_fedb7e19, TypeMAPPING> {
10767let hasNewValue = 1;
10768let opNewValue = 0;
10769let isPseudo = 1;
10770let isCodeGenOnly = 1;
10771}
10772def L2_ploadrifnew_io : HInst<
10773(outs IntRegs:$Rd32),
10774(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10775"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10776tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10777let Inst{13-13} = 0b0;
10778let Inst{31-21} = 0b01000111100;
10779let isPredicated = 1;
10780let isPredicatedFalse = 1;
10781let hasNewValue = 1;
10782let opNewValue = 0;
10783let addrMode = BaseImmOffset;
10784let accessSize = WordAccess;
10785let isPredicatedNew = 1;
10786let mayLoad = 1;
10787let BaseOpcode = "L2_loadri_io";
10788let CextOpcode = "L2_loadri";
10789let isExtendable = 1;
10790let opExtendable = 3;
10791let isExtentSigned = 0;
10792let opExtentBits = 8;
10793let opExtentAlign = 2;
10794}
10795def L2_ploadrifnew_pi : HInst<
10796(outs IntRegs:$Rd32, IntRegs:$Rx32),
10797(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10798"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10799tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10800let Inst{13-11} = 0b111;
10801let Inst{31-21} = 0b10011011100;
10802let isPredicated = 1;
10803let isPredicatedFalse = 1;
10804let hasNewValue = 1;
10805let opNewValue = 0;
10806let addrMode = PostInc;
10807let accessSize = WordAccess;
10808let isPredicatedNew = 1;
10809let mayLoad = 1;
10810let BaseOpcode = "L2_loadri_pi";
10811let Constraints = "$Rx32 = $Rx32in";
10812}
10813def L2_ploadrifnew_zomap : HInst<
10814(outs IntRegs:$Rd32),
10815(ins PredRegs:$Pt4, IntRegs:$Rs32),
10816"if (!$Pt4.new) $Rd32 = memw($Rs32)",
10817tc_075c8dd8, TypeMAPPING> {
10818let hasNewValue = 1;
10819let opNewValue = 0;
10820let isPseudo = 1;
10821let isCodeGenOnly = 1;
10822}
10823def L2_ploadrit_io : HInst<
10824(outs IntRegs:$Rd32),
10825(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10826"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)",
10827tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10828let Inst{13-13} = 0b0;
10829let Inst{31-21} = 0b01000001100;
10830let isPredicated = 1;
10831let hasNewValue = 1;
10832let opNewValue = 0;
10833let addrMode = BaseImmOffset;
10834let accessSize = WordAccess;
10835let mayLoad = 1;
10836let BaseOpcode = "L2_loadri_io";
10837let CextOpcode = "L2_loadri";
10838let isExtendable = 1;
10839let opExtendable = 3;
10840let isExtentSigned = 0;
10841let opExtentBits = 8;
10842let opExtentAlign = 2;
10843}
10844def L2_ploadrit_pi : HInst<
10845(outs IntRegs:$Rd32, IntRegs:$Rx32),
10846(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10847"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)",
10848tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel {
10849let Inst{13-11} = 0b100;
10850let Inst{31-21} = 0b10011011100;
10851let isPredicated = 1;
10852let hasNewValue = 1;
10853let opNewValue = 0;
10854let addrMode = PostInc;
10855let accessSize = WordAccess;
10856let mayLoad = 1;
10857let BaseOpcode = "L2_loadri_pi";
10858let Constraints = "$Rx32 = $Rx32in";
10859}
10860def L2_ploadrit_zomap : HInst<
10861(outs IntRegs:$Rd32),
10862(ins PredRegs:$Pt4, IntRegs:$Rs32),
10863"if ($Pt4) $Rd32 = memw($Rs32)",
10864tc_fedb7e19, TypeMAPPING> {
10865let hasNewValue = 1;
10866let opNewValue = 0;
10867let isPseudo = 1;
10868let isCodeGenOnly = 1;
10869}
10870def L2_ploadritnew_io : HInst<
10871(outs IntRegs:$Rd32),
10872(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii),
10873"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)",
10874tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel {
10875let Inst{13-13} = 0b0;
10876let Inst{31-21} = 0b01000011100;
10877let isPredicated = 1;
10878let hasNewValue = 1;
10879let opNewValue = 0;
10880let addrMode = BaseImmOffset;
10881let accessSize = WordAccess;
10882let isPredicatedNew = 1;
10883let mayLoad = 1;
10884let BaseOpcode = "L2_loadri_io";
10885let CextOpcode = "L2_loadri";
10886let isExtendable = 1;
10887let opExtendable = 3;
10888let isExtentSigned = 0;
10889let opExtentBits = 8;
10890let opExtentAlign = 2;
10891}
10892def L2_ploadritnew_pi : HInst<
10893(outs IntRegs:$Rd32, IntRegs:$Rx32),
10894(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii),
10895"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)",
10896tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel {
10897let Inst{13-11} = 0b110;
10898let Inst{31-21} = 0b10011011100;
10899let isPredicated = 1;
10900let hasNewValue = 1;
10901let opNewValue = 0;
10902let addrMode = PostInc;
10903let accessSize = WordAccess;
10904let isPredicatedNew = 1;
10905let mayLoad = 1;
10906let BaseOpcode = "L2_loadri_pi";
10907let Constraints = "$Rx32 = $Rx32in";
10908}
10909def L2_ploadritnew_zomap : HInst<
10910(outs IntRegs:$Rd32),
10911(ins PredRegs:$Pt4, IntRegs:$Rs32),
10912"if ($Pt4.new) $Rd32 = memw($Rs32)",
10913tc_075c8dd8, TypeMAPPING> {
10914let hasNewValue = 1;
10915let opNewValue = 0;
10916let isPseudo = 1;
10917let isCodeGenOnly = 1;
10918}
10919def L2_ploadrubf_io : HInst<
10920(outs IntRegs:$Rd32),
10921(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10922"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)",
10923tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10924let Inst{13-13} = 0b0;
10925let Inst{31-21} = 0b01000101001;
10926let isPredicated = 1;
10927let isPredicatedFalse = 1;
10928let hasNewValue = 1;
10929let opNewValue = 0;
10930let addrMode = BaseImmOffset;
10931let accessSize = ByteAccess;
10932let mayLoad = 1;
10933let BaseOpcode = "L2_loadrub_io";
10934let CextOpcode = "L2_loadrub";
10935let isExtendable = 1;
10936let opExtendable = 3;
10937let isExtentSigned = 0;
10938let opExtentBits = 6;
10939let opExtentAlign = 0;
10940}
10941def L2_ploadrubf_pi : HInst<
10942(outs IntRegs:$Rd32, IntRegs:$Rx32),
10943(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10944"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)",
10945tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
10946let Inst{13-11} = 0b101;
10947let Inst{31-21} = 0b10011011001;
10948let isPredicated = 1;
10949let isPredicatedFalse = 1;
10950let hasNewValue = 1;
10951let opNewValue = 0;
10952let addrMode = PostInc;
10953let accessSize = ByteAccess;
10954let mayLoad = 1;
10955let BaseOpcode = "L2_loadrub_pi";
10956let Constraints = "$Rx32 = $Rx32in";
10957}
10958def L2_ploadrubf_zomap : HInst<
10959(outs IntRegs:$Rd32),
10960(ins PredRegs:$Pt4, IntRegs:$Rs32),
10961"if (!$Pt4) $Rd32 = memub($Rs32)",
10962tc_fedb7e19, TypeMAPPING> {
10963let hasNewValue = 1;
10964let opNewValue = 0;
10965let isPseudo = 1;
10966let isCodeGenOnly = 1;
10967}
10968def L2_ploadrubfnew_io : HInst<
10969(outs IntRegs:$Rd32),
10970(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
10971"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
10972tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
10973let Inst{13-13} = 0b0;
10974let Inst{31-21} = 0b01000111001;
10975let isPredicated = 1;
10976let isPredicatedFalse = 1;
10977let hasNewValue = 1;
10978let opNewValue = 0;
10979let addrMode = BaseImmOffset;
10980let accessSize = ByteAccess;
10981let isPredicatedNew = 1;
10982let mayLoad = 1;
10983let BaseOpcode = "L2_loadrub_io";
10984let CextOpcode = "L2_loadrub";
10985let isExtendable = 1;
10986let opExtendable = 3;
10987let isExtentSigned = 0;
10988let opExtentBits = 6;
10989let opExtentAlign = 0;
10990}
10991def L2_ploadrubfnew_pi : HInst<
10992(outs IntRegs:$Rd32, IntRegs:$Rx32),
10993(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
10994"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
10995tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
10996let Inst{13-11} = 0b111;
10997let Inst{31-21} = 0b10011011001;
10998let isPredicated = 1;
10999let isPredicatedFalse = 1;
11000let hasNewValue = 1;
11001let opNewValue = 0;
11002let addrMode = PostInc;
11003let accessSize = ByteAccess;
11004let isPredicatedNew = 1;
11005let mayLoad = 1;
11006let BaseOpcode = "L2_loadrub_pi";
11007let Constraints = "$Rx32 = $Rx32in";
11008}
11009def L2_ploadrubfnew_zomap : HInst<
11010(outs IntRegs:$Rd32),
11011(ins PredRegs:$Pt4, IntRegs:$Rs32),
11012"if (!$Pt4.new) $Rd32 = memub($Rs32)",
11013tc_075c8dd8, TypeMAPPING> {
11014let hasNewValue = 1;
11015let opNewValue = 0;
11016let isPseudo = 1;
11017let isCodeGenOnly = 1;
11018}
11019def L2_ploadrubt_io : HInst<
11020(outs IntRegs:$Rd32),
11021(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11022"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)",
11023tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11024let Inst{13-13} = 0b0;
11025let Inst{31-21} = 0b01000001001;
11026let isPredicated = 1;
11027let hasNewValue = 1;
11028let opNewValue = 0;
11029let addrMode = BaseImmOffset;
11030let accessSize = ByteAccess;
11031let mayLoad = 1;
11032let BaseOpcode = "L2_loadrub_io";
11033let CextOpcode = "L2_loadrub";
11034let isExtendable = 1;
11035let opExtendable = 3;
11036let isExtentSigned = 0;
11037let opExtentBits = 6;
11038let opExtentAlign = 0;
11039}
11040def L2_ploadrubt_pi : HInst<
11041(outs IntRegs:$Rd32, IntRegs:$Rx32),
11042(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11043"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)",
11044tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel {
11045let Inst{13-11} = 0b100;
11046let Inst{31-21} = 0b10011011001;
11047let isPredicated = 1;
11048let hasNewValue = 1;
11049let opNewValue = 0;
11050let addrMode = PostInc;
11051let accessSize = ByteAccess;
11052let mayLoad = 1;
11053let BaseOpcode = "L2_loadrub_pi";
11054let Constraints = "$Rx32 = $Rx32in";
11055}
11056def L2_ploadrubt_zomap : HInst<
11057(outs IntRegs:$Rd32),
11058(ins PredRegs:$Pt4, IntRegs:$Rs32),
11059"if ($Pt4) $Rd32 = memub($Rs32)",
11060tc_fedb7e19, TypeMAPPING> {
11061let hasNewValue = 1;
11062let opNewValue = 0;
11063let isPseudo = 1;
11064let isCodeGenOnly = 1;
11065}
11066def L2_ploadrubtnew_io : HInst<
11067(outs IntRegs:$Rd32),
11068(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii),
11069"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)",
11070tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel {
11071let Inst{13-13} = 0b0;
11072let Inst{31-21} = 0b01000011001;
11073let isPredicated = 1;
11074let hasNewValue = 1;
11075let opNewValue = 0;
11076let addrMode = BaseImmOffset;
11077let accessSize = ByteAccess;
11078let isPredicatedNew = 1;
11079let mayLoad = 1;
11080let BaseOpcode = "L2_loadrub_io";
11081let CextOpcode = "L2_loadrub";
11082let isExtendable = 1;
11083let opExtendable = 3;
11084let isExtentSigned = 0;
11085let opExtentBits = 6;
11086let opExtentAlign = 0;
11087}
11088def L2_ploadrubtnew_pi : HInst<
11089(outs IntRegs:$Rd32, IntRegs:$Rx32),
11090(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii),
11091"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)",
11092tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel {
11093let Inst{13-11} = 0b110;
11094let Inst{31-21} = 0b10011011001;
11095let isPredicated = 1;
11096let hasNewValue = 1;
11097let opNewValue = 0;
11098let addrMode = PostInc;
11099let accessSize = ByteAccess;
11100let isPredicatedNew = 1;
11101let mayLoad = 1;
11102let BaseOpcode = "L2_loadrub_pi";
11103let Constraints = "$Rx32 = $Rx32in";
11104}
11105def L2_ploadrubtnew_zomap : HInst<
11106(outs IntRegs:$Rd32),
11107(ins PredRegs:$Pt4, IntRegs:$Rs32),
11108"if ($Pt4.new) $Rd32 = memub($Rs32)",
11109tc_075c8dd8, TypeMAPPING> {
11110let hasNewValue = 1;
11111let opNewValue = 0;
11112let isPseudo = 1;
11113let isCodeGenOnly = 1;
11114}
11115def L2_ploadruhf_io : HInst<
11116(outs IntRegs:$Rd32),
11117(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11118"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11119tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11120let Inst{13-13} = 0b0;
11121let Inst{31-21} = 0b01000101011;
11122let isPredicated = 1;
11123let isPredicatedFalse = 1;
11124let hasNewValue = 1;
11125let opNewValue = 0;
11126let addrMode = BaseImmOffset;
11127let accessSize = HalfWordAccess;
11128let mayLoad = 1;
11129let BaseOpcode = "L2_loadruh_io";
11130let CextOpcode = "L2_loadruh";
11131let isExtendable = 1;
11132let opExtendable = 3;
11133let isExtentSigned = 0;
11134let opExtentBits = 7;
11135let opExtentAlign = 1;
11136}
11137def L2_ploadruhf_pi : HInst<
11138(outs IntRegs:$Rd32, IntRegs:$Rx32),
11139(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11140"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11141tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11142let Inst{13-11} = 0b101;
11143let Inst{31-21} = 0b10011011011;
11144let isPredicated = 1;
11145let isPredicatedFalse = 1;
11146let hasNewValue = 1;
11147let opNewValue = 0;
11148let addrMode = PostInc;
11149let accessSize = HalfWordAccess;
11150let mayLoad = 1;
11151let BaseOpcode = "L2_loadruh_pi";
11152let Constraints = "$Rx32 = $Rx32in";
11153}
11154def L2_ploadruhf_zomap : HInst<
11155(outs IntRegs:$Rd32),
11156(ins PredRegs:$Pt4, IntRegs:$Rs32),
11157"if (!$Pt4) $Rd32 = memuh($Rs32)",
11158tc_fedb7e19, TypeMAPPING> {
11159let hasNewValue = 1;
11160let opNewValue = 0;
11161let isPseudo = 1;
11162let isCodeGenOnly = 1;
11163}
11164def L2_ploadruhfnew_io : HInst<
11165(outs IntRegs:$Rd32),
11166(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11167"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11168tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11169let Inst{13-13} = 0b0;
11170let Inst{31-21} = 0b01000111011;
11171let isPredicated = 1;
11172let isPredicatedFalse = 1;
11173let hasNewValue = 1;
11174let opNewValue = 0;
11175let addrMode = BaseImmOffset;
11176let accessSize = HalfWordAccess;
11177let isPredicatedNew = 1;
11178let mayLoad = 1;
11179let BaseOpcode = "L2_loadruh_io";
11180let CextOpcode = "L2_loadruh";
11181let isExtendable = 1;
11182let opExtendable = 3;
11183let isExtentSigned = 0;
11184let opExtentBits = 7;
11185let opExtentAlign = 1;
11186}
11187def L2_ploadruhfnew_pi : HInst<
11188(outs IntRegs:$Rd32, IntRegs:$Rx32),
11189(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11190"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11191tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11192let Inst{13-11} = 0b111;
11193let Inst{31-21} = 0b10011011011;
11194let isPredicated = 1;
11195let isPredicatedFalse = 1;
11196let hasNewValue = 1;
11197let opNewValue = 0;
11198let addrMode = PostInc;
11199let accessSize = HalfWordAccess;
11200let isPredicatedNew = 1;
11201let mayLoad = 1;
11202let BaseOpcode = "L2_loadruh_pi";
11203let Constraints = "$Rx32 = $Rx32in";
11204}
11205def L2_ploadruhfnew_zomap : HInst<
11206(outs IntRegs:$Rd32),
11207(ins PredRegs:$Pt4, IntRegs:$Rs32),
11208"if (!$Pt4.new) $Rd32 = memuh($Rs32)",
11209tc_075c8dd8, TypeMAPPING> {
11210let hasNewValue = 1;
11211let opNewValue = 0;
11212let isPseudo = 1;
11213let isCodeGenOnly = 1;
11214}
11215def L2_ploadruht_io : HInst<
11216(outs IntRegs:$Rd32),
11217(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11218"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)",
11219tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11220let Inst{13-13} = 0b0;
11221let Inst{31-21} = 0b01000001011;
11222let isPredicated = 1;
11223let hasNewValue = 1;
11224let opNewValue = 0;
11225let addrMode = BaseImmOffset;
11226let accessSize = HalfWordAccess;
11227let mayLoad = 1;
11228let BaseOpcode = "L2_loadruh_io";
11229let CextOpcode = "L2_loadruh";
11230let isExtendable = 1;
11231let opExtendable = 3;
11232let isExtentSigned = 0;
11233let opExtentBits = 7;
11234let opExtentAlign = 1;
11235}
11236def L2_ploadruht_pi : HInst<
11237(outs IntRegs:$Rd32, IntRegs:$Rx32),
11238(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11239"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)",
11240tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel {
11241let Inst{13-11} = 0b100;
11242let Inst{31-21} = 0b10011011011;
11243let isPredicated = 1;
11244let hasNewValue = 1;
11245let opNewValue = 0;
11246let addrMode = PostInc;
11247let accessSize = HalfWordAccess;
11248let mayLoad = 1;
11249let BaseOpcode = "L2_loadruh_pi";
11250let Constraints = "$Rx32 = $Rx32in";
11251}
11252def L2_ploadruht_zomap : HInst<
11253(outs IntRegs:$Rd32),
11254(ins PredRegs:$Pt4, IntRegs:$Rs32),
11255"if ($Pt4) $Rd32 = memuh($Rs32)",
11256tc_fedb7e19, TypeMAPPING> {
11257let hasNewValue = 1;
11258let opNewValue = 0;
11259let isPseudo = 1;
11260let isCodeGenOnly = 1;
11261}
11262def L2_ploadruhtnew_io : HInst<
11263(outs IntRegs:$Rd32),
11264(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii),
11265"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)",
11266tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel {
11267let Inst{13-13} = 0b0;
11268let Inst{31-21} = 0b01000011011;
11269let isPredicated = 1;
11270let hasNewValue = 1;
11271let opNewValue = 0;
11272let addrMode = BaseImmOffset;
11273let accessSize = HalfWordAccess;
11274let isPredicatedNew = 1;
11275let mayLoad = 1;
11276let BaseOpcode = "L2_loadruh_io";
11277let CextOpcode = "L2_loadruh";
11278let isExtendable = 1;
11279let opExtendable = 3;
11280let isExtentSigned = 0;
11281let opExtentBits = 7;
11282let opExtentAlign = 1;
11283}
11284def L2_ploadruhtnew_pi : HInst<
11285(outs IntRegs:$Rd32, IntRegs:$Rx32),
11286(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii),
11287"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)",
11288tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel {
11289let Inst{13-11} = 0b110;
11290let Inst{31-21} = 0b10011011011;
11291let isPredicated = 1;
11292let hasNewValue = 1;
11293let opNewValue = 0;
11294let addrMode = PostInc;
11295let accessSize = HalfWordAccess;
11296let isPredicatedNew = 1;
11297let mayLoad = 1;
11298let BaseOpcode = "L2_loadruh_pi";
11299let Constraints = "$Rx32 = $Rx32in";
11300}
11301def L2_ploadruhtnew_zomap : HInst<
11302(outs IntRegs:$Rd32),
11303(ins PredRegs:$Pt4, IntRegs:$Rs32),
11304"if ($Pt4.new) $Rd32 = memuh($Rs32)",
11305tc_075c8dd8, TypeMAPPING> {
11306let hasNewValue = 1;
11307let opNewValue = 0;
11308let isPseudo = 1;
11309let isCodeGenOnly = 1;
11310}
11311def L4_add_memopb_io : HInst<
11312(outs),
11313(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11314"memb($Rs32+#$Ii) += $Rt32",
11315tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11316let Inst{6-5} = 0b00;
11317let Inst{13-13} = 0b0;
11318let Inst{31-21} = 0b00111110000;
11319let addrMode = BaseImmOffset;
11320let accessSize = ByteAccess;
11321let mayLoad = 1;
11322let isRestrictNoSlot1Store = 1;
11323let mayStore = 1;
11324let isExtendable = 1;
11325let opExtendable = 1;
11326let isExtentSigned = 0;
11327let opExtentBits = 6;
11328let opExtentAlign = 0;
11329}
11330def L4_add_memopb_zomap : HInst<
11331(outs),
11332(ins IntRegs:$Rs32, IntRegs:$Rt32),
11333"memb($Rs32) += $Rt32",
11334tc_9bcfb2ee, TypeMAPPING> {
11335let isPseudo = 1;
11336let isCodeGenOnly = 1;
11337}
11338def L4_add_memoph_io : HInst<
11339(outs),
11340(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11341"memh($Rs32+#$Ii) += $Rt32",
11342tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11343let Inst{6-5} = 0b00;
11344let Inst{13-13} = 0b0;
11345let Inst{31-21} = 0b00111110001;
11346let addrMode = BaseImmOffset;
11347let accessSize = HalfWordAccess;
11348let mayLoad = 1;
11349let isRestrictNoSlot1Store = 1;
11350let mayStore = 1;
11351let isExtendable = 1;
11352let opExtendable = 1;
11353let isExtentSigned = 0;
11354let opExtentBits = 7;
11355let opExtentAlign = 1;
11356}
11357def L4_add_memoph_zomap : HInst<
11358(outs),
11359(ins IntRegs:$Rs32, IntRegs:$Rt32),
11360"memh($Rs32) += $Rt32",
11361tc_9bcfb2ee, TypeMAPPING> {
11362let isPseudo = 1;
11363let isCodeGenOnly = 1;
11364}
11365def L4_add_memopw_io : HInst<
11366(outs),
11367(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11368"memw($Rs32+#$Ii) += $Rt32",
11369tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11370let Inst{6-5} = 0b00;
11371let Inst{13-13} = 0b0;
11372let Inst{31-21} = 0b00111110010;
11373let addrMode = BaseImmOffset;
11374let accessSize = WordAccess;
11375let mayLoad = 1;
11376let isRestrictNoSlot1Store = 1;
11377let mayStore = 1;
11378let isExtendable = 1;
11379let opExtendable = 1;
11380let isExtentSigned = 0;
11381let opExtentBits = 8;
11382let opExtentAlign = 2;
11383}
11384def L4_add_memopw_zomap : HInst<
11385(outs),
11386(ins IntRegs:$Rs32, IntRegs:$Rt32),
11387"memw($Rs32) += $Rt32",
11388tc_9bcfb2ee, TypeMAPPING> {
11389let isPseudo = 1;
11390let isCodeGenOnly = 1;
11391}
11392def L4_and_memopb_io : HInst<
11393(outs),
11394(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
11395"memb($Rs32+#$Ii) &= $Rt32",
11396tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
11397let Inst{6-5} = 0b10;
11398let Inst{13-13} = 0b0;
11399let Inst{31-21} = 0b00111110000;
11400let addrMode = BaseImmOffset;
11401let accessSize = ByteAccess;
11402let mayLoad = 1;
11403let isRestrictNoSlot1Store = 1;
11404let mayStore = 1;
11405let isExtendable = 1;
11406let opExtendable = 1;
11407let isExtentSigned = 0;
11408let opExtentBits = 6;
11409let opExtentAlign = 0;
11410}
11411def L4_and_memopb_zomap : HInst<
11412(outs),
11413(ins IntRegs:$Rs32, IntRegs:$Rt32),
11414"memb($Rs32) &= $Rt32",
11415tc_9bcfb2ee, TypeMAPPING> {
11416let isPseudo = 1;
11417let isCodeGenOnly = 1;
11418}
11419def L4_and_memoph_io : HInst<
11420(outs),
11421(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
11422"memh($Rs32+#$Ii) &= $Rt32",
11423tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
11424let Inst{6-5} = 0b10;
11425let Inst{13-13} = 0b0;
11426let Inst{31-21} = 0b00111110001;
11427let addrMode = BaseImmOffset;
11428let accessSize = HalfWordAccess;
11429let mayLoad = 1;
11430let isRestrictNoSlot1Store = 1;
11431let mayStore = 1;
11432let isExtendable = 1;
11433let opExtendable = 1;
11434let isExtentSigned = 0;
11435let opExtentBits = 7;
11436let opExtentAlign = 1;
11437}
11438def L4_and_memoph_zomap : HInst<
11439(outs),
11440(ins IntRegs:$Rs32, IntRegs:$Rt32),
11441"memh($Rs32) &= $Rt32",
11442tc_9bcfb2ee, TypeMAPPING> {
11443let isPseudo = 1;
11444let isCodeGenOnly = 1;
11445}
11446def L4_and_memopw_io : HInst<
11447(outs),
11448(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
11449"memw($Rs32+#$Ii) &= $Rt32",
11450tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
11451let Inst{6-5} = 0b10;
11452let Inst{13-13} = 0b0;
11453let Inst{31-21} = 0b00111110010;
11454let addrMode = BaseImmOffset;
11455let accessSize = WordAccess;
11456let mayLoad = 1;
11457let isRestrictNoSlot1Store = 1;
11458let mayStore = 1;
11459let isExtendable = 1;
11460let opExtendable = 1;
11461let isExtentSigned = 0;
11462let opExtentBits = 8;
11463let opExtentAlign = 2;
11464}
11465def L4_and_memopw_zomap : HInst<
11466(outs),
11467(ins IntRegs:$Rs32, IntRegs:$Rt32),
11468"memw($Rs32) &= $Rt32",
11469tc_9bcfb2ee, TypeMAPPING> {
11470let isPseudo = 1;
11471let isCodeGenOnly = 1;
11472}
11473def L4_iadd_memopb_io : HInst<
11474(outs),
11475(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11476"memb($Rs32+#$Ii) += #$II",
11477tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11478let Inst{6-5} = 0b00;
11479let Inst{13-13} = 0b0;
11480let Inst{31-21} = 0b00111111000;
11481let addrMode = BaseImmOffset;
11482let accessSize = ByteAccess;
11483let mayLoad = 1;
11484let isRestrictNoSlot1Store = 1;
11485let mayStore = 1;
11486let isExtendable = 1;
11487let opExtendable = 1;
11488let isExtentSigned = 0;
11489let opExtentBits = 6;
11490let opExtentAlign = 0;
11491}
11492def L4_iadd_memopb_zomap : HInst<
11493(outs),
11494(ins IntRegs:$Rs32, u5_0Imm:$II),
11495"memb($Rs32) += #$II",
11496tc_158aa3f7, TypeMAPPING> {
11497let isPseudo = 1;
11498let isCodeGenOnly = 1;
11499}
11500def L4_iadd_memoph_io : HInst<
11501(outs),
11502(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11503"memh($Rs32+#$Ii) += #$II",
11504tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11505let Inst{6-5} = 0b00;
11506let Inst{13-13} = 0b0;
11507let Inst{31-21} = 0b00111111001;
11508let addrMode = BaseImmOffset;
11509let accessSize = HalfWordAccess;
11510let mayLoad = 1;
11511let isRestrictNoSlot1Store = 1;
11512let mayStore = 1;
11513let isExtendable = 1;
11514let opExtendable = 1;
11515let isExtentSigned = 0;
11516let opExtentBits = 7;
11517let opExtentAlign = 1;
11518}
11519def L4_iadd_memoph_zomap : HInst<
11520(outs),
11521(ins IntRegs:$Rs32, u5_0Imm:$II),
11522"memh($Rs32) += #$II",
11523tc_158aa3f7, TypeMAPPING> {
11524let isPseudo = 1;
11525let isCodeGenOnly = 1;
11526}
11527def L4_iadd_memopw_io : HInst<
11528(outs),
11529(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11530"memw($Rs32+#$Ii) += #$II",
11531tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11532let Inst{6-5} = 0b00;
11533let Inst{13-13} = 0b0;
11534let Inst{31-21} = 0b00111111010;
11535let addrMode = BaseImmOffset;
11536let accessSize = WordAccess;
11537let mayLoad = 1;
11538let isRestrictNoSlot1Store = 1;
11539let mayStore = 1;
11540let isExtendable = 1;
11541let opExtendable = 1;
11542let isExtentSigned = 0;
11543let opExtentBits = 8;
11544let opExtentAlign = 2;
11545}
11546def L4_iadd_memopw_zomap : HInst<
11547(outs),
11548(ins IntRegs:$Rs32, u5_0Imm:$II),
11549"memw($Rs32) += #$II",
11550tc_158aa3f7, TypeMAPPING> {
11551let isPseudo = 1;
11552let isCodeGenOnly = 1;
11553}
11554def L4_iand_memopb_io : HInst<
11555(outs),
11556(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11557"memb($Rs32+#$Ii) = clrbit(#$II)",
11558tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11559let Inst{6-5} = 0b10;
11560let Inst{13-13} = 0b0;
11561let Inst{31-21} = 0b00111111000;
11562let addrMode = BaseImmOffset;
11563let accessSize = ByteAccess;
11564let mayLoad = 1;
11565let isRestrictNoSlot1Store = 1;
11566let mayStore = 1;
11567let isExtendable = 1;
11568let opExtendable = 1;
11569let isExtentSigned = 0;
11570let opExtentBits = 6;
11571let opExtentAlign = 0;
11572}
11573def L4_iand_memopb_zomap : HInst<
11574(outs),
11575(ins IntRegs:$Rs32, u5_0Imm:$II),
11576"memb($Rs32) = clrbit(#$II)",
11577tc_158aa3f7, TypeMAPPING> {
11578let isPseudo = 1;
11579let isCodeGenOnly = 1;
11580}
11581def L4_iand_memoph_io : HInst<
11582(outs),
11583(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11584"memh($Rs32+#$Ii) = clrbit(#$II)",
11585tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11586let Inst{6-5} = 0b10;
11587let Inst{13-13} = 0b0;
11588let Inst{31-21} = 0b00111111001;
11589let addrMode = BaseImmOffset;
11590let accessSize = HalfWordAccess;
11591let mayLoad = 1;
11592let isRestrictNoSlot1Store = 1;
11593let mayStore = 1;
11594let isExtendable = 1;
11595let opExtendable = 1;
11596let isExtentSigned = 0;
11597let opExtentBits = 7;
11598let opExtentAlign = 1;
11599}
11600def L4_iand_memoph_zomap : HInst<
11601(outs),
11602(ins IntRegs:$Rs32, u5_0Imm:$II),
11603"memh($Rs32) = clrbit(#$II)",
11604tc_158aa3f7, TypeMAPPING> {
11605let isPseudo = 1;
11606let isCodeGenOnly = 1;
11607}
11608def L4_iand_memopw_io : HInst<
11609(outs),
11610(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11611"memw($Rs32+#$Ii) = clrbit(#$II)",
11612tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11613let Inst{6-5} = 0b10;
11614let Inst{13-13} = 0b0;
11615let Inst{31-21} = 0b00111111010;
11616let addrMode = BaseImmOffset;
11617let accessSize = WordAccess;
11618let mayLoad = 1;
11619let isRestrictNoSlot1Store = 1;
11620let mayStore = 1;
11621let isExtendable = 1;
11622let opExtendable = 1;
11623let isExtentSigned = 0;
11624let opExtentBits = 8;
11625let opExtentAlign = 2;
11626}
11627def L4_iand_memopw_zomap : HInst<
11628(outs),
11629(ins IntRegs:$Rs32, u5_0Imm:$II),
11630"memw($Rs32) = clrbit(#$II)",
11631tc_158aa3f7, TypeMAPPING> {
11632let isPseudo = 1;
11633let isCodeGenOnly = 1;
11634}
11635def L4_ior_memopb_io : HInst<
11636(outs),
11637(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11638"memb($Rs32+#$Ii) = setbit(#$II)",
11639tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11640let Inst{6-5} = 0b11;
11641let Inst{13-13} = 0b0;
11642let Inst{31-21} = 0b00111111000;
11643let addrMode = BaseImmOffset;
11644let accessSize = ByteAccess;
11645let mayLoad = 1;
11646let isRestrictNoSlot1Store = 1;
11647let mayStore = 1;
11648let isExtendable = 1;
11649let opExtendable = 1;
11650let isExtentSigned = 0;
11651let opExtentBits = 6;
11652let opExtentAlign = 0;
11653}
11654def L4_ior_memopb_zomap : HInst<
11655(outs),
11656(ins IntRegs:$Rs32, u5_0Imm:$II),
11657"memb($Rs32) = setbit(#$II)",
11658tc_158aa3f7, TypeMAPPING> {
11659let isPseudo = 1;
11660let isCodeGenOnly = 1;
11661}
11662def L4_ior_memoph_io : HInst<
11663(outs),
11664(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11665"memh($Rs32+#$Ii) = setbit(#$II)",
11666tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11667let Inst{6-5} = 0b11;
11668let Inst{13-13} = 0b0;
11669let Inst{31-21} = 0b00111111001;
11670let addrMode = BaseImmOffset;
11671let accessSize = HalfWordAccess;
11672let mayLoad = 1;
11673let isRestrictNoSlot1Store = 1;
11674let mayStore = 1;
11675let isExtendable = 1;
11676let opExtendable = 1;
11677let isExtentSigned = 0;
11678let opExtentBits = 7;
11679let opExtentAlign = 1;
11680}
11681def L4_ior_memoph_zomap : HInst<
11682(outs),
11683(ins IntRegs:$Rs32, u5_0Imm:$II),
11684"memh($Rs32) = setbit(#$II)",
11685tc_158aa3f7, TypeMAPPING> {
11686let isPseudo = 1;
11687let isCodeGenOnly = 1;
11688}
11689def L4_ior_memopw_io : HInst<
11690(outs),
11691(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11692"memw($Rs32+#$Ii) = setbit(#$II)",
11693tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11694let Inst{6-5} = 0b11;
11695let Inst{13-13} = 0b0;
11696let Inst{31-21} = 0b00111111010;
11697let addrMode = BaseImmOffset;
11698let accessSize = WordAccess;
11699let mayLoad = 1;
11700let isRestrictNoSlot1Store = 1;
11701let mayStore = 1;
11702let isExtendable = 1;
11703let opExtendable = 1;
11704let isExtentSigned = 0;
11705let opExtentBits = 8;
11706let opExtentAlign = 2;
11707}
11708def L4_ior_memopw_zomap : HInst<
11709(outs),
11710(ins IntRegs:$Rs32, u5_0Imm:$II),
11711"memw($Rs32) = setbit(#$II)",
11712tc_158aa3f7, TypeMAPPING> {
11713let isPseudo = 1;
11714let isCodeGenOnly = 1;
11715}
11716def L4_isub_memopb_io : HInst<
11717(outs),
11718(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II),
11719"memb($Rs32+#$Ii) -= #$II",
11720tc_158aa3f7, TypeV4LDST>, Enc_46c951 {
11721let Inst{6-5} = 0b01;
11722let Inst{13-13} = 0b0;
11723let Inst{31-21} = 0b00111111000;
11724let addrMode = BaseImmOffset;
11725let accessSize = ByteAccess;
11726let mayLoad = 1;
11727let isRestrictNoSlot1Store = 1;
11728let mayStore = 1;
11729let isExtendable = 1;
11730let opExtendable = 1;
11731let isExtentSigned = 0;
11732let opExtentBits = 6;
11733let opExtentAlign = 0;
11734}
11735def L4_isub_memopb_zomap : HInst<
11736(outs),
11737(ins IntRegs:$Rs32, u5_0Imm:$II),
11738"memb($Rs32) -= #$II",
11739tc_158aa3f7, TypeMAPPING> {
11740let isPseudo = 1;
11741let isCodeGenOnly = 1;
11742}
11743def L4_isub_memoph_io : HInst<
11744(outs),
11745(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II),
11746"memh($Rs32+#$Ii) -= #$II",
11747tc_158aa3f7, TypeV4LDST>, Enc_e66a97 {
11748let Inst{6-5} = 0b01;
11749let Inst{13-13} = 0b0;
11750let Inst{31-21} = 0b00111111001;
11751let addrMode = BaseImmOffset;
11752let accessSize = HalfWordAccess;
11753let mayLoad = 1;
11754let isRestrictNoSlot1Store = 1;
11755let mayStore = 1;
11756let isExtendable = 1;
11757let opExtendable = 1;
11758let isExtentSigned = 0;
11759let opExtentBits = 7;
11760let opExtentAlign = 1;
11761}
11762def L4_isub_memoph_zomap : HInst<
11763(outs),
11764(ins IntRegs:$Rs32, u5_0Imm:$II),
11765"memh($Rs32) -= #$II",
11766tc_158aa3f7, TypeMAPPING> {
11767let isPseudo = 1;
11768let isCodeGenOnly = 1;
11769}
11770def L4_isub_memopw_io : HInst<
11771(outs),
11772(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II),
11773"memw($Rs32+#$Ii) -= #$II",
11774tc_158aa3f7, TypeV4LDST>, Enc_84b2cd {
11775let Inst{6-5} = 0b01;
11776let Inst{13-13} = 0b0;
11777let Inst{31-21} = 0b00111111010;
11778let addrMode = BaseImmOffset;
11779let accessSize = WordAccess;
11780let mayLoad = 1;
11781let isRestrictNoSlot1Store = 1;
11782let mayStore = 1;
11783let isExtendable = 1;
11784let opExtendable = 1;
11785let isExtentSigned = 0;
11786let opExtentBits = 8;
11787let opExtentAlign = 2;
11788}
11789def L4_isub_memopw_zomap : HInst<
11790(outs),
11791(ins IntRegs:$Rs32, u5_0Imm:$II),
11792"memw($Rs32) -= #$II",
11793tc_158aa3f7, TypeMAPPING> {
11794let isPseudo = 1;
11795let isCodeGenOnly = 1;
11796}
11797def L4_loadalignb_ap : HInst<
11798(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11799(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11800"$Ryy32 = memb_fifo($Re32=#$II)",
11801tc_ac65613f, TypeLD>, Enc_f394d3 {
11802let Inst{7-7} = 0b0;
11803let Inst{13-12} = 0b01;
11804let Inst{31-21} = 0b10011010100;
11805let addrMode = AbsoluteSet;
11806let accessSize = ByteAccess;
11807let mayLoad = 1;
11808let isExtended = 1;
11809let DecoderNamespace = "MustExtend";
11810let isExtendable = 1;
11811let opExtendable = 3;
11812let isExtentSigned = 0;
11813let opExtentBits = 6;
11814let opExtentAlign = 0;
11815let Constraints = "$Ryy32 = $Ryy32in";
11816}
11817def L4_loadalignb_ur : HInst<
11818(outs DoubleRegs:$Ryy32),
11819(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11820"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)",
11821tc_a32e03e7, TypeLD>, Enc_04c959 {
11822let Inst{12-12} = 0b1;
11823let Inst{31-21} = 0b10011100100;
11824let addrMode = BaseLongOffset;
11825let accessSize = ByteAccess;
11826let mayLoad = 1;
11827let isExtended = 1;
11828let InputType = "imm";
11829let DecoderNamespace = "MustExtend";
11830let isExtendable = 1;
11831let opExtendable = 4;
11832let isExtentSigned = 0;
11833let opExtentBits = 6;
11834let opExtentAlign = 0;
11835let Constraints = "$Ryy32 = $Ryy32in";
11836}
11837def L4_loadalignh_ap : HInst<
11838(outs DoubleRegs:$Ryy32, IntRegs:$Re32),
11839(ins DoubleRegs:$Ryy32in, u32_0Imm:$II),
11840"$Ryy32 = memh_fifo($Re32=#$II)",
11841tc_ac65613f, TypeLD>, Enc_f394d3 {
11842let Inst{7-7} = 0b0;
11843let Inst{13-12} = 0b01;
11844let Inst{31-21} = 0b10011010010;
11845let addrMode = AbsoluteSet;
11846let accessSize = HalfWordAccess;
11847let mayLoad = 1;
11848let isExtended = 1;
11849let DecoderNamespace = "MustExtend";
11850let isExtendable = 1;
11851let opExtendable = 3;
11852let isExtentSigned = 0;
11853let opExtentBits = 6;
11854let opExtentAlign = 0;
11855let Constraints = "$Ryy32 = $Ryy32in";
11856}
11857def L4_loadalignh_ur : HInst<
11858(outs DoubleRegs:$Ryy32),
11859(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11860"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)",
11861tc_a32e03e7, TypeLD>, Enc_04c959 {
11862let Inst{12-12} = 0b1;
11863let Inst{31-21} = 0b10011100010;
11864let addrMode = BaseLongOffset;
11865let accessSize = HalfWordAccess;
11866let mayLoad = 1;
11867let isExtended = 1;
11868let InputType = "imm";
11869let DecoderNamespace = "MustExtend";
11870let isExtendable = 1;
11871let opExtendable = 4;
11872let isExtentSigned = 0;
11873let opExtentBits = 6;
11874let opExtentAlign = 0;
11875let Constraints = "$Ryy32 = $Ryy32in";
11876}
11877def L4_loadbsw2_ap : HInst<
11878(outs IntRegs:$Rd32, IntRegs:$Re32),
11879(ins u32_0Imm:$II),
11880"$Rd32 = membh($Re32=#$II)",
11881tc_822c3c68, TypeLD>, Enc_323f2d {
11882let Inst{7-7} = 0b0;
11883let Inst{13-12} = 0b01;
11884let Inst{31-21} = 0b10011010001;
11885let hasNewValue = 1;
11886let opNewValue = 0;
11887let addrMode = AbsoluteSet;
11888let accessSize = HalfWordAccess;
11889let mayLoad = 1;
11890let isExtended = 1;
11891let DecoderNamespace = "MustExtend";
11892let isExtendable = 1;
11893let opExtendable = 2;
11894let isExtentSigned = 0;
11895let opExtentBits = 6;
11896let opExtentAlign = 0;
11897}
11898def L4_loadbsw2_ur : HInst<
11899(outs IntRegs:$Rd32),
11900(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11901"$Rd32 = membh($Rt32<<#$Ii+#$II)",
11902tc_abfd9a6d, TypeLD>, Enc_4f677b {
11903let Inst{12-12} = 0b1;
11904let Inst{31-21} = 0b10011100001;
11905let hasNewValue = 1;
11906let opNewValue = 0;
11907let addrMode = BaseLongOffset;
11908let accessSize = HalfWordAccess;
11909let mayLoad = 1;
11910let isExtended = 1;
11911let InputType = "imm";
11912let DecoderNamespace = "MustExtend";
11913let isExtendable = 1;
11914let opExtendable = 3;
11915let isExtentSigned = 0;
11916let opExtentBits = 6;
11917let opExtentAlign = 0;
11918}
11919def L4_loadbsw4_ap : HInst<
11920(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
11921(ins u32_0Imm:$II),
11922"$Rdd32 = membh($Re32=#$II)",
11923tc_822c3c68, TypeLD>, Enc_7fa7f6 {
11924let Inst{7-7} = 0b0;
11925let Inst{13-12} = 0b01;
11926let Inst{31-21} = 0b10011010111;
11927let addrMode = AbsoluteSet;
11928let accessSize = WordAccess;
11929let mayLoad = 1;
11930let isExtended = 1;
11931let DecoderNamespace = "MustExtend";
11932let isExtendable = 1;
11933let opExtendable = 2;
11934let isExtentSigned = 0;
11935let opExtentBits = 6;
11936let opExtentAlign = 0;
11937}
11938def L4_loadbsw4_ur : HInst<
11939(outs DoubleRegs:$Rdd32),
11940(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11941"$Rdd32 = membh($Rt32<<#$Ii+#$II)",
11942tc_abfd9a6d, TypeLD>, Enc_6185fe {
11943let Inst{12-12} = 0b1;
11944let Inst{31-21} = 0b10011100111;
11945let addrMode = BaseLongOffset;
11946let accessSize = WordAccess;
11947let mayLoad = 1;
11948let isExtended = 1;
11949let InputType = "imm";
11950let DecoderNamespace = "MustExtend";
11951let isExtendable = 1;
11952let opExtendable = 3;
11953let isExtentSigned = 0;
11954let opExtentBits = 6;
11955let opExtentAlign = 0;
11956}
11957def L4_loadbzw2_ap : HInst<
11958(outs IntRegs:$Rd32, IntRegs:$Re32),
11959(ins u32_0Imm:$II),
11960"$Rd32 = memubh($Re32=#$II)",
11961tc_822c3c68, TypeLD>, Enc_323f2d {
11962let Inst{7-7} = 0b0;
11963let Inst{13-12} = 0b01;
11964let Inst{31-21} = 0b10011010011;
11965let hasNewValue = 1;
11966let opNewValue = 0;
11967let addrMode = AbsoluteSet;
11968let accessSize = HalfWordAccess;
11969let mayLoad = 1;
11970let isExtended = 1;
11971let DecoderNamespace = "MustExtend";
11972let isExtendable = 1;
11973let opExtendable = 2;
11974let isExtentSigned = 0;
11975let opExtentBits = 6;
11976let opExtentAlign = 0;
11977}
11978def L4_loadbzw2_ur : HInst<
11979(outs IntRegs:$Rd32),
11980(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
11981"$Rd32 = memubh($Rt32<<#$Ii+#$II)",
11982tc_abfd9a6d, TypeLD>, Enc_4f677b {
11983let Inst{12-12} = 0b1;
11984let Inst{31-21} = 0b10011100011;
11985let hasNewValue = 1;
11986let opNewValue = 0;
11987let addrMode = BaseLongOffset;
11988let accessSize = HalfWordAccess;
11989let mayLoad = 1;
11990let isExtended = 1;
11991let InputType = "imm";
11992let DecoderNamespace = "MustExtend";
11993let isExtendable = 1;
11994let opExtendable = 3;
11995let isExtentSigned = 0;
11996let opExtentBits = 6;
11997let opExtentAlign = 0;
11998}
11999def L4_loadbzw4_ap : HInst<
12000(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12001(ins u32_0Imm:$II),
12002"$Rdd32 = memubh($Re32=#$II)",
12003tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12004let Inst{7-7} = 0b0;
12005let Inst{13-12} = 0b01;
12006let Inst{31-21} = 0b10011010101;
12007let addrMode = AbsoluteSet;
12008let accessSize = WordAccess;
12009let mayLoad = 1;
12010let isExtended = 1;
12011let DecoderNamespace = "MustExtend";
12012let isExtendable = 1;
12013let opExtendable = 2;
12014let isExtentSigned = 0;
12015let opExtentBits = 6;
12016let opExtentAlign = 0;
12017}
12018def L4_loadbzw4_ur : HInst<
12019(outs DoubleRegs:$Rdd32),
12020(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12021"$Rdd32 = memubh($Rt32<<#$Ii+#$II)",
12022tc_abfd9a6d, TypeLD>, Enc_6185fe {
12023let Inst{12-12} = 0b1;
12024let Inst{31-21} = 0b10011100101;
12025let addrMode = BaseLongOffset;
12026let accessSize = WordAccess;
12027let mayLoad = 1;
12028let isExtended = 1;
12029let InputType = "imm";
12030let DecoderNamespace = "MustExtend";
12031let isExtendable = 1;
12032let opExtendable = 3;
12033let isExtentSigned = 0;
12034let opExtentBits = 6;
12035let opExtentAlign = 0;
12036}
12037def L4_loadd_aq : HInst<
12038(outs DoubleRegs:$Rdd32),
12039(ins IntRegs:$Rs32),
12040"$Rdd32 = memd_aq($Rs32)",
12041tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> {
12042let Inst{13-5} = 0b011000000;
12043let Inst{31-21} = 0b10010010000;
12044let accessSize = DoubleWordAccess;
12045let mayLoad = 1;
12046}
12047def L4_loadd_locked : HInst<
12048(outs DoubleRegs:$Rdd32),
12049(ins IntRegs:$Rs32),
12050"$Rdd32 = memd_locked($Rs32)",
12051tc_64b00d8a, TypeLD>, Enc_3a3d62 {
12052let Inst{13-5} = 0b010000000;
12053let Inst{31-21} = 0b10010010000;
12054let accessSize = DoubleWordAccess;
12055let mayLoad = 1;
12056let isSoloAX = 1;
12057}
12058def L4_loadrb_ap : HInst<
12059(outs IntRegs:$Rd32, IntRegs:$Re32),
12060(ins u32_0Imm:$II),
12061"$Rd32 = memb($Re32=#$II)",
12062tc_822c3c68, TypeLD>, Enc_323f2d {
12063let Inst{7-7} = 0b0;
12064let Inst{13-12} = 0b01;
12065let Inst{31-21} = 0b10011011000;
12066let hasNewValue = 1;
12067let opNewValue = 0;
12068let addrMode = AbsoluteSet;
12069let accessSize = ByteAccess;
12070let mayLoad = 1;
12071let isExtended = 1;
12072let DecoderNamespace = "MustExtend";
12073let isExtendable = 1;
12074let opExtendable = 2;
12075let isExtentSigned = 0;
12076let opExtentBits = 6;
12077let opExtentAlign = 0;
12078}
12079def L4_loadrb_rr : HInst<
12080(outs IntRegs:$Rd32),
12081(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12082"$Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12083tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12084let Inst{6-5} = 0b00;
12085let Inst{31-21} = 0b00111010000;
12086let hasNewValue = 1;
12087let opNewValue = 0;
12088let addrMode = BaseRegOffset;
12089let accessSize = ByteAccess;
12090let mayLoad = 1;
12091let BaseOpcode = "L4_loadrb_rr";
12092let CextOpcode = "L2_loadrb";
12093let InputType = "reg";
12094let isPredicable = 1;
12095}
12096def L4_loadrb_ur : HInst<
12097(outs IntRegs:$Rd32),
12098(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12099"$Rd32 = memb($Rt32<<#$Ii+#$II)",
12100tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12101let Inst{12-12} = 0b1;
12102let Inst{31-21} = 0b10011101000;
12103let hasNewValue = 1;
12104let opNewValue = 0;
12105let addrMode = BaseLongOffset;
12106let accessSize = ByteAccess;
12107let mayLoad = 1;
12108let isExtended = 1;
12109let CextOpcode = "L2_loadrb";
12110let InputType = "imm";
12111let DecoderNamespace = "MustExtend";
12112let isExtendable = 1;
12113let opExtendable = 3;
12114let isExtentSigned = 0;
12115let opExtentBits = 6;
12116let opExtentAlign = 0;
12117}
12118def L4_loadrd_ap : HInst<
12119(outs DoubleRegs:$Rdd32, IntRegs:$Re32),
12120(ins u32_0Imm:$II),
12121"$Rdd32 = memd($Re32=#$II)",
12122tc_822c3c68, TypeLD>, Enc_7fa7f6 {
12123let Inst{7-7} = 0b0;
12124let Inst{13-12} = 0b01;
12125let Inst{31-21} = 0b10011011110;
12126let addrMode = AbsoluteSet;
12127let accessSize = DoubleWordAccess;
12128let mayLoad = 1;
12129let isExtended = 1;
12130let DecoderNamespace = "MustExtend";
12131let isExtendable = 1;
12132let opExtendable = 2;
12133let isExtentSigned = 0;
12134let opExtentBits = 6;
12135let opExtentAlign = 0;
12136}
12137def L4_loadrd_rr : HInst<
12138(outs DoubleRegs:$Rdd32),
12139(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12140"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12141tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl {
12142let Inst{6-5} = 0b00;
12143let Inst{31-21} = 0b00111010110;
12144let addrMode = BaseRegOffset;
12145let accessSize = DoubleWordAccess;
12146let mayLoad = 1;
12147let BaseOpcode = "L4_loadrd_rr";
12148let CextOpcode = "L2_loadrd";
12149let InputType = "reg";
12150let isPredicable = 1;
12151}
12152def L4_loadrd_ur : HInst<
12153(outs DoubleRegs:$Rdd32),
12154(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12155"$Rdd32 = memd($Rt32<<#$Ii+#$II)",
12156tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl {
12157let Inst{12-12} = 0b1;
12158let Inst{31-21} = 0b10011101110;
12159let addrMode = BaseLongOffset;
12160let accessSize = DoubleWordAccess;
12161let mayLoad = 1;
12162let isExtended = 1;
12163let CextOpcode = "L2_loadrd";
12164let InputType = "imm";
12165let DecoderNamespace = "MustExtend";
12166let isExtendable = 1;
12167let opExtendable = 3;
12168let isExtentSigned = 0;
12169let opExtentBits = 6;
12170let opExtentAlign = 0;
12171}
12172def L4_loadrh_ap : HInst<
12173(outs IntRegs:$Rd32, IntRegs:$Re32),
12174(ins u32_0Imm:$II),
12175"$Rd32 = memh($Re32=#$II)",
12176tc_822c3c68, TypeLD>, Enc_323f2d {
12177let Inst{7-7} = 0b0;
12178let Inst{13-12} = 0b01;
12179let Inst{31-21} = 0b10011011010;
12180let hasNewValue = 1;
12181let opNewValue = 0;
12182let addrMode = AbsoluteSet;
12183let accessSize = HalfWordAccess;
12184let mayLoad = 1;
12185let isExtended = 1;
12186let DecoderNamespace = "MustExtend";
12187let isExtendable = 1;
12188let opExtendable = 2;
12189let isExtentSigned = 0;
12190let opExtentBits = 6;
12191let opExtentAlign = 0;
12192}
12193def L4_loadrh_rr : HInst<
12194(outs IntRegs:$Rd32),
12195(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12196"$Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12197tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12198let Inst{6-5} = 0b00;
12199let Inst{31-21} = 0b00111010010;
12200let hasNewValue = 1;
12201let opNewValue = 0;
12202let addrMode = BaseRegOffset;
12203let accessSize = HalfWordAccess;
12204let mayLoad = 1;
12205let BaseOpcode = "L4_loadrh_rr";
12206let CextOpcode = "L2_loadrh";
12207let InputType = "reg";
12208let isPredicable = 1;
12209}
12210def L4_loadrh_ur : HInst<
12211(outs IntRegs:$Rd32),
12212(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12213"$Rd32 = memh($Rt32<<#$Ii+#$II)",
12214tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12215let Inst{12-12} = 0b1;
12216let Inst{31-21} = 0b10011101010;
12217let hasNewValue = 1;
12218let opNewValue = 0;
12219let addrMode = BaseLongOffset;
12220let accessSize = HalfWordAccess;
12221let mayLoad = 1;
12222let isExtended = 1;
12223let CextOpcode = "L2_loadrh";
12224let InputType = "imm";
12225let DecoderNamespace = "MustExtend";
12226let isExtendable = 1;
12227let opExtendable = 3;
12228let isExtentSigned = 0;
12229let opExtentBits = 6;
12230let opExtentAlign = 0;
12231}
12232def L4_loadri_ap : HInst<
12233(outs IntRegs:$Rd32, IntRegs:$Re32),
12234(ins u32_0Imm:$II),
12235"$Rd32 = memw($Re32=#$II)",
12236tc_822c3c68, TypeLD>, Enc_323f2d {
12237let Inst{7-7} = 0b0;
12238let Inst{13-12} = 0b01;
12239let Inst{31-21} = 0b10011011100;
12240let hasNewValue = 1;
12241let opNewValue = 0;
12242let addrMode = AbsoluteSet;
12243let accessSize = WordAccess;
12244let mayLoad = 1;
12245let isExtended = 1;
12246let DecoderNamespace = "MustExtend";
12247let isExtendable = 1;
12248let opExtendable = 2;
12249let isExtentSigned = 0;
12250let opExtentBits = 6;
12251let opExtentAlign = 0;
12252}
12253def L4_loadri_rr : HInst<
12254(outs IntRegs:$Rd32),
12255(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12256"$Rd32 = memw($Rs32+$Rt32<<#$Ii)",
12257tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12258let Inst{6-5} = 0b00;
12259let Inst{31-21} = 0b00111010100;
12260let hasNewValue = 1;
12261let opNewValue = 0;
12262let addrMode = BaseRegOffset;
12263let accessSize = WordAccess;
12264let mayLoad = 1;
12265let BaseOpcode = "L4_loadri_rr";
12266let CextOpcode = "L2_loadri";
12267let InputType = "reg";
12268let isPredicable = 1;
12269}
12270def L4_loadri_ur : HInst<
12271(outs IntRegs:$Rd32),
12272(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12273"$Rd32 = memw($Rt32<<#$Ii+#$II)",
12274tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12275let Inst{12-12} = 0b1;
12276let Inst{31-21} = 0b10011101100;
12277let hasNewValue = 1;
12278let opNewValue = 0;
12279let addrMode = BaseLongOffset;
12280let accessSize = WordAccess;
12281let mayLoad = 1;
12282let isExtended = 1;
12283let CextOpcode = "L2_loadri";
12284let InputType = "imm";
12285let DecoderNamespace = "MustExtend";
12286let isExtendable = 1;
12287let opExtendable = 3;
12288let isExtentSigned = 0;
12289let opExtentBits = 6;
12290let opExtentAlign = 0;
12291}
12292def L4_loadrub_ap : HInst<
12293(outs IntRegs:$Rd32, IntRegs:$Re32),
12294(ins u32_0Imm:$II),
12295"$Rd32 = memub($Re32=#$II)",
12296tc_822c3c68, TypeLD>, Enc_323f2d {
12297let Inst{7-7} = 0b0;
12298let Inst{13-12} = 0b01;
12299let Inst{31-21} = 0b10011011001;
12300let hasNewValue = 1;
12301let opNewValue = 0;
12302let addrMode = AbsoluteSet;
12303let accessSize = ByteAccess;
12304let mayLoad = 1;
12305let isExtended = 1;
12306let DecoderNamespace = "MustExtend";
12307let isExtendable = 1;
12308let opExtendable = 2;
12309let isExtentSigned = 0;
12310let opExtentBits = 6;
12311let opExtentAlign = 0;
12312}
12313def L4_loadrub_rr : HInst<
12314(outs IntRegs:$Rd32),
12315(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12316"$Rd32 = memub($Rs32+$Rt32<<#$Ii)",
12317tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12318let Inst{6-5} = 0b00;
12319let Inst{31-21} = 0b00111010001;
12320let hasNewValue = 1;
12321let opNewValue = 0;
12322let addrMode = BaseRegOffset;
12323let accessSize = ByteAccess;
12324let mayLoad = 1;
12325let BaseOpcode = "L4_loadrub_rr";
12326let CextOpcode = "L2_loadrub";
12327let InputType = "reg";
12328let isPredicable = 1;
12329}
12330def L4_loadrub_ur : HInst<
12331(outs IntRegs:$Rd32),
12332(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12333"$Rd32 = memub($Rt32<<#$Ii+#$II)",
12334tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12335let Inst{12-12} = 0b1;
12336let Inst{31-21} = 0b10011101001;
12337let hasNewValue = 1;
12338let opNewValue = 0;
12339let addrMode = BaseLongOffset;
12340let accessSize = ByteAccess;
12341let mayLoad = 1;
12342let isExtended = 1;
12343let CextOpcode = "L2_loadrub";
12344let InputType = "imm";
12345let DecoderNamespace = "MustExtend";
12346let isExtendable = 1;
12347let opExtendable = 3;
12348let isExtentSigned = 0;
12349let opExtentBits = 6;
12350let opExtentAlign = 0;
12351}
12352def L4_loadruh_ap : HInst<
12353(outs IntRegs:$Rd32, IntRegs:$Re32),
12354(ins u32_0Imm:$II),
12355"$Rd32 = memuh($Re32=#$II)",
12356tc_822c3c68, TypeLD>, Enc_323f2d {
12357let Inst{7-7} = 0b0;
12358let Inst{13-12} = 0b01;
12359let Inst{31-21} = 0b10011011011;
12360let hasNewValue = 1;
12361let opNewValue = 0;
12362let addrMode = AbsoluteSet;
12363let accessSize = HalfWordAccess;
12364let mayLoad = 1;
12365let isExtended = 1;
12366let DecoderNamespace = "MustExtend";
12367let isExtendable = 1;
12368let opExtendable = 2;
12369let isExtentSigned = 0;
12370let opExtentBits = 6;
12371let opExtentAlign = 0;
12372}
12373def L4_loadruh_rr : HInst<
12374(outs IntRegs:$Rd32),
12375(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12376"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
12377tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl {
12378let Inst{6-5} = 0b00;
12379let Inst{31-21} = 0b00111010011;
12380let hasNewValue = 1;
12381let opNewValue = 0;
12382let addrMode = BaseRegOffset;
12383let accessSize = HalfWordAccess;
12384let mayLoad = 1;
12385let BaseOpcode = "L4_loadruh_rr";
12386let CextOpcode = "L2_loadruh";
12387let InputType = "reg";
12388let isPredicable = 1;
12389}
12390def L4_loadruh_ur : HInst<
12391(outs IntRegs:$Rd32),
12392(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II),
12393"$Rd32 = memuh($Rt32<<#$Ii+#$II)",
12394tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl {
12395let Inst{12-12} = 0b1;
12396let Inst{31-21} = 0b10011101011;
12397let hasNewValue = 1;
12398let opNewValue = 0;
12399let addrMode = BaseLongOffset;
12400let accessSize = HalfWordAccess;
12401let mayLoad = 1;
12402let isExtended = 1;
12403let CextOpcode = "L2_loadruh";
12404let InputType = "imm";
12405let DecoderNamespace = "MustExtend";
12406let isExtendable = 1;
12407let opExtendable = 3;
12408let isExtentSigned = 0;
12409let opExtentBits = 6;
12410let opExtentAlign = 0;
12411}
12412def L4_or_memopb_io : HInst<
12413(outs),
12414(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
12415"memb($Rs32+#$Ii) |= $Rt32",
12416tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
12417let Inst{6-5} = 0b11;
12418let Inst{13-13} = 0b0;
12419let Inst{31-21} = 0b00111110000;
12420let addrMode = BaseImmOffset;
12421let accessSize = ByteAccess;
12422let mayLoad = 1;
12423let isRestrictNoSlot1Store = 1;
12424let mayStore = 1;
12425let isExtendable = 1;
12426let opExtendable = 1;
12427let isExtentSigned = 0;
12428let opExtentBits = 6;
12429let opExtentAlign = 0;
12430}
12431def L4_or_memopb_zomap : HInst<
12432(outs),
12433(ins IntRegs:$Rs32, IntRegs:$Rt32),
12434"memb($Rs32) |= $Rt32",
12435tc_9bcfb2ee, TypeMAPPING> {
12436let isPseudo = 1;
12437let isCodeGenOnly = 1;
12438}
12439def L4_or_memoph_io : HInst<
12440(outs),
12441(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
12442"memh($Rs32+#$Ii) |= $Rt32",
12443tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
12444let Inst{6-5} = 0b11;
12445let Inst{13-13} = 0b0;
12446let Inst{31-21} = 0b00111110001;
12447let addrMode = BaseImmOffset;
12448let accessSize = HalfWordAccess;
12449let mayLoad = 1;
12450let isRestrictNoSlot1Store = 1;
12451let mayStore = 1;
12452let isExtendable = 1;
12453let opExtendable = 1;
12454let isExtentSigned = 0;
12455let opExtentBits = 7;
12456let opExtentAlign = 1;
12457}
12458def L4_or_memoph_zomap : HInst<
12459(outs),
12460(ins IntRegs:$Rs32, IntRegs:$Rt32),
12461"memh($Rs32) |= $Rt32",
12462tc_9bcfb2ee, TypeMAPPING> {
12463let isPseudo = 1;
12464let isCodeGenOnly = 1;
12465}
12466def L4_or_memopw_io : HInst<
12467(outs),
12468(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
12469"memw($Rs32+#$Ii) |= $Rt32",
12470tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
12471let Inst{6-5} = 0b11;
12472let Inst{13-13} = 0b0;
12473let Inst{31-21} = 0b00111110010;
12474let addrMode = BaseImmOffset;
12475let accessSize = WordAccess;
12476let mayLoad = 1;
12477let isRestrictNoSlot1Store = 1;
12478let mayStore = 1;
12479let isExtendable = 1;
12480let opExtendable = 1;
12481let isExtentSigned = 0;
12482let opExtentBits = 8;
12483let opExtentAlign = 2;
12484}
12485def L4_or_memopw_zomap : HInst<
12486(outs),
12487(ins IntRegs:$Rs32, IntRegs:$Rt32),
12488"memw($Rs32) |= $Rt32",
12489tc_9bcfb2ee, TypeMAPPING> {
12490let isPseudo = 1;
12491let isCodeGenOnly = 1;
12492}
12493def L4_ploadrbf_abs : HInst<
12494(outs IntRegs:$Rd32),
12495(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12496"if (!$Pt4) $Rd32 = memb(#$Ii)",
12497tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12498let Inst{7-5} = 0b100;
12499let Inst{13-11} = 0b101;
12500let Inst{31-21} = 0b10011111000;
12501let isPredicated = 1;
12502let isPredicatedFalse = 1;
12503let hasNewValue = 1;
12504let opNewValue = 0;
12505let addrMode = Absolute;
12506let accessSize = ByteAccess;
12507let mayLoad = 1;
12508let isExtended = 1;
12509let BaseOpcode = "L4_loadrb_abs";
12510let CextOpcode = "L2_loadrb";
12511let DecoderNamespace = "MustExtend";
12512let isExtendable = 1;
12513let opExtendable = 2;
12514let isExtentSigned = 0;
12515let opExtentBits = 6;
12516let opExtentAlign = 0;
12517}
12518def L4_ploadrbf_rr : HInst<
12519(outs IntRegs:$Rd32),
12520(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12521"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12522tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12523let Inst{31-21} = 0b00110001000;
12524let isPredicated = 1;
12525let isPredicatedFalse = 1;
12526let hasNewValue = 1;
12527let opNewValue = 0;
12528let addrMode = BaseRegOffset;
12529let accessSize = ByteAccess;
12530let mayLoad = 1;
12531let BaseOpcode = "L4_loadrb_rr";
12532let CextOpcode = "L2_loadrb";
12533let InputType = "reg";
12534}
12535def L4_ploadrbfnew_abs : HInst<
12536(outs IntRegs:$Rd32),
12537(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12538"if (!$Pt4.new) $Rd32 = memb(#$Ii)",
12539tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12540let Inst{7-5} = 0b100;
12541let Inst{13-11} = 0b111;
12542let Inst{31-21} = 0b10011111000;
12543let isPredicated = 1;
12544let isPredicatedFalse = 1;
12545let hasNewValue = 1;
12546let opNewValue = 0;
12547let addrMode = Absolute;
12548let accessSize = ByteAccess;
12549let isPredicatedNew = 1;
12550let mayLoad = 1;
12551let isExtended = 1;
12552let BaseOpcode = "L4_loadrb_abs";
12553let CextOpcode = "L2_loadrb";
12554let DecoderNamespace = "MustExtend";
12555let isExtendable = 1;
12556let opExtendable = 2;
12557let isExtentSigned = 0;
12558let opExtentBits = 6;
12559let opExtentAlign = 0;
12560}
12561def L4_ploadrbfnew_rr : HInst<
12562(outs IntRegs:$Rd32),
12563(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12564"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12565tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12566let Inst{31-21} = 0b00110011000;
12567let isPredicated = 1;
12568let isPredicatedFalse = 1;
12569let hasNewValue = 1;
12570let opNewValue = 0;
12571let addrMode = BaseRegOffset;
12572let accessSize = ByteAccess;
12573let isPredicatedNew = 1;
12574let mayLoad = 1;
12575let BaseOpcode = "L4_loadrb_rr";
12576let CextOpcode = "L2_loadrb";
12577let InputType = "reg";
12578}
12579def L4_ploadrbt_abs : HInst<
12580(outs IntRegs:$Rd32),
12581(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12582"if ($Pt4) $Rd32 = memb(#$Ii)",
12583tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12584let Inst{7-5} = 0b100;
12585let Inst{13-11} = 0b100;
12586let Inst{31-21} = 0b10011111000;
12587let isPredicated = 1;
12588let hasNewValue = 1;
12589let opNewValue = 0;
12590let addrMode = Absolute;
12591let accessSize = ByteAccess;
12592let mayLoad = 1;
12593let isExtended = 1;
12594let BaseOpcode = "L4_loadrb_abs";
12595let CextOpcode = "L2_loadrb";
12596let DecoderNamespace = "MustExtend";
12597let isExtendable = 1;
12598let opExtendable = 2;
12599let isExtentSigned = 0;
12600let opExtentBits = 6;
12601let opExtentAlign = 0;
12602}
12603def L4_ploadrbt_rr : HInst<
12604(outs IntRegs:$Rd32),
12605(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12606"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12607tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12608let Inst{31-21} = 0b00110000000;
12609let isPredicated = 1;
12610let hasNewValue = 1;
12611let opNewValue = 0;
12612let addrMode = BaseRegOffset;
12613let accessSize = ByteAccess;
12614let mayLoad = 1;
12615let BaseOpcode = "L4_loadrb_rr";
12616let CextOpcode = "L2_loadrb";
12617let InputType = "reg";
12618}
12619def L4_ploadrbtnew_abs : HInst<
12620(outs IntRegs:$Rd32),
12621(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12622"if ($Pt4.new) $Rd32 = memb(#$Ii)",
12623tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12624let Inst{7-5} = 0b100;
12625let Inst{13-11} = 0b110;
12626let Inst{31-21} = 0b10011111000;
12627let isPredicated = 1;
12628let hasNewValue = 1;
12629let opNewValue = 0;
12630let addrMode = Absolute;
12631let accessSize = ByteAccess;
12632let isPredicatedNew = 1;
12633let mayLoad = 1;
12634let isExtended = 1;
12635let BaseOpcode = "L4_loadrb_abs";
12636let CextOpcode = "L2_loadrb";
12637let DecoderNamespace = "MustExtend";
12638let isExtendable = 1;
12639let opExtendable = 2;
12640let isExtentSigned = 0;
12641let opExtentBits = 6;
12642let opExtentAlign = 0;
12643}
12644def L4_ploadrbtnew_rr : HInst<
12645(outs IntRegs:$Rd32),
12646(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12647"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)",
12648tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12649let Inst{31-21} = 0b00110010000;
12650let isPredicated = 1;
12651let hasNewValue = 1;
12652let opNewValue = 0;
12653let addrMode = BaseRegOffset;
12654let accessSize = ByteAccess;
12655let isPredicatedNew = 1;
12656let mayLoad = 1;
12657let BaseOpcode = "L4_loadrb_rr";
12658let CextOpcode = "L2_loadrb";
12659let InputType = "reg";
12660}
12661def L4_ploadrdf_abs : HInst<
12662(outs DoubleRegs:$Rdd32),
12663(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12664"if (!$Pt4) $Rdd32 = memd(#$Ii)",
12665tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12666let Inst{7-5} = 0b100;
12667let Inst{13-11} = 0b101;
12668let Inst{31-21} = 0b10011111110;
12669let isPredicated = 1;
12670let isPredicatedFalse = 1;
12671let addrMode = Absolute;
12672let accessSize = DoubleWordAccess;
12673let mayLoad = 1;
12674let isExtended = 1;
12675let BaseOpcode = "L4_loadrd_abs";
12676let CextOpcode = "L2_loadrd";
12677let DecoderNamespace = "MustExtend";
12678let isExtendable = 1;
12679let opExtendable = 2;
12680let isExtentSigned = 0;
12681let opExtentBits = 6;
12682let opExtentAlign = 0;
12683}
12684def L4_ploadrdf_rr : HInst<
12685(outs DoubleRegs:$Rdd32),
12686(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12687"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12688tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12689let Inst{31-21} = 0b00110001110;
12690let isPredicated = 1;
12691let isPredicatedFalse = 1;
12692let addrMode = BaseRegOffset;
12693let accessSize = DoubleWordAccess;
12694let mayLoad = 1;
12695let BaseOpcode = "L4_loadrd_rr";
12696let CextOpcode = "L2_loadrd";
12697let InputType = "reg";
12698}
12699def L4_ploadrdfnew_abs : HInst<
12700(outs DoubleRegs:$Rdd32),
12701(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12702"if (!$Pt4.new) $Rdd32 = memd(#$Ii)",
12703tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12704let Inst{7-5} = 0b100;
12705let Inst{13-11} = 0b111;
12706let Inst{31-21} = 0b10011111110;
12707let isPredicated = 1;
12708let isPredicatedFalse = 1;
12709let addrMode = Absolute;
12710let accessSize = DoubleWordAccess;
12711let isPredicatedNew = 1;
12712let mayLoad = 1;
12713let isExtended = 1;
12714let BaseOpcode = "L4_loadrd_abs";
12715let CextOpcode = "L2_loadrd";
12716let DecoderNamespace = "MustExtend";
12717let isExtendable = 1;
12718let opExtendable = 2;
12719let isExtentSigned = 0;
12720let opExtentBits = 6;
12721let opExtentAlign = 0;
12722}
12723def L4_ploadrdfnew_rr : HInst<
12724(outs DoubleRegs:$Rdd32),
12725(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12726"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12727tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12728let Inst{31-21} = 0b00110011110;
12729let isPredicated = 1;
12730let isPredicatedFalse = 1;
12731let addrMode = BaseRegOffset;
12732let accessSize = DoubleWordAccess;
12733let isPredicatedNew = 1;
12734let mayLoad = 1;
12735let BaseOpcode = "L4_loadrd_rr";
12736let CextOpcode = "L2_loadrd";
12737let InputType = "reg";
12738}
12739def L4_ploadrdt_abs : HInst<
12740(outs DoubleRegs:$Rdd32),
12741(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12742"if ($Pt4) $Rdd32 = memd(#$Ii)",
12743tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel {
12744let Inst{7-5} = 0b100;
12745let Inst{13-11} = 0b100;
12746let Inst{31-21} = 0b10011111110;
12747let isPredicated = 1;
12748let addrMode = Absolute;
12749let accessSize = DoubleWordAccess;
12750let mayLoad = 1;
12751let isExtended = 1;
12752let BaseOpcode = "L4_loadrd_abs";
12753let CextOpcode = "L2_loadrd";
12754let DecoderNamespace = "MustExtend";
12755let isExtendable = 1;
12756let opExtendable = 2;
12757let isExtentSigned = 0;
12758let opExtentBits = 6;
12759let opExtentAlign = 0;
12760}
12761def L4_ploadrdt_rr : HInst<
12762(outs DoubleRegs:$Rdd32),
12763(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12764"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12765tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel {
12766let Inst{31-21} = 0b00110000110;
12767let isPredicated = 1;
12768let addrMode = BaseRegOffset;
12769let accessSize = DoubleWordAccess;
12770let mayLoad = 1;
12771let BaseOpcode = "L4_loadrd_rr";
12772let CextOpcode = "L2_loadrd";
12773let InputType = "reg";
12774}
12775def L4_ploadrdtnew_abs : HInst<
12776(outs DoubleRegs:$Rdd32),
12777(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12778"if ($Pt4.new) $Rdd32 = memd(#$Ii)",
12779tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel {
12780let Inst{7-5} = 0b100;
12781let Inst{13-11} = 0b110;
12782let Inst{31-21} = 0b10011111110;
12783let isPredicated = 1;
12784let addrMode = Absolute;
12785let accessSize = DoubleWordAccess;
12786let isPredicatedNew = 1;
12787let mayLoad = 1;
12788let isExtended = 1;
12789let BaseOpcode = "L4_loadrd_abs";
12790let CextOpcode = "L2_loadrd";
12791let DecoderNamespace = "MustExtend";
12792let isExtendable = 1;
12793let opExtendable = 2;
12794let isExtentSigned = 0;
12795let opExtentBits = 6;
12796let opExtentAlign = 0;
12797}
12798def L4_ploadrdtnew_rr : HInst<
12799(outs DoubleRegs:$Rdd32),
12800(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12801"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)",
12802tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel {
12803let Inst{31-21} = 0b00110010110;
12804let isPredicated = 1;
12805let addrMode = BaseRegOffset;
12806let accessSize = DoubleWordAccess;
12807let isPredicatedNew = 1;
12808let mayLoad = 1;
12809let BaseOpcode = "L4_loadrd_rr";
12810let CextOpcode = "L2_loadrd";
12811let InputType = "reg";
12812}
12813def L4_ploadrhf_abs : HInst<
12814(outs IntRegs:$Rd32),
12815(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12816"if (!$Pt4) $Rd32 = memh(#$Ii)",
12817tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12818let Inst{7-5} = 0b100;
12819let Inst{13-11} = 0b101;
12820let Inst{31-21} = 0b10011111010;
12821let isPredicated = 1;
12822let isPredicatedFalse = 1;
12823let hasNewValue = 1;
12824let opNewValue = 0;
12825let addrMode = Absolute;
12826let accessSize = HalfWordAccess;
12827let mayLoad = 1;
12828let isExtended = 1;
12829let BaseOpcode = "L4_loadrh_abs";
12830let CextOpcode = "L2_loadrh";
12831let DecoderNamespace = "MustExtend";
12832let isExtendable = 1;
12833let opExtendable = 2;
12834let isExtentSigned = 0;
12835let opExtentBits = 6;
12836let opExtentAlign = 0;
12837}
12838def L4_ploadrhf_rr : HInst<
12839(outs IntRegs:$Rd32),
12840(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12841"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12842tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12843let Inst{31-21} = 0b00110001010;
12844let isPredicated = 1;
12845let isPredicatedFalse = 1;
12846let hasNewValue = 1;
12847let opNewValue = 0;
12848let addrMode = BaseRegOffset;
12849let accessSize = HalfWordAccess;
12850let mayLoad = 1;
12851let BaseOpcode = "L4_loadrh_rr";
12852let CextOpcode = "L2_loadrh";
12853let InputType = "reg";
12854}
12855def L4_ploadrhfnew_abs : HInst<
12856(outs IntRegs:$Rd32),
12857(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12858"if (!$Pt4.new) $Rd32 = memh(#$Ii)",
12859tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12860let Inst{7-5} = 0b100;
12861let Inst{13-11} = 0b111;
12862let Inst{31-21} = 0b10011111010;
12863let isPredicated = 1;
12864let isPredicatedFalse = 1;
12865let hasNewValue = 1;
12866let opNewValue = 0;
12867let addrMode = Absolute;
12868let accessSize = HalfWordAccess;
12869let isPredicatedNew = 1;
12870let mayLoad = 1;
12871let isExtended = 1;
12872let BaseOpcode = "L4_loadrh_abs";
12873let CextOpcode = "L2_loadrh";
12874let DecoderNamespace = "MustExtend";
12875let isExtendable = 1;
12876let opExtendable = 2;
12877let isExtentSigned = 0;
12878let opExtentBits = 6;
12879let opExtentAlign = 0;
12880}
12881def L4_ploadrhfnew_rr : HInst<
12882(outs IntRegs:$Rd32),
12883(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12884"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12885tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12886let Inst{31-21} = 0b00110011010;
12887let isPredicated = 1;
12888let isPredicatedFalse = 1;
12889let hasNewValue = 1;
12890let opNewValue = 0;
12891let addrMode = BaseRegOffset;
12892let accessSize = HalfWordAccess;
12893let isPredicatedNew = 1;
12894let mayLoad = 1;
12895let BaseOpcode = "L4_loadrh_rr";
12896let CextOpcode = "L2_loadrh";
12897let InputType = "reg";
12898}
12899def L4_ploadrht_abs : HInst<
12900(outs IntRegs:$Rd32),
12901(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12902"if ($Pt4) $Rd32 = memh(#$Ii)",
12903tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12904let Inst{7-5} = 0b100;
12905let Inst{13-11} = 0b100;
12906let Inst{31-21} = 0b10011111010;
12907let isPredicated = 1;
12908let hasNewValue = 1;
12909let opNewValue = 0;
12910let addrMode = Absolute;
12911let accessSize = HalfWordAccess;
12912let mayLoad = 1;
12913let isExtended = 1;
12914let BaseOpcode = "L4_loadrh_abs";
12915let CextOpcode = "L2_loadrh";
12916let DecoderNamespace = "MustExtend";
12917let isExtendable = 1;
12918let opExtendable = 2;
12919let isExtentSigned = 0;
12920let opExtentBits = 6;
12921let opExtentAlign = 0;
12922}
12923def L4_ploadrht_rr : HInst<
12924(outs IntRegs:$Rd32),
12925(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12926"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12927tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
12928let Inst{31-21} = 0b00110000010;
12929let isPredicated = 1;
12930let hasNewValue = 1;
12931let opNewValue = 0;
12932let addrMode = BaseRegOffset;
12933let accessSize = HalfWordAccess;
12934let mayLoad = 1;
12935let BaseOpcode = "L4_loadrh_rr";
12936let CextOpcode = "L2_loadrh";
12937let InputType = "reg";
12938}
12939def L4_ploadrhtnew_abs : HInst<
12940(outs IntRegs:$Rd32),
12941(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12942"if ($Pt4.new) $Rd32 = memh(#$Ii)",
12943tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
12944let Inst{7-5} = 0b100;
12945let Inst{13-11} = 0b110;
12946let Inst{31-21} = 0b10011111010;
12947let isPredicated = 1;
12948let hasNewValue = 1;
12949let opNewValue = 0;
12950let addrMode = Absolute;
12951let accessSize = HalfWordAccess;
12952let isPredicatedNew = 1;
12953let mayLoad = 1;
12954let isExtended = 1;
12955let BaseOpcode = "L4_loadrh_abs";
12956let CextOpcode = "L2_loadrh";
12957let DecoderNamespace = "MustExtend";
12958let isExtendable = 1;
12959let opExtendable = 2;
12960let isExtentSigned = 0;
12961let opExtentBits = 6;
12962let opExtentAlign = 0;
12963}
12964def L4_ploadrhtnew_rr : HInst<
12965(outs IntRegs:$Rd32),
12966(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
12967"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)",
12968tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
12969let Inst{31-21} = 0b00110010010;
12970let isPredicated = 1;
12971let hasNewValue = 1;
12972let opNewValue = 0;
12973let addrMode = BaseRegOffset;
12974let accessSize = HalfWordAccess;
12975let isPredicatedNew = 1;
12976let mayLoad = 1;
12977let BaseOpcode = "L4_loadrh_rr";
12978let CextOpcode = "L2_loadrh";
12979let InputType = "reg";
12980}
12981def L4_ploadrif_abs : HInst<
12982(outs IntRegs:$Rd32),
12983(ins PredRegs:$Pt4, u32_0Imm:$Ii),
12984"if (!$Pt4) $Rd32 = memw(#$Ii)",
12985tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
12986let Inst{7-5} = 0b100;
12987let Inst{13-11} = 0b101;
12988let Inst{31-21} = 0b10011111100;
12989let isPredicated = 1;
12990let isPredicatedFalse = 1;
12991let hasNewValue = 1;
12992let opNewValue = 0;
12993let addrMode = Absolute;
12994let accessSize = WordAccess;
12995let mayLoad = 1;
12996let isExtended = 1;
12997let BaseOpcode = "L4_loadri_abs";
12998let CextOpcode = "L2_loadri";
12999let DecoderNamespace = "MustExtend";
13000let isExtendable = 1;
13001let opExtendable = 2;
13002let isExtentSigned = 0;
13003let opExtentBits = 6;
13004let opExtentAlign = 0;
13005}
13006def L4_ploadrif_rr : HInst<
13007(outs IntRegs:$Rd32),
13008(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13009"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13010tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13011let Inst{31-21} = 0b00110001100;
13012let isPredicated = 1;
13013let isPredicatedFalse = 1;
13014let hasNewValue = 1;
13015let opNewValue = 0;
13016let addrMode = BaseRegOffset;
13017let accessSize = WordAccess;
13018let mayLoad = 1;
13019let BaseOpcode = "L4_loadri_rr";
13020let CextOpcode = "L2_loadri";
13021let InputType = "reg";
13022}
13023def L4_ploadrifnew_abs : HInst<
13024(outs IntRegs:$Rd32),
13025(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13026"if (!$Pt4.new) $Rd32 = memw(#$Ii)",
13027tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13028let Inst{7-5} = 0b100;
13029let Inst{13-11} = 0b111;
13030let Inst{31-21} = 0b10011111100;
13031let isPredicated = 1;
13032let isPredicatedFalse = 1;
13033let hasNewValue = 1;
13034let opNewValue = 0;
13035let addrMode = Absolute;
13036let accessSize = WordAccess;
13037let isPredicatedNew = 1;
13038let mayLoad = 1;
13039let isExtended = 1;
13040let BaseOpcode = "L4_loadri_abs";
13041let CextOpcode = "L2_loadri";
13042let DecoderNamespace = "MustExtend";
13043let isExtendable = 1;
13044let opExtendable = 2;
13045let isExtentSigned = 0;
13046let opExtentBits = 6;
13047let opExtentAlign = 0;
13048}
13049def L4_ploadrifnew_rr : HInst<
13050(outs IntRegs:$Rd32),
13051(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13052"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13053tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13054let Inst{31-21} = 0b00110011100;
13055let isPredicated = 1;
13056let isPredicatedFalse = 1;
13057let hasNewValue = 1;
13058let opNewValue = 0;
13059let addrMode = BaseRegOffset;
13060let accessSize = WordAccess;
13061let isPredicatedNew = 1;
13062let mayLoad = 1;
13063let BaseOpcode = "L4_loadri_rr";
13064let CextOpcode = "L2_loadri";
13065let InputType = "reg";
13066}
13067def L4_ploadrit_abs : HInst<
13068(outs IntRegs:$Rd32),
13069(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13070"if ($Pt4) $Rd32 = memw(#$Ii)",
13071tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13072let Inst{7-5} = 0b100;
13073let Inst{13-11} = 0b100;
13074let Inst{31-21} = 0b10011111100;
13075let isPredicated = 1;
13076let hasNewValue = 1;
13077let opNewValue = 0;
13078let addrMode = Absolute;
13079let accessSize = WordAccess;
13080let mayLoad = 1;
13081let isExtended = 1;
13082let BaseOpcode = "L4_loadri_abs";
13083let CextOpcode = "L2_loadri";
13084let DecoderNamespace = "MustExtend";
13085let isExtendable = 1;
13086let opExtendable = 2;
13087let isExtentSigned = 0;
13088let opExtentBits = 6;
13089let opExtentAlign = 0;
13090}
13091def L4_ploadrit_rr : HInst<
13092(outs IntRegs:$Rd32),
13093(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13094"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13095tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13096let Inst{31-21} = 0b00110000100;
13097let isPredicated = 1;
13098let hasNewValue = 1;
13099let opNewValue = 0;
13100let addrMode = BaseRegOffset;
13101let accessSize = WordAccess;
13102let mayLoad = 1;
13103let BaseOpcode = "L4_loadri_rr";
13104let CextOpcode = "L2_loadri";
13105let InputType = "reg";
13106}
13107def L4_ploadritnew_abs : HInst<
13108(outs IntRegs:$Rd32),
13109(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13110"if ($Pt4.new) $Rd32 = memw(#$Ii)",
13111tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13112let Inst{7-5} = 0b100;
13113let Inst{13-11} = 0b110;
13114let Inst{31-21} = 0b10011111100;
13115let isPredicated = 1;
13116let hasNewValue = 1;
13117let opNewValue = 0;
13118let addrMode = Absolute;
13119let accessSize = WordAccess;
13120let isPredicatedNew = 1;
13121let mayLoad = 1;
13122let isExtended = 1;
13123let BaseOpcode = "L4_loadri_abs";
13124let CextOpcode = "L2_loadri";
13125let DecoderNamespace = "MustExtend";
13126let isExtendable = 1;
13127let opExtendable = 2;
13128let isExtentSigned = 0;
13129let opExtentBits = 6;
13130let opExtentAlign = 0;
13131}
13132def L4_ploadritnew_rr : HInst<
13133(outs IntRegs:$Rd32),
13134(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13135"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)",
13136tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13137let Inst{31-21} = 0b00110010100;
13138let isPredicated = 1;
13139let hasNewValue = 1;
13140let opNewValue = 0;
13141let addrMode = BaseRegOffset;
13142let accessSize = WordAccess;
13143let isPredicatedNew = 1;
13144let mayLoad = 1;
13145let BaseOpcode = "L4_loadri_rr";
13146let CextOpcode = "L2_loadri";
13147let InputType = "reg";
13148}
13149def L4_ploadrubf_abs : HInst<
13150(outs IntRegs:$Rd32),
13151(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13152"if (!$Pt4) $Rd32 = memub(#$Ii)",
13153tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13154let Inst{7-5} = 0b100;
13155let Inst{13-11} = 0b101;
13156let Inst{31-21} = 0b10011111001;
13157let isPredicated = 1;
13158let isPredicatedFalse = 1;
13159let hasNewValue = 1;
13160let opNewValue = 0;
13161let addrMode = Absolute;
13162let accessSize = ByteAccess;
13163let mayLoad = 1;
13164let isExtended = 1;
13165let BaseOpcode = "L4_loadrub_abs";
13166let CextOpcode = "L2_loadrub";
13167let DecoderNamespace = "MustExtend";
13168let isExtendable = 1;
13169let opExtendable = 2;
13170let isExtentSigned = 0;
13171let opExtentBits = 6;
13172let opExtentAlign = 0;
13173}
13174def L4_ploadrubf_rr : HInst<
13175(outs IntRegs:$Rd32),
13176(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13177"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13178tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13179let Inst{31-21} = 0b00110001001;
13180let isPredicated = 1;
13181let isPredicatedFalse = 1;
13182let hasNewValue = 1;
13183let opNewValue = 0;
13184let addrMode = BaseRegOffset;
13185let accessSize = ByteAccess;
13186let mayLoad = 1;
13187let BaseOpcode = "L4_loadrub_rr";
13188let CextOpcode = "L2_loadrub";
13189let InputType = "reg";
13190}
13191def L4_ploadrubfnew_abs : HInst<
13192(outs IntRegs:$Rd32),
13193(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13194"if (!$Pt4.new) $Rd32 = memub(#$Ii)",
13195tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13196let Inst{7-5} = 0b100;
13197let Inst{13-11} = 0b111;
13198let Inst{31-21} = 0b10011111001;
13199let isPredicated = 1;
13200let isPredicatedFalse = 1;
13201let hasNewValue = 1;
13202let opNewValue = 0;
13203let addrMode = Absolute;
13204let accessSize = ByteAccess;
13205let isPredicatedNew = 1;
13206let mayLoad = 1;
13207let isExtended = 1;
13208let BaseOpcode = "L4_loadrub_abs";
13209let CextOpcode = "L2_loadrub";
13210let DecoderNamespace = "MustExtend";
13211let isExtendable = 1;
13212let opExtendable = 2;
13213let isExtentSigned = 0;
13214let opExtentBits = 6;
13215let opExtentAlign = 0;
13216}
13217def L4_ploadrubfnew_rr : HInst<
13218(outs IntRegs:$Rd32),
13219(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13220"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13221tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13222let Inst{31-21} = 0b00110011001;
13223let isPredicated = 1;
13224let isPredicatedFalse = 1;
13225let hasNewValue = 1;
13226let opNewValue = 0;
13227let addrMode = BaseRegOffset;
13228let accessSize = ByteAccess;
13229let isPredicatedNew = 1;
13230let mayLoad = 1;
13231let BaseOpcode = "L4_loadrub_rr";
13232let CextOpcode = "L2_loadrub";
13233let InputType = "reg";
13234}
13235def L4_ploadrubt_abs : HInst<
13236(outs IntRegs:$Rd32),
13237(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13238"if ($Pt4) $Rd32 = memub(#$Ii)",
13239tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13240let Inst{7-5} = 0b100;
13241let Inst{13-11} = 0b100;
13242let Inst{31-21} = 0b10011111001;
13243let isPredicated = 1;
13244let hasNewValue = 1;
13245let opNewValue = 0;
13246let addrMode = Absolute;
13247let accessSize = ByteAccess;
13248let mayLoad = 1;
13249let isExtended = 1;
13250let BaseOpcode = "L4_loadrub_abs";
13251let CextOpcode = "L2_loadrub";
13252let DecoderNamespace = "MustExtend";
13253let isExtendable = 1;
13254let opExtendable = 2;
13255let isExtentSigned = 0;
13256let opExtentBits = 6;
13257let opExtentAlign = 0;
13258}
13259def L4_ploadrubt_rr : HInst<
13260(outs IntRegs:$Rd32),
13261(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13262"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13263tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13264let Inst{31-21} = 0b00110000001;
13265let isPredicated = 1;
13266let hasNewValue = 1;
13267let opNewValue = 0;
13268let addrMode = BaseRegOffset;
13269let accessSize = ByteAccess;
13270let mayLoad = 1;
13271let BaseOpcode = "L4_loadrub_rr";
13272let CextOpcode = "L2_loadrub";
13273let InputType = "reg";
13274}
13275def L4_ploadrubtnew_abs : HInst<
13276(outs IntRegs:$Rd32),
13277(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13278"if ($Pt4.new) $Rd32 = memub(#$Ii)",
13279tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13280let Inst{7-5} = 0b100;
13281let Inst{13-11} = 0b110;
13282let Inst{31-21} = 0b10011111001;
13283let isPredicated = 1;
13284let hasNewValue = 1;
13285let opNewValue = 0;
13286let addrMode = Absolute;
13287let accessSize = ByteAccess;
13288let isPredicatedNew = 1;
13289let mayLoad = 1;
13290let isExtended = 1;
13291let BaseOpcode = "L4_loadrub_abs";
13292let CextOpcode = "L2_loadrub";
13293let DecoderNamespace = "MustExtend";
13294let isExtendable = 1;
13295let opExtendable = 2;
13296let isExtentSigned = 0;
13297let opExtentBits = 6;
13298let opExtentAlign = 0;
13299}
13300def L4_ploadrubtnew_rr : HInst<
13301(outs IntRegs:$Rd32),
13302(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13303"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)",
13304tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13305let Inst{31-21} = 0b00110010001;
13306let isPredicated = 1;
13307let hasNewValue = 1;
13308let opNewValue = 0;
13309let addrMode = BaseRegOffset;
13310let accessSize = ByteAccess;
13311let isPredicatedNew = 1;
13312let mayLoad = 1;
13313let BaseOpcode = "L4_loadrub_rr";
13314let CextOpcode = "L2_loadrub";
13315let InputType = "reg";
13316}
13317def L4_ploadruhf_abs : HInst<
13318(outs IntRegs:$Rd32),
13319(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13320"if (!$Pt4) $Rd32 = memuh(#$Ii)",
13321tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13322let Inst{7-5} = 0b100;
13323let Inst{13-11} = 0b101;
13324let Inst{31-21} = 0b10011111011;
13325let isPredicated = 1;
13326let isPredicatedFalse = 1;
13327let hasNewValue = 1;
13328let opNewValue = 0;
13329let addrMode = Absolute;
13330let accessSize = HalfWordAccess;
13331let mayLoad = 1;
13332let isExtended = 1;
13333let BaseOpcode = "L4_loadruh_abs";
13334let CextOpcode = "L2_loadruh";
13335let DecoderNamespace = "MustExtend";
13336let isExtendable = 1;
13337let opExtendable = 2;
13338let isExtentSigned = 0;
13339let opExtentBits = 6;
13340let opExtentAlign = 0;
13341}
13342def L4_ploadruhf_rr : HInst<
13343(outs IntRegs:$Rd32),
13344(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13345"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13346tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13347let Inst{31-21} = 0b00110001011;
13348let isPredicated = 1;
13349let isPredicatedFalse = 1;
13350let hasNewValue = 1;
13351let opNewValue = 0;
13352let addrMode = BaseRegOffset;
13353let accessSize = HalfWordAccess;
13354let mayLoad = 1;
13355let BaseOpcode = "L4_loadruh_rr";
13356let CextOpcode = "L2_loadruh";
13357let InputType = "reg";
13358}
13359def L4_ploadruhfnew_abs : HInst<
13360(outs IntRegs:$Rd32),
13361(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13362"if (!$Pt4.new) $Rd32 = memuh(#$Ii)",
13363tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13364let Inst{7-5} = 0b100;
13365let Inst{13-11} = 0b111;
13366let Inst{31-21} = 0b10011111011;
13367let isPredicated = 1;
13368let isPredicatedFalse = 1;
13369let hasNewValue = 1;
13370let opNewValue = 0;
13371let addrMode = Absolute;
13372let accessSize = HalfWordAccess;
13373let isPredicatedNew = 1;
13374let mayLoad = 1;
13375let isExtended = 1;
13376let BaseOpcode = "L4_loadruh_abs";
13377let CextOpcode = "L2_loadruh";
13378let DecoderNamespace = "MustExtend";
13379let isExtendable = 1;
13380let opExtendable = 2;
13381let isExtentSigned = 0;
13382let opExtentBits = 6;
13383let opExtentAlign = 0;
13384}
13385def L4_ploadruhfnew_rr : HInst<
13386(outs IntRegs:$Rd32),
13387(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13388"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13389tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13390let Inst{31-21} = 0b00110011011;
13391let isPredicated = 1;
13392let isPredicatedFalse = 1;
13393let hasNewValue = 1;
13394let opNewValue = 0;
13395let addrMode = BaseRegOffset;
13396let accessSize = HalfWordAccess;
13397let isPredicatedNew = 1;
13398let mayLoad = 1;
13399let BaseOpcode = "L4_loadruh_rr";
13400let CextOpcode = "L2_loadruh";
13401let InputType = "reg";
13402}
13403def L4_ploadruht_abs : HInst<
13404(outs IntRegs:$Rd32),
13405(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13406"if ($Pt4) $Rd32 = memuh(#$Ii)",
13407tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel {
13408let Inst{7-5} = 0b100;
13409let Inst{13-11} = 0b100;
13410let Inst{31-21} = 0b10011111011;
13411let isPredicated = 1;
13412let hasNewValue = 1;
13413let opNewValue = 0;
13414let addrMode = Absolute;
13415let accessSize = HalfWordAccess;
13416let mayLoad = 1;
13417let isExtended = 1;
13418let BaseOpcode = "L4_loadruh_abs";
13419let CextOpcode = "L2_loadruh";
13420let DecoderNamespace = "MustExtend";
13421let isExtendable = 1;
13422let opExtendable = 2;
13423let isExtentSigned = 0;
13424let opExtentBits = 6;
13425let opExtentAlign = 0;
13426}
13427def L4_ploadruht_rr : HInst<
13428(outs IntRegs:$Rd32),
13429(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13430"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13431tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel {
13432let Inst{31-21} = 0b00110000011;
13433let isPredicated = 1;
13434let hasNewValue = 1;
13435let opNewValue = 0;
13436let addrMode = BaseRegOffset;
13437let accessSize = HalfWordAccess;
13438let mayLoad = 1;
13439let BaseOpcode = "L4_loadruh_rr";
13440let CextOpcode = "L2_loadruh";
13441let InputType = "reg";
13442}
13443def L4_ploadruhtnew_abs : HInst<
13444(outs IntRegs:$Rd32),
13445(ins PredRegs:$Pt4, u32_0Imm:$Ii),
13446"if ($Pt4.new) $Rd32 = memuh(#$Ii)",
13447tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel {
13448let Inst{7-5} = 0b100;
13449let Inst{13-11} = 0b110;
13450let Inst{31-21} = 0b10011111011;
13451let isPredicated = 1;
13452let hasNewValue = 1;
13453let opNewValue = 0;
13454let addrMode = Absolute;
13455let accessSize = HalfWordAccess;
13456let isPredicatedNew = 1;
13457let mayLoad = 1;
13458let isExtended = 1;
13459let BaseOpcode = "L4_loadruh_abs";
13460let CextOpcode = "L2_loadruh";
13461let DecoderNamespace = "MustExtend";
13462let isExtendable = 1;
13463let opExtendable = 2;
13464let isExtentSigned = 0;
13465let opExtentBits = 6;
13466let opExtentAlign = 0;
13467}
13468def L4_ploadruhtnew_rr : HInst<
13469(outs IntRegs:$Rd32),
13470(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii),
13471"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)",
13472tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel {
13473let Inst{31-21} = 0b00110010011;
13474let isPredicated = 1;
13475let hasNewValue = 1;
13476let opNewValue = 0;
13477let addrMode = BaseRegOffset;
13478let accessSize = HalfWordAccess;
13479let isPredicatedNew = 1;
13480let mayLoad = 1;
13481let BaseOpcode = "L4_loadruh_rr";
13482let CextOpcode = "L2_loadruh";
13483let InputType = "reg";
13484}
13485def L4_return : HInst<
13486(outs DoubleRegs:$Rdd32),
13487(ins IntRegs:$Rs32),
13488"$Rdd32 = dealloc_return($Rs32):raw",
13489tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel {
13490let Inst{13-5} = 0b000000000;
13491let Inst{31-21} = 0b10010110000;
13492let isTerminator = 1;
13493let isIndirectBranch = 1;
13494let accessSize = DoubleWordAccess;
13495let mayLoad = 1;
13496let cofMax1 = 1;
13497let isRestrictNoSlot1Store = 1;
13498let isReturn = 1;
13499let Uses = [FRAMEKEY];
13500let Defs = [PC, R29];
13501let BaseOpcode = "L4_return";
13502let isBarrier = 1;
13503let isPredicable = 1;
13504let isTaken = 1;
13505}
13506def L4_return_f : HInst<
13507(outs DoubleRegs:$Rdd32),
13508(ins PredRegs:$Pv4, IntRegs:$Rs32),
13509"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13510tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13511let Inst{7-5} = 0b000;
13512let Inst{13-10} = 0b1100;
13513let Inst{31-21} = 0b10010110000;
13514let isPredicated = 1;
13515let isPredicatedFalse = 1;
13516let isTerminator = 1;
13517let isIndirectBranch = 1;
13518let accessSize = DoubleWordAccess;
13519let mayLoad = 1;
13520let cofMax1 = 1;
13521let isRestrictNoSlot1Store = 1;
13522let isReturn = 1;
13523let Uses = [FRAMEKEY];
13524let Defs = [PC, R29];
13525let BaseOpcode = "L4_return";
13526let isTaken = Inst{12};
13527}
13528def L4_return_fnew_pnt : HInst<
13529(outs DoubleRegs:$Rdd32),
13530(ins PredRegs:$Pv4, IntRegs:$Rs32),
13531"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13532tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13533let Inst{7-5} = 0b000;
13534let Inst{13-10} = 0b1010;
13535let Inst{31-21} = 0b10010110000;
13536let isPredicated = 1;
13537let isPredicatedFalse = 1;
13538let isTerminator = 1;
13539let isIndirectBranch = 1;
13540let accessSize = DoubleWordAccess;
13541let isPredicatedNew = 1;
13542let mayLoad = 1;
13543let cofMax1 = 1;
13544let isRestrictNoSlot1Store = 1;
13545let isReturn = 1;
13546let Uses = [FRAMEKEY];
13547let Defs = [PC, R29];
13548let BaseOpcode = "L4_return";
13549let isTaken = Inst{12};
13550}
13551def L4_return_fnew_pt : HInst<
13552(outs DoubleRegs:$Rdd32),
13553(ins PredRegs:$Pv4, IntRegs:$Rs32),
13554"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13555tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13556let Inst{7-5} = 0b000;
13557let Inst{13-10} = 0b1110;
13558let Inst{31-21} = 0b10010110000;
13559let isPredicated = 1;
13560let isPredicatedFalse = 1;
13561let isTerminator = 1;
13562let isIndirectBranch = 1;
13563let accessSize = DoubleWordAccess;
13564let isPredicatedNew = 1;
13565let mayLoad = 1;
13566let cofMax1 = 1;
13567let isRestrictNoSlot1Store = 1;
13568let isReturn = 1;
13569let Uses = [FRAMEKEY];
13570let Defs = [PC, R29];
13571let BaseOpcode = "L4_return";
13572let isTaken = Inst{12};
13573}
13574def L4_return_map_to_raw_f : HInst<
13575(outs),
13576(ins PredRegs:$Pv4),
13577"if (!$Pv4) dealloc_return",
13578tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> {
13579let isPseudo = 1;
13580let isCodeGenOnly = 1;
13581}
13582def L4_return_map_to_raw_fnew_pnt : HInst<
13583(outs),
13584(ins PredRegs:$Pv4),
13585"if (!$Pv4.new) dealloc_return:nt",
13586tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13587let isPseudo = 1;
13588let isCodeGenOnly = 1;
13589}
13590def L4_return_map_to_raw_fnew_pt : HInst<
13591(outs),
13592(ins PredRegs:$Pv4),
13593"if (!$Pv4.new) dealloc_return:t",
13594tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> {
13595let isPseudo = 1;
13596let isCodeGenOnly = 1;
13597}
13598def L4_return_map_to_raw_t : HInst<
13599(outs),
13600(ins PredRegs:$Pv4),
13601"if ($Pv4) dealloc_return",
13602tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> {
13603let isPseudo = 1;
13604let isCodeGenOnly = 1;
13605}
13606def L4_return_map_to_raw_tnew_pnt : HInst<
13607(outs),
13608(ins PredRegs:$Pv4),
13609"if ($Pv4.new) dealloc_return:nt",
13610tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13611let isPseudo = 1;
13612let isCodeGenOnly = 1;
13613}
13614def L4_return_map_to_raw_tnew_pt : HInst<
13615(outs),
13616(ins PredRegs:$Pv4),
13617"if ($Pv4.new) dealloc_return:t",
13618tc_1981450d, TypeMAPPING>, Requires<[HasV65]> {
13619let isPseudo = 1;
13620let isCodeGenOnly = 1;
13621}
13622def L4_return_t : HInst<
13623(outs DoubleRegs:$Rdd32),
13624(ins PredRegs:$Pv4, IntRegs:$Rs32),
13625"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw",
13626tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel {
13627let Inst{7-5} = 0b000;
13628let Inst{13-10} = 0b0100;
13629let Inst{31-21} = 0b10010110000;
13630let isPredicated = 1;
13631let isTerminator = 1;
13632let isIndirectBranch = 1;
13633let accessSize = DoubleWordAccess;
13634let mayLoad = 1;
13635let cofMax1 = 1;
13636let isRestrictNoSlot1Store = 1;
13637let isReturn = 1;
13638let Uses = [FRAMEKEY];
13639let Defs = [PC, R29];
13640let BaseOpcode = "L4_return";
13641let isTaken = Inst{12};
13642}
13643def L4_return_tnew_pnt : HInst<
13644(outs DoubleRegs:$Rdd32),
13645(ins PredRegs:$Pv4, IntRegs:$Rs32),
13646"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw",
13647tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13648let Inst{7-5} = 0b000;
13649let Inst{13-10} = 0b0010;
13650let Inst{31-21} = 0b10010110000;
13651let isPredicated = 1;
13652let isTerminator = 1;
13653let isIndirectBranch = 1;
13654let accessSize = DoubleWordAccess;
13655let isPredicatedNew = 1;
13656let mayLoad = 1;
13657let cofMax1 = 1;
13658let isRestrictNoSlot1Store = 1;
13659let isReturn = 1;
13660let Uses = [FRAMEKEY];
13661let Defs = [PC, R29];
13662let BaseOpcode = "L4_return";
13663let isTaken = Inst{12};
13664}
13665def L4_return_tnew_pt : HInst<
13666(outs DoubleRegs:$Rdd32),
13667(ins PredRegs:$Pv4, IntRegs:$Rs32),
13668"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw",
13669tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel {
13670let Inst{7-5} = 0b000;
13671let Inst{13-10} = 0b0110;
13672let Inst{31-21} = 0b10010110000;
13673let isPredicated = 1;
13674let isTerminator = 1;
13675let isIndirectBranch = 1;
13676let accessSize = DoubleWordAccess;
13677let isPredicatedNew = 1;
13678let mayLoad = 1;
13679let cofMax1 = 1;
13680let isRestrictNoSlot1Store = 1;
13681let isReturn = 1;
13682let Uses = [FRAMEKEY];
13683let Defs = [PC, R29];
13684let BaseOpcode = "L4_return";
13685let isTaken = Inst{12};
13686}
13687def L4_sub_memopb_io : HInst<
13688(outs),
13689(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
13690"memb($Rs32+#$Ii) -= $Rt32",
13691tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 {
13692let Inst{6-5} = 0b01;
13693let Inst{13-13} = 0b0;
13694let Inst{31-21} = 0b00111110000;
13695let addrMode = BaseImmOffset;
13696let accessSize = ByteAccess;
13697let mayLoad = 1;
13698let isRestrictNoSlot1Store = 1;
13699let mayStore = 1;
13700let isExtendable = 1;
13701let opExtendable = 1;
13702let isExtentSigned = 0;
13703let opExtentBits = 6;
13704let opExtentAlign = 0;
13705}
13706def L4_sub_memopb_zomap : HInst<
13707(outs),
13708(ins IntRegs:$Rs32, IntRegs:$Rt32),
13709"memb($Rs32) -= $Rt32",
13710tc_9bcfb2ee, TypeMAPPING> {
13711let isPseudo = 1;
13712let isCodeGenOnly = 1;
13713}
13714def L4_sub_memoph_io : HInst<
13715(outs),
13716(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
13717"memh($Rs32+#$Ii) -= $Rt32",
13718tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c {
13719let Inst{6-5} = 0b01;
13720let Inst{13-13} = 0b0;
13721let Inst{31-21} = 0b00111110001;
13722let addrMode = BaseImmOffset;
13723let accessSize = HalfWordAccess;
13724let mayLoad = 1;
13725let isRestrictNoSlot1Store = 1;
13726let mayStore = 1;
13727let isExtendable = 1;
13728let opExtendable = 1;
13729let isExtentSigned = 0;
13730let opExtentBits = 7;
13731let opExtentAlign = 1;
13732}
13733def L4_sub_memoph_zomap : HInst<
13734(outs),
13735(ins IntRegs:$Rs32, IntRegs:$Rt32),
13736"memh($Rs32) -= $Rt32",
13737tc_9bcfb2ee, TypeMAPPING> {
13738let isPseudo = 1;
13739let isCodeGenOnly = 1;
13740}
13741def L4_sub_memopw_io : HInst<
13742(outs),
13743(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
13744"memw($Rs32+#$Ii) -= $Rt32",
13745tc_9bcfb2ee, TypeV4LDST>, Enc_226535 {
13746let Inst{6-5} = 0b01;
13747let Inst{13-13} = 0b0;
13748let Inst{31-21} = 0b00111110010;
13749let addrMode = BaseImmOffset;
13750let accessSize = WordAccess;
13751let mayLoad = 1;
13752let isRestrictNoSlot1Store = 1;
13753let mayStore = 1;
13754let isExtendable = 1;
13755let opExtendable = 1;
13756let isExtentSigned = 0;
13757let opExtentBits = 8;
13758let opExtentAlign = 2;
13759}
13760def L4_sub_memopw_zomap : HInst<
13761(outs),
13762(ins IntRegs:$Rs32, IntRegs:$Rt32),
13763"memw($Rs32) -= $Rt32",
13764tc_9bcfb2ee, TypeMAPPING> {
13765let isPseudo = 1;
13766let isCodeGenOnly = 1;
13767}
13768def L6_deallocframe_map_to_raw : HInst<
13769(outs),
13770(ins),
13771"deallocframe",
13772tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> {
13773let isPseudo = 1;
13774let isCodeGenOnly = 1;
13775}
13776def L6_memcpy : HInst<
13777(outs),
13778(ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2),
13779"memcpy($Rs32,$Rt32,$Mu2)",
13780tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> {
13781let Inst{7-0} = 0b01000000;
13782let Inst{31-21} = 0b10010010000;
13783let mayLoad = 1;
13784let isSolo = 1;
13785let mayStore = 1;
13786}
13787def L6_return_map_to_raw : HInst<
13788(outs),
13789(ins),
13790"dealloc_return",
13791tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> {
13792let isPseudo = 1;
13793let isCodeGenOnly = 1;
13794}
13795def M2_acci : HInst<
13796(outs IntRegs:$Rx32),
13797(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13798"$Rx32 += add($Rs32,$Rt32)",
13799tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel {
13800let Inst{7-5} = 0b001;
13801let Inst{13-13} = 0b0;
13802let Inst{31-21} = 0b11101111000;
13803let hasNewValue = 1;
13804let opNewValue = 0;
13805let prefersSlot3 = 1;
13806let CextOpcode = "M2_acci";
13807let InputType = "reg";
13808let Constraints = "$Rx32 = $Rx32in";
13809}
13810def M2_accii : HInst<
13811(outs IntRegs:$Rx32),
13812(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
13813"$Rx32 += add($Rs32,#$Ii)",
13814tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel {
13815let Inst{13-13} = 0b0;
13816let Inst{31-21} = 0b11100010000;
13817let hasNewValue = 1;
13818let opNewValue = 0;
13819let prefersSlot3 = 1;
13820let CextOpcode = "M2_acci";
13821let InputType = "imm";
13822let isExtendable = 1;
13823let opExtendable = 3;
13824let isExtentSigned = 1;
13825let opExtentBits = 8;
13826let opExtentAlign = 0;
13827let Constraints = "$Rx32 = $Rx32in";
13828}
13829def M2_cmaci_s0 : HInst<
13830(outs DoubleRegs:$Rxx32),
13831(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13832"$Rxx32 += cmpyi($Rs32,$Rt32)",
13833tc_7f8ae742, TypeM>, Enc_61f0b0 {
13834let Inst{7-5} = 0b001;
13835let Inst{13-13} = 0b0;
13836let Inst{31-21} = 0b11100111000;
13837let prefersSlot3 = 1;
13838let Constraints = "$Rxx32 = $Rxx32in";
13839}
13840def M2_cmacr_s0 : HInst<
13841(outs DoubleRegs:$Rxx32),
13842(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13843"$Rxx32 += cmpyr($Rs32,$Rt32)",
13844tc_7f8ae742, TypeM>, Enc_61f0b0 {
13845let Inst{7-5} = 0b010;
13846let Inst{13-13} = 0b0;
13847let Inst{31-21} = 0b11100111000;
13848let prefersSlot3 = 1;
13849let Constraints = "$Rxx32 = $Rxx32in";
13850}
13851def M2_cmacs_s0 : HInst<
13852(outs DoubleRegs:$Rxx32),
13853(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13854"$Rxx32 += cmpy($Rs32,$Rt32):sat",
13855tc_7f8ae742, TypeM>, Enc_61f0b0 {
13856let Inst{7-5} = 0b110;
13857let Inst{13-13} = 0b0;
13858let Inst{31-21} = 0b11100111000;
13859let prefersSlot3 = 1;
13860let Defs = [USR_OVF];
13861let Constraints = "$Rxx32 = $Rxx32in";
13862}
13863def M2_cmacs_s1 : HInst<
13864(outs DoubleRegs:$Rxx32),
13865(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13866"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat",
13867tc_7f8ae742, TypeM>, Enc_61f0b0 {
13868let Inst{7-5} = 0b110;
13869let Inst{13-13} = 0b0;
13870let Inst{31-21} = 0b11100111100;
13871let prefersSlot3 = 1;
13872let Defs = [USR_OVF];
13873let Constraints = "$Rxx32 = $Rxx32in";
13874}
13875def M2_cmacsc_s0 : HInst<
13876(outs DoubleRegs:$Rxx32),
13877(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13878"$Rxx32 += cmpy($Rs32,$Rt32*):sat",
13879tc_7f8ae742, TypeM>, Enc_61f0b0 {
13880let Inst{7-5} = 0b110;
13881let Inst{13-13} = 0b0;
13882let Inst{31-21} = 0b11100111010;
13883let prefersSlot3 = 1;
13884let Defs = [USR_OVF];
13885let Constraints = "$Rxx32 = $Rxx32in";
13886}
13887def M2_cmacsc_s1 : HInst<
13888(outs DoubleRegs:$Rxx32),
13889(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
13890"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat",
13891tc_7f8ae742, TypeM>, Enc_61f0b0 {
13892let Inst{7-5} = 0b110;
13893let Inst{13-13} = 0b0;
13894let Inst{31-21} = 0b11100111110;
13895let prefersSlot3 = 1;
13896let Defs = [USR_OVF];
13897let Constraints = "$Rxx32 = $Rxx32in";
13898}
13899def M2_cmpyi_s0 : HInst<
13900(outs DoubleRegs:$Rdd32),
13901(ins IntRegs:$Rs32, IntRegs:$Rt32),
13902"$Rdd32 = cmpyi($Rs32,$Rt32)",
13903tc_c21d7447, TypeM>, Enc_be32a5 {
13904let Inst{7-5} = 0b001;
13905let Inst{13-13} = 0b0;
13906let Inst{31-21} = 0b11100101000;
13907let prefersSlot3 = 1;
13908}
13909def M2_cmpyr_s0 : HInst<
13910(outs DoubleRegs:$Rdd32),
13911(ins IntRegs:$Rs32, IntRegs:$Rt32),
13912"$Rdd32 = cmpyr($Rs32,$Rt32)",
13913tc_c21d7447, TypeM>, Enc_be32a5 {
13914let Inst{7-5} = 0b010;
13915let Inst{13-13} = 0b0;
13916let Inst{31-21} = 0b11100101000;
13917let prefersSlot3 = 1;
13918}
13919def M2_cmpyrs_s0 : HInst<
13920(outs IntRegs:$Rd32),
13921(ins IntRegs:$Rs32, IntRegs:$Rt32),
13922"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat",
13923tc_c21d7447, TypeM>, Enc_5ab2be {
13924let Inst{7-5} = 0b110;
13925let Inst{13-13} = 0b0;
13926let Inst{31-21} = 0b11101101001;
13927let hasNewValue = 1;
13928let opNewValue = 0;
13929let prefersSlot3 = 1;
13930let Defs = [USR_OVF];
13931}
13932def M2_cmpyrs_s1 : HInst<
13933(outs IntRegs:$Rd32),
13934(ins IntRegs:$Rs32, IntRegs:$Rt32),
13935"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat",
13936tc_c21d7447, TypeM>, Enc_5ab2be {
13937let Inst{7-5} = 0b110;
13938let Inst{13-13} = 0b0;
13939let Inst{31-21} = 0b11101101101;
13940let hasNewValue = 1;
13941let opNewValue = 0;
13942let prefersSlot3 = 1;
13943let Defs = [USR_OVF];
13944}
13945def M2_cmpyrsc_s0 : HInst<
13946(outs IntRegs:$Rd32),
13947(ins IntRegs:$Rs32, IntRegs:$Rt32),
13948"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat",
13949tc_c21d7447, TypeM>, Enc_5ab2be {
13950let Inst{7-5} = 0b110;
13951let Inst{13-13} = 0b0;
13952let Inst{31-21} = 0b11101101011;
13953let hasNewValue = 1;
13954let opNewValue = 0;
13955let prefersSlot3 = 1;
13956let Defs = [USR_OVF];
13957}
13958def M2_cmpyrsc_s1 : HInst<
13959(outs IntRegs:$Rd32),
13960(ins IntRegs:$Rs32, IntRegs:$Rt32),
13961"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat",
13962tc_c21d7447, TypeM>, Enc_5ab2be {
13963let Inst{7-5} = 0b110;
13964let Inst{13-13} = 0b0;
13965let Inst{31-21} = 0b11101101111;
13966let hasNewValue = 1;
13967let opNewValue = 0;
13968let prefersSlot3 = 1;
13969let Defs = [USR_OVF];
13970}
13971def M2_cmpys_s0 : HInst<
13972(outs DoubleRegs:$Rdd32),
13973(ins IntRegs:$Rs32, IntRegs:$Rt32),
13974"$Rdd32 = cmpy($Rs32,$Rt32):sat",
13975tc_c21d7447, TypeM>, Enc_be32a5 {
13976let Inst{7-5} = 0b110;
13977let Inst{13-13} = 0b0;
13978let Inst{31-21} = 0b11100101000;
13979let prefersSlot3 = 1;
13980let Defs = [USR_OVF];
13981}
13982def M2_cmpys_s1 : HInst<
13983(outs DoubleRegs:$Rdd32),
13984(ins IntRegs:$Rs32, IntRegs:$Rt32),
13985"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat",
13986tc_c21d7447, TypeM>, Enc_be32a5 {
13987let Inst{7-5} = 0b110;
13988let Inst{13-13} = 0b0;
13989let Inst{31-21} = 0b11100101100;
13990let prefersSlot3 = 1;
13991let Defs = [USR_OVF];
13992}
13993def M2_cmpysc_s0 : HInst<
13994(outs DoubleRegs:$Rdd32),
13995(ins IntRegs:$Rs32, IntRegs:$Rt32),
13996"$Rdd32 = cmpy($Rs32,$Rt32*):sat",
13997tc_c21d7447, TypeM>, Enc_be32a5 {
13998let Inst{7-5} = 0b110;
13999let Inst{13-13} = 0b0;
14000let Inst{31-21} = 0b11100101010;
14001let prefersSlot3 = 1;
14002let Defs = [USR_OVF];
14003}
14004def M2_cmpysc_s1 : HInst<
14005(outs DoubleRegs:$Rdd32),
14006(ins IntRegs:$Rs32, IntRegs:$Rt32),
14007"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat",
14008tc_c21d7447, TypeM>, Enc_be32a5 {
14009let Inst{7-5} = 0b110;
14010let Inst{13-13} = 0b0;
14011let Inst{31-21} = 0b11100101110;
14012let prefersSlot3 = 1;
14013let Defs = [USR_OVF];
14014}
14015def M2_cnacs_s0 : HInst<
14016(outs DoubleRegs:$Rxx32),
14017(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14018"$Rxx32 -= cmpy($Rs32,$Rt32):sat",
14019tc_7f8ae742, TypeM>, Enc_61f0b0 {
14020let Inst{7-5} = 0b111;
14021let Inst{13-13} = 0b0;
14022let Inst{31-21} = 0b11100111000;
14023let prefersSlot3 = 1;
14024let Defs = [USR_OVF];
14025let Constraints = "$Rxx32 = $Rxx32in";
14026}
14027def M2_cnacs_s1 : HInst<
14028(outs DoubleRegs:$Rxx32),
14029(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14030"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat",
14031tc_7f8ae742, TypeM>, Enc_61f0b0 {
14032let Inst{7-5} = 0b111;
14033let Inst{13-13} = 0b0;
14034let Inst{31-21} = 0b11100111100;
14035let prefersSlot3 = 1;
14036let Defs = [USR_OVF];
14037let Constraints = "$Rxx32 = $Rxx32in";
14038}
14039def M2_cnacsc_s0 : HInst<
14040(outs DoubleRegs:$Rxx32),
14041(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14042"$Rxx32 -= cmpy($Rs32,$Rt32*):sat",
14043tc_7f8ae742, TypeM>, Enc_61f0b0 {
14044let Inst{7-5} = 0b111;
14045let Inst{13-13} = 0b0;
14046let Inst{31-21} = 0b11100111010;
14047let prefersSlot3 = 1;
14048let Defs = [USR_OVF];
14049let Constraints = "$Rxx32 = $Rxx32in";
14050}
14051def M2_cnacsc_s1 : HInst<
14052(outs DoubleRegs:$Rxx32),
14053(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14054"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat",
14055tc_7f8ae742, TypeM>, Enc_61f0b0 {
14056let Inst{7-5} = 0b111;
14057let Inst{13-13} = 0b0;
14058let Inst{31-21} = 0b11100111110;
14059let prefersSlot3 = 1;
14060let Defs = [USR_OVF];
14061let Constraints = "$Rxx32 = $Rxx32in";
14062}
14063def M2_dpmpyss_acc_s0 : HInst<
14064(outs DoubleRegs:$Rxx32),
14065(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14066"$Rxx32 += mpy($Rs32,$Rt32)",
14067tc_7f8ae742, TypeM>, Enc_61f0b0 {
14068let Inst{7-5} = 0b000;
14069let Inst{13-13} = 0b0;
14070let Inst{31-21} = 0b11100111000;
14071let prefersSlot3 = 1;
14072let Constraints = "$Rxx32 = $Rxx32in";
14073}
14074def M2_dpmpyss_nac_s0 : HInst<
14075(outs DoubleRegs:$Rxx32),
14076(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14077"$Rxx32 -= mpy($Rs32,$Rt32)",
14078tc_7f8ae742, TypeM>, Enc_61f0b0 {
14079let Inst{7-5} = 0b000;
14080let Inst{13-13} = 0b0;
14081let Inst{31-21} = 0b11100111001;
14082let prefersSlot3 = 1;
14083let Constraints = "$Rxx32 = $Rxx32in";
14084}
14085def M2_dpmpyss_rnd_s0 : HInst<
14086(outs IntRegs:$Rd32),
14087(ins IntRegs:$Rs32, IntRegs:$Rt32),
14088"$Rd32 = mpy($Rs32,$Rt32):rnd",
14089tc_c21d7447, TypeM>, Enc_5ab2be {
14090let Inst{7-5} = 0b001;
14091let Inst{13-13} = 0b0;
14092let Inst{31-21} = 0b11101101001;
14093let hasNewValue = 1;
14094let opNewValue = 0;
14095let prefersSlot3 = 1;
14096}
14097def M2_dpmpyss_s0 : HInst<
14098(outs DoubleRegs:$Rdd32),
14099(ins IntRegs:$Rs32, IntRegs:$Rt32),
14100"$Rdd32 = mpy($Rs32,$Rt32)",
14101tc_c21d7447, TypeM>, Enc_be32a5 {
14102let Inst{7-5} = 0b000;
14103let Inst{13-13} = 0b0;
14104let Inst{31-21} = 0b11100101000;
14105let prefersSlot3 = 1;
14106}
14107def M2_dpmpyuu_acc_s0 : HInst<
14108(outs DoubleRegs:$Rxx32),
14109(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14110"$Rxx32 += mpyu($Rs32,$Rt32)",
14111tc_7f8ae742, TypeM>, Enc_61f0b0 {
14112let Inst{7-5} = 0b000;
14113let Inst{13-13} = 0b0;
14114let Inst{31-21} = 0b11100111010;
14115let prefersSlot3 = 1;
14116let Constraints = "$Rxx32 = $Rxx32in";
14117}
14118def M2_dpmpyuu_nac_s0 : HInst<
14119(outs DoubleRegs:$Rxx32),
14120(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14121"$Rxx32 -= mpyu($Rs32,$Rt32)",
14122tc_7f8ae742, TypeM>, Enc_61f0b0 {
14123let Inst{7-5} = 0b000;
14124let Inst{13-13} = 0b0;
14125let Inst{31-21} = 0b11100111011;
14126let prefersSlot3 = 1;
14127let Constraints = "$Rxx32 = $Rxx32in";
14128}
14129def M2_dpmpyuu_s0 : HInst<
14130(outs DoubleRegs:$Rdd32),
14131(ins IntRegs:$Rs32, IntRegs:$Rt32),
14132"$Rdd32 = mpyu($Rs32,$Rt32)",
14133tc_c21d7447, TypeM>, Enc_be32a5 {
14134let Inst{7-5} = 0b000;
14135let Inst{13-13} = 0b0;
14136let Inst{31-21} = 0b11100101010;
14137let prefersSlot3 = 1;
14138}
14139def M2_hmmpyh_rs1 : HInst<
14140(outs IntRegs:$Rd32),
14141(ins IntRegs:$Rs32, IntRegs:$Rt32),
14142"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat",
14143tc_c21d7447, TypeM>, Enc_5ab2be {
14144let Inst{7-5} = 0b100;
14145let Inst{13-13} = 0b0;
14146let Inst{31-21} = 0b11101101101;
14147let hasNewValue = 1;
14148let opNewValue = 0;
14149let prefersSlot3 = 1;
14150let Defs = [USR_OVF];
14151}
14152def M2_hmmpyh_s1 : HInst<
14153(outs IntRegs:$Rd32),
14154(ins IntRegs:$Rs32, IntRegs:$Rt32),
14155"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat",
14156tc_c21d7447, TypeM>, Enc_5ab2be {
14157let Inst{7-5} = 0b000;
14158let Inst{13-13} = 0b0;
14159let Inst{31-21} = 0b11101101101;
14160let hasNewValue = 1;
14161let opNewValue = 0;
14162let prefersSlot3 = 1;
14163let Defs = [USR_OVF];
14164}
14165def M2_hmmpyl_rs1 : HInst<
14166(outs IntRegs:$Rd32),
14167(ins IntRegs:$Rs32, IntRegs:$Rt32),
14168"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat",
14169tc_c21d7447, TypeM>, Enc_5ab2be {
14170let Inst{7-5} = 0b100;
14171let Inst{13-13} = 0b0;
14172let Inst{31-21} = 0b11101101111;
14173let hasNewValue = 1;
14174let opNewValue = 0;
14175let prefersSlot3 = 1;
14176let Defs = [USR_OVF];
14177}
14178def M2_hmmpyl_s1 : HInst<
14179(outs IntRegs:$Rd32),
14180(ins IntRegs:$Rs32, IntRegs:$Rt32),
14181"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat",
14182tc_c21d7447, TypeM>, Enc_5ab2be {
14183let Inst{7-5} = 0b001;
14184let Inst{13-13} = 0b0;
14185let Inst{31-21} = 0b11101101101;
14186let hasNewValue = 1;
14187let opNewValue = 0;
14188let prefersSlot3 = 1;
14189let Defs = [USR_OVF];
14190}
14191def M2_maci : HInst<
14192(outs IntRegs:$Rx32),
14193(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14194"$Rx32 += mpyi($Rs32,$Rt32)",
14195tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel {
14196let Inst{7-5} = 0b000;
14197let Inst{13-13} = 0b0;
14198let Inst{31-21} = 0b11101111000;
14199let hasNewValue = 1;
14200let opNewValue = 0;
14201let prefersSlot3 = 1;
14202let CextOpcode = "M2_maci";
14203let InputType = "reg";
14204let Constraints = "$Rx32 = $Rx32in";
14205}
14206def M2_macsin : HInst<
14207(outs IntRegs:$Rx32),
14208(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14209"$Rx32 -= mpyi($Rs32,#$Ii)",
14210tc_a154b476, TypeM>, Enc_c90aca {
14211let Inst{13-13} = 0b0;
14212let Inst{31-21} = 0b11100001100;
14213let hasNewValue = 1;
14214let opNewValue = 0;
14215let prefersSlot3 = 1;
14216let InputType = "imm";
14217let isExtendable = 1;
14218let opExtendable = 3;
14219let isExtentSigned = 0;
14220let opExtentBits = 8;
14221let opExtentAlign = 0;
14222let Constraints = "$Rx32 = $Rx32in";
14223}
14224def M2_macsip : HInst<
14225(outs IntRegs:$Rx32),
14226(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii),
14227"$Rx32 += mpyi($Rs32,#$Ii)",
14228tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel {
14229let Inst{13-13} = 0b0;
14230let Inst{31-21} = 0b11100001000;
14231let hasNewValue = 1;
14232let opNewValue = 0;
14233let prefersSlot3 = 1;
14234let CextOpcode = "M2_maci";
14235let InputType = "imm";
14236let isExtendable = 1;
14237let opExtendable = 3;
14238let isExtentSigned = 0;
14239let opExtentBits = 8;
14240let opExtentAlign = 0;
14241let Constraints = "$Rx32 = $Rx32in";
14242}
14243def M2_mmachs_rs0 : HInst<
14244(outs DoubleRegs:$Rxx32),
14245(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14246"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat",
14247tc_7f8ae742, TypeM>, Enc_88c16c {
14248let Inst{7-5} = 0b111;
14249let Inst{13-13} = 0b0;
14250let Inst{31-21} = 0b11101010001;
14251let prefersSlot3 = 1;
14252let Defs = [USR_OVF];
14253let Constraints = "$Rxx32 = $Rxx32in";
14254}
14255def M2_mmachs_rs1 : HInst<
14256(outs DoubleRegs:$Rxx32),
14257(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14258"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14259tc_7f8ae742, TypeM>, Enc_88c16c {
14260let Inst{7-5} = 0b111;
14261let Inst{13-13} = 0b0;
14262let Inst{31-21} = 0b11101010101;
14263let prefersSlot3 = 1;
14264let Defs = [USR_OVF];
14265let Constraints = "$Rxx32 = $Rxx32in";
14266}
14267def M2_mmachs_s0 : HInst<
14268(outs DoubleRegs:$Rxx32),
14269(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14270"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat",
14271tc_7f8ae742, TypeM>, Enc_88c16c {
14272let Inst{7-5} = 0b111;
14273let Inst{13-13} = 0b0;
14274let Inst{31-21} = 0b11101010000;
14275let prefersSlot3 = 1;
14276let Defs = [USR_OVF];
14277let Constraints = "$Rxx32 = $Rxx32in";
14278}
14279def M2_mmachs_s1 : HInst<
14280(outs DoubleRegs:$Rxx32),
14281(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14282"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat",
14283tc_7f8ae742, TypeM>, Enc_88c16c {
14284let Inst{7-5} = 0b111;
14285let Inst{13-13} = 0b0;
14286let Inst{31-21} = 0b11101010100;
14287let prefersSlot3 = 1;
14288let Defs = [USR_OVF];
14289let Constraints = "$Rxx32 = $Rxx32in";
14290}
14291def M2_mmacls_rs0 : HInst<
14292(outs DoubleRegs:$Rxx32),
14293(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14294"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat",
14295tc_7f8ae742, TypeM>, Enc_88c16c {
14296let Inst{7-5} = 0b101;
14297let Inst{13-13} = 0b0;
14298let Inst{31-21} = 0b11101010001;
14299let prefersSlot3 = 1;
14300let Defs = [USR_OVF];
14301let Constraints = "$Rxx32 = $Rxx32in";
14302}
14303def M2_mmacls_rs1 : HInst<
14304(outs DoubleRegs:$Rxx32),
14305(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14306"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14307tc_7f8ae742, TypeM>, Enc_88c16c {
14308let Inst{7-5} = 0b101;
14309let Inst{13-13} = 0b0;
14310let Inst{31-21} = 0b11101010101;
14311let prefersSlot3 = 1;
14312let Defs = [USR_OVF];
14313let Constraints = "$Rxx32 = $Rxx32in";
14314}
14315def M2_mmacls_s0 : HInst<
14316(outs DoubleRegs:$Rxx32),
14317(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14318"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat",
14319tc_7f8ae742, TypeM>, Enc_88c16c {
14320let Inst{7-5} = 0b101;
14321let Inst{13-13} = 0b0;
14322let Inst{31-21} = 0b11101010000;
14323let prefersSlot3 = 1;
14324let Defs = [USR_OVF];
14325let Constraints = "$Rxx32 = $Rxx32in";
14326}
14327def M2_mmacls_s1 : HInst<
14328(outs DoubleRegs:$Rxx32),
14329(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14330"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat",
14331tc_7f8ae742, TypeM>, Enc_88c16c {
14332let Inst{7-5} = 0b101;
14333let Inst{13-13} = 0b0;
14334let Inst{31-21} = 0b11101010100;
14335let prefersSlot3 = 1;
14336let Defs = [USR_OVF];
14337let Constraints = "$Rxx32 = $Rxx32in";
14338}
14339def M2_mmacuhs_rs0 : HInst<
14340(outs DoubleRegs:$Rxx32),
14341(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14342"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat",
14343tc_7f8ae742, TypeM>, Enc_88c16c {
14344let Inst{7-5} = 0b111;
14345let Inst{13-13} = 0b0;
14346let Inst{31-21} = 0b11101010011;
14347let prefersSlot3 = 1;
14348let Defs = [USR_OVF];
14349let Constraints = "$Rxx32 = $Rxx32in";
14350}
14351def M2_mmacuhs_rs1 : HInst<
14352(outs DoubleRegs:$Rxx32),
14353(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14354"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14355tc_7f8ae742, TypeM>, Enc_88c16c {
14356let Inst{7-5} = 0b111;
14357let Inst{13-13} = 0b0;
14358let Inst{31-21} = 0b11101010111;
14359let prefersSlot3 = 1;
14360let Defs = [USR_OVF];
14361let Constraints = "$Rxx32 = $Rxx32in";
14362}
14363def M2_mmacuhs_s0 : HInst<
14364(outs DoubleRegs:$Rxx32),
14365(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14366"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat",
14367tc_7f8ae742, TypeM>, Enc_88c16c {
14368let Inst{7-5} = 0b111;
14369let Inst{13-13} = 0b0;
14370let Inst{31-21} = 0b11101010010;
14371let prefersSlot3 = 1;
14372let Defs = [USR_OVF];
14373let Constraints = "$Rxx32 = $Rxx32in";
14374}
14375def M2_mmacuhs_s1 : HInst<
14376(outs DoubleRegs:$Rxx32),
14377(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14378"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat",
14379tc_7f8ae742, TypeM>, Enc_88c16c {
14380let Inst{7-5} = 0b111;
14381let Inst{13-13} = 0b0;
14382let Inst{31-21} = 0b11101010110;
14383let prefersSlot3 = 1;
14384let Defs = [USR_OVF];
14385let Constraints = "$Rxx32 = $Rxx32in";
14386}
14387def M2_mmaculs_rs0 : HInst<
14388(outs DoubleRegs:$Rxx32),
14389(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14390"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat",
14391tc_7f8ae742, TypeM>, Enc_88c16c {
14392let Inst{7-5} = 0b101;
14393let Inst{13-13} = 0b0;
14394let Inst{31-21} = 0b11101010011;
14395let prefersSlot3 = 1;
14396let Defs = [USR_OVF];
14397let Constraints = "$Rxx32 = $Rxx32in";
14398}
14399def M2_mmaculs_rs1 : HInst<
14400(outs DoubleRegs:$Rxx32),
14401(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14402"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14403tc_7f8ae742, TypeM>, Enc_88c16c {
14404let Inst{7-5} = 0b101;
14405let Inst{13-13} = 0b0;
14406let Inst{31-21} = 0b11101010111;
14407let prefersSlot3 = 1;
14408let Defs = [USR_OVF];
14409let Constraints = "$Rxx32 = $Rxx32in";
14410}
14411def M2_mmaculs_s0 : HInst<
14412(outs DoubleRegs:$Rxx32),
14413(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14414"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat",
14415tc_7f8ae742, TypeM>, Enc_88c16c {
14416let Inst{7-5} = 0b101;
14417let Inst{13-13} = 0b0;
14418let Inst{31-21} = 0b11101010010;
14419let prefersSlot3 = 1;
14420let Defs = [USR_OVF];
14421let Constraints = "$Rxx32 = $Rxx32in";
14422}
14423def M2_mmaculs_s1 : HInst<
14424(outs DoubleRegs:$Rxx32),
14425(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14426"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat",
14427tc_7f8ae742, TypeM>, Enc_88c16c {
14428let Inst{7-5} = 0b101;
14429let Inst{13-13} = 0b0;
14430let Inst{31-21} = 0b11101010110;
14431let prefersSlot3 = 1;
14432let Defs = [USR_OVF];
14433let Constraints = "$Rxx32 = $Rxx32in";
14434}
14435def M2_mmpyh_rs0 : HInst<
14436(outs DoubleRegs:$Rdd32),
14437(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14438"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat",
14439tc_c21d7447, TypeM>, Enc_a56825 {
14440let Inst{7-5} = 0b111;
14441let Inst{13-13} = 0b0;
14442let Inst{31-21} = 0b11101000001;
14443let prefersSlot3 = 1;
14444let Defs = [USR_OVF];
14445}
14446def M2_mmpyh_rs1 : HInst<
14447(outs DoubleRegs:$Rdd32),
14448(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14449"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat",
14450tc_c21d7447, TypeM>, Enc_a56825 {
14451let Inst{7-5} = 0b111;
14452let Inst{13-13} = 0b0;
14453let Inst{31-21} = 0b11101000101;
14454let prefersSlot3 = 1;
14455let Defs = [USR_OVF];
14456}
14457def M2_mmpyh_s0 : HInst<
14458(outs DoubleRegs:$Rdd32),
14459(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14460"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat",
14461tc_c21d7447, TypeM>, Enc_a56825 {
14462let Inst{7-5} = 0b111;
14463let Inst{13-13} = 0b0;
14464let Inst{31-21} = 0b11101000000;
14465let prefersSlot3 = 1;
14466let Defs = [USR_OVF];
14467}
14468def M2_mmpyh_s1 : HInst<
14469(outs DoubleRegs:$Rdd32),
14470(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14471"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat",
14472tc_c21d7447, TypeM>, Enc_a56825 {
14473let Inst{7-5} = 0b111;
14474let Inst{13-13} = 0b0;
14475let Inst{31-21} = 0b11101000100;
14476let prefersSlot3 = 1;
14477let Defs = [USR_OVF];
14478}
14479def M2_mmpyl_rs0 : HInst<
14480(outs DoubleRegs:$Rdd32),
14481(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14482"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat",
14483tc_c21d7447, TypeM>, Enc_a56825 {
14484let Inst{7-5} = 0b101;
14485let Inst{13-13} = 0b0;
14486let Inst{31-21} = 0b11101000001;
14487let prefersSlot3 = 1;
14488let Defs = [USR_OVF];
14489}
14490def M2_mmpyl_rs1 : HInst<
14491(outs DoubleRegs:$Rdd32),
14492(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14493"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat",
14494tc_c21d7447, TypeM>, Enc_a56825 {
14495let Inst{7-5} = 0b101;
14496let Inst{13-13} = 0b0;
14497let Inst{31-21} = 0b11101000101;
14498let prefersSlot3 = 1;
14499let Defs = [USR_OVF];
14500}
14501def M2_mmpyl_s0 : HInst<
14502(outs DoubleRegs:$Rdd32),
14503(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14504"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat",
14505tc_c21d7447, TypeM>, Enc_a56825 {
14506let Inst{7-5} = 0b101;
14507let Inst{13-13} = 0b0;
14508let Inst{31-21} = 0b11101000000;
14509let prefersSlot3 = 1;
14510let Defs = [USR_OVF];
14511}
14512def M2_mmpyl_s1 : HInst<
14513(outs DoubleRegs:$Rdd32),
14514(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14515"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat",
14516tc_c21d7447, TypeM>, Enc_a56825 {
14517let Inst{7-5} = 0b101;
14518let Inst{13-13} = 0b0;
14519let Inst{31-21} = 0b11101000100;
14520let prefersSlot3 = 1;
14521let Defs = [USR_OVF];
14522}
14523def M2_mmpyuh_rs0 : HInst<
14524(outs DoubleRegs:$Rdd32),
14525(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14526"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat",
14527tc_c21d7447, TypeM>, Enc_a56825 {
14528let Inst{7-5} = 0b111;
14529let Inst{13-13} = 0b0;
14530let Inst{31-21} = 0b11101000011;
14531let prefersSlot3 = 1;
14532let Defs = [USR_OVF];
14533}
14534def M2_mmpyuh_rs1 : HInst<
14535(outs DoubleRegs:$Rdd32),
14536(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14537"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat",
14538tc_c21d7447, TypeM>, Enc_a56825 {
14539let Inst{7-5} = 0b111;
14540let Inst{13-13} = 0b0;
14541let Inst{31-21} = 0b11101000111;
14542let prefersSlot3 = 1;
14543let Defs = [USR_OVF];
14544}
14545def M2_mmpyuh_s0 : HInst<
14546(outs DoubleRegs:$Rdd32),
14547(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14548"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat",
14549tc_c21d7447, TypeM>, Enc_a56825 {
14550let Inst{7-5} = 0b111;
14551let Inst{13-13} = 0b0;
14552let Inst{31-21} = 0b11101000010;
14553let prefersSlot3 = 1;
14554let Defs = [USR_OVF];
14555}
14556def M2_mmpyuh_s1 : HInst<
14557(outs DoubleRegs:$Rdd32),
14558(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14559"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat",
14560tc_c21d7447, TypeM>, Enc_a56825 {
14561let Inst{7-5} = 0b111;
14562let Inst{13-13} = 0b0;
14563let Inst{31-21} = 0b11101000110;
14564let prefersSlot3 = 1;
14565let Defs = [USR_OVF];
14566}
14567def M2_mmpyul_rs0 : HInst<
14568(outs DoubleRegs:$Rdd32),
14569(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14570"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat",
14571tc_c21d7447, TypeM>, Enc_a56825 {
14572let Inst{7-5} = 0b101;
14573let Inst{13-13} = 0b0;
14574let Inst{31-21} = 0b11101000011;
14575let prefersSlot3 = 1;
14576let Defs = [USR_OVF];
14577}
14578def M2_mmpyul_rs1 : HInst<
14579(outs DoubleRegs:$Rdd32),
14580(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14581"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat",
14582tc_c21d7447, TypeM>, Enc_a56825 {
14583let Inst{7-5} = 0b101;
14584let Inst{13-13} = 0b0;
14585let Inst{31-21} = 0b11101000111;
14586let prefersSlot3 = 1;
14587let Defs = [USR_OVF];
14588}
14589def M2_mmpyul_s0 : HInst<
14590(outs DoubleRegs:$Rdd32),
14591(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14592"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat",
14593tc_c21d7447, TypeM>, Enc_a56825 {
14594let Inst{7-5} = 0b101;
14595let Inst{13-13} = 0b0;
14596let Inst{31-21} = 0b11101000010;
14597let prefersSlot3 = 1;
14598let Defs = [USR_OVF];
14599}
14600def M2_mmpyul_s1 : HInst<
14601(outs DoubleRegs:$Rdd32),
14602(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
14603"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat",
14604tc_c21d7447, TypeM>, Enc_a56825 {
14605let Inst{7-5} = 0b101;
14606let Inst{13-13} = 0b0;
14607let Inst{31-21} = 0b11101000110;
14608let prefersSlot3 = 1;
14609let Defs = [USR_OVF];
14610}
14611def M2_mnaci : HInst<
14612(outs IntRegs:$Rx32),
14613(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14614"$Rx32 -= mpyi($Rs32,$Rt32)",
14615tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> {
14616let Inst{7-5} = 0b000;
14617let Inst{13-13} = 0b0;
14618let Inst{31-21} = 0b11101111100;
14619let hasNewValue = 1;
14620let opNewValue = 0;
14621let prefersSlot3 = 1;
14622let Constraints = "$Rx32 = $Rx32in";
14623}
14624def M2_mpy_acc_hh_s0 : HInst<
14625(outs IntRegs:$Rx32),
14626(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14627"$Rx32 += mpy($Rs32.h,$Rt32.h)",
14628tc_7f8ae742, TypeM>, Enc_2ae154 {
14629let Inst{7-5} = 0b011;
14630let Inst{13-13} = 0b0;
14631let Inst{31-21} = 0b11101110000;
14632let hasNewValue = 1;
14633let opNewValue = 0;
14634let prefersSlot3 = 1;
14635let Constraints = "$Rx32 = $Rx32in";
14636}
14637def M2_mpy_acc_hh_s1 : HInst<
14638(outs IntRegs:$Rx32),
14639(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14640"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1",
14641tc_7f8ae742, TypeM>, Enc_2ae154 {
14642let Inst{7-5} = 0b011;
14643let Inst{13-13} = 0b0;
14644let Inst{31-21} = 0b11101110100;
14645let hasNewValue = 1;
14646let opNewValue = 0;
14647let prefersSlot3 = 1;
14648let Constraints = "$Rx32 = $Rx32in";
14649}
14650def M2_mpy_acc_hl_s0 : HInst<
14651(outs IntRegs:$Rx32),
14652(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14653"$Rx32 += mpy($Rs32.h,$Rt32.l)",
14654tc_7f8ae742, TypeM>, Enc_2ae154 {
14655let Inst{7-5} = 0b010;
14656let Inst{13-13} = 0b0;
14657let Inst{31-21} = 0b11101110000;
14658let hasNewValue = 1;
14659let opNewValue = 0;
14660let prefersSlot3 = 1;
14661let Constraints = "$Rx32 = $Rx32in";
14662}
14663def M2_mpy_acc_hl_s1 : HInst<
14664(outs IntRegs:$Rx32),
14665(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14666"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1",
14667tc_7f8ae742, TypeM>, Enc_2ae154 {
14668let Inst{7-5} = 0b010;
14669let Inst{13-13} = 0b0;
14670let Inst{31-21} = 0b11101110100;
14671let hasNewValue = 1;
14672let opNewValue = 0;
14673let prefersSlot3 = 1;
14674let Constraints = "$Rx32 = $Rx32in";
14675}
14676def M2_mpy_acc_lh_s0 : HInst<
14677(outs IntRegs:$Rx32),
14678(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14679"$Rx32 += mpy($Rs32.l,$Rt32.h)",
14680tc_7f8ae742, TypeM>, Enc_2ae154 {
14681let Inst{7-5} = 0b001;
14682let Inst{13-13} = 0b0;
14683let Inst{31-21} = 0b11101110000;
14684let hasNewValue = 1;
14685let opNewValue = 0;
14686let prefersSlot3 = 1;
14687let Constraints = "$Rx32 = $Rx32in";
14688}
14689def M2_mpy_acc_lh_s1 : HInst<
14690(outs IntRegs:$Rx32),
14691(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14692"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1",
14693tc_7f8ae742, TypeM>, Enc_2ae154 {
14694let Inst{7-5} = 0b001;
14695let Inst{13-13} = 0b0;
14696let Inst{31-21} = 0b11101110100;
14697let hasNewValue = 1;
14698let opNewValue = 0;
14699let prefersSlot3 = 1;
14700let Constraints = "$Rx32 = $Rx32in";
14701}
14702def M2_mpy_acc_ll_s0 : HInst<
14703(outs IntRegs:$Rx32),
14704(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14705"$Rx32 += mpy($Rs32.l,$Rt32.l)",
14706tc_7f8ae742, TypeM>, Enc_2ae154 {
14707let Inst{7-5} = 0b000;
14708let Inst{13-13} = 0b0;
14709let Inst{31-21} = 0b11101110000;
14710let hasNewValue = 1;
14711let opNewValue = 0;
14712let prefersSlot3 = 1;
14713let Constraints = "$Rx32 = $Rx32in";
14714}
14715def M2_mpy_acc_ll_s1 : HInst<
14716(outs IntRegs:$Rx32),
14717(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14718"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1",
14719tc_7f8ae742, TypeM>, Enc_2ae154 {
14720let Inst{7-5} = 0b000;
14721let Inst{13-13} = 0b0;
14722let Inst{31-21} = 0b11101110100;
14723let hasNewValue = 1;
14724let opNewValue = 0;
14725let prefersSlot3 = 1;
14726let Constraints = "$Rx32 = $Rx32in";
14727}
14728def M2_mpy_acc_sat_hh_s0 : HInst<
14729(outs IntRegs:$Rx32),
14730(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14731"$Rx32 += mpy($Rs32.h,$Rt32.h):sat",
14732tc_7f8ae742, TypeM>, Enc_2ae154 {
14733let Inst{7-5} = 0b111;
14734let Inst{13-13} = 0b0;
14735let Inst{31-21} = 0b11101110000;
14736let hasNewValue = 1;
14737let opNewValue = 0;
14738let prefersSlot3 = 1;
14739let Defs = [USR_OVF];
14740let Constraints = "$Rx32 = $Rx32in";
14741}
14742def M2_mpy_acc_sat_hh_s1 : HInst<
14743(outs IntRegs:$Rx32),
14744(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14745"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat",
14746tc_7f8ae742, TypeM>, Enc_2ae154 {
14747let Inst{7-5} = 0b111;
14748let Inst{13-13} = 0b0;
14749let Inst{31-21} = 0b11101110100;
14750let hasNewValue = 1;
14751let opNewValue = 0;
14752let prefersSlot3 = 1;
14753let Defs = [USR_OVF];
14754let Constraints = "$Rx32 = $Rx32in";
14755}
14756def M2_mpy_acc_sat_hl_s0 : HInst<
14757(outs IntRegs:$Rx32),
14758(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14759"$Rx32 += mpy($Rs32.h,$Rt32.l):sat",
14760tc_7f8ae742, TypeM>, Enc_2ae154 {
14761let Inst{7-5} = 0b110;
14762let Inst{13-13} = 0b0;
14763let Inst{31-21} = 0b11101110000;
14764let hasNewValue = 1;
14765let opNewValue = 0;
14766let prefersSlot3 = 1;
14767let Defs = [USR_OVF];
14768let Constraints = "$Rx32 = $Rx32in";
14769}
14770def M2_mpy_acc_sat_hl_s1 : HInst<
14771(outs IntRegs:$Rx32),
14772(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14773"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat",
14774tc_7f8ae742, TypeM>, Enc_2ae154 {
14775let Inst{7-5} = 0b110;
14776let Inst{13-13} = 0b0;
14777let Inst{31-21} = 0b11101110100;
14778let hasNewValue = 1;
14779let opNewValue = 0;
14780let prefersSlot3 = 1;
14781let Defs = [USR_OVF];
14782let Constraints = "$Rx32 = $Rx32in";
14783}
14784def M2_mpy_acc_sat_lh_s0 : HInst<
14785(outs IntRegs:$Rx32),
14786(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14787"$Rx32 += mpy($Rs32.l,$Rt32.h):sat",
14788tc_7f8ae742, TypeM>, Enc_2ae154 {
14789let Inst{7-5} = 0b101;
14790let Inst{13-13} = 0b0;
14791let Inst{31-21} = 0b11101110000;
14792let hasNewValue = 1;
14793let opNewValue = 0;
14794let prefersSlot3 = 1;
14795let Defs = [USR_OVF];
14796let Constraints = "$Rx32 = $Rx32in";
14797}
14798def M2_mpy_acc_sat_lh_s1 : HInst<
14799(outs IntRegs:$Rx32),
14800(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14801"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat",
14802tc_7f8ae742, TypeM>, Enc_2ae154 {
14803let Inst{7-5} = 0b101;
14804let Inst{13-13} = 0b0;
14805let Inst{31-21} = 0b11101110100;
14806let hasNewValue = 1;
14807let opNewValue = 0;
14808let prefersSlot3 = 1;
14809let Defs = [USR_OVF];
14810let Constraints = "$Rx32 = $Rx32in";
14811}
14812def M2_mpy_acc_sat_ll_s0 : HInst<
14813(outs IntRegs:$Rx32),
14814(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14815"$Rx32 += mpy($Rs32.l,$Rt32.l):sat",
14816tc_7f8ae742, TypeM>, Enc_2ae154 {
14817let Inst{7-5} = 0b100;
14818let Inst{13-13} = 0b0;
14819let Inst{31-21} = 0b11101110000;
14820let hasNewValue = 1;
14821let opNewValue = 0;
14822let prefersSlot3 = 1;
14823let Defs = [USR_OVF];
14824let Constraints = "$Rx32 = $Rx32in";
14825}
14826def M2_mpy_acc_sat_ll_s1 : HInst<
14827(outs IntRegs:$Rx32),
14828(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14829"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat",
14830tc_7f8ae742, TypeM>, Enc_2ae154 {
14831let Inst{7-5} = 0b100;
14832let Inst{13-13} = 0b0;
14833let Inst{31-21} = 0b11101110100;
14834let hasNewValue = 1;
14835let opNewValue = 0;
14836let prefersSlot3 = 1;
14837let Defs = [USR_OVF];
14838let Constraints = "$Rx32 = $Rx32in";
14839}
14840def M2_mpy_hh_s0 : HInst<
14841(outs IntRegs:$Rd32),
14842(ins IntRegs:$Rs32, IntRegs:$Rt32),
14843"$Rd32 = mpy($Rs32.h,$Rt32.h)",
14844tc_c21d7447, TypeM>, Enc_5ab2be {
14845let Inst{7-5} = 0b011;
14846let Inst{13-13} = 0b0;
14847let Inst{31-21} = 0b11101100000;
14848let hasNewValue = 1;
14849let opNewValue = 0;
14850let prefersSlot3 = 1;
14851}
14852def M2_mpy_hh_s1 : HInst<
14853(outs IntRegs:$Rd32),
14854(ins IntRegs:$Rs32, IntRegs:$Rt32),
14855"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1",
14856tc_c21d7447, TypeM>, Enc_5ab2be {
14857let Inst{7-5} = 0b011;
14858let Inst{13-13} = 0b0;
14859let Inst{31-21} = 0b11101100100;
14860let hasNewValue = 1;
14861let opNewValue = 0;
14862let prefersSlot3 = 1;
14863}
14864def M2_mpy_hl_s0 : HInst<
14865(outs IntRegs:$Rd32),
14866(ins IntRegs:$Rs32, IntRegs:$Rt32),
14867"$Rd32 = mpy($Rs32.h,$Rt32.l)",
14868tc_c21d7447, TypeM>, Enc_5ab2be {
14869let Inst{7-5} = 0b010;
14870let Inst{13-13} = 0b0;
14871let Inst{31-21} = 0b11101100000;
14872let hasNewValue = 1;
14873let opNewValue = 0;
14874let prefersSlot3 = 1;
14875}
14876def M2_mpy_hl_s1 : HInst<
14877(outs IntRegs:$Rd32),
14878(ins IntRegs:$Rs32, IntRegs:$Rt32),
14879"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1",
14880tc_c21d7447, TypeM>, Enc_5ab2be {
14881let Inst{7-5} = 0b010;
14882let Inst{13-13} = 0b0;
14883let Inst{31-21} = 0b11101100100;
14884let hasNewValue = 1;
14885let opNewValue = 0;
14886let prefersSlot3 = 1;
14887}
14888def M2_mpy_lh_s0 : HInst<
14889(outs IntRegs:$Rd32),
14890(ins IntRegs:$Rs32, IntRegs:$Rt32),
14891"$Rd32 = mpy($Rs32.l,$Rt32.h)",
14892tc_c21d7447, TypeM>, Enc_5ab2be {
14893let Inst{7-5} = 0b001;
14894let Inst{13-13} = 0b0;
14895let Inst{31-21} = 0b11101100000;
14896let hasNewValue = 1;
14897let opNewValue = 0;
14898let prefersSlot3 = 1;
14899}
14900def M2_mpy_lh_s1 : HInst<
14901(outs IntRegs:$Rd32),
14902(ins IntRegs:$Rs32, IntRegs:$Rt32),
14903"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1",
14904tc_c21d7447, TypeM>, Enc_5ab2be {
14905let Inst{7-5} = 0b001;
14906let Inst{13-13} = 0b0;
14907let Inst{31-21} = 0b11101100100;
14908let hasNewValue = 1;
14909let opNewValue = 0;
14910let prefersSlot3 = 1;
14911}
14912def M2_mpy_ll_s0 : HInst<
14913(outs IntRegs:$Rd32),
14914(ins IntRegs:$Rs32, IntRegs:$Rt32),
14915"$Rd32 = mpy($Rs32.l,$Rt32.l)",
14916tc_c21d7447, TypeM>, Enc_5ab2be {
14917let Inst{7-5} = 0b000;
14918let Inst{13-13} = 0b0;
14919let Inst{31-21} = 0b11101100000;
14920let hasNewValue = 1;
14921let opNewValue = 0;
14922let prefersSlot3 = 1;
14923}
14924def M2_mpy_ll_s1 : HInst<
14925(outs IntRegs:$Rd32),
14926(ins IntRegs:$Rs32, IntRegs:$Rt32),
14927"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1",
14928tc_c21d7447, TypeM>, Enc_5ab2be {
14929let Inst{7-5} = 0b000;
14930let Inst{13-13} = 0b0;
14931let Inst{31-21} = 0b11101100100;
14932let hasNewValue = 1;
14933let opNewValue = 0;
14934let prefersSlot3 = 1;
14935}
14936def M2_mpy_nac_hh_s0 : HInst<
14937(outs IntRegs:$Rx32),
14938(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14939"$Rx32 -= mpy($Rs32.h,$Rt32.h)",
14940tc_7f8ae742, TypeM>, Enc_2ae154 {
14941let Inst{7-5} = 0b011;
14942let Inst{13-13} = 0b0;
14943let Inst{31-21} = 0b11101110001;
14944let hasNewValue = 1;
14945let opNewValue = 0;
14946let prefersSlot3 = 1;
14947let Constraints = "$Rx32 = $Rx32in";
14948}
14949def M2_mpy_nac_hh_s1 : HInst<
14950(outs IntRegs:$Rx32),
14951(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14952"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1",
14953tc_7f8ae742, TypeM>, Enc_2ae154 {
14954let Inst{7-5} = 0b011;
14955let Inst{13-13} = 0b0;
14956let Inst{31-21} = 0b11101110101;
14957let hasNewValue = 1;
14958let opNewValue = 0;
14959let prefersSlot3 = 1;
14960let Constraints = "$Rx32 = $Rx32in";
14961}
14962def M2_mpy_nac_hl_s0 : HInst<
14963(outs IntRegs:$Rx32),
14964(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14965"$Rx32 -= mpy($Rs32.h,$Rt32.l)",
14966tc_7f8ae742, TypeM>, Enc_2ae154 {
14967let Inst{7-5} = 0b010;
14968let Inst{13-13} = 0b0;
14969let Inst{31-21} = 0b11101110001;
14970let hasNewValue = 1;
14971let opNewValue = 0;
14972let prefersSlot3 = 1;
14973let Constraints = "$Rx32 = $Rx32in";
14974}
14975def M2_mpy_nac_hl_s1 : HInst<
14976(outs IntRegs:$Rx32),
14977(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14978"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1",
14979tc_7f8ae742, TypeM>, Enc_2ae154 {
14980let Inst{7-5} = 0b010;
14981let Inst{13-13} = 0b0;
14982let Inst{31-21} = 0b11101110101;
14983let hasNewValue = 1;
14984let opNewValue = 0;
14985let prefersSlot3 = 1;
14986let Constraints = "$Rx32 = $Rx32in";
14987}
14988def M2_mpy_nac_lh_s0 : HInst<
14989(outs IntRegs:$Rx32),
14990(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
14991"$Rx32 -= mpy($Rs32.l,$Rt32.h)",
14992tc_7f8ae742, TypeM>, Enc_2ae154 {
14993let Inst{7-5} = 0b001;
14994let Inst{13-13} = 0b0;
14995let Inst{31-21} = 0b11101110001;
14996let hasNewValue = 1;
14997let opNewValue = 0;
14998let prefersSlot3 = 1;
14999let Constraints = "$Rx32 = $Rx32in";
15000}
15001def M2_mpy_nac_lh_s1 : HInst<
15002(outs IntRegs:$Rx32),
15003(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15004"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15005tc_7f8ae742, TypeM>, Enc_2ae154 {
15006let Inst{7-5} = 0b001;
15007let Inst{13-13} = 0b0;
15008let Inst{31-21} = 0b11101110101;
15009let hasNewValue = 1;
15010let opNewValue = 0;
15011let prefersSlot3 = 1;
15012let Constraints = "$Rx32 = $Rx32in";
15013}
15014def M2_mpy_nac_ll_s0 : HInst<
15015(outs IntRegs:$Rx32),
15016(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15017"$Rx32 -= mpy($Rs32.l,$Rt32.l)",
15018tc_7f8ae742, TypeM>, Enc_2ae154 {
15019let Inst{7-5} = 0b000;
15020let Inst{13-13} = 0b0;
15021let Inst{31-21} = 0b11101110001;
15022let hasNewValue = 1;
15023let opNewValue = 0;
15024let prefersSlot3 = 1;
15025let Constraints = "$Rx32 = $Rx32in";
15026}
15027def M2_mpy_nac_ll_s1 : HInst<
15028(outs IntRegs:$Rx32),
15029(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15030"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15031tc_7f8ae742, TypeM>, Enc_2ae154 {
15032let Inst{7-5} = 0b000;
15033let Inst{13-13} = 0b0;
15034let Inst{31-21} = 0b11101110101;
15035let hasNewValue = 1;
15036let opNewValue = 0;
15037let prefersSlot3 = 1;
15038let Constraints = "$Rx32 = $Rx32in";
15039}
15040def M2_mpy_nac_sat_hh_s0 : HInst<
15041(outs IntRegs:$Rx32),
15042(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15043"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat",
15044tc_7f8ae742, TypeM>, Enc_2ae154 {
15045let Inst{7-5} = 0b111;
15046let Inst{13-13} = 0b0;
15047let Inst{31-21} = 0b11101110001;
15048let hasNewValue = 1;
15049let opNewValue = 0;
15050let prefersSlot3 = 1;
15051let Defs = [USR_OVF];
15052let Constraints = "$Rx32 = $Rx32in";
15053}
15054def M2_mpy_nac_sat_hh_s1 : HInst<
15055(outs IntRegs:$Rx32),
15056(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15057"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat",
15058tc_7f8ae742, TypeM>, Enc_2ae154 {
15059let Inst{7-5} = 0b111;
15060let Inst{13-13} = 0b0;
15061let Inst{31-21} = 0b11101110101;
15062let hasNewValue = 1;
15063let opNewValue = 0;
15064let prefersSlot3 = 1;
15065let Defs = [USR_OVF];
15066let Constraints = "$Rx32 = $Rx32in";
15067}
15068def M2_mpy_nac_sat_hl_s0 : HInst<
15069(outs IntRegs:$Rx32),
15070(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15071"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat",
15072tc_7f8ae742, TypeM>, Enc_2ae154 {
15073let Inst{7-5} = 0b110;
15074let Inst{13-13} = 0b0;
15075let Inst{31-21} = 0b11101110001;
15076let hasNewValue = 1;
15077let opNewValue = 0;
15078let prefersSlot3 = 1;
15079let Defs = [USR_OVF];
15080let Constraints = "$Rx32 = $Rx32in";
15081}
15082def M2_mpy_nac_sat_hl_s1 : HInst<
15083(outs IntRegs:$Rx32),
15084(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15085"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat",
15086tc_7f8ae742, TypeM>, Enc_2ae154 {
15087let Inst{7-5} = 0b110;
15088let Inst{13-13} = 0b0;
15089let Inst{31-21} = 0b11101110101;
15090let hasNewValue = 1;
15091let opNewValue = 0;
15092let prefersSlot3 = 1;
15093let Defs = [USR_OVF];
15094let Constraints = "$Rx32 = $Rx32in";
15095}
15096def M2_mpy_nac_sat_lh_s0 : HInst<
15097(outs IntRegs:$Rx32),
15098(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15099"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat",
15100tc_7f8ae742, TypeM>, Enc_2ae154 {
15101let Inst{7-5} = 0b101;
15102let Inst{13-13} = 0b0;
15103let Inst{31-21} = 0b11101110001;
15104let hasNewValue = 1;
15105let opNewValue = 0;
15106let prefersSlot3 = 1;
15107let Defs = [USR_OVF];
15108let Constraints = "$Rx32 = $Rx32in";
15109}
15110def M2_mpy_nac_sat_lh_s1 : HInst<
15111(outs IntRegs:$Rx32),
15112(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15113"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat",
15114tc_7f8ae742, TypeM>, Enc_2ae154 {
15115let Inst{7-5} = 0b101;
15116let Inst{13-13} = 0b0;
15117let Inst{31-21} = 0b11101110101;
15118let hasNewValue = 1;
15119let opNewValue = 0;
15120let prefersSlot3 = 1;
15121let Defs = [USR_OVF];
15122let Constraints = "$Rx32 = $Rx32in";
15123}
15124def M2_mpy_nac_sat_ll_s0 : HInst<
15125(outs IntRegs:$Rx32),
15126(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15127"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat",
15128tc_7f8ae742, TypeM>, Enc_2ae154 {
15129let Inst{7-5} = 0b100;
15130let Inst{13-13} = 0b0;
15131let Inst{31-21} = 0b11101110001;
15132let hasNewValue = 1;
15133let opNewValue = 0;
15134let prefersSlot3 = 1;
15135let Defs = [USR_OVF];
15136let Constraints = "$Rx32 = $Rx32in";
15137}
15138def M2_mpy_nac_sat_ll_s1 : HInst<
15139(outs IntRegs:$Rx32),
15140(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15141"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat",
15142tc_7f8ae742, TypeM>, Enc_2ae154 {
15143let Inst{7-5} = 0b100;
15144let Inst{13-13} = 0b0;
15145let Inst{31-21} = 0b11101110101;
15146let hasNewValue = 1;
15147let opNewValue = 0;
15148let prefersSlot3 = 1;
15149let Defs = [USR_OVF];
15150let Constraints = "$Rx32 = $Rx32in";
15151}
15152def M2_mpy_rnd_hh_s0 : HInst<
15153(outs IntRegs:$Rd32),
15154(ins IntRegs:$Rs32, IntRegs:$Rt32),
15155"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd",
15156tc_c21d7447, TypeM>, Enc_5ab2be {
15157let Inst{7-5} = 0b011;
15158let Inst{13-13} = 0b0;
15159let Inst{31-21} = 0b11101100001;
15160let hasNewValue = 1;
15161let opNewValue = 0;
15162let prefersSlot3 = 1;
15163}
15164def M2_mpy_rnd_hh_s1 : HInst<
15165(outs IntRegs:$Rd32),
15166(ins IntRegs:$Rs32, IntRegs:$Rt32),
15167"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15168tc_c21d7447, TypeM>, Enc_5ab2be {
15169let Inst{7-5} = 0b011;
15170let Inst{13-13} = 0b0;
15171let Inst{31-21} = 0b11101100101;
15172let hasNewValue = 1;
15173let opNewValue = 0;
15174let prefersSlot3 = 1;
15175}
15176def M2_mpy_rnd_hl_s0 : HInst<
15177(outs IntRegs:$Rd32),
15178(ins IntRegs:$Rs32, IntRegs:$Rt32),
15179"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd",
15180tc_c21d7447, TypeM>, Enc_5ab2be {
15181let Inst{7-5} = 0b010;
15182let Inst{13-13} = 0b0;
15183let Inst{31-21} = 0b11101100001;
15184let hasNewValue = 1;
15185let opNewValue = 0;
15186let prefersSlot3 = 1;
15187}
15188def M2_mpy_rnd_hl_s1 : HInst<
15189(outs IntRegs:$Rd32),
15190(ins IntRegs:$Rs32, IntRegs:$Rt32),
15191"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15192tc_c21d7447, TypeM>, Enc_5ab2be {
15193let Inst{7-5} = 0b010;
15194let Inst{13-13} = 0b0;
15195let Inst{31-21} = 0b11101100101;
15196let hasNewValue = 1;
15197let opNewValue = 0;
15198let prefersSlot3 = 1;
15199}
15200def M2_mpy_rnd_lh_s0 : HInst<
15201(outs IntRegs:$Rd32),
15202(ins IntRegs:$Rs32, IntRegs:$Rt32),
15203"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd",
15204tc_c21d7447, TypeM>, Enc_5ab2be {
15205let Inst{7-5} = 0b001;
15206let Inst{13-13} = 0b0;
15207let Inst{31-21} = 0b11101100001;
15208let hasNewValue = 1;
15209let opNewValue = 0;
15210let prefersSlot3 = 1;
15211}
15212def M2_mpy_rnd_lh_s1 : HInst<
15213(outs IntRegs:$Rd32),
15214(ins IntRegs:$Rs32, IntRegs:$Rt32),
15215"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15216tc_c21d7447, TypeM>, Enc_5ab2be {
15217let Inst{7-5} = 0b001;
15218let Inst{13-13} = 0b0;
15219let Inst{31-21} = 0b11101100101;
15220let hasNewValue = 1;
15221let opNewValue = 0;
15222let prefersSlot3 = 1;
15223}
15224def M2_mpy_rnd_ll_s0 : HInst<
15225(outs IntRegs:$Rd32),
15226(ins IntRegs:$Rs32, IntRegs:$Rt32),
15227"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd",
15228tc_c21d7447, TypeM>, Enc_5ab2be {
15229let Inst{7-5} = 0b000;
15230let Inst{13-13} = 0b0;
15231let Inst{31-21} = 0b11101100001;
15232let hasNewValue = 1;
15233let opNewValue = 0;
15234let prefersSlot3 = 1;
15235}
15236def M2_mpy_rnd_ll_s1 : HInst<
15237(outs IntRegs:$Rd32),
15238(ins IntRegs:$Rs32, IntRegs:$Rt32),
15239"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15240tc_c21d7447, TypeM>, Enc_5ab2be {
15241let Inst{7-5} = 0b000;
15242let Inst{13-13} = 0b0;
15243let Inst{31-21} = 0b11101100101;
15244let hasNewValue = 1;
15245let opNewValue = 0;
15246let prefersSlot3 = 1;
15247}
15248def M2_mpy_sat_hh_s0 : HInst<
15249(outs IntRegs:$Rd32),
15250(ins IntRegs:$Rs32, IntRegs:$Rt32),
15251"$Rd32 = mpy($Rs32.h,$Rt32.h):sat",
15252tc_c21d7447, TypeM>, Enc_5ab2be {
15253let Inst{7-5} = 0b111;
15254let Inst{13-13} = 0b0;
15255let Inst{31-21} = 0b11101100000;
15256let hasNewValue = 1;
15257let opNewValue = 0;
15258let prefersSlot3 = 1;
15259let Defs = [USR_OVF];
15260}
15261def M2_mpy_sat_hh_s1 : HInst<
15262(outs IntRegs:$Rd32),
15263(ins IntRegs:$Rs32, IntRegs:$Rt32),
15264"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat",
15265tc_c21d7447, TypeM>, Enc_5ab2be {
15266let Inst{7-5} = 0b111;
15267let Inst{13-13} = 0b0;
15268let Inst{31-21} = 0b11101100100;
15269let hasNewValue = 1;
15270let opNewValue = 0;
15271let prefersSlot3 = 1;
15272let Defs = [USR_OVF];
15273}
15274def M2_mpy_sat_hl_s0 : HInst<
15275(outs IntRegs:$Rd32),
15276(ins IntRegs:$Rs32, IntRegs:$Rt32),
15277"$Rd32 = mpy($Rs32.h,$Rt32.l):sat",
15278tc_c21d7447, TypeM>, Enc_5ab2be {
15279let Inst{7-5} = 0b110;
15280let Inst{13-13} = 0b0;
15281let Inst{31-21} = 0b11101100000;
15282let hasNewValue = 1;
15283let opNewValue = 0;
15284let prefersSlot3 = 1;
15285let Defs = [USR_OVF];
15286}
15287def M2_mpy_sat_hl_s1 : HInst<
15288(outs IntRegs:$Rd32),
15289(ins IntRegs:$Rs32, IntRegs:$Rt32),
15290"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat",
15291tc_c21d7447, TypeM>, Enc_5ab2be {
15292let Inst{7-5} = 0b110;
15293let Inst{13-13} = 0b0;
15294let Inst{31-21} = 0b11101100100;
15295let hasNewValue = 1;
15296let opNewValue = 0;
15297let prefersSlot3 = 1;
15298let Defs = [USR_OVF];
15299}
15300def M2_mpy_sat_lh_s0 : HInst<
15301(outs IntRegs:$Rd32),
15302(ins IntRegs:$Rs32, IntRegs:$Rt32),
15303"$Rd32 = mpy($Rs32.l,$Rt32.h):sat",
15304tc_c21d7447, TypeM>, Enc_5ab2be {
15305let Inst{7-5} = 0b101;
15306let Inst{13-13} = 0b0;
15307let Inst{31-21} = 0b11101100000;
15308let hasNewValue = 1;
15309let opNewValue = 0;
15310let prefersSlot3 = 1;
15311let Defs = [USR_OVF];
15312}
15313def M2_mpy_sat_lh_s1 : HInst<
15314(outs IntRegs:$Rd32),
15315(ins IntRegs:$Rs32, IntRegs:$Rt32),
15316"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat",
15317tc_c21d7447, TypeM>, Enc_5ab2be {
15318let Inst{7-5} = 0b101;
15319let Inst{13-13} = 0b0;
15320let Inst{31-21} = 0b11101100100;
15321let hasNewValue = 1;
15322let opNewValue = 0;
15323let prefersSlot3 = 1;
15324let Defs = [USR_OVF];
15325}
15326def M2_mpy_sat_ll_s0 : HInst<
15327(outs IntRegs:$Rd32),
15328(ins IntRegs:$Rs32, IntRegs:$Rt32),
15329"$Rd32 = mpy($Rs32.l,$Rt32.l):sat",
15330tc_c21d7447, TypeM>, Enc_5ab2be {
15331let Inst{7-5} = 0b100;
15332let Inst{13-13} = 0b0;
15333let Inst{31-21} = 0b11101100000;
15334let hasNewValue = 1;
15335let opNewValue = 0;
15336let prefersSlot3 = 1;
15337let Defs = [USR_OVF];
15338}
15339def M2_mpy_sat_ll_s1 : HInst<
15340(outs IntRegs:$Rd32),
15341(ins IntRegs:$Rs32, IntRegs:$Rt32),
15342"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat",
15343tc_c21d7447, TypeM>, Enc_5ab2be {
15344let Inst{7-5} = 0b100;
15345let Inst{13-13} = 0b0;
15346let Inst{31-21} = 0b11101100100;
15347let hasNewValue = 1;
15348let opNewValue = 0;
15349let prefersSlot3 = 1;
15350let Defs = [USR_OVF];
15351}
15352def M2_mpy_sat_rnd_hh_s0 : HInst<
15353(outs IntRegs:$Rd32),
15354(ins IntRegs:$Rs32, IntRegs:$Rt32),
15355"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat",
15356tc_c21d7447, TypeM>, Enc_5ab2be {
15357let Inst{7-5} = 0b111;
15358let Inst{13-13} = 0b0;
15359let Inst{31-21} = 0b11101100001;
15360let hasNewValue = 1;
15361let opNewValue = 0;
15362let prefersSlot3 = 1;
15363let Defs = [USR_OVF];
15364}
15365def M2_mpy_sat_rnd_hh_s1 : HInst<
15366(outs IntRegs:$Rd32),
15367(ins IntRegs:$Rs32, IntRegs:$Rt32),
15368"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat",
15369tc_c21d7447, TypeM>, Enc_5ab2be {
15370let Inst{7-5} = 0b111;
15371let Inst{13-13} = 0b0;
15372let Inst{31-21} = 0b11101100101;
15373let hasNewValue = 1;
15374let opNewValue = 0;
15375let prefersSlot3 = 1;
15376let Defs = [USR_OVF];
15377}
15378def M2_mpy_sat_rnd_hl_s0 : HInst<
15379(outs IntRegs:$Rd32),
15380(ins IntRegs:$Rs32, IntRegs:$Rt32),
15381"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat",
15382tc_c21d7447, TypeM>, Enc_5ab2be {
15383let Inst{7-5} = 0b110;
15384let Inst{13-13} = 0b0;
15385let Inst{31-21} = 0b11101100001;
15386let hasNewValue = 1;
15387let opNewValue = 0;
15388let prefersSlot3 = 1;
15389let Defs = [USR_OVF];
15390}
15391def M2_mpy_sat_rnd_hl_s1 : HInst<
15392(outs IntRegs:$Rd32),
15393(ins IntRegs:$Rs32, IntRegs:$Rt32),
15394"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat",
15395tc_c21d7447, TypeM>, Enc_5ab2be {
15396let Inst{7-5} = 0b110;
15397let Inst{13-13} = 0b0;
15398let Inst{31-21} = 0b11101100101;
15399let hasNewValue = 1;
15400let opNewValue = 0;
15401let prefersSlot3 = 1;
15402let Defs = [USR_OVF];
15403}
15404def M2_mpy_sat_rnd_lh_s0 : HInst<
15405(outs IntRegs:$Rd32),
15406(ins IntRegs:$Rs32, IntRegs:$Rt32),
15407"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat",
15408tc_c21d7447, TypeM>, Enc_5ab2be {
15409let Inst{7-5} = 0b101;
15410let Inst{13-13} = 0b0;
15411let Inst{31-21} = 0b11101100001;
15412let hasNewValue = 1;
15413let opNewValue = 0;
15414let prefersSlot3 = 1;
15415let Defs = [USR_OVF];
15416}
15417def M2_mpy_sat_rnd_lh_s1 : HInst<
15418(outs IntRegs:$Rd32),
15419(ins IntRegs:$Rs32, IntRegs:$Rt32),
15420"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat",
15421tc_c21d7447, TypeM>, Enc_5ab2be {
15422let Inst{7-5} = 0b101;
15423let Inst{13-13} = 0b0;
15424let Inst{31-21} = 0b11101100101;
15425let hasNewValue = 1;
15426let opNewValue = 0;
15427let prefersSlot3 = 1;
15428let Defs = [USR_OVF];
15429}
15430def M2_mpy_sat_rnd_ll_s0 : HInst<
15431(outs IntRegs:$Rd32),
15432(ins IntRegs:$Rs32, IntRegs:$Rt32),
15433"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat",
15434tc_c21d7447, TypeM>, Enc_5ab2be {
15435let Inst{7-5} = 0b100;
15436let Inst{13-13} = 0b0;
15437let Inst{31-21} = 0b11101100001;
15438let hasNewValue = 1;
15439let opNewValue = 0;
15440let prefersSlot3 = 1;
15441let Defs = [USR_OVF];
15442}
15443def M2_mpy_sat_rnd_ll_s1 : HInst<
15444(outs IntRegs:$Rd32),
15445(ins IntRegs:$Rs32, IntRegs:$Rt32),
15446"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat",
15447tc_c21d7447, TypeM>, Enc_5ab2be {
15448let Inst{7-5} = 0b100;
15449let Inst{13-13} = 0b0;
15450let Inst{31-21} = 0b11101100101;
15451let hasNewValue = 1;
15452let opNewValue = 0;
15453let prefersSlot3 = 1;
15454let Defs = [USR_OVF];
15455}
15456def M2_mpy_up : HInst<
15457(outs IntRegs:$Rd32),
15458(ins IntRegs:$Rs32, IntRegs:$Rt32),
15459"$Rd32 = mpy($Rs32,$Rt32)",
15460tc_c21d7447, TypeM>, Enc_5ab2be {
15461let Inst{7-5} = 0b001;
15462let Inst{13-13} = 0b0;
15463let Inst{31-21} = 0b11101101000;
15464let hasNewValue = 1;
15465let opNewValue = 0;
15466let prefersSlot3 = 1;
15467}
15468def M2_mpy_up_s1 : HInst<
15469(outs IntRegs:$Rd32),
15470(ins IntRegs:$Rs32, IntRegs:$Rt32),
15471"$Rd32 = mpy($Rs32,$Rt32):<<1",
15472tc_c21d7447, TypeM>, Enc_5ab2be {
15473let Inst{7-5} = 0b010;
15474let Inst{13-13} = 0b0;
15475let Inst{31-21} = 0b11101101101;
15476let hasNewValue = 1;
15477let opNewValue = 0;
15478let prefersSlot3 = 1;
15479}
15480def M2_mpy_up_s1_sat : HInst<
15481(outs IntRegs:$Rd32),
15482(ins IntRegs:$Rs32, IntRegs:$Rt32),
15483"$Rd32 = mpy($Rs32,$Rt32):<<1:sat",
15484tc_c21d7447, TypeM>, Enc_5ab2be {
15485let Inst{7-5} = 0b000;
15486let Inst{13-13} = 0b0;
15487let Inst{31-21} = 0b11101101111;
15488let hasNewValue = 1;
15489let opNewValue = 0;
15490let prefersSlot3 = 1;
15491let Defs = [USR_OVF];
15492}
15493def M2_mpyd_acc_hh_s0 : HInst<
15494(outs DoubleRegs:$Rxx32),
15495(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15496"$Rxx32 += mpy($Rs32.h,$Rt32.h)",
15497tc_7f8ae742, TypeM>, Enc_61f0b0 {
15498let Inst{7-5} = 0b011;
15499let Inst{13-13} = 0b0;
15500let Inst{31-21} = 0b11100110000;
15501let prefersSlot3 = 1;
15502let Constraints = "$Rxx32 = $Rxx32in";
15503}
15504def M2_mpyd_acc_hh_s1 : HInst<
15505(outs DoubleRegs:$Rxx32),
15506(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15507"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1",
15508tc_7f8ae742, TypeM>, Enc_61f0b0 {
15509let Inst{7-5} = 0b011;
15510let Inst{13-13} = 0b0;
15511let Inst{31-21} = 0b11100110100;
15512let prefersSlot3 = 1;
15513let Constraints = "$Rxx32 = $Rxx32in";
15514}
15515def M2_mpyd_acc_hl_s0 : HInst<
15516(outs DoubleRegs:$Rxx32),
15517(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15518"$Rxx32 += mpy($Rs32.h,$Rt32.l)",
15519tc_7f8ae742, TypeM>, Enc_61f0b0 {
15520let Inst{7-5} = 0b010;
15521let Inst{13-13} = 0b0;
15522let Inst{31-21} = 0b11100110000;
15523let prefersSlot3 = 1;
15524let Constraints = "$Rxx32 = $Rxx32in";
15525}
15526def M2_mpyd_acc_hl_s1 : HInst<
15527(outs DoubleRegs:$Rxx32),
15528(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15529"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1",
15530tc_7f8ae742, TypeM>, Enc_61f0b0 {
15531let Inst{7-5} = 0b010;
15532let Inst{13-13} = 0b0;
15533let Inst{31-21} = 0b11100110100;
15534let prefersSlot3 = 1;
15535let Constraints = "$Rxx32 = $Rxx32in";
15536}
15537def M2_mpyd_acc_lh_s0 : HInst<
15538(outs DoubleRegs:$Rxx32),
15539(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15540"$Rxx32 += mpy($Rs32.l,$Rt32.h)",
15541tc_7f8ae742, TypeM>, Enc_61f0b0 {
15542let Inst{7-5} = 0b001;
15543let Inst{13-13} = 0b0;
15544let Inst{31-21} = 0b11100110000;
15545let prefersSlot3 = 1;
15546let Constraints = "$Rxx32 = $Rxx32in";
15547}
15548def M2_mpyd_acc_lh_s1 : HInst<
15549(outs DoubleRegs:$Rxx32),
15550(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15551"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1",
15552tc_7f8ae742, TypeM>, Enc_61f0b0 {
15553let Inst{7-5} = 0b001;
15554let Inst{13-13} = 0b0;
15555let Inst{31-21} = 0b11100110100;
15556let prefersSlot3 = 1;
15557let Constraints = "$Rxx32 = $Rxx32in";
15558}
15559def M2_mpyd_acc_ll_s0 : HInst<
15560(outs DoubleRegs:$Rxx32),
15561(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15562"$Rxx32 += mpy($Rs32.l,$Rt32.l)",
15563tc_7f8ae742, TypeM>, Enc_61f0b0 {
15564let Inst{7-5} = 0b000;
15565let Inst{13-13} = 0b0;
15566let Inst{31-21} = 0b11100110000;
15567let prefersSlot3 = 1;
15568let Constraints = "$Rxx32 = $Rxx32in";
15569}
15570def M2_mpyd_acc_ll_s1 : HInst<
15571(outs DoubleRegs:$Rxx32),
15572(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15573"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1",
15574tc_7f8ae742, TypeM>, Enc_61f0b0 {
15575let Inst{7-5} = 0b000;
15576let Inst{13-13} = 0b0;
15577let Inst{31-21} = 0b11100110100;
15578let prefersSlot3 = 1;
15579let Constraints = "$Rxx32 = $Rxx32in";
15580}
15581def M2_mpyd_hh_s0 : HInst<
15582(outs DoubleRegs:$Rdd32),
15583(ins IntRegs:$Rs32, IntRegs:$Rt32),
15584"$Rdd32 = mpy($Rs32.h,$Rt32.h)",
15585tc_c21d7447, TypeM>, Enc_be32a5 {
15586let Inst{7-5} = 0b011;
15587let Inst{13-13} = 0b0;
15588let Inst{31-21} = 0b11100100000;
15589let prefersSlot3 = 1;
15590}
15591def M2_mpyd_hh_s1 : HInst<
15592(outs DoubleRegs:$Rdd32),
15593(ins IntRegs:$Rs32, IntRegs:$Rt32),
15594"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1",
15595tc_c21d7447, TypeM>, Enc_be32a5 {
15596let Inst{7-5} = 0b011;
15597let Inst{13-13} = 0b0;
15598let Inst{31-21} = 0b11100100100;
15599let prefersSlot3 = 1;
15600}
15601def M2_mpyd_hl_s0 : HInst<
15602(outs DoubleRegs:$Rdd32),
15603(ins IntRegs:$Rs32, IntRegs:$Rt32),
15604"$Rdd32 = mpy($Rs32.h,$Rt32.l)",
15605tc_c21d7447, TypeM>, Enc_be32a5 {
15606let Inst{7-5} = 0b010;
15607let Inst{13-13} = 0b0;
15608let Inst{31-21} = 0b11100100000;
15609let prefersSlot3 = 1;
15610}
15611def M2_mpyd_hl_s1 : HInst<
15612(outs DoubleRegs:$Rdd32),
15613(ins IntRegs:$Rs32, IntRegs:$Rt32),
15614"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1",
15615tc_c21d7447, TypeM>, Enc_be32a5 {
15616let Inst{7-5} = 0b010;
15617let Inst{13-13} = 0b0;
15618let Inst{31-21} = 0b11100100100;
15619let prefersSlot3 = 1;
15620}
15621def M2_mpyd_lh_s0 : HInst<
15622(outs DoubleRegs:$Rdd32),
15623(ins IntRegs:$Rs32, IntRegs:$Rt32),
15624"$Rdd32 = mpy($Rs32.l,$Rt32.h)",
15625tc_c21d7447, TypeM>, Enc_be32a5 {
15626let Inst{7-5} = 0b001;
15627let Inst{13-13} = 0b0;
15628let Inst{31-21} = 0b11100100000;
15629let prefersSlot3 = 1;
15630}
15631def M2_mpyd_lh_s1 : HInst<
15632(outs DoubleRegs:$Rdd32),
15633(ins IntRegs:$Rs32, IntRegs:$Rt32),
15634"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1",
15635tc_c21d7447, TypeM>, Enc_be32a5 {
15636let Inst{7-5} = 0b001;
15637let Inst{13-13} = 0b0;
15638let Inst{31-21} = 0b11100100100;
15639let prefersSlot3 = 1;
15640}
15641def M2_mpyd_ll_s0 : HInst<
15642(outs DoubleRegs:$Rdd32),
15643(ins IntRegs:$Rs32, IntRegs:$Rt32),
15644"$Rdd32 = mpy($Rs32.l,$Rt32.l)",
15645tc_c21d7447, TypeM>, Enc_be32a5 {
15646let Inst{7-5} = 0b000;
15647let Inst{13-13} = 0b0;
15648let Inst{31-21} = 0b11100100000;
15649let prefersSlot3 = 1;
15650}
15651def M2_mpyd_ll_s1 : HInst<
15652(outs DoubleRegs:$Rdd32),
15653(ins IntRegs:$Rs32, IntRegs:$Rt32),
15654"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1",
15655tc_c21d7447, TypeM>, Enc_be32a5 {
15656let Inst{7-5} = 0b000;
15657let Inst{13-13} = 0b0;
15658let Inst{31-21} = 0b11100100100;
15659let prefersSlot3 = 1;
15660}
15661def M2_mpyd_nac_hh_s0 : HInst<
15662(outs DoubleRegs:$Rxx32),
15663(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15664"$Rxx32 -= mpy($Rs32.h,$Rt32.h)",
15665tc_7f8ae742, TypeM>, Enc_61f0b0 {
15666let Inst{7-5} = 0b011;
15667let Inst{13-13} = 0b0;
15668let Inst{31-21} = 0b11100110001;
15669let prefersSlot3 = 1;
15670let Constraints = "$Rxx32 = $Rxx32in";
15671}
15672def M2_mpyd_nac_hh_s1 : HInst<
15673(outs DoubleRegs:$Rxx32),
15674(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15675"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1",
15676tc_7f8ae742, TypeM>, Enc_61f0b0 {
15677let Inst{7-5} = 0b011;
15678let Inst{13-13} = 0b0;
15679let Inst{31-21} = 0b11100110101;
15680let prefersSlot3 = 1;
15681let Constraints = "$Rxx32 = $Rxx32in";
15682}
15683def M2_mpyd_nac_hl_s0 : HInst<
15684(outs DoubleRegs:$Rxx32),
15685(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15686"$Rxx32 -= mpy($Rs32.h,$Rt32.l)",
15687tc_7f8ae742, TypeM>, Enc_61f0b0 {
15688let Inst{7-5} = 0b010;
15689let Inst{13-13} = 0b0;
15690let Inst{31-21} = 0b11100110001;
15691let prefersSlot3 = 1;
15692let Constraints = "$Rxx32 = $Rxx32in";
15693}
15694def M2_mpyd_nac_hl_s1 : HInst<
15695(outs DoubleRegs:$Rxx32),
15696(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15697"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1",
15698tc_7f8ae742, TypeM>, Enc_61f0b0 {
15699let Inst{7-5} = 0b010;
15700let Inst{13-13} = 0b0;
15701let Inst{31-21} = 0b11100110101;
15702let prefersSlot3 = 1;
15703let Constraints = "$Rxx32 = $Rxx32in";
15704}
15705def M2_mpyd_nac_lh_s0 : HInst<
15706(outs DoubleRegs:$Rxx32),
15707(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15708"$Rxx32 -= mpy($Rs32.l,$Rt32.h)",
15709tc_7f8ae742, TypeM>, Enc_61f0b0 {
15710let Inst{7-5} = 0b001;
15711let Inst{13-13} = 0b0;
15712let Inst{31-21} = 0b11100110001;
15713let prefersSlot3 = 1;
15714let Constraints = "$Rxx32 = $Rxx32in";
15715}
15716def M2_mpyd_nac_lh_s1 : HInst<
15717(outs DoubleRegs:$Rxx32),
15718(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15719"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1",
15720tc_7f8ae742, TypeM>, Enc_61f0b0 {
15721let Inst{7-5} = 0b001;
15722let Inst{13-13} = 0b0;
15723let Inst{31-21} = 0b11100110101;
15724let prefersSlot3 = 1;
15725let Constraints = "$Rxx32 = $Rxx32in";
15726}
15727def M2_mpyd_nac_ll_s0 : HInst<
15728(outs DoubleRegs:$Rxx32),
15729(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15730"$Rxx32 -= mpy($Rs32.l,$Rt32.l)",
15731tc_7f8ae742, TypeM>, Enc_61f0b0 {
15732let Inst{7-5} = 0b000;
15733let Inst{13-13} = 0b0;
15734let Inst{31-21} = 0b11100110001;
15735let prefersSlot3 = 1;
15736let Constraints = "$Rxx32 = $Rxx32in";
15737}
15738def M2_mpyd_nac_ll_s1 : HInst<
15739(outs DoubleRegs:$Rxx32),
15740(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15741"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1",
15742tc_7f8ae742, TypeM>, Enc_61f0b0 {
15743let Inst{7-5} = 0b000;
15744let Inst{13-13} = 0b0;
15745let Inst{31-21} = 0b11100110101;
15746let prefersSlot3 = 1;
15747let Constraints = "$Rxx32 = $Rxx32in";
15748}
15749def M2_mpyd_rnd_hh_s0 : HInst<
15750(outs DoubleRegs:$Rdd32),
15751(ins IntRegs:$Rs32, IntRegs:$Rt32),
15752"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd",
15753tc_c21d7447, TypeM>, Enc_be32a5 {
15754let Inst{7-5} = 0b011;
15755let Inst{13-13} = 0b0;
15756let Inst{31-21} = 0b11100100001;
15757let prefersSlot3 = 1;
15758}
15759def M2_mpyd_rnd_hh_s1 : HInst<
15760(outs DoubleRegs:$Rdd32),
15761(ins IntRegs:$Rs32, IntRegs:$Rt32),
15762"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd",
15763tc_c21d7447, TypeM>, Enc_be32a5 {
15764let Inst{7-5} = 0b011;
15765let Inst{13-13} = 0b0;
15766let Inst{31-21} = 0b11100100101;
15767let prefersSlot3 = 1;
15768}
15769def M2_mpyd_rnd_hl_s0 : HInst<
15770(outs DoubleRegs:$Rdd32),
15771(ins IntRegs:$Rs32, IntRegs:$Rt32),
15772"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd",
15773tc_c21d7447, TypeM>, Enc_be32a5 {
15774let Inst{7-5} = 0b010;
15775let Inst{13-13} = 0b0;
15776let Inst{31-21} = 0b11100100001;
15777let prefersSlot3 = 1;
15778}
15779def M2_mpyd_rnd_hl_s1 : HInst<
15780(outs DoubleRegs:$Rdd32),
15781(ins IntRegs:$Rs32, IntRegs:$Rt32),
15782"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd",
15783tc_c21d7447, TypeM>, Enc_be32a5 {
15784let Inst{7-5} = 0b010;
15785let Inst{13-13} = 0b0;
15786let Inst{31-21} = 0b11100100101;
15787let prefersSlot3 = 1;
15788}
15789def M2_mpyd_rnd_lh_s0 : HInst<
15790(outs DoubleRegs:$Rdd32),
15791(ins IntRegs:$Rs32, IntRegs:$Rt32),
15792"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd",
15793tc_c21d7447, TypeM>, Enc_be32a5 {
15794let Inst{7-5} = 0b001;
15795let Inst{13-13} = 0b0;
15796let Inst{31-21} = 0b11100100001;
15797let prefersSlot3 = 1;
15798}
15799def M2_mpyd_rnd_lh_s1 : HInst<
15800(outs DoubleRegs:$Rdd32),
15801(ins IntRegs:$Rs32, IntRegs:$Rt32),
15802"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd",
15803tc_c21d7447, TypeM>, Enc_be32a5 {
15804let Inst{7-5} = 0b001;
15805let Inst{13-13} = 0b0;
15806let Inst{31-21} = 0b11100100101;
15807let prefersSlot3 = 1;
15808}
15809def M2_mpyd_rnd_ll_s0 : HInst<
15810(outs DoubleRegs:$Rdd32),
15811(ins IntRegs:$Rs32, IntRegs:$Rt32),
15812"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd",
15813tc_c21d7447, TypeM>, Enc_be32a5 {
15814let Inst{7-5} = 0b000;
15815let Inst{13-13} = 0b0;
15816let Inst{31-21} = 0b11100100001;
15817let prefersSlot3 = 1;
15818}
15819def M2_mpyd_rnd_ll_s1 : HInst<
15820(outs DoubleRegs:$Rdd32),
15821(ins IntRegs:$Rs32, IntRegs:$Rt32),
15822"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd",
15823tc_c21d7447, TypeM>, Enc_be32a5 {
15824let Inst{7-5} = 0b000;
15825let Inst{13-13} = 0b0;
15826let Inst{31-21} = 0b11100100101;
15827let prefersSlot3 = 1;
15828}
15829def M2_mpyi : HInst<
15830(outs IntRegs:$Rd32),
15831(ins IntRegs:$Rs32, IntRegs:$Rt32),
15832"$Rd32 = mpyi($Rs32,$Rt32)",
15833tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel {
15834let Inst{7-5} = 0b000;
15835let Inst{13-13} = 0b0;
15836let Inst{31-21} = 0b11101101000;
15837let hasNewValue = 1;
15838let opNewValue = 0;
15839let prefersSlot3 = 1;
15840let CextOpcode = "M2_mpyi";
15841let InputType = "reg";
15842}
15843def M2_mpysin : HInst<
15844(outs IntRegs:$Rd32),
15845(ins IntRegs:$Rs32, u8_0Imm:$Ii),
15846"$Rd32 = -mpyi($Rs32,#$Ii)",
15847tc_38382228, TypeM>, Enc_b8c967 {
15848let Inst{13-13} = 0b0;
15849let Inst{31-21} = 0b11100000100;
15850let hasNewValue = 1;
15851let opNewValue = 0;
15852let prefersSlot3 = 1;
15853}
15854def M2_mpysip : HInst<
15855(outs IntRegs:$Rd32),
15856(ins IntRegs:$Rs32, u32_0Imm:$Ii),
15857"$Rd32 = +mpyi($Rs32,#$Ii)",
15858tc_38382228, TypeM>, Enc_b8c967 {
15859let Inst{13-13} = 0b0;
15860let Inst{31-21} = 0b11100000000;
15861let hasNewValue = 1;
15862let opNewValue = 0;
15863let prefersSlot3 = 1;
15864let isExtendable = 1;
15865let opExtendable = 2;
15866let isExtentSigned = 0;
15867let opExtentBits = 8;
15868let opExtentAlign = 0;
15869}
15870def M2_mpysmi : HInst<
15871(outs IntRegs:$Rd32),
15872(ins IntRegs:$Rs32, m32_0Imm:$Ii),
15873"$Rd32 = mpyi($Rs32,#$Ii)",
15874tc_38382228, TypeM>, ImmRegRel {
15875let hasNewValue = 1;
15876let opNewValue = 0;
15877let CextOpcode = "M2_mpyi";
15878let InputType = "imm";
15879let isPseudo = 1;
15880let isExtendable = 1;
15881let opExtendable = 2;
15882let isExtentSigned = 1;
15883let opExtentBits = 9;
15884let opExtentAlign = 0;
15885}
15886def M2_mpysu_up : HInst<
15887(outs IntRegs:$Rd32),
15888(ins IntRegs:$Rs32, IntRegs:$Rt32),
15889"$Rd32 = mpysu($Rs32,$Rt32)",
15890tc_c21d7447, TypeM>, Enc_5ab2be {
15891let Inst{7-5} = 0b001;
15892let Inst{13-13} = 0b0;
15893let Inst{31-21} = 0b11101101011;
15894let hasNewValue = 1;
15895let opNewValue = 0;
15896let prefersSlot3 = 1;
15897}
15898def M2_mpyu_acc_hh_s0 : HInst<
15899(outs IntRegs:$Rx32),
15900(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15901"$Rx32 += mpyu($Rs32.h,$Rt32.h)",
15902tc_7f8ae742, TypeM>, Enc_2ae154 {
15903let Inst{7-5} = 0b011;
15904let Inst{13-13} = 0b0;
15905let Inst{31-21} = 0b11101110010;
15906let hasNewValue = 1;
15907let opNewValue = 0;
15908let prefersSlot3 = 1;
15909let Constraints = "$Rx32 = $Rx32in";
15910}
15911def M2_mpyu_acc_hh_s1 : HInst<
15912(outs IntRegs:$Rx32),
15913(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15914"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1",
15915tc_7f8ae742, TypeM>, Enc_2ae154 {
15916let Inst{7-5} = 0b011;
15917let Inst{13-13} = 0b0;
15918let Inst{31-21} = 0b11101110110;
15919let hasNewValue = 1;
15920let opNewValue = 0;
15921let prefersSlot3 = 1;
15922let Constraints = "$Rx32 = $Rx32in";
15923}
15924def M2_mpyu_acc_hl_s0 : HInst<
15925(outs IntRegs:$Rx32),
15926(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15927"$Rx32 += mpyu($Rs32.h,$Rt32.l)",
15928tc_7f8ae742, TypeM>, Enc_2ae154 {
15929let Inst{7-5} = 0b010;
15930let Inst{13-13} = 0b0;
15931let Inst{31-21} = 0b11101110010;
15932let hasNewValue = 1;
15933let opNewValue = 0;
15934let prefersSlot3 = 1;
15935let Constraints = "$Rx32 = $Rx32in";
15936}
15937def M2_mpyu_acc_hl_s1 : HInst<
15938(outs IntRegs:$Rx32),
15939(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15940"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1",
15941tc_7f8ae742, TypeM>, Enc_2ae154 {
15942let Inst{7-5} = 0b010;
15943let Inst{13-13} = 0b0;
15944let Inst{31-21} = 0b11101110110;
15945let hasNewValue = 1;
15946let opNewValue = 0;
15947let prefersSlot3 = 1;
15948let Constraints = "$Rx32 = $Rx32in";
15949}
15950def M2_mpyu_acc_lh_s0 : HInst<
15951(outs IntRegs:$Rx32),
15952(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15953"$Rx32 += mpyu($Rs32.l,$Rt32.h)",
15954tc_7f8ae742, TypeM>, Enc_2ae154 {
15955let Inst{7-5} = 0b001;
15956let Inst{13-13} = 0b0;
15957let Inst{31-21} = 0b11101110010;
15958let hasNewValue = 1;
15959let opNewValue = 0;
15960let prefersSlot3 = 1;
15961let Constraints = "$Rx32 = $Rx32in";
15962}
15963def M2_mpyu_acc_lh_s1 : HInst<
15964(outs IntRegs:$Rx32),
15965(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15966"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1",
15967tc_7f8ae742, TypeM>, Enc_2ae154 {
15968let Inst{7-5} = 0b001;
15969let Inst{13-13} = 0b0;
15970let Inst{31-21} = 0b11101110110;
15971let hasNewValue = 1;
15972let opNewValue = 0;
15973let prefersSlot3 = 1;
15974let Constraints = "$Rx32 = $Rx32in";
15975}
15976def M2_mpyu_acc_ll_s0 : HInst<
15977(outs IntRegs:$Rx32),
15978(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15979"$Rx32 += mpyu($Rs32.l,$Rt32.l)",
15980tc_7f8ae742, TypeM>, Enc_2ae154 {
15981let Inst{7-5} = 0b000;
15982let Inst{13-13} = 0b0;
15983let Inst{31-21} = 0b11101110010;
15984let hasNewValue = 1;
15985let opNewValue = 0;
15986let prefersSlot3 = 1;
15987let Constraints = "$Rx32 = $Rx32in";
15988}
15989def M2_mpyu_acc_ll_s1 : HInst<
15990(outs IntRegs:$Rx32),
15991(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
15992"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1",
15993tc_7f8ae742, TypeM>, Enc_2ae154 {
15994let Inst{7-5} = 0b000;
15995let Inst{13-13} = 0b0;
15996let Inst{31-21} = 0b11101110110;
15997let hasNewValue = 1;
15998let opNewValue = 0;
15999let prefersSlot3 = 1;
16000let Constraints = "$Rx32 = $Rx32in";
16001}
16002def M2_mpyu_hh_s0 : HInst<
16003(outs IntRegs:$Rd32),
16004(ins IntRegs:$Rs32, IntRegs:$Rt32),
16005"$Rd32 = mpyu($Rs32.h,$Rt32.h)",
16006tc_c21d7447, TypeM>, Enc_5ab2be {
16007let Inst{7-5} = 0b011;
16008let Inst{13-13} = 0b0;
16009let Inst{31-21} = 0b11101100010;
16010let hasNewValue = 1;
16011let opNewValue = 0;
16012let prefersSlot3 = 1;
16013}
16014def M2_mpyu_hh_s1 : HInst<
16015(outs IntRegs:$Rd32),
16016(ins IntRegs:$Rs32, IntRegs:$Rt32),
16017"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16018tc_c21d7447, TypeM>, Enc_5ab2be {
16019let Inst{7-5} = 0b011;
16020let Inst{13-13} = 0b0;
16021let Inst{31-21} = 0b11101100110;
16022let hasNewValue = 1;
16023let opNewValue = 0;
16024let prefersSlot3 = 1;
16025}
16026def M2_mpyu_hl_s0 : HInst<
16027(outs IntRegs:$Rd32),
16028(ins IntRegs:$Rs32, IntRegs:$Rt32),
16029"$Rd32 = mpyu($Rs32.h,$Rt32.l)",
16030tc_c21d7447, TypeM>, Enc_5ab2be {
16031let Inst{7-5} = 0b010;
16032let Inst{13-13} = 0b0;
16033let Inst{31-21} = 0b11101100010;
16034let hasNewValue = 1;
16035let opNewValue = 0;
16036let prefersSlot3 = 1;
16037}
16038def M2_mpyu_hl_s1 : HInst<
16039(outs IntRegs:$Rd32),
16040(ins IntRegs:$Rs32, IntRegs:$Rt32),
16041"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16042tc_c21d7447, TypeM>, Enc_5ab2be {
16043let Inst{7-5} = 0b010;
16044let Inst{13-13} = 0b0;
16045let Inst{31-21} = 0b11101100110;
16046let hasNewValue = 1;
16047let opNewValue = 0;
16048let prefersSlot3 = 1;
16049}
16050def M2_mpyu_lh_s0 : HInst<
16051(outs IntRegs:$Rd32),
16052(ins IntRegs:$Rs32, IntRegs:$Rt32),
16053"$Rd32 = mpyu($Rs32.l,$Rt32.h)",
16054tc_c21d7447, TypeM>, Enc_5ab2be {
16055let Inst{7-5} = 0b001;
16056let Inst{13-13} = 0b0;
16057let Inst{31-21} = 0b11101100010;
16058let hasNewValue = 1;
16059let opNewValue = 0;
16060let prefersSlot3 = 1;
16061}
16062def M2_mpyu_lh_s1 : HInst<
16063(outs IntRegs:$Rd32),
16064(ins IntRegs:$Rs32, IntRegs:$Rt32),
16065"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16066tc_c21d7447, TypeM>, Enc_5ab2be {
16067let Inst{7-5} = 0b001;
16068let Inst{13-13} = 0b0;
16069let Inst{31-21} = 0b11101100110;
16070let hasNewValue = 1;
16071let opNewValue = 0;
16072let prefersSlot3 = 1;
16073}
16074def M2_mpyu_ll_s0 : HInst<
16075(outs IntRegs:$Rd32),
16076(ins IntRegs:$Rs32, IntRegs:$Rt32),
16077"$Rd32 = mpyu($Rs32.l,$Rt32.l)",
16078tc_c21d7447, TypeM>, Enc_5ab2be {
16079let Inst{7-5} = 0b000;
16080let Inst{13-13} = 0b0;
16081let Inst{31-21} = 0b11101100010;
16082let hasNewValue = 1;
16083let opNewValue = 0;
16084let prefersSlot3 = 1;
16085}
16086def M2_mpyu_ll_s1 : HInst<
16087(outs IntRegs:$Rd32),
16088(ins IntRegs:$Rs32, IntRegs:$Rt32),
16089"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16090tc_c21d7447, TypeM>, Enc_5ab2be {
16091let Inst{7-5} = 0b000;
16092let Inst{13-13} = 0b0;
16093let Inst{31-21} = 0b11101100110;
16094let hasNewValue = 1;
16095let opNewValue = 0;
16096let prefersSlot3 = 1;
16097}
16098def M2_mpyu_nac_hh_s0 : HInst<
16099(outs IntRegs:$Rx32),
16100(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16101"$Rx32 -= mpyu($Rs32.h,$Rt32.h)",
16102tc_7f8ae742, TypeM>, Enc_2ae154 {
16103let Inst{7-5} = 0b011;
16104let Inst{13-13} = 0b0;
16105let Inst{31-21} = 0b11101110011;
16106let hasNewValue = 1;
16107let opNewValue = 0;
16108let prefersSlot3 = 1;
16109let Constraints = "$Rx32 = $Rx32in";
16110}
16111def M2_mpyu_nac_hh_s1 : HInst<
16112(outs IntRegs:$Rx32),
16113(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16114"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16115tc_7f8ae742, TypeM>, Enc_2ae154 {
16116let Inst{7-5} = 0b011;
16117let Inst{13-13} = 0b0;
16118let Inst{31-21} = 0b11101110111;
16119let hasNewValue = 1;
16120let opNewValue = 0;
16121let prefersSlot3 = 1;
16122let Constraints = "$Rx32 = $Rx32in";
16123}
16124def M2_mpyu_nac_hl_s0 : HInst<
16125(outs IntRegs:$Rx32),
16126(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16127"$Rx32 -= mpyu($Rs32.h,$Rt32.l)",
16128tc_7f8ae742, TypeM>, Enc_2ae154 {
16129let Inst{7-5} = 0b010;
16130let Inst{13-13} = 0b0;
16131let Inst{31-21} = 0b11101110011;
16132let hasNewValue = 1;
16133let opNewValue = 0;
16134let prefersSlot3 = 1;
16135let Constraints = "$Rx32 = $Rx32in";
16136}
16137def M2_mpyu_nac_hl_s1 : HInst<
16138(outs IntRegs:$Rx32),
16139(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16140"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16141tc_7f8ae742, TypeM>, Enc_2ae154 {
16142let Inst{7-5} = 0b010;
16143let Inst{13-13} = 0b0;
16144let Inst{31-21} = 0b11101110111;
16145let hasNewValue = 1;
16146let opNewValue = 0;
16147let prefersSlot3 = 1;
16148let Constraints = "$Rx32 = $Rx32in";
16149}
16150def M2_mpyu_nac_lh_s0 : HInst<
16151(outs IntRegs:$Rx32),
16152(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16153"$Rx32 -= mpyu($Rs32.l,$Rt32.h)",
16154tc_7f8ae742, TypeM>, Enc_2ae154 {
16155let Inst{7-5} = 0b001;
16156let Inst{13-13} = 0b0;
16157let Inst{31-21} = 0b11101110011;
16158let hasNewValue = 1;
16159let opNewValue = 0;
16160let prefersSlot3 = 1;
16161let Constraints = "$Rx32 = $Rx32in";
16162}
16163def M2_mpyu_nac_lh_s1 : HInst<
16164(outs IntRegs:$Rx32),
16165(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16166"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16167tc_7f8ae742, TypeM>, Enc_2ae154 {
16168let Inst{7-5} = 0b001;
16169let Inst{13-13} = 0b0;
16170let Inst{31-21} = 0b11101110111;
16171let hasNewValue = 1;
16172let opNewValue = 0;
16173let prefersSlot3 = 1;
16174let Constraints = "$Rx32 = $Rx32in";
16175}
16176def M2_mpyu_nac_ll_s0 : HInst<
16177(outs IntRegs:$Rx32),
16178(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16179"$Rx32 -= mpyu($Rs32.l,$Rt32.l)",
16180tc_7f8ae742, TypeM>, Enc_2ae154 {
16181let Inst{7-5} = 0b000;
16182let Inst{13-13} = 0b0;
16183let Inst{31-21} = 0b11101110011;
16184let hasNewValue = 1;
16185let opNewValue = 0;
16186let prefersSlot3 = 1;
16187let Constraints = "$Rx32 = $Rx32in";
16188}
16189def M2_mpyu_nac_ll_s1 : HInst<
16190(outs IntRegs:$Rx32),
16191(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16192"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16193tc_7f8ae742, TypeM>, Enc_2ae154 {
16194let Inst{7-5} = 0b000;
16195let Inst{13-13} = 0b0;
16196let Inst{31-21} = 0b11101110111;
16197let hasNewValue = 1;
16198let opNewValue = 0;
16199let prefersSlot3 = 1;
16200let Constraints = "$Rx32 = $Rx32in";
16201}
16202def M2_mpyu_up : HInst<
16203(outs IntRegs:$Rd32),
16204(ins IntRegs:$Rs32, IntRegs:$Rt32),
16205"$Rd32 = mpyu($Rs32,$Rt32)",
16206tc_c21d7447, TypeM>, Enc_5ab2be {
16207let Inst{7-5} = 0b001;
16208let Inst{13-13} = 0b0;
16209let Inst{31-21} = 0b11101101010;
16210let hasNewValue = 1;
16211let opNewValue = 0;
16212let prefersSlot3 = 1;
16213}
16214def M2_mpyud_acc_hh_s0 : HInst<
16215(outs DoubleRegs:$Rxx32),
16216(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16217"$Rxx32 += mpyu($Rs32.h,$Rt32.h)",
16218tc_7f8ae742, TypeM>, Enc_61f0b0 {
16219let Inst{7-5} = 0b011;
16220let Inst{13-13} = 0b0;
16221let Inst{31-21} = 0b11100110010;
16222let prefersSlot3 = 1;
16223let Constraints = "$Rxx32 = $Rxx32in";
16224}
16225def M2_mpyud_acc_hh_s1 : HInst<
16226(outs DoubleRegs:$Rxx32),
16227(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16228"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1",
16229tc_7f8ae742, TypeM>, Enc_61f0b0 {
16230let Inst{7-5} = 0b011;
16231let Inst{13-13} = 0b0;
16232let Inst{31-21} = 0b11100110110;
16233let prefersSlot3 = 1;
16234let Constraints = "$Rxx32 = $Rxx32in";
16235}
16236def M2_mpyud_acc_hl_s0 : HInst<
16237(outs DoubleRegs:$Rxx32),
16238(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16239"$Rxx32 += mpyu($Rs32.h,$Rt32.l)",
16240tc_7f8ae742, TypeM>, Enc_61f0b0 {
16241let Inst{7-5} = 0b010;
16242let Inst{13-13} = 0b0;
16243let Inst{31-21} = 0b11100110010;
16244let prefersSlot3 = 1;
16245let Constraints = "$Rxx32 = $Rxx32in";
16246}
16247def M2_mpyud_acc_hl_s1 : HInst<
16248(outs DoubleRegs:$Rxx32),
16249(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16250"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1",
16251tc_7f8ae742, TypeM>, Enc_61f0b0 {
16252let Inst{7-5} = 0b010;
16253let Inst{13-13} = 0b0;
16254let Inst{31-21} = 0b11100110110;
16255let prefersSlot3 = 1;
16256let Constraints = "$Rxx32 = $Rxx32in";
16257}
16258def M2_mpyud_acc_lh_s0 : HInst<
16259(outs DoubleRegs:$Rxx32),
16260(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16261"$Rxx32 += mpyu($Rs32.l,$Rt32.h)",
16262tc_7f8ae742, TypeM>, Enc_61f0b0 {
16263let Inst{7-5} = 0b001;
16264let Inst{13-13} = 0b0;
16265let Inst{31-21} = 0b11100110010;
16266let prefersSlot3 = 1;
16267let Constraints = "$Rxx32 = $Rxx32in";
16268}
16269def M2_mpyud_acc_lh_s1 : HInst<
16270(outs DoubleRegs:$Rxx32),
16271(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16272"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1",
16273tc_7f8ae742, TypeM>, Enc_61f0b0 {
16274let Inst{7-5} = 0b001;
16275let Inst{13-13} = 0b0;
16276let Inst{31-21} = 0b11100110110;
16277let prefersSlot3 = 1;
16278let Constraints = "$Rxx32 = $Rxx32in";
16279}
16280def M2_mpyud_acc_ll_s0 : HInst<
16281(outs DoubleRegs:$Rxx32),
16282(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16283"$Rxx32 += mpyu($Rs32.l,$Rt32.l)",
16284tc_7f8ae742, TypeM>, Enc_61f0b0 {
16285let Inst{7-5} = 0b000;
16286let Inst{13-13} = 0b0;
16287let Inst{31-21} = 0b11100110010;
16288let prefersSlot3 = 1;
16289let Constraints = "$Rxx32 = $Rxx32in";
16290}
16291def M2_mpyud_acc_ll_s1 : HInst<
16292(outs DoubleRegs:$Rxx32),
16293(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16294"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1",
16295tc_7f8ae742, TypeM>, Enc_61f0b0 {
16296let Inst{7-5} = 0b000;
16297let Inst{13-13} = 0b0;
16298let Inst{31-21} = 0b11100110110;
16299let prefersSlot3 = 1;
16300let Constraints = "$Rxx32 = $Rxx32in";
16301}
16302def M2_mpyud_hh_s0 : HInst<
16303(outs DoubleRegs:$Rdd32),
16304(ins IntRegs:$Rs32, IntRegs:$Rt32),
16305"$Rdd32 = mpyu($Rs32.h,$Rt32.h)",
16306tc_c21d7447, TypeM>, Enc_be32a5 {
16307let Inst{7-5} = 0b011;
16308let Inst{13-13} = 0b0;
16309let Inst{31-21} = 0b11100100010;
16310let prefersSlot3 = 1;
16311}
16312def M2_mpyud_hh_s1 : HInst<
16313(outs DoubleRegs:$Rdd32),
16314(ins IntRegs:$Rs32, IntRegs:$Rt32),
16315"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1",
16316tc_c21d7447, TypeM>, Enc_be32a5 {
16317let Inst{7-5} = 0b011;
16318let Inst{13-13} = 0b0;
16319let Inst{31-21} = 0b11100100110;
16320let prefersSlot3 = 1;
16321}
16322def M2_mpyud_hl_s0 : HInst<
16323(outs DoubleRegs:$Rdd32),
16324(ins IntRegs:$Rs32, IntRegs:$Rt32),
16325"$Rdd32 = mpyu($Rs32.h,$Rt32.l)",
16326tc_c21d7447, TypeM>, Enc_be32a5 {
16327let Inst{7-5} = 0b010;
16328let Inst{13-13} = 0b0;
16329let Inst{31-21} = 0b11100100010;
16330let prefersSlot3 = 1;
16331}
16332def M2_mpyud_hl_s1 : HInst<
16333(outs DoubleRegs:$Rdd32),
16334(ins IntRegs:$Rs32, IntRegs:$Rt32),
16335"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1",
16336tc_c21d7447, TypeM>, Enc_be32a5 {
16337let Inst{7-5} = 0b010;
16338let Inst{13-13} = 0b0;
16339let Inst{31-21} = 0b11100100110;
16340let prefersSlot3 = 1;
16341}
16342def M2_mpyud_lh_s0 : HInst<
16343(outs DoubleRegs:$Rdd32),
16344(ins IntRegs:$Rs32, IntRegs:$Rt32),
16345"$Rdd32 = mpyu($Rs32.l,$Rt32.h)",
16346tc_c21d7447, TypeM>, Enc_be32a5 {
16347let Inst{7-5} = 0b001;
16348let Inst{13-13} = 0b0;
16349let Inst{31-21} = 0b11100100010;
16350let prefersSlot3 = 1;
16351}
16352def M2_mpyud_lh_s1 : HInst<
16353(outs DoubleRegs:$Rdd32),
16354(ins IntRegs:$Rs32, IntRegs:$Rt32),
16355"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1",
16356tc_c21d7447, TypeM>, Enc_be32a5 {
16357let Inst{7-5} = 0b001;
16358let Inst{13-13} = 0b0;
16359let Inst{31-21} = 0b11100100110;
16360let prefersSlot3 = 1;
16361}
16362def M2_mpyud_ll_s0 : HInst<
16363(outs DoubleRegs:$Rdd32),
16364(ins IntRegs:$Rs32, IntRegs:$Rt32),
16365"$Rdd32 = mpyu($Rs32.l,$Rt32.l)",
16366tc_c21d7447, TypeM>, Enc_be32a5 {
16367let Inst{7-5} = 0b000;
16368let Inst{13-13} = 0b0;
16369let Inst{31-21} = 0b11100100010;
16370let prefersSlot3 = 1;
16371}
16372def M2_mpyud_ll_s1 : HInst<
16373(outs DoubleRegs:$Rdd32),
16374(ins IntRegs:$Rs32, IntRegs:$Rt32),
16375"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1",
16376tc_c21d7447, TypeM>, Enc_be32a5 {
16377let Inst{7-5} = 0b000;
16378let Inst{13-13} = 0b0;
16379let Inst{31-21} = 0b11100100110;
16380let prefersSlot3 = 1;
16381}
16382def M2_mpyud_nac_hh_s0 : HInst<
16383(outs DoubleRegs:$Rxx32),
16384(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16385"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)",
16386tc_7f8ae742, TypeM>, Enc_61f0b0 {
16387let Inst{7-5} = 0b011;
16388let Inst{13-13} = 0b0;
16389let Inst{31-21} = 0b11100110011;
16390let prefersSlot3 = 1;
16391let Constraints = "$Rxx32 = $Rxx32in";
16392}
16393def M2_mpyud_nac_hh_s1 : HInst<
16394(outs DoubleRegs:$Rxx32),
16395(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16396"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1",
16397tc_7f8ae742, TypeM>, Enc_61f0b0 {
16398let Inst{7-5} = 0b011;
16399let Inst{13-13} = 0b0;
16400let Inst{31-21} = 0b11100110111;
16401let prefersSlot3 = 1;
16402let Constraints = "$Rxx32 = $Rxx32in";
16403}
16404def M2_mpyud_nac_hl_s0 : HInst<
16405(outs DoubleRegs:$Rxx32),
16406(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16407"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)",
16408tc_7f8ae742, TypeM>, Enc_61f0b0 {
16409let Inst{7-5} = 0b010;
16410let Inst{13-13} = 0b0;
16411let Inst{31-21} = 0b11100110011;
16412let prefersSlot3 = 1;
16413let Constraints = "$Rxx32 = $Rxx32in";
16414}
16415def M2_mpyud_nac_hl_s1 : HInst<
16416(outs DoubleRegs:$Rxx32),
16417(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16418"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1",
16419tc_7f8ae742, TypeM>, Enc_61f0b0 {
16420let Inst{7-5} = 0b010;
16421let Inst{13-13} = 0b0;
16422let Inst{31-21} = 0b11100110111;
16423let prefersSlot3 = 1;
16424let Constraints = "$Rxx32 = $Rxx32in";
16425}
16426def M2_mpyud_nac_lh_s0 : HInst<
16427(outs DoubleRegs:$Rxx32),
16428(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16429"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)",
16430tc_7f8ae742, TypeM>, Enc_61f0b0 {
16431let Inst{7-5} = 0b001;
16432let Inst{13-13} = 0b0;
16433let Inst{31-21} = 0b11100110011;
16434let prefersSlot3 = 1;
16435let Constraints = "$Rxx32 = $Rxx32in";
16436}
16437def M2_mpyud_nac_lh_s1 : HInst<
16438(outs DoubleRegs:$Rxx32),
16439(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16440"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1",
16441tc_7f8ae742, TypeM>, Enc_61f0b0 {
16442let Inst{7-5} = 0b001;
16443let Inst{13-13} = 0b0;
16444let Inst{31-21} = 0b11100110111;
16445let prefersSlot3 = 1;
16446let Constraints = "$Rxx32 = $Rxx32in";
16447}
16448def M2_mpyud_nac_ll_s0 : HInst<
16449(outs DoubleRegs:$Rxx32),
16450(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16451"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)",
16452tc_7f8ae742, TypeM>, Enc_61f0b0 {
16453let Inst{7-5} = 0b000;
16454let Inst{13-13} = 0b0;
16455let Inst{31-21} = 0b11100110011;
16456let prefersSlot3 = 1;
16457let Constraints = "$Rxx32 = $Rxx32in";
16458}
16459def M2_mpyud_nac_ll_s1 : HInst<
16460(outs DoubleRegs:$Rxx32),
16461(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16462"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1",
16463tc_7f8ae742, TypeM>, Enc_61f0b0 {
16464let Inst{7-5} = 0b000;
16465let Inst{13-13} = 0b0;
16466let Inst{31-21} = 0b11100110111;
16467let prefersSlot3 = 1;
16468let Constraints = "$Rxx32 = $Rxx32in";
16469}
16470def M2_mpyui : HInst<
16471(outs IntRegs:$Rd32),
16472(ins IntRegs:$Rs32, IntRegs:$Rt32),
16473"$Rd32 = mpyui($Rs32,$Rt32)",
16474tc_c21d7447, TypeM> {
16475let hasNewValue = 1;
16476let opNewValue = 0;
16477let isPseudo = 1;
16478let isCodeGenOnly = 1;
16479}
16480def M2_nacci : HInst<
16481(outs IntRegs:$Rx32),
16482(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16483"$Rx32 -= add($Rs32,$Rt32)",
16484tc_2c13e7f5, TypeM>, Enc_2ae154 {
16485let Inst{7-5} = 0b001;
16486let Inst{13-13} = 0b0;
16487let Inst{31-21} = 0b11101111100;
16488let hasNewValue = 1;
16489let opNewValue = 0;
16490let prefersSlot3 = 1;
16491let InputType = "reg";
16492let Constraints = "$Rx32 = $Rx32in";
16493}
16494def M2_naccii : HInst<
16495(outs IntRegs:$Rx32),
16496(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
16497"$Rx32 -= add($Rs32,#$Ii)",
16498tc_2c13e7f5, TypeM>, Enc_c90aca {
16499let Inst{13-13} = 0b0;
16500let Inst{31-21} = 0b11100010100;
16501let hasNewValue = 1;
16502let opNewValue = 0;
16503let prefersSlot3 = 1;
16504let InputType = "imm";
16505let isExtendable = 1;
16506let opExtendable = 3;
16507let isExtentSigned = 1;
16508let opExtentBits = 8;
16509let opExtentAlign = 0;
16510let Constraints = "$Rx32 = $Rx32in";
16511}
16512def M2_subacc : HInst<
16513(outs IntRegs:$Rx32),
16514(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32),
16515"$Rx32 += sub($Rt32,$Rs32)",
16516tc_2c13e7f5, TypeM>, Enc_a568d4 {
16517let Inst{7-5} = 0b011;
16518let Inst{13-13} = 0b0;
16519let Inst{31-21} = 0b11101111000;
16520let hasNewValue = 1;
16521let opNewValue = 0;
16522let prefersSlot3 = 1;
16523let InputType = "reg";
16524let Constraints = "$Rx32 = $Rx32in";
16525}
16526def M2_vabsdiffh : HInst<
16527(outs DoubleRegs:$Rdd32),
16528(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16529"$Rdd32 = vabsdiffh($Rtt32,$Rss32)",
16530tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16531let Inst{7-5} = 0b000;
16532let Inst{13-13} = 0b0;
16533let Inst{31-21} = 0b11101000011;
16534let prefersSlot3 = 1;
16535}
16536def M2_vabsdiffw : HInst<
16537(outs DoubleRegs:$Rdd32),
16538(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
16539"$Rdd32 = vabsdiffw($Rtt32,$Rss32)",
16540tc_0dfac0a7, TypeM>, Enc_ea23e4 {
16541let Inst{7-5} = 0b000;
16542let Inst{13-13} = 0b0;
16543let Inst{31-21} = 0b11101000001;
16544let prefersSlot3 = 1;
16545}
16546def M2_vcmac_s0_sat_i : HInst<
16547(outs DoubleRegs:$Rxx32),
16548(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16549"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat",
16550tc_7f8ae742, TypeM>, Enc_88c16c {
16551let Inst{7-5} = 0b100;
16552let Inst{13-13} = 0b0;
16553let Inst{31-21} = 0b11101010010;
16554let prefersSlot3 = 1;
16555let Defs = [USR_OVF];
16556let Constraints = "$Rxx32 = $Rxx32in";
16557}
16558def M2_vcmac_s0_sat_r : HInst<
16559(outs DoubleRegs:$Rxx32),
16560(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16561"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat",
16562tc_7f8ae742, TypeM>, Enc_88c16c {
16563let Inst{7-5} = 0b100;
16564let Inst{13-13} = 0b0;
16565let Inst{31-21} = 0b11101010001;
16566let prefersSlot3 = 1;
16567let Defs = [USR_OVF];
16568let Constraints = "$Rxx32 = $Rxx32in";
16569}
16570def M2_vcmpy_s0_sat_i : HInst<
16571(outs DoubleRegs:$Rdd32),
16572(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16573"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat",
16574tc_c21d7447, TypeM>, Enc_a56825 {
16575let Inst{7-5} = 0b110;
16576let Inst{13-13} = 0b0;
16577let Inst{31-21} = 0b11101000010;
16578let prefersSlot3 = 1;
16579let Defs = [USR_OVF];
16580}
16581def M2_vcmpy_s0_sat_r : HInst<
16582(outs DoubleRegs:$Rdd32),
16583(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16584"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat",
16585tc_c21d7447, TypeM>, Enc_a56825 {
16586let Inst{7-5} = 0b110;
16587let Inst{13-13} = 0b0;
16588let Inst{31-21} = 0b11101000001;
16589let prefersSlot3 = 1;
16590let Defs = [USR_OVF];
16591}
16592def M2_vcmpy_s1_sat_i : HInst<
16593(outs DoubleRegs:$Rdd32),
16594(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16595"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat",
16596tc_c21d7447, TypeM>, Enc_a56825 {
16597let Inst{7-5} = 0b110;
16598let Inst{13-13} = 0b0;
16599let Inst{31-21} = 0b11101000110;
16600let prefersSlot3 = 1;
16601let Defs = [USR_OVF];
16602}
16603def M2_vcmpy_s1_sat_r : HInst<
16604(outs DoubleRegs:$Rdd32),
16605(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16606"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat",
16607tc_c21d7447, TypeM>, Enc_a56825 {
16608let Inst{7-5} = 0b110;
16609let Inst{13-13} = 0b0;
16610let Inst{31-21} = 0b11101000101;
16611let prefersSlot3 = 1;
16612let Defs = [USR_OVF];
16613}
16614def M2_vdmacs_s0 : HInst<
16615(outs DoubleRegs:$Rxx32),
16616(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16617"$Rxx32 += vdmpy($Rss32,$Rtt32):sat",
16618tc_7f8ae742, TypeM>, Enc_88c16c {
16619let Inst{7-5} = 0b100;
16620let Inst{13-13} = 0b0;
16621let Inst{31-21} = 0b11101010000;
16622let prefersSlot3 = 1;
16623let Defs = [USR_OVF];
16624let Constraints = "$Rxx32 = $Rxx32in";
16625}
16626def M2_vdmacs_s1 : HInst<
16627(outs DoubleRegs:$Rxx32),
16628(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16629"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat",
16630tc_7f8ae742, TypeM>, Enc_88c16c {
16631let Inst{7-5} = 0b100;
16632let Inst{13-13} = 0b0;
16633let Inst{31-21} = 0b11101010100;
16634let prefersSlot3 = 1;
16635let Defs = [USR_OVF];
16636let Constraints = "$Rxx32 = $Rxx32in";
16637}
16638def M2_vdmpyrs_s0 : HInst<
16639(outs IntRegs:$Rd32),
16640(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16641"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat",
16642tc_c21d7447, TypeM>, Enc_d2216a {
16643let Inst{7-5} = 0b000;
16644let Inst{13-13} = 0b0;
16645let Inst{31-21} = 0b11101001000;
16646let hasNewValue = 1;
16647let opNewValue = 0;
16648let prefersSlot3 = 1;
16649let Defs = [USR_OVF];
16650}
16651def M2_vdmpyrs_s1 : HInst<
16652(outs IntRegs:$Rd32),
16653(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16654"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat",
16655tc_c21d7447, TypeM>, Enc_d2216a {
16656let Inst{7-5} = 0b000;
16657let Inst{13-13} = 0b0;
16658let Inst{31-21} = 0b11101001100;
16659let hasNewValue = 1;
16660let opNewValue = 0;
16661let prefersSlot3 = 1;
16662let Defs = [USR_OVF];
16663}
16664def M2_vdmpys_s0 : HInst<
16665(outs DoubleRegs:$Rdd32),
16666(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16667"$Rdd32 = vdmpy($Rss32,$Rtt32):sat",
16668tc_c21d7447, TypeM>, Enc_a56825 {
16669let Inst{7-5} = 0b100;
16670let Inst{13-13} = 0b0;
16671let Inst{31-21} = 0b11101000000;
16672let prefersSlot3 = 1;
16673let Defs = [USR_OVF];
16674}
16675def M2_vdmpys_s1 : HInst<
16676(outs DoubleRegs:$Rdd32),
16677(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16678"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat",
16679tc_c21d7447, TypeM>, Enc_a56825 {
16680let Inst{7-5} = 0b100;
16681let Inst{13-13} = 0b0;
16682let Inst{31-21} = 0b11101000100;
16683let prefersSlot3 = 1;
16684let Defs = [USR_OVF];
16685}
16686def M2_vmac2 : HInst<
16687(outs DoubleRegs:$Rxx32),
16688(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16689"$Rxx32 += vmpyh($Rs32,$Rt32)",
16690tc_7f8ae742, TypeM>, Enc_61f0b0 {
16691let Inst{7-5} = 0b001;
16692let Inst{13-13} = 0b0;
16693let Inst{31-21} = 0b11100111001;
16694let prefersSlot3 = 1;
16695let Constraints = "$Rxx32 = $Rxx32in";
16696}
16697def M2_vmac2es : HInst<
16698(outs DoubleRegs:$Rxx32),
16699(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16700"$Rxx32 += vmpyeh($Rss32,$Rtt32)",
16701tc_7f8ae742, TypeM>, Enc_88c16c {
16702let Inst{7-5} = 0b010;
16703let Inst{13-13} = 0b0;
16704let Inst{31-21} = 0b11101010001;
16705let prefersSlot3 = 1;
16706let Constraints = "$Rxx32 = $Rxx32in";
16707}
16708def M2_vmac2es_s0 : HInst<
16709(outs DoubleRegs:$Rxx32),
16710(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16711"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat",
16712tc_7f8ae742, TypeM>, Enc_88c16c {
16713let Inst{7-5} = 0b110;
16714let Inst{13-13} = 0b0;
16715let Inst{31-21} = 0b11101010000;
16716let prefersSlot3 = 1;
16717let Defs = [USR_OVF];
16718let Constraints = "$Rxx32 = $Rxx32in";
16719}
16720def M2_vmac2es_s1 : HInst<
16721(outs DoubleRegs:$Rxx32),
16722(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16723"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat",
16724tc_7f8ae742, TypeM>, Enc_88c16c {
16725let Inst{7-5} = 0b110;
16726let Inst{13-13} = 0b0;
16727let Inst{31-21} = 0b11101010100;
16728let prefersSlot3 = 1;
16729let Defs = [USR_OVF];
16730let Constraints = "$Rxx32 = $Rxx32in";
16731}
16732def M2_vmac2s_s0 : HInst<
16733(outs DoubleRegs:$Rxx32),
16734(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16735"$Rxx32 += vmpyh($Rs32,$Rt32):sat",
16736tc_7f8ae742, TypeM>, Enc_61f0b0 {
16737let Inst{7-5} = 0b101;
16738let Inst{13-13} = 0b0;
16739let Inst{31-21} = 0b11100111000;
16740let prefersSlot3 = 1;
16741let Defs = [USR_OVF];
16742let Constraints = "$Rxx32 = $Rxx32in";
16743}
16744def M2_vmac2s_s1 : HInst<
16745(outs DoubleRegs:$Rxx32),
16746(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16747"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat",
16748tc_7f8ae742, TypeM>, Enc_61f0b0 {
16749let Inst{7-5} = 0b101;
16750let Inst{13-13} = 0b0;
16751let Inst{31-21} = 0b11100111100;
16752let prefersSlot3 = 1;
16753let Defs = [USR_OVF];
16754let Constraints = "$Rxx32 = $Rxx32in";
16755}
16756def M2_vmac2su_s0 : HInst<
16757(outs DoubleRegs:$Rxx32),
16758(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16759"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat",
16760tc_7f8ae742, TypeM>, Enc_61f0b0 {
16761let Inst{7-5} = 0b101;
16762let Inst{13-13} = 0b0;
16763let Inst{31-21} = 0b11100111011;
16764let prefersSlot3 = 1;
16765let Defs = [USR_OVF];
16766let Constraints = "$Rxx32 = $Rxx32in";
16767}
16768def M2_vmac2su_s1 : HInst<
16769(outs DoubleRegs:$Rxx32),
16770(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
16771"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat",
16772tc_7f8ae742, TypeM>, Enc_61f0b0 {
16773let Inst{7-5} = 0b101;
16774let Inst{13-13} = 0b0;
16775let Inst{31-21} = 0b11100111111;
16776let prefersSlot3 = 1;
16777let Defs = [USR_OVF];
16778let Constraints = "$Rxx32 = $Rxx32in";
16779}
16780def M2_vmpy2es_s0 : HInst<
16781(outs DoubleRegs:$Rdd32),
16782(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16783"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat",
16784tc_c21d7447, TypeM>, Enc_a56825 {
16785let Inst{7-5} = 0b110;
16786let Inst{13-13} = 0b0;
16787let Inst{31-21} = 0b11101000000;
16788let prefersSlot3 = 1;
16789let Defs = [USR_OVF];
16790}
16791def M2_vmpy2es_s1 : HInst<
16792(outs DoubleRegs:$Rdd32),
16793(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16794"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat",
16795tc_c21d7447, TypeM>, Enc_a56825 {
16796let Inst{7-5} = 0b110;
16797let Inst{13-13} = 0b0;
16798let Inst{31-21} = 0b11101000100;
16799let prefersSlot3 = 1;
16800let Defs = [USR_OVF];
16801}
16802def M2_vmpy2s_s0 : HInst<
16803(outs DoubleRegs:$Rdd32),
16804(ins IntRegs:$Rs32, IntRegs:$Rt32),
16805"$Rdd32 = vmpyh($Rs32,$Rt32):sat",
16806tc_c21d7447, TypeM>, Enc_be32a5 {
16807let Inst{7-5} = 0b101;
16808let Inst{13-13} = 0b0;
16809let Inst{31-21} = 0b11100101000;
16810let prefersSlot3 = 1;
16811let Defs = [USR_OVF];
16812}
16813def M2_vmpy2s_s0pack : HInst<
16814(outs IntRegs:$Rd32),
16815(ins IntRegs:$Rs32, IntRegs:$Rt32),
16816"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat",
16817tc_c21d7447, TypeM>, Enc_5ab2be {
16818let Inst{7-5} = 0b111;
16819let Inst{13-13} = 0b0;
16820let Inst{31-21} = 0b11101101001;
16821let hasNewValue = 1;
16822let opNewValue = 0;
16823let prefersSlot3 = 1;
16824let Defs = [USR_OVF];
16825}
16826def M2_vmpy2s_s1 : HInst<
16827(outs DoubleRegs:$Rdd32),
16828(ins IntRegs:$Rs32, IntRegs:$Rt32),
16829"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat",
16830tc_c21d7447, TypeM>, Enc_be32a5 {
16831let Inst{7-5} = 0b101;
16832let Inst{13-13} = 0b0;
16833let Inst{31-21} = 0b11100101100;
16834let prefersSlot3 = 1;
16835let Defs = [USR_OVF];
16836}
16837def M2_vmpy2s_s1pack : HInst<
16838(outs IntRegs:$Rd32),
16839(ins IntRegs:$Rs32, IntRegs:$Rt32),
16840"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat",
16841tc_c21d7447, TypeM>, Enc_5ab2be {
16842let Inst{7-5} = 0b111;
16843let Inst{13-13} = 0b0;
16844let Inst{31-21} = 0b11101101101;
16845let hasNewValue = 1;
16846let opNewValue = 0;
16847let prefersSlot3 = 1;
16848let Defs = [USR_OVF];
16849}
16850def M2_vmpy2su_s0 : HInst<
16851(outs DoubleRegs:$Rdd32),
16852(ins IntRegs:$Rs32, IntRegs:$Rt32),
16853"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat",
16854tc_c21d7447, TypeM>, Enc_be32a5 {
16855let Inst{7-5} = 0b111;
16856let Inst{13-13} = 0b0;
16857let Inst{31-21} = 0b11100101000;
16858let prefersSlot3 = 1;
16859let Defs = [USR_OVF];
16860}
16861def M2_vmpy2su_s1 : HInst<
16862(outs DoubleRegs:$Rdd32),
16863(ins IntRegs:$Rs32, IntRegs:$Rt32),
16864"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat",
16865tc_c21d7447, TypeM>, Enc_be32a5 {
16866let Inst{7-5} = 0b111;
16867let Inst{13-13} = 0b0;
16868let Inst{31-21} = 0b11100101100;
16869let prefersSlot3 = 1;
16870let Defs = [USR_OVF];
16871}
16872def M2_vraddh : HInst<
16873(outs IntRegs:$Rd32),
16874(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16875"$Rd32 = vraddh($Rss32,$Rtt32)",
16876tc_c21d7447, TypeM>, Enc_d2216a {
16877let Inst{7-5} = 0b111;
16878let Inst{13-13} = 0b0;
16879let Inst{31-21} = 0b11101001001;
16880let hasNewValue = 1;
16881let opNewValue = 0;
16882let prefersSlot3 = 1;
16883}
16884def M2_vradduh : HInst<
16885(outs IntRegs:$Rd32),
16886(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16887"$Rd32 = vradduh($Rss32,$Rtt32)",
16888tc_c21d7447, TypeM>, Enc_d2216a {
16889let Inst{7-5} = 0b001;
16890let Inst{13-13} = 0b0;
16891let Inst{31-21} = 0b11101001000;
16892let hasNewValue = 1;
16893let opNewValue = 0;
16894let prefersSlot3 = 1;
16895}
16896def M2_vrcmaci_s0 : HInst<
16897(outs DoubleRegs:$Rxx32),
16898(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16899"$Rxx32 += vrcmpyi($Rss32,$Rtt32)",
16900tc_7f8ae742, TypeM>, Enc_88c16c {
16901let Inst{7-5} = 0b000;
16902let Inst{13-13} = 0b0;
16903let Inst{31-21} = 0b11101010000;
16904let prefersSlot3 = 1;
16905let Constraints = "$Rxx32 = $Rxx32in";
16906}
16907def M2_vrcmaci_s0c : HInst<
16908(outs DoubleRegs:$Rxx32),
16909(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16910"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)",
16911tc_7f8ae742, TypeM>, Enc_88c16c {
16912let Inst{7-5} = 0b000;
16913let Inst{13-13} = 0b0;
16914let Inst{31-21} = 0b11101010010;
16915let prefersSlot3 = 1;
16916let Constraints = "$Rxx32 = $Rxx32in";
16917}
16918def M2_vrcmacr_s0 : HInst<
16919(outs DoubleRegs:$Rxx32),
16920(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16921"$Rxx32 += vrcmpyr($Rss32,$Rtt32)",
16922tc_7f8ae742, TypeM>, Enc_88c16c {
16923let Inst{7-5} = 0b001;
16924let Inst{13-13} = 0b0;
16925let Inst{31-21} = 0b11101010000;
16926let prefersSlot3 = 1;
16927let Constraints = "$Rxx32 = $Rxx32in";
16928}
16929def M2_vrcmacr_s0c : HInst<
16930(outs DoubleRegs:$Rxx32),
16931(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16932"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)",
16933tc_7f8ae742, TypeM>, Enc_88c16c {
16934let Inst{7-5} = 0b001;
16935let Inst{13-13} = 0b0;
16936let Inst{31-21} = 0b11101010011;
16937let prefersSlot3 = 1;
16938let Constraints = "$Rxx32 = $Rxx32in";
16939}
16940def M2_vrcmpyi_s0 : HInst<
16941(outs DoubleRegs:$Rdd32),
16942(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16943"$Rdd32 = vrcmpyi($Rss32,$Rtt32)",
16944tc_c21d7447, TypeM>, Enc_a56825 {
16945let Inst{7-5} = 0b000;
16946let Inst{13-13} = 0b0;
16947let Inst{31-21} = 0b11101000000;
16948let prefersSlot3 = 1;
16949}
16950def M2_vrcmpyi_s0c : HInst<
16951(outs DoubleRegs:$Rdd32),
16952(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16953"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)",
16954tc_c21d7447, TypeM>, Enc_a56825 {
16955let Inst{7-5} = 0b000;
16956let Inst{13-13} = 0b0;
16957let Inst{31-21} = 0b11101000010;
16958let prefersSlot3 = 1;
16959}
16960def M2_vrcmpyr_s0 : HInst<
16961(outs DoubleRegs:$Rdd32),
16962(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16963"$Rdd32 = vrcmpyr($Rss32,$Rtt32)",
16964tc_c21d7447, TypeM>, Enc_a56825 {
16965let Inst{7-5} = 0b001;
16966let Inst{13-13} = 0b0;
16967let Inst{31-21} = 0b11101000000;
16968let prefersSlot3 = 1;
16969}
16970def M2_vrcmpyr_s0c : HInst<
16971(outs DoubleRegs:$Rdd32),
16972(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16973"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)",
16974tc_c21d7447, TypeM>, Enc_a56825 {
16975let Inst{7-5} = 0b001;
16976let Inst{13-13} = 0b0;
16977let Inst{31-21} = 0b11101000011;
16978let prefersSlot3 = 1;
16979}
16980def M2_vrcmpys_acc_s1 : HInst<
16981(outs DoubleRegs:$Rxx32),
16982(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
16983"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat",
16984tc_7f8ae742, TypeM> {
16985let isPseudo = 1;
16986let Constraints = "$Rxx32 = $Rxx32in";
16987}
16988def M2_vrcmpys_acc_s1_h : HInst<
16989(outs DoubleRegs:$Rxx32),
16990(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
16991"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
16992tc_7f8ae742, TypeM>, Enc_88c16c {
16993let Inst{7-5} = 0b100;
16994let Inst{13-13} = 0b0;
16995let Inst{31-21} = 0b11101010101;
16996let prefersSlot3 = 1;
16997let Defs = [USR_OVF];
16998let Constraints = "$Rxx32 = $Rxx32in";
16999}
17000def M2_vrcmpys_acc_s1_l : HInst<
17001(outs DoubleRegs:$Rxx32),
17002(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17003"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17004tc_7f8ae742, TypeM>, Enc_88c16c {
17005let Inst{7-5} = 0b100;
17006let Inst{13-13} = 0b0;
17007let Inst{31-21} = 0b11101010111;
17008let prefersSlot3 = 1;
17009let Defs = [USR_OVF];
17010let Constraints = "$Rxx32 = $Rxx32in";
17011}
17012def M2_vrcmpys_s1 : HInst<
17013(outs DoubleRegs:$Rdd32),
17014(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17015"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat",
17016tc_c21d7447, TypeM> {
17017let isPseudo = 1;
17018}
17019def M2_vrcmpys_s1_h : HInst<
17020(outs DoubleRegs:$Rdd32),
17021(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17022"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi",
17023tc_c21d7447, TypeM>, Enc_a56825 {
17024let Inst{7-5} = 0b100;
17025let Inst{13-13} = 0b0;
17026let Inst{31-21} = 0b11101000101;
17027let prefersSlot3 = 1;
17028let Defs = [USR_OVF];
17029}
17030def M2_vrcmpys_s1_l : HInst<
17031(outs DoubleRegs:$Rdd32),
17032(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17033"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo",
17034tc_c21d7447, TypeM>, Enc_a56825 {
17035let Inst{7-5} = 0b100;
17036let Inst{13-13} = 0b0;
17037let Inst{31-21} = 0b11101000111;
17038let prefersSlot3 = 1;
17039let Defs = [USR_OVF];
17040}
17041def M2_vrcmpys_s1rp : HInst<
17042(outs IntRegs:$Rd32),
17043(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17044"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat",
17045tc_c21d7447, TypeM> {
17046let hasNewValue = 1;
17047let opNewValue = 0;
17048let isPseudo = 1;
17049}
17050def M2_vrcmpys_s1rp_h : HInst<
17051(outs IntRegs:$Rd32),
17052(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17053"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi",
17054tc_c21d7447, TypeM>, Enc_d2216a {
17055let Inst{7-5} = 0b110;
17056let Inst{13-13} = 0b0;
17057let Inst{31-21} = 0b11101001101;
17058let hasNewValue = 1;
17059let opNewValue = 0;
17060let prefersSlot3 = 1;
17061let Defs = [USR_OVF];
17062}
17063def M2_vrcmpys_s1rp_l : HInst<
17064(outs IntRegs:$Rd32),
17065(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17066"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo",
17067tc_c21d7447, TypeM>, Enc_d2216a {
17068let Inst{7-5} = 0b111;
17069let Inst{13-13} = 0b0;
17070let Inst{31-21} = 0b11101001101;
17071let hasNewValue = 1;
17072let opNewValue = 0;
17073let prefersSlot3 = 1;
17074let Defs = [USR_OVF];
17075}
17076def M2_vrmac_s0 : HInst<
17077(outs DoubleRegs:$Rxx32),
17078(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17079"$Rxx32 += vrmpyh($Rss32,$Rtt32)",
17080tc_7f8ae742, TypeM>, Enc_88c16c {
17081let Inst{7-5} = 0b010;
17082let Inst{13-13} = 0b0;
17083let Inst{31-21} = 0b11101010000;
17084let prefersSlot3 = 1;
17085let Constraints = "$Rxx32 = $Rxx32in";
17086}
17087def M2_vrmpy_s0 : HInst<
17088(outs DoubleRegs:$Rdd32),
17089(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17090"$Rdd32 = vrmpyh($Rss32,$Rtt32)",
17091tc_c21d7447, TypeM>, Enc_a56825 {
17092let Inst{7-5} = 0b010;
17093let Inst{13-13} = 0b0;
17094let Inst{31-21} = 0b11101000000;
17095let prefersSlot3 = 1;
17096}
17097def M2_xor_xacc : HInst<
17098(outs IntRegs:$Rx32),
17099(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17100"$Rx32 ^= xor($Rs32,$Rt32)",
17101tc_a4e22bbd, TypeM>, Enc_2ae154 {
17102let Inst{7-5} = 0b011;
17103let Inst{13-13} = 0b0;
17104let Inst{31-21} = 0b11101111100;
17105let hasNewValue = 1;
17106let opNewValue = 0;
17107let prefersSlot3 = 1;
17108let InputType = "reg";
17109let Constraints = "$Rx32 = $Rx32in";
17110}
17111def M4_and_and : HInst<
17112(outs IntRegs:$Rx32),
17113(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17114"$Rx32 &= and($Rs32,$Rt32)",
17115tc_a4e22bbd, TypeM>, Enc_2ae154 {
17116let Inst{7-5} = 0b000;
17117let Inst{13-13} = 0b0;
17118let Inst{31-21} = 0b11101111010;
17119let hasNewValue = 1;
17120let opNewValue = 0;
17121let prefersSlot3 = 1;
17122let InputType = "reg";
17123let Constraints = "$Rx32 = $Rx32in";
17124}
17125def M4_and_andn : HInst<
17126(outs IntRegs:$Rx32),
17127(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17128"$Rx32 &= and($Rs32,~$Rt32)",
17129tc_a4e22bbd, TypeM>, Enc_2ae154 {
17130let Inst{7-5} = 0b001;
17131let Inst{13-13} = 0b0;
17132let Inst{31-21} = 0b11101111001;
17133let hasNewValue = 1;
17134let opNewValue = 0;
17135let prefersSlot3 = 1;
17136let InputType = "reg";
17137let Constraints = "$Rx32 = $Rx32in";
17138}
17139def M4_and_or : HInst<
17140(outs IntRegs:$Rx32),
17141(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17142"$Rx32 &= or($Rs32,$Rt32)",
17143tc_a4e22bbd, TypeM>, Enc_2ae154 {
17144let Inst{7-5} = 0b001;
17145let Inst{13-13} = 0b0;
17146let Inst{31-21} = 0b11101111010;
17147let hasNewValue = 1;
17148let opNewValue = 0;
17149let prefersSlot3 = 1;
17150let InputType = "reg";
17151let Constraints = "$Rx32 = $Rx32in";
17152}
17153def M4_and_xor : HInst<
17154(outs IntRegs:$Rx32),
17155(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17156"$Rx32 &= xor($Rs32,$Rt32)",
17157tc_a4e22bbd, TypeM>, Enc_2ae154 {
17158let Inst{7-5} = 0b010;
17159let Inst{13-13} = 0b0;
17160let Inst{31-21} = 0b11101111010;
17161let hasNewValue = 1;
17162let opNewValue = 0;
17163let prefersSlot3 = 1;
17164let InputType = "reg";
17165let Constraints = "$Rx32 = $Rx32in";
17166}
17167def M4_cmpyi_wh : HInst<
17168(outs IntRegs:$Rd32),
17169(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17170"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat",
17171tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17172let Inst{7-5} = 0b100;
17173let Inst{13-13} = 0b0;
17174let Inst{31-21} = 0b11000101000;
17175let hasNewValue = 1;
17176let opNewValue = 0;
17177let prefersSlot3 = 1;
17178let Defs = [USR_OVF];
17179}
17180def M4_cmpyi_whc : HInst<
17181(outs IntRegs:$Rd32),
17182(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17183"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat",
17184tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17185let Inst{7-5} = 0b101;
17186let Inst{13-13} = 0b0;
17187let Inst{31-21} = 0b11000101000;
17188let hasNewValue = 1;
17189let opNewValue = 0;
17190let prefersSlot3 = 1;
17191let Defs = [USR_OVF];
17192}
17193def M4_cmpyr_wh : HInst<
17194(outs IntRegs:$Rd32),
17195(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17196"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat",
17197tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17198let Inst{7-5} = 0b110;
17199let Inst{13-13} = 0b0;
17200let Inst{31-21} = 0b11000101000;
17201let hasNewValue = 1;
17202let opNewValue = 0;
17203let prefersSlot3 = 1;
17204let Defs = [USR_OVF];
17205}
17206def M4_cmpyr_whc : HInst<
17207(outs IntRegs:$Rd32),
17208(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
17209"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat",
17210tc_c21d7447, TypeS_3op>, Enc_3d5b28 {
17211let Inst{7-5} = 0b111;
17212let Inst{13-13} = 0b0;
17213let Inst{31-21} = 0b11000101000;
17214let hasNewValue = 1;
17215let opNewValue = 0;
17216let prefersSlot3 = 1;
17217let Defs = [USR_OVF];
17218}
17219def M4_mac_up_s1_sat : HInst<
17220(outs IntRegs:$Rx32),
17221(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17222"$Rx32 += mpy($Rs32,$Rt32):<<1:sat",
17223tc_7f8ae742, TypeM>, Enc_2ae154 {
17224let Inst{7-5} = 0b000;
17225let Inst{13-13} = 0b0;
17226let Inst{31-21} = 0b11101111011;
17227let hasNewValue = 1;
17228let opNewValue = 0;
17229let prefersSlot3 = 1;
17230let Defs = [USR_OVF];
17231let InputType = "reg";
17232let Constraints = "$Rx32 = $Rx32in";
17233}
17234def M4_mpyri_addi : HInst<
17235(outs IntRegs:$Rd32),
17236(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II),
17237"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))",
17238tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel {
17239let Inst{31-24} = 0b11011000;
17240let hasNewValue = 1;
17241let opNewValue = 0;
17242let prefersSlot3 = 1;
17243let CextOpcode = "M4_mpyri_addr";
17244let isExtendable = 1;
17245let opExtendable = 1;
17246let isExtentSigned = 0;
17247let opExtentBits = 6;
17248let opExtentAlign = 0;
17249}
17250def M4_mpyri_addr : HInst<
17251(outs IntRegs:$Rd32),
17252(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii),
17253"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))",
17254tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel {
17255let Inst{31-23} = 0b110111111;
17256let hasNewValue = 1;
17257let opNewValue = 0;
17258let prefersSlot3 = 1;
17259let CextOpcode = "M4_mpyri_addr";
17260let InputType = "imm";
17261let isExtendable = 1;
17262let opExtendable = 3;
17263let isExtentSigned = 0;
17264let opExtentBits = 6;
17265let opExtentAlign = 0;
17266}
17267def M4_mpyri_addr_u2 : HInst<
17268(outs IntRegs:$Rd32),
17269(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32),
17270"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))",
17271tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> {
17272let Inst{31-23} = 0b110111110;
17273let hasNewValue = 1;
17274let opNewValue = 0;
17275let prefersSlot3 = 1;
17276}
17277def M4_mpyrr_addi : HInst<
17278(outs IntRegs:$Rd32),
17279(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32),
17280"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))",
17281tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel {
17282let Inst{31-23} = 0b110101110;
17283let hasNewValue = 1;
17284let opNewValue = 0;
17285let prefersSlot3 = 1;
17286let CextOpcode = "M4_mpyrr_addr";
17287let InputType = "imm";
17288let isExtendable = 1;
17289let opExtendable = 1;
17290let isExtentSigned = 0;
17291let opExtentBits = 6;
17292let opExtentAlign = 0;
17293}
17294def M4_mpyrr_addr : HInst<
17295(outs IntRegs:$Ry32),
17296(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32),
17297"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))",
17298tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel {
17299let Inst{7-5} = 0b000;
17300let Inst{13-13} = 0b0;
17301let Inst{31-21} = 0b11100011000;
17302let hasNewValue = 1;
17303let opNewValue = 0;
17304let prefersSlot3 = 1;
17305let CextOpcode = "M4_mpyrr_addr";
17306let InputType = "reg";
17307let Constraints = "$Ry32 = $Ry32in";
17308}
17309def M4_nac_up_s1_sat : HInst<
17310(outs IntRegs:$Rx32),
17311(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17312"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat",
17313tc_7f8ae742, TypeM>, Enc_2ae154 {
17314let Inst{7-5} = 0b001;
17315let Inst{13-13} = 0b0;
17316let Inst{31-21} = 0b11101111011;
17317let hasNewValue = 1;
17318let opNewValue = 0;
17319let prefersSlot3 = 1;
17320let Defs = [USR_OVF];
17321let InputType = "reg";
17322let Constraints = "$Rx32 = $Rx32in";
17323}
17324def M4_or_and : HInst<
17325(outs IntRegs:$Rx32),
17326(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17327"$Rx32 |= and($Rs32,$Rt32)",
17328tc_a4e22bbd, TypeM>, Enc_2ae154 {
17329let Inst{7-5} = 0b011;
17330let Inst{13-13} = 0b0;
17331let Inst{31-21} = 0b11101111010;
17332let hasNewValue = 1;
17333let opNewValue = 0;
17334let prefersSlot3 = 1;
17335let InputType = "reg";
17336let Constraints = "$Rx32 = $Rx32in";
17337}
17338def M4_or_andn : HInst<
17339(outs IntRegs:$Rx32),
17340(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17341"$Rx32 |= and($Rs32,~$Rt32)",
17342tc_a4e22bbd, TypeM>, Enc_2ae154 {
17343let Inst{7-5} = 0b000;
17344let Inst{13-13} = 0b0;
17345let Inst{31-21} = 0b11101111001;
17346let hasNewValue = 1;
17347let opNewValue = 0;
17348let prefersSlot3 = 1;
17349let InputType = "reg";
17350let Constraints = "$Rx32 = $Rx32in";
17351}
17352def M4_or_or : HInst<
17353(outs IntRegs:$Rx32),
17354(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17355"$Rx32 |= or($Rs32,$Rt32)",
17356tc_a4e22bbd, TypeM>, Enc_2ae154 {
17357let Inst{7-5} = 0b000;
17358let Inst{13-13} = 0b0;
17359let Inst{31-21} = 0b11101111110;
17360let hasNewValue = 1;
17361let opNewValue = 0;
17362let prefersSlot3 = 1;
17363let InputType = "reg";
17364let Constraints = "$Rx32 = $Rx32in";
17365}
17366def M4_or_xor : HInst<
17367(outs IntRegs:$Rx32),
17368(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17369"$Rx32 |= xor($Rs32,$Rt32)",
17370tc_a4e22bbd, TypeM>, Enc_2ae154 {
17371let Inst{7-5} = 0b001;
17372let Inst{13-13} = 0b0;
17373let Inst{31-21} = 0b11101111110;
17374let hasNewValue = 1;
17375let opNewValue = 0;
17376let prefersSlot3 = 1;
17377let InputType = "reg";
17378let Constraints = "$Rx32 = $Rx32in";
17379}
17380def M4_pmpyw : HInst<
17381(outs DoubleRegs:$Rdd32),
17382(ins IntRegs:$Rs32, IntRegs:$Rt32),
17383"$Rdd32 = pmpyw($Rs32,$Rt32)",
17384tc_c21d7447, TypeM>, Enc_be32a5 {
17385let Inst{7-5} = 0b111;
17386let Inst{13-13} = 0b0;
17387let Inst{31-21} = 0b11100101010;
17388let prefersSlot3 = 1;
17389}
17390def M4_pmpyw_acc : HInst<
17391(outs DoubleRegs:$Rxx32),
17392(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17393"$Rxx32 ^= pmpyw($Rs32,$Rt32)",
17394tc_7f8ae742, TypeM>, Enc_61f0b0 {
17395let Inst{7-5} = 0b111;
17396let Inst{13-13} = 0b0;
17397let Inst{31-21} = 0b11100111001;
17398let prefersSlot3 = 1;
17399let Constraints = "$Rxx32 = $Rxx32in";
17400}
17401def M4_vpmpyh : HInst<
17402(outs DoubleRegs:$Rdd32),
17403(ins IntRegs:$Rs32, IntRegs:$Rt32),
17404"$Rdd32 = vpmpyh($Rs32,$Rt32)",
17405tc_c21d7447, TypeM>, Enc_be32a5 {
17406let Inst{7-5} = 0b111;
17407let Inst{13-13} = 0b0;
17408let Inst{31-21} = 0b11100101110;
17409let prefersSlot3 = 1;
17410}
17411def M4_vpmpyh_acc : HInst<
17412(outs DoubleRegs:$Rxx32),
17413(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17414"$Rxx32 ^= vpmpyh($Rs32,$Rt32)",
17415tc_7f8ae742, TypeM>, Enc_61f0b0 {
17416let Inst{7-5} = 0b111;
17417let Inst{13-13} = 0b0;
17418let Inst{31-21} = 0b11100111101;
17419let prefersSlot3 = 1;
17420let Constraints = "$Rxx32 = $Rxx32in";
17421}
17422def M4_vrmpyeh_acc_s0 : HInst<
17423(outs DoubleRegs:$Rxx32),
17424(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17425"$Rxx32 += vrmpyweh($Rss32,$Rtt32)",
17426tc_7f8ae742, TypeM>, Enc_88c16c {
17427let Inst{7-5} = 0b110;
17428let Inst{13-13} = 0b0;
17429let Inst{31-21} = 0b11101010001;
17430let prefersSlot3 = 1;
17431let Constraints = "$Rxx32 = $Rxx32in";
17432}
17433def M4_vrmpyeh_acc_s1 : HInst<
17434(outs DoubleRegs:$Rxx32),
17435(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17436"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1",
17437tc_7f8ae742, TypeM>, Enc_88c16c {
17438let Inst{7-5} = 0b110;
17439let Inst{13-13} = 0b0;
17440let Inst{31-21} = 0b11101010101;
17441let prefersSlot3 = 1;
17442let Constraints = "$Rxx32 = $Rxx32in";
17443}
17444def M4_vrmpyeh_s0 : HInst<
17445(outs DoubleRegs:$Rdd32),
17446(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17447"$Rdd32 = vrmpyweh($Rss32,$Rtt32)",
17448tc_c21d7447, TypeM>, Enc_a56825 {
17449let Inst{7-5} = 0b100;
17450let Inst{13-13} = 0b0;
17451let Inst{31-21} = 0b11101000010;
17452let prefersSlot3 = 1;
17453}
17454def M4_vrmpyeh_s1 : HInst<
17455(outs DoubleRegs:$Rdd32),
17456(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17457"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1",
17458tc_c21d7447, TypeM>, Enc_a56825 {
17459let Inst{7-5} = 0b100;
17460let Inst{13-13} = 0b0;
17461let Inst{31-21} = 0b11101000110;
17462let prefersSlot3 = 1;
17463}
17464def M4_vrmpyoh_acc_s0 : HInst<
17465(outs DoubleRegs:$Rxx32),
17466(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17467"$Rxx32 += vrmpywoh($Rss32,$Rtt32)",
17468tc_7f8ae742, TypeM>, Enc_88c16c {
17469let Inst{7-5} = 0b110;
17470let Inst{13-13} = 0b0;
17471let Inst{31-21} = 0b11101010011;
17472let prefersSlot3 = 1;
17473let Constraints = "$Rxx32 = $Rxx32in";
17474}
17475def M4_vrmpyoh_acc_s1 : HInst<
17476(outs DoubleRegs:$Rxx32),
17477(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17478"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1",
17479tc_7f8ae742, TypeM>, Enc_88c16c {
17480let Inst{7-5} = 0b110;
17481let Inst{13-13} = 0b0;
17482let Inst{31-21} = 0b11101010111;
17483let prefersSlot3 = 1;
17484let Constraints = "$Rxx32 = $Rxx32in";
17485}
17486def M4_vrmpyoh_s0 : HInst<
17487(outs DoubleRegs:$Rdd32),
17488(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17489"$Rdd32 = vrmpywoh($Rss32,$Rtt32)",
17490tc_c21d7447, TypeM>, Enc_a56825 {
17491let Inst{7-5} = 0b010;
17492let Inst{13-13} = 0b0;
17493let Inst{31-21} = 0b11101000001;
17494let prefersSlot3 = 1;
17495}
17496def M4_vrmpyoh_s1 : HInst<
17497(outs DoubleRegs:$Rdd32),
17498(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17499"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1",
17500tc_c21d7447, TypeM>, Enc_a56825 {
17501let Inst{7-5} = 0b010;
17502let Inst{13-13} = 0b0;
17503let Inst{31-21} = 0b11101000101;
17504let prefersSlot3 = 1;
17505}
17506def M4_xor_and : HInst<
17507(outs IntRegs:$Rx32),
17508(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17509"$Rx32 ^= and($Rs32,$Rt32)",
17510tc_a4e22bbd, TypeM>, Enc_2ae154 {
17511let Inst{7-5} = 0b010;
17512let Inst{13-13} = 0b0;
17513let Inst{31-21} = 0b11101111110;
17514let hasNewValue = 1;
17515let opNewValue = 0;
17516let prefersSlot3 = 1;
17517let InputType = "reg";
17518let Constraints = "$Rx32 = $Rx32in";
17519}
17520def M4_xor_andn : HInst<
17521(outs IntRegs:$Rx32),
17522(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17523"$Rx32 ^= and($Rs32,~$Rt32)",
17524tc_a4e22bbd, TypeM>, Enc_2ae154 {
17525let Inst{7-5} = 0b010;
17526let Inst{13-13} = 0b0;
17527let Inst{31-21} = 0b11101111001;
17528let hasNewValue = 1;
17529let opNewValue = 0;
17530let prefersSlot3 = 1;
17531let InputType = "reg";
17532let Constraints = "$Rx32 = $Rx32in";
17533}
17534def M4_xor_or : HInst<
17535(outs IntRegs:$Rx32),
17536(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17537"$Rx32 ^= or($Rs32,$Rt32)",
17538tc_a4e22bbd, TypeM>, Enc_2ae154 {
17539let Inst{7-5} = 0b011;
17540let Inst{13-13} = 0b0;
17541let Inst{31-21} = 0b11101111110;
17542let hasNewValue = 1;
17543let opNewValue = 0;
17544let prefersSlot3 = 1;
17545let InputType = "reg";
17546let Constraints = "$Rx32 = $Rx32in";
17547}
17548def M4_xor_xacc : HInst<
17549(outs DoubleRegs:$Rxx32),
17550(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17551"$Rxx32 ^= xor($Rss32,$Rtt32)",
17552tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
17553let Inst{7-5} = 0b000;
17554let Inst{13-13} = 0b0;
17555let Inst{31-21} = 0b11001010100;
17556let prefersSlot3 = 1;
17557let Constraints = "$Rxx32 = $Rxx32in";
17558}
17559def M5_vdmacbsu : HInst<
17560(outs DoubleRegs:$Rxx32),
17561(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17562"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat",
17563tc_7f8ae742, TypeM>, Enc_88c16c {
17564let Inst{7-5} = 0b001;
17565let Inst{13-13} = 0b0;
17566let Inst{31-21} = 0b11101010001;
17567let prefersSlot3 = 1;
17568let Defs = [USR_OVF];
17569let Constraints = "$Rxx32 = $Rxx32in";
17570}
17571def M5_vdmpybsu : HInst<
17572(outs DoubleRegs:$Rdd32),
17573(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17574"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat",
17575tc_c21d7447, TypeM>, Enc_a56825 {
17576let Inst{7-5} = 0b001;
17577let Inst{13-13} = 0b0;
17578let Inst{31-21} = 0b11101000101;
17579let prefersSlot3 = 1;
17580let Defs = [USR_OVF];
17581}
17582def M5_vmacbsu : HInst<
17583(outs DoubleRegs:$Rxx32),
17584(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17585"$Rxx32 += vmpybsu($Rs32,$Rt32)",
17586tc_7f8ae742, TypeM>, Enc_61f0b0 {
17587let Inst{7-5} = 0b001;
17588let Inst{13-13} = 0b0;
17589let Inst{31-21} = 0b11100111110;
17590let prefersSlot3 = 1;
17591let Constraints = "$Rxx32 = $Rxx32in";
17592}
17593def M5_vmacbuu : HInst<
17594(outs DoubleRegs:$Rxx32),
17595(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32),
17596"$Rxx32 += vmpybu($Rs32,$Rt32)",
17597tc_7f8ae742, TypeM>, Enc_61f0b0 {
17598let Inst{7-5} = 0b001;
17599let Inst{13-13} = 0b0;
17600let Inst{31-21} = 0b11100111100;
17601let prefersSlot3 = 1;
17602let Constraints = "$Rxx32 = $Rxx32in";
17603}
17604def M5_vmpybsu : HInst<
17605(outs DoubleRegs:$Rdd32),
17606(ins IntRegs:$Rs32, IntRegs:$Rt32),
17607"$Rdd32 = vmpybsu($Rs32,$Rt32)",
17608tc_c21d7447, TypeM>, Enc_be32a5 {
17609let Inst{7-5} = 0b001;
17610let Inst{13-13} = 0b0;
17611let Inst{31-21} = 0b11100101010;
17612let prefersSlot3 = 1;
17613}
17614def M5_vmpybuu : HInst<
17615(outs DoubleRegs:$Rdd32),
17616(ins IntRegs:$Rs32, IntRegs:$Rt32),
17617"$Rdd32 = vmpybu($Rs32,$Rt32)",
17618tc_c21d7447, TypeM>, Enc_be32a5 {
17619let Inst{7-5} = 0b001;
17620let Inst{13-13} = 0b0;
17621let Inst{31-21} = 0b11100101100;
17622let prefersSlot3 = 1;
17623}
17624def M5_vrmacbsu : HInst<
17625(outs DoubleRegs:$Rxx32),
17626(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17627"$Rxx32 += vrmpybsu($Rss32,$Rtt32)",
17628tc_7f8ae742, TypeM>, Enc_88c16c {
17629let Inst{7-5} = 0b001;
17630let Inst{13-13} = 0b0;
17631let Inst{31-21} = 0b11101010110;
17632let prefersSlot3 = 1;
17633let Constraints = "$Rxx32 = $Rxx32in";
17634}
17635def M5_vrmacbuu : HInst<
17636(outs DoubleRegs:$Rxx32),
17637(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17638"$Rxx32 += vrmpybu($Rss32,$Rtt32)",
17639tc_7f8ae742, TypeM>, Enc_88c16c {
17640let Inst{7-5} = 0b001;
17641let Inst{13-13} = 0b0;
17642let Inst{31-21} = 0b11101010100;
17643let prefersSlot3 = 1;
17644let Constraints = "$Rxx32 = $Rxx32in";
17645}
17646def M5_vrmpybsu : HInst<
17647(outs DoubleRegs:$Rdd32),
17648(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17649"$Rdd32 = vrmpybsu($Rss32,$Rtt32)",
17650tc_c21d7447, TypeM>, Enc_a56825 {
17651let Inst{7-5} = 0b001;
17652let Inst{13-13} = 0b0;
17653let Inst{31-21} = 0b11101000110;
17654let prefersSlot3 = 1;
17655}
17656def M5_vrmpybuu : HInst<
17657(outs DoubleRegs:$Rdd32),
17658(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17659"$Rdd32 = vrmpybu($Rss32,$Rtt32)",
17660tc_c21d7447, TypeM>, Enc_a56825 {
17661let Inst{7-5} = 0b001;
17662let Inst{13-13} = 0b0;
17663let Inst{31-21} = 0b11101000100;
17664let prefersSlot3 = 1;
17665}
17666def M6_vabsdiffb : HInst<
17667(outs DoubleRegs:$Rdd32),
17668(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17669"$Rdd32 = vabsdiffb($Rtt32,$Rss32)",
17670tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17671let Inst{7-5} = 0b000;
17672let Inst{13-13} = 0b0;
17673let Inst{31-21} = 0b11101000111;
17674let prefersSlot3 = 1;
17675}
17676def M6_vabsdiffub : HInst<
17677(outs DoubleRegs:$Rdd32),
17678(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
17679"$Rdd32 = vabsdiffub($Rtt32,$Rss32)",
17680tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> {
17681let Inst{7-5} = 0b000;
17682let Inst{13-13} = 0b0;
17683let Inst{31-21} = 0b11101000101;
17684let prefersSlot3 = 1;
17685}
17686def M7_dcmpyiw : HInst<
17687(outs DoubleRegs:$Rdd32),
17688(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17689"$Rdd32 = cmpyiw($Rss32,$Rtt32)",
17690tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17691let Inst{7-5} = 0b010;
17692let Inst{13-13} = 0b0;
17693let Inst{31-21} = 0b11101000011;
17694let prefersSlot3 = 1;
17695}
17696def M7_dcmpyiw_acc : HInst<
17697(outs DoubleRegs:$Rxx32),
17698(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17699"$Rxx32 += cmpyiw($Rss32,$Rtt32)",
17700tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17701let Inst{7-5} = 0b010;
17702let Inst{13-13} = 0b0;
17703let Inst{31-21} = 0b11101010011;
17704let prefersSlot3 = 1;
17705let Constraints = "$Rxx32 = $Rxx32in";
17706}
17707def M7_dcmpyiwc : HInst<
17708(outs DoubleRegs:$Rdd32),
17709(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17710"$Rdd32 = cmpyiw($Rss32,$Rtt32*)",
17711tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17712let Inst{7-5} = 0b010;
17713let Inst{13-13} = 0b0;
17714let Inst{31-21} = 0b11101000111;
17715let prefersSlot3 = 1;
17716}
17717def M7_dcmpyiwc_acc : HInst<
17718(outs DoubleRegs:$Rxx32),
17719(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17720"$Rxx32 += cmpyiw($Rss32,$Rtt32*)",
17721tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17722let Inst{7-5} = 0b110;
17723let Inst{13-13} = 0b0;
17724let Inst{31-21} = 0b11101010010;
17725let prefersSlot3 = 1;
17726let Constraints = "$Rxx32 = $Rxx32in";
17727}
17728def M7_dcmpyrw : HInst<
17729(outs DoubleRegs:$Rdd32),
17730(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17731"$Rdd32 = cmpyrw($Rss32,$Rtt32)",
17732tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17733let Inst{7-5} = 0b010;
17734let Inst{13-13} = 0b0;
17735let Inst{31-21} = 0b11101000100;
17736let prefersSlot3 = 1;
17737}
17738def M7_dcmpyrw_acc : HInst<
17739(outs DoubleRegs:$Rxx32),
17740(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17741"$Rxx32 += cmpyrw($Rss32,$Rtt32)",
17742tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17743let Inst{7-5} = 0b010;
17744let Inst{13-13} = 0b0;
17745let Inst{31-21} = 0b11101010100;
17746let prefersSlot3 = 1;
17747let Constraints = "$Rxx32 = $Rxx32in";
17748}
17749def M7_dcmpyrwc : HInst<
17750(outs DoubleRegs:$Rdd32),
17751(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17752"$Rdd32 = cmpyrw($Rss32,$Rtt32*)",
17753tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> {
17754let Inst{7-5} = 0b010;
17755let Inst{13-13} = 0b0;
17756let Inst{31-21} = 0b11101000110;
17757let prefersSlot3 = 1;
17758}
17759def M7_dcmpyrwc_acc : HInst<
17760(outs DoubleRegs:$Rxx32),
17761(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17762"$Rxx32 += cmpyrw($Rss32,$Rtt32*)",
17763tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> {
17764let Inst{7-5} = 0b010;
17765let Inst{13-13} = 0b0;
17766let Inst{31-21} = 0b11101010110;
17767let prefersSlot3 = 1;
17768let Constraints = "$Rxx32 = $Rxx32in";
17769}
17770def M7_vdmpy : HInst<
17771(outs DoubleRegs:$Rdd32),
17772(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17773"$Rdd32 = vdmpyw($Rss32,$Rtt32)",
17774tc_5a4b5e58, TypeM>, Requires<[HasV67]> {
17775let isPseudo = 1;
17776let isCodeGenOnly = 1;
17777}
17778def M7_vdmpy_acc : HInst<
17779(outs DoubleRegs:$Rxx32),
17780(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17781"$Rxx32 += vdmpyw($Rss32,$Rtt32)",
17782tc_197dce51, TypeM>, Requires<[HasV67]> {
17783let isPseudo = 1;
17784let isCodeGenOnly = 1;
17785let Constraints = "$Rxx32 = $Rxx32in";
17786}
17787def M7_wcmpyiw : HInst<
17788(outs IntRegs:$Rd32),
17789(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17790"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat",
17791tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17792let Inst{7-5} = 0b000;
17793let Inst{13-13} = 0b0;
17794let Inst{31-21} = 0b11101001001;
17795let hasNewValue = 1;
17796let opNewValue = 0;
17797let prefersSlot3 = 1;
17798let Defs = [USR_OVF];
17799}
17800def M7_wcmpyiw_rnd : HInst<
17801(outs IntRegs:$Rd32),
17802(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17803"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat",
17804tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17805let Inst{7-5} = 0b000;
17806let Inst{13-13} = 0b0;
17807let Inst{31-21} = 0b11101001101;
17808let hasNewValue = 1;
17809let opNewValue = 0;
17810let prefersSlot3 = 1;
17811let Defs = [USR_OVF];
17812}
17813def M7_wcmpyiwc : HInst<
17814(outs IntRegs:$Rd32),
17815(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17816"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat",
17817tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17818let Inst{7-5} = 0b100;
17819let Inst{13-13} = 0b0;
17820let Inst{31-21} = 0b11101001000;
17821let hasNewValue = 1;
17822let opNewValue = 0;
17823let prefersSlot3 = 1;
17824let Defs = [USR_OVF];
17825}
17826def M7_wcmpyiwc_rnd : HInst<
17827(outs IntRegs:$Rd32),
17828(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17829"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat",
17830tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17831let Inst{7-5} = 0b100;
17832let Inst{13-13} = 0b0;
17833let Inst{31-21} = 0b11101001100;
17834let hasNewValue = 1;
17835let opNewValue = 0;
17836let prefersSlot3 = 1;
17837let Defs = [USR_OVF];
17838}
17839def M7_wcmpyrw : HInst<
17840(outs IntRegs:$Rd32),
17841(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17842"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat",
17843tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17844let Inst{7-5} = 0b000;
17845let Inst{13-13} = 0b0;
17846let Inst{31-21} = 0b11101001010;
17847let hasNewValue = 1;
17848let opNewValue = 0;
17849let prefersSlot3 = 1;
17850let Defs = [USR_OVF];
17851}
17852def M7_wcmpyrw_rnd : HInst<
17853(outs IntRegs:$Rd32),
17854(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17855"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat",
17856tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17857let Inst{7-5} = 0b000;
17858let Inst{13-13} = 0b0;
17859let Inst{31-21} = 0b11101001110;
17860let hasNewValue = 1;
17861let opNewValue = 0;
17862let prefersSlot3 = 1;
17863let Defs = [USR_OVF];
17864}
17865def M7_wcmpyrwc : HInst<
17866(outs IntRegs:$Rd32),
17867(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17868"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat",
17869tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17870let Inst{7-5} = 0b000;
17871let Inst{13-13} = 0b0;
17872let Inst{31-21} = 0b11101001011;
17873let hasNewValue = 1;
17874let opNewValue = 0;
17875let prefersSlot3 = 1;
17876let Defs = [USR_OVF];
17877}
17878def M7_wcmpyrwc_rnd : HInst<
17879(outs IntRegs:$Rd32),
17880(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
17881"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat",
17882tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> {
17883let Inst{7-5} = 0b000;
17884let Inst{13-13} = 0b0;
17885let Inst{31-21} = 0b11101001111;
17886let hasNewValue = 1;
17887let opNewValue = 0;
17888let prefersSlot3 = 1;
17889let Defs = [USR_OVF];
17890}
17891def PS_loadrbabs : HInst<
17892(outs IntRegs:$Rd32),
17893(ins u32_0Imm:$Ii),
17894"$Rd32 = memb(#$Ii)",
17895tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17896let Inst{24-21} = 0b1000;
17897let Inst{31-27} = 0b01001;
17898let hasNewValue = 1;
17899let opNewValue = 0;
17900let addrMode = Absolute;
17901let accessSize = ByteAccess;
17902let mayLoad = 1;
17903let isExtended = 1;
17904let BaseOpcode = "L4_loadrb_abs";
17905let CextOpcode = "L2_loadrb";
17906let isPredicable = 1;
17907let DecoderNamespace = "MustExtend";
17908let isExtended = 1;
17909let opExtendable = 1;
17910let isExtentSigned = 0;
17911let opExtentBits = 16;
17912let opExtentAlign = 0;
17913}
17914def PS_loadrdabs : HInst<
17915(outs DoubleRegs:$Rdd32),
17916(ins u29_3Imm:$Ii),
17917"$Rdd32 = memd(#$Ii)",
17918tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel {
17919let Inst{24-21} = 0b1110;
17920let Inst{31-27} = 0b01001;
17921let addrMode = Absolute;
17922let accessSize = DoubleWordAccess;
17923let mayLoad = 1;
17924let isExtended = 1;
17925let BaseOpcode = "L4_loadrd_abs";
17926let CextOpcode = "L2_loadrd";
17927let isPredicable = 1;
17928let DecoderNamespace = "MustExtend";
17929let isExtended = 1;
17930let opExtendable = 1;
17931let isExtentSigned = 0;
17932let opExtentBits = 19;
17933let opExtentAlign = 3;
17934}
17935def PS_loadrhabs : HInst<
17936(outs IntRegs:$Rd32),
17937(ins u31_1Imm:$Ii),
17938"$Rd32 = memh(#$Ii)",
17939tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
17940let Inst{24-21} = 0b1010;
17941let Inst{31-27} = 0b01001;
17942let hasNewValue = 1;
17943let opNewValue = 0;
17944let addrMode = Absolute;
17945let accessSize = HalfWordAccess;
17946let mayLoad = 1;
17947let isExtended = 1;
17948let BaseOpcode = "L4_loadrh_abs";
17949let CextOpcode = "L2_loadrh";
17950let isPredicable = 1;
17951let DecoderNamespace = "MustExtend";
17952let isExtended = 1;
17953let opExtendable = 1;
17954let isExtentSigned = 0;
17955let opExtentBits = 17;
17956let opExtentAlign = 1;
17957}
17958def PS_loadriabs : HInst<
17959(outs IntRegs:$Rd32),
17960(ins u30_2Imm:$Ii),
17961"$Rd32 = memw(#$Ii)",
17962tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel {
17963let Inst{24-21} = 0b1100;
17964let Inst{31-27} = 0b01001;
17965let hasNewValue = 1;
17966let opNewValue = 0;
17967let addrMode = Absolute;
17968let accessSize = WordAccess;
17969let mayLoad = 1;
17970let isExtended = 1;
17971let BaseOpcode = "L4_loadri_abs";
17972let CextOpcode = "L2_loadri";
17973let isPredicable = 1;
17974let DecoderNamespace = "MustExtend";
17975let isExtended = 1;
17976let opExtendable = 1;
17977let isExtentSigned = 0;
17978let opExtentBits = 18;
17979let opExtentAlign = 2;
17980}
17981def PS_loadrubabs : HInst<
17982(outs IntRegs:$Rd32),
17983(ins u32_0Imm:$Ii),
17984"$Rd32 = memub(#$Ii)",
17985tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel {
17986let Inst{24-21} = 0b1001;
17987let Inst{31-27} = 0b01001;
17988let hasNewValue = 1;
17989let opNewValue = 0;
17990let addrMode = Absolute;
17991let accessSize = ByteAccess;
17992let mayLoad = 1;
17993let isExtended = 1;
17994let BaseOpcode = "L4_loadrub_abs";
17995let CextOpcode = "L2_loadrub";
17996let isPredicable = 1;
17997let DecoderNamespace = "MustExtend";
17998let isExtended = 1;
17999let opExtendable = 1;
18000let isExtentSigned = 0;
18001let opExtentBits = 16;
18002let opExtentAlign = 0;
18003}
18004def PS_loadruhabs : HInst<
18005(outs IntRegs:$Rd32),
18006(ins u31_1Imm:$Ii),
18007"$Rd32 = memuh(#$Ii)",
18008tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel {
18009let Inst{24-21} = 0b1011;
18010let Inst{31-27} = 0b01001;
18011let hasNewValue = 1;
18012let opNewValue = 0;
18013let addrMode = Absolute;
18014let accessSize = HalfWordAccess;
18015let mayLoad = 1;
18016let isExtended = 1;
18017let BaseOpcode = "L4_loadruh_abs";
18018let CextOpcode = "L2_loadruh";
18019let isPredicable = 1;
18020let DecoderNamespace = "MustExtend";
18021let isExtended = 1;
18022let opExtendable = 1;
18023let isExtentSigned = 0;
18024let opExtentBits = 17;
18025let opExtentAlign = 1;
18026}
18027def PS_storerbabs : HInst<
18028(outs),
18029(ins u32_0Imm:$Ii, IntRegs:$Rt32),
18030"memb(#$Ii) = $Rt32",
18031tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
18032let Inst{24-21} = 0b0000;
18033let Inst{31-27} = 0b01001;
18034let addrMode = Absolute;
18035let accessSize = ByteAccess;
18036let isExtended = 1;
18037let mayStore = 1;
18038let BaseOpcode = "S2_storerbabs";
18039let CextOpcode = "S2_storerb";
18040let isNVStorable = 1;
18041let isPredicable = 1;
18042let DecoderNamespace = "MustExtend";
18043let isExtended = 1;
18044let opExtendable = 0;
18045let isExtentSigned = 0;
18046let opExtentBits = 16;
18047let opExtentAlign = 0;
18048}
18049def PS_storerbnewabs : HInst<
18050(outs),
18051(ins u32_0Imm:$Ii, IntRegs:$Nt8),
18052"memb(#$Ii) = $Nt8.new",
18053tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
18054let Inst{12-11} = 0b00;
18055let Inst{24-21} = 0b0101;
18056let Inst{31-27} = 0b01001;
18057let addrMode = Absolute;
18058let accessSize = ByteAccess;
18059let isNVStore = 1;
18060let isNewValue = 1;
18061let isExtended = 1;
18062let isRestrictNoSlot1Store = 1;
18063let mayStore = 1;
18064let BaseOpcode = "S2_storerbabs";
18065let CextOpcode = "S2_storerb";
18066let isPredicable = 1;
18067let DecoderNamespace = "MustExtend";
18068let isExtended = 1;
18069let opExtendable = 0;
18070let isExtentSigned = 0;
18071let opExtentBits = 16;
18072let opExtentAlign = 0;
18073let opNewValue = 1;
18074}
18075def PS_storerdabs : HInst<
18076(outs),
18077(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
18078"memd(#$Ii) = $Rtt32",
18079tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
18080let Inst{24-21} = 0b0110;
18081let Inst{31-27} = 0b01001;
18082let addrMode = Absolute;
18083let accessSize = DoubleWordAccess;
18084let isExtended = 1;
18085let mayStore = 1;
18086let BaseOpcode = "S2_storerdabs";
18087let CextOpcode = "S2_storerd";
18088let isPredicable = 1;
18089let DecoderNamespace = "MustExtend";
18090let isExtended = 1;
18091let opExtendable = 0;
18092let isExtentSigned = 0;
18093let opExtentBits = 19;
18094let opExtentAlign = 3;
18095}
18096def PS_storerfabs : HInst<
18097(outs),
18098(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18099"memh(#$Ii) = $Rt32.h",
18100tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18101let Inst{24-21} = 0b0011;
18102let Inst{31-27} = 0b01001;
18103let addrMode = Absolute;
18104let accessSize = HalfWordAccess;
18105let isExtended = 1;
18106let mayStore = 1;
18107let BaseOpcode = "S2_storerfabs";
18108let CextOpcode = "S2_storerf";
18109let isPredicable = 1;
18110let DecoderNamespace = "MustExtend";
18111let isExtended = 1;
18112let opExtendable = 0;
18113let isExtentSigned = 0;
18114let opExtentBits = 17;
18115let opExtentAlign = 1;
18116}
18117def PS_storerhabs : HInst<
18118(outs),
18119(ins u31_1Imm:$Ii, IntRegs:$Rt32),
18120"memh(#$Ii) = $Rt32",
18121tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
18122let Inst{24-21} = 0b0010;
18123let Inst{31-27} = 0b01001;
18124let addrMode = Absolute;
18125let accessSize = HalfWordAccess;
18126let isExtended = 1;
18127let mayStore = 1;
18128let BaseOpcode = "S2_storerhabs";
18129let CextOpcode = "S2_storerh";
18130let isNVStorable = 1;
18131let isPredicable = 1;
18132let DecoderNamespace = "MustExtend";
18133let isExtended = 1;
18134let opExtendable = 0;
18135let isExtentSigned = 0;
18136let opExtentBits = 17;
18137let opExtentAlign = 1;
18138}
18139def PS_storerhnewabs : HInst<
18140(outs),
18141(ins u31_1Imm:$Ii, IntRegs:$Nt8),
18142"memh(#$Ii) = $Nt8.new",
18143tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
18144let Inst{12-11} = 0b01;
18145let Inst{24-21} = 0b0101;
18146let Inst{31-27} = 0b01001;
18147let addrMode = Absolute;
18148let accessSize = HalfWordAccess;
18149let isNVStore = 1;
18150let isNewValue = 1;
18151let isExtended = 1;
18152let isRestrictNoSlot1Store = 1;
18153let mayStore = 1;
18154let BaseOpcode = "S2_storerhabs";
18155let CextOpcode = "S2_storerh";
18156let isPredicable = 1;
18157let DecoderNamespace = "MustExtend";
18158let isExtended = 1;
18159let opExtendable = 0;
18160let isExtentSigned = 0;
18161let opExtentBits = 17;
18162let opExtentAlign = 1;
18163let opNewValue = 1;
18164}
18165def PS_storeriabs : HInst<
18166(outs),
18167(ins u30_2Imm:$Ii, IntRegs:$Rt32),
18168"memw(#$Ii) = $Rt32",
18169tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
18170let Inst{24-21} = 0b0100;
18171let Inst{31-27} = 0b01001;
18172let addrMode = Absolute;
18173let accessSize = WordAccess;
18174let isExtended = 1;
18175let mayStore = 1;
18176let BaseOpcode = "S2_storeriabs";
18177let CextOpcode = "S2_storeri";
18178let isNVStorable = 1;
18179let isPredicable = 1;
18180let DecoderNamespace = "MustExtend";
18181let isExtended = 1;
18182let opExtendable = 0;
18183let isExtentSigned = 0;
18184let opExtentBits = 18;
18185let opExtentAlign = 2;
18186}
18187def PS_storerinewabs : HInst<
18188(outs),
18189(ins u30_2Imm:$Ii, IntRegs:$Nt8),
18190"memw(#$Ii) = $Nt8.new",
18191tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
18192let Inst{12-11} = 0b10;
18193let Inst{24-21} = 0b0101;
18194let Inst{31-27} = 0b01001;
18195let addrMode = Absolute;
18196let accessSize = WordAccess;
18197let isNVStore = 1;
18198let isNewValue = 1;
18199let isExtended = 1;
18200let isRestrictNoSlot1Store = 1;
18201let mayStore = 1;
18202let BaseOpcode = "S2_storeriabs";
18203let CextOpcode = "S2_storeri";
18204let isPredicable = 1;
18205let DecoderNamespace = "MustExtend";
18206let isExtended = 1;
18207let opExtendable = 0;
18208let isExtentSigned = 0;
18209let opExtentBits = 18;
18210let opExtentAlign = 2;
18211let opNewValue = 1;
18212}
18213def PS_trap1 : HInst<
18214(outs),
18215(ins u8_0Imm:$Ii),
18216"trap1(#$Ii)",
18217tc_53c851ab, TypeJ>, Enc_a51a9a, Requires<[HasPreV65]> {
18218let Inst{1-0} = 0b00;
18219let Inst{7-5} = 0b000;
18220let Inst{13-13} = 0b0;
18221let Inst{31-16} = 0b0101010010000000;
18222}
18223def R6_release_at_vi : HInst<
18224(outs),
18225(ins IntRegs:$Rs32),
18226"release($Rs32):at",
18227tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18228let Inst{7-2} = 0b000011;
18229let Inst{13-13} = 0b0;
18230let Inst{31-21} = 0b10100000111;
18231let isSolo = 1;
18232let mayStore = 1;
18233}
18234def R6_release_st_vi : HInst<
18235(outs),
18236(ins IntRegs:$Rs32),
18237"release($Rs32):st",
18238tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
18239let Inst{7-2} = 0b001011;
18240let Inst{13-13} = 0b0;
18241let Inst{31-21} = 0b10100000111;
18242let isSolo = 1;
18243let mayStore = 1;
18244}
18245def S2_addasl_rrri : HInst<
18246(outs IntRegs:$Rd32),
18247(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii),
18248"$Rd32 = addasl($Rt32,$Rs32,#$Ii)",
18249tc_2c13e7f5, TypeS_3op>, Enc_47ef61 {
18250let Inst{13-13} = 0b0;
18251let Inst{31-21} = 0b11000100000;
18252let hasNewValue = 1;
18253let opNewValue = 0;
18254let prefersSlot3 = 1;
18255}
18256def S2_allocframe : HInst<
18257(outs IntRegs:$Rx32),
18258(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
18259"allocframe($Rx32,#$Ii):raw",
18260tc_934753bb, TypeST>, Enc_22c845 {
18261let Inst{13-11} = 0b000;
18262let Inst{31-21} = 0b10100000100;
18263let hasNewValue = 1;
18264let opNewValue = 0;
18265let addrMode = BaseImmOffset;
18266let accessSize = DoubleWordAccess;
18267let mayStore = 1;
18268let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
18269let Defs = [R30];
18270let Constraints = "$Rx32 = $Rx32in";
18271}
18272def S2_asl_i_p : HInst<
18273(outs DoubleRegs:$Rdd32),
18274(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18275"$Rdd32 = asl($Rss32,#$Ii)",
18276tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18277let Inst{7-5} = 0b010;
18278let Inst{31-21} = 0b10000000000;
18279}
18280def S2_asl_i_p_acc : HInst<
18281(outs DoubleRegs:$Rxx32),
18282(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18283"$Rxx32 += asl($Rss32,#$Ii)",
18284tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18285let Inst{7-5} = 0b110;
18286let Inst{31-21} = 0b10000010000;
18287let prefersSlot3 = 1;
18288let Constraints = "$Rxx32 = $Rxx32in";
18289}
18290def S2_asl_i_p_and : HInst<
18291(outs DoubleRegs:$Rxx32),
18292(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18293"$Rxx32 &= asl($Rss32,#$Ii)",
18294tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18295let Inst{7-5} = 0b010;
18296let Inst{31-21} = 0b10000010010;
18297let prefersSlot3 = 1;
18298let Constraints = "$Rxx32 = $Rxx32in";
18299}
18300def S2_asl_i_p_nac : HInst<
18301(outs DoubleRegs:$Rxx32),
18302(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18303"$Rxx32 -= asl($Rss32,#$Ii)",
18304tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18305let Inst{7-5} = 0b010;
18306let Inst{31-21} = 0b10000010000;
18307let prefersSlot3 = 1;
18308let Constraints = "$Rxx32 = $Rxx32in";
18309}
18310def S2_asl_i_p_or : HInst<
18311(outs DoubleRegs:$Rxx32),
18312(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18313"$Rxx32 |= asl($Rss32,#$Ii)",
18314tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18315let Inst{7-5} = 0b110;
18316let Inst{31-21} = 0b10000010010;
18317let prefersSlot3 = 1;
18318let Constraints = "$Rxx32 = $Rxx32in";
18319}
18320def S2_asl_i_p_xacc : HInst<
18321(outs DoubleRegs:$Rxx32),
18322(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18323"$Rxx32 ^= asl($Rss32,#$Ii)",
18324tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18325let Inst{7-5} = 0b010;
18326let Inst{31-21} = 0b10000010100;
18327let prefersSlot3 = 1;
18328let Constraints = "$Rxx32 = $Rxx32in";
18329}
18330def S2_asl_i_r : HInst<
18331(outs IntRegs:$Rd32),
18332(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18333"$Rd32 = asl($Rs32,#$Ii)",
18334tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18335let Inst{7-5} = 0b010;
18336let Inst{13-13} = 0b0;
18337let Inst{31-21} = 0b10001100000;
18338let hasNewValue = 1;
18339let opNewValue = 0;
18340}
18341def S2_asl_i_r_acc : HInst<
18342(outs IntRegs:$Rx32),
18343(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18344"$Rx32 += asl($Rs32,#$Ii)",
18345tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18346let Inst{7-5} = 0b110;
18347let Inst{13-13} = 0b0;
18348let Inst{31-21} = 0b10001110000;
18349let hasNewValue = 1;
18350let opNewValue = 0;
18351let prefersSlot3 = 1;
18352let Constraints = "$Rx32 = $Rx32in";
18353}
18354def S2_asl_i_r_and : HInst<
18355(outs IntRegs:$Rx32),
18356(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18357"$Rx32 &= asl($Rs32,#$Ii)",
18358tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18359let Inst{7-5} = 0b010;
18360let Inst{13-13} = 0b0;
18361let Inst{31-21} = 0b10001110010;
18362let hasNewValue = 1;
18363let opNewValue = 0;
18364let prefersSlot3 = 1;
18365let Constraints = "$Rx32 = $Rx32in";
18366}
18367def S2_asl_i_r_nac : HInst<
18368(outs IntRegs:$Rx32),
18369(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18370"$Rx32 -= asl($Rs32,#$Ii)",
18371tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18372let Inst{7-5} = 0b010;
18373let Inst{13-13} = 0b0;
18374let Inst{31-21} = 0b10001110000;
18375let hasNewValue = 1;
18376let opNewValue = 0;
18377let prefersSlot3 = 1;
18378let Constraints = "$Rx32 = $Rx32in";
18379}
18380def S2_asl_i_r_or : HInst<
18381(outs IntRegs:$Rx32),
18382(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18383"$Rx32 |= asl($Rs32,#$Ii)",
18384tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18385let Inst{7-5} = 0b110;
18386let Inst{13-13} = 0b0;
18387let Inst{31-21} = 0b10001110010;
18388let hasNewValue = 1;
18389let opNewValue = 0;
18390let prefersSlot3 = 1;
18391let Constraints = "$Rx32 = $Rx32in";
18392}
18393def S2_asl_i_r_sat : HInst<
18394(outs IntRegs:$Rd32),
18395(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18396"$Rd32 = asl($Rs32,#$Ii):sat",
18397tc_8a825db2, TypeS_2op>, Enc_a05677 {
18398let Inst{7-5} = 0b010;
18399let Inst{13-13} = 0b0;
18400let Inst{31-21} = 0b10001100010;
18401let hasNewValue = 1;
18402let opNewValue = 0;
18403let prefersSlot3 = 1;
18404let Defs = [USR_OVF];
18405}
18406def S2_asl_i_r_xacc : HInst<
18407(outs IntRegs:$Rx32),
18408(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18409"$Rx32 ^= asl($Rs32,#$Ii)",
18410tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18411let Inst{7-5} = 0b010;
18412let Inst{13-13} = 0b0;
18413let Inst{31-21} = 0b10001110100;
18414let hasNewValue = 1;
18415let opNewValue = 0;
18416let prefersSlot3 = 1;
18417let Constraints = "$Rx32 = $Rx32in";
18418}
18419def S2_asl_i_vh : HInst<
18420(outs DoubleRegs:$Rdd32),
18421(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18422"$Rdd32 = vaslh($Rss32,#$Ii)",
18423tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18424let Inst{7-5} = 0b010;
18425let Inst{13-12} = 0b00;
18426let Inst{31-21} = 0b10000000100;
18427}
18428def S2_asl_i_vw : HInst<
18429(outs DoubleRegs:$Rdd32),
18430(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18431"$Rdd32 = vaslw($Rss32,#$Ii)",
18432tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18433let Inst{7-5} = 0b010;
18434let Inst{13-13} = 0b0;
18435let Inst{31-21} = 0b10000000010;
18436}
18437def S2_asl_r_p : HInst<
18438(outs DoubleRegs:$Rdd32),
18439(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18440"$Rdd32 = asl($Rss32,$Rt32)",
18441tc_5da50c4b, TypeS_3op>, Enc_927852 {
18442let Inst{7-5} = 0b100;
18443let Inst{13-13} = 0b0;
18444let Inst{31-21} = 0b11000011100;
18445}
18446def S2_asl_r_p_acc : HInst<
18447(outs DoubleRegs:$Rxx32),
18448(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18449"$Rxx32 += asl($Rss32,$Rt32)",
18450tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18451let Inst{7-5} = 0b100;
18452let Inst{13-13} = 0b0;
18453let Inst{31-21} = 0b11001011110;
18454let prefersSlot3 = 1;
18455let Constraints = "$Rxx32 = $Rxx32in";
18456}
18457def S2_asl_r_p_and : HInst<
18458(outs DoubleRegs:$Rxx32),
18459(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18460"$Rxx32 &= asl($Rss32,$Rt32)",
18461tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18462let Inst{7-5} = 0b100;
18463let Inst{13-13} = 0b0;
18464let Inst{31-21} = 0b11001011010;
18465let prefersSlot3 = 1;
18466let Constraints = "$Rxx32 = $Rxx32in";
18467}
18468def S2_asl_r_p_nac : HInst<
18469(outs DoubleRegs:$Rxx32),
18470(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18471"$Rxx32 -= asl($Rss32,$Rt32)",
18472tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18473let Inst{7-5} = 0b100;
18474let Inst{13-13} = 0b0;
18475let Inst{31-21} = 0b11001011100;
18476let prefersSlot3 = 1;
18477let Constraints = "$Rxx32 = $Rxx32in";
18478}
18479def S2_asl_r_p_or : HInst<
18480(outs DoubleRegs:$Rxx32),
18481(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18482"$Rxx32 |= asl($Rss32,$Rt32)",
18483tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18484let Inst{7-5} = 0b100;
18485let Inst{13-13} = 0b0;
18486let Inst{31-21} = 0b11001011000;
18487let prefersSlot3 = 1;
18488let Constraints = "$Rxx32 = $Rxx32in";
18489}
18490def S2_asl_r_p_xor : HInst<
18491(outs DoubleRegs:$Rxx32),
18492(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18493"$Rxx32 ^= asl($Rss32,$Rt32)",
18494tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18495let Inst{7-5} = 0b100;
18496let Inst{13-13} = 0b0;
18497let Inst{31-21} = 0b11001011011;
18498let prefersSlot3 = 1;
18499let Constraints = "$Rxx32 = $Rxx32in";
18500}
18501def S2_asl_r_r : HInst<
18502(outs IntRegs:$Rd32),
18503(ins IntRegs:$Rs32, IntRegs:$Rt32),
18504"$Rd32 = asl($Rs32,$Rt32)",
18505tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18506let Inst{7-5} = 0b100;
18507let Inst{13-13} = 0b0;
18508let Inst{31-21} = 0b11000110010;
18509let hasNewValue = 1;
18510let opNewValue = 0;
18511}
18512def S2_asl_r_r_acc : HInst<
18513(outs IntRegs:$Rx32),
18514(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18515"$Rx32 += asl($Rs32,$Rt32)",
18516tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18517let Inst{7-5} = 0b100;
18518let Inst{13-13} = 0b0;
18519let Inst{31-21} = 0b11001100110;
18520let hasNewValue = 1;
18521let opNewValue = 0;
18522let prefersSlot3 = 1;
18523let Constraints = "$Rx32 = $Rx32in";
18524}
18525def S2_asl_r_r_and : HInst<
18526(outs IntRegs:$Rx32),
18527(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18528"$Rx32 &= asl($Rs32,$Rt32)",
18529tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18530let Inst{7-5} = 0b100;
18531let Inst{13-13} = 0b0;
18532let Inst{31-21} = 0b11001100010;
18533let hasNewValue = 1;
18534let opNewValue = 0;
18535let prefersSlot3 = 1;
18536let Constraints = "$Rx32 = $Rx32in";
18537}
18538def S2_asl_r_r_nac : HInst<
18539(outs IntRegs:$Rx32),
18540(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18541"$Rx32 -= asl($Rs32,$Rt32)",
18542tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18543let Inst{7-5} = 0b100;
18544let Inst{13-13} = 0b0;
18545let Inst{31-21} = 0b11001100100;
18546let hasNewValue = 1;
18547let opNewValue = 0;
18548let prefersSlot3 = 1;
18549let Constraints = "$Rx32 = $Rx32in";
18550}
18551def S2_asl_r_r_or : HInst<
18552(outs IntRegs:$Rx32),
18553(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18554"$Rx32 |= asl($Rs32,$Rt32)",
18555tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18556let Inst{7-5} = 0b100;
18557let Inst{13-13} = 0b0;
18558let Inst{31-21} = 0b11001100000;
18559let hasNewValue = 1;
18560let opNewValue = 0;
18561let prefersSlot3 = 1;
18562let Constraints = "$Rx32 = $Rx32in";
18563}
18564def S2_asl_r_r_sat : HInst<
18565(outs IntRegs:$Rd32),
18566(ins IntRegs:$Rs32, IntRegs:$Rt32),
18567"$Rd32 = asl($Rs32,$Rt32):sat",
18568tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18569let Inst{7-5} = 0b100;
18570let Inst{13-13} = 0b0;
18571let Inst{31-21} = 0b11000110000;
18572let hasNewValue = 1;
18573let opNewValue = 0;
18574let prefersSlot3 = 1;
18575let Defs = [USR_OVF];
18576}
18577def S2_asl_r_vh : HInst<
18578(outs DoubleRegs:$Rdd32),
18579(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18580"$Rdd32 = vaslh($Rss32,$Rt32)",
18581tc_5da50c4b, TypeS_3op>, Enc_927852 {
18582let Inst{7-5} = 0b100;
18583let Inst{13-13} = 0b0;
18584let Inst{31-21} = 0b11000011010;
18585}
18586def S2_asl_r_vw : HInst<
18587(outs DoubleRegs:$Rdd32),
18588(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18589"$Rdd32 = vaslw($Rss32,$Rt32)",
18590tc_5da50c4b, TypeS_3op>, Enc_927852 {
18591let Inst{7-5} = 0b100;
18592let Inst{13-13} = 0b0;
18593let Inst{31-21} = 0b11000011000;
18594}
18595def S2_asr_i_p : HInst<
18596(outs DoubleRegs:$Rdd32),
18597(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18598"$Rdd32 = asr($Rss32,#$Ii)",
18599tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
18600let Inst{7-5} = 0b000;
18601let Inst{31-21} = 0b10000000000;
18602}
18603def S2_asr_i_p_acc : HInst<
18604(outs DoubleRegs:$Rxx32),
18605(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18606"$Rxx32 += asr($Rss32,#$Ii)",
18607tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18608let Inst{7-5} = 0b100;
18609let Inst{31-21} = 0b10000010000;
18610let prefersSlot3 = 1;
18611let Constraints = "$Rxx32 = $Rxx32in";
18612}
18613def S2_asr_i_p_and : HInst<
18614(outs DoubleRegs:$Rxx32),
18615(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18616"$Rxx32 &= asr($Rss32,#$Ii)",
18617tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18618let Inst{7-5} = 0b000;
18619let Inst{31-21} = 0b10000010010;
18620let prefersSlot3 = 1;
18621let Constraints = "$Rxx32 = $Rxx32in";
18622}
18623def S2_asr_i_p_nac : HInst<
18624(outs DoubleRegs:$Rxx32),
18625(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18626"$Rxx32 -= asr($Rss32,#$Ii)",
18627tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
18628let Inst{7-5} = 0b000;
18629let Inst{31-21} = 0b10000010000;
18630let prefersSlot3 = 1;
18631let Constraints = "$Rxx32 = $Rxx32in";
18632}
18633def S2_asr_i_p_or : HInst<
18634(outs DoubleRegs:$Rxx32),
18635(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
18636"$Rxx32 |= asr($Rss32,#$Ii)",
18637tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
18638let Inst{7-5} = 0b100;
18639let Inst{31-21} = 0b10000010010;
18640let prefersSlot3 = 1;
18641let Constraints = "$Rxx32 = $Rxx32in";
18642}
18643def S2_asr_i_p_rnd : HInst<
18644(outs DoubleRegs:$Rdd32),
18645(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18646"$Rdd32 = asr($Rss32,#$Ii):rnd",
18647tc_0dfac0a7, TypeS_2op>, Enc_5eac98 {
18648let Inst{7-5} = 0b111;
18649let Inst{31-21} = 0b10000000110;
18650let prefersSlot3 = 1;
18651}
18652def S2_asr_i_p_rnd_goodsyntax : HInst<
18653(outs DoubleRegs:$Rdd32),
18654(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
18655"$Rdd32 = asrrnd($Rss32,#$Ii)",
18656tc_0dfac0a7, TypeS_2op> {
18657let isPseudo = 1;
18658}
18659def S2_asr_i_r : HInst<
18660(outs IntRegs:$Rd32),
18661(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18662"$Rd32 = asr($Rs32,#$Ii)",
18663tc_5da50c4b, TypeS_2op>, Enc_a05677 {
18664let Inst{7-5} = 0b000;
18665let Inst{13-13} = 0b0;
18666let Inst{31-21} = 0b10001100000;
18667let hasNewValue = 1;
18668let opNewValue = 0;
18669}
18670def S2_asr_i_r_acc : HInst<
18671(outs IntRegs:$Rx32),
18672(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18673"$Rx32 += asr($Rs32,#$Ii)",
18674tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18675let Inst{7-5} = 0b100;
18676let Inst{13-13} = 0b0;
18677let Inst{31-21} = 0b10001110000;
18678let hasNewValue = 1;
18679let opNewValue = 0;
18680let prefersSlot3 = 1;
18681let Constraints = "$Rx32 = $Rx32in";
18682}
18683def S2_asr_i_r_and : HInst<
18684(outs IntRegs:$Rx32),
18685(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18686"$Rx32 &= asr($Rs32,#$Ii)",
18687tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18688let Inst{7-5} = 0b000;
18689let Inst{13-13} = 0b0;
18690let Inst{31-21} = 0b10001110010;
18691let hasNewValue = 1;
18692let opNewValue = 0;
18693let prefersSlot3 = 1;
18694let Constraints = "$Rx32 = $Rx32in";
18695}
18696def S2_asr_i_r_nac : HInst<
18697(outs IntRegs:$Rx32),
18698(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18699"$Rx32 -= asr($Rs32,#$Ii)",
18700tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
18701let Inst{7-5} = 0b000;
18702let Inst{13-13} = 0b0;
18703let Inst{31-21} = 0b10001110000;
18704let hasNewValue = 1;
18705let opNewValue = 0;
18706let prefersSlot3 = 1;
18707let Constraints = "$Rx32 = $Rx32in";
18708}
18709def S2_asr_i_r_or : HInst<
18710(outs IntRegs:$Rx32),
18711(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
18712"$Rx32 |= asr($Rs32,#$Ii)",
18713tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
18714let Inst{7-5} = 0b100;
18715let Inst{13-13} = 0b0;
18716let Inst{31-21} = 0b10001110010;
18717let hasNewValue = 1;
18718let opNewValue = 0;
18719let prefersSlot3 = 1;
18720let Constraints = "$Rx32 = $Rx32in";
18721}
18722def S2_asr_i_r_rnd : HInst<
18723(outs IntRegs:$Rd32),
18724(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18725"$Rd32 = asr($Rs32,#$Ii):rnd",
18726tc_0dfac0a7, TypeS_2op>, Enc_a05677 {
18727let Inst{7-5} = 0b000;
18728let Inst{13-13} = 0b0;
18729let Inst{31-21} = 0b10001100010;
18730let hasNewValue = 1;
18731let opNewValue = 0;
18732let prefersSlot3 = 1;
18733}
18734def S2_asr_i_r_rnd_goodsyntax : HInst<
18735(outs IntRegs:$Rd32),
18736(ins IntRegs:$Rs32, u5_0Imm:$Ii),
18737"$Rd32 = asrrnd($Rs32,#$Ii)",
18738tc_0dfac0a7, TypeS_2op> {
18739let hasNewValue = 1;
18740let opNewValue = 0;
18741let isPseudo = 1;
18742}
18743def S2_asr_i_svw_trun : HInst<
18744(outs IntRegs:$Rd32),
18745(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18746"$Rd32 = vasrw($Rss32,#$Ii)",
18747tc_f34c1c21, TypeS_2op>, Enc_8dec2e {
18748let Inst{7-5} = 0b010;
18749let Inst{13-13} = 0b0;
18750let Inst{31-21} = 0b10001000110;
18751let hasNewValue = 1;
18752let opNewValue = 0;
18753let prefersSlot3 = 1;
18754}
18755def S2_asr_i_vh : HInst<
18756(outs DoubleRegs:$Rdd32),
18757(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
18758"$Rdd32 = vasrh($Rss32,#$Ii)",
18759tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
18760let Inst{7-5} = 0b000;
18761let Inst{13-12} = 0b00;
18762let Inst{31-21} = 0b10000000100;
18763}
18764def S2_asr_i_vw : HInst<
18765(outs DoubleRegs:$Rdd32),
18766(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
18767"$Rdd32 = vasrw($Rss32,#$Ii)",
18768tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
18769let Inst{7-5} = 0b000;
18770let Inst{13-13} = 0b0;
18771let Inst{31-21} = 0b10000000010;
18772}
18773def S2_asr_r_p : HInst<
18774(outs DoubleRegs:$Rdd32),
18775(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18776"$Rdd32 = asr($Rss32,$Rt32)",
18777tc_5da50c4b, TypeS_3op>, Enc_927852 {
18778let Inst{7-5} = 0b000;
18779let Inst{13-13} = 0b0;
18780let Inst{31-21} = 0b11000011100;
18781}
18782def S2_asr_r_p_acc : HInst<
18783(outs DoubleRegs:$Rxx32),
18784(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18785"$Rxx32 += asr($Rss32,$Rt32)",
18786tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18787let Inst{7-5} = 0b000;
18788let Inst{13-13} = 0b0;
18789let Inst{31-21} = 0b11001011110;
18790let prefersSlot3 = 1;
18791let Constraints = "$Rxx32 = $Rxx32in";
18792}
18793def S2_asr_r_p_and : HInst<
18794(outs DoubleRegs:$Rxx32),
18795(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18796"$Rxx32 &= asr($Rss32,$Rt32)",
18797tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18798let Inst{7-5} = 0b000;
18799let Inst{13-13} = 0b0;
18800let Inst{31-21} = 0b11001011010;
18801let prefersSlot3 = 1;
18802let Constraints = "$Rxx32 = $Rxx32in";
18803}
18804def S2_asr_r_p_nac : HInst<
18805(outs DoubleRegs:$Rxx32),
18806(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18807"$Rxx32 -= asr($Rss32,$Rt32)",
18808tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
18809let Inst{7-5} = 0b000;
18810let Inst{13-13} = 0b0;
18811let Inst{31-21} = 0b11001011100;
18812let prefersSlot3 = 1;
18813let Constraints = "$Rxx32 = $Rxx32in";
18814}
18815def S2_asr_r_p_or : HInst<
18816(outs DoubleRegs:$Rxx32),
18817(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18818"$Rxx32 |= asr($Rss32,$Rt32)",
18819tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18820let Inst{7-5} = 0b000;
18821let Inst{13-13} = 0b0;
18822let Inst{31-21} = 0b11001011000;
18823let prefersSlot3 = 1;
18824let Constraints = "$Rxx32 = $Rxx32in";
18825}
18826def S2_asr_r_p_xor : HInst<
18827(outs DoubleRegs:$Rxx32),
18828(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
18829"$Rxx32 ^= asr($Rss32,$Rt32)",
18830tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
18831let Inst{7-5} = 0b000;
18832let Inst{13-13} = 0b0;
18833let Inst{31-21} = 0b11001011011;
18834let prefersSlot3 = 1;
18835let Constraints = "$Rxx32 = $Rxx32in";
18836}
18837def S2_asr_r_r : HInst<
18838(outs IntRegs:$Rd32),
18839(ins IntRegs:$Rs32, IntRegs:$Rt32),
18840"$Rd32 = asr($Rs32,$Rt32)",
18841tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
18842let Inst{7-5} = 0b000;
18843let Inst{13-13} = 0b0;
18844let Inst{31-21} = 0b11000110010;
18845let hasNewValue = 1;
18846let opNewValue = 0;
18847}
18848def S2_asr_r_r_acc : HInst<
18849(outs IntRegs:$Rx32),
18850(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18851"$Rx32 += asr($Rs32,$Rt32)",
18852tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18853let Inst{7-5} = 0b000;
18854let Inst{13-13} = 0b0;
18855let Inst{31-21} = 0b11001100110;
18856let hasNewValue = 1;
18857let opNewValue = 0;
18858let prefersSlot3 = 1;
18859let Constraints = "$Rx32 = $Rx32in";
18860}
18861def S2_asr_r_r_and : HInst<
18862(outs IntRegs:$Rx32),
18863(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18864"$Rx32 &= asr($Rs32,$Rt32)",
18865tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18866let Inst{7-5} = 0b000;
18867let Inst{13-13} = 0b0;
18868let Inst{31-21} = 0b11001100010;
18869let hasNewValue = 1;
18870let opNewValue = 0;
18871let prefersSlot3 = 1;
18872let Constraints = "$Rx32 = $Rx32in";
18873}
18874def S2_asr_r_r_nac : HInst<
18875(outs IntRegs:$Rx32),
18876(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18877"$Rx32 -= asr($Rs32,$Rt32)",
18878tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
18879let Inst{7-5} = 0b000;
18880let Inst{13-13} = 0b0;
18881let Inst{31-21} = 0b11001100100;
18882let hasNewValue = 1;
18883let opNewValue = 0;
18884let prefersSlot3 = 1;
18885let Constraints = "$Rx32 = $Rx32in";
18886}
18887def S2_asr_r_r_or : HInst<
18888(outs IntRegs:$Rx32),
18889(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
18890"$Rx32 |= asr($Rs32,$Rt32)",
18891tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
18892let Inst{7-5} = 0b000;
18893let Inst{13-13} = 0b0;
18894let Inst{31-21} = 0b11001100000;
18895let hasNewValue = 1;
18896let opNewValue = 0;
18897let prefersSlot3 = 1;
18898let Constraints = "$Rx32 = $Rx32in";
18899}
18900def S2_asr_r_r_sat : HInst<
18901(outs IntRegs:$Rd32),
18902(ins IntRegs:$Rs32, IntRegs:$Rt32),
18903"$Rd32 = asr($Rs32,$Rt32):sat",
18904tc_8a825db2, TypeS_3op>, Enc_5ab2be {
18905let Inst{7-5} = 0b000;
18906let Inst{13-13} = 0b0;
18907let Inst{31-21} = 0b11000110000;
18908let hasNewValue = 1;
18909let opNewValue = 0;
18910let prefersSlot3 = 1;
18911let Defs = [USR_OVF];
18912}
18913def S2_asr_r_svw_trun : HInst<
18914(outs IntRegs:$Rd32),
18915(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18916"$Rd32 = vasrw($Rss32,$Rt32)",
18917tc_f34c1c21, TypeS_3op>, Enc_3d5b28 {
18918let Inst{7-5} = 0b010;
18919let Inst{13-13} = 0b0;
18920let Inst{31-21} = 0b11000101000;
18921let hasNewValue = 1;
18922let opNewValue = 0;
18923let prefersSlot3 = 1;
18924}
18925def S2_asr_r_vh : HInst<
18926(outs DoubleRegs:$Rdd32),
18927(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18928"$Rdd32 = vasrh($Rss32,$Rt32)",
18929tc_5da50c4b, TypeS_3op>, Enc_927852 {
18930let Inst{7-5} = 0b000;
18931let Inst{13-13} = 0b0;
18932let Inst{31-21} = 0b11000011010;
18933}
18934def S2_asr_r_vw : HInst<
18935(outs DoubleRegs:$Rdd32),
18936(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
18937"$Rdd32 = vasrw($Rss32,$Rt32)",
18938tc_5da50c4b, TypeS_3op>, Enc_927852 {
18939let Inst{7-5} = 0b000;
18940let Inst{13-13} = 0b0;
18941let Inst{31-21} = 0b11000011000;
18942}
18943def S2_brev : HInst<
18944(outs IntRegs:$Rd32),
18945(ins IntRegs:$Rs32),
18946"$Rd32 = brev($Rs32)",
18947tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18948let Inst{13-5} = 0b000000110;
18949let Inst{31-21} = 0b10001100010;
18950let hasNewValue = 1;
18951let opNewValue = 0;
18952let prefersSlot3 = 1;
18953}
18954def S2_brevp : HInst<
18955(outs DoubleRegs:$Rdd32),
18956(ins DoubleRegs:$Rss32),
18957"$Rdd32 = brev($Rss32)",
18958tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
18959let Inst{13-5} = 0b000000110;
18960let Inst{31-21} = 0b10000000110;
18961let prefersSlot3 = 1;
18962}
18963def S2_cabacdecbin : HInst<
18964(outs DoubleRegs:$Rdd32),
18965(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
18966"$Rdd32 = decbin($Rss32,$Rtt32)",
18967tc_db596beb, TypeS_3op>, Enc_a56825 {
18968let Inst{7-5} = 0b110;
18969let Inst{13-13} = 0b0;
18970let Inst{31-21} = 0b11000001110;
18971let isPredicateLate = 1;
18972let prefersSlot3 = 1;
18973let Defs = [P0];
18974}
18975def S2_cl0 : HInst<
18976(outs IntRegs:$Rd32),
18977(ins IntRegs:$Rs32),
18978"$Rd32 = cl0($Rs32)",
18979tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
18980let Inst{13-5} = 0b000000101;
18981let Inst{31-21} = 0b10001100000;
18982let hasNewValue = 1;
18983let opNewValue = 0;
18984let prefersSlot3 = 1;
18985}
18986def S2_cl0p : HInst<
18987(outs IntRegs:$Rd32),
18988(ins DoubleRegs:$Rss32),
18989"$Rd32 = cl0($Rss32)",
18990tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
18991let Inst{13-5} = 0b000000010;
18992let Inst{31-21} = 0b10001000010;
18993let hasNewValue = 1;
18994let opNewValue = 0;
18995let prefersSlot3 = 1;
18996}
18997def S2_cl1 : HInst<
18998(outs IntRegs:$Rd32),
18999(ins IntRegs:$Rs32),
19000"$Rd32 = cl1($Rs32)",
19001tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19002let Inst{13-5} = 0b000000110;
19003let Inst{31-21} = 0b10001100000;
19004let hasNewValue = 1;
19005let opNewValue = 0;
19006let prefersSlot3 = 1;
19007}
19008def S2_cl1p : HInst<
19009(outs IntRegs:$Rd32),
19010(ins DoubleRegs:$Rss32),
19011"$Rd32 = cl1($Rss32)",
19012tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19013let Inst{13-5} = 0b000000100;
19014let Inst{31-21} = 0b10001000010;
19015let hasNewValue = 1;
19016let opNewValue = 0;
19017let prefersSlot3 = 1;
19018}
19019def S2_clb : HInst<
19020(outs IntRegs:$Rd32),
19021(ins IntRegs:$Rs32),
19022"$Rd32 = clb($Rs32)",
19023tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19024let Inst{13-5} = 0b000000100;
19025let Inst{31-21} = 0b10001100000;
19026let hasNewValue = 1;
19027let opNewValue = 0;
19028let prefersSlot3 = 1;
19029}
19030def S2_clbnorm : HInst<
19031(outs IntRegs:$Rd32),
19032(ins IntRegs:$Rs32),
19033"$Rd32 = normamt($Rs32)",
19034tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19035let Inst{13-5} = 0b000000111;
19036let Inst{31-21} = 0b10001100000;
19037let hasNewValue = 1;
19038let opNewValue = 0;
19039let prefersSlot3 = 1;
19040}
19041def S2_clbp : HInst<
19042(outs IntRegs:$Rd32),
19043(ins DoubleRegs:$Rss32),
19044"$Rd32 = clb($Rss32)",
19045tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19046let Inst{13-5} = 0b000000000;
19047let Inst{31-21} = 0b10001000010;
19048let hasNewValue = 1;
19049let opNewValue = 0;
19050let prefersSlot3 = 1;
19051}
19052def S2_clrbit_i : HInst<
19053(outs IntRegs:$Rd32),
19054(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19055"$Rd32 = clrbit($Rs32,#$Ii)",
19056tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19057let Inst{7-5} = 0b001;
19058let Inst{13-13} = 0b0;
19059let Inst{31-21} = 0b10001100110;
19060let hasNewValue = 1;
19061let opNewValue = 0;
19062}
19063def S2_clrbit_r : HInst<
19064(outs IntRegs:$Rd32),
19065(ins IntRegs:$Rs32, IntRegs:$Rt32),
19066"$Rd32 = clrbit($Rs32,$Rt32)",
19067tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19068let Inst{7-5} = 0b010;
19069let Inst{13-13} = 0b0;
19070let Inst{31-21} = 0b11000110100;
19071let hasNewValue = 1;
19072let opNewValue = 0;
19073}
19074def S2_ct0 : HInst<
19075(outs IntRegs:$Rd32),
19076(ins IntRegs:$Rs32),
19077"$Rd32 = ct0($Rs32)",
19078tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19079let Inst{13-5} = 0b000000100;
19080let Inst{31-21} = 0b10001100010;
19081let hasNewValue = 1;
19082let opNewValue = 0;
19083let prefersSlot3 = 1;
19084}
19085def S2_ct0p : HInst<
19086(outs IntRegs:$Rd32),
19087(ins DoubleRegs:$Rss32),
19088"$Rd32 = ct0($Rss32)",
19089tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19090let Inst{13-5} = 0b000000010;
19091let Inst{31-21} = 0b10001000111;
19092let hasNewValue = 1;
19093let opNewValue = 0;
19094let prefersSlot3 = 1;
19095}
19096def S2_ct1 : HInst<
19097(outs IntRegs:$Rd32),
19098(ins IntRegs:$Rs32),
19099"$Rd32 = ct1($Rs32)",
19100tc_a7bdb22c, TypeS_2op>, Enc_5e2823 {
19101let Inst{13-5} = 0b000000101;
19102let Inst{31-21} = 0b10001100010;
19103let hasNewValue = 1;
19104let opNewValue = 0;
19105let prefersSlot3 = 1;
19106}
19107def S2_ct1p : HInst<
19108(outs IntRegs:$Rd32),
19109(ins DoubleRegs:$Rss32),
19110"$Rd32 = ct1($Rss32)",
19111tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
19112let Inst{13-5} = 0b000000100;
19113let Inst{31-21} = 0b10001000111;
19114let hasNewValue = 1;
19115let opNewValue = 0;
19116let prefersSlot3 = 1;
19117}
19118def S2_deinterleave : HInst<
19119(outs DoubleRegs:$Rdd32),
19120(ins DoubleRegs:$Rss32),
19121"$Rdd32 = deinterleave($Rss32)",
19122tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19123let Inst{13-5} = 0b000000100;
19124let Inst{31-21} = 0b10000000110;
19125let prefersSlot3 = 1;
19126}
19127def S2_extractu : HInst<
19128(outs IntRegs:$Rd32),
19129(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19130"$Rd32 = extractu($Rs32,#$Ii,#$II)",
19131tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
19132let Inst{13-13} = 0b0;
19133let Inst{31-23} = 0b100011010;
19134let hasNewValue = 1;
19135let opNewValue = 0;
19136let prefersSlot3 = 1;
19137}
19138def S2_extractu_rp : HInst<
19139(outs IntRegs:$Rd32),
19140(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
19141"$Rd32 = extractu($Rs32,$Rtt32)",
19142tc_a08b630b, TypeS_3op>, Enc_e07374 {
19143let Inst{7-5} = 0b000;
19144let Inst{13-13} = 0b0;
19145let Inst{31-21} = 0b11001001000;
19146let hasNewValue = 1;
19147let opNewValue = 0;
19148let prefersSlot3 = 1;
19149}
19150def S2_extractup : HInst<
19151(outs DoubleRegs:$Rdd32),
19152(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19153"$Rdd32 = extractu($Rss32,#$Ii,#$II)",
19154tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
19155let Inst{31-24} = 0b10000001;
19156let prefersSlot3 = 1;
19157}
19158def S2_extractup_rp : HInst<
19159(outs DoubleRegs:$Rdd32),
19160(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19161"$Rdd32 = extractu($Rss32,$Rtt32)",
19162tc_a08b630b, TypeS_3op>, Enc_a56825 {
19163let Inst{7-5} = 0b000;
19164let Inst{13-13} = 0b0;
19165let Inst{31-21} = 0b11000001000;
19166let prefersSlot3 = 1;
19167}
19168def S2_insert : HInst<
19169(outs IntRegs:$Rx32),
19170(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
19171"$Rx32 = insert($Rs32,#$Ii,#$II)",
19172tc_bb831a7c, TypeS_2op>, Enc_a1e29d {
19173let Inst{13-13} = 0b0;
19174let Inst{31-23} = 0b100011110;
19175let hasNewValue = 1;
19176let opNewValue = 0;
19177let prefersSlot3 = 1;
19178let Constraints = "$Rx32 = $Rx32in";
19179}
19180def S2_insert_rp : HInst<
19181(outs IntRegs:$Rx32),
19182(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32),
19183"$Rx32 = insert($Rs32,$Rtt32)",
19184tc_a4e22bbd, TypeS_3op>, Enc_179b35 {
19185let Inst{7-5} = 0b000;
19186let Inst{13-13} = 0b0;
19187let Inst{31-21} = 0b11001000000;
19188let hasNewValue = 1;
19189let opNewValue = 0;
19190let prefersSlot3 = 1;
19191let Constraints = "$Rx32 = $Rx32in";
19192}
19193def S2_insertp : HInst<
19194(outs DoubleRegs:$Rxx32),
19195(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
19196"$Rxx32 = insert($Rss32,#$Ii,#$II)",
19197tc_bb831a7c, TypeS_2op>, Enc_143a3c {
19198let Inst{31-24} = 0b10000011;
19199let prefersSlot3 = 1;
19200let Constraints = "$Rxx32 = $Rxx32in";
19201}
19202def S2_insertp_rp : HInst<
19203(outs DoubleRegs:$Rxx32),
19204(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19205"$Rxx32 = insert($Rss32,$Rtt32)",
19206tc_a4e22bbd, TypeS_3op>, Enc_88c16c {
19207let Inst{7-5} = 0b000;
19208let Inst{13-13} = 0b0;
19209let Inst{31-21} = 0b11001010000;
19210let prefersSlot3 = 1;
19211let Constraints = "$Rxx32 = $Rxx32in";
19212}
19213def S2_interleave : HInst<
19214(outs DoubleRegs:$Rdd32),
19215(ins DoubleRegs:$Rss32),
19216"$Rdd32 = interleave($Rss32)",
19217tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb {
19218let Inst{13-5} = 0b000000101;
19219let Inst{31-21} = 0b10000000110;
19220let prefersSlot3 = 1;
19221}
19222def S2_lfsp : HInst<
19223(outs DoubleRegs:$Rdd32),
19224(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19225"$Rdd32 = lfs($Rss32,$Rtt32)",
19226tc_a08b630b, TypeS_3op>, Enc_a56825 {
19227let Inst{7-5} = 0b110;
19228let Inst{13-13} = 0b0;
19229let Inst{31-21} = 0b11000001100;
19230let prefersSlot3 = 1;
19231}
19232def S2_lsl_r_p : HInst<
19233(outs DoubleRegs:$Rdd32),
19234(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19235"$Rdd32 = lsl($Rss32,$Rt32)",
19236tc_5da50c4b, TypeS_3op>, Enc_927852 {
19237let Inst{7-5} = 0b110;
19238let Inst{13-13} = 0b0;
19239let Inst{31-21} = 0b11000011100;
19240}
19241def S2_lsl_r_p_acc : HInst<
19242(outs DoubleRegs:$Rxx32),
19243(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19244"$Rxx32 += lsl($Rss32,$Rt32)",
19245tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19246let Inst{7-5} = 0b110;
19247let Inst{13-13} = 0b0;
19248let Inst{31-21} = 0b11001011110;
19249let prefersSlot3 = 1;
19250let Constraints = "$Rxx32 = $Rxx32in";
19251}
19252def S2_lsl_r_p_and : HInst<
19253(outs DoubleRegs:$Rxx32),
19254(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19255"$Rxx32 &= lsl($Rss32,$Rt32)",
19256tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19257let Inst{7-5} = 0b110;
19258let Inst{13-13} = 0b0;
19259let Inst{31-21} = 0b11001011010;
19260let prefersSlot3 = 1;
19261let Constraints = "$Rxx32 = $Rxx32in";
19262}
19263def S2_lsl_r_p_nac : HInst<
19264(outs DoubleRegs:$Rxx32),
19265(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19266"$Rxx32 -= lsl($Rss32,$Rt32)",
19267tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19268let Inst{7-5} = 0b110;
19269let Inst{13-13} = 0b0;
19270let Inst{31-21} = 0b11001011100;
19271let prefersSlot3 = 1;
19272let Constraints = "$Rxx32 = $Rxx32in";
19273}
19274def S2_lsl_r_p_or : HInst<
19275(outs DoubleRegs:$Rxx32),
19276(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19277"$Rxx32 |= lsl($Rss32,$Rt32)",
19278tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19279let Inst{7-5} = 0b110;
19280let Inst{13-13} = 0b0;
19281let Inst{31-21} = 0b11001011000;
19282let prefersSlot3 = 1;
19283let Constraints = "$Rxx32 = $Rxx32in";
19284}
19285def S2_lsl_r_p_xor : HInst<
19286(outs DoubleRegs:$Rxx32),
19287(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19288"$Rxx32 ^= lsl($Rss32,$Rt32)",
19289tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19290let Inst{7-5} = 0b110;
19291let Inst{13-13} = 0b0;
19292let Inst{31-21} = 0b11001011011;
19293let prefersSlot3 = 1;
19294let Constraints = "$Rxx32 = $Rxx32in";
19295}
19296def S2_lsl_r_r : HInst<
19297(outs IntRegs:$Rd32),
19298(ins IntRegs:$Rs32, IntRegs:$Rt32),
19299"$Rd32 = lsl($Rs32,$Rt32)",
19300tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19301let Inst{7-5} = 0b110;
19302let Inst{13-13} = 0b0;
19303let Inst{31-21} = 0b11000110010;
19304let hasNewValue = 1;
19305let opNewValue = 0;
19306}
19307def S2_lsl_r_r_acc : HInst<
19308(outs IntRegs:$Rx32),
19309(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19310"$Rx32 += lsl($Rs32,$Rt32)",
19311tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19312let Inst{7-5} = 0b110;
19313let Inst{13-13} = 0b0;
19314let Inst{31-21} = 0b11001100110;
19315let hasNewValue = 1;
19316let opNewValue = 0;
19317let prefersSlot3 = 1;
19318let Constraints = "$Rx32 = $Rx32in";
19319}
19320def S2_lsl_r_r_and : HInst<
19321(outs IntRegs:$Rx32),
19322(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19323"$Rx32 &= lsl($Rs32,$Rt32)",
19324tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19325let Inst{7-5} = 0b110;
19326let Inst{13-13} = 0b0;
19327let Inst{31-21} = 0b11001100010;
19328let hasNewValue = 1;
19329let opNewValue = 0;
19330let prefersSlot3 = 1;
19331let Constraints = "$Rx32 = $Rx32in";
19332}
19333def S2_lsl_r_r_nac : HInst<
19334(outs IntRegs:$Rx32),
19335(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19336"$Rx32 -= lsl($Rs32,$Rt32)",
19337tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19338let Inst{7-5} = 0b110;
19339let Inst{13-13} = 0b0;
19340let Inst{31-21} = 0b11001100100;
19341let hasNewValue = 1;
19342let opNewValue = 0;
19343let prefersSlot3 = 1;
19344let Constraints = "$Rx32 = $Rx32in";
19345}
19346def S2_lsl_r_r_or : HInst<
19347(outs IntRegs:$Rx32),
19348(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19349"$Rx32 |= lsl($Rs32,$Rt32)",
19350tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19351let Inst{7-5} = 0b110;
19352let Inst{13-13} = 0b0;
19353let Inst{31-21} = 0b11001100000;
19354let hasNewValue = 1;
19355let opNewValue = 0;
19356let prefersSlot3 = 1;
19357let Constraints = "$Rx32 = $Rx32in";
19358}
19359def S2_lsl_r_vh : HInst<
19360(outs DoubleRegs:$Rdd32),
19361(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19362"$Rdd32 = vlslh($Rss32,$Rt32)",
19363tc_5da50c4b, TypeS_3op>, Enc_927852 {
19364let Inst{7-5} = 0b110;
19365let Inst{13-13} = 0b0;
19366let Inst{31-21} = 0b11000011010;
19367}
19368def S2_lsl_r_vw : HInst<
19369(outs DoubleRegs:$Rdd32),
19370(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19371"$Rdd32 = vlslw($Rss32,$Rt32)",
19372tc_5da50c4b, TypeS_3op>, Enc_927852 {
19373let Inst{7-5} = 0b110;
19374let Inst{13-13} = 0b0;
19375let Inst{31-21} = 0b11000011000;
19376}
19377def S2_lsr_i_p : HInst<
19378(outs DoubleRegs:$Rdd32),
19379(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
19380"$Rdd32 = lsr($Rss32,#$Ii)",
19381tc_5da50c4b, TypeS_2op>, Enc_5eac98 {
19382let Inst{7-5} = 0b001;
19383let Inst{31-21} = 0b10000000000;
19384}
19385def S2_lsr_i_p_acc : HInst<
19386(outs DoubleRegs:$Rxx32),
19387(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19388"$Rxx32 += lsr($Rss32,#$Ii)",
19389tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19390let Inst{7-5} = 0b101;
19391let Inst{31-21} = 0b10000010000;
19392let prefersSlot3 = 1;
19393let Constraints = "$Rxx32 = $Rxx32in";
19394}
19395def S2_lsr_i_p_and : HInst<
19396(outs DoubleRegs:$Rxx32),
19397(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19398"$Rxx32 &= lsr($Rss32,#$Ii)",
19399tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19400let Inst{7-5} = 0b001;
19401let Inst{31-21} = 0b10000010010;
19402let prefersSlot3 = 1;
19403let Constraints = "$Rxx32 = $Rxx32in";
19404}
19405def S2_lsr_i_p_nac : HInst<
19406(outs DoubleRegs:$Rxx32),
19407(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19408"$Rxx32 -= lsr($Rss32,#$Ii)",
19409tc_2c13e7f5, TypeS_2op>, Enc_70fb07 {
19410let Inst{7-5} = 0b001;
19411let Inst{31-21} = 0b10000010000;
19412let prefersSlot3 = 1;
19413let Constraints = "$Rxx32 = $Rxx32in";
19414}
19415def S2_lsr_i_p_or : HInst<
19416(outs DoubleRegs:$Rxx32),
19417(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19418"$Rxx32 |= lsr($Rss32,#$Ii)",
19419tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19420let Inst{7-5} = 0b101;
19421let Inst{31-21} = 0b10000010010;
19422let prefersSlot3 = 1;
19423let Constraints = "$Rxx32 = $Rxx32in";
19424}
19425def S2_lsr_i_p_xacc : HInst<
19426(outs DoubleRegs:$Rxx32),
19427(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
19428"$Rxx32 ^= lsr($Rss32,#$Ii)",
19429tc_a4e22bbd, TypeS_2op>, Enc_70fb07 {
19430let Inst{7-5} = 0b001;
19431let Inst{31-21} = 0b10000010100;
19432let prefersSlot3 = 1;
19433let Constraints = "$Rxx32 = $Rxx32in";
19434}
19435def S2_lsr_i_r : HInst<
19436(outs IntRegs:$Rd32),
19437(ins IntRegs:$Rs32, u5_0Imm:$Ii),
19438"$Rd32 = lsr($Rs32,#$Ii)",
19439tc_5da50c4b, TypeS_2op>, Enc_a05677 {
19440let Inst{7-5} = 0b001;
19441let Inst{13-13} = 0b0;
19442let Inst{31-21} = 0b10001100000;
19443let hasNewValue = 1;
19444let opNewValue = 0;
19445}
19446def S2_lsr_i_r_acc : HInst<
19447(outs IntRegs:$Rx32),
19448(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19449"$Rx32 += lsr($Rs32,#$Ii)",
19450tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19451let Inst{7-5} = 0b101;
19452let Inst{13-13} = 0b0;
19453let Inst{31-21} = 0b10001110000;
19454let hasNewValue = 1;
19455let opNewValue = 0;
19456let prefersSlot3 = 1;
19457let Constraints = "$Rx32 = $Rx32in";
19458}
19459def S2_lsr_i_r_and : HInst<
19460(outs IntRegs:$Rx32),
19461(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19462"$Rx32 &= lsr($Rs32,#$Ii)",
19463tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19464let Inst{7-5} = 0b001;
19465let Inst{13-13} = 0b0;
19466let Inst{31-21} = 0b10001110010;
19467let hasNewValue = 1;
19468let opNewValue = 0;
19469let prefersSlot3 = 1;
19470let Constraints = "$Rx32 = $Rx32in";
19471}
19472def S2_lsr_i_r_nac : HInst<
19473(outs IntRegs:$Rx32),
19474(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19475"$Rx32 -= lsr($Rs32,#$Ii)",
19476tc_2c13e7f5, TypeS_2op>, Enc_28a2dc {
19477let Inst{7-5} = 0b001;
19478let Inst{13-13} = 0b0;
19479let Inst{31-21} = 0b10001110000;
19480let hasNewValue = 1;
19481let opNewValue = 0;
19482let prefersSlot3 = 1;
19483let Constraints = "$Rx32 = $Rx32in";
19484}
19485def S2_lsr_i_r_or : HInst<
19486(outs IntRegs:$Rx32),
19487(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19488"$Rx32 |= lsr($Rs32,#$Ii)",
19489tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19490let Inst{7-5} = 0b101;
19491let Inst{13-13} = 0b0;
19492let Inst{31-21} = 0b10001110010;
19493let hasNewValue = 1;
19494let opNewValue = 0;
19495let prefersSlot3 = 1;
19496let Constraints = "$Rx32 = $Rx32in";
19497}
19498def S2_lsr_i_r_xacc : HInst<
19499(outs IntRegs:$Rx32),
19500(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
19501"$Rx32 ^= lsr($Rs32,#$Ii)",
19502tc_a4e22bbd, TypeS_2op>, Enc_28a2dc {
19503let Inst{7-5} = 0b001;
19504let Inst{13-13} = 0b0;
19505let Inst{31-21} = 0b10001110100;
19506let hasNewValue = 1;
19507let opNewValue = 0;
19508let prefersSlot3 = 1;
19509let Constraints = "$Rx32 = $Rx32in";
19510}
19511def S2_lsr_i_vh : HInst<
19512(outs DoubleRegs:$Rdd32),
19513(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
19514"$Rdd32 = vlsrh($Rss32,#$Ii)",
19515tc_5da50c4b, TypeS_2op>, Enc_12b6e9 {
19516let Inst{7-5} = 0b001;
19517let Inst{13-12} = 0b00;
19518let Inst{31-21} = 0b10000000100;
19519}
19520def S2_lsr_i_vw : HInst<
19521(outs DoubleRegs:$Rdd32),
19522(ins DoubleRegs:$Rss32, u5_0Imm:$Ii),
19523"$Rdd32 = vlsrw($Rss32,#$Ii)",
19524tc_5da50c4b, TypeS_2op>, Enc_7e5a82 {
19525let Inst{7-5} = 0b001;
19526let Inst{13-13} = 0b0;
19527let Inst{31-21} = 0b10000000010;
19528}
19529def S2_lsr_r_p : HInst<
19530(outs DoubleRegs:$Rdd32),
19531(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19532"$Rdd32 = lsr($Rss32,$Rt32)",
19533tc_5da50c4b, TypeS_3op>, Enc_927852 {
19534let Inst{7-5} = 0b010;
19535let Inst{13-13} = 0b0;
19536let Inst{31-21} = 0b11000011100;
19537}
19538def S2_lsr_r_p_acc : HInst<
19539(outs DoubleRegs:$Rxx32),
19540(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19541"$Rxx32 += lsr($Rss32,$Rt32)",
19542tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19543let Inst{7-5} = 0b010;
19544let Inst{13-13} = 0b0;
19545let Inst{31-21} = 0b11001011110;
19546let prefersSlot3 = 1;
19547let Constraints = "$Rxx32 = $Rxx32in";
19548}
19549def S2_lsr_r_p_and : HInst<
19550(outs DoubleRegs:$Rxx32),
19551(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19552"$Rxx32 &= lsr($Rss32,$Rt32)",
19553tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19554let Inst{7-5} = 0b010;
19555let Inst{13-13} = 0b0;
19556let Inst{31-21} = 0b11001011010;
19557let prefersSlot3 = 1;
19558let Constraints = "$Rxx32 = $Rxx32in";
19559}
19560def S2_lsr_r_p_nac : HInst<
19561(outs DoubleRegs:$Rxx32),
19562(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19563"$Rxx32 -= lsr($Rss32,$Rt32)",
19564tc_2c13e7f5, TypeS_3op>, Enc_1aa186 {
19565let Inst{7-5} = 0b010;
19566let Inst{13-13} = 0b0;
19567let Inst{31-21} = 0b11001011100;
19568let prefersSlot3 = 1;
19569let Constraints = "$Rxx32 = $Rxx32in";
19570}
19571def S2_lsr_r_p_or : HInst<
19572(outs DoubleRegs:$Rxx32),
19573(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19574"$Rxx32 |= lsr($Rss32,$Rt32)",
19575tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19576let Inst{7-5} = 0b010;
19577let Inst{13-13} = 0b0;
19578let Inst{31-21} = 0b11001011000;
19579let prefersSlot3 = 1;
19580let Constraints = "$Rxx32 = $Rxx32in";
19581}
19582def S2_lsr_r_p_xor : HInst<
19583(outs DoubleRegs:$Rxx32),
19584(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
19585"$Rxx32 ^= lsr($Rss32,$Rt32)",
19586tc_a4e22bbd, TypeS_3op>, Enc_1aa186 {
19587let Inst{7-5} = 0b010;
19588let Inst{13-13} = 0b0;
19589let Inst{31-21} = 0b11001011011;
19590let prefersSlot3 = 1;
19591let Constraints = "$Rxx32 = $Rxx32in";
19592}
19593def S2_lsr_r_r : HInst<
19594(outs IntRegs:$Rd32),
19595(ins IntRegs:$Rs32, IntRegs:$Rt32),
19596"$Rd32 = lsr($Rs32,$Rt32)",
19597tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
19598let Inst{7-5} = 0b010;
19599let Inst{13-13} = 0b0;
19600let Inst{31-21} = 0b11000110010;
19601let hasNewValue = 1;
19602let opNewValue = 0;
19603}
19604def S2_lsr_r_r_acc : HInst<
19605(outs IntRegs:$Rx32),
19606(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19607"$Rx32 += lsr($Rs32,$Rt32)",
19608tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19609let Inst{7-5} = 0b010;
19610let Inst{13-13} = 0b0;
19611let Inst{31-21} = 0b11001100110;
19612let hasNewValue = 1;
19613let opNewValue = 0;
19614let prefersSlot3 = 1;
19615let Constraints = "$Rx32 = $Rx32in";
19616}
19617def S2_lsr_r_r_and : HInst<
19618(outs IntRegs:$Rx32),
19619(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19620"$Rx32 &= lsr($Rs32,$Rt32)",
19621tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19622let Inst{7-5} = 0b010;
19623let Inst{13-13} = 0b0;
19624let Inst{31-21} = 0b11001100010;
19625let hasNewValue = 1;
19626let opNewValue = 0;
19627let prefersSlot3 = 1;
19628let Constraints = "$Rx32 = $Rx32in";
19629}
19630def S2_lsr_r_r_nac : HInst<
19631(outs IntRegs:$Rx32),
19632(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19633"$Rx32 -= lsr($Rs32,$Rt32)",
19634tc_2c13e7f5, TypeS_3op>, Enc_2ae154 {
19635let Inst{7-5} = 0b010;
19636let Inst{13-13} = 0b0;
19637let Inst{31-21} = 0b11001100100;
19638let hasNewValue = 1;
19639let opNewValue = 0;
19640let prefersSlot3 = 1;
19641let Constraints = "$Rx32 = $Rx32in";
19642}
19643def S2_lsr_r_r_or : HInst<
19644(outs IntRegs:$Rx32),
19645(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
19646"$Rx32 |= lsr($Rs32,$Rt32)",
19647tc_a4e22bbd, TypeS_3op>, Enc_2ae154 {
19648let Inst{7-5} = 0b010;
19649let Inst{13-13} = 0b0;
19650let Inst{31-21} = 0b11001100000;
19651let hasNewValue = 1;
19652let opNewValue = 0;
19653let prefersSlot3 = 1;
19654let Constraints = "$Rx32 = $Rx32in";
19655}
19656def S2_lsr_r_vh : HInst<
19657(outs DoubleRegs:$Rdd32),
19658(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19659"$Rdd32 = vlsrh($Rss32,$Rt32)",
19660tc_5da50c4b, TypeS_3op>, Enc_927852 {
19661let Inst{7-5} = 0b010;
19662let Inst{13-13} = 0b0;
19663let Inst{31-21} = 0b11000011010;
19664}
19665def S2_lsr_r_vw : HInst<
19666(outs DoubleRegs:$Rdd32),
19667(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
19668"$Rdd32 = vlsrw($Rss32,$Rt32)",
19669tc_5da50c4b, TypeS_3op>, Enc_927852 {
19670let Inst{7-5} = 0b010;
19671let Inst{13-13} = 0b0;
19672let Inst{31-21} = 0b11000011000;
19673}
19674def S2_mask : HInst<
19675(outs IntRegs:$Rd32),
19676(ins u5_0Imm:$Ii, u5_0Imm:$II),
19677"$Rd32 = mask(#$Ii,#$II)",
19678tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> {
19679let Inst{13-13} = 0b1;
19680let Inst{20-16} = 0b00000;
19681let Inst{31-23} = 0b100011010;
19682let hasNewValue = 1;
19683let opNewValue = 0;
19684let prefersSlot3 = 1;
19685}
19686def S2_packhl : HInst<
19687(outs DoubleRegs:$Rdd32),
19688(ins IntRegs:$Rs32, IntRegs:$Rt32),
19689"$Rdd32 = packhl($Rs32,$Rt32)",
19690tc_713b66bf, TypeALU32_3op>, Enc_be32a5 {
19691let Inst{7-5} = 0b000;
19692let Inst{13-13} = 0b0;
19693let Inst{31-21} = 0b11110101100;
19694let InputType = "reg";
19695}
19696def S2_parityp : HInst<
19697(outs IntRegs:$Rd32),
19698(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
19699"$Rd32 = parity($Rss32,$Rtt32)",
19700tc_a08b630b, TypeALU64>, Enc_d2216a {
19701let Inst{7-5} = 0b000;
19702let Inst{13-13} = 0b0;
19703let Inst{31-21} = 0b11010000000;
19704let hasNewValue = 1;
19705let opNewValue = 0;
19706let prefersSlot3 = 1;
19707}
19708def S2_pstorerbf_io : HInst<
19709(outs),
19710(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19711"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32",
19712tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19713let Inst{2-2} = 0b0;
19714let Inst{31-21} = 0b01000100000;
19715let isPredicated = 1;
19716let isPredicatedFalse = 1;
19717let addrMode = BaseImmOffset;
19718let accessSize = ByteAccess;
19719let mayStore = 1;
19720let BaseOpcode = "S2_storerb_io";
19721let CextOpcode = "S2_storerb";
19722let InputType = "imm";
19723let isNVStorable = 1;
19724let isExtendable = 1;
19725let opExtendable = 2;
19726let isExtentSigned = 0;
19727let opExtentBits = 6;
19728let opExtentAlign = 0;
19729}
19730def S2_pstorerbf_pi : HInst<
19731(outs IntRegs:$Rx32),
19732(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19733"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32",
19734tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19735let Inst{2-2} = 0b1;
19736let Inst{7-7} = 0b0;
19737let Inst{13-13} = 0b1;
19738let Inst{31-21} = 0b10101011000;
19739let isPredicated = 1;
19740let isPredicatedFalse = 1;
19741let addrMode = PostInc;
19742let accessSize = ByteAccess;
19743let mayStore = 1;
19744let BaseOpcode = "S2_storerb_pi";
19745let isNVStorable = 1;
19746let Constraints = "$Rx32 = $Rx32in";
19747}
19748def S2_pstorerbf_zomap : HInst<
19749(outs),
19750(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19751"if (!$Pv4) memb($Rs32) = $Rt32",
19752tc_8035e91f, TypeMAPPING> {
19753let isPseudo = 1;
19754let isCodeGenOnly = 1;
19755}
19756def S2_pstorerbfnew_pi : HInst<
19757(outs IntRegs:$Rx32),
19758(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19759"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19760tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19761let Inst{2-2} = 0b1;
19762let Inst{7-7} = 0b1;
19763let Inst{13-13} = 0b1;
19764let Inst{31-21} = 0b10101011000;
19765let isPredicated = 1;
19766let isPredicatedFalse = 1;
19767let addrMode = PostInc;
19768let accessSize = ByteAccess;
19769let isPredicatedNew = 1;
19770let mayStore = 1;
19771let BaseOpcode = "S2_storerb_pi";
19772let isNVStorable = 1;
19773let Constraints = "$Rx32 = $Rx32in";
19774}
19775def S2_pstorerbnewf_io : HInst<
19776(outs),
19777(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19778"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19779tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19780let Inst{2-2} = 0b0;
19781let Inst{12-11} = 0b00;
19782let Inst{31-21} = 0b01000100101;
19783let isPredicated = 1;
19784let isPredicatedFalse = 1;
19785let addrMode = BaseImmOffset;
19786let accessSize = ByteAccess;
19787let isNVStore = 1;
19788let isNewValue = 1;
19789let isRestrictNoSlot1Store = 1;
19790let mayStore = 1;
19791let BaseOpcode = "S2_storerb_io";
19792let CextOpcode = "S2_storerb";
19793let InputType = "imm";
19794let isExtendable = 1;
19795let opExtendable = 2;
19796let isExtentSigned = 0;
19797let opExtentBits = 6;
19798let opExtentAlign = 0;
19799let opNewValue = 3;
19800}
19801def S2_pstorerbnewf_pi : HInst<
19802(outs IntRegs:$Rx32),
19803(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19804"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19805tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19806let Inst{2-2} = 0b1;
19807let Inst{7-7} = 0b0;
19808let Inst{13-11} = 0b100;
19809let Inst{31-21} = 0b10101011101;
19810let isPredicated = 1;
19811let isPredicatedFalse = 1;
19812let addrMode = PostInc;
19813let accessSize = ByteAccess;
19814let isNVStore = 1;
19815let isNewValue = 1;
19816let isRestrictNoSlot1Store = 1;
19817let mayStore = 1;
19818let BaseOpcode = "S2_storerb_pi";
19819let CextOpcode = "S2_storerb";
19820let opNewValue = 4;
19821let Constraints = "$Rx32 = $Rx32in";
19822}
19823def S2_pstorerbnewf_zomap : HInst<
19824(outs),
19825(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19826"if (!$Pv4) memb($Rs32) = $Nt8.new",
19827tc_011e0e9d, TypeMAPPING> {
19828let isPseudo = 1;
19829let isCodeGenOnly = 1;
19830let opNewValue = 2;
19831}
19832def S2_pstorerbnewfnew_pi : HInst<
19833(outs IntRegs:$Rx32),
19834(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19835"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19836tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19837let Inst{2-2} = 0b1;
19838let Inst{7-7} = 0b1;
19839let Inst{13-11} = 0b100;
19840let Inst{31-21} = 0b10101011101;
19841let isPredicated = 1;
19842let isPredicatedFalse = 1;
19843let addrMode = PostInc;
19844let accessSize = ByteAccess;
19845let isNVStore = 1;
19846let isPredicatedNew = 1;
19847let isNewValue = 1;
19848let isRestrictNoSlot1Store = 1;
19849let mayStore = 1;
19850let BaseOpcode = "S2_storerb_pi";
19851let CextOpcode = "S2_storerb";
19852let opNewValue = 4;
19853let Constraints = "$Rx32 = $Rx32in";
19854}
19855def S2_pstorerbnewt_io : HInst<
19856(outs),
19857(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
19858"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new",
19859tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel {
19860let Inst{2-2} = 0b0;
19861let Inst{12-11} = 0b00;
19862let Inst{31-21} = 0b01000000101;
19863let isPredicated = 1;
19864let addrMode = BaseImmOffset;
19865let accessSize = ByteAccess;
19866let isNVStore = 1;
19867let isNewValue = 1;
19868let isRestrictNoSlot1Store = 1;
19869let mayStore = 1;
19870let BaseOpcode = "S2_storerb_io";
19871let CextOpcode = "S2_storerb";
19872let InputType = "imm";
19873let isExtendable = 1;
19874let opExtendable = 2;
19875let isExtentSigned = 0;
19876let opExtentBits = 6;
19877let opExtentAlign = 0;
19878let opNewValue = 3;
19879}
19880def S2_pstorerbnewt_pi : HInst<
19881(outs IntRegs:$Rx32),
19882(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19883"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new",
19884tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel {
19885let Inst{2-2} = 0b0;
19886let Inst{7-7} = 0b0;
19887let Inst{13-11} = 0b100;
19888let Inst{31-21} = 0b10101011101;
19889let isPredicated = 1;
19890let addrMode = PostInc;
19891let accessSize = ByteAccess;
19892let isNVStore = 1;
19893let isNewValue = 1;
19894let isRestrictNoSlot1Store = 1;
19895let mayStore = 1;
19896let BaseOpcode = "S2_storerb_pi";
19897let CextOpcode = "S2_storerb";
19898let opNewValue = 4;
19899let Constraints = "$Rx32 = $Rx32in";
19900}
19901def S2_pstorerbnewt_zomap : HInst<
19902(outs),
19903(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
19904"if ($Pv4) memb($Rs32) = $Nt8.new",
19905tc_011e0e9d, TypeMAPPING> {
19906let isPseudo = 1;
19907let isCodeGenOnly = 1;
19908let opNewValue = 2;
19909}
19910def S2_pstorerbnewtnew_pi : HInst<
19911(outs IntRegs:$Rx32),
19912(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
19913"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new",
19914tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel {
19915let Inst{2-2} = 0b0;
19916let Inst{7-7} = 0b1;
19917let Inst{13-11} = 0b100;
19918let Inst{31-21} = 0b10101011101;
19919let isPredicated = 1;
19920let addrMode = PostInc;
19921let accessSize = ByteAccess;
19922let isNVStore = 1;
19923let isPredicatedNew = 1;
19924let isNewValue = 1;
19925let isRestrictNoSlot1Store = 1;
19926let mayStore = 1;
19927let BaseOpcode = "S2_storerb_pi";
19928let CextOpcode = "S2_storerb";
19929let opNewValue = 4;
19930let Constraints = "$Rx32 = $Rx32in";
19931}
19932def S2_pstorerbt_io : HInst<
19933(outs),
19934(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
19935"if ($Pv4) memb($Rs32+#$Ii) = $Rt32",
19936tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel {
19937let Inst{2-2} = 0b0;
19938let Inst{31-21} = 0b01000000000;
19939let isPredicated = 1;
19940let addrMode = BaseImmOffset;
19941let accessSize = ByteAccess;
19942let mayStore = 1;
19943let BaseOpcode = "S2_storerb_io";
19944let CextOpcode = "S2_storerb";
19945let InputType = "imm";
19946let isNVStorable = 1;
19947let isExtendable = 1;
19948let opExtendable = 2;
19949let isExtentSigned = 0;
19950let opExtentBits = 6;
19951let opExtentAlign = 0;
19952}
19953def S2_pstorerbt_pi : HInst<
19954(outs IntRegs:$Rx32),
19955(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19956"if ($Pv4) memb($Rx32++#$Ii) = $Rt32",
19957tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel {
19958let Inst{2-2} = 0b0;
19959let Inst{7-7} = 0b0;
19960let Inst{13-13} = 0b1;
19961let Inst{31-21} = 0b10101011000;
19962let isPredicated = 1;
19963let addrMode = PostInc;
19964let accessSize = ByteAccess;
19965let mayStore = 1;
19966let BaseOpcode = "S2_storerb_pi";
19967let isNVStorable = 1;
19968let Constraints = "$Rx32 = $Rx32in";
19969}
19970def S2_pstorerbt_zomap : HInst<
19971(outs),
19972(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
19973"if ($Pv4) memb($Rs32) = $Rt32",
19974tc_8035e91f, TypeMAPPING> {
19975let isPseudo = 1;
19976let isCodeGenOnly = 1;
19977}
19978def S2_pstorerbtnew_pi : HInst<
19979(outs IntRegs:$Rx32),
19980(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
19981"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32",
19982tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel {
19983let Inst{2-2} = 0b0;
19984let Inst{7-7} = 0b1;
19985let Inst{13-13} = 0b1;
19986let Inst{31-21} = 0b10101011000;
19987let isPredicated = 1;
19988let addrMode = PostInc;
19989let accessSize = ByteAccess;
19990let isPredicatedNew = 1;
19991let mayStore = 1;
19992let BaseOpcode = "S2_storerb_pi";
19993let isNVStorable = 1;
19994let Constraints = "$Rx32 = $Rx32in";
19995}
19996def S2_pstorerdf_io : HInst<
19997(outs),
19998(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
19999"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32",
20000tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20001let Inst{2-2} = 0b0;
20002let Inst{31-21} = 0b01000100110;
20003let isPredicated = 1;
20004let isPredicatedFalse = 1;
20005let addrMode = BaseImmOffset;
20006let accessSize = DoubleWordAccess;
20007let mayStore = 1;
20008let BaseOpcode = "S2_storerd_io";
20009let CextOpcode = "S2_storerd";
20010let InputType = "imm";
20011let isExtendable = 1;
20012let opExtendable = 2;
20013let isExtentSigned = 0;
20014let opExtentBits = 9;
20015let opExtentAlign = 3;
20016}
20017def S2_pstorerdf_pi : HInst<
20018(outs IntRegs:$Rx32),
20019(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20020"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32",
20021tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20022let Inst{2-2} = 0b1;
20023let Inst{7-7} = 0b0;
20024let Inst{13-13} = 0b1;
20025let Inst{31-21} = 0b10101011110;
20026let isPredicated = 1;
20027let isPredicatedFalse = 1;
20028let addrMode = PostInc;
20029let accessSize = DoubleWordAccess;
20030let mayStore = 1;
20031let BaseOpcode = "S2_storerd_pi";
20032let CextOpcode = "S2_storerd";
20033let Constraints = "$Rx32 = $Rx32in";
20034}
20035def S2_pstorerdf_zomap : HInst<
20036(outs),
20037(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20038"if (!$Pv4) memd($Rs32) = $Rtt32",
20039tc_8035e91f, TypeMAPPING> {
20040let isPseudo = 1;
20041let isCodeGenOnly = 1;
20042}
20043def S2_pstorerdfnew_pi : HInst<
20044(outs IntRegs:$Rx32),
20045(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20046"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20047tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20048let Inst{2-2} = 0b1;
20049let Inst{7-7} = 0b1;
20050let Inst{13-13} = 0b1;
20051let Inst{31-21} = 0b10101011110;
20052let isPredicated = 1;
20053let isPredicatedFalse = 1;
20054let addrMode = PostInc;
20055let accessSize = DoubleWordAccess;
20056let isPredicatedNew = 1;
20057let mayStore = 1;
20058let BaseOpcode = "S2_storerd_pi";
20059let CextOpcode = "S2_storerd";
20060let Constraints = "$Rx32 = $Rx32in";
20061}
20062def S2_pstorerdt_io : HInst<
20063(outs),
20064(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
20065"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32",
20066tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel {
20067let Inst{2-2} = 0b0;
20068let Inst{31-21} = 0b01000000110;
20069let isPredicated = 1;
20070let addrMode = BaseImmOffset;
20071let accessSize = DoubleWordAccess;
20072let mayStore = 1;
20073let BaseOpcode = "S2_storerd_io";
20074let CextOpcode = "S2_storerd";
20075let InputType = "imm";
20076let isExtendable = 1;
20077let opExtendable = 2;
20078let isExtentSigned = 0;
20079let opExtentBits = 9;
20080let opExtentAlign = 3;
20081}
20082def S2_pstorerdt_pi : HInst<
20083(outs IntRegs:$Rx32),
20084(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20085"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32",
20086tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel {
20087let Inst{2-2} = 0b0;
20088let Inst{7-7} = 0b0;
20089let Inst{13-13} = 0b1;
20090let Inst{31-21} = 0b10101011110;
20091let isPredicated = 1;
20092let addrMode = PostInc;
20093let accessSize = DoubleWordAccess;
20094let mayStore = 1;
20095let BaseOpcode = "S2_storerd_pi";
20096let CextOpcode = "S2_storerd";
20097let Constraints = "$Rx32 = $Rx32in";
20098}
20099def S2_pstorerdt_zomap : HInst<
20100(outs),
20101(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
20102"if ($Pv4) memd($Rs32) = $Rtt32",
20103tc_8035e91f, TypeMAPPING> {
20104let isPseudo = 1;
20105let isCodeGenOnly = 1;
20106}
20107def S2_pstorerdtnew_pi : HInst<
20108(outs IntRegs:$Rx32),
20109(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
20110"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32",
20111tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel {
20112let Inst{2-2} = 0b0;
20113let Inst{7-7} = 0b1;
20114let Inst{13-13} = 0b1;
20115let Inst{31-21} = 0b10101011110;
20116let isPredicated = 1;
20117let addrMode = PostInc;
20118let accessSize = DoubleWordAccess;
20119let isPredicatedNew = 1;
20120let mayStore = 1;
20121let BaseOpcode = "S2_storerd_pi";
20122let CextOpcode = "S2_storerd";
20123let Constraints = "$Rx32 = $Rx32in";
20124}
20125def S2_pstorerff_io : HInst<
20126(outs),
20127(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20128"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20129tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20130let Inst{2-2} = 0b0;
20131let Inst{31-21} = 0b01000100011;
20132let isPredicated = 1;
20133let isPredicatedFalse = 1;
20134let addrMode = BaseImmOffset;
20135let accessSize = HalfWordAccess;
20136let mayStore = 1;
20137let BaseOpcode = "S2_storerf_io";
20138let CextOpcode = "S2_storerf";
20139let InputType = "imm";
20140let isExtendable = 1;
20141let opExtendable = 2;
20142let isExtentSigned = 0;
20143let opExtentBits = 7;
20144let opExtentAlign = 1;
20145}
20146def S2_pstorerff_pi : HInst<
20147(outs IntRegs:$Rx32),
20148(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20149"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20150tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20151let Inst{2-2} = 0b1;
20152let Inst{7-7} = 0b0;
20153let Inst{13-13} = 0b1;
20154let Inst{31-21} = 0b10101011011;
20155let isPredicated = 1;
20156let isPredicatedFalse = 1;
20157let addrMode = PostInc;
20158let accessSize = HalfWordAccess;
20159let mayStore = 1;
20160let BaseOpcode = "S2_storerf_pi";
20161let CextOpcode = "S2_storerf";
20162let Constraints = "$Rx32 = $Rx32in";
20163}
20164def S2_pstorerff_zomap : HInst<
20165(outs),
20166(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20167"if (!$Pv4) memh($Rs32) = $Rt32.h",
20168tc_8035e91f, TypeMAPPING> {
20169let isPseudo = 1;
20170let isCodeGenOnly = 1;
20171}
20172def S2_pstorerffnew_pi : HInst<
20173(outs IntRegs:$Rx32),
20174(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20175"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20176tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20177let Inst{2-2} = 0b1;
20178let Inst{7-7} = 0b1;
20179let Inst{13-13} = 0b1;
20180let Inst{31-21} = 0b10101011011;
20181let isPredicated = 1;
20182let isPredicatedFalse = 1;
20183let addrMode = PostInc;
20184let accessSize = HalfWordAccess;
20185let isPredicatedNew = 1;
20186let mayStore = 1;
20187let BaseOpcode = "S2_storerf_pi";
20188let CextOpcode = "S2_storerf";
20189let Constraints = "$Rx32 = $Rx32in";
20190}
20191def S2_pstorerft_io : HInst<
20192(outs),
20193(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20194"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h",
20195tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20196let Inst{2-2} = 0b0;
20197let Inst{31-21} = 0b01000000011;
20198let isPredicated = 1;
20199let addrMode = BaseImmOffset;
20200let accessSize = HalfWordAccess;
20201let mayStore = 1;
20202let BaseOpcode = "S2_storerf_io";
20203let CextOpcode = "S2_storerf";
20204let InputType = "imm";
20205let isExtendable = 1;
20206let opExtendable = 2;
20207let isExtentSigned = 0;
20208let opExtentBits = 7;
20209let opExtentAlign = 1;
20210}
20211def S2_pstorerft_pi : HInst<
20212(outs IntRegs:$Rx32),
20213(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20214"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h",
20215tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20216let Inst{2-2} = 0b0;
20217let Inst{7-7} = 0b0;
20218let Inst{13-13} = 0b1;
20219let Inst{31-21} = 0b10101011011;
20220let isPredicated = 1;
20221let addrMode = PostInc;
20222let accessSize = HalfWordAccess;
20223let mayStore = 1;
20224let BaseOpcode = "S2_storerf_pi";
20225let CextOpcode = "S2_storerf";
20226let Constraints = "$Rx32 = $Rx32in";
20227}
20228def S2_pstorerft_zomap : HInst<
20229(outs),
20230(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20231"if ($Pv4) memh($Rs32) = $Rt32.h",
20232tc_8035e91f, TypeMAPPING> {
20233let isPseudo = 1;
20234let isCodeGenOnly = 1;
20235}
20236def S2_pstorerftnew_pi : HInst<
20237(outs IntRegs:$Rx32),
20238(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20239"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h",
20240tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20241let Inst{2-2} = 0b0;
20242let Inst{7-7} = 0b1;
20243let Inst{13-13} = 0b1;
20244let Inst{31-21} = 0b10101011011;
20245let isPredicated = 1;
20246let addrMode = PostInc;
20247let accessSize = HalfWordAccess;
20248let isPredicatedNew = 1;
20249let mayStore = 1;
20250let BaseOpcode = "S2_storerf_pi";
20251let CextOpcode = "S2_storerf";
20252let Constraints = "$Rx32 = $Rx32in";
20253}
20254def S2_pstorerhf_io : HInst<
20255(outs),
20256(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20257"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32",
20258tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20259let Inst{2-2} = 0b0;
20260let Inst{31-21} = 0b01000100010;
20261let isPredicated = 1;
20262let isPredicatedFalse = 1;
20263let addrMode = BaseImmOffset;
20264let accessSize = HalfWordAccess;
20265let mayStore = 1;
20266let BaseOpcode = "S2_storerh_io";
20267let CextOpcode = "S2_storerh";
20268let InputType = "imm";
20269let isNVStorable = 1;
20270let isExtendable = 1;
20271let opExtendable = 2;
20272let isExtentSigned = 0;
20273let opExtentBits = 7;
20274let opExtentAlign = 1;
20275}
20276def S2_pstorerhf_pi : HInst<
20277(outs IntRegs:$Rx32),
20278(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20279"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32",
20280tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20281let Inst{2-2} = 0b1;
20282let Inst{7-7} = 0b0;
20283let Inst{13-13} = 0b1;
20284let Inst{31-21} = 0b10101011010;
20285let isPredicated = 1;
20286let isPredicatedFalse = 1;
20287let addrMode = PostInc;
20288let accessSize = HalfWordAccess;
20289let mayStore = 1;
20290let BaseOpcode = "S2_storerh_pi";
20291let isNVStorable = 1;
20292let Constraints = "$Rx32 = $Rx32in";
20293}
20294def S2_pstorerhf_zomap : HInst<
20295(outs),
20296(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20297"if (!$Pv4) memh($Rs32) = $Rt32",
20298tc_8035e91f, TypeMAPPING> {
20299let isPseudo = 1;
20300let isCodeGenOnly = 1;
20301}
20302def S2_pstorerhfnew_pi : HInst<
20303(outs IntRegs:$Rx32),
20304(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20305"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20306tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20307let Inst{2-2} = 0b1;
20308let Inst{7-7} = 0b1;
20309let Inst{13-13} = 0b1;
20310let Inst{31-21} = 0b10101011010;
20311let isPredicated = 1;
20312let isPredicatedFalse = 1;
20313let addrMode = PostInc;
20314let accessSize = HalfWordAccess;
20315let isPredicatedNew = 1;
20316let mayStore = 1;
20317let BaseOpcode = "S2_storerh_pi";
20318let isNVStorable = 1;
20319let Constraints = "$Rx32 = $Rx32in";
20320}
20321def S2_pstorerhnewf_io : HInst<
20322(outs),
20323(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20324"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20325tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20326let Inst{2-2} = 0b0;
20327let Inst{12-11} = 0b01;
20328let Inst{31-21} = 0b01000100101;
20329let isPredicated = 1;
20330let isPredicatedFalse = 1;
20331let addrMode = BaseImmOffset;
20332let accessSize = HalfWordAccess;
20333let isNVStore = 1;
20334let isNewValue = 1;
20335let isRestrictNoSlot1Store = 1;
20336let mayStore = 1;
20337let BaseOpcode = "S2_storerh_io";
20338let CextOpcode = "S2_storerh";
20339let InputType = "imm";
20340let isExtendable = 1;
20341let opExtendable = 2;
20342let isExtentSigned = 0;
20343let opExtentBits = 7;
20344let opExtentAlign = 1;
20345let opNewValue = 3;
20346}
20347def S2_pstorerhnewf_pi : HInst<
20348(outs IntRegs:$Rx32),
20349(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20350"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20351tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20352let Inst{2-2} = 0b1;
20353let Inst{7-7} = 0b0;
20354let Inst{13-11} = 0b101;
20355let Inst{31-21} = 0b10101011101;
20356let isPredicated = 1;
20357let isPredicatedFalse = 1;
20358let addrMode = PostInc;
20359let accessSize = HalfWordAccess;
20360let isNVStore = 1;
20361let isNewValue = 1;
20362let isRestrictNoSlot1Store = 1;
20363let mayStore = 1;
20364let BaseOpcode = "S2_storerh_pi";
20365let CextOpcode = "S2_storerh";
20366let opNewValue = 4;
20367let Constraints = "$Rx32 = $Rx32in";
20368}
20369def S2_pstorerhnewf_zomap : HInst<
20370(outs),
20371(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20372"if (!$Pv4) memh($Rs32) = $Nt8.new",
20373tc_011e0e9d, TypeMAPPING> {
20374let isPseudo = 1;
20375let isCodeGenOnly = 1;
20376let opNewValue = 2;
20377}
20378def S2_pstorerhnewfnew_pi : HInst<
20379(outs IntRegs:$Rx32),
20380(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20381"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20382tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20383let Inst{2-2} = 0b1;
20384let Inst{7-7} = 0b1;
20385let Inst{13-11} = 0b101;
20386let Inst{31-21} = 0b10101011101;
20387let isPredicated = 1;
20388let isPredicatedFalse = 1;
20389let addrMode = PostInc;
20390let accessSize = HalfWordAccess;
20391let isNVStore = 1;
20392let isPredicatedNew = 1;
20393let isNewValue = 1;
20394let isRestrictNoSlot1Store = 1;
20395let mayStore = 1;
20396let BaseOpcode = "S2_storerh_pi";
20397let CextOpcode = "S2_storerh";
20398let opNewValue = 4;
20399let Constraints = "$Rx32 = $Rx32in";
20400}
20401def S2_pstorerhnewt_io : HInst<
20402(outs),
20403(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
20404"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new",
20405tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel {
20406let Inst{2-2} = 0b0;
20407let Inst{12-11} = 0b01;
20408let Inst{31-21} = 0b01000000101;
20409let isPredicated = 1;
20410let addrMode = BaseImmOffset;
20411let accessSize = HalfWordAccess;
20412let isNVStore = 1;
20413let isNewValue = 1;
20414let isRestrictNoSlot1Store = 1;
20415let mayStore = 1;
20416let BaseOpcode = "S2_storerh_io";
20417let CextOpcode = "S2_storerh";
20418let InputType = "imm";
20419let isExtendable = 1;
20420let opExtendable = 2;
20421let isExtentSigned = 0;
20422let opExtentBits = 7;
20423let opExtentAlign = 1;
20424let opNewValue = 3;
20425}
20426def S2_pstorerhnewt_pi : HInst<
20427(outs IntRegs:$Rx32),
20428(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20429"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new",
20430tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel {
20431let Inst{2-2} = 0b0;
20432let Inst{7-7} = 0b0;
20433let Inst{13-11} = 0b101;
20434let Inst{31-21} = 0b10101011101;
20435let isPredicated = 1;
20436let addrMode = PostInc;
20437let accessSize = HalfWordAccess;
20438let isNVStore = 1;
20439let isNewValue = 1;
20440let isRestrictNoSlot1Store = 1;
20441let mayStore = 1;
20442let BaseOpcode = "S2_storerh_pi";
20443let CextOpcode = "S2_storerh";
20444let opNewValue = 4;
20445let Constraints = "$Rx32 = $Rx32in";
20446}
20447def S2_pstorerhnewt_zomap : HInst<
20448(outs),
20449(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20450"if ($Pv4) memh($Rs32) = $Nt8.new",
20451tc_011e0e9d, TypeMAPPING> {
20452let isPseudo = 1;
20453let isCodeGenOnly = 1;
20454let opNewValue = 2;
20455}
20456def S2_pstorerhnewtnew_pi : HInst<
20457(outs IntRegs:$Rx32),
20458(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
20459"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new",
20460tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel {
20461let Inst{2-2} = 0b0;
20462let Inst{7-7} = 0b1;
20463let Inst{13-11} = 0b101;
20464let Inst{31-21} = 0b10101011101;
20465let isPredicated = 1;
20466let addrMode = PostInc;
20467let accessSize = HalfWordAccess;
20468let isNVStore = 1;
20469let isPredicatedNew = 1;
20470let isNewValue = 1;
20471let isRestrictNoSlot1Store = 1;
20472let mayStore = 1;
20473let BaseOpcode = "S2_storerh_pi";
20474let CextOpcode = "S2_storerh";
20475let opNewValue = 4;
20476let Constraints = "$Rx32 = $Rx32in";
20477}
20478def S2_pstorerht_io : HInst<
20479(outs),
20480(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
20481"if ($Pv4) memh($Rs32+#$Ii) = $Rt32",
20482tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
20483let Inst{2-2} = 0b0;
20484let Inst{31-21} = 0b01000000010;
20485let isPredicated = 1;
20486let addrMode = BaseImmOffset;
20487let accessSize = HalfWordAccess;
20488let mayStore = 1;
20489let BaseOpcode = "S2_storerh_io";
20490let CextOpcode = "S2_storerh";
20491let InputType = "imm";
20492let isNVStorable = 1;
20493let isExtendable = 1;
20494let opExtendable = 2;
20495let isExtentSigned = 0;
20496let opExtentBits = 7;
20497let opExtentAlign = 1;
20498}
20499def S2_pstorerht_pi : HInst<
20500(outs IntRegs:$Rx32),
20501(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20502"if ($Pv4) memh($Rx32++#$Ii) = $Rt32",
20503tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel {
20504let Inst{2-2} = 0b0;
20505let Inst{7-7} = 0b0;
20506let Inst{13-13} = 0b1;
20507let Inst{31-21} = 0b10101011010;
20508let isPredicated = 1;
20509let addrMode = PostInc;
20510let accessSize = HalfWordAccess;
20511let mayStore = 1;
20512let BaseOpcode = "S2_storerh_pi";
20513let isNVStorable = 1;
20514let Constraints = "$Rx32 = $Rx32in";
20515}
20516def S2_pstorerht_zomap : HInst<
20517(outs),
20518(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20519"if ($Pv4) memh($Rs32) = $Rt32",
20520tc_8035e91f, TypeMAPPING> {
20521let isPseudo = 1;
20522let isCodeGenOnly = 1;
20523}
20524def S2_pstorerhtnew_pi : HInst<
20525(outs IntRegs:$Rx32),
20526(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
20527"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32",
20528tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel {
20529let Inst{2-2} = 0b0;
20530let Inst{7-7} = 0b1;
20531let Inst{13-13} = 0b1;
20532let Inst{31-21} = 0b10101011010;
20533let isPredicated = 1;
20534let addrMode = PostInc;
20535let accessSize = HalfWordAccess;
20536let isPredicatedNew = 1;
20537let mayStore = 1;
20538let BaseOpcode = "S2_storerh_pi";
20539let isNVStorable = 1;
20540let Constraints = "$Rx32 = $Rx32in";
20541}
20542def S2_pstorerif_io : HInst<
20543(outs),
20544(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20545"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32",
20546tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20547let Inst{2-2} = 0b0;
20548let Inst{31-21} = 0b01000100100;
20549let isPredicated = 1;
20550let isPredicatedFalse = 1;
20551let addrMode = BaseImmOffset;
20552let accessSize = WordAccess;
20553let mayStore = 1;
20554let BaseOpcode = "S2_storeri_io";
20555let CextOpcode = "S2_storeri";
20556let InputType = "imm";
20557let isNVStorable = 1;
20558let isExtendable = 1;
20559let opExtendable = 2;
20560let isExtentSigned = 0;
20561let opExtentBits = 8;
20562let opExtentAlign = 2;
20563}
20564def S2_pstorerif_pi : HInst<
20565(outs IntRegs:$Rx32),
20566(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20567"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32",
20568tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20569let Inst{2-2} = 0b1;
20570let Inst{7-7} = 0b0;
20571let Inst{13-13} = 0b1;
20572let Inst{31-21} = 0b10101011100;
20573let isPredicated = 1;
20574let isPredicatedFalse = 1;
20575let addrMode = PostInc;
20576let accessSize = WordAccess;
20577let mayStore = 1;
20578let BaseOpcode = "S2_storeri_pi";
20579let isNVStorable = 1;
20580let Constraints = "$Rx32 = $Rx32in";
20581}
20582def S2_pstorerif_zomap : HInst<
20583(outs),
20584(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20585"if (!$Pv4) memw($Rs32) = $Rt32",
20586tc_8035e91f, TypeMAPPING> {
20587let isPseudo = 1;
20588let isCodeGenOnly = 1;
20589}
20590def S2_pstorerifnew_pi : HInst<
20591(outs IntRegs:$Rx32),
20592(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20593"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20594tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20595let Inst{2-2} = 0b1;
20596let Inst{7-7} = 0b1;
20597let Inst{13-13} = 0b1;
20598let Inst{31-21} = 0b10101011100;
20599let isPredicated = 1;
20600let isPredicatedFalse = 1;
20601let addrMode = PostInc;
20602let accessSize = WordAccess;
20603let isPredicatedNew = 1;
20604let mayStore = 1;
20605let BaseOpcode = "S2_storeri_pi";
20606let CextOpcode = "S2_storeri";
20607let isNVStorable = 1;
20608let Constraints = "$Rx32 = $Rx32in";
20609}
20610def S2_pstorerinewf_io : HInst<
20611(outs),
20612(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20613"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20614tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20615let Inst{2-2} = 0b0;
20616let Inst{12-11} = 0b10;
20617let Inst{31-21} = 0b01000100101;
20618let isPredicated = 1;
20619let isPredicatedFalse = 1;
20620let addrMode = BaseImmOffset;
20621let accessSize = WordAccess;
20622let isNVStore = 1;
20623let isNewValue = 1;
20624let isRestrictNoSlot1Store = 1;
20625let mayStore = 1;
20626let BaseOpcode = "S2_storeri_io";
20627let CextOpcode = "S2_storeri";
20628let InputType = "imm";
20629let isExtendable = 1;
20630let opExtendable = 2;
20631let isExtentSigned = 0;
20632let opExtentBits = 8;
20633let opExtentAlign = 2;
20634let opNewValue = 3;
20635}
20636def S2_pstorerinewf_pi : HInst<
20637(outs IntRegs:$Rx32),
20638(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20639"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20640tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20641let Inst{2-2} = 0b1;
20642let Inst{7-7} = 0b0;
20643let Inst{13-11} = 0b110;
20644let Inst{31-21} = 0b10101011101;
20645let isPredicated = 1;
20646let isPredicatedFalse = 1;
20647let addrMode = PostInc;
20648let accessSize = WordAccess;
20649let isNVStore = 1;
20650let isNewValue = 1;
20651let isRestrictNoSlot1Store = 1;
20652let mayStore = 1;
20653let BaseOpcode = "S2_storeri_pi";
20654let CextOpcode = "S2_storeri";
20655let opNewValue = 4;
20656let Constraints = "$Rx32 = $Rx32in";
20657}
20658def S2_pstorerinewf_zomap : HInst<
20659(outs),
20660(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20661"if (!$Pv4) memw($Rs32) = $Nt8.new",
20662tc_011e0e9d, TypeMAPPING> {
20663let isPseudo = 1;
20664let isCodeGenOnly = 1;
20665let opNewValue = 2;
20666}
20667def S2_pstorerinewfnew_pi : HInst<
20668(outs IntRegs:$Rx32),
20669(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20670"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20671tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20672let Inst{2-2} = 0b1;
20673let Inst{7-7} = 0b1;
20674let Inst{13-11} = 0b110;
20675let Inst{31-21} = 0b10101011101;
20676let isPredicated = 1;
20677let isPredicatedFalse = 1;
20678let addrMode = PostInc;
20679let accessSize = WordAccess;
20680let isNVStore = 1;
20681let isPredicatedNew = 1;
20682let isNewValue = 1;
20683let isRestrictNoSlot1Store = 1;
20684let mayStore = 1;
20685let BaseOpcode = "S2_storeri_pi";
20686let CextOpcode = "S2_storeri";
20687let opNewValue = 4;
20688let Constraints = "$Rx32 = $Rx32in";
20689}
20690def S2_pstorerinewt_io : HInst<
20691(outs),
20692(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
20693"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new",
20694tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
20695let Inst{2-2} = 0b0;
20696let Inst{12-11} = 0b10;
20697let Inst{31-21} = 0b01000000101;
20698let isPredicated = 1;
20699let addrMode = BaseImmOffset;
20700let accessSize = WordAccess;
20701let isNVStore = 1;
20702let isNewValue = 1;
20703let isRestrictNoSlot1Store = 1;
20704let mayStore = 1;
20705let BaseOpcode = "S2_storeri_io";
20706let CextOpcode = "S2_storeri";
20707let InputType = "imm";
20708let isExtendable = 1;
20709let opExtendable = 2;
20710let isExtentSigned = 0;
20711let opExtentBits = 8;
20712let opExtentAlign = 2;
20713let opNewValue = 3;
20714}
20715def S2_pstorerinewt_pi : HInst<
20716(outs IntRegs:$Rx32),
20717(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20718"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new",
20719tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel {
20720let Inst{2-2} = 0b0;
20721let Inst{7-7} = 0b0;
20722let Inst{13-11} = 0b110;
20723let Inst{31-21} = 0b10101011101;
20724let isPredicated = 1;
20725let addrMode = PostInc;
20726let accessSize = WordAccess;
20727let isNVStore = 1;
20728let isNewValue = 1;
20729let isRestrictNoSlot1Store = 1;
20730let mayStore = 1;
20731let BaseOpcode = "S2_storeri_pi";
20732let CextOpcode = "S2_storeri";
20733let opNewValue = 4;
20734let Constraints = "$Rx32 = $Rx32in";
20735}
20736def S2_pstorerinewt_zomap : HInst<
20737(outs),
20738(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
20739"if ($Pv4) memw($Rs32) = $Nt8.new",
20740tc_011e0e9d, TypeMAPPING> {
20741let isPseudo = 1;
20742let isCodeGenOnly = 1;
20743let opNewValue = 2;
20744}
20745def S2_pstorerinewtnew_pi : HInst<
20746(outs IntRegs:$Rx32),
20747(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
20748"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new",
20749tc_f529831b, TypeST>, Enc_65f095, AddrModeRel {
20750let Inst{2-2} = 0b0;
20751let Inst{7-7} = 0b1;
20752let Inst{13-11} = 0b110;
20753let Inst{31-21} = 0b10101011101;
20754let isPredicated = 1;
20755let addrMode = PostInc;
20756let accessSize = WordAccess;
20757let isNVStore = 1;
20758let isPredicatedNew = 1;
20759let isNewValue = 1;
20760let isRestrictNoSlot1Store = 1;
20761let mayStore = 1;
20762let BaseOpcode = "S2_storeri_pi";
20763let CextOpcode = "S2_storeri";
20764let opNewValue = 4;
20765let Constraints = "$Rx32 = $Rx32in";
20766}
20767def S2_pstorerit_io : HInst<
20768(outs),
20769(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
20770"if ($Pv4) memw($Rs32+#$Ii) = $Rt32",
20771tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel {
20772let Inst{2-2} = 0b0;
20773let Inst{31-21} = 0b01000000100;
20774let isPredicated = 1;
20775let addrMode = BaseImmOffset;
20776let accessSize = WordAccess;
20777let mayStore = 1;
20778let BaseOpcode = "S2_storeri_io";
20779let CextOpcode = "S2_storeri";
20780let InputType = "imm";
20781let isNVStorable = 1;
20782let isExtendable = 1;
20783let opExtendable = 2;
20784let isExtentSigned = 0;
20785let opExtentBits = 8;
20786let opExtentAlign = 2;
20787}
20788def S2_pstorerit_pi : HInst<
20789(outs IntRegs:$Rx32),
20790(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20791"if ($Pv4) memw($Rx32++#$Ii) = $Rt32",
20792tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel {
20793let Inst{2-2} = 0b0;
20794let Inst{7-7} = 0b0;
20795let Inst{13-13} = 0b1;
20796let Inst{31-21} = 0b10101011100;
20797let isPredicated = 1;
20798let addrMode = PostInc;
20799let accessSize = WordAccess;
20800let mayStore = 1;
20801let BaseOpcode = "S2_storeri_pi";
20802let isNVStorable = 1;
20803let Constraints = "$Rx32 = $Rx32in";
20804}
20805def S2_pstorerit_zomap : HInst<
20806(outs),
20807(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
20808"if ($Pv4) memw($Rs32) = $Rt32",
20809tc_8035e91f, TypeMAPPING> {
20810let isPseudo = 1;
20811let isCodeGenOnly = 1;
20812}
20813def S2_pstoreritnew_pi : HInst<
20814(outs IntRegs:$Rx32),
20815(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
20816"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32",
20817tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel {
20818let Inst{2-2} = 0b0;
20819let Inst{7-7} = 0b1;
20820let Inst{13-13} = 0b1;
20821let Inst{31-21} = 0b10101011100;
20822let isPredicated = 1;
20823let addrMode = PostInc;
20824let accessSize = WordAccess;
20825let isPredicatedNew = 1;
20826let mayStore = 1;
20827let BaseOpcode = "S2_storeri_pi";
20828let isNVStorable = 1;
20829let Constraints = "$Rx32 = $Rx32in";
20830}
20831def S2_setbit_i : HInst<
20832(outs IntRegs:$Rd32),
20833(ins IntRegs:$Rs32, u5_0Imm:$Ii),
20834"$Rd32 = setbit($Rs32,#$Ii)",
20835tc_5da50c4b, TypeS_2op>, Enc_a05677 {
20836let Inst{7-5} = 0b000;
20837let Inst{13-13} = 0b0;
20838let Inst{31-21} = 0b10001100110;
20839let hasNewValue = 1;
20840let opNewValue = 0;
20841}
20842def S2_setbit_r : HInst<
20843(outs IntRegs:$Rd32),
20844(ins IntRegs:$Rs32, IntRegs:$Rt32),
20845"$Rd32 = setbit($Rs32,$Rt32)",
20846tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
20847let Inst{7-5} = 0b000;
20848let Inst{13-13} = 0b0;
20849let Inst{31-21} = 0b11000110100;
20850let hasNewValue = 1;
20851let opNewValue = 0;
20852}
20853def S2_shuffeb : HInst<
20854(outs DoubleRegs:$Rdd32),
20855(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20856"$Rdd32 = shuffeb($Rss32,$Rtt32)",
20857tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20858let Inst{7-5} = 0b010;
20859let Inst{13-13} = 0b0;
20860let Inst{31-21} = 0b11000001000;
20861}
20862def S2_shuffeh : HInst<
20863(outs DoubleRegs:$Rdd32),
20864(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
20865"$Rdd32 = shuffeh($Rss32,$Rtt32)",
20866tc_5da50c4b, TypeS_3op>, Enc_a56825 {
20867let Inst{7-5} = 0b110;
20868let Inst{13-13} = 0b0;
20869let Inst{31-21} = 0b11000001000;
20870}
20871def S2_shuffob : HInst<
20872(outs DoubleRegs:$Rdd32),
20873(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20874"$Rdd32 = shuffob($Rtt32,$Rss32)",
20875tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20876let Inst{7-5} = 0b100;
20877let Inst{13-13} = 0b0;
20878let Inst{31-21} = 0b11000001000;
20879}
20880def S2_shuffoh : HInst<
20881(outs DoubleRegs:$Rdd32),
20882(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32),
20883"$Rdd32 = shuffoh($Rtt32,$Rss32)",
20884tc_5da50c4b, TypeS_3op>, Enc_ea23e4 {
20885let Inst{7-5} = 0b000;
20886let Inst{13-13} = 0b0;
20887let Inst{31-21} = 0b11000001100;
20888}
20889def S2_storerb_io : HInst<
20890(outs),
20891(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
20892"memb($Rs32+#$Ii) = $Rt32",
20893tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm {
20894let Inst{24-21} = 0b1000;
20895let Inst{31-27} = 0b10100;
20896let addrMode = BaseImmOffset;
20897let accessSize = ByteAccess;
20898let mayStore = 1;
20899let BaseOpcode = "S2_storerb_io";
20900let CextOpcode = "S2_storerb";
20901let InputType = "imm";
20902let isNVStorable = 1;
20903let isPredicable = 1;
20904let isExtendable = 1;
20905let opExtendable = 1;
20906let isExtentSigned = 1;
20907let opExtentBits = 11;
20908let opExtentAlign = 0;
20909}
20910def S2_storerb_pbr : HInst<
20911(outs IntRegs:$Rx32),
20912(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20913"memb($Rx32++$Mu2:brev) = $Rt32",
20914tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20915let Inst{7-0} = 0b00000000;
20916let Inst{31-21} = 0b10101111000;
20917let addrMode = PostInc;
20918let accessSize = ByteAccess;
20919let mayStore = 1;
20920let BaseOpcode = "S2_storerb_pbr";
20921let isNVStorable = 1;
20922let Constraints = "$Rx32 = $Rx32in";
20923}
20924def S2_storerb_pci : HInst<
20925(outs IntRegs:$Rx32),
20926(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
20927"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32",
20928tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel {
20929let Inst{2-0} = 0b000;
20930let Inst{7-7} = 0b0;
20931let Inst{31-21} = 0b10101001000;
20932let addrMode = PostInc;
20933let accessSize = ByteAccess;
20934let mayStore = 1;
20935let Uses = [CS];
20936let BaseOpcode = "S2_storerb_pci";
20937let isNVStorable = 1;
20938let Constraints = "$Rx32 = $Rx32in";
20939}
20940def S2_storerb_pcr : HInst<
20941(outs IntRegs:$Rx32),
20942(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20943"memb($Rx32++I:circ($Mu2)) = $Rt32",
20944tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20945let Inst{7-0} = 0b00000010;
20946let Inst{31-21} = 0b10101001000;
20947let addrMode = PostInc;
20948let accessSize = ByteAccess;
20949let mayStore = 1;
20950let Uses = [CS];
20951let BaseOpcode = "S2_storerb_pcr";
20952let isNVStorable = 1;
20953let Constraints = "$Rx32 = $Rx32in";
20954}
20955def S2_storerb_pi : HInst<
20956(outs IntRegs:$Rx32),
20957(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32),
20958"memb($Rx32++#$Ii) = $Rt32",
20959tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm {
20960let Inst{2-0} = 0b000;
20961let Inst{7-7} = 0b0;
20962let Inst{13-13} = 0b0;
20963let Inst{31-21} = 0b10101011000;
20964let addrMode = PostInc;
20965let accessSize = ByteAccess;
20966let mayStore = 1;
20967let BaseOpcode = "S2_storerb_pi";
20968let CextOpcode = "S2_storerb";
20969let isNVStorable = 1;
20970let isPredicable = 1;
20971let Constraints = "$Rx32 = $Rx32in";
20972}
20973def S2_storerb_pr : HInst<
20974(outs IntRegs:$Rx32),
20975(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
20976"memb($Rx32++$Mu2) = $Rt32",
20977tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
20978let Inst{7-0} = 0b00000000;
20979let Inst{31-21} = 0b10101101000;
20980let addrMode = PostInc;
20981let accessSize = ByteAccess;
20982let mayStore = 1;
20983let BaseOpcode = "S2_storerb_pr";
20984let isNVStorable = 1;
20985let Constraints = "$Rx32 = $Rx32in";
20986}
20987def S2_storerb_zomap : HInst<
20988(outs),
20989(ins IntRegs:$Rs32, IntRegs:$Rt32),
20990"memb($Rs32) = $Rt32",
20991tc_ae5babd7, TypeMAPPING> {
20992let isPseudo = 1;
20993let isCodeGenOnly = 1;
20994}
20995def S2_storerbgp : HInst<
20996(outs),
20997(ins u32_0Imm:$Ii, IntRegs:$Rt32),
20998"memb(gp+#$Ii) = $Rt32",
20999tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel {
21000let Inst{24-21} = 0b0000;
21001let Inst{31-27} = 0b01001;
21002let accessSize = ByteAccess;
21003let mayStore = 1;
21004let Uses = [GP];
21005let BaseOpcode = "S2_storerbabs";
21006let isNVStorable = 1;
21007let isPredicable = 1;
21008let opExtendable = 0;
21009let isExtentSigned = 0;
21010let opExtentBits = 16;
21011let opExtentAlign = 0;
21012}
21013def S2_storerbnew_io : HInst<
21014(outs),
21015(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8),
21016"memb($Rs32+#$Ii) = $Nt8.new",
21017tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel {
21018let Inst{12-11} = 0b00;
21019let Inst{24-21} = 0b1101;
21020let Inst{31-27} = 0b10100;
21021let addrMode = BaseImmOffset;
21022let accessSize = ByteAccess;
21023let isNVStore = 1;
21024let isNewValue = 1;
21025let isRestrictNoSlot1Store = 1;
21026let mayStore = 1;
21027let BaseOpcode = "S2_storerb_io";
21028let CextOpcode = "S2_storerb";
21029let InputType = "imm";
21030let isPredicable = 1;
21031let isExtendable = 1;
21032let opExtendable = 1;
21033let isExtentSigned = 1;
21034let opExtentBits = 11;
21035let opExtentAlign = 0;
21036let opNewValue = 2;
21037}
21038def S2_storerbnew_pbr : HInst<
21039(outs IntRegs:$Rx32),
21040(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21041"memb($Rx32++$Mu2:brev) = $Nt8.new",
21042tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21043let Inst{7-0} = 0b00000000;
21044let Inst{12-11} = 0b00;
21045let Inst{31-21} = 0b10101111101;
21046let addrMode = PostInc;
21047let accessSize = ByteAccess;
21048let isNVStore = 1;
21049let isNewValue = 1;
21050let isRestrictNoSlot1Store = 1;
21051let mayStore = 1;
21052let BaseOpcode = "S2_storerb_pbr";
21053let opNewValue = 3;
21054let Constraints = "$Rx32 = $Rx32in";
21055}
21056def S2_storerbnew_pci : HInst<
21057(outs IntRegs:$Rx32),
21058(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21059"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21060tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel {
21061let Inst{2-0} = 0b000;
21062let Inst{7-7} = 0b0;
21063let Inst{12-11} = 0b00;
21064let Inst{31-21} = 0b10101001101;
21065let addrMode = PostInc;
21066let accessSize = ByteAccess;
21067let isNVStore = 1;
21068let isNewValue = 1;
21069let isRestrictNoSlot1Store = 1;
21070let mayStore = 1;
21071let Uses = [CS];
21072let BaseOpcode = "S2_storerb_pci";
21073let opNewValue = 4;
21074let Constraints = "$Rx32 = $Rx32in";
21075}
21076def S2_storerbnew_pcr : HInst<
21077(outs IntRegs:$Rx32),
21078(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21079"memb($Rx32++I:circ($Mu2)) = $Nt8.new",
21080tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21081let Inst{7-0} = 0b00000010;
21082let Inst{12-11} = 0b00;
21083let Inst{31-21} = 0b10101001101;
21084let addrMode = PostInc;
21085let accessSize = ByteAccess;
21086let isNVStore = 1;
21087let isNewValue = 1;
21088let isRestrictNoSlot1Store = 1;
21089let mayStore = 1;
21090let Uses = [CS];
21091let BaseOpcode = "S2_storerb_pcr";
21092let opNewValue = 3;
21093let Constraints = "$Rx32 = $Rx32in";
21094}
21095def S2_storerbnew_pi : HInst<
21096(outs IntRegs:$Rx32),
21097(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8),
21098"memb($Rx32++#$Ii) = $Nt8.new",
21099tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel {
21100let Inst{2-0} = 0b000;
21101let Inst{7-7} = 0b0;
21102let Inst{13-11} = 0b000;
21103let Inst{31-21} = 0b10101011101;
21104let addrMode = PostInc;
21105let accessSize = ByteAccess;
21106let isNVStore = 1;
21107let isNewValue = 1;
21108let isRestrictNoSlot1Store = 1;
21109let mayStore = 1;
21110let BaseOpcode = "S2_storerb_pi";
21111let isNVStorable = 1;
21112let isPredicable = 1;
21113let opNewValue = 3;
21114let Constraints = "$Rx32 = $Rx32in";
21115}
21116def S2_storerbnew_pr : HInst<
21117(outs IntRegs:$Rx32),
21118(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21119"memb($Rx32++$Mu2) = $Nt8.new",
21120tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21121let Inst{7-0} = 0b00000000;
21122let Inst{12-11} = 0b00;
21123let Inst{31-21} = 0b10101101101;
21124let addrMode = PostInc;
21125let accessSize = ByteAccess;
21126let isNVStore = 1;
21127let isNewValue = 1;
21128let isRestrictNoSlot1Store = 1;
21129let mayStore = 1;
21130let BaseOpcode = "S2_storerb_pr";
21131let opNewValue = 3;
21132let Constraints = "$Rx32 = $Rx32in";
21133}
21134def S2_storerbnew_zomap : HInst<
21135(outs),
21136(ins IntRegs:$Rs32, IntRegs:$Nt8),
21137"memb($Rs32) = $Nt8.new",
21138tc_5deb5e47, TypeMAPPING> {
21139let isPseudo = 1;
21140let isCodeGenOnly = 1;
21141let opNewValue = 1;
21142}
21143def S2_storerbnewgp : HInst<
21144(outs),
21145(ins u32_0Imm:$Ii, IntRegs:$Nt8),
21146"memb(gp+#$Ii) = $Nt8.new",
21147tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel {
21148let Inst{12-11} = 0b00;
21149let Inst{24-21} = 0b0101;
21150let Inst{31-27} = 0b01001;
21151let accessSize = ByteAccess;
21152let isNVStore = 1;
21153let isNewValue = 1;
21154let isRestrictNoSlot1Store = 1;
21155let mayStore = 1;
21156let Uses = [GP];
21157let BaseOpcode = "S2_storerbabs";
21158let isPredicable = 1;
21159let opExtendable = 0;
21160let isExtentSigned = 0;
21161let opExtentBits = 16;
21162let opExtentAlign = 0;
21163let opNewValue = 1;
21164}
21165def S2_storerd_io : HInst<
21166(outs),
21167(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
21168"memd($Rs32+#$Ii) = $Rtt32",
21169tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm {
21170let Inst{24-21} = 0b1110;
21171let Inst{31-27} = 0b10100;
21172let addrMode = BaseImmOffset;
21173let accessSize = DoubleWordAccess;
21174let mayStore = 1;
21175let BaseOpcode = "S2_storerd_io";
21176let CextOpcode = "S2_storerd";
21177let InputType = "imm";
21178let isPredicable = 1;
21179let isExtendable = 1;
21180let opExtendable = 1;
21181let isExtentSigned = 1;
21182let opExtentBits = 14;
21183let opExtentAlign = 3;
21184}
21185def S2_storerd_pbr : HInst<
21186(outs IntRegs:$Rx32),
21187(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21188"memd($Rx32++$Mu2:brev) = $Rtt32",
21189tc_a2b365d2, TypeST>, Enc_928ca1 {
21190let Inst{7-0} = 0b00000000;
21191let Inst{31-21} = 0b10101111110;
21192let addrMode = PostInc;
21193let accessSize = DoubleWordAccess;
21194let mayStore = 1;
21195let Constraints = "$Rx32 = $Rx32in";
21196}
21197def S2_storerd_pci : HInst<
21198(outs IntRegs:$Rx32),
21199(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21200"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32",
21201tc_b4dc7630, TypeST>, Enc_395cc4 {
21202let Inst{2-0} = 0b000;
21203let Inst{7-7} = 0b0;
21204let Inst{31-21} = 0b10101001110;
21205let addrMode = PostInc;
21206let accessSize = DoubleWordAccess;
21207let mayStore = 1;
21208let Uses = [CS];
21209let Constraints = "$Rx32 = $Rx32in";
21210}
21211def S2_storerd_pcr : HInst<
21212(outs IntRegs:$Rx32),
21213(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21214"memd($Rx32++I:circ($Mu2)) = $Rtt32",
21215tc_a2b365d2, TypeST>, Enc_928ca1 {
21216let Inst{7-0} = 0b00000010;
21217let Inst{31-21} = 0b10101001110;
21218let addrMode = PostInc;
21219let accessSize = DoubleWordAccess;
21220let mayStore = 1;
21221let Uses = [CS];
21222let Constraints = "$Rx32 = $Rx32in";
21223}
21224def S2_storerd_pi : HInst<
21225(outs IntRegs:$Rx32),
21226(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32),
21227"memd($Rx32++#$Ii) = $Rtt32",
21228tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm {
21229let Inst{2-0} = 0b000;
21230let Inst{7-7} = 0b0;
21231let Inst{13-13} = 0b0;
21232let Inst{31-21} = 0b10101011110;
21233let addrMode = PostInc;
21234let accessSize = DoubleWordAccess;
21235let mayStore = 1;
21236let BaseOpcode = "S2_storerd_pi";
21237let CextOpcode = "S2_storerd";
21238let isPredicable = 1;
21239let Constraints = "$Rx32 = $Rx32in";
21240}
21241def S2_storerd_pr : HInst<
21242(outs IntRegs:$Rx32),
21243(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32),
21244"memd($Rx32++$Mu2) = $Rtt32",
21245tc_a2b365d2, TypeST>, Enc_928ca1 {
21246let Inst{7-0} = 0b00000000;
21247let Inst{31-21} = 0b10101101110;
21248let addrMode = PostInc;
21249let accessSize = DoubleWordAccess;
21250let mayStore = 1;
21251let Constraints = "$Rx32 = $Rx32in";
21252}
21253def S2_storerd_zomap : HInst<
21254(outs),
21255(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
21256"memd($Rs32) = $Rtt32",
21257tc_ae5babd7, TypeMAPPING> {
21258let isPseudo = 1;
21259let isCodeGenOnly = 1;
21260}
21261def S2_storerdgp : HInst<
21262(outs),
21263(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32),
21264"memd(gp+#$Ii) = $Rtt32",
21265tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel {
21266let Inst{24-21} = 0b0110;
21267let Inst{31-27} = 0b01001;
21268let accessSize = DoubleWordAccess;
21269let mayStore = 1;
21270let Uses = [GP];
21271let BaseOpcode = "S2_storerdabs";
21272let isPredicable = 1;
21273let opExtendable = 0;
21274let isExtentSigned = 0;
21275let opExtentBits = 19;
21276let opExtentAlign = 3;
21277}
21278def S2_storerf_io : HInst<
21279(outs),
21280(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21281"memh($Rs32+#$Ii) = $Rt32.h",
21282tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21283let Inst{24-21} = 0b1011;
21284let Inst{31-27} = 0b10100;
21285let addrMode = BaseImmOffset;
21286let accessSize = HalfWordAccess;
21287let mayStore = 1;
21288let BaseOpcode = "S2_storerf_io";
21289let CextOpcode = "S2_storerf";
21290let InputType = "imm";
21291let isPredicable = 1;
21292let isExtendable = 1;
21293let opExtendable = 1;
21294let isExtentSigned = 1;
21295let opExtentBits = 12;
21296let opExtentAlign = 1;
21297}
21298def S2_storerf_pbr : HInst<
21299(outs IntRegs:$Rx32),
21300(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21301"memh($Rx32++$Mu2:brev) = $Rt32.h",
21302tc_a2b365d2, TypeST>, Enc_d5c73f {
21303let Inst{7-0} = 0b00000000;
21304let Inst{31-21} = 0b10101111011;
21305let addrMode = PostInc;
21306let accessSize = HalfWordAccess;
21307let mayStore = 1;
21308let Constraints = "$Rx32 = $Rx32in";
21309}
21310def S2_storerf_pci : HInst<
21311(outs IntRegs:$Rx32),
21312(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21313"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h",
21314tc_b4dc7630, TypeST>, Enc_935d9b {
21315let Inst{2-0} = 0b000;
21316let Inst{7-7} = 0b0;
21317let Inst{31-21} = 0b10101001011;
21318let addrMode = PostInc;
21319let accessSize = HalfWordAccess;
21320let mayStore = 1;
21321let Uses = [CS];
21322let Constraints = "$Rx32 = $Rx32in";
21323}
21324def S2_storerf_pcr : HInst<
21325(outs IntRegs:$Rx32),
21326(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21327"memh($Rx32++I:circ($Mu2)) = $Rt32.h",
21328tc_a2b365d2, TypeST>, Enc_d5c73f {
21329let Inst{7-0} = 0b00000010;
21330let Inst{31-21} = 0b10101001011;
21331let addrMode = PostInc;
21332let accessSize = HalfWordAccess;
21333let mayStore = 1;
21334let Uses = [CS];
21335let Constraints = "$Rx32 = $Rx32in";
21336}
21337def S2_storerf_pi : HInst<
21338(outs IntRegs:$Rx32),
21339(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21340"memh($Rx32++#$Ii) = $Rt32.h",
21341tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21342let Inst{2-0} = 0b000;
21343let Inst{7-7} = 0b0;
21344let Inst{13-13} = 0b0;
21345let Inst{31-21} = 0b10101011011;
21346let addrMode = PostInc;
21347let accessSize = HalfWordAccess;
21348let mayStore = 1;
21349let BaseOpcode = "S2_storerf_pi";
21350let CextOpcode = "S2_storerf";
21351let isPredicable = 1;
21352let Constraints = "$Rx32 = $Rx32in";
21353}
21354def S2_storerf_pr : HInst<
21355(outs IntRegs:$Rx32),
21356(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21357"memh($Rx32++$Mu2) = $Rt32.h",
21358tc_a2b365d2, TypeST>, Enc_d5c73f {
21359let Inst{7-0} = 0b00000000;
21360let Inst{31-21} = 0b10101101011;
21361let addrMode = PostInc;
21362let accessSize = HalfWordAccess;
21363let mayStore = 1;
21364let Constraints = "$Rx32 = $Rx32in";
21365}
21366def S2_storerf_zomap : HInst<
21367(outs),
21368(ins IntRegs:$Rs32, IntRegs:$Rt32),
21369"memh($Rs32) = $Rt32.h",
21370tc_ae5babd7, TypeMAPPING> {
21371let isPseudo = 1;
21372let isCodeGenOnly = 1;
21373}
21374def S2_storerfgp : HInst<
21375(outs),
21376(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21377"memh(gp+#$Ii) = $Rt32.h",
21378tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21379let Inst{24-21} = 0b0011;
21380let Inst{31-27} = 0b01001;
21381let accessSize = HalfWordAccess;
21382let mayStore = 1;
21383let Uses = [GP];
21384let BaseOpcode = "S2_storerfabs";
21385let isPredicable = 1;
21386let opExtendable = 0;
21387let isExtentSigned = 0;
21388let opExtentBits = 17;
21389let opExtentAlign = 1;
21390}
21391def S2_storerh_io : HInst<
21392(outs),
21393(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
21394"memh($Rs32+#$Ii) = $Rt32",
21395tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm {
21396let Inst{24-21} = 0b1010;
21397let Inst{31-27} = 0b10100;
21398let addrMode = BaseImmOffset;
21399let accessSize = HalfWordAccess;
21400let mayStore = 1;
21401let BaseOpcode = "S2_storerh_io";
21402let CextOpcode = "S2_storerh";
21403let InputType = "imm";
21404let isNVStorable = 1;
21405let isPredicable = 1;
21406let isExtendable = 1;
21407let opExtendable = 1;
21408let isExtentSigned = 1;
21409let opExtentBits = 12;
21410let opExtentAlign = 1;
21411}
21412def S2_storerh_pbr : HInst<
21413(outs IntRegs:$Rx32),
21414(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21415"memh($Rx32++$Mu2:brev) = $Rt32",
21416tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21417let Inst{7-0} = 0b00000000;
21418let Inst{31-21} = 0b10101111010;
21419let addrMode = PostInc;
21420let accessSize = HalfWordAccess;
21421let mayStore = 1;
21422let BaseOpcode = "S2_storerh_pbr";
21423let isNVStorable = 1;
21424let Constraints = "$Rx32 = $Rx32in";
21425}
21426def S2_storerh_pci : HInst<
21427(outs IntRegs:$Rx32),
21428(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21429"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21430tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel {
21431let Inst{2-0} = 0b000;
21432let Inst{7-7} = 0b0;
21433let Inst{31-21} = 0b10101001010;
21434let addrMode = PostInc;
21435let accessSize = HalfWordAccess;
21436let mayStore = 1;
21437let Uses = [CS];
21438let BaseOpcode = "S2_storerh_pci";
21439let isNVStorable = 1;
21440let Constraints = "$Rx32 = $Rx32in";
21441}
21442def S2_storerh_pcr : HInst<
21443(outs IntRegs:$Rx32),
21444(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21445"memh($Rx32++I:circ($Mu2)) = $Rt32",
21446tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21447let Inst{7-0} = 0b00000010;
21448let Inst{31-21} = 0b10101001010;
21449let addrMode = PostInc;
21450let accessSize = HalfWordAccess;
21451let mayStore = 1;
21452let Uses = [CS];
21453let BaseOpcode = "S2_storerh_pcr";
21454let isNVStorable = 1;
21455let Constraints = "$Rx32 = $Rx32in";
21456}
21457def S2_storerh_pi : HInst<
21458(outs IntRegs:$Rx32),
21459(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32),
21460"memh($Rx32++#$Ii) = $Rt32",
21461tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm {
21462let Inst{2-0} = 0b000;
21463let Inst{7-7} = 0b0;
21464let Inst{13-13} = 0b0;
21465let Inst{31-21} = 0b10101011010;
21466let addrMode = PostInc;
21467let accessSize = HalfWordAccess;
21468let mayStore = 1;
21469let BaseOpcode = "S2_storerh_pi";
21470let CextOpcode = "S2_storerh";
21471let isNVStorable = 1;
21472let isPredicable = 1;
21473let Constraints = "$Rx32 = $Rx32in";
21474}
21475def S2_storerh_pr : HInst<
21476(outs IntRegs:$Rx32),
21477(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21478"memh($Rx32++$Mu2) = $Rt32",
21479tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21480let Inst{7-0} = 0b00000000;
21481let Inst{31-21} = 0b10101101010;
21482let addrMode = PostInc;
21483let accessSize = HalfWordAccess;
21484let mayStore = 1;
21485let BaseOpcode = "S2_storerh_pr";
21486let isNVStorable = 1;
21487let Constraints = "$Rx32 = $Rx32in";
21488}
21489def S2_storerh_zomap : HInst<
21490(outs),
21491(ins IntRegs:$Rs32, IntRegs:$Rt32),
21492"memh($Rs32) = $Rt32",
21493tc_ae5babd7, TypeMAPPING> {
21494let isPseudo = 1;
21495let isCodeGenOnly = 1;
21496}
21497def S2_storerhgp : HInst<
21498(outs),
21499(ins u31_1Imm:$Ii, IntRegs:$Rt32),
21500"memh(gp+#$Ii) = $Rt32",
21501tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel {
21502let Inst{24-21} = 0b0010;
21503let Inst{31-27} = 0b01001;
21504let accessSize = HalfWordAccess;
21505let mayStore = 1;
21506let Uses = [GP];
21507let BaseOpcode = "S2_storerhabs";
21508let isNVStorable = 1;
21509let isPredicable = 1;
21510let opExtendable = 0;
21511let isExtentSigned = 0;
21512let opExtentBits = 17;
21513let opExtentAlign = 1;
21514}
21515def S2_storerhnew_io : HInst<
21516(outs),
21517(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8),
21518"memh($Rs32+#$Ii) = $Nt8.new",
21519tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel {
21520let Inst{12-11} = 0b01;
21521let Inst{24-21} = 0b1101;
21522let Inst{31-27} = 0b10100;
21523let addrMode = BaseImmOffset;
21524let accessSize = HalfWordAccess;
21525let isNVStore = 1;
21526let isNewValue = 1;
21527let isRestrictNoSlot1Store = 1;
21528let mayStore = 1;
21529let BaseOpcode = "S2_storerh_io";
21530let CextOpcode = "S2_storerh";
21531let InputType = "imm";
21532let isPredicable = 1;
21533let isExtendable = 1;
21534let opExtendable = 1;
21535let isExtentSigned = 1;
21536let opExtentBits = 12;
21537let opExtentAlign = 1;
21538let opNewValue = 2;
21539}
21540def S2_storerhnew_pbr : HInst<
21541(outs IntRegs:$Rx32),
21542(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21543"memh($Rx32++$Mu2:brev) = $Nt8.new",
21544tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21545let Inst{7-0} = 0b00000000;
21546let Inst{12-11} = 0b01;
21547let Inst{31-21} = 0b10101111101;
21548let addrMode = PostInc;
21549let accessSize = HalfWordAccess;
21550let isNVStore = 1;
21551let isNewValue = 1;
21552let isRestrictNoSlot1Store = 1;
21553let mayStore = 1;
21554let BaseOpcode = "S2_storerh_pbr";
21555let opNewValue = 3;
21556let Constraints = "$Rx32 = $Rx32in";
21557}
21558def S2_storerhnew_pci : HInst<
21559(outs IntRegs:$Rx32),
21560(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21561"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21562tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel {
21563let Inst{2-0} = 0b000;
21564let Inst{7-7} = 0b0;
21565let Inst{12-11} = 0b01;
21566let Inst{31-21} = 0b10101001101;
21567let addrMode = PostInc;
21568let accessSize = HalfWordAccess;
21569let isNVStore = 1;
21570let isNewValue = 1;
21571let isRestrictNoSlot1Store = 1;
21572let mayStore = 1;
21573let Uses = [CS];
21574let BaseOpcode = "S2_storerh_pci";
21575let opNewValue = 4;
21576let Constraints = "$Rx32 = $Rx32in";
21577}
21578def S2_storerhnew_pcr : HInst<
21579(outs IntRegs:$Rx32),
21580(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21581"memh($Rx32++I:circ($Mu2)) = $Nt8.new",
21582tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21583let Inst{7-0} = 0b00000010;
21584let Inst{12-11} = 0b01;
21585let Inst{31-21} = 0b10101001101;
21586let addrMode = PostInc;
21587let accessSize = HalfWordAccess;
21588let isNVStore = 1;
21589let isNewValue = 1;
21590let isRestrictNoSlot1Store = 1;
21591let mayStore = 1;
21592let Uses = [CS];
21593let BaseOpcode = "S2_storerh_pcr";
21594let opNewValue = 3;
21595let Constraints = "$Rx32 = $Rx32in";
21596}
21597def S2_storerhnew_pi : HInst<
21598(outs IntRegs:$Rx32),
21599(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8),
21600"memh($Rx32++#$Ii) = $Nt8.new",
21601tc_92240447, TypeST>, Enc_e26546, AddrModeRel {
21602let Inst{2-0} = 0b000;
21603let Inst{7-7} = 0b0;
21604let Inst{13-11} = 0b001;
21605let Inst{31-21} = 0b10101011101;
21606let addrMode = PostInc;
21607let accessSize = HalfWordAccess;
21608let isNVStore = 1;
21609let isNewValue = 1;
21610let isRestrictNoSlot1Store = 1;
21611let mayStore = 1;
21612let BaseOpcode = "S2_storerh_pi";
21613let isNVStorable = 1;
21614let isPredicable = 1;
21615let opNewValue = 3;
21616let Constraints = "$Rx32 = $Rx32in";
21617}
21618def S2_storerhnew_pr : HInst<
21619(outs IntRegs:$Rx32),
21620(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21621"memh($Rx32++$Mu2) = $Nt8.new",
21622tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21623let Inst{7-0} = 0b00000000;
21624let Inst{12-11} = 0b01;
21625let Inst{31-21} = 0b10101101101;
21626let addrMode = PostInc;
21627let accessSize = HalfWordAccess;
21628let isNVStore = 1;
21629let isNewValue = 1;
21630let isRestrictNoSlot1Store = 1;
21631let mayStore = 1;
21632let BaseOpcode = "S2_storerh_pr";
21633let opNewValue = 3;
21634let Constraints = "$Rx32 = $Rx32in";
21635}
21636def S2_storerhnew_zomap : HInst<
21637(outs),
21638(ins IntRegs:$Rs32, IntRegs:$Nt8),
21639"memh($Rs32) = $Nt8.new",
21640tc_5deb5e47, TypeMAPPING> {
21641let isPseudo = 1;
21642let isCodeGenOnly = 1;
21643let opNewValue = 1;
21644}
21645def S2_storerhnewgp : HInst<
21646(outs),
21647(ins u31_1Imm:$Ii, IntRegs:$Nt8),
21648"memh(gp+#$Ii) = $Nt8.new",
21649tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel {
21650let Inst{12-11} = 0b01;
21651let Inst{24-21} = 0b0101;
21652let Inst{31-27} = 0b01001;
21653let accessSize = HalfWordAccess;
21654let isNVStore = 1;
21655let isNewValue = 1;
21656let isRestrictNoSlot1Store = 1;
21657let mayStore = 1;
21658let Uses = [GP];
21659let BaseOpcode = "S2_storerhabs";
21660let isPredicable = 1;
21661let opExtendable = 0;
21662let isExtentSigned = 0;
21663let opExtentBits = 17;
21664let opExtentAlign = 1;
21665let opNewValue = 1;
21666}
21667def S2_storeri_io : HInst<
21668(outs),
21669(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
21670"memw($Rs32+#$Ii) = $Rt32",
21671tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm {
21672let Inst{24-21} = 0b1100;
21673let Inst{31-27} = 0b10100;
21674let addrMode = BaseImmOffset;
21675let accessSize = WordAccess;
21676let mayStore = 1;
21677let BaseOpcode = "S2_storeri_io";
21678let CextOpcode = "S2_storeri";
21679let InputType = "imm";
21680let isNVStorable = 1;
21681let isPredicable = 1;
21682let isExtendable = 1;
21683let opExtendable = 1;
21684let isExtentSigned = 1;
21685let opExtentBits = 13;
21686let opExtentAlign = 2;
21687}
21688def S2_storeri_pbr : HInst<
21689(outs IntRegs:$Rx32),
21690(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21691"memw($Rx32++$Mu2:brev) = $Rt32",
21692tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21693let Inst{7-0} = 0b00000000;
21694let Inst{31-21} = 0b10101111100;
21695let addrMode = PostInc;
21696let accessSize = WordAccess;
21697let mayStore = 1;
21698let BaseOpcode = "S2_storeri_pbr";
21699let isNVStorable = 1;
21700let Constraints = "$Rx32 = $Rx32in";
21701}
21702def S2_storeri_pci : HInst<
21703(outs IntRegs:$Rx32),
21704(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32),
21705"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32",
21706tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel {
21707let Inst{2-0} = 0b000;
21708let Inst{7-7} = 0b0;
21709let Inst{31-21} = 0b10101001100;
21710let addrMode = PostInc;
21711let accessSize = WordAccess;
21712let mayStore = 1;
21713let Uses = [CS];
21714let BaseOpcode = "S2_storeri_pci";
21715let isNVStorable = 1;
21716let Constraints = "$Rx32 = $Rx32in";
21717}
21718def S2_storeri_pcr : HInst<
21719(outs IntRegs:$Rx32),
21720(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21721"memw($Rx32++I:circ($Mu2)) = $Rt32",
21722tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21723let Inst{7-0} = 0b00000010;
21724let Inst{31-21} = 0b10101001100;
21725let addrMode = PostInc;
21726let accessSize = WordAccess;
21727let mayStore = 1;
21728let Uses = [CS];
21729let BaseOpcode = "S2_storeri_pcr";
21730let isNVStorable = 1;
21731let Constraints = "$Rx32 = $Rx32in";
21732}
21733def S2_storeri_pi : HInst<
21734(outs IntRegs:$Rx32),
21735(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32),
21736"memw($Rx32++#$Ii) = $Rt32",
21737tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm {
21738let Inst{2-0} = 0b000;
21739let Inst{7-7} = 0b0;
21740let Inst{13-13} = 0b0;
21741let Inst{31-21} = 0b10101011100;
21742let addrMode = PostInc;
21743let accessSize = WordAccess;
21744let mayStore = 1;
21745let BaseOpcode = "S2_storeri_pi";
21746let CextOpcode = "S2_storeri";
21747let isNVStorable = 1;
21748let isPredicable = 1;
21749let Constraints = "$Rx32 = $Rx32in";
21750}
21751def S2_storeri_pr : HInst<
21752(outs IntRegs:$Rx32),
21753(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32),
21754"memw($Rx32++$Mu2) = $Rt32",
21755tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel {
21756let Inst{7-0} = 0b00000000;
21757let Inst{31-21} = 0b10101101100;
21758let addrMode = PostInc;
21759let accessSize = WordAccess;
21760let mayStore = 1;
21761let BaseOpcode = "S2_storeri_pr";
21762let isNVStorable = 1;
21763let Constraints = "$Rx32 = $Rx32in";
21764}
21765def S2_storeri_zomap : HInst<
21766(outs),
21767(ins IntRegs:$Rs32, IntRegs:$Rt32),
21768"memw($Rs32) = $Rt32",
21769tc_ae5babd7, TypeMAPPING> {
21770let isPseudo = 1;
21771let isCodeGenOnly = 1;
21772}
21773def S2_storerigp : HInst<
21774(outs),
21775(ins u30_2Imm:$Ii, IntRegs:$Rt32),
21776"memw(gp+#$Ii) = $Rt32",
21777tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel {
21778let Inst{24-21} = 0b0100;
21779let Inst{31-27} = 0b01001;
21780let accessSize = WordAccess;
21781let mayStore = 1;
21782let Uses = [GP];
21783let BaseOpcode = "S2_storeriabs";
21784let isNVStorable = 1;
21785let isPredicable = 1;
21786let opExtendable = 0;
21787let isExtentSigned = 0;
21788let opExtentBits = 18;
21789let opExtentAlign = 2;
21790}
21791def S2_storerinew_io : HInst<
21792(outs),
21793(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8),
21794"memw($Rs32+#$Ii) = $Nt8.new",
21795tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel {
21796let Inst{12-11} = 0b10;
21797let Inst{24-21} = 0b1101;
21798let Inst{31-27} = 0b10100;
21799let addrMode = BaseImmOffset;
21800let accessSize = WordAccess;
21801let isNVStore = 1;
21802let isNewValue = 1;
21803let isRestrictNoSlot1Store = 1;
21804let mayStore = 1;
21805let BaseOpcode = "S2_storeri_io";
21806let CextOpcode = "S2_storeri";
21807let InputType = "imm";
21808let isPredicable = 1;
21809let isExtendable = 1;
21810let opExtendable = 1;
21811let isExtentSigned = 1;
21812let opExtentBits = 13;
21813let opExtentAlign = 2;
21814let opNewValue = 2;
21815}
21816def S2_storerinew_pbr : HInst<
21817(outs IntRegs:$Rx32),
21818(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21819"memw($Rx32++$Mu2:brev) = $Nt8.new",
21820tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21821let Inst{7-0} = 0b00000000;
21822let Inst{12-11} = 0b10;
21823let Inst{31-21} = 0b10101111101;
21824let addrMode = PostInc;
21825let accessSize = WordAccess;
21826let isNVStore = 1;
21827let isNewValue = 1;
21828let isRestrictNoSlot1Store = 1;
21829let mayStore = 1;
21830let BaseOpcode = "S2_storeri_pbr";
21831let opNewValue = 3;
21832let Constraints = "$Rx32 = $Rx32in";
21833}
21834def S2_storerinew_pci : HInst<
21835(outs IntRegs:$Rx32),
21836(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8),
21837"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new",
21838tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel {
21839let Inst{2-0} = 0b000;
21840let Inst{7-7} = 0b0;
21841let Inst{12-11} = 0b10;
21842let Inst{31-21} = 0b10101001101;
21843let addrMode = PostInc;
21844let accessSize = WordAccess;
21845let isNVStore = 1;
21846let isNewValue = 1;
21847let isRestrictNoSlot1Store = 1;
21848let mayStore = 1;
21849let Uses = [CS];
21850let BaseOpcode = "S2_storeri_pci";
21851let opNewValue = 4;
21852let Constraints = "$Rx32 = $Rx32in";
21853}
21854def S2_storerinew_pcr : HInst<
21855(outs IntRegs:$Rx32),
21856(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21857"memw($Rx32++I:circ($Mu2)) = $Nt8.new",
21858tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21859let Inst{7-0} = 0b00000010;
21860let Inst{12-11} = 0b10;
21861let Inst{31-21} = 0b10101001101;
21862let addrMode = PostInc;
21863let accessSize = WordAccess;
21864let isNVStore = 1;
21865let isNewValue = 1;
21866let isRestrictNoSlot1Store = 1;
21867let mayStore = 1;
21868let Uses = [CS];
21869let BaseOpcode = "S2_storeri_pcr";
21870let opNewValue = 3;
21871let Constraints = "$Rx32 = $Rx32in";
21872}
21873def S2_storerinew_pi : HInst<
21874(outs IntRegs:$Rx32),
21875(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8),
21876"memw($Rx32++#$Ii) = $Nt8.new",
21877tc_92240447, TypeST>, Enc_223005, AddrModeRel {
21878let Inst{2-0} = 0b000;
21879let Inst{7-7} = 0b0;
21880let Inst{13-11} = 0b010;
21881let Inst{31-21} = 0b10101011101;
21882let addrMode = PostInc;
21883let accessSize = WordAccess;
21884let isNVStore = 1;
21885let isNewValue = 1;
21886let isRestrictNoSlot1Store = 1;
21887let mayStore = 1;
21888let BaseOpcode = "S2_storeri_pi";
21889let isPredicable = 1;
21890let opNewValue = 3;
21891let Constraints = "$Rx32 = $Rx32in";
21892}
21893def S2_storerinew_pr : HInst<
21894(outs IntRegs:$Rx32),
21895(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8),
21896"memw($Rx32++$Mu2) = $Nt8.new",
21897tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel {
21898let Inst{7-0} = 0b00000000;
21899let Inst{12-11} = 0b10;
21900let Inst{31-21} = 0b10101101101;
21901let addrMode = PostInc;
21902let accessSize = WordAccess;
21903let isNVStore = 1;
21904let isNewValue = 1;
21905let isRestrictNoSlot1Store = 1;
21906let mayStore = 1;
21907let BaseOpcode = "S2_storeri_pr";
21908let opNewValue = 3;
21909let Constraints = "$Rx32 = $Rx32in";
21910}
21911def S2_storerinew_zomap : HInst<
21912(outs),
21913(ins IntRegs:$Rs32, IntRegs:$Nt8),
21914"memw($Rs32) = $Nt8.new",
21915tc_5deb5e47, TypeMAPPING> {
21916let isPseudo = 1;
21917let isCodeGenOnly = 1;
21918let opNewValue = 1;
21919}
21920def S2_storerinewgp : HInst<
21921(outs),
21922(ins u30_2Imm:$Ii, IntRegs:$Nt8),
21923"memw(gp+#$Ii) = $Nt8.new",
21924tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel {
21925let Inst{12-11} = 0b10;
21926let Inst{24-21} = 0b0101;
21927let Inst{31-27} = 0b01001;
21928let accessSize = WordAccess;
21929let isNVStore = 1;
21930let isNewValue = 1;
21931let isRestrictNoSlot1Store = 1;
21932let mayStore = 1;
21933let Uses = [GP];
21934let BaseOpcode = "S2_storeriabs";
21935let isPredicable = 1;
21936let opExtendable = 0;
21937let isExtentSigned = 0;
21938let opExtentBits = 18;
21939let opExtentAlign = 2;
21940let opNewValue = 1;
21941}
21942def S2_storew_locked : HInst<
21943(outs PredRegs:$Pd4),
21944(ins IntRegs:$Rs32, IntRegs:$Rt32),
21945"memw_locked($Rs32,$Pd4) = $Rt32",
21946tc_6f42bc60, TypeST>, Enc_c2b48e {
21947let Inst{7-2} = 0b000000;
21948let Inst{13-13} = 0b0;
21949let Inst{31-21} = 0b10100000101;
21950let accessSize = WordAccess;
21951let isPredicateLate = 1;
21952let isSoloAX = 1;
21953let mayStore = 1;
21954}
21955def S2_storew_rl_at_vi : HInst<
21956(outs),
21957(ins IntRegs:$Rs32, IntRegs:$Rt32),
21958"memw_rl($Rs32):at = $Rt32",
21959tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21960let Inst{7-2} = 0b000010;
21961let Inst{13-13} = 0b0;
21962let Inst{31-21} = 0b10100000101;
21963let accessSize = WordAccess;
21964let isSolo = 1;
21965let mayStore = 1;
21966}
21967def S2_storew_rl_st_vi : HInst<
21968(outs),
21969(ins IntRegs:$Rs32, IntRegs:$Rt32),
21970"memw_rl($Rs32):st = $Rt32",
21971tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
21972let Inst{7-2} = 0b001010;
21973let Inst{13-13} = 0b0;
21974let Inst{31-21} = 0b10100000101;
21975let accessSize = WordAccess;
21976let isSolo = 1;
21977let mayStore = 1;
21978}
21979def S2_svsathb : HInst<
21980(outs IntRegs:$Rd32),
21981(ins IntRegs:$Rs32),
21982"$Rd32 = vsathb($Rs32)",
21983tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21984let Inst{13-5} = 0b000000000;
21985let Inst{31-21} = 0b10001100100;
21986let hasNewValue = 1;
21987let opNewValue = 0;
21988let Defs = [USR_OVF];
21989}
21990def S2_svsathub : HInst<
21991(outs IntRegs:$Rd32),
21992(ins IntRegs:$Rs32),
21993"$Rd32 = vsathub($Rs32)",
21994tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
21995let Inst{13-5} = 0b000000010;
21996let Inst{31-21} = 0b10001100100;
21997let hasNewValue = 1;
21998let opNewValue = 0;
21999let Defs = [USR_OVF];
22000}
22001def S2_tableidxb : HInst<
22002(outs IntRegs:$Rx32),
22003(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22004"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw",
22005tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22006let Inst{31-22} = 0b1000011100;
22007let hasNewValue = 1;
22008let opNewValue = 0;
22009let prefersSlot3 = 1;
22010let Constraints = "$Rx32 = $Rx32in";
22011}
22012def S2_tableidxb_goodsyntax : HInst<
22013(outs IntRegs:$Rx32),
22014(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22015"$Rx32 = tableidxb($Rs32,#$Ii,#$II)",
22016tc_bb831a7c, TypeS_2op> {
22017let hasNewValue = 1;
22018let opNewValue = 0;
22019let isPseudo = 1;
22020let isCodeGenOnly = 1;
22021let Constraints = "$Rx32 = $Rx32in";
22022}
22023def S2_tableidxd : HInst<
22024(outs IntRegs:$Rx32),
22025(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22026"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw",
22027tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22028let Inst{31-22} = 0b1000011111;
22029let hasNewValue = 1;
22030let opNewValue = 0;
22031let prefersSlot3 = 1;
22032let Constraints = "$Rx32 = $Rx32in";
22033}
22034def S2_tableidxd_goodsyntax : HInst<
22035(outs IntRegs:$Rx32),
22036(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22037"$Rx32 = tableidxd($Rs32,#$Ii,#$II)",
22038tc_bb831a7c, TypeS_2op> {
22039let hasNewValue = 1;
22040let opNewValue = 0;
22041let isPseudo = 1;
22042let Constraints = "$Rx32 = $Rx32in";
22043}
22044def S2_tableidxh : HInst<
22045(outs IntRegs:$Rx32),
22046(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22047"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw",
22048tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22049let Inst{31-22} = 0b1000011101;
22050let hasNewValue = 1;
22051let opNewValue = 0;
22052let prefersSlot3 = 1;
22053let Constraints = "$Rx32 = $Rx32in";
22054}
22055def S2_tableidxh_goodsyntax : HInst<
22056(outs IntRegs:$Rx32),
22057(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22058"$Rx32 = tableidxh($Rs32,#$Ii,#$II)",
22059tc_bb831a7c, TypeS_2op> {
22060let hasNewValue = 1;
22061let opNewValue = 0;
22062let isPseudo = 1;
22063let Constraints = "$Rx32 = $Rx32in";
22064}
22065def S2_tableidxw : HInst<
22066(outs IntRegs:$Rx32),
22067(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II),
22068"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw",
22069tc_bb831a7c, TypeS_2op>, Enc_cd82bc {
22070let Inst{31-22} = 0b1000011110;
22071let hasNewValue = 1;
22072let opNewValue = 0;
22073let prefersSlot3 = 1;
22074let Constraints = "$Rx32 = $Rx32in";
22075}
22076def S2_tableidxw_goodsyntax : HInst<
22077(outs IntRegs:$Rx32),
22078(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II),
22079"$Rx32 = tableidxw($Rs32,#$Ii,#$II)",
22080tc_bb831a7c, TypeS_2op> {
22081let hasNewValue = 1;
22082let opNewValue = 0;
22083let isPseudo = 1;
22084let Constraints = "$Rx32 = $Rx32in";
22085}
22086def S2_togglebit_i : HInst<
22087(outs IntRegs:$Rd32),
22088(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22089"$Rd32 = togglebit($Rs32,#$Ii)",
22090tc_5da50c4b, TypeS_2op>, Enc_a05677 {
22091let Inst{7-5} = 0b010;
22092let Inst{13-13} = 0b0;
22093let Inst{31-21} = 0b10001100110;
22094let hasNewValue = 1;
22095let opNewValue = 0;
22096}
22097def S2_togglebit_r : HInst<
22098(outs IntRegs:$Rd32),
22099(ins IntRegs:$Rs32, IntRegs:$Rt32),
22100"$Rd32 = togglebit($Rs32,$Rt32)",
22101tc_5da50c4b, TypeS_3op>, Enc_5ab2be {
22102let Inst{7-5} = 0b100;
22103let Inst{13-13} = 0b0;
22104let Inst{31-21} = 0b11000110100;
22105let hasNewValue = 1;
22106let opNewValue = 0;
22107}
22108def S2_tstbit_i : HInst<
22109(outs PredRegs:$Pd4),
22110(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22111"$Pd4 = tstbit($Rs32,#$Ii)",
22112tc_a1297125, TypeS_2op>, Enc_83ee64 {
22113let Inst{7-2} = 0b000000;
22114let Inst{13-13} = 0b0;
22115let Inst{31-21} = 0b10000101000;
22116}
22117def S2_tstbit_r : HInst<
22118(outs PredRegs:$Pd4),
22119(ins IntRegs:$Rs32, IntRegs:$Rt32),
22120"$Pd4 = tstbit($Rs32,$Rt32)",
22121tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22122let Inst{7-2} = 0b000000;
22123let Inst{13-13} = 0b0;
22124let Inst{31-21} = 0b11000111000;
22125}
22126def S2_valignib : HInst<
22127(outs DoubleRegs:$Rdd32),
22128(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii),
22129"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)",
22130tc_6fc5dbea, TypeS_3op>, Enc_729ff7 {
22131let Inst{13-13} = 0b0;
22132let Inst{31-21} = 0b11000000000;
22133}
22134def S2_valignrb : HInst<
22135(outs DoubleRegs:$Rdd32),
22136(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4),
22137"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)",
22138tc_6fc5dbea, TypeS_3op>, Enc_8c6530 {
22139let Inst{7-7} = 0b0;
22140let Inst{13-13} = 0b0;
22141let Inst{31-21} = 0b11000010000;
22142}
22143def S2_vcnegh : HInst<
22144(outs DoubleRegs:$Rdd32),
22145(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22146"$Rdd32 = vcnegh($Rss32,$Rt32)",
22147tc_8a825db2, TypeS_3op>, Enc_927852 {
22148let Inst{7-5} = 0b010;
22149let Inst{13-13} = 0b0;
22150let Inst{31-21} = 0b11000011110;
22151let prefersSlot3 = 1;
22152let Defs = [USR_OVF];
22153}
22154def S2_vcrotate : HInst<
22155(outs DoubleRegs:$Rdd32),
22156(ins DoubleRegs:$Rss32, IntRegs:$Rt32),
22157"$Rdd32 = vcrotate($Rss32,$Rt32)",
22158tc_0dfac0a7, TypeS_3op>, Enc_927852 {
22159let Inst{7-5} = 0b000;
22160let Inst{13-13} = 0b0;
22161let Inst{31-21} = 0b11000011110;
22162let prefersSlot3 = 1;
22163let Defs = [USR_OVF];
22164}
22165def S2_vrcnegh : HInst<
22166(outs DoubleRegs:$Rxx32),
22167(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32),
22168"$Rxx32 += vrcnegh($Rss32,$Rt32)",
22169tc_7f8ae742, TypeS_3op>, Enc_1aa186 {
22170let Inst{7-5} = 0b111;
22171let Inst{13-13} = 0b1;
22172let Inst{31-21} = 0b11001011001;
22173let prefersSlot3 = 1;
22174let Constraints = "$Rxx32 = $Rxx32in";
22175}
22176def S2_vrndpackwh : HInst<
22177(outs IntRegs:$Rd32),
22178(ins DoubleRegs:$Rss32),
22179"$Rd32 = vrndwh($Rss32)",
22180tc_e3d699e3, TypeS_2op>, Enc_90cd8b {
22181let Inst{13-5} = 0b000000100;
22182let Inst{31-21} = 0b10001000100;
22183let hasNewValue = 1;
22184let opNewValue = 0;
22185let prefersSlot3 = 1;
22186}
22187def S2_vrndpackwhs : HInst<
22188(outs IntRegs:$Rd32),
22189(ins DoubleRegs:$Rss32),
22190"$Rd32 = vrndwh($Rss32):sat",
22191tc_d61dfdc3, TypeS_2op>, Enc_90cd8b {
22192let Inst{13-5} = 0b000000110;
22193let Inst{31-21} = 0b10001000100;
22194let hasNewValue = 1;
22195let opNewValue = 0;
22196let prefersSlot3 = 1;
22197let Defs = [USR_OVF];
22198}
22199def S2_vsathb : HInst<
22200(outs IntRegs:$Rd32),
22201(ins DoubleRegs:$Rss32),
22202"$Rd32 = vsathb($Rss32)",
22203tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22204let Inst{13-5} = 0b000000110;
22205let Inst{31-21} = 0b10001000000;
22206let hasNewValue = 1;
22207let opNewValue = 0;
22208let Defs = [USR_OVF];
22209}
22210def S2_vsathb_nopack : HInst<
22211(outs DoubleRegs:$Rdd32),
22212(ins DoubleRegs:$Rss32),
22213"$Rdd32 = vsathb($Rss32)",
22214tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22215let Inst{13-5} = 0b000000111;
22216let Inst{31-21} = 0b10000000000;
22217let Defs = [USR_OVF];
22218}
22219def S2_vsathub : HInst<
22220(outs IntRegs:$Rd32),
22221(ins DoubleRegs:$Rss32),
22222"$Rd32 = vsathub($Rss32)",
22223tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22224let Inst{13-5} = 0b000000000;
22225let Inst{31-21} = 0b10001000000;
22226let hasNewValue = 1;
22227let opNewValue = 0;
22228let Defs = [USR_OVF];
22229}
22230def S2_vsathub_nopack : HInst<
22231(outs DoubleRegs:$Rdd32),
22232(ins DoubleRegs:$Rss32),
22233"$Rdd32 = vsathub($Rss32)",
22234tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22235let Inst{13-5} = 0b000000100;
22236let Inst{31-21} = 0b10000000000;
22237let Defs = [USR_OVF];
22238}
22239def S2_vsatwh : HInst<
22240(outs IntRegs:$Rd32),
22241(ins DoubleRegs:$Rss32),
22242"$Rd32 = vsatwh($Rss32)",
22243tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22244let Inst{13-5} = 0b000000010;
22245let Inst{31-21} = 0b10001000000;
22246let hasNewValue = 1;
22247let opNewValue = 0;
22248let Defs = [USR_OVF];
22249}
22250def S2_vsatwh_nopack : HInst<
22251(outs DoubleRegs:$Rdd32),
22252(ins DoubleRegs:$Rss32),
22253"$Rdd32 = vsatwh($Rss32)",
22254tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22255let Inst{13-5} = 0b000000110;
22256let Inst{31-21} = 0b10000000000;
22257let Defs = [USR_OVF];
22258}
22259def S2_vsatwuh : HInst<
22260(outs IntRegs:$Rd32),
22261(ins DoubleRegs:$Rss32),
22262"$Rd32 = vsatwuh($Rss32)",
22263tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22264let Inst{13-5} = 0b000000100;
22265let Inst{31-21} = 0b10001000000;
22266let hasNewValue = 1;
22267let opNewValue = 0;
22268let Defs = [USR_OVF];
22269}
22270def S2_vsatwuh_nopack : HInst<
22271(outs DoubleRegs:$Rdd32),
22272(ins DoubleRegs:$Rss32),
22273"$Rdd32 = vsatwuh($Rss32)",
22274tc_9f6cd987, TypeS_2op>, Enc_b9c5fb {
22275let Inst{13-5} = 0b000000101;
22276let Inst{31-21} = 0b10000000000;
22277let Defs = [USR_OVF];
22278}
22279def S2_vsplatrb : HInst<
22280(outs IntRegs:$Rd32),
22281(ins IntRegs:$Rs32),
22282"$Rd32 = vsplatb($Rs32)",
22283tc_9f6cd987, TypeS_2op>, Enc_5e2823 {
22284let Inst{13-5} = 0b000000111;
22285let Inst{31-21} = 0b10001100010;
22286let hasNewValue = 1;
22287let opNewValue = 0;
22288let isAsCheapAsAMove = 1;
22289let isReMaterializable = 1;
22290}
22291def S2_vsplatrh : HInst<
22292(outs DoubleRegs:$Rdd32),
22293(ins IntRegs:$Rs32),
22294"$Rdd32 = vsplath($Rs32)",
22295tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22296let Inst{13-5} = 0b000000010;
22297let Inst{31-21} = 0b10000100010;
22298let isAsCheapAsAMove = 1;
22299let isReMaterializable = 1;
22300}
22301def S2_vspliceib : HInst<
22302(outs DoubleRegs:$Rdd32),
22303(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii),
22304"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)",
22305tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 {
22306let Inst{13-13} = 0b0;
22307let Inst{31-21} = 0b11000000100;
22308}
22309def S2_vsplicerb : HInst<
22310(outs DoubleRegs:$Rdd32),
22311(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4),
22312"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)",
22313tc_6fc5dbea, TypeS_3op>, Enc_dbd70c {
22314let Inst{7-7} = 0b0;
22315let Inst{13-13} = 0b0;
22316let Inst{31-21} = 0b11000010100;
22317}
22318def S2_vsxtbh : HInst<
22319(outs DoubleRegs:$Rdd32),
22320(ins IntRegs:$Rs32),
22321"$Rdd32 = vsxtbh($Rs32)",
22322tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22323let Inst{13-5} = 0b000000000;
22324let Inst{31-21} = 0b10000100000;
22325let isAsCheapAsAMove = 1;
22326let isReMaterializable = 1;
22327}
22328def S2_vsxthw : HInst<
22329(outs DoubleRegs:$Rdd32),
22330(ins IntRegs:$Rs32),
22331"$Rdd32 = vsxthw($Rs32)",
22332tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22333let Inst{13-5} = 0b000000100;
22334let Inst{31-21} = 0b10000100000;
22335let isAsCheapAsAMove = 1;
22336let isReMaterializable = 1;
22337}
22338def S2_vtrunehb : HInst<
22339(outs IntRegs:$Rd32),
22340(ins DoubleRegs:$Rss32),
22341"$Rd32 = vtrunehb($Rss32)",
22342tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22343let Inst{13-5} = 0b000000010;
22344let Inst{31-21} = 0b10001000100;
22345let hasNewValue = 1;
22346let opNewValue = 0;
22347}
22348def S2_vtrunewh : HInst<
22349(outs DoubleRegs:$Rdd32),
22350(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22351"$Rdd32 = vtrunewh($Rss32,$Rtt32)",
22352tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22353let Inst{7-5} = 0b010;
22354let Inst{13-13} = 0b0;
22355let Inst{31-21} = 0b11000001100;
22356}
22357def S2_vtrunohb : HInst<
22358(outs IntRegs:$Rd32),
22359(ins DoubleRegs:$Rss32),
22360"$Rd32 = vtrunohb($Rss32)",
22361tc_9f6cd987, TypeS_2op>, Enc_90cd8b {
22362let Inst{13-5} = 0b000000000;
22363let Inst{31-21} = 0b10001000100;
22364let hasNewValue = 1;
22365let opNewValue = 0;
22366}
22367def S2_vtrunowh : HInst<
22368(outs DoubleRegs:$Rdd32),
22369(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22370"$Rdd32 = vtrunowh($Rss32,$Rtt32)",
22371tc_5da50c4b, TypeS_3op>, Enc_a56825 {
22372let Inst{7-5} = 0b100;
22373let Inst{13-13} = 0b0;
22374let Inst{31-21} = 0b11000001100;
22375}
22376def S2_vzxtbh : HInst<
22377(outs DoubleRegs:$Rdd32),
22378(ins IntRegs:$Rs32),
22379"$Rdd32 = vzxtbh($Rs32)",
22380tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22381let Inst{13-5} = 0b000000010;
22382let Inst{31-21} = 0b10000100000;
22383let isAsCheapAsAMove = 1;
22384let isReMaterializable = 1;
22385}
22386def S2_vzxthw : HInst<
22387(outs DoubleRegs:$Rdd32),
22388(ins IntRegs:$Rs32),
22389"$Rdd32 = vzxthw($Rs32)",
22390tc_9f6cd987, TypeS_2op>, Enc_3a3d62 {
22391let Inst{13-5} = 0b000000110;
22392let Inst{31-21} = 0b10000100000;
22393let isAsCheapAsAMove = 1;
22394let isReMaterializable = 1;
22395}
22396def S4_addaddi : HInst<
22397(outs IntRegs:$Rd32),
22398(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii),
22399"$Rd32 = add($Rs32,add($Ru32,#$Ii))",
22400tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
22401let Inst{31-23} = 0b110110110;
22402let hasNewValue = 1;
22403let opNewValue = 0;
22404let prefersSlot3 = 1;
22405let isExtendable = 1;
22406let opExtendable = 3;
22407let isExtentSigned = 1;
22408let opExtentBits = 6;
22409let opExtentAlign = 0;
22410}
22411def S4_addi_asl_ri : HInst<
22412(outs IntRegs:$Rx32),
22413(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22414"$Rx32 = add(#$Ii,asl($Rx32in,#$II))",
22415tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22416let Inst{2-0} = 0b100;
22417let Inst{4-4} = 0b0;
22418let Inst{31-24} = 0b11011110;
22419let hasNewValue = 1;
22420let opNewValue = 0;
22421let prefersSlot3 = 1;
22422let isExtendable = 1;
22423let opExtendable = 1;
22424let isExtentSigned = 0;
22425let opExtentBits = 8;
22426let opExtentAlign = 0;
22427let Constraints = "$Rx32 = $Rx32in";
22428}
22429def S4_addi_lsr_ri : HInst<
22430(outs IntRegs:$Rx32),
22431(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22432"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))",
22433tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22434let Inst{2-0} = 0b100;
22435let Inst{4-4} = 0b1;
22436let Inst{31-24} = 0b11011110;
22437let hasNewValue = 1;
22438let opNewValue = 0;
22439let prefersSlot3 = 1;
22440let isExtendable = 1;
22441let opExtendable = 1;
22442let isExtentSigned = 0;
22443let opExtentBits = 8;
22444let opExtentAlign = 0;
22445let Constraints = "$Rx32 = $Rx32in";
22446}
22447def S4_andi_asl_ri : HInst<
22448(outs IntRegs:$Rx32),
22449(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22450"$Rx32 = and(#$Ii,asl($Rx32in,#$II))",
22451tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22452let Inst{2-0} = 0b000;
22453let Inst{4-4} = 0b0;
22454let Inst{31-24} = 0b11011110;
22455let hasNewValue = 1;
22456let opNewValue = 0;
22457let prefersSlot3 = 1;
22458let isExtendable = 1;
22459let opExtendable = 1;
22460let isExtentSigned = 0;
22461let opExtentBits = 8;
22462let opExtentAlign = 0;
22463let Constraints = "$Rx32 = $Rx32in";
22464}
22465def S4_andi_lsr_ri : HInst<
22466(outs IntRegs:$Rx32),
22467(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22468"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))",
22469tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22470let Inst{2-0} = 0b000;
22471let Inst{4-4} = 0b1;
22472let Inst{31-24} = 0b11011110;
22473let hasNewValue = 1;
22474let opNewValue = 0;
22475let prefersSlot3 = 1;
22476let isExtendable = 1;
22477let opExtendable = 1;
22478let isExtentSigned = 0;
22479let opExtentBits = 8;
22480let opExtentAlign = 0;
22481let Constraints = "$Rx32 = $Rx32in";
22482}
22483def S4_clbaddi : HInst<
22484(outs IntRegs:$Rd32),
22485(ins IntRegs:$Rs32, s6_0Imm:$Ii),
22486"$Rd32 = add(clb($Rs32),#$Ii)",
22487tc_a08b630b, TypeS_2op>, Enc_9fae8a {
22488let Inst{7-5} = 0b000;
22489let Inst{31-21} = 0b10001100001;
22490let hasNewValue = 1;
22491let opNewValue = 0;
22492let prefersSlot3 = 1;
22493}
22494def S4_clbpaddi : HInst<
22495(outs IntRegs:$Rd32),
22496(ins DoubleRegs:$Rss32, s6_0Imm:$Ii),
22497"$Rd32 = add(clb($Rss32),#$Ii)",
22498tc_a08b630b, TypeS_2op>, Enc_a1640c {
22499let Inst{7-5} = 0b010;
22500let Inst{31-21} = 0b10001000011;
22501let hasNewValue = 1;
22502let opNewValue = 0;
22503let prefersSlot3 = 1;
22504}
22505def S4_clbpnorm : HInst<
22506(outs IntRegs:$Rd32),
22507(ins DoubleRegs:$Rss32),
22508"$Rd32 = normamt($Rss32)",
22509tc_a7bdb22c, TypeS_2op>, Enc_90cd8b {
22510let Inst{13-5} = 0b000000000;
22511let Inst{31-21} = 0b10001000011;
22512let hasNewValue = 1;
22513let opNewValue = 0;
22514let prefersSlot3 = 1;
22515}
22516def S4_extract : HInst<
22517(outs IntRegs:$Rd32),
22518(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II),
22519"$Rd32 = extract($Rs32,#$Ii,#$II)",
22520tc_2c13e7f5, TypeS_2op>, Enc_b388cf {
22521let Inst{13-13} = 0b0;
22522let Inst{31-23} = 0b100011011;
22523let hasNewValue = 1;
22524let opNewValue = 0;
22525let prefersSlot3 = 1;
22526}
22527def S4_extract_rp : HInst<
22528(outs IntRegs:$Rd32),
22529(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
22530"$Rd32 = extract($Rs32,$Rtt32)",
22531tc_a08b630b, TypeS_3op>, Enc_e07374 {
22532let Inst{7-5} = 0b010;
22533let Inst{13-13} = 0b0;
22534let Inst{31-21} = 0b11001001000;
22535let hasNewValue = 1;
22536let opNewValue = 0;
22537let prefersSlot3 = 1;
22538}
22539def S4_extractp : HInst<
22540(outs DoubleRegs:$Rdd32),
22541(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II),
22542"$Rdd32 = extract($Rss32,#$Ii,#$II)",
22543tc_2c13e7f5, TypeS_2op>, Enc_b84c4c {
22544let Inst{31-24} = 0b10001010;
22545let prefersSlot3 = 1;
22546}
22547def S4_extractp_rp : HInst<
22548(outs DoubleRegs:$Rdd32),
22549(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
22550"$Rdd32 = extract($Rss32,$Rtt32)",
22551tc_a08b630b, TypeS_3op>, Enc_a56825 {
22552let Inst{7-5} = 0b100;
22553let Inst{13-13} = 0b0;
22554let Inst{31-21} = 0b11000001110;
22555let prefersSlot3 = 1;
22556}
22557def S4_lsli : HInst<
22558(outs IntRegs:$Rd32),
22559(ins s6_0Imm:$Ii, IntRegs:$Rt32),
22560"$Rd32 = lsl(#$Ii,$Rt32)",
22561tc_5da50c4b, TypeS_3op>, Enc_fef969 {
22562let Inst{7-6} = 0b11;
22563let Inst{13-13} = 0b0;
22564let Inst{31-21} = 0b11000110100;
22565let hasNewValue = 1;
22566let opNewValue = 0;
22567}
22568def S4_ntstbit_i : HInst<
22569(outs PredRegs:$Pd4),
22570(ins IntRegs:$Rs32, u5_0Imm:$Ii),
22571"$Pd4 = !tstbit($Rs32,#$Ii)",
22572tc_a1297125, TypeS_2op>, Enc_83ee64 {
22573let Inst{7-2} = 0b000000;
22574let Inst{13-13} = 0b0;
22575let Inst{31-21} = 0b10000101001;
22576}
22577def S4_ntstbit_r : HInst<
22578(outs PredRegs:$Pd4),
22579(ins IntRegs:$Rs32, IntRegs:$Rt32),
22580"$Pd4 = !tstbit($Rs32,$Rt32)",
22581tc_4a55d03c, TypeS_3op>, Enc_c2b48e {
22582let Inst{7-2} = 0b000000;
22583let Inst{13-13} = 0b0;
22584let Inst{31-21} = 0b11000111001;
22585}
22586def S4_or_andi : HInst<
22587(outs IntRegs:$Rx32),
22588(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22589"$Rx32 |= and($Rs32,#$Ii)",
22590tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22591let Inst{31-22} = 0b1101101000;
22592let hasNewValue = 1;
22593let opNewValue = 0;
22594let prefersSlot3 = 1;
22595let InputType = "imm";
22596let isExtendable = 1;
22597let opExtendable = 3;
22598let isExtentSigned = 1;
22599let opExtentBits = 10;
22600let opExtentAlign = 0;
22601let Constraints = "$Rx32 = $Rx32in";
22602}
22603def S4_or_andix : HInst<
22604(outs IntRegs:$Rx32),
22605(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii),
22606"$Rx32 = or($Ru32,and($Rx32in,#$Ii))",
22607tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> {
22608let Inst{31-22} = 0b1101101001;
22609let hasNewValue = 1;
22610let opNewValue = 0;
22611let prefersSlot3 = 1;
22612let isExtendable = 1;
22613let opExtendable = 3;
22614let isExtentSigned = 1;
22615let opExtentBits = 10;
22616let opExtentAlign = 0;
22617let Constraints = "$Rx32 = $Rx32in";
22618}
22619def S4_or_ori : HInst<
22620(outs IntRegs:$Rx32),
22621(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii),
22622"$Rx32 |= or($Rs32,#$Ii)",
22623tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 {
22624let Inst{31-22} = 0b1101101010;
22625let hasNewValue = 1;
22626let opNewValue = 0;
22627let prefersSlot3 = 1;
22628let InputType = "imm";
22629let isExtendable = 1;
22630let opExtendable = 3;
22631let isExtentSigned = 1;
22632let opExtentBits = 10;
22633let opExtentAlign = 0;
22634let Constraints = "$Rx32 = $Rx32in";
22635}
22636def S4_ori_asl_ri : HInst<
22637(outs IntRegs:$Rx32),
22638(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22639"$Rx32 = or(#$Ii,asl($Rx32in,#$II))",
22640tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22641let Inst{2-0} = 0b010;
22642let Inst{4-4} = 0b0;
22643let Inst{31-24} = 0b11011110;
22644let hasNewValue = 1;
22645let opNewValue = 0;
22646let prefersSlot3 = 1;
22647let isExtendable = 1;
22648let opExtendable = 1;
22649let isExtentSigned = 0;
22650let opExtentBits = 8;
22651let opExtentAlign = 0;
22652let Constraints = "$Rx32 = $Rx32in";
22653}
22654def S4_ori_lsr_ri : HInst<
22655(outs IntRegs:$Rx32),
22656(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
22657"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))",
22658tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
22659let Inst{2-0} = 0b010;
22660let Inst{4-4} = 0b1;
22661let Inst{31-24} = 0b11011110;
22662let hasNewValue = 1;
22663let opNewValue = 0;
22664let prefersSlot3 = 1;
22665let isExtendable = 1;
22666let opExtendable = 1;
22667let isExtentSigned = 0;
22668let opExtentBits = 8;
22669let opExtentAlign = 0;
22670let Constraints = "$Rx32 = $Rx32in";
22671}
22672def S4_parity : HInst<
22673(outs IntRegs:$Rd32),
22674(ins IntRegs:$Rs32, IntRegs:$Rt32),
22675"$Rd32 = parity($Rs32,$Rt32)",
22676tc_a08b630b, TypeALU64>, Enc_5ab2be {
22677let Inst{7-5} = 0b000;
22678let Inst{13-13} = 0b0;
22679let Inst{31-21} = 0b11010101111;
22680let hasNewValue = 1;
22681let opNewValue = 0;
22682let prefersSlot3 = 1;
22683}
22684def S4_pstorerbf_abs : HInst<
22685(outs),
22686(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22687"if (!$Pv4) memb(#$Ii) = $Rt32",
22688tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
22689let Inst{2-2} = 0b1;
22690let Inst{7-7} = 0b1;
22691let Inst{13-13} = 0b0;
22692let Inst{31-18} = 0b10101111000000;
22693let isPredicated = 1;
22694let isPredicatedFalse = 1;
22695let addrMode = Absolute;
22696let accessSize = ByteAccess;
22697let isExtended = 1;
22698let mayStore = 1;
22699let BaseOpcode = "S2_storerbabs";
22700let CextOpcode = "S2_storerb";
22701let isNVStorable = 1;
22702let DecoderNamespace = "MustExtend";
22703let isExtendable = 1;
22704let opExtendable = 1;
22705let isExtentSigned = 0;
22706let opExtentBits = 6;
22707let opExtentAlign = 0;
22708}
22709def S4_pstorerbf_rr : HInst<
22710(outs),
22711(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22712"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22713tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
22714let Inst{31-21} = 0b00110101000;
22715let isPredicated = 1;
22716let isPredicatedFalse = 1;
22717let addrMode = BaseRegOffset;
22718let accessSize = ByteAccess;
22719let mayStore = 1;
22720let BaseOpcode = "S4_storerb_rr";
22721let CextOpcode = "S2_storerb";
22722let InputType = "reg";
22723let isNVStorable = 1;
22724}
22725def S4_pstorerbfnew_abs : HInst<
22726(outs),
22727(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
22728"if (!$Pv4.new) memb(#$Ii) = $Rt32",
22729tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
22730let Inst{2-2} = 0b1;
22731let Inst{7-7} = 0b1;
22732let Inst{13-13} = 0b1;
22733let Inst{31-18} = 0b10101111000000;
22734let isPredicated = 1;
22735let isPredicatedFalse = 1;
22736let addrMode = Absolute;
22737let accessSize = ByteAccess;
22738let isPredicatedNew = 1;
22739let isExtended = 1;
22740let mayStore = 1;
22741let BaseOpcode = "S2_storerbabs";
22742let CextOpcode = "S2_storerb";
22743let isNVStorable = 1;
22744let DecoderNamespace = "MustExtend";
22745let isExtendable = 1;
22746let opExtendable = 1;
22747let isExtentSigned = 0;
22748let opExtentBits = 6;
22749let opExtentAlign = 0;
22750}
22751def S4_pstorerbfnew_io : HInst<
22752(outs),
22753(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
22754"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32",
22755tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
22756let Inst{2-2} = 0b0;
22757let Inst{31-21} = 0b01000110000;
22758let isPredicated = 1;
22759let isPredicatedFalse = 1;
22760let addrMode = BaseImmOffset;
22761let accessSize = ByteAccess;
22762let isPredicatedNew = 1;
22763let mayStore = 1;
22764let BaseOpcode = "S2_storerb_io";
22765let CextOpcode = "S2_storerb";
22766let InputType = "imm";
22767let isNVStorable = 1;
22768let isExtendable = 1;
22769let opExtendable = 2;
22770let isExtentSigned = 0;
22771let opExtentBits = 6;
22772let opExtentAlign = 0;
22773}
22774def S4_pstorerbfnew_rr : HInst<
22775(outs),
22776(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
22777"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
22778tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
22779let Inst{31-21} = 0b00110111000;
22780let isPredicated = 1;
22781let isPredicatedFalse = 1;
22782let addrMode = BaseRegOffset;
22783let accessSize = ByteAccess;
22784let isPredicatedNew = 1;
22785let mayStore = 1;
22786let BaseOpcode = "S4_storerb_rr";
22787let CextOpcode = "S2_storerb";
22788let InputType = "reg";
22789let isNVStorable = 1;
22790}
22791def S4_pstorerbfnew_zomap : HInst<
22792(outs),
22793(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
22794"if (!$Pv4.new) memb($Rs32) = $Rt32",
22795tc_a2b365d2, TypeMAPPING> {
22796let isPseudo = 1;
22797let isCodeGenOnly = 1;
22798}
22799def S4_pstorerbnewf_abs : HInst<
22800(outs),
22801(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22802"if (!$Pv4) memb(#$Ii) = $Nt8.new",
22803tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22804let Inst{2-2} = 0b1;
22805let Inst{7-7} = 0b1;
22806let Inst{13-11} = 0b000;
22807let Inst{31-18} = 0b10101111101000;
22808let isPredicated = 1;
22809let isPredicatedFalse = 1;
22810let addrMode = Absolute;
22811let accessSize = ByteAccess;
22812let isNVStore = 1;
22813let isNewValue = 1;
22814let isExtended = 1;
22815let isRestrictNoSlot1Store = 1;
22816let mayStore = 1;
22817let BaseOpcode = "S2_storerbabs";
22818let CextOpcode = "S2_storerb";
22819let DecoderNamespace = "MustExtend";
22820let isExtendable = 1;
22821let opExtendable = 1;
22822let isExtentSigned = 0;
22823let opExtentBits = 6;
22824let opExtentAlign = 0;
22825let opNewValue = 2;
22826}
22827def S4_pstorerbnewf_rr : HInst<
22828(outs),
22829(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22830"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22831tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22832let Inst{4-3} = 0b00;
22833let Inst{31-21} = 0b00110101101;
22834let isPredicated = 1;
22835let isPredicatedFalse = 1;
22836let addrMode = BaseRegOffset;
22837let accessSize = ByteAccess;
22838let isNVStore = 1;
22839let isNewValue = 1;
22840let isRestrictNoSlot1Store = 1;
22841let mayStore = 1;
22842let BaseOpcode = "S4_storerb_rr";
22843let CextOpcode = "S2_storerb";
22844let InputType = "reg";
22845let opNewValue = 4;
22846}
22847def S4_pstorerbnewfnew_abs : HInst<
22848(outs),
22849(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22850"if (!$Pv4.new) memb(#$Ii) = $Nt8.new",
22851tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22852let Inst{2-2} = 0b1;
22853let Inst{7-7} = 0b1;
22854let Inst{13-11} = 0b100;
22855let Inst{31-18} = 0b10101111101000;
22856let isPredicated = 1;
22857let isPredicatedFalse = 1;
22858let addrMode = Absolute;
22859let accessSize = ByteAccess;
22860let isNVStore = 1;
22861let isPredicatedNew = 1;
22862let isNewValue = 1;
22863let isExtended = 1;
22864let isRestrictNoSlot1Store = 1;
22865let mayStore = 1;
22866let BaseOpcode = "S2_storerbabs";
22867let CextOpcode = "S2_storerb";
22868let DecoderNamespace = "MustExtend";
22869let isExtendable = 1;
22870let opExtendable = 1;
22871let isExtentSigned = 0;
22872let opExtentBits = 6;
22873let opExtentAlign = 0;
22874let opNewValue = 2;
22875}
22876def S4_pstorerbnewfnew_io : HInst<
22877(outs),
22878(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
22879"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
22880tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
22881let Inst{2-2} = 0b0;
22882let Inst{12-11} = 0b00;
22883let Inst{31-21} = 0b01000110101;
22884let isPredicated = 1;
22885let isPredicatedFalse = 1;
22886let addrMode = BaseImmOffset;
22887let accessSize = ByteAccess;
22888let isNVStore = 1;
22889let isPredicatedNew = 1;
22890let isNewValue = 1;
22891let isRestrictNoSlot1Store = 1;
22892let mayStore = 1;
22893let BaseOpcode = "S2_storerb_io";
22894let CextOpcode = "S2_storerb";
22895let InputType = "imm";
22896let isExtendable = 1;
22897let opExtendable = 2;
22898let isExtentSigned = 0;
22899let opExtentBits = 6;
22900let opExtentAlign = 0;
22901let opNewValue = 3;
22902}
22903def S4_pstorerbnewfnew_rr : HInst<
22904(outs),
22905(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22906"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22907tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
22908let Inst{4-3} = 0b00;
22909let Inst{31-21} = 0b00110111101;
22910let isPredicated = 1;
22911let isPredicatedFalse = 1;
22912let addrMode = BaseRegOffset;
22913let accessSize = ByteAccess;
22914let isNVStore = 1;
22915let isPredicatedNew = 1;
22916let isNewValue = 1;
22917let isRestrictNoSlot1Store = 1;
22918let mayStore = 1;
22919let BaseOpcode = "S4_storerb_rr";
22920let CextOpcode = "S2_storerb";
22921let InputType = "reg";
22922let opNewValue = 4;
22923}
22924def S4_pstorerbnewfnew_zomap : HInst<
22925(outs),
22926(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
22927"if (!$Pv4.new) memb($Rs32) = $Nt8.new",
22928tc_92240447, TypeMAPPING> {
22929let isPseudo = 1;
22930let isCodeGenOnly = 1;
22931let opNewValue = 2;
22932}
22933def S4_pstorerbnewt_abs : HInst<
22934(outs),
22935(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22936"if ($Pv4) memb(#$Ii) = $Nt8.new",
22937tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
22938let Inst{2-2} = 0b0;
22939let Inst{7-7} = 0b1;
22940let Inst{13-11} = 0b000;
22941let Inst{31-18} = 0b10101111101000;
22942let isPredicated = 1;
22943let addrMode = Absolute;
22944let accessSize = ByteAccess;
22945let isNVStore = 1;
22946let isNewValue = 1;
22947let isExtended = 1;
22948let isRestrictNoSlot1Store = 1;
22949let mayStore = 1;
22950let BaseOpcode = "S2_storerbabs";
22951let CextOpcode = "S2_storerb";
22952let DecoderNamespace = "MustExtend";
22953let isExtendable = 1;
22954let opExtendable = 1;
22955let isExtentSigned = 0;
22956let opExtentBits = 6;
22957let opExtentAlign = 0;
22958let opNewValue = 2;
22959}
22960def S4_pstorerbnewt_rr : HInst<
22961(outs),
22962(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
22963"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
22964tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
22965let Inst{4-3} = 0b00;
22966let Inst{31-21} = 0b00110100101;
22967let isPredicated = 1;
22968let addrMode = BaseRegOffset;
22969let accessSize = ByteAccess;
22970let isNVStore = 1;
22971let isNewValue = 1;
22972let isRestrictNoSlot1Store = 1;
22973let mayStore = 1;
22974let BaseOpcode = "S4_storerb_rr";
22975let CextOpcode = "S2_storerb";
22976let InputType = "reg";
22977let opNewValue = 4;
22978}
22979def S4_pstorerbnewtnew_abs : HInst<
22980(outs),
22981(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
22982"if ($Pv4.new) memb(#$Ii) = $Nt8.new",
22983tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
22984let Inst{2-2} = 0b0;
22985let Inst{7-7} = 0b1;
22986let Inst{13-11} = 0b100;
22987let Inst{31-18} = 0b10101111101000;
22988let isPredicated = 1;
22989let addrMode = Absolute;
22990let accessSize = ByteAccess;
22991let isNVStore = 1;
22992let isPredicatedNew = 1;
22993let isNewValue = 1;
22994let isExtended = 1;
22995let isRestrictNoSlot1Store = 1;
22996let mayStore = 1;
22997let BaseOpcode = "S2_storerbabs";
22998let CextOpcode = "S2_storerb";
22999let DecoderNamespace = "MustExtend";
23000let isExtendable = 1;
23001let opExtendable = 1;
23002let isExtentSigned = 0;
23003let opExtentBits = 6;
23004let opExtentAlign = 0;
23005let opNewValue = 2;
23006}
23007def S4_pstorerbnewtnew_io : HInst<
23008(outs),
23009(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8),
23010"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new",
23011tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel {
23012let Inst{2-2} = 0b0;
23013let Inst{12-11} = 0b00;
23014let Inst{31-21} = 0b01000010101;
23015let isPredicated = 1;
23016let addrMode = BaseImmOffset;
23017let accessSize = ByteAccess;
23018let isNVStore = 1;
23019let isPredicatedNew = 1;
23020let isNewValue = 1;
23021let isRestrictNoSlot1Store = 1;
23022let mayStore = 1;
23023let BaseOpcode = "S2_storerb_io";
23024let CextOpcode = "S2_storerb";
23025let InputType = "imm";
23026let isExtendable = 1;
23027let opExtendable = 2;
23028let isExtentSigned = 0;
23029let opExtentBits = 6;
23030let opExtentAlign = 0;
23031let opNewValue = 3;
23032}
23033def S4_pstorerbnewtnew_rr : HInst<
23034(outs),
23035(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23036"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23037tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23038let Inst{4-3} = 0b00;
23039let Inst{31-21} = 0b00110110101;
23040let isPredicated = 1;
23041let addrMode = BaseRegOffset;
23042let accessSize = ByteAccess;
23043let isNVStore = 1;
23044let isPredicatedNew = 1;
23045let isNewValue = 1;
23046let isRestrictNoSlot1Store = 1;
23047let mayStore = 1;
23048let BaseOpcode = "S4_storerb_rr";
23049let CextOpcode = "S2_storerb";
23050let InputType = "reg";
23051let opNewValue = 4;
23052}
23053def S4_pstorerbnewtnew_zomap : HInst<
23054(outs),
23055(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23056"if ($Pv4.new) memb($Rs32) = $Nt8.new",
23057tc_92240447, TypeMAPPING> {
23058let isPseudo = 1;
23059let isCodeGenOnly = 1;
23060let opNewValue = 2;
23061}
23062def S4_pstorerbt_abs : HInst<
23063(outs),
23064(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23065"if ($Pv4) memb(#$Ii) = $Rt32",
23066tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23067let Inst{2-2} = 0b0;
23068let Inst{7-7} = 0b1;
23069let Inst{13-13} = 0b0;
23070let Inst{31-18} = 0b10101111000000;
23071let isPredicated = 1;
23072let addrMode = Absolute;
23073let accessSize = ByteAccess;
23074let isExtended = 1;
23075let mayStore = 1;
23076let BaseOpcode = "S2_storerbabs";
23077let CextOpcode = "S2_storerb";
23078let isNVStorable = 1;
23079let DecoderNamespace = "MustExtend";
23080let isExtendable = 1;
23081let opExtendable = 1;
23082let isExtentSigned = 0;
23083let opExtentBits = 6;
23084let opExtentAlign = 0;
23085}
23086def S4_pstorerbt_rr : HInst<
23087(outs),
23088(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23089"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23090tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23091let Inst{31-21} = 0b00110100000;
23092let isPredicated = 1;
23093let addrMode = BaseRegOffset;
23094let accessSize = ByteAccess;
23095let mayStore = 1;
23096let BaseOpcode = "S4_storerb_rr";
23097let CextOpcode = "S2_storerb";
23098let InputType = "reg";
23099let isNVStorable = 1;
23100}
23101def S4_pstorerbtnew_abs : HInst<
23102(outs),
23103(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23104"if ($Pv4.new) memb(#$Ii) = $Rt32",
23105tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23106let Inst{2-2} = 0b0;
23107let Inst{7-7} = 0b1;
23108let Inst{13-13} = 0b1;
23109let Inst{31-18} = 0b10101111000000;
23110let isPredicated = 1;
23111let addrMode = Absolute;
23112let accessSize = ByteAccess;
23113let isPredicatedNew = 1;
23114let isExtended = 1;
23115let mayStore = 1;
23116let BaseOpcode = "S2_storerbabs";
23117let CextOpcode = "S2_storerb";
23118let isNVStorable = 1;
23119let DecoderNamespace = "MustExtend";
23120let isExtendable = 1;
23121let opExtendable = 1;
23122let isExtentSigned = 0;
23123let opExtentBits = 6;
23124let opExtentAlign = 0;
23125}
23126def S4_pstorerbtnew_io : HInst<
23127(outs),
23128(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32),
23129"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32",
23130tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel {
23131let Inst{2-2} = 0b0;
23132let Inst{31-21} = 0b01000010000;
23133let isPredicated = 1;
23134let addrMode = BaseImmOffset;
23135let accessSize = ByteAccess;
23136let isPredicatedNew = 1;
23137let mayStore = 1;
23138let BaseOpcode = "S2_storerb_io";
23139let CextOpcode = "S2_storerb";
23140let InputType = "imm";
23141let isNVStorable = 1;
23142let isExtendable = 1;
23143let opExtendable = 2;
23144let isExtentSigned = 0;
23145let opExtentBits = 6;
23146let opExtentAlign = 0;
23147}
23148def S4_pstorerbtnew_rr : HInst<
23149(outs),
23150(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23151"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32",
23152tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23153let Inst{31-21} = 0b00110110000;
23154let isPredicated = 1;
23155let addrMode = BaseRegOffset;
23156let accessSize = ByteAccess;
23157let isPredicatedNew = 1;
23158let mayStore = 1;
23159let BaseOpcode = "S4_storerb_rr";
23160let CextOpcode = "S2_storerb";
23161let InputType = "reg";
23162let isNVStorable = 1;
23163}
23164def S4_pstorerbtnew_zomap : HInst<
23165(outs),
23166(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23167"if ($Pv4.new) memb($Rs32) = $Rt32",
23168tc_a2b365d2, TypeMAPPING> {
23169let isPseudo = 1;
23170let isCodeGenOnly = 1;
23171}
23172def S4_pstorerdf_abs : HInst<
23173(outs),
23174(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23175"if (!$Pv4) memd(#$Ii) = $Rtt32",
23176tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23177let Inst{2-2} = 0b1;
23178let Inst{7-7} = 0b1;
23179let Inst{13-13} = 0b0;
23180let Inst{31-18} = 0b10101111110000;
23181let isPredicated = 1;
23182let isPredicatedFalse = 1;
23183let addrMode = Absolute;
23184let accessSize = DoubleWordAccess;
23185let isExtended = 1;
23186let mayStore = 1;
23187let BaseOpcode = "S2_storerdabs";
23188let CextOpcode = "S2_storerd";
23189let DecoderNamespace = "MustExtend";
23190let isExtendable = 1;
23191let opExtendable = 1;
23192let isExtentSigned = 0;
23193let opExtentBits = 6;
23194let opExtentAlign = 0;
23195}
23196def S4_pstorerdf_rr : HInst<
23197(outs),
23198(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23199"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23200tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23201let Inst{31-21} = 0b00110101110;
23202let isPredicated = 1;
23203let isPredicatedFalse = 1;
23204let addrMode = BaseRegOffset;
23205let accessSize = DoubleWordAccess;
23206let mayStore = 1;
23207let BaseOpcode = "S2_storerd_rr";
23208let CextOpcode = "S2_storerd";
23209let InputType = "reg";
23210}
23211def S4_pstorerdfnew_abs : HInst<
23212(outs),
23213(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23214"if (!$Pv4.new) memd(#$Ii) = $Rtt32",
23215tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23216let Inst{2-2} = 0b1;
23217let Inst{7-7} = 0b1;
23218let Inst{13-13} = 0b1;
23219let Inst{31-18} = 0b10101111110000;
23220let isPredicated = 1;
23221let isPredicatedFalse = 1;
23222let addrMode = Absolute;
23223let accessSize = DoubleWordAccess;
23224let isPredicatedNew = 1;
23225let isExtended = 1;
23226let mayStore = 1;
23227let BaseOpcode = "S2_storerdabs";
23228let CextOpcode = "S2_storerd";
23229let DecoderNamespace = "MustExtend";
23230let isExtendable = 1;
23231let opExtendable = 1;
23232let isExtentSigned = 0;
23233let opExtentBits = 6;
23234let opExtentAlign = 0;
23235}
23236def S4_pstorerdfnew_io : HInst<
23237(outs),
23238(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23239"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23240tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23241let Inst{2-2} = 0b0;
23242let Inst{31-21} = 0b01000110110;
23243let isPredicated = 1;
23244let isPredicatedFalse = 1;
23245let addrMode = BaseImmOffset;
23246let accessSize = DoubleWordAccess;
23247let isPredicatedNew = 1;
23248let mayStore = 1;
23249let BaseOpcode = "S2_storerd_io";
23250let CextOpcode = "S2_storerd";
23251let InputType = "imm";
23252let isExtendable = 1;
23253let opExtendable = 2;
23254let isExtentSigned = 0;
23255let opExtentBits = 9;
23256let opExtentAlign = 3;
23257}
23258def S4_pstorerdfnew_rr : HInst<
23259(outs),
23260(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23261"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23262tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23263let Inst{31-21} = 0b00110111110;
23264let isPredicated = 1;
23265let isPredicatedFalse = 1;
23266let addrMode = BaseRegOffset;
23267let accessSize = DoubleWordAccess;
23268let isPredicatedNew = 1;
23269let mayStore = 1;
23270let BaseOpcode = "S2_storerd_rr";
23271let CextOpcode = "S2_storerd";
23272let InputType = "reg";
23273}
23274def S4_pstorerdfnew_zomap : HInst<
23275(outs),
23276(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23277"if (!$Pv4.new) memd($Rs32) = $Rtt32",
23278tc_a2b365d2, TypeMAPPING> {
23279let isPseudo = 1;
23280let isCodeGenOnly = 1;
23281}
23282def S4_pstorerdt_abs : HInst<
23283(outs),
23284(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23285"if ($Pv4) memd(#$Ii) = $Rtt32",
23286tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel {
23287let Inst{2-2} = 0b0;
23288let Inst{7-7} = 0b1;
23289let Inst{13-13} = 0b0;
23290let Inst{31-18} = 0b10101111110000;
23291let isPredicated = 1;
23292let addrMode = Absolute;
23293let accessSize = DoubleWordAccess;
23294let isExtended = 1;
23295let mayStore = 1;
23296let BaseOpcode = "S2_storerdabs";
23297let CextOpcode = "S2_storerd";
23298let DecoderNamespace = "MustExtend";
23299let isExtendable = 1;
23300let opExtendable = 1;
23301let isExtentSigned = 0;
23302let opExtentBits = 6;
23303let opExtentAlign = 0;
23304}
23305def S4_pstorerdt_rr : HInst<
23306(outs),
23307(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23308"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23309tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel {
23310let Inst{31-21} = 0b00110100110;
23311let isPredicated = 1;
23312let addrMode = BaseRegOffset;
23313let accessSize = DoubleWordAccess;
23314let mayStore = 1;
23315let BaseOpcode = "S2_storerd_rr";
23316let CextOpcode = "S2_storerd";
23317let InputType = "reg";
23318}
23319def S4_pstorerdtnew_abs : HInst<
23320(outs),
23321(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32),
23322"if ($Pv4.new) memd(#$Ii) = $Rtt32",
23323tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel {
23324let Inst{2-2} = 0b0;
23325let Inst{7-7} = 0b1;
23326let Inst{13-13} = 0b1;
23327let Inst{31-18} = 0b10101111110000;
23328let isPredicated = 1;
23329let addrMode = Absolute;
23330let accessSize = DoubleWordAccess;
23331let isPredicatedNew = 1;
23332let isExtended = 1;
23333let mayStore = 1;
23334let BaseOpcode = "S2_storerdabs";
23335let CextOpcode = "S2_storerd";
23336let DecoderNamespace = "MustExtend";
23337let isExtendable = 1;
23338let opExtendable = 1;
23339let isExtentSigned = 0;
23340let opExtentBits = 6;
23341let opExtentAlign = 0;
23342}
23343def S4_pstorerdtnew_io : HInst<
23344(outs),
23345(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32),
23346"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32",
23347tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel {
23348let Inst{2-2} = 0b0;
23349let Inst{31-21} = 0b01000010110;
23350let isPredicated = 1;
23351let addrMode = BaseImmOffset;
23352let accessSize = DoubleWordAccess;
23353let isPredicatedNew = 1;
23354let mayStore = 1;
23355let BaseOpcode = "S2_storerd_io";
23356let CextOpcode = "S2_storerd";
23357let InputType = "imm";
23358let isExtendable = 1;
23359let opExtendable = 2;
23360let isExtentSigned = 0;
23361let opExtentBits = 9;
23362let opExtentAlign = 3;
23363}
23364def S4_pstorerdtnew_rr : HInst<
23365(outs),
23366(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
23367"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
23368tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel {
23369let Inst{31-21} = 0b00110110110;
23370let isPredicated = 1;
23371let addrMode = BaseRegOffset;
23372let accessSize = DoubleWordAccess;
23373let isPredicatedNew = 1;
23374let mayStore = 1;
23375let BaseOpcode = "S2_storerd_rr";
23376let CextOpcode = "S2_storerd";
23377let InputType = "reg";
23378}
23379def S4_pstorerdtnew_zomap : HInst<
23380(outs),
23381(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32),
23382"if ($Pv4.new) memd($Rs32) = $Rtt32",
23383tc_a2b365d2, TypeMAPPING> {
23384let isPseudo = 1;
23385let isCodeGenOnly = 1;
23386}
23387def S4_pstorerff_abs : HInst<
23388(outs),
23389(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23390"if (!$Pv4) memh(#$Ii) = $Rt32.h",
23391tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23392let Inst{2-2} = 0b1;
23393let Inst{7-7} = 0b1;
23394let Inst{13-13} = 0b0;
23395let Inst{31-18} = 0b10101111011000;
23396let isPredicated = 1;
23397let isPredicatedFalse = 1;
23398let addrMode = Absolute;
23399let accessSize = HalfWordAccess;
23400let isExtended = 1;
23401let mayStore = 1;
23402let BaseOpcode = "S2_storerfabs";
23403let CextOpcode = "S2_storerf";
23404let DecoderNamespace = "MustExtend";
23405let isExtendable = 1;
23406let opExtendable = 1;
23407let isExtentSigned = 0;
23408let opExtentBits = 6;
23409let opExtentAlign = 0;
23410}
23411def S4_pstorerff_rr : HInst<
23412(outs),
23413(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23414"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23415tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23416let Inst{31-21} = 0b00110101011;
23417let isPredicated = 1;
23418let isPredicatedFalse = 1;
23419let addrMode = BaseRegOffset;
23420let accessSize = HalfWordAccess;
23421let mayStore = 1;
23422let BaseOpcode = "S4_storerf_rr";
23423let CextOpcode = "S2_storerf";
23424let InputType = "reg";
23425}
23426def S4_pstorerffnew_abs : HInst<
23427(outs),
23428(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23429"if (!$Pv4.new) memh(#$Ii) = $Rt32.h",
23430tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23431let Inst{2-2} = 0b1;
23432let Inst{7-7} = 0b1;
23433let Inst{13-13} = 0b1;
23434let Inst{31-18} = 0b10101111011000;
23435let isPredicated = 1;
23436let isPredicatedFalse = 1;
23437let addrMode = Absolute;
23438let accessSize = HalfWordAccess;
23439let isPredicatedNew = 1;
23440let isExtended = 1;
23441let mayStore = 1;
23442let BaseOpcode = "S2_storerfabs";
23443let CextOpcode = "S2_storerf";
23444let DecoderNamespace = "MustExtend";
23445let isExtendable = 1;
23446let opExtendable = 1;
23447let isExtentSigned = 0;
23448let opExtentBits = 6;
23449let opExtentAlign = 0;
23450}
23451def S4_pstorerffnew_io : HInst<
23452(outs),
23453(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23454"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23455tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23456let Inst{2-2} = 0b0;
23457let Inst{31-21} = 0b01000110011;
23458let isPredicated = 1;
23459let isPredicatedFalse = 1;
23460let addrMode = BaseImmOffset;
23461let accessSize = HalfWordAccess;
23462let isPredicatedNew = 1;
23463let mayStore = 1;
23464let BaseOpcode = "S2_storerf_io";
23465let CextOpcode = "S2_storerf";
23466let InputType = "imm";
23467let isExtendable = 1;
23468let opExtendable = 2;
23469let isExtentSigned = 0;
23470let opExtentBits = 7;
23471let opExtentAlign = 1;
23472}
23473def S4_pstorerffnew_rr : HInst<
23474(outs),
23475(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23476"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23477tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23478let Inst{31-21} = 0b00110111011;
23479let isPredicated = 1;
23480let isPredicatedFalse = 1;
23481let addrMode = BaseRegOffset;
23482let accessSize = HalfWordAccess;
23483let isPredicatedNew = 1;
23484let mayStore = 1;
23485let BaseOpcode = "S4_storerf_rr";
23486let CextOpcode = "S2_storerf";
23487let InputType = "reg";
23488}
23489def S4_pstorerffnew_zomap : HInst<
23490(outs),
23491(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23492"if (!$Pv4.new) memh($Rs32) = $Rt32.h",
23493tc_a2b365d2, TypeMAPPING> {
23494let isPseudo = 1;
23495let isCodeGenOnly = 1;
23496}
23497def S4_pstorerft_abs : HInst<
23498(outs),
23499(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23500"if ($Pv4) memh(#$Ii) = $Rt32.h",
23501tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23502let Inst{2-2} = 0b0;
23503let Inst{7-7} = 0b1;
23504let Inst{13-13} = 0b0;
23505let Inst{31-18} = 0b10101111011000;
23506let isPredicated = 1;
23507let addrMode = Absolute;
23508let accessSize = HalfWordAccess;
23509let isExtended = 1;
23510let mayStore = 1;
23511let BaseOpcode = "S2_storerfabs";
23512let CextOpcode = "S2_storerf";
23513let DecoderNamespace = "MustExtend";
23514let isExtendable = 1;
23515let opExtendable = 1;
23516let isExtentSigned = 0;
23517let opExtentBits = 6;
23518let opExtentAlign = 0;
23519}
23520def S4_pstorerft_rr : HInst<
23521(outs),
23522(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23523"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23524tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23525let Inst{31-21} = 0b00110100011;
23526let isPredicated = 1;
23527let addrMode = BaseRegOffset;
23528let accessSize = HalfWordAccess;
23529let mayStore = 1;
23530let BaseOpcode = "S4_storerf_rr";
23531let CextOpcode = "S2_storerf";
23532let InputType = "reg";
23533}
23534def S4_pstorerftnew_abs : HInst<
23535(outs),
23536(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23537"if ($Pv4.new) memh(#$Ii) = $Rt32.h",
23538tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23539let Inst{2-2} = 0b0;
23540let Inst{7-7} = 0b1;
23541let Inst{13-13} = 0b1;
23542let Inst{31-18} = 0b10101111011000;
23543let isPredicated = 1;
23544let addrMode = Absolute;
23545let accessSize = HalfWordAccess;
23546let isPredicatedNew = 1;
23547let isExtended = 1;
23548let mayStore = 1;
23549let BaseOpcode = "S2_storerfabs";
23550let CextOpcode = "S2_storerf";
23551let DecoderNamespace = "MustExtend";
23552let isExtendable = 1;
23553let opExtendable = 1;
23554let isExtentSigned = 0;
23555let opExtentBits = 6;
23556let opExtentAlign = 0;
23557}
23558def S4_pstorerftnew_io : HInst<
23559(outs),
23560(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23561"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h",
23562tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23563let Inst{2-2} = 0b0;
23564let Inst{31-21} = 0b01000010011;
23565let isPredicated = 1;
23566let addrMode = BaseImmOffset;
23567let accessSize = HalfWordAccess;
23568let isPredicatedNew = 1;
23569let mayStore = 1;
23570let BaseOpcode = "S2_storerf_io";
23571let CextOpcode = "S2_storerf";
23572let InputType = "imm";
23573let isExtendable = 1;
23574let opExtendable = 2;
23575let isExtentSigned = 0;
23576let opExtentBits = 7;
23577let opExtentAlign = 1;
23578}
23579def S4_pstorerftnew_rr : HInst<
23580(outs),
23581(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23582"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
23583tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23584let Inst{31-21} = 0b00110110011;
23585let isPredicated = 1;
23586let addrMode = BaseRegOffset;
23587let accessSize = HalfWordAccess;
23588let isPredicatedNew = 1;
23589let mayStore = 1;
23590let BaseOpcode = "S4_storerf_rr";
23591let CextOpcode = "S2_storerf";
23592let InputType = "reg";
23593}
23594def S4_pstorerftnew_zomap : HInst<
23595(outs),
23596(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23597"if ($Pv4.new) memh($Rs32) = $Rt32.h",
23598tc_a2b365d2, TypeMAPPING> {
23599let isPseudo = 1;
23600let isCodeGenOnly = 1;
23601}
23602def S4_pstorerhf_abs : HInst<
23603(outs),
23604(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23605"if (!$Pv4) memh(#$Ii) = $Rt32",
23606tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23607let Inst{2-2} = 0b1;
23608let Inst{7-7} = 0b1;
23609let Inst{13-13} = 0b0;
23610let Inst{31-18} = 0b10101111010000;
23611let isPredicated = 1;
23612let isPredicatedFalse = 1;
23613let addrMode = Absolute;
23614let accessSize = HalfWordAccess;
23615let isExtended = 1;
23616let mayStore = 1;
23617let BaseOpcode = "S2_storerhabs";
23618let CextOpcode = "S2_storerh";
23619let isNVStorable = 1;
23620let DecoderNamespace = "MustExtend";
23621let isExtendable = 1;
23622let opExtendable = 1;
23623let isExtentSigned = 0;
23624let opExtentBits = 6;
23625let opExtentAlign = 0;
23626}
23627def S4_pstorerhf_rr : HInst<
23628(outs),
23629(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23630"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23631tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
23632let Inst{31-21} = 0b00110101010;
23633let isPredicated = 1;
23634let isPredicatedFalse = 1;
23635let addrMode = BaseRegOffset;
23636let accessSize = HalfWordAccess;
23637let mayStore = 1;
23638let BaseOpcode = "S2_storerh_rr";
23639let CextOpcode = "S2_storerh";
23640let InputType = "reg";
23641let isNVStorable = 1;
23642}
23643def S4_pstorerhfnew_abs : HInst<
23644(outs),
23645(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23646"if (!$Pv4.new) memh(#$Ii) = $Rt32",
23647tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
23648let Inst{2-2} = 0b1;
23649let Inst{7-7} = 0b1;
23650let Inst{13-13} = 0b1;
23651let Inst{31-18} = 0b10101111010000;
23652let isPredicated = 1;
23653let isPredicatedFalse = 1;
23654let addrMode = Absolute;
23655let accessSize = HalfWordAccess;
23656let isPredicatedNew = 1;
23657let isExtended = 1;
23658let mayStore = 1;
23659let BaseOpcode = "S2_storerhabs";
23660let CextOpcode = "S2_storerh";
23661let isNVStorable = 1;
23662let DecoderNamespace = "MustExtend";
23663let isExtendable = 1;
23664let opExtendable = 1;
23665let isExtentSigned = 0;
23666let opExtentBits = 6;
23667let opExtentAlign = 0;
23668}
23669def S4_pstorerhfnew_io : HInst<
23670(outs),
23671(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
23672"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32",
23673tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
23674let Inst{2-2} = 0b0;
23675let Inst{31-21} = 0b01000110010;
23676let isPredicated = 1;
23677let isPredicatedFalse = 1;
23678let addrMode = BaseImmOffset;
23679let accessSize = HalfWordAccess;
23680let isPredicatedNew = 1;
23681let mayStore = 1;
23682let BaseOpcode = "S2_storerh_io";
23683let CextOpcode = "S2_storerh";
23684let InputType = "imm";
23685let isNVStorable = 1;
23686let isExtendable = 1;
23687let opExtendable = 2;
23688let isExtentSigned = 0;
23689let opExtentBits = 7;
23690let opExtentAlign = 1;
23691}
23692def S4_pstorerhfnew_rr : HInst<
23693(outs),
23694(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
23695"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
23696tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
23697let Inst{31-21} = 0b00110111010;
23698let isPredicated = 1;
23699let isPredicatedFalse = 1;
23700let addrMode = BaseRegOffset;
23701let accessSize = HalfWordAccess;
23702let isPredicatedNew = 1;
23703let mayStore = 1;
23704let BaseOpcode = "S2_storerh_rr";
23705let CextOpcode = "S2_storerh";
23706let InputType = "reg";
23707let isNVStorable = 1;
23708}
23709def S4_pstorerhfnew_zomap : HInst<
23710(outs),
23711(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
23712"if (!$Pv4.new) memh($Rs32) = $Rt32",
23713tc_a2b365d2, TypeMAPPING> {
23714let isPseudo = 1;
23715let isCodeGenOnly = 1;
23716}
23717def S4_pstorerhnewf_abs : HInst<
23718(outs),
23719(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23720"if (!$Pv4) memh(#$Ii) = $Nt8.new",
23721tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23722let Inst{2-2} = 0b1;
23723let Inst{7-7} = 0b1;
23724let Inst{13-11} = 0b001;
23725let Inst{31-18} = 0b10101111101000;
23726let isPredicated = 1;
23727let isPredicatedFalse = 1;
23728let addrMode = Absolute;
23729let accessSize = HalfWordAccess;
23730let isNVStore = 1;
23731let isNewValue = 1;
23732let isExtended = 1;
23733let isRestrictNoSlot1Store = 1;
23734let mayStore = 1;
23735let BaseOpcode = "S2_storerhabs";
23736let CextOpcode = "S2_storerh";
23737let DecoderNamespace = "MustExtend";
23738let isExtendable = 1;
23739let opExtendable = 1;
23740let isExtentSigned = 0;
23741let opExtentBits = 6;
23742let opExtentAlign = 0;
23743let opNewValue = 2;
23744}
23745def S4_pstorerhnewf_rr : HInst<
23746(outs),
23747(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23748"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23749tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23750let Inst{4-3} = 0b01;
23751let Inst{31-21} = 0b00110101101;
23752let isPredicated = 1;
23753let isPredicatedFalse = 1;
23754let addrMode = BaseRegOffset;
23755let accessSize = HalfWordAccess;
23756let isNVStore = 1;
23757let isNewValue = 1;
23758let isRestrictNoSlot1Store = 1;
23759let mayStore = 1;
23760let BaseOpcode = "S2_storerh_rr";
23761let CextOpcode = "S2_storerh";
23762let InputType = "reg";
23763let opNewValue = 4;
23764}
23765def S4_pstorerhnewfnew_abs : HInst<
23766(outs),
23767(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23768"if (!$Pv4.new) memh(#$Ii) = $Nt8.new",
23769tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23770let Inst{2-2} = 0b1;
23771let Inst{7-7} = 0b1;
23772let Inst{13-11} = 0b101;
23773let Inst{31-18} = 0b10101111101000;
23774let isPredicated = 1;
23775let isPredicatedFalse = 1;
23776let addrMode = Absolute;
23777let accessSize = HalfWordAccess;
23778let isNVStore = 1;
23779let isPredicatedNew = 1;
23780let isNewValue = 1;
23781let isExtended = 1;
23782let isRestrictNoSlot1Store = 1;
23783let mayStore = 1;
23784let BaseOpcode = "S2_storerhabs";
23785let CextOpcode = "S2_storerh";
23786let DecoderNamespace = "MustExtend";
23787let isExtendable = 1;
23788let opExtendable = 1;
23789let isExtentSigned = 0;
23790let opExtentBits = 6;
23791let opExtentAlign = 0;
23792let opNewValue = 2;
23793}
23794def S4_pstorerhnewfnew_io : HInst<
23795(outs),
23796(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23797"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23798tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23799let Inst{2-2} = 0b0;
23800let Inst{12-11} = 0b01;
23801let Inst{31-21} = 0b01000110101;
23802let isPredicated = 1;
23803let isPredicatedFalse = 1;
23804let addrMode = BaseImmOffset;
23805let accessSize = HalfWordAccess;
23806let isNVStore = 1;
23807let isPredicatedNew = 1;
23808let isNewValue = 1;
23809let isRestrictNoSlot1Store = 1;
23810let mayStore = 1;
23811let BaseOpcode = "S2_storerh_io";
23812let CextOpcode = "S2_storerh";
23813let InputType = "imm";
23814let isExtendable = 1;
23815let opExtendable = 2;
23816let isExtentSigned = 0;
23817let opExtentBits = 7;
23818let opExtentAlign = 1;
23819let opNewValue = 3;
23820}
23821def S4_pstorerhnewfnew_rr : HInst<
23822(outs),
23823(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23824"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23825tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23826let Inst{4-3} = 0b01;
23827let Inst{31-21} = 0b00110111101;
23828let isPredicated = 1;
23829let isPredicatedFalse = 1;
23830let addrMode = BaseRegOffset;
23831let accessSize = HalfWordAccess;
23832let isNVStore = 1;
23833let isPredicatedNew = 1;
23834let isNewValue = 1;
23835let isRestrictNoSlot1Store = 1;
23836let mayStore = 1;
23837let BaseOpcode = "S2_storerh_rr";
23838let CextOpcode = "S2_storerh";
23839let InputType = "reg";
23840let opNewValue = 4;
23841}
23842def S4_pstorerhnewfnew_zomap : HInst<
23843(outs),
23844(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23845"if (!$Pv4.new) memh($Rs32) = $Nt8.new",
23846tc_92240447, TypeMAPPING> {
23847let isPseudo = 1;
23848let isCodeGenOnly = 1;
23849let opNewValue = 2;
23850}
23851def S4_pstorerhnewt_abs : HInst<
23852(outs),
23853(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23854"if ($Pv4) memh(#$Ii) = $Nt8.new",
23855tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
23856let Inst{2-2} = 0b0;
23857let Inst{7-7} = 0b1;
23858let Inst{13-11} = 0b001;
23859let Inst{31-18} = 0b10101111101000;
23860let isPredicated = 1;
23861let addrMode = Absolute;
23862let accessSize = HalfWordAccess;
23863let isNVStore = 1;
23864let isNewValue = 1;
23865let isExtended = 1;
23866let isRestrictNoSlot1Store = 1;
23867let mayStore = 1;
23868let BaseOpcode = "S2_storerhabs";
23869let CextOpcode = "S2_storerh";
23870let DecoderNamespace = "MustExtend";
23871let isExtendable = 1;
23872let opExtendable = 1;
23873let isExtentSigned = 0;
23874let opExtentBits = 6;
23875let opExtentAlign = 0;
23876let opNewValue = 2;
23877}
23878def S4_pstorerhnewt_rr : HInst<
23879(outs),
23880(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23881"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23882tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
23883let Inst{4-3} = 0b01;
23884let Inst{31-21} = 0b00110100101;
23885let isPredicated = 1;
23886let addrMode = BaseRegOffset;
23887let accessSize = HalfWordAccess;
23888let isNVStore = 1;
23889let isNewValue = 1;
23890let isRestrictNoSlot1Store = 1;
23891let mayStore = 1;
23892let BaseOpcode = "S2_storerh_rr";
23893let CextOpcode = "S2_storerh";
23894let InputType = "reg";
23895let opNewValue = 4;
23896}
23897def S4_pstorerhnewtnew_abs : HInst<
23898(outs),
23899(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
23900"if ($Pv4.new) memh(#$Ii) = $Nt8.new",
23901tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
23902let Inst{2-2} = 0b0;
23903let Inst{7-7} = 0b1;
23904let Inst{13-11} = 0b101;
23905let Inst{31-18} = 0b10101111101000;
23906let isPredicated = 1;
23907let addrMode = Absolute;
23908let accessSize = HalfWordAccess;
23909let isNVStore = 1;
23910let isPredicatedNew = 1;
23911let isNewValue = 1;
23912let isExtended = 1;
23913let isRestrictNoSlot1Store = 1;
23914let mayStore = 1;
23915let BaseOpcode = "S2_storerhabs";
23916let CextOpcode = "S2_storerh";
23917let DecoderNamespace = "MustExtend";
23918let isExtendable = 1;
23919let opExtendable = 1;
23920let isExtentSigned = 0;
23921let opExtentBits = 6;
23922let opExtentAlign = 0;
23923let opNewValue = 2;
23924}
23925def S4_pstorerhnewtnew_io : HInst<
23926(outs),
23927(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8),
23928"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new",
23929tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel {
23930let Inst{2-2} = 0b0;
23931let Inst{12-11} = 0b01;
23932let Inst{31-21} = 0b01000010101;
23933let isPredicated = 1;
23934let addrMode = BaseImmOffset;
23935let accessSize = HalfWordAccess;
23936let isNVStore = 1;
23937let isPredicatedNew = 1;
23938let isNewValue = 1;
23939let isRestrictNoSlot1Store = 1;
23940let mayStore = 1;
23941let BaseOpcode = "S2_storerh_io";
23942let CextOpcode = "S2_storerh";
23943let InputType = "imm";
23944let isExtendable = 1;
23945let opExtendable = 2;
23946let isExtentSigned = 0;
23947let opExtentBits = 7;
23948let opExtentAlign = 1;
23949let opNewValue = 3;
23950}
23951def S4_pstorerhnewtnew_rr : HInst<
23952(outs),
23953(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
23954"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
23955tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
23956let Inst{4-3} = 0b01;
23957let Inst{31-21} = 0b00110110101;
23958let isPredicated = 1;
23959let addrMode = BaseRegOffset;
23960let accessSize = HalfWordAccess;
23961let isNVStore = 1;
23962let isPredicatedNew = 1;
23963let isNewValue = 1;
23964let isRestrictNoSlot1Store = 1;
23965let mayStore = 1;
23966let BaseOpcode = "S2_storerh_rr";
23967let CextOpcode = "S2_storerh";
23968let InputType = "reg";
23969let opNewValue = 4;
23970}
23971def S4_pstorerhnewtnew_zomap : HInst<
23972(outs),
23973(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
23974"if ($Pv4.new) memh($Rs32) = $Nt8.new",
23975tc_92240447, TypeMAPPING> {
23976let isPseudo = 1;
23977let isCodeGenOnly = 1;
23978let opNewValue = 2;
23979}
23980def S4_pstorerht_abs : HInst<
23981(outs),
23982(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
23983"if ($Pv4) memh(#$Ii) = $Rt32",
23984tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
23985let Inst{2-2} = 0b0;
23986let Inst{7-7} = 0b1;
23987let Inst{13-13} = 0b0;
23988let Inst{31-18} = 0b10101111010000;
23989let isPredicated = 1;
23990let addrMode = Absolute;
23991let accessSize = HalfWordAccess;
23992let isExtended = 1;
23993let mayStore = 1;
23994let BaseOpcode = "S2_storerhabs";
23995let CextOpcode = "S2_storerh";
23996let isNVStorable = 1;
23997let DecoderNamespace = "MustExtend";
23998let isExtendable = 1;
23999let opExtendable = 1;
24000let isExtentSigned = 0;
24001let opExtentBits = 6;
24002let opExtentAlign = 0;
24003}
24004def S4_pstorerht_rr : HInst<
24005(outs),
24006(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24007"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24008tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24009let Inst{31-21} = 0b00110100010;
24010let isPredicated = 1;
24011let addrMode = BaseRegOffset;
24012let accessSize = HalfWordAccess;
24013let mayStore = 1;
24014let BaseOpcode = "S2_storerh_rr";
24015let CextOpcode = "S2_storerh";
24016let InputType = "reg";
24017let isNVStorable = 1;
24018}
24019def S4_pstorerhtnew_abs : HInst<
24020(outs),
24021(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24022"if ($Pv4.new) memh(#$Ii) = $Rt32",
24023tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24024let Inst{2-2} = 0b0;
24025let Inst{7-7} = 0b1;
24026let Inst{13-13} = 0b1;
24027let Inst{31-18} = 0b10101111010000;
24028let isPredicated = 1;
24029let addrMode = Absolute;
24030let accessSize = HalfWordAccess;
24031let isPredicatedNew = 1;
24032let isExtended = 1;
24033let mayStore = 1;
24034let BaseOpcode = "S2_storerhabs";
24035let CextOpcode = "S2_storerh";
24036let isNVStorable = 1;
24037let DecoderNamespace = "MustExtend";
24038let isExtendable = 1;
24039let opExtendable = 1;
24040let isExtentSigned = 0;
24041let opExtentBits = 6;
24042let opExtentAlign = 0;
24043}
24044def S4_pstorerhtnew_io : HInst<
24045(outs),
24046(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32),
24047"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32",
24048tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel {
24049let Inst{2-2} = 0b0;
24050let Inst{31-21} = 0b01000010010;
24051let isPredicated = 1;
24052let addrMode = BaseImmOffset;
24053let accessSize = HalfWordAccess;
24054let isPredicatedNew = 1;
24055let mayStore = 1;
24056let BaseOpcode = "S2_storerh_io";
24057let CextOpcode = "S2_storerh";
24058let InputType = "imm";
24059let isNVStorable = 1;
24060let isExtendable = 1;
24061let opExtendable = 2;
24062let isExtentSigned = 0;
24063let opExtentBits = 7;
24064let opExtentAlign = 1;
24065}
24066def S4_pstorerhtnew_rr : HInst<
24067(outs),
24068(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24069"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32",
24070tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24071let Inst{31-21} = 0b00110110010;
24072let isPredicated = 1;
24073let addrMode = BaseRegOffset;
24074let accessSize = HalfWordAccess;
24075let isPredicatedNew = 1;
24076let mayStore = 1;
24077let BaseOpcode = "S2_storerh_rr";
24078let CextOpcode = "S2_storerh";
24079let InputType = "reg";
24080let isNVStorable = 1;
24081}
24082def S4_pstorerhtnew_zomap : HInst<
24083(outs),
24084(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24085"if ($Pv4.new) memh($Rs32) = $Rt32",
24086tc_a2b365d2, TypeMAPPING> {
24087let isPseudo = 1;
24088let isCodeGenOnly = 1;
24089}
24090def S4_pstorerif_abs : HInst<
24091(outs),
24092(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24093"if (!$Pv4) memw(#$Ii) = $Rt32",
24094tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24095let Inst{2-2} = 0b1;
24096let Inst{7-7} = 0b1;
24097let Inst{13-13} = 0b0;
24098let Inst{31-18} = 0b10101111100000;
24099let isPredicated = 1;
24100let isPredicatedFalse = 1;
24101let addrMode = Absolute;
24102let accessSize = WordAccess;
24103let isExtended = 1;
24104let mayStore = 1;
24105let BaseOpcode = "S2_storeriabs";
24106let CextOpcode = "S2_storeri";
24107let isNVStorable = 1;
24108let DecoderNamespace = "MustExtend";
24109let isExtendable = 1;
24110let opExtendable = 1;
24111let isExtentSigned = 0;
24112let opExtentBits = 6;
24113let opExtentAlign = 0;
24114}
24115def S4_pstorerif_rr : HInst<
24116(outs),
24117(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24118"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24119tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24120let Inst{31-21} = 0b00110101100;
24121let isPredicated = 1;
24122let isPredicatedFalse = 1;
24123let addrMode = BaseRegOffset;
24124let accessSize = WordAccess;
24125let mayStore = 1;
24126let BaseOpcode = "S2_storeri_rr";
24127let CextOpcode = "S2_storeri";
24128let InputType = "reg";
24129let isNVStorable = 1;
24130}
24131def S4_pstorerifnew_abs : HInst<
24132(outs),
24133(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24134"if (!$Pv4.new) memw(#$Ii) = $Rt32",
24135tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24136let Inst{2-2} = 0b1;
24137let Inst{7-7} = 0b1;
24138let Inst{13-13} = 0b1;
24139let Inst{31-18} = 0b10101111100000;
24140let isPredicated = 1;
24141let isPredicatedFalse = 1;
24142let addrMode = Absolute;
24143let accessSize = WordAccess;
24144let isPredicatedNew = 1;
24145let isExtended = 1;
24146let mayStore = 1;
24147let BaseOpcode = "S2_storeriabs";
24148let CextOpcode = "S2_storeri";
24149let isNVStorable = 1;
24150let DecoderNamespace = "MustExtend";
24151let isExtendable = 1;
24152let opExtendable = 1;
24153let isExtentSigned = 0;
24154let opExtentBits = 6;
24155let opExtentAlign = 0;
24156}
24157def S4_pstorerifnew_io : HInst<
24158(outs),
24159(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24160"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24161tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24162let Inst{2-2} = 0b0;
24163let Inst{31-21} = 0b01000110100;
24164let isPredicated = 1;
24165let isPredicatedFalse = 1;
24166let addrMode = BaseImmOffset;
24167let accessSize = WordAccess;
24168let isPredicatedNew = 1;
24169let mayStore = 1;
24170let BaseOpcode = "S2_storeri_io";
24171let CextOpcode = "S2_storeri";
24172let InputType = "imm";
24173let isNVStorable = 1;
24174let isExtendable = 1;
24175let opExtendable = 2;
24176let isExtentSigned = 0;
24177let opExtentBits = 8;
24178let opExtentAlign = 2;
24179}
24180def S4_pstorerifnew_rr : HInst<
24181(outs),
24182(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24183"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24184tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24185let Inst{31-21} = 0b00110111100;
24186let isPredicated = 1;
24187let isPredicatedFalse = 1;
24188let addrMode = BaseRegOffset;
24189let accessSize = WordAccess;
24190let isPredicatedNew = 1;
24191let mayStore = 1;
24192let BaseOpcode = "S2_storeri_rr";
24193let CextOpcode = "S2_storeri";
24194let InputType = "reg";
24195let isNVStorable = 1;
24196}
24197def S4_pstorerifnew_zomap : HInst<
24198(outs),
24199(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24200"if (!$Pv4.new) memw($Rs32) = $Rt32",
24201tc_a2b365d2, TypeMAPPING> {
24202let isPseudo = 1;
24203let isCodeGenOnly = 1;
24204}
24205def S4_pstorerinewf_abs : HInst<
24206(outs),
24207(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24208"if (!$Pv4) memw(#$Ii) = $Nt8.new",
24209tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24210let Inst{2-2} = 0b1;
24211let Inst{7-7} = 0b1;
24212let Inst{13-11} = 0b010;
24213let Inst{31-18} = 0b10101111101000;
24214let isPredicated = 1;
24215let isPredicatedFalse = 1;
24216let addrMode = Absolute;
24217let accessSize = WordAccess;
24218let isNVStore = 1;
24219let isNewValue = 1;
24220let isExtended = 1;
24221let isRestrictNoSlot1Store = 1;
24222let mayStore = 1;
24223let BaseOpcode = "S2_storeriabs";
24224let CextOpcode = "S2_storeri";
24225let DecoderNamespace = "MustExtend";
24226let isExtendable = 1;
24227let opExtendable = 1;
24228let isExtentSigned = 0;
24229let opExtentBits = 6;
24230let opExtentAlign = 0;
24231let opNewValue = 2;
24232}
24233def S4_pstorerinewf_rr : HInst<
24234(outs),
24235(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24236"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24237tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24238let Inst{4-3} = 0b10;
24239let Inst{31-21} = 0b00110101101;
24240let isPredicated = 1;
24241let isPredicatedFalse = 1;
24242let addrMode = BaseRegOffset;
24243let accessSize = WordAccess;
24244let isNVStore = 1;
24245let isNewValue = 1;
24246let isRestrictNoSlot1Store = 1;
24247let mayStore = 1;
24248let BaseOpcode = "S2_storeri_rr";
24249let CextOpcode = "S2_storeri";
24250let InputType = "reg";
24251let opNewValue = 4;
24252}
24253def S4_pstorerinewfnew_abs : HInst<
24254(outs),
24255(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24256"if (!$Pv4.new) memw(#$Ii) = $Nt8.new",
24257tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24258let Inst{2-2} = 0b1;
24259let Inst{7-7} = 0b1;
24260let Inst{13-11} = 0b110;
24261let Inst{31-18} = 0b10101111101000;
24262let isPredicated = 1;
24263let isPredicatedFalse = 1;
24264let addrMode = Absolute;
24265let accessSize = WordAccess;
24266let isNVStore = 1;
24267let isPredicatedNew = 1;
24268let isNewValue = 1;
24269let isExtended = 1;
24270let isRestrictNoSlot1Store = 1;
24271let mayStore = 1;
24272let BaseOpcode = "S2_storeriabs";
24273let CextOpcode = "S2_storeri";
24274let DecoderNamespace = "MustExtend";
24275let isExtendable = 1;
24276let opExtendable = 1;
24277let isExtentSigned = 0;
24278let opExtentBits = 6;
24279let opExtentAlign = 0;
24280let opNewValue = 2;
24281}
24282def S4_pstorerinewfnew_io : HInst<
24283(outs),
24284(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24285"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24286tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24287let Inst{2-2} = 0b0;
24288let Inst{12-11} = 0b10;
24289let Inst{31-21} = 0b01000110101;
24290let isPredicated = 1;
24291let isPredicatedFalse = 1;
24292let addrMode = BaseImmOffset;
24293let accessSize = WordAccess;
24294let isNVStore = 1;
24295let isPredicatedNew = 1;
24296let isNewValue = 1;
24297let isRestrictNoSlot1Store = 1;
24298let mayStore = 1;
24299let BaseOpcode = "S2_storeri_io";
24300let CextOpcode = "S2_storeri";
24301let InputType = "imm";
24302let isExtendable = 1;
24303let opExtendable = 2;
24304let isExtentSigned = 0;
24305let opExtentBits = 8;
24306let opExtentAlign = 2;
24307let opNewValue = 3;
24308}
24309def S4_pstorerinewfnew_rr : HInst<
24310(outs),
24311(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24312"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24313tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24314let Inst{4-3} = 0b10;
24315let Inst{31-21} = 0b00110111101;
24316let isPredicated = 1;
24317let isPredicatedFalse = 1;
24318let addrMode = BaseRegOffset;
24319let accessSize = WordAccess;
24320let isNVStore = 1;
24321let isPredicatedNew = 1;
24322let isNewValue = 1;
24323let isRestrictNoSlot1Store = 1;
24324let mayStore = 1;
24325let BaseOpcode = "S2_storeri_rr";
24326let CextOpcode = "S2_storeri";
24327let InputType = "reg";
24328let opNewValue = 4;
24329}
24330def S4_pstorerinewfnew_zomap : HInst<
24331(outs),
24332(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24333"if (!$Pv4.new) memw($Rs32) = $Nt8.new",
24334tc_92240447, TypeMAPPING> {
24335let isPseudo = 1;
24336let isCodeGenOnly = 1;
24337let opNewValue = 2;
24338}
24339def S4_pstorerinewt_abs : HInst<
24340(outs),
24341(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24342"if ($Pv4) memw(#$Ii) = $Nt8.new",
24343tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel {
24344let Inst{2-2} = 0b0;
24345let Inst{7-7} = 0b1;
24346let Inst{13-11} = 0b010;
24347let Inst{31-18} = 0b10101111101000;
24348let isPredicated = 1;
24349let addrMode = Absolute;
24350let accessSize = WordAccess;
24351let isNVStore = 1;
24352let isNewValue = 1;
24353let isExtended = 1;
24354let isRestrictNoSlot1Store = 1;
24355let mayStore = 1;
24356let BaseOpcode = "S2_storeriabs";
24357let CextOpcode = "S2_storeri";
24358let DecoderNamespace = "MustExtend";
24359let isExtendable = 1;
24360let opExtendable = 1;
24361let isExtentSigned = 0;
24362let opExtentBits = 6;
24363let opExtentAlign = 0;
24364let opNewValue = 2;
24365}
24366def S4_pstorerinewt_rr : HInst<
24367(outs),
24368(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24369"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24370tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel {
24371let Inst{4-3} = 0b10;
24372let Inst{31-21} = 0b00110100101;
24373let isPredicated = 1;
24374let addrMode = BaseRegOffset;
24375let accessSize = WordAccess;
24376let isNVStore = 1;
24377let isNewValue = 1;
24378let isRestrictNoSlot1Store = 1;
24379let mayStore = 1;
24380let BaseOpcode = "S2_storeri_rr";
24381let CextOpcode = "S2_storeri";
24382let InputType = "reg";
24383let opNewValue = 4;
24384}
24385def S4_pstorerinewtnew_abs : HInst<
24386(outs),
24387(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8),
24388"if ($Pv4.new) memw(#$Ii) = $Nt8.new",
24389tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel {
24390let Inst{2-2} = 0b0;
24391let Inst{7-7} = 0b1;
24392let Inst{13-11} = 0b110;
24393let Inst{31-18} = 0b10101111101000;
24394let isPredicated = 1;
24395let addrMode = Absolute;
24396let accessSize = WordAccess;
24397let isNVStore = 1;
24398let isPredicatedNew = 1;
24399let isNewValue = 1;
24400let isExtended = 1;
24401let isRestrictNoSlot1Store = 1;
24402let mayStore = 1;
24403let BaseOpcode = "S2_storeriabs";
24404let CextOpcode = "S2_storeri";
24405let DecoderNamespace = "MustExtend";
24406let isExtendable = 1;
24407let opExtendable = 1;
24408let isExtentSigned = 0;
24409let opExtentBits = 6;
24410let opExtentAlign = 0;
24411let opNewValue = 2;
24412}
24413def S4_pstorerinewtnew_io : HInst<
24414(outs),
24415(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8),
24416"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new",
24417tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel {
24418let Inst{2-2} = 0b0;
24419let Inst{12-11} = 0b10;
24420let Inst{31-21} = 0b01000010101;
24421let isPredicated = 1;
24422let addrMode = BaseImmOffset;
24423let accessSize = WordAccess;
24424let isNVStore = 1;
24425let isPredicatedNew = 1;
24426let isNewValue = 1;
24427let isRestrictNoSlot1Store = 1;
24428let mayStore = 1;
24429let BaseOpcode = "S2_storeri_io";
24430let CextOpcode = "S2_storeri";
24431let InputType = "imm";
24432let isExtendable = 1;
24433let opExtendable = 2;
24434let isExtentSigned = 0;
24435let opExtentBits = 8;
24436let opExtentAlign = 2;
24437let opNewValue = 3;
24438}
24439def S4_pstorerinewtnew_rr : HInst<
24440(outs),
24441(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
24442"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
24443tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel {
24444let Inst{4-3} = 0b10;
24445let Inst{31-21} = 0b00110110101;
24446let isPredicated = 1;
24447let addrMode = BaseRegOffset;
24448let accessSize = WordAccess;
24449let isNVStore = 1;
24450let isPredicatedNew = 1;
24451let isNewValue = 1;
24452let isRestrictNoSlot1Store = 1;
24453let mayStore = 1;
24454let BaseOpcode = "S2_storeri_rr";
24455let CextOpcode = "S2_storeri";
24456let InputType = "reg";
24457let opNewValue = 4;
24458}
24459def S4_pstorerinewtnew_zomap : HInst<
24460(outs),
24461(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8),
24462"if ($Pv4.new) memw($Rs32) = $Nt8.new",
24463tc_92240447, TypeMAPPING> {
24464let isPseudo = 1;
24465let isCodeGenOnly = 1;
24466let opNewValue = 2;
24467}
24468def S4_pstorerit_abs : HInst<
24469(outs),
24470(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24471"if ($Pv4) memw(#$Ii) = $Rt32",
24472tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel {
24473let Inst{2-2} = 0b0;
24474let Inst{7-7} = 0b1;
24475let Inst{13-13} = 0b0;
24476let Inst{31-18} = 0b10101111100000;
24477let isPredicated = 1;
24478let addrMode = Absolute;
24479let accessSize = WordAccess;
24480let isExtended = 1;
24481let mayStore = 1;
24482let BaseOpcode = "S2_storeriabs";
24483let CextOpcode = "S2_storeri";
24484let isNVStorable = 1;
24485let DecoderNamespace = "MustExtend";
24486let isExtendable = 1;
24487let opExtendable = 1;
24488let isExtentSigned = 0;
24489let opExtentBits = 6;
24490let opExtentAlign = 0;
24491}
24492def S4_pstorerit_rr : HInst<
24493(outs),
24494(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24495"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24496tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel {
24497let Inst{31-21} = 0b00110100100;
24498let isPredicated = 1;
24499let addrMode = BaseRegOffset;
24500let accessSize = WordAccess;
24501let mayStore = 1;
24502let BaseOpcode = "S2_storeri_rr";
24503let CextOpcode = "S2_storeri";
24504let InputType = "reg";
24505let isNVStorable = 1;
24506}
24507def S4_pstoreritnew_abs : HInst<
24508(outs),
24509(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32),
24510"if ($Pv4.new) memw(#$Ii) = $Rt32",
24511tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel {
24512let Inst{2-2} = 0b0;
24513let Inst{7-7} = 0b1;
24514let Inst{13-13} = 0b1;
24515let Inst{31-18} = 0b10101111100000;
24516let isPredicated = 1;
24517let addrMode = Absolute;
24518let accessSize = WordAccess;
24519let isPredicatedNew = 1;
24520let isExtended = 1;
24521let mayStore = 1;
24522let BaseOpcode = "S2_storeriabs";
24523let CextOpcode = "S2_storeri";
24524let isNVStorable = 1;
24525let DecoderNamespace = "MustExtend";
24526let isExtendable = 1;
24527let opExtendable = 1;
24528let isExtentSigned = 0;
24529let opExtentBits = 6;
24530let opExtentAlign = 0;
24531}
24532def S4_pstoreritnew_io : HInst<
24533(outs),
24534(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32),
24535"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32",
24536tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel {
24537let Inst{2-2} = 0b0;
24538let Inst{31-21} = 0b01000010100;
24539let isPredicated = 1;
24540let addrMode = BaseImmOffset;
24541let accessSize = WordAccess;
24542let isPredicatedNew = 1;
24543let mayStore = 1;
24544let BaseOpcode = "S2_storeri_io";
24545let CextOpcode = "S2_storeri";
24546let InputType = "imm";
24547let isNVStorable = 1;
24548let isExtendable = 1;
24549let opExtendable = 2;
24550let isExtentSigned = 0;
24551let opExtentBits = 8;
24552let opExtentAlign = 2;
24553}
24554def S4_pstoreritnew_rr : HInst<
24555(outs),
24556(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
24557"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32",
24558tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel {
24559let Inst{31-21} = 0b00110110100;
24560let isPredicated = 1;
24561let addrMode = BaseRegOffset;
24562let accessSize = WordAccess;
24563let isPredicatedNew = 1;
24564let mayStore = 1;
24565let BaseOpcode = "S2_storeri_rr";
24566let CextOpcode = "S2_storeri";
24567let InputType = "reg";
24568let isNVStorable = 1;
24569}
24570def S4_pstoreritnew_zomap : HInst<
24571(outs),
24572(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32),
24573"if ($Pv4.new) memw($Rs32) = $Rt32",
24574tc_a2b365d2, TypeMAPPING> {
24575let isPseudo = 1;
24576let isCodeGenOnly = 1;
24577}
24578def S4_stored_locked : HInst<
24579(outs PredRegs:$Pd4),
24580(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24581"memd_locked($Rs32,$Pd4) = $Rtt32",
24582tc_6f42bc60, TypeST>, Enc_d7dc10 {
24583let Inst{7-2} = 0b000000;
24584let Inst{13-13} = 0b0;
24585let Inst{31-21} = 0b10100000111;
24586let accessSize = DoubleWordAccess;
24587let isPredicateLate = 1;
24588let isSoloAX = 1;
24589let mayStore = 1;
24590}
24591def S4_stored_rl_at_vi : HInst<
24592(outs),
24593(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24594"memd_rl($Rs32):at = $Rtt32",
24595tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24596let Inst{7-2} = 0b000010;
24597let Inst{13-13} = 0b0;
24598let Inst{31-21} = 0b10100000111;
24599let accessSize = DoubleWordAccess;
24600let isSolo = 1;
24601let mayStore = 1;
24602}
24603def S4_stored_rl_st_vi : HInst<
24604(outs),
24605(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
24606"memd_rl($Rs32):st = $Rtt32",
24607tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> {
24608let Inst{7-2} = 0b001010;
24609let Inst{13-13} = 0b0;
24610let Inst{31-21} = 0b10100000111;
24611let accessSize = DoubleWordAccess;
24612let isSolo = 1;
24613let mayStore = 1;
24614}
24615def S4_storeirb_io : HInst<
24616(outs),
24617(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24618"memb($Rs32+#$Ii) = #$II",
24619tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel {
24620let Inst{31-21} = 0b00111100000;
24621let addrMode = BaseImmOffset;
24622let accessSize = ByteAccess;
24623let mayStore = 1;
24624let BaseOpcode = "S4_storeirb_io";
24625let CextOpcode = "S2_storerb";
24626let InputType = "imm";
24627let isPredicable = 1;
24628let isExtendable = 1;
24629let opExtendable = 2;
24630let isExtentSigned = 1;
24631let opExtentBits = 8;
24632let opExtentAlign = 0;
24633}
24634def S4_storeirb_zomap : HInst<
24635(outs),
24636(ins IntRegs:$Rs32, s8_0Imm:$II),
24637"memb($Rs32) = #$II",
24638tc_7c31e19a, TypeMAPPING> {
24639let isPseudo = 1;
24640let isCodeGenOnly = 1;
24641}
24642def S4_storeirbf_io : HInst<
24643(outs),
24644(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24645"if (!$Pv4) memb($Rs32+#$Ii) = #$II",
24646tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24647let Inst{31-21} = 0b00111000100;
24648let isPredicated = 1;
24649let isPredicatedFalse = 1;
24650let addrMode = BaseImmOffset;
24651let accessSize = ByteAccess;
24652let mayStore = 1;
24653let BaseOpcode = "S4_storeirb_io";
24654let CextOpcode = "S2_storerb";
24655let InputType = "imm";
24656let isExtendable = 1;
24657let opExtendable = 3;
24658let isExtentSigned = 1;
24659let opExtentBits = 6;
24660let opExtentAlign = 0;
24661}
24662def S4_storeirbf_zomap : HInst<
24663(outs),
24664(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24665"if (!$Pv4) memb($Rs32) = #$II",
24666tc_d03278fd, TypeMAPPING> {
24667let isPseudo = 1;
24668let isCodeGenOnly = 1;
24669}
24670def S4_storeirbfnew_io : HInst<
24671(outs),
24672(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24673"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II",
24674tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24675let Inst{31-21} = 0b00111001100;
24676let isPredicated = 1;
24677let isPredicatedFalse = 1;
24678let addrMode = BaseImmOffset;
24679let accessSize = ByteAccess;
24680let isPredicatedNew = 1;
24681let mayStore = 1;
24682let BaseOpcode = "S4_storeirb_io";
24683let CextOpcode = "S2_storerb";
24684let InputType = "imm";
24685let isExtendable = 1;
24686let opExtendable = 3;
24687let isExtentSigned = 1;
24688let opExtentBits = 6;
24689let opExtentAlign = 0;
24690}
24691def S4_storeirbfnew_zomap : HInst<
24692(outs),
24693(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24694"if (!$Pv4.new) memb($Rs32) = #$II",
24695tc_65cbd974, TypeMAPPING> {
24696let isPseudo = 1;
24697let isCodeGenOnly = 1;
24698}
24699def S4_storeirbt_io : HInst<
24700(outs),
24701(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24702"if ($Pv4) memb($Rs32+#$Ii) = #$II",
24703tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel {
24704let Inst{31-21} = 0b00111000000;
24705let isPredicated = 1;
24706let addrMode = BaseImmOffset;
24707let accessSize = ByteAccess;
24708let mayStore = 1;
24709let BaseOpcode = "S4_storeirb_io";
24710let CextOpcode = "S2_storerb";
24711let InputType = "imm";
24712let isExtendable = 1;
24713let opExtendable = 3;
24714let isExtentSigned = 1;
24715let opExtentBits = 6;
24716let opExtentAlign = 0;
24717}
24718def S4_storeirbt_zomap : HInst<
24719(outs),
24720(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24721"if ($Pv4) memb($Rs32) = #$II",
24722tc_d03278fd, TypeMAPPING> {
24723let isPseudo = 1;
24724let isCodeGenOnly = 1;
24725}
24726def S4_storeirbtnew_io : HInst<
24727(outs),
24728(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
24729"if ($Pv4.new) memb($Rs32+#$Ii) = #$II",
24730tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel {
24731let Inst{31-21} = 0b00111001000;
24732let isPredicated = 1;
24733let addrMode = BaseImmOffset;
24734let accessSize = ByteAccess;
24735let isPredicatedNew = 1;
24736let mayStore = 1;
24737let BaseOpcode = "S4_storeirb_io";
24738let CextOpcode = "S2_storerb";
24739let InputType = "imm";
24740let isExtendable = 1;
24741let opExtendable = 3;
24742let isExtentSigned = 1;
24743let opExtentBits = 6;
24744let opExtentAlign = 0;
24745}
24746def S4_storeirbtnew_zomap : HInst<
24747(outs),
24748(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24749"if ($Pv4.new) memb($Rs32) = #$II",
24750tc_65cbd974, TypeMAPPING> {
24751let isPseudo = 1;
24752let isCodeGenOnly = 1;
24753}
24754def S4_storeirh_io : HInst<
24755(outs),
24756(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24757"memh($Rs32+#$Ii) = #$II",
24758tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel {
24759let Inst{31-21} = 0b00111100001;
24760let addrMode = BaseImmOffset;
24761let accessSize = HalfWordAccess;
24762let mayStore = 1;
24763let BaseOpcode = "S4_storeirh_io";
24764let CextOpcode = "S2_storerh";
24765let InputType = "imm";
24766let isPredicable = 1;
24767let isExtendable = 1;
24768let opExtendable = 2;
24769let isExtentSigned = 1;
24770let opExtentBits = 8;
24771let opExtentAlign = 0;
24772}
24773def S4_storeirh_zomap : HInst<
24774(outs),
24775(ins IntRegs:$Rs32, s8_0Imm:$II),
24776"memh($Rs32) = #$II",
24777tc_7c31e19a, TypeMAPPING> {
24778let isPseudo = 1;
24779let isCodeGenOnly = 1;
24780}
24781def S4_storeirhf_io : HInst<
24782(outs),
24783(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24784"if (!$Pv4) memh($Rs32+#$Ii) = #$II",
24785tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24786let Inst{31-21} = 0b00111000101;
24787let isPredicated = 1;
24788let isPredicatedFalse = 1;
24789let addrMode = BaseImmOffset;
24790let accessSize = HalfWordAccess;
24791let mayStore = 1;
24792let BaseOpcode = "S4_storeirh_io";
24793let CextOpcode = "S2_storerh";
24794let InputType = "imm";
24795let isExtendable = 1;
24796let opExtendable = 3;
24797let isExtentSigned = 1;
24798let opExtentBits = 6;
24799let opExtentAlign = 0;
24800}
24801def S4_storeirhf_zomap : HInst<
24802(outs),
24803(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24804"if (!$Pv4) memh($Rs32) = #$II",
24805tc_d03278fd, TypeMAPPING> {
24806let isPseudo = 1;
24807let isCodeGenOnly = 1;
24808}
24809def S4_storeirhfnew_io : HInst<
24810(outs),
24811(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24812"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II",
24813tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24814let Inst{31-21} = 0b00111001101;
24815let isPredicated = 1;
24816let isPredicatedFalse = 1;
24817let addrMode = BaseImmOffset;
24818let accessSize = HalfWordAccess;
24819let isPredicatedNew = 1;
24820let mayStore = 1;
24821let BaseOpcode = "S4_storeirh_io";
24822let CextOpcode = "S2_storerh";
24823let InputType = "imm";
24824let isExtendable = 1;
24825let opExtendable = 3;
24826let isExtentSigned = 1;
24827let opExtentBits = 6;
24828let opExtentAlign = 0;
24829}
24830def S4_storeirhfnew_zomap : HInst<
24831(outs),
24832(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24833"if (!$Pv4.new) memh($Rs32) = #$II",
24834tc_65cbd974, TypeMAPPING> {
24835let isPseudo = 1;
24836let isCodeGenOnly = 1;
24837}
24838def S4_storeirht_io : HInst<
24839(outs),
24840(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24841"if ($Pv4) memh($Rs32+#$Ii) = #$II",
24842tc_d03278fd, TypeST>, Enc_f20719, PredNewRel {
24843let Inst{31-21} = 0b00111000001;
24844let isPredicated = 1;
24845let addrMode = BaseImmOffset;
24846let accessSize = HalfWordAccess;
24847let mayStore = 1;
24848let BaseOpcode = "S4_storeirh_io";
24849let CextOpcode = "S2_storerh";
24850let InputType = "imm";
24851let isExtendable = 1;
24852let opExtendable = 3;
24853let isExtentSigned = 1;
24854let opExtentBits = 6;
24855let opExtentAlign = 0;
24856}
24857def S4_storeirht_zomap : HInst<
24858(outs),
24859(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24860"if ($Pv4) memh($Rs32) = #$II",
24861tc_d03278fd, TypeMAPPING> {
24862let isPseudo = 1;
24863let isCodeGenOnly = 1;
24864}
24865def S4_storeirhtnew_io : HInst<
24866(outs),
24867(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II),
24868"if ($Pv4.new) memh($Rs32+#$Ii) = #$II",
24869tc_65cbd974, TypeST>, Enc_f20719, PredNewRel {
24870let Inst{31-21} = 0b00111001001;
24871let isPredicated = 1;
24872let addrMode = BaseImmOffset;
24873let accessSize = HalfWordAccess;
24874let isPredicatedNew = 1;
24875let mayStore = 1;
24876let BaseOpcode = "S4_storeirh_io";
24877let CextOpcode = "S2_storerh";
24878let InputType = "imm";
24879let isExtendable = 1;
24880let opExtendable = 3;
24881let isExtentSigned = 1;
24882let opExtentBits = 6;
24883let opExtentAlign = 0;
24884}
24885def S4_storeirhtnew_zomap : HInst<
24886(outs),
24887(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24888"if ($Pv4.new) memh($Rs32) = #$II",
24889tc_65cbd974, TypeMAPPING> {
24890let isPseudo = 1;
24891let isCodeGenOnly = 1;
24892}
24893def S4_storeiri_io : HInst<
24894(outs),
24895(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24896"memw($Rs32+#$Ii) = #$II",
24897tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel {
24898let Inst{31-21} = 0b00111100010;
24899let addrMode = BaseImmOffset;
24900let accessSize = WordAccess;
24901let mayStore = 1;
24902let BaseOpcode = "S4_storeiri_io";
24903let CextOpcode = "S2_storeri";
24904let InputType = "imm";
24905let isPredicable = 1;
24906let isExtendable = 1;
24907let opExtendable = 2;
24908let isExtentSigned = 1;
24909let opExtentBits = 8;
24910let opExtentAlign = 0;
24911}
24912def S4_storeiri_zomap : HInst<
24913(outs),
24914(ins IntRegs:$Rs32, s8_0Imm:$II),
24915"memw($Rs32) = #$II",
24916tc_7c31e19a, TypeMAPPING> {
24917let isPseudo = 1;
24918let isCodeGenOnly = 1;
24919}
24920def S4_storeirif_io : HInst<
24921(outs),
24922(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24923"if (!$Pv4) memw($Rs32+#$Ii) = #$II",
24924tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24925let Inst{31-21} = 0b00111000110;
24926let isPredicated = 1;
24927let isPredicatedFalse = 1;
24928let addrMode = BaseImmOffset;
24929let accessSize = WordAccess;
24930let mayStore = 1;
24931let BaseOpcode = "S4_storeiri_io";
24932let CextOpcode = "S2_storeri";
24933let InputType = "imm";
24934let isExtendable = 1;
24935let opExtendable = 3;
24936let isExtentSigned = 1;
24937let opExtentBits = 6;
24938let opExtentAlign = 0;
24939}
24940def S4_storeirif_zomap : HInst<
24941(outs),
24942(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24943"if (!$Pv4) memw($Rs32) = #$II",
24944tc_d03278fd, TypeMAPPING> {
24945let isPseudo = 1;
24946let isCodeGenOnly = 1;
24947}
24948def S4_storeirifnew_io : HInst<
24949(outs),
24950(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24951"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II",
24952tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
24953let Inst{31-21} = 0b00111001110;
24954let isPredicated = 1;
24955let isPredicatedFalse = 1;
24956let addrMode = BaseImmOffset;
24957let accessSize = WordAccess;
24958let isPredicatedNew = 1;
24959let mayStore = 1;
24960let BaseOpcode = "S4_storeiri_io";
24961let CextOpcode = "S2_storeri";
24962let InputType = "imm";
24963let isExtendable = 1;
24964let opExtendable = 3;
24965let isExtentSigned = 1;
24966let opExtentBits = 6;
24967let opExtentAlign = 0;
24968}
24969def S4_storeirifnew_zomap : HInst<
24970(outs),
24971(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24972"if (!$Pv4.new) memw($Rs32) = #$II",
24973tc_65cbd974, TypeMAPPING> {
24974let isPseudo = 1;
24975let isCodeGenOnly = 1;
24976}
24977def S4_storeirit_io : HInst<
24978(outs),
24979(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
24980"if ($Pv4) memw($Rs32+#$Ii) = #$II",
24981tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel {
24982let Inst{31-21} = 0b00111000010;
24983let isPredicated = 1;
24984let addrMode = BaseImmOffset;
24985let accessSize = WordAccess;
24986let mayStore = 1;
24987let BaseOpcode = "S4_storeiri_io";
24988let CextOpcode = "S2_storeri";
24989let InputType = "imm";
24990let isExtendable = 1;
24991let opExtendable = 3;
24992let isExtentSigned = 1;
24993let opExtentBits = 6;
24994let opExtentAlign = 0;
24995}
24996def S4_storeirit_zomap : HInst<
24997(outs),
24998(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
24999"if ($Pv4) memw($Rs32) = #$II",
25000tc_d03278fd, TypeMAPPING> {
25001let isPseudo = 1;
25002let isCodeGenOnly = 1;
25003}
25004def S4_storeiritnew_io : HInst<
25005(outs),
25006(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
25007"if ($Pv4.new) memw($Rs32+#$Ii) = #$II",
25008tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel {
25009let Inst{31-21} = 0b00111001010;
25010let isPredicated = 1;
25011let addrMode = BaseImmOffset;
25012let accessSize = WordAccess;
25013let isPredicatedNew = 1;
25014let mayStore = 1;
25015let BaseOpcode = "S4_storeiri_io";
25016let CextOpcode = "S2_storeri";
25017let InputType = "imm";
25018let isExtendable = 1;
25019let opExtendable = 3;
25020let isExtentSigned = 1;
25021let opExtentBits = 6;
25022let opExtentAlign = 0;
25023}
25024def S4_storeiritnew_zomap : HInst<
25025(outs),
25026(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II),
25027"if ($Pv4.new) memw($Rs32) = #$II",
25028tc_65cbd974, TypeMAPPING> {
25029let isPseudo = 1;
25030let isCodeGenOnly = 1;
25031}
25032def S4_storerb_ap : HInst<
25033(outs IntRegs:$Re32),
25034(ins u32_0Imm:$II, IntRegs:$Rt32),
25035"memb($Re32=#$II) = $Rt32",
25036tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25037let Inst{7-6} = 0b10;
25038let Inst{13-13} = 0b0;
25039let Inst{31-21} = 0b10101011000;
25040let addrMode = AbsoluteSet;
25041let accessSize = ByteAccess;
25042let isExtended = 1;
25043let mayStore = 1;
25044let BaseOpcode = "S2_storerb_ap";
25045let isNVStorable = 1;
25046let DecoderNamespace = "MustExtend";
25047let isExtendable = 1;
25048let opExtendable = 1;
25049let isExtentSigned = 0;
25050let opExtentBits = 6;
25051let opExtentAlign = 0;
25052}
25053def S4_storerb_rr : HInst<
25054(outs),
25055(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25056"memb($Rs32+$Ru32<<#$Ii) = $Rt32",
25057tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25058let Inst{6-5} = 0b00;
25059let Inst{31-21} = 0b00111011000;
25060let addrMode = BaseRegOffset;
25061let accessSize = ByteAccess;
25062let mayStore = 1;
25063let BaseOpcode = "S4_storerb_rr";
25064let CextOpcode = "S2_storerb";
25065let InputType = "reg";
25066let isNVStorable = 1;
25067let isPredicable = 1;
25068}
25069def S4_storerb_ur : HInst<
25070(outs),
25071(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25072"memb($Ru32<<#$Ii+#$II) = $Rt32",
25073tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25074let Inst{7-7} = 0b1;
25075let Inst{31-21} = 0b10101101000;
25076let addrMode = BaseLongOffset;
25077let accessSize = ByteAccess;
25078let isExtended = 1;
25079let mayStore = 1;
25080let BaseOpcode = "S4_storerb_ur";
25081let CextOpcode = "S2_storerb";
25082let InputType = "imm";
25083let isNVStorable = 1;
25084let DecoderNamespace = "MustExtend";
25085let isExtendable = 1;
25086let opExtendable = 2;
25087let isExtentSigned = 0;
25088let opExtentBits = 6;
25089let opExtentAlign = 0;
25090}
25091def S4_storerbnew_ap : HInst<
25092(outs IntRegs:$Re32),
25093(ins u32_0Imm:$II, IntRegs:$Nt8),
25094"memb($Re32=#$II) = $Nt8.new",
25095tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25096let Inst{7-6} = 0b10;
25097let Inst{13-11} = 0b000;
25098let Inst{31-21} = 0b10101011101;
25099let addrMode = AbsoluteSet;
25100let accessSize = ByteAccess;
25101let isNVStore = 1;
25102let isNewValue = 1;
25103let isExtended = 1;
25104let isRestrictNoSlot1Store = 1;
25105let mayStore = 1;
25106let BaseOpcode = "S2_storerb_ap";
25107let DecoderNamespace = "MustExtend";
25108let isExtendable = 1;
25109let opExtendable = 1;
25110let isExtentSigned = 0;
25111let opExtentBits = 6;
25112let opExtentAlign = 0;
25113let opNewValue = 2;
25114}
25115def S4_storerbnew_rr : HInst<
25116(outs),
25117(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25118"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25119tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25120let Inst{6-3} = 0b0000;
25121let Inst{31-21} = 0b00111011101;
25122let addrMode = BaseRegOffset;
25123let accessSize = ByteAccess;
25124let isNVStore = 1;
25125let isNewValue = 1;
25126let isRestrictNoSlot1Store = 1;
25127let mayStore = 1;
25128let BaseOpcode = "S4_storerb_rr";
25129let CextOpcode = "S2_storerb";
25130let InputType = "reg";
25131let isPredicable = 1;
25132let opNewValue = 3;
25133}
25134def S4_storerbnew_ur : HInst<
25135(outs),
25136(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25137"memb($Ru32<<#$Ii+#$II) = $Nt8.new",
25138tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25139let Inst{7-7} = 0b1;
25140let Inst{12-11} = 0b00;
25141let Inst{31-21} = 0b10101101101;
25142let addrMode = BaseLongOffset;
25143let accessSize = ByteAccess;
25144let isNVStore = 1;
25145let isNewValue = 1;
25146let isExtended = 1;
25147let isRestrictNoSlot1Store = 1;
25148let mayStore = 1;
25149let BaseOpcode = "S4_storerb_ur";
25150let CextOpcode = "S2_storerb";
25151let DecoderNamespace = "MustExtend";
25152let isExtendable = 1;
25153let opExtendable = 2;
25154let isExtentSigned = 0;
25155let opExtentBits = 6;
25156let opExtentAlign = 0;
25157let opNewValue = 3;
25158}
25159def S4_storerd_ap : HInst<
25160(outs IntRegs:$Re32),
25161(ins u32_0Imm:$II, DoubleRegs:$Rtt32),
25162"memd($Re32=#$II) = $Rtt32",
25163tc_bb07f2c5, TypeST>, Enc_c7a204 {
25164let Inst{7-6} = 0b10;
25165let Inst{13-13} = 0b0;
25166let Inst{31-21} = 0b10101011110;
25167let addrMode = AbsoluteSet;
25168let accessSize = DoubleWordAccess;
25169let isExtended = 1;
25170let mayStore = 1;
25171let BaseOpcode = "S4_storerd_ap";
25172let DecoderNamespace = "MustExtend";
25173let isExtendable = 1;
25174let opExtendable = 1;
25175let isExtentSigned = 0;
25176let opExtentBits = 6;
25177let opExtentAlign = 0;
25178}
25179def S4_storerd_rr : HInst<
25180(outs),
25181(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32),
25182"memd($Rs32+$Ru32<<#$Ii) = $Rtt32",
25183tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl {
25184let Inst{6-5} = 0b00;
25185let Inst{31-21} = 0b00111011110;
25186let addrMode = BaseRegOffset;
25187let accessSize = DoubleWordAccess;
25188let mayStore = 1;
25189let BaseOpcode = "S2_storerd_rr";
25190let CextOpcode = "S2_storerd";
25191let InputType = "reg";
25192let isPredicable = 1;
25193}
25194def S4_storerd_ur : HInst<
25195(outs),
25196(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32),
25197"memd($Ru32<<#$Ii+#$II) = $Rtt32",
25198tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl {
25199let Inst{7-7} = 0b1;
25200let Inst{31-21} = 0b10101101110;
25201let addrMode = BaseLongOffset;
25202let accessSize = DoubleWordAccess;
25203let isExtended = 1;
25204let mayStore = 1;
25205let BaseOpcode = "S2_storerd_ur";
25206let CextOpcode = "S2_storerd";
25207let InputType = "imm";
25208let DecoderNamespace = "MustExtend";
25209let isExtendable = 1;
25210let opExtendable = 2;
25211let isExtentSigned = 0;
25212let opExtentBits = 6;
25213let opExtentAlign = 0;
25214}
25215def S4_storerf_ap : HInst<
25216(outs IntRegs:$Re32),
25217(ins u32_0Imm:$II, IntRegs:$Rt32),
25218"memh($Re32=#$II) = $Rt32.h",
25219tc_bb07f2c5, TypeST>, Enc_8bcba4 {
25220let Inst{7-6} = 0b10;
25221let Inst{13-13} = 0b0;
25222let Inst{31-21} = 0b10101011011;
25223let addrMode = AbsoluteSet;
25224let accessSize = HalfWordAccess;
25225let isExtended = 1;
25226let mayStore = 1;
25227let BaseOpcode = "S4_storerf_ap";
25228let DecoderNamespace = "MustExtend";
25229let isExtendable = 1;
25230let opExtendable = 1;
25231let isExtentSigned = 0;
25232let opExtentBits = 6;
25233let opExtentAlign = 0;
25234}
25235def S4_storerf_rr : HInst<
25236(outs),
25237(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25238"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h",
25239tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25240let Inst{6-5} = 0b00;
25241let Inst{31-21} = 0b00111011011;
25242let addrMode = BaseRegOffset;
25243let accessSize = HalfWordAccess;
25244let mayStore = 1;
25245let BaseOpcode = "S4_storerf_rr";
25246let CextOpcode = "S2_storerf";
25247let InputType = "reg";
25248let isPredicable = 1;
25249}
25250def S4_storerf_ur : HInst<
25251(outs),
25252(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25253"memh($Ru32<<#$Ii+#$II) = $Rt32.h",
25254tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25255let Inst{7-7} = 0b1;
25256let Inst{31-21} = 0b10101101011;
25257let addrMode = BaseLongOffset;
25258let accessSize = HalfWordAccess;
25259let isExtended = 1;
25260let mayStore = 1;
25261let BaseOpcode = "S4_storerf_rr";
25262let CextOpcode = "S2_storerf";
25263let InputType = "imm";
25264let DecoderNamespace = "MustExtend";
25265let isExtendable = 1;
25266let opExtendable = 2;
25267let isExtentSigned = 0;
25268let opExtentBits = 6;
25269let opExtentAlign = 0;
25270}
25271def S4_storerh_ap : HInst<
25272(outs IntRegs:$Re32),
25273(ins u32_0Imm:$II, IntRegs:$Rt32),
25274"memh($Re32=#$II) = $Rt32",
25275tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25276let Inst{7-6} = 0b10;
25277let Inst{13-13} = 0b0;
25278let Inst{31-21} = 0b10101011010;
25279let addrMode = AbsoluteSet;
25280let accessSize = HalfWordAccess;
25281let isExtended = 1;
25282let mayStore = 1;
25283let BaseOpcode = "S2_storerh_ap";
25284let isNVStorable = 1;
25285let DecoderNamespace = "MustExtend";
25286let isExtendable = 1;
25287let opExtendable = 1;
25288let isExtentSigned = 0;
25289let opExtentBits = 6;
25290let opExtentAlign = 0;
25291}
25292def S4_storerh_rr : HInst<
25293(outs),
25294(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25295"memh($Rs32+$Ru32<<#$Ii) = $Rt32",
25296tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25297let Inst{6-5} = 0b00;
25298let Inst{31-21} = 0b00111011010;
25299let addrMode = BaseRegOffset;
25300let accessSize = HalfWordAccess;
25301let mayStore = 1;
25302let BaseOpcode = "S2_storerh_rr";
25303let CextOpcode = "S2_storerh";
25304let InputType = "reg";
25305let isNVStorable = 1;
25306let isPredicable = 1;
25307}
25308def S4_storerh_ur : HInst<
25309(outs),
25310(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25311"memh($Ru32<<#$Ii+#$II) = $Rt32",
25312tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25313let Inst{7-7} = 0b1;
25314let Inst{31-21} = 0b10101101010;
25315let addrMode = BaseLongOffset;
25316let accessSize = HalfWordAccess;
25317let isExtended = 1;
25318let mayStore = 1;
25319let BaseOpcode = "S2_storerh_ur";
25320let CextOpcode = "S2_storerh";
25321let InputType = "imm";
25322let isNVStorable = 1;
25323let DecoderNamespace = "MustExtend";
25324let isExtendable = 1;
25325let opExtendable = 2;
25326let isExtentSigned = 0;
25327let opExtentBits = 6;
25328let opExtentAlign = 0;
25329}
25330def S4_storerhnew_ap : HInst<
25331(outs IntRegs:$Re32),
25332(ins u32_0Imm:$II, IntRegs:$Nt8),
25333"memh($Re32=#$II) = $Nt8.new",
25334tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25335let Inst{7-6} = 0b10;
25336let Inst{13-11} = 0b001;
25337let Inst{31-21} = 0b10101011101;
25338let addrMode = AbsoluteSet;
25339let accessSize = HalfWordAccess;
25340let isNVStore = 1;
25341let isNewValue = 1;
25342let isExtended = 1;
25343let isRestrictNoSlot1Store = 1;
25344let mayStore = 1;
25345let BaseOpcode = "S2_storerh_ap";
25346let DecoderNamespace = "MustExtend";
25347let isExtendable = 1;
25348let opExtendable = 1;
25349let isExtentSigned = 0;
25350let opExtentBits = 6;
25351let opExtentAlign = 0;
25352let opNewValue = 2;
25353}
25354def S4_storerhnew_rr : HInst<
25355(outs),
25356(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25357"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25358tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25359let Inst{6-3} = 0b0001;
25360let Inst{31-21} = 0b00111011101;
25361let addrMode = BaseRegOffset;
25362let accessSize = HalfWordAccess;
25363let isNVStore = 1;
25364let isNewValue = 1;
25365let isRestrictNoSlot1Store = 1;
25366let mayStore = 1;
25367let BaseOpcode = "S2_storerh_rr";
25368let CextOpcode = "S2_storerh";
25369let InputType = "reg";
25370let isPredicable = 1;
25371let opNewValue = 3;
25372}
25373def S4_storerhnew_ur : HInst<
25374(outs),
25375(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25376"memh($Ru32<<#$Ii+#$II) = $Nt8.new",
25377tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25378let Inst{7-7} = 0b1;
25379let Inst{12-11} = 0b01;
25380let Inst{31-21} = 0b10101101101;
25381let addrMode = BaseLongOffset;
25382let accessSize = HalfWordAccess;
25383let isNVStore = 1;
25384let isNewValue = 1;
25385let isExtended = 1;
25386let isRestrictNoSlot1Store = 1;
25387let mayStore = 1;
25388let BaseOpcode = "S2_storerh_ur";
25389let CextOpcode = "S2_storerh";
25390let DecoderNamespace = "MustExtend";
25391let isExtendable = 1;
25392let opExtendable = 2;
25393let isExtentSigned = 0;
25394let opExtentBits = 6;
25395let opExtentAlign = 0;
25396let opNewValue = 3;
25397}
25398def S4_storeri_ap : HInst<
25399(outs IntRegs:$Re32),
25400(ins u32_0Imm:$II, IntRegs:$Rt32),
25401"memw($Re32=#$II) = $Rt32",
25402tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel {
25403let Inst{7-6} = 0b10;
25404let Inst{13-13} = 0b0;
25405let Inst{31-21} = 0b10101011100;
25406let addrMode = AbsoluteSet;
25407let accessSize = WordAccess;
25408let isExtended = 1;
25409let mayStore = 1;
25410let BaseOpcode = "S2_storeri_ap";
25411let isNVStorable = 1;
25412let DecoderNamespace = "MustExtend";
25413let isExtendable = 1;
25414let opExtendable = 1;
25415let isExtentSigned = 0;
25416let opExtentBits = 6;
25417let opExtentAlign = 0;
25418}
25419def S4_storeri_rr : HInst<
25420(outs),
25421(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32),
25422"memw($Rs32+$Ru32<<#$Ii) = $Rt32",
25423tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl {
25424let Inst{6-5} = 0b00;
25425let Inst{31-21} = 0b00111011100;
25426let addrMode = BaseRegOffset;
25427let accessSize = WordAccess;
25428let mayStore = 1;
25429let BaseOpcode = "S2_storeri_rr";
25430let CextOpcode = "S2_storeri";
25431let InputType = "reg";
25432let isNVStorable = 1;
25433let isPredicable = 1;
25434}
25435def S4_storeri_ur : HInst<
25436(outs),
25437(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32),
25438"memw($Ru32<<#$Ii+#$II) = $Rt32",
25439tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl {
25440let Inst{7-7} = 0b1;
25441let Inst{31-21} = 0b10101101100;
25442let addrMode = BaseLongOffset;
25443let accessSize = WordAccess;
25444let isExtended = 1;
25445let mayStore = 1;
25446let BaseOpcode = "S2_storeri_ur";
25447let CextOpcode = "S2_storeri";
25448let InputType = "imm";
25449let isNVStorable = 1;
25450let DecoderNamespace = "MustExtend";
25451let isExtendable = 1;
25452let opExtendable = 2;
25453let isExtentSigned = 0;
25454let opExtentBits = 6;
25455let opExtentAlign = 0;
25456}
25457def S4_storerinew_ap : HInst<
25458(outs IntRegs:$Re32),
25459(ins u32_0Imm:$II, IntRegs:$Nt8),
25460"memw($Re32=#$II) = $Nt8.new",
25461tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel {
25462let Inst{7-6} = 0b10;
25463let Inst{13-11} = 0b010;
25464let Inst{31-21} = 0b10101011101;
25465let addrMode = AbsoluteSet;
25466let accessSize = WordAccess;
25467let isNVStore = 1;
25468let isNewValue = 1;
25469let isExtended = 1;
25470let isRestrictNoSlot1Store = 1;
25471let mayStore = 1;
25472let BaseOpcode = "S2_storeri_ap";
25473let DecoderNamespace = "MustExtend";
25474let isExtendable = 1;
25475let opExtendable = 1;
25476let isExtentSigned = 0;
25477let opExtentBits = 6;
25478let opExtentAlign = 0;
25479let opNewValue = 2;
25480}
25481def S4_storerinew_rr : HInst<
25482(outs),
25483(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8),
25484"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new",
25485tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel {
25486let Inst{6-3} = 0b0010;
25487let Inst{31-21} = 0b00111011101;
25488let addrMode = BaseRegOffset;
25489let accessSize = WordAccess;
25490let isNVStore = 1;
25491let isNewValue = 1;
25492let isRestrictNoSlot1Store = 1;
25493let mayStore = 1;
25494let BaseOpcode = "S2_storeri_rr";
25495let CextOpcode = "S2_storeri";
25496let InputType = "reg";
25497let isPredicable = 1;
25498let opNewValue = 3;
25499}
25500def S4_storerinew_ur : HInst<
25501(outs),
25502(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8),
25503"memw($Ru32<<#$Ii+#$II) = $Nt8.new",
25504tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel {
25505let Inst{7-7} = 0b1;
25506let Inst{12-11} = 0b10;
25507let Inst{31-21} = 0b10101101101;
25508let addrMode = BaseLongOffset;
25509let accessSize = WordAccess;
25510let isNVStore = 1;
25511let isNewValue = 1;
25512let isExtended = 1;
25513let isRestrictNoSlot1Store = 1;
25514let mayStore = 1;
25515let BaseOpcode = "S2_storeri_ur";
25516let CextOpcode = "S2_storeri";
25517let DecoderNamespace = "MustExtend";
25518let isExtendable = 1;
25519let opExtendable = 2;
25520let isExtentSigned = 0;
25521let opExtentBits = 6;
25522let opExtentAlign = 0;
25523let opNewValue = 3;
25524}
25525def S4_subaddi : HInst<
25526(outs IntRegs:$Rd32),
25527(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32),
25528"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))",
25529tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> {
25530let Inst{31-23} = 0b110110111;
25531let hasNewValue = 1;
25532let opNewValue = 0;
25533let prefersSlot3 = 1;
25534let isExtendable = 1;
25535let opExtendable = 2;
25536let isExtentSigned = 1;
25537let opExtentBits = 6;
25538let opExtentAlign = 0;
25539}
25540def S4_subi_asl_ri : HInst<
25541(outs IntRegs:$Rx32),
25542(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25543"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))",
25544tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25545let Inst{2-0} = 0b110;
25546let Inst{4-4} = 0b0;
25547let Inst{31-24} = 0b11011110;
25548let hasNewValue = 1;
25549let opNewValue = 0;
25550let prefersSlot3 = 1;
25551let isExtendable = 1;
25552let opExtendable = 1;
25553let isExtentSigned = 0;
25554let opExtentBits = 8;
25555let opExtentAlign = 0;
25556let Constraints = "$Rx32 = $Rx32in";
25557}
25558def S4_subi_lsr_ri : HInst<
25559(outs IntRegs:$Rx32),
25560(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II),
25561"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))",
25562tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> {
25563let Inst{2-0} = 0b110;
25564let Inst{4-4} = 0b1;
25565let Inst{31-24} = 0b11011110;
25566let hasNewValue = 1;
25567let opNewValue = 0;
25568let prefersSlot3 = 1;
25569let isExtendable = 1;
25570let opExtendable = 1;
25571let isExtentSigned = 0;
25572let opExtentBits = 8;
25573let opExtentAlign = 0;
25574let Constraints = "$Rx32 = $Rx32in";
25575}
25576def S4_vrcrotate : HInst<
25577(outs DoubleRegs:$Rdd32),
25578(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25579"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)",
25580tc_f0cdeccf, TypeS_3op>, Enc_645d54 {
25581let Inst{7-6} = 0b11;
25582let Inst{31-21} = 0b11000011110;
25583let prefersSlot3 = 1;
25584}
25585def S4_vrcrotate_acc : HInst<
25586(outs DoubleRegs:$Rxx32),
25587(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii),
25588"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)",
25589tc_a38c45dc, TypeS_3op>, Enc_b72622 {
25590let Inst{7-6} = 0b00;
25591let Inst{31-21} = 0b11001011101;
25592let prefersSlot3 = 1;
25593let Constraints = "$Rxx32 = $Rxx32in";
25594}
25595def S4_vxaddsubh : HInst<
25596(outs DoubleRegs:$Rdd32),
25597(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25598"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat",
25599tc_8a825db2, TypeS_3op>, Enc_a56825 {
25600let Inst{7-5} = 0b100;
25601let Inst{13-13} = 0b0;
25602let Inst{31-21} = 0b11000001010;
25603let prefersSlot3 = 1;
25604let Defs = [USR_OVF];
25605}
25606def S4_vxaddsubhr : HInst<
25607(outs DoubleRegs:$Rdd32),
25608(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25609"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat",
25610tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25611let Inst{7-5} = 0b000;
25612let Inst{13-13} = 0b0;
25613let Inst{31-21} = 0b11000001110;
25614let prefersSlot3 = 1;
25615let Defs = [USR_OVF];
25616}
25617def S4_vxaddsubw : HInst<
25618(outs DoubleRegs:$Rdd32),
25619(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25620"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat",
25621tc_8a825db2, TypeS_3op>, Enc_a56825 {
25622let Inst{7-5} = 0b000;
25623let Inst{13-13} = 0b0;
25624let Inst{31-21} = 0b11000001010;
25625let prefersSlot3 = 1;
25626let Defs = [USR_OVF];
25627}
25628def S4_vxsubaddh : HInst<
25629(outs DoubleRegs:$Rdd32),
25630(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25631"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat",
25632tc_8a825db2, TypeS_3op>, Enc_a56825 {
25633let Inst{7-5} = 0b110;
25634let Inst{13-13} = 0b0;
25635let Inst{31-21} = 0b11000001010;
25636let prefersSlot3 = 1;
25637let Defs = [USR_OVF];
25638}
25639def S4_vxsubaddhr : HInst<
25640(outs DoubleRegs:$Rdd32),
25641(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25642"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat",
25643tc_0dfac0a7, TypeS_3op>, Enc_a56825 {
25644let Inst{7-5} = 0b010;
25645let Inst{13-13} = 0b0;
25646let Inst{31-21} = 0b11000001110;
25647let prefersSlot3 = 1;
25648let Defs = [USR_OVF];
25649}
25650def S4_vxsubaddw : HInst<
25651(outs DoubleRegs:$Rdd32),
25652(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25653"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat",
25654tc_8a825db2, TypeS_3op>, Enc_a56825 {
25655let Inst{7-5} = 0b010;
25656let Inst{13-13} = 0b0;
25657let Inst{31-21} = 0b11000001010;
25658let prefersSlot3 = 1;
25659let Defs = [USR_OVF];
25660}
25661def S5_asrhub_rnd_sat : HInst<
25662(outs IntRegs:$Rd32),
25663(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25664"$Rd32 = vasrhub($Rss32,#$Ii):raw",
25665tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25666let Inst{7-5} = 0b100;
25667let Inst{13-12} = 0b00;
25668let Inst{31-21} = 0b10001000011;
25669let hasNewValue = 1;
25670let opNewValue = 0;
25671let prefersSlot3 = 1;
25672let Defs = [USR_OVF];
25673}
25674def S5_asrhub_rnd_sat_goodsyntax : HInst<
25675(outs IntRegs:$Rd32),
25676(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25677"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat",
25678tc_0dfac0a7, TypeS_2op> {
25679let hasNewValue = 1;
25680let opNewValue = 0;
25681let isPseudo = 1;
25682}
25683def S5_asrhub_sat : HInst<
25684(outs IntRegs:$Rd32),
25685(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25686"$Rd32 = vasrhub($Rss32,#$Ii):sat",
25687tc_0dfac0a7, TypeS_2op>, Enc_11a146 {
25688let Inst{7-5} = 0b101;
25689let Inst{13-12} = 0b00;
25690let Inst{31-21} = 0b10001000011;
25691let hasNewValue = 1;
25692let opNewValue = 0;
25693let prefersSlot3 = 1;
25694let Defs = [USR_OVF];
25695}
25696def S5_popcountp : HInst<
25697(outs IntRegs:$Rd32),
25698(ins DoubleRegs:$Rss32),
25699"$Rd32 = popcount($Rss32)",
25700tc_d3632d88, TypeS_2op>, Enc_90cd8b {
25701let Inst{13-5} = 0b000000011;
25702let Inst{31-21} = 0b10001000011;
25703let hasNewValue = 1;
25704let opNewValue = 0;
25705let prefersSlot3 = 1;
25706}
25707def S5_vasrhrnd : HInst<
25708(outs DoubleRegs:$Rdd32),
25709(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25710"$Rdd32 = vasrh($Rss32,#$Ii):raw",
25711tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 {
25712let Inst{7-5} = 0b000;
25713let Inst{13-12} = 0b00;
25714let Inst{31-21} = 0b10000000001;
25715let prefersSlot3 = 1;
25716}
25717def S5_vasrhrnd_goodsyntax : HInst<
25718(outs DoubleRegs:$Rdd32),
25719(ins DoubleRegs:$Rss32, u4_0Imm:$Ii),
25720"$Rdd32 = vasrh($Rss32,#$Ii):rnd",
25721tc_0dfac0a7, TypeS_2op> {
25722let isPseudo = 1;
25723}
25724def S6_allocframe_to_raw : HInst<
25725(outs),
25726(ins u11_3Imm:$Ii),
25727"allocframe(#$Ii)",
25728tc_934753bb, TypeMAPPING>, Requires<[HasV65]> {
25729let isPseudo = 1;
25730let isCodeGenOnly = 1;
25731}
25732def S6_rol_i_p : HInst<
25733(outs DoubleRegs:$Rdd32),
25734(ins DoubleRegs:$Rss32, u6_0Imm:$Ii),
25735"$Rdd32 = rol($Rss32,#$Ii)",
25736tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> {
25737let Inst{7-5} = 0b011;
25738let Inst{31-21} = 0b10000000000;
25739}
25740def S6_rol_i_p_acc : HInst<
25741(outs DoubleRegs:$Rxx32),
25742(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25743"$Rxx32 += rol($Rss32,#$Ii)",
25744tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25745let Inst{7-5} = 0b111;
25746let Inst{31-21} = 0b10000010000;
25747let prefersSlot3 = 1;
25748let Constraints = "$Rxx32 = $Rxx32in";
25749}
25750def S6_rol_i_p_and : HInst<
25751(outs DoubleRegs:$Rxx32),
25752(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25753"$Rxx32 &= rol($Rss32,#$Ii)",
25754tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25755let Inst{7-5} = 0b011;
25756let Inst{31-21} = 0b10000010010;
25757let prefersSlot3 = 1;
25758let Constraints = "$Rxx32 = $Rxx32in";
25759}
25760def S6_rol_i_p_nac : HInst<
25761(outs DoubleRegs:$Rxx32),
25762(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25763"$Rxx32 -= rol($Rss32,#$Ii)",
25764tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25765let Inst{7-5} = 0b011;
25766let Inst{31-21} = 0b10000010000;
25767let prefersSlot3 = 1;
25768let Constraints = "$Rxx32 = $Rxx32in";
25769}
25770def S6_rol_i_p_or : HInst<
25771(outs DoubleRegs:$Rxx32),
25772(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25773"$Rxx32 |= rol($Rss32,#$Ii)",
25774tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25775let Inst{7-5} = 0b111;
25776let Inst{31-21} = 0b10000010010;
25777let prefersSlot3 = 1;
25778let Constraints = "$Rxx32 = $Rxx32in";
25779}
25780def S6_rol_i_p_xacc : HInst<
25781(outs DoubleRegs:$Rxx32),
25782(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii),
25783"$Rxx32 ^= rol($Rss32,#$Ii)",
25784tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> {
25785let Inst{7-5} = 0b011;
25786let Inst{31-21} = 0b10000010100;
25787let prefersSlot3 = 1;
25788let Constraints = "$Rxx32 = $Rxx32in";
25789}
25790def S6_rol_i_r : HInst<
25791(outs IntRegs:$Rd32),
25792(ins IntRegs:$Rs32, u5_0Imm:$Ii),
25793"$Rd32 = rol($Rs32,#$Ii)",
25794tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> {
25795let Inst{7-5} = 0b011;
25796let Inst{13-13} = 0b0;
25797let Inst{31-21} = 0b10001100000;
25798let hasNewValue = 1;
25799let opNewValue = 0;
25800}
25801def S6_rol_i_r_acc : HInst<
25802(outs IntRegs:$Rx32),
25803(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25804"$Rx32 += rol($Rs32,#$Ii)",
25805tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25806let Inst{7-5} = 0b111;
25807let Inst{13-13} = 0b0;
25808let Inst{31-21} = 0b10001110000;
25809let hasNewValue = 1;
25810let opNewValue = 0;
25811let prefersSlot3 = 1;
25812let Constraints = "$Rx32 = $Rx32in";
25813}
25814def S6_rol_i_r_and : HInst<
25815(outs IntRegs:$Rx32),
25816(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25817"$Rx32 &= rol($Rs32,#$Ii)",
25818tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25819let Inst{7-5} = 0b011;
25820let Inst{13-13} = 0b0;
25821let Inst{31-21} = 0b10001110010;
25822let hasNewValue = 1;
25823let opNewValue = 0;
25824let prefersSlot3 = 1;
25825let Constraints = "$Rx32 = $Rx32in";
25826}
25827def S6_rol_i_r_nac : HInst<
25828(outs IntRegs:$Rx32),
25829(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25830"$Rx32 -= rol($Rs32,#$Ii)",
25831tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25832let Inst{7-5} = 0b011;
25833let Inst{13-13} = 0b0;
25834let Inst{31-21} = 0b10001110000;
25835let hasNewValue = 1;
25836let opNewValue = 0;
25837let prefersSlot3 = 1;
25838let Constraints = "$Rx32 = $Rx32in";
25839}
25840def S6_rol_i_r_or : HInst<
25841(outs IntRegs:$Rx32),
25842(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25843"$Rx32 |= rol($Rs32,#$Ii)",
25844tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25845let Inst{7-5} = 0b111;
25846let Inst{13-13} = 0b0;
25847let Inst{31-21} = 0b10001110010;
25848let hasNewValue = 1;
25849let opNewValue = 0;
25850let prefersSlot3 = 1;
25851let Constraints = "$Rx32 = $Rx32in";
25852}
25853def S6_rol_i_r_xacc : HInst<
25854(outs IntRegs:$Rx32),
25855(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii),
25856"$Rx32 ^= rol($Rs32,#$Ii)",
25857tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> {
25858let Inst{7-5} = 0b011;
25859let Inst{13-13} = 0b0;
25860let Inst{31-21} = 0b10001110100;
25861let hasNewValue = 1;
25862let opNewValue = 0;
25863let prefersSlot3 = 1;
25864let Constraints = "$Rx32 = $Rx32in";
25865}
25866def S6_vsplatrbp : HInst<
25867(outs DoubleRegs:$Rdd32),
25868(ins IntRegs:$Rs32),
25869"$Rdd32 = vsplatb($Rs32)",
25870tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> {
25871let Inst{13-5} = 0b000000100;
25872let Inst{31-21} = 0b10000100010;
25873}
25874def S6_vtrunehb_ppp : HInst<
25875(outs DoubleRegs:$Rdd32),
25876(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25877"$Rdd32 = vtrunehb($Rss32,$Rtt32)",
25878tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25879let Inst{7-5} = 0b011;
25880let Inst{13-13} = 0b0;
25881let Inst{31-21} = 0b11000001100;
25882}
25883def S6_vtrunohb_ppp : HInst<
25884(outs DoubleRegs:$Rdd32),
25885(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
25886"$Rdd32 = vtrunohb($Rss32,$Rtt32)",
25887tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> {
25888let Inst{7-5} = 0b101;
25889let Inst{13-13} = 0b0;
25890let Inst{31-21} = 0b11000001100;
25891}
25892def SA1_addi : HInst<
25893(outs GeneralSubRegs:$Rx16),
25894(ins GeneralSubRegs:$Rx16in, s32_0Imm:$Ii),
25895"$Rx16 = add($Rx16in,#$Ii)",
25896tc_5b347363, TypeSUBINSN>, Enc_93af4c {
25897let Inst{12-11} = 0b00;
25898let hasNewValue = 1;
25899let opNewValue = 0;
25900let AsmVariantName = "NonParsable";
25901let DecoderNamespace = "SUBINSN_A";
25902let isExtendable = 1;
25903let opExtendable = 2;
25904let isExtentSigned = 1;
25905let opExtentBits = 7;
25906let opExtentAlign = 0;
25907let Constraints = "$Rx16 = $Rx16in";
25908}
25909def SA1_addrx : HInst<
25910(outs GeneralSubRegs:$Rx16),
25911(ins GeneralSubRegs:$Rx16in, GeneralSubRegs:$Rs16),
25912"$Rx16 = add($Rx16in,$Rs16)",
25913tc_5b347363, TypeSUBINSN>, Enc_0527db {
25914let Inst{12-8} = 0b11000;
25915let hasNewValue = 1;
25916let opNewValue = 0;
25917let AsmVariantName = "NonParsable";
25918let DecoderNamespace = "SUBINSN_A";
25919let Constraints = "$Rx16 = $Rx16in";
25920}
25921def SA1_addsp : HInst<
25922(outs GeneralSubRegs:$Rd16),
25923(ins u6_2Imm:$Ii),
25924"$Rd16 = add(r29,#$Ii)",
25925tc_3d14a17b, TypeSUBINSN>, Enc_2df31d {
25926let Inst{12-10} = 0b011;
25927let hasNewValue = 1;
25928let opNewValue = 0;
25929let AsmVariantName = "NonParsable";
25930let Uses = [R29];
25931let DecoderNamespace = "SUBINSN_A";
25932}
25933def SA1_and1 : HInst<
25934(outs GeneralSubRegs:$Rd16),
25935(ins GeneralSubRegs:$Rs16),
25936"$Rd16 = and($Rs16,#1)",
25937tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
25938let Inst{12-8} = 0b10010;
25939let hasNewValue = 1;
25940let opNewValue = 0;
25941let AsmVariantName = "NonParsable";
25942let DecoderNamespace = "SUBINSN_A";
25943}
25944def SA1_clrf : HInst<
25945(outs GeneralSubRegs:$Rd16),
25946(ins),
25947"if (!p0) $Rd16 = #0",
25948tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25949let Inst{12-4} = 0b110100111;
25950let isPredicated = 1;
25951let isPredicatedFalse = 1;
25952let hasNewValue = 1;
25953let opNewValue = 0;
25954let AsmVariantName = "NonParsable";
25955let Uses = [P0];
25956let DecoderNamespace = "SUBINSN_A";
25957}
25958def SA1_clrfnew : HInst<
25959(outs GeneralSubRegs:$Rd16),
25960(ins),
25961"if (!p0.new) $Rd16 = #0",
25962tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25963let Inst{12-4} = 0b110100101;
25964let isPredicated = 1;
25965let isPredicatedFalse = 1;
25966let hasNewValue = 1;
25967let opNewValue = 0;
25968let AsmVariantName = "NonParsable";
25969let isPredicatedNew = 1;
25970let Uses = [P0];
25971let DecoderNamespace = "SUBINSN_A";
25972}
25973def SA1_clrt : HInst<
25974(outs GeneralSubRegs:$Rd16),
25975(ins),
25976"if (p0) $Rd16 = #0",
25977tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 {
25978let Inst{12-4} = 0b110100110;
25979let isPredicated = 1;
25980let hasNewValue = 1;
25981let opNewValue = 0;
25982let AsmVariantName = "NonParsable";
25983let Uses = [P0];
25984let DecoderNamespace = "SUBINSN_A";
25985}
25986def SA1_clrtnew : HInst<
25987(outs GeneralSubRegs:$Rd16),
25988(ins),
25989"if (p0.new) $Rd16 = #0",
25990tc_63567288, TypeSUBINSN>, Enc_1f5ba6 {
25991let Inst{12-4} = 0b110100100;
25992let isPredicated = 1;
25993let hasNewValue = 1;
25994let opNewValue = 0;
25995let AsmVariantName = "NonParsable";
25996let isPredicatedNew = 1;
25997let Uses = [P0];
25998let DecoderNamespace = "SUBINSN_A";
25999}
26000def SA1_cmpeqi : HInst<
26001(outs),
26002(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii),
26003"p0 = cmp.eq($Rs16,#$Ii)",
26004tc_59a7822c, TypeSUBINSN>, Enc_63eaeb {
26005let Inst{3-2} = 0b00;
26006let Inst{12-8} = 0b11001;
26007let AsmVariantName = "NonParsable";
26008let Defs = [P0];
26009let DecoderNamespace = "SUBINSN_A";
26010}
26011def SA1_combine0i : HInst<
26012(outs GeneralDoubleLow8Regs:$Rdd8),
26013(ins u2_0Imm:$Ii),
26014"$Rdd8 = combine(#0,#$Ii)",
26015tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26016let Inst{4-3} = 0b00;
26017let Inst{12-7} = 0b111000;
26018let hasNewValue = 1;
26019let opNewValue = 0;
26020let AsmVariantName = "NonParsable";
26021let DecoderNamespace = "SUBINSN_A";
26022}
26023def SA1_combine1i : HInst<
26024(outs GeneralDoubleLow8Regs:$Rdd8),
26025(ins u2_0Imm:$Ii),
26026"$Rdd8 = combine(#1,#$Ii)",
26027tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26028let Inst{4-3} = 0b01;
26029let Inst{12-7} = 0b111000;
26030let hasNewValue = 1;
26031let opNewValue = 0;
26032let AsmVariantName = "NonParsable";
26033let DecoderNamespace = "SUBINSN_A";
26034}
26035def SA1_combine2i : HInst<
26036(outs GeneralDoubleLow8Regs:$Rdd8),
26037(ins u2_0Imm:$Ii),
26038"$Rdd8 = combine(#2,#$Ii)",
26039tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26040let Inst{4-3} = 0b10;
26041let Inst{12-7} = 0b111000;
26042let hasNewValue = 1;
26043let opNewValue = 0;
26044let AsmVariantName = "NonParsable";
26045let DecoderNamespace = "SUBINSN_A";
26046}
26047def SA1_combine3i : HInst<
26048(outs GeneralDoubleLow8Regs:$Rdd8),
26049(ins u2_0Imm:$Ii),
26050"$Rdd8 = combine(#3,#$Ii)",
26051tc_3d14a17b, TypeSUBINSN>, Enc_ed48be {
26052let Inst{4-3} = 0b11;
26053let Inst{12-7} = 0b111000;
26054let hasNewValue = 1;
26055let opNewValue = 0;
26056let AsmVariantName = "NonParsable";
26057let DecoderNamespace = "SUBINSN_A";
26058}
26059def SA1_combinerz : HInst<
26060(outs GeneralDoubleLow8Regs:$Rdd8),
26061(ins GeneralSubRegs:$Rs16),
26062"$Rdd8 = combine($Rs16,#0)",
26063tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26064let Inst{3-3} = 0b1;
26065let Inst{12-8} = 0b11101;
26066let hasNewValue = 1;
26067let opNewValue = 0;
26068let AsmVariantName = "NonParsable";
26069let DecoderNamespace = "SUBINSN_A";
26070}
26071def SA1_combinezr : HInst<
26072(outs GeneralDoubleLow8Regs:$Rdd8),
26073(ins GeneralSubRegs:$Rs16),
26074"$Rdd8 = combine(#0,$Rs16)",
26075tc_3d14a17b, TypeSUBINSN>, Enc_399e12 {
26076let Inst{3-3} = 0b0;
26077let Inst{12-8} = 0b11101;
26078let hasNewValue = 1;
26079let opNewValue = 0;
26080let AsmVariantName = "NonParsable";
26081let DecoderNamespace = "SUBINSN_A";
26082}
26083def SA1_dec : HInst<
26084(outs GeneralSubRegs:$Rd16),
26085(ins GeneralSubRegs:$Rs16, n1Const:$n1),
26086"$Rd16 = add($Rs16,#$n1)",
26087tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 {
26088let Inst{12-8} = 0b10011;
26089let hasNewValue = 1;
26090let opNewValue = 0;
26091let AsmVariantName = "NonParsable";
26092let DecoderNamespace = "SUBINSN_A";
26093}
26094def SA1_inc : HInst<
26095(outs GeneralSubRegs:$Rd16),
26096(ins GeneralSubRegs:$Rs16),
26097"$Rd16 = add($Rs16,#1)",
26098tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26099let Inst{12-8} = 0b10001;
26100let hasNewValue = 1;
26101let opNewValue = 0;
26102let AsmVariantName = "NonParsable";
26103let DecoderNamespace = "SUBINSN_A";
26104}
26105def SA1_seti : HInst<
26106(outs GeneralSubRegs:$Rd16),
26107(ins u32_0Imm:$Ii),
26108"$Rd16 = #$Ii",
26109tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 {
26110let Inst{12-10} = 0b010;
26111let hasNewValue = 1;
26112let opNewValue = 0;
26113let AsmVariantName = "NonParsable";
26114let DecoderNamespace = "SUBINSN_A";
26115let isExtendable = 1;
26116let opExtendable = 1;
26117let isExtentSigned = 0;
26118let opExtentBits = 6;
26119let opExtentAlign = 0;
26120}
26121def SA1_setin1 : HInst<
26122(outs GeneralSubRegs:$Rd16),
26123(ins n1Const:$n1),
26124"$Rd16 = #$n1",
26125tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 {
26126let Inst{12-4} = 0b110100000;
26127let hasNewValue = 1;
26128let opNewValue = 0;
26129let AsmVariantName = "NonParsable";
26130let DecoderNamespace = "SUBINSN_A";
26131}
26132def SA1_sxtb : HInst<
26133(outs GeneralSubRegs:$Rd16),
26134(ins GeneralSubRegs:$Rs16),
26135"$Rd16 = sxtb($Rs16)",
26136tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26137let Inst{12-8} = 0b10101;
26138let hasNewValue = 1;
26139let opNewValue = 0;
26140let AsmVariantName = "NonParsable";
26141let DecoderNamespace = "SUBINSN_A";
26142}
26143def SA1_sxth : HInst<
26144(outs GeneralSubRegs:$Rd16),
26145(ins GeneralSubRegs:$Rs16),
26146"$Rd16 = sxth($Rs16)",
26147tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26148let Inst{12-8} = 0b10100;
26149let hasNewValue = 1;
26150let opNewValue = 0;
26151let AsmVariantName = "NonParsable";
26152let DecoderNamespace = "SUBINSN_A";
26153}
26154def SA1_tfr : HInst<
26155(outs GeneralSubRegs:$Rd16),
26156(ins GeneralSubRegs:$Rs16),
26157"$Rd16 = $Rs16",
26158tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26159let Inst{12-8} = 0b10000;
26160let hasNewValue = 1;
26161let opNewValue = 0;
26162let AsmVariantName = "NonParsable";
26163let DecoderNamespace = "SUBINSN_A";
26164}
26165def SA1_zxtb : HInst<
26166(outs GeneralSubRegs:$Rd16),
26167(ins GeneralSubRegs:$Rs16),
26168"$Rd16 = and($Rs16,#255)",
26169tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26170let Inst{12-8} = 0b10111;
26171let hasNewValue = 1;
26172let opNewValue = 0;
26173let AsmVariantName = "NonParsable";
26174let DecoderNamespace = "SUBINSN_A";
26175}
26176def SA1_zxth : HInst<
26177(outs GeneralSubRegs:$Rd16),
26178(ins GeneralSubRegs:$Rs16),
26179"$Rd16 = zxth($Rs16)",
26180tc_3d14a17b, TypeSUBINSN>, Enc_97d666 {
26181let Inst{12-8} = 0b10110;
26182let hasNewValue = 1;
26183let opNewValue = 0;
26184let AsmVariantName = "NonParsable";
26185let DecoderNamespace = "SUBINSN_A";
26186}
26187def SL1_loadri_io : HInst<
26188(outs GeneralSubRegs:$Rd16),
26189(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26190"$Rd16 = memw($Rs16+#$Ii)",
26191tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 {
26192let Inst{12-12} = 0b0;
26193let hasNewValue = 1;
26194let opNewValue = 0;
26195let addrMode = BaseImmOffset;
26196let accessSize = WordAccess;
26197let AsmVariantName = "NonParsable";
26198let mayLoad = 1;
26199let DecoderNamespace = "SUBINSN_L1";
26200}
26201def SL1_loadrub_io : HInst<
26202(outs GeneralSubRegs:$Rd16),
26203(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26204"$Rd16 = memub($Rs16+#$Ii)",
26205tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 {
26206let Inst{12-12} = 0b1;
26207let hasNewValue = 1;
26208let opNewValue = 0;
26209let addrMode = BaseImmOffset;
26210let accessSize = ByteAccess;
26211let AsmVariantName = "NonParsable";
26212let mayLoad = 1;
26213let DecoderNamespace = "SUBINSN_L1";
26214}
26215def SL2_deallocframe : HInst<
26216(outs),
26217(ins),
26218"deallocframe",
26219tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 {
26220let Inst{12-0} = 0b1111100000000;
26221let accessSize = DoubleWordAccess;
26222let AsmVariantName = "NonParsable";
26223let mayLoad = 1;
26224let Uses = [FRAMEKEY, R30];
26225let Defs = [R29, R30, R31];
26226let DecoderNamespace = "SUBINSN_L2";
26227}
26228def SL2_jumpr31 : HInst<
26229(outs),
26230(ins),
26231"jumpr r31",
26232tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26233let Inst{12-0} = 0b1111111000000;
26234let isTerminator = 1;
26235let isIndirectBranch = 1;
26236let AsmVariantName = "NonParsable";
26237let cofMax1 = 1;
26238let isReturn = 1;
26239let Uses = [R31];
26240let Defs = [PC];
26241let DecoderNamespace = "SUBINSN_L2";
26242}
26243def SL2_jumpr31_f : HInst<
26244(outs),
26245(ins),
26246"if (!p0) jumpr r31",
26247tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26248let Inst{12-0} = 0b1111111000101;
26249let isPredicated = 1;
26250let isPredicatedFalse = 1;
26251let isTerminator = 1;
26252let isIndirectBranch = 1;
26253let AsmVariantName = "NonParsable";
26254let cofMax1 = 1;
26255let isReturn = 1;
26256let Uses = [P0, R31];
26257let Defs = [PC];
26258let isTaken = Inst{4};
26259let DecoderNamespace = "SUBINSN_L2";
26260}
26261def SL2_jumpr31_fnew : HInst<
26262(outs),
26263(ins),
26264"if (!p0.new) jumpr:nt r31",
26265tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26266let Inst{12-0} = 0b1111111000111;
26267let isPredicated = 1;
26268let isPredicatedFalse = 1;
26269let isTerminator = 1;
26270let isIndirectBranch = 1;
26271let AsmVariantName = "NonParsable";
26272let isPredicatedNew = 1;
26273let cofMax1 = 1;
26274let isReturn = 1;
26275let Uses = [P0, R31];
26276let Defs = [PC];
26277let isTaken = Inst{4};
26278let DecoderNamespace = "SUBINSN_L2";
26279}
26280def SL2_jumpr31_t : HInst<
26281(outs),
26282(ins),
26283"if (p0) jumpr r31",
26284tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26285let Inst{12-0} = 0b1111111000100;
26286let isPredicated = 1;
26287let isTerminator = 1;
26288let isIndirectBranch = 1;
26289let AsmVariantName = "NonParsable";
26290let cofMax1 = 1;
26291let isReturn = 1;
26292let Uses = [P0, R31];
26293let Defs = [PC];
26294let isTaken = Inst{4};
26295let DecoderNamespace = "SUBINSN_L2";
26296}
26297def SL2_jumpr31_tnew : HInst<
26298(outs),
26299(ins),
26300"if (p0.new) jumpr:nt r31",
26301tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 {
26302let Inst{12-0} = 0b1111111000110;
26303let isPredicated = 1;
26304let isTerminator = 1;
26305let isIndirectBranch = 1;
26306let AsmVariantName = "NonParsable";
26307let isPredicatedNew = 1;
26308let cofMax1 = 1;
26309let isReturn = 1;
26310let Uses = [P0, R31];
26311let Defs = [PC];
26312let isTaken = Inst{4};
26313let DecoderNamespace = "SUBINSN_L2";
26314}
26315def SL2_loadrb_io : HInst<
26316(outs GeneralSubRegs:$Rd16),
26317(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii),
26318"$Rd16 = memb($Rs16+#$Ii)",
26319tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c {
26320let Inst{12-11} = 0b10;
26321let hasNewValue = 1;
26322let opNewValue = 0;
26323let addrMode = BaseImmOffset;
26324let accessSize = ByteAccess;
26325let AsmVariantName = "NonParsable";
26326let mayLoad = 1;
26327let DecoderNamespace = "SUBINSN_L2";
26328}
26329def SL2_loadrd_sp : HInst<
26330(outs GeneralDoubleLow8Regs:$Rdd8),
26331(ins u5_3Imm:$Ii),
26332"$Rdd8 = memd(r29+#$Ii)",
26333tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b {
26334let Inst{12-8} = 0b11110;
26335let hasNewValue = 1;
26336let opNewValue = 0;
26337let addrMode = BaseImmOffset;
26338let accessSize = DoubleWordAccess;
26339let AsmVariantName = "NonParsable";
26340let mayLoad = 1;
26341let Uses = [R29];
26342let DecoderNamespace = "SUBINSN_L2";
26343}
26344def SL2_loadrh_io : HInst<
26345(outs GeneralSubRegs:$Rd16),
26346(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26347"$Rd16 = memh($Rs16+#$Ii)",
26348tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26349let Inst{12-11} = 0b00;
26350let hasNewValue = 1;
26351let opNewValue = 0;
26352let addrMode = BaseImmOffset;
26353let accessSize = HalfWordAccess;
26354let AsmVariantName = "NonParsable";
26355let mayLoad = 1;
26356let DecoderNamespace = "SUBINSN_L2";
26357}
26358def SL2_loadri_sp : HInst<
26359(outs GeneralSubRegs:$Rd16),
26360(ins u5_2Imm:$Ii),
26361"$Rd16 = memw(r29+#$Ii)",
26362tc_8a6d0d94, TypeSUBINSN>, Enc_51635c {
26363let Inst{12-9} = 0b1110;
26364let hasNewValue = 1;
26365let opNewValue = 0;
26366let addrMode = BaseImmOffset;
26367let accessSize = WordAccess;
26368let AsmVariantName = "NonParsable";
26369let mayLoad = 1;
26370let Uses = [R29];
26371let DecoderNamespace = "SUBINSN_L2";
26372}
26373def SL2_loadruh_io : HInst<
26374(outs GeneralSubRegs:$Rd16),
26375(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii),
26376"$Rd16 = memuh($Rs16+#$Ii)",
26377tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 {
26378let Inst{12-11} = 0b01;
26379let hasNewValue = 1;
26380let opNewValue = 0;
26381let addrMode = BaseImmOffset;
26382let accessSize = HalfWordAccess;
26383let AsmVariantName = "NonParsable";
26384let mayLoad = 1;
26385let DecoderNamespace = "SUBINSN_L2";
26386}
26387def SL2_return : HInst<
26388(outs),
26389(ins),
26390"dealloc_return",
26391tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26392let Inst{12-0} = 0b1111101000000;
26393let isTerminator = 1;
26394let isIndirectBranch = 1;
26395let accessSize = DoubleWordAccess;
26396let AsmVariantName = "NonParsable";
26397let mayLoad = 1;
26398let cofMax1 = 1;
26399let isRestrictNoSlot1Store = 1;
26400let isReturn = 1;
26401let Uses = [FRAMEKEY, R30];
26402let Defs = [PC, R29, R30, R31];
26403let DecoderNamespace = "SUBINSN_L2";
26404}
26405def SL2_return_f : HInst<
26406(outs),
26407(ins),
26408"if (!p0) dealloc_return",
26409tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26410let Inst{12-0} = 0b1111101000101;
26411let isPredicated = 1;
26412let isPredicatedFalse = 1;
26413let isTerminator = 1;
26414let isIndirectBranch = 1;
26415let accessSize = DoubleWordAccess;
26416let AsmVariantName = "NonParsable";
26417let mayLoad = 1;
26418let cofMax1 = 1;
26419let isRestrictNoSlot1Store = 1;
26420let isReturn = 1;
26421let Uses = [FRAMEKEY, P0, R30];
26422let Defs = [PC, R29, R30, R31];
26423let isTaken = Inst{4};
26424let DecoderNamespace = "SUBINSN_L2";
26425}
26426def SL2_return_fnew : HInst<
26427(outs),
26428(ins),
26429"if (!p0.new) dealloc_return:nt",
26430tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26431let Inst{12-0} = 0b1111101000111;
26432let isPredicated = 1;
26433let isPredicatedFalse = 1;
26434let isTerminator = 1;
26435let isIndirectBranch = 1;
26436let accessSize = DoubleWordAccess;
26437let AsmVariantName = "NonParsable";
26438let isPredicatedNew = 1;
26439let mayLoad = 1;
26440let cofMax1 = 1;
26441let isRestrictNoSlot1Store = 1;
26442let isReturn = 1;
26443let Uses = [FRAMEKEY, P0, R30];
26444let Defs = [PC, R29, R30, R31];
26445let isTaken = Inst{4};
26446let DecoderNamespace = "SUBINSN_L2";
26447}
26448def SL2_return_t : HInst<
26449(outs),
26450(ins),
26451"if (p0) dealloc_return",
26452tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26453let Inst{12-0} = 0b1111101000100;
26454let isPredicated = 1;
26455let isTerminator = 1;
26456let isIndirectBranch = 1;
26457let accessSize = DoubleWordAccess;
26458let AsmVariantName = "NonParsable";
26459let mayLoad = 1;
26460let cofMax1 = 1;
26461let isRestrictNoSlot1Store = 1;
26462let isReturn = 1;
26463let Uses = [FRAMEKEY, P0, R30];
26464let Defs = [PC, R29, R30, R31];
26465let isTaken = Inst{4};
26466let DecoderNamespace = "SUBINSN_L2";
26467}
26468def SL2_return_tnew : HInst<
26469(outs),
26470(ins),
26471"if (p0.new) dealloc_return:nt",
26472tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 {
26473let Inst{12-0} = 0b1111101000110;
26474let isPredicated = 1;
26475let isTerminator = 1;
26476let isIndirectBranch = 1;
26477let accessSize = DoubleWordAccess;
26478let AsmVariantName = "NonParsable";
26479let isPredicatedNew = 1;
26480let mayLoad = 1;
26481let cofMax1 = 1;
26482let isRestrictNoSlot1Store = 1;
26483let isReturn = 1;
26484let Uses = [FRAMEKEY, P0, R30];
26485let Defs = [PC, R29, R30, R31];
26486let isTaken = Inst{4};
26487let DecoderNamespace = "SUBINSN_L2";
26488}
26489def SS1_storeb_io : HInst<
26490(outs),
26491(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16),
26492"memb($Rs16+#$Ii) = $Rt16",
26493tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc {
26494let Inst{12-12} = 0b1;
26495let addrMode = BaseImmOffset;
26496let accessSize = ByteAccess;
26497let AsmVariantName = "NonParsable";
26498let mayStore = 1;
26499let DecoderNamespace = "SUBINSN_S1";
26500}
26501def SS1_storew_io : HInst<
26502(outs),
26503(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16),
26504"memw($Rs16+#$Ii) = $Rt16",
26505tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c {
26506let Inst{12-12} = 0b0;
26507let addrMode = BaseImmOffset;
26508let accessSize = WordAccess;
26509let AsmVariantName = "NonParsable";
26510let mayStore = 1;
26511let DecoderNamespace = "SUBINSN_S1";
26512}
26513def SS2_allocframe : HInst<
26514(outs),
26515(ins u5_3Imm:$Ii),
26516"allocframe(#$Ii)",
26517tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca {
26518let Inst{3-0} = 0b0000;
26519let Inst{12-9} = 0b1110;
26520let addrMode = BaseImmOffset;
26521let accessSize = DoubleWordAccess;
26522let AsmVariantName = "NonParsable";
26523let mayStore = 1;
26524let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31];
26525let Defs = [R29, R30];
26526let DecoderNamespace = "SUBINSN_S2";
26527}
26528def SS2_storebi0 : HInst<
26529(outs),
26530(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26531"memb($Rs16+#$Ii) = #0",
26532tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26533let Inst{12-8} = 0b10010;
26534let addrMode = BaseImmOffset;
26535let accessSize = ByteAccess;
26536let AsmVariantName = "NonParsable";
26537let mayStore = 1;
26538let DecoderNamespace = "SUBINSN_S2";
26539}
26540def SS2_storebi1 : HInst<
26541(outs),
26542(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii),
26543"memb($Rs16+#$Ii) = #1",
26544tc_44d5a428, TypeSUBINSN>, Enc_84d359 {
26545let Inst{12-8} = 0b10011;
26546let addrMode = BaseImmOffset;
26547let accessSize = ByteAccess;
26548let AsmVariantName = "NonParsable";
26549let mayStore = 1;
26550let DecoderNamespace = "SUBINSN_S2";
26551}
26552def SS2_stored_sp : HInst<
26553(outs),
26554(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8),
26555"memd(r29+#$Ii) = $Rtt8",
26556tc_0655b949, TypeSUBINSN>, Enc_b8309d {
26557let Inst{12-9} = 0b0101;
26558let addrMode = BaseImmOffset;
26559let accessSize = DoubleWordAccess;
26560let AsmVariantName = "NonParsable";
26561let mayStore = 1;
26562let Uses = [R29];
26563let DecoderNamespace = "SUBINSN_S2";
26564}
26565def SS2_storeh_io : HInst<
26566(outs),
26567(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16),
26568"memh($Rs16+#$Ii) = $Rt16",
26569tc_ae5babd7, TypeSUBINSN>, Enc_625deb {
26570let Inst{12-11} = 0b00;
26571let addrMode = BaseImmOffset;
26572let accessSize = HalfWordAccess;
26573let AsmVariantName = "NonParsable";
26574let mayStore = 1;
26575let DecoderNamespace = "SUBINSN_S2";
26576}
26577def SS2_storew_sp : HInst<
26578(outs),
26579(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16),
26580"memw(r29+#$Ii) = $Rt16",
26581tc_0655b949, TypeSUBINSN>, Enc_87c142 {
26582let Inst{12-9} = 0b0100;
26583let addrMode = BaseImmOffset;
26584let accessSize = WordAccess;
26585let AsmVariantName = "NonParsable";
26586let mayStore = 1;
26587let Uses = [R29];
26588let DecoderNamespace = "SUBINSN_S2";
26589}
26590def SS2_storewi0 : HInst<
26591(outs),
26592(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26593"memw($Rs16+#$Ii) = #0",
26594tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26595let Inst{12-8} = 0b10000;
26596let addrMode = BaseImmOffset;
26597let accessSize = WordAccess;
26598let AsmVariantName = "NonParsable";
26599let mayStore = 1;
26600let DecoderNamespace = "SUBINSN_S2";
26601}
26602def SS2_storewi1 : HInst<
26603(outs),
26604(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii),
26605"memw($Rs16+#$Ii) = #1",
26606tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c {
26607let Inst{12-8} = 0b10001;
26608let addrMode = BaseImmOffset;
26609let accessSize = WordAccess;
26610let AsmVariantName = "NonParsable";
26611let mayStore = 1;
26612let DecoderNamespace = "SUBINSN_S2";
26613}
26614def V6_MAP_equb : HInst<
26615(outs HvxQR:$Qd4),
26616(ins HvxVR:$Vu32, HvxVR:$Vv32),
26617"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)",
26618PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26619let hasNewValue = 1;
26620let opNewValue = 0;
26621let isCVI = 1;
26622let isPseudo = 1;
26623let isCodeGenOnly = 1;
26624let DecoderNamespace = "EXT_mmvec";
26625}
26626def V6_MAP_equb_and : HInst<
26627(outs HvxQR:$Qx4),
26628(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26629"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)",
26630PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26631let isCVI = 1;
26632let isPseudo = 1;
26633let isCodeGenOnly = 1;
26634let DecoderNamespace = "EXT_mmvec";
26635let Constraints = "$Qx4 = $Qx4in";
26636}
26637def V6_MAP_equb_ior : HInst<
26638(outs HvxQR:$Qx4),
26639(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26640"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)",
26641PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26642let isAccumulator = 1;
26643let isCVI = 1;
26644let isPseudo = 1;
26645let isCodeGenOnly = 1;
26646let DecoderNamespace = "EXT_mmvec";
26647let Constraints = "$Qx4 = $Qx4in";
26648}
26649def V6_MAP_equb_xor : HInst<
26650(outs HvxQR:$Qx4),
26651(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26652"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)",
26653PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26654let isCVI = 1;
26655let isPseudo = 1;
26656let isCodeGenOnly = 1;
26657let DecoderNamespace = "EXT_mmvec";
26658let Constraints = "$Qx4 = $Qx4in";
26659}
26660def V6_MAP_equh : HInst<
26661(outs HvxQR:$Qd4),
26662(ins HvxVR:$Vu32, HvxVR:$Vv32),
26663"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)",
26664PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26665let hasNewValue = 1;
26666let opNewValue = 0;
26667let isCVI = 1;
26668let isPseudo = 1;
26669let isCodeGenOnly = 1;
26670let DecoderNamespace = "EXT_mmvec";
26671}
26672def V6_MAP_equh_and : HInst<
26673(outs HvxQR:$Qx4),
26674(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26675"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)",
26676PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26677let isCVI = 1;
26678let isPseudo = 1;
26679let isCodeGenOnly = 1;
26680let DecoderNamespace = "EXT_mmvec";
26681let Constraints = "$Qx4 = $Qx4in";
26682}
26683def V6_MAP_equh_ior : HInst<
26684(outs HvxQR:$Qx4),
26685(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26686"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)",
26687PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26688let isAccumulator = 1;
26689let isCVI = 1;
26690let isPseudo = 1;
26691let isCodeGenOnly = 1;
26692let DecoderNamespace = "EXT_mmvec";
26693let Constraints = "$Qx4 = $Qx4in";
26694}
26695def V6_MAP_equh_xor : HInst<
26696(outs HvxQR:$Qx4),
26697(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26698"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)",
26699PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26700let isCVI = 1;
26701let isPseudo = 1;
26702let isCodeGenOnly = 1;
26703let DecoderNamespace = "EXT_mmvec";
26704let Constraints = "$Qx4 = $Qx4in";
26705}
26706def V6_MAP_equw : HInst<
26707(outs HvxQR:$Qd4),
26708(ins HvxVR:$Vu32, HvxVR:$Vv32),
26709"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)",
26710PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26711let hasNewValue = 1;
26712let opNewValue = 0;
26713let isCVI = 1;
26714let isPseudo = 1;
26715let isCodeGenOnly = 1;
26716let DecoderNamespace = "EXT_mmvec";
26717}
26718def V6_MAP_equw_and : HInst<
26719(outs HvxQR:$Qx4),
26720(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26721"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)",
26722PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26723let isCVI = 1;
26724let isPseudo = 1;
26725let isCodeGenOnly = 1;
26726let DecoderNamespace = "EXT_mmvec";
26727let Constraints = "$Qx4 = $Qx4in";
26728}
26729def V6_MAP_equw_ior : HInst<
26730(outs HvxQR:$Qx4),
26731(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26732"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)",
26733PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26734let isAccumulator = 1;
26735let isCVI = 1;
26736let isPseudo = 1;
26737let isCodeGenOnly = 1;
26738let DecoderNamespace = "EXT_mmvec";
26739let Constraints = "$Qx4 = $Qx4in";
26740}
26741def V6_MAP_equw_xor : HInst<
26742(outs HvxQR:$Qx4),
26743(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
26744"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)",
26745PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26746let isCVI = 1;
26747let isPseudo = 1;
26748let isCodeGenOnly = 1;
26749let DecoderNamespace = "EXT_mmvec";
26750let Constraints = "$Qx4 = $Qx4in";
26751}
26752def V6_extractw : HInst<
26753(outs IntRegs:$Rd32),
26754(ins HvxVR:$Vu32, IntRegs:$Rs32),
26755"$Rd32 = vextract($Vu32,$Rs32)",
26756tc_540c3da3, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> {
26757let Inst{7-5} = 0b001;
26758let Inst{13-13} = 0b0;
26759let Inst{31-21} = 0b10010010000;
26760let hasNewValue = 1;
26761let opNewValue = 0;
26762let isCVI = 1;
26763let isSolo = 1;
26764let mayLoad = 1;
26765let DecoderNamespace = "EXT_mmvec";
26766}
26767def V6_extractw_alt : HInst<
26768(outs IntRegs:$Rd32),
26769(ins HvxVR:$Vu32, IntRegs:$Rs32),
26770"$Rd32.w = vextract($Vu32,$Rs32)",
26771PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
26772let hasNewValue = 1;
26773let opNewValue = 0;
26774let isCVI = 1;
26775let isPseudo = 1;
26776let isCodeGenOnly = 1;
26777let DecoderNamespace = "EXT_mmvec";
26778}
26779def V6_hi : HInst<
26780(outs HvxVR:$Vd32),
26781(ins HvxWR:$Vss32),
26782"$Vd32 = hi($Vss32)",
26783CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26784let hasNewValue = 1;
26785let opNewValue = 0;
26786let isCVI = 1;
26787let isPseudo = 1;
26788let DecoderNamespace = "EXT_mmvec";
26789}
26790def V6_ld0 : HInst<
26791(outs HvxVR:$Vd32),
26792(ins IntRegs:$Rt32),
26793"$Vd32 = vmem($Rt32)",
26794PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26795let hasNewValue = 1;
26796let opNewValue = 0;
26797let isCVI = 1;
26798let isPseudo = 1;
26799let isCodeGenOnly = 1;
26800let DecoderNamespace = "EXT_mmvec";
26801}
26802def V6_ldcnp0 : HInst<
26803(outs HvxVR:$Vd32),
26804(ins PredRegs:$Pv4, IntRegs:$Rt32),
26805"if (!$Pv4) $Vd32.cur = vmem($Rt32)",
26806PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26807let hasNewValue = 1;
26808let opNewValue = 0;
26809let isCVI = 1;
26810let isPseudo = 1;
26811let isCodeGenOnly = 1;
26812let DecoderNamespace = "EXT_mmvec";
26813}
26814def V6_ldcnpnt0 : HInst<
26815(outs HvxVR:$Vd32),
26816(ins PredRegs:$Pv4, IntRegs:$Rt32),
26817"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt",
26818PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26819let hasNewValue = 1;
26820let opNewValue = 0;
26821let isCVI = 1;
26822let isPseudo = 1;
26823let isCodeGenOnly = 1;
26824let DecoderNamespace = "EXT_mmvec";
26825}
26826def V6_ldcp0 : HInst<
26827(outs HvxVR:$Vd32),
26828(ins PredRegs:$Pv4, IntRegs:$Rt32),
26829"if ($Pv4) $Vd32.cur = vmem($Rt32)",
26830PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26831let hasNewValue = 1;
26832let opNewValue = 0;
26833let isCVI = 1;
26834let isPseudo = 1;
26835let isCodeGenOnly = 1;
26836let DecoderNamespace = "EXT_mmvec";
26837}
26838def V6_ldcpnt0 : HInst<
26839(outs HvxVR:$Vd32),
26840(ins PredRegs:$Pv4, IntRegs:$Rt32),
26841"if ($Pv4) $Vd32.cur = vmem($Rt32):nt",
26842PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26843let hasNewValue = 1;
26844let opNewValue = 0;
26845let isCVI = 1;
26846let isPseudo = 1;
26847let isCodeGenOnly = 1;
26848let DecoderNamespace = "EXT_mmvec";
26849}
26850def V6_ldnp0 : HInst<
26851(outs HvxVR:$Vd32),
26852(ins PredRegs:$Pv4, IntRegs:$Rt32),
26853"if (!$Pv4) $Vd32 = vmem($Rt32)",
26854PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26855let hasNewValue = 1;
26856let opNewValue = 0;
26857let isCVI = 1;
26858let isPseudo = 1;
26859let isCodeGenOnly = 1;
26860let DecoderNamespace = "EXT_mmvec";
26861}
26862def V6_ldnpnt0 : HInst<
26863(outs HvxVR:$Vd32),
26864(ins PredRegs:$Pv4, IntRegs:$Rt32),
26865"if (!$Pv4) $Vd32 = vmem($Rt32):nt",
26866PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26867let hasNewValue = 1;
26868let opNewValue = 0;
26869let isCVI = 1;
26870let isPseudo = 1;
26871let isCodeGenOnly = 1;
26872let DecoderNamespace = "EXT_mmvec";
26873}
26874def V6_ldnt0 : HInst<
26875(outs HvxVR:$Vd32),
26876(ins IntRegs:$Rt32),
26877"$Vd32 = vmem($Rt32):nt",
26878PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26879let hasNewValue = 1;
26880let opNewValue = 0;
26881let isCVI = 1;
26882let isPseudo = 1;
26883let isCodeGenOnly = 1;
26884let DecoderNamespace = "EXT_mmvec";
26885}
26886def V6_ldntnt0 : HInst<
26887(outs HvxVR:$Vd32),
26888(ins IntRegs:$Rt32),
26889"$Vd32 = vmem($Rt32):nt",
26890PSEUDO, TypeMAPPING>, Requires<[HasV62]> {
26891let hasNewValue = 1;
26892let opNewValue = 0;
26893let isPseudo = 1;
26894let isCodeGenOnly = 1;
26895let DecoderNamespace = "EXT_mmvec";
26896}
26897def V6_ldp0 : HInst<
26898(outs HvxVR:$Vd32),
26899(ins PredRegs:$Pv4, IntRegs:$Rt32),
26900"if ($Pv4) $Vd32 = vmem($Rt32)",
26901PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26902let hasNewValue = 1;
26903let opNewValue = 0;
26904let isCVI = 1;
26905let isPseudo = 1;
26906let isCodeGenOnly = 1;
26907let DecoderNamespace = "EXT_mmvec";
26908}
26909def V6_ldpnt0 : HInst<
26910(outs HvxVR:$Vd32),
26911(ins PredRegs:$Pv4, IntRegs:$Rt32),
26912"if ($Pv4) $Vd32 = vmem($Rt32):nt",
26913PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26914let hasNewValue = 1;
26915let opNewValue = 0;
26916let isCVI = 1;
26917let isPseudo = 1;
26918let isCodeGenOnly = 1;
26919let DecoderNamespace = "EXT_mmvec";
26920}
26921def V6_ldtnp0 : HInst<
26922(outs HvxVR:$Vd32),
26923(ins PredRegs:$Pv4, IntRegs:$Rt32),
26924"if (!$Pv4) $Vd32.tmp = vmem($Rt32)",
26925PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26926let hasNewValue = 1;
26927let opNewValue = 0;
26928let isCVI = 1;
26929let isPseudo = 1;
26930let isCodeGenOnly = 1;
26931let DecoderNamespace = "EXT_mmvec";
26932}
26933def V6_ldtnpnt0 : HInst<
26934(outs HvxVR:$Vd32),
26935(ins PredRegs:$Pv4, IntRegs:$Rt32),
26936"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt",
26937PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26938let hasNewValue = 1;
26939let opNewValue = 0;
26940let isCVI = 1;
26941let isPseudo = 1;
26942let isCodeGenOnly = 1;
26943let DecoderNamespace = "EXT_mmvec";
26944}
26945def V6_ldtp0 : HInst<
26946(outs HvxVR:$Vd32),
26947(ins PredRegs:$Pv4, IntRegs:$Rt32),
26948"if ($Pv4) $Vd32.tmp = vmem($Rt32)",
26949PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26950let hasNewValue = 1;
26951let opNewValue = 0;
26952let isCVI = 1;
26953let isPseudo = 1;
26954let isCodeGenOnly = 1;
26955let DecoderNamespace = "EXT_mmvec";
26956}
26957def V6_ldtpnt0 : HInst<
26958(outs HvxVR:$Vd32),
26959(ins PredRegs:$Pv4, IntRegs:$Rt32),
26960"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt",
26961PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
26962let hasNewValue = 1;
26963let opNewValue = 0;
26964let isCVI = 1;
26965let isPseudo = 1;
26966let isCodeGenOnly = 1;
26967let DecoderNamespace = "EXT_mmvec";
26968}
26969def V6_ldu0 : HInst<
26970(outs HvxVR:$Vd32),
26971(ins IntRegs:$Rt32),
26972"$Vd32 = vmemu($Rt32)",
26973PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> {
26974let hasNewValue = 1;
26975let opNewValue = 0;
26976let isCVI = 1;
26977let isPseudo = 1;
26978let isCodeGenOnly = 1;
26979let DecoderNamespace = "EXT_mmvec";
26980}
26981def V6_lo : HInst<
26982(outs HvxVR:$Vd32),
26983(ins HvxWR:$Vss32),
26984"$Vd32 = lo($Vss32)",
26985CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
26986let hasNewValue = 1;
26987let opNewValue = 0;
26988let isCVI = 1;
26989let isPseudo = 1;
26990let DecoderNamespace = "EXT_mmvec";
26991}
26992def V6_lvsplatb : HInst<
26993(outs HvxVR:$Vd32),
26994(ins IntRegs:$Rt32),
26995"$Vd32.b = vsplat($Rt32)",
26996tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
26997let Inst{13-5} = 0b000000010;
26998let Inst{31-21} = 0b00011001110;
26999let hasNewValue = 1;
27000let opNewValue = 0;
27001let isCVI = 1;
27002let DecoderNamespace = "EXT_mmvec";
27003}
27004def V6_lvsplath : HInst<
27005(outs HvxVR:$Vd32),
27006(ins IntRegs:$Rt32),
27007"$Vd32.h = vsplat($Rt32)",
27008tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> {
27009let Inst{13-5} = 0b000000001;
27010let Inst{31-21} = 0b00011001110;
27011let hasNewValue = 1;
27012let opNewValue = 0;
27013let isCVI = 1;
27014let DecoderNamespace = "EXT_mmvec";
27015}
27016def V6_lvsplatw : HInst<
27017(outs HvxVR:$Vd32),
27018(ins IntRegs:$Rt32),
27019"$Vd32 = vsplat($Rt32)",
27020tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> {
27021let Inst{13-5} = 0b000000001;
27022let Inst{31-21} = 0b00011001101;
27023let hasNewValue = 1;
27024let opNewValue = 0;
27025let isCVI = 1;
27026let DecoderNamespace = "EXT_mmvec";
27027}
27028def V6_pred_and : HInst<
27029(outs HvxQR:$Qd4),
27030(ins HvxQR:$Qs4, HvxQR:$Qt4),
27031"$Qd4 = and($Qs4,$Qt4)",
27032tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27033let Inst{7-2} = 0b000000;
27034let Inst{13-10} = 0b0000;
27035let Inst{21-16} = 0b000011;
27036let Inst{31-24} = 0b00011110;
27037let hasNewValue = 1;
27038let opNewValue = 0;
27039let isCVI = 1;
27040let DecoderNamespace = "EXT_mmvec";
27041}
27042def V6_pred_and_n : HInst<
27043(outs HvxQR:$Qd4),
27044(ins HvxQR:$Qs4, HvxQR:$Qt4),
27045"$Qd4 = and($Qs4,!$Qt4)",
27046tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27047let Inst{7-2} = 0b000101;
27048let Inst{13-10} = 0b0000;
27049let Inst{21-16} = 0b000011;
27050let Inst{31-24} = 0b00011110;
27051let hasNewValue = 1;
27052let opNewValue = 0;
27053let isCVI = 1;
27054let DecoderNamespace = "EXT_mmvec";
27055}
27056def V6_pred_not : HInst<
27057(outs HvxQR:$Qd4),
27058(ins HvxQR:$Qs4),
27059"$Qd4 = not($Qs4)",
27060tc_0ec46cf9, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> {
27061let Inst{7-2} = 0b000010;
27062let Inst{13-10} = 0b0000;
27063let Inst{31-16} = 0b0001111000000011;
27064let hasNewValue = 1;
27065let opNewValue = 0;
27066let isCVI = 1;
27067let DecoderNamespace = "EXT_mmvec";
27068}
27069def V6_pred_or : HInst<
27070(outs HvxQR:$Qd4),
27071(ins HvxQR:$Qs4, HvxQR:$Qt4),
27072"$Qd4 = or($Qs4,$Qt4)",
27073tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27074let Inst{7-2} = 0b000001;
27075let Inst{13-10} = 0b0000;
27076let Inst{21-16} = 0b000011;
27077let Inst{31-24} = 0b00011110;
27078let hasNewValue = 1;
27079let opNewValue = 0;
27080let isCVI = 1;
27081let DecoderNamespace = "EXT_mmvec";
27082}
27083def V6_pred_or_n : HInst<
27084(outs HvxQR:$Qd4),
27085(ins HvxQR:$Qs4, HvxQR:$Qt4),
27086"$Qd4 = or($Qs4,!$Qt4)",
27087tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27088let Inst{7-2} = 0b000100;
27089let Inst{13-10} = 0b0000;
27090let Inst{21-16} = 0b000011;
27091let Inst{31-24} = 0b00011110;
27092let hasNewValue = 1;
27093let opNewValue = 0;
27094let isCVI = 1;
27095let DecoderNamespace = "EXT_mmvec";
27096}
27097def V6_pred_scalar2 : HInst<
27098(outs HvxQR:$Qd4),
27099(ins IntRegs:$Rt32),
27100"$Qd4 = vsetq($Rt32)",
27101tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> {
27102let Inst{13-2} = 0b000000010001;
27103let Inst{31-21} = 0b00011001101;
27104let hasNewValue = 1;
27105let opNewValue = 0;
27106let isCVI = 1;
27107let DecoderNamespace = "EXT_mmvec";
27108}
27109def V6_pred_scalar2v2 : HInst<
27110(outs HvxQR:$Qd4),
27111(ins IntRegs:$Rt32),
27112"$Qd4 = vsetq2($Rt32)",
27113tc_5bf8afbb, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> {
27114let Inst{13-2} = 0b000000010011;
27115let Inst{31-21} = 0b00011001101;
27116let hasNewValue = 1;
27117let opNewValue = 0;
27118let isCVI = 1;
27119let DecoderNamespace = "EXT_mmvec";
27120}
27121def V6_pred_xor : HInst<
27122(outs HvxQR:$Qd4),
27123(ins HvxQR:$Qs4, HvxQR:$Qt4),
27124"$Qd4 = xor($Qs4,$Qt4)",
27125tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> {
27126let Inst{7-2} = 0b000011;
27127let Inst{13-10} = 0b0000;
27128let Inst{21-16} = 0b000011;
27129let Inst{31-24} = 0b00011110;
27130let hasNewValue = 1;
27131let opNewValue = 0;
27132let isCVI = 1;
27133let DecoderNamespace = "EXT_mmvec";
27134}
27135def V6_shuffeqh : HInst<
27136(outs HvxQR:$Qd4),
27137(ins HvxQR:$Qs4, HvxQR:$Qt4),
27138"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)",
27139tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27140let Inst{7-2} = 0b000110;
27141let Inst{13-10} = 0b0000;
27142let Inst{21-16} = 0b000011;
27143let Inst{31-24} = 0b00011110;
27144let hasNewValue = 1;
27145let opNewValue = 0;
27146let isCVI = 1;
27147let DecoderNamespace = "EXT_mmvec";
27148}
27149def V6_shuffeqw : HInst<
27150(outs HvxQR:$Qd4),
27151(ins HvxQR:$Qs4, HvxQR:$Qt4),
27152"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)",
27153tc_db5555f3, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> {
27154let Inst{7-2} = 0b000111;
27155let Inst{13-10} = 0b0000;
27156let Inst{21-16} = 0b000011;
27157let Inst{31-24} = 0b00011110;
27158let hasNewValue = 1;
27159let opNewValue = 0;
27160let isCVI = 1;
27161let DecoderNamespace = "EXT_mmvec";
27162}
27163def V6_st0 : HInst<
27164(outs),
27165(ins IntRegs:$Rt32, HvxVR:$Vs32),
27166"vmem($Rt32) = $Vs32",
27167PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27168let isCVI = 1;
27169let isPseudo = 1;
27170let isCodeGenOnly = 1;
27171let DecoderNamespace = "EXT_mmvec";
27172}
27173def V6_stn0 : HInst<
27174(outs),
27175(ins IntRegs:$Rt32, HvxVR:$Os8),
27176"vmem($Rt32) = $Os8.new",
27177PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27178let isCVI = 1;
27179let isPseudo = 1;
27180let isCodeGenOnly = 1;
27181let DecoderNamespace = "EXT_mmvec";
27182let opNewValue = 1;
27183}
27184def V6_stnnt0 : HInst<
27185(outs),
27186(ins IntRegs:$Rt32, HvxVR:$Os8),
27187"vmem($Rt32):nt = $Os8.new",
27188PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27189let isCVI = 1;
27190let isPseudo = 1;
27191let isCodeGenOnly = 1;
27192let DecoderNamespace = "EXT_mmvec";
27193let opNewValue = 1;
27194}
27195def V6_stnp0 : HInst<
27196(outs),
27197(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27198"if (!$Pv4) vmem($Rt32) = $Vs32",
27199PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27200let isCVI = 1;
27201let isPseudo = 1;
27202let isCodeGenOnly = 1;
27203let DecoderNamespace = "EXT_mmvec";
27204}
27205def V6_stnpnt0 : HInst<
27206(outs),
27207(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27208"if (!$Pv4) vmem($Rt32):nt = $Vs32",
27209PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27210let isCVI = 1;
27211let isPseudo = 1;
27212let isCodeGenOnly = 1;
27213let DecoderNamespace = "EXT_mmvec";
27214}
27215def V6_stnq0 : HInst<
27216(outs),
27217(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27218"if (!$Qv4) vmem($Rt32) = $Vs32",
27219PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27220let isCVI = 1;
27221let isPseudo = 1;
27222let isCodeGenOnly = 1;
27223let DecoderNamespace = "EXT_mmvec";
27224}
27225def V6_stnqnt0 : HInst<
27226(outs),
27227(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27228"if (!$Qv4) vmem($Rt32):nt = $Vs32",
27229PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27230let isCVI = 1;
27231let isPseudo = 1;
27232let isCodeGenOnly = 1;
27233let DecoderNamespace = "EXT_mmvec";
27234}
27235def V6_stnt0 : HInst<
27236(outs),
27237(ins IntRegs:$Rt32, HvxVR:$Vs32),
27238"vmem($Rt32):nt = $Vs32",
27239PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27240let isCVI = 1;
27241let isPseudo = 1;
27242let isCodeGenOnly = 1;
27243let DecoderNamespace = "EXT_mmvec";
27244}
27245def V6_stp0 : HInst<
27246(outs),
27247(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27248"if ($Pv4) vmem($Rt32) = $Vs32",
27249PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27250let isCVI = 1;
27251let isPseudo = 1;
27252let isCodeGenOnly = 1;
27253let DecoderNamespace = "EXT_mmvec";
27254}
27255def V6_stpnt0 : HInst<
27256(outs),
27257(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27258"if ($Pv4) vmem($Rt32):nt = $Vs32",
27259PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27260let isCVI = 1;
27261let isPseudo = 1;
27262let isCodeGenOnly = 1;
27263let DecoderNamespace = "EXT_mmvec";
27264}
27265def V6_stq0 : HInst<
27266(outs),
27267(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27268"if ($Qv4) vmem($Rt32) = $Vs32",
27269PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27270let isCVI = 1;
27271let isPseudo = 1;
27272let isCodeGenOnly = 1;
27273let DecoderNamespace = "EXT_mmvec";
27274}
27275def V6_stqnt0 : HInst<
27276(outs),
27277(ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32),
27278"if ($Qv4) vmem($Rt32):nt = $Vs32",
27279PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27280let isCVI = 1;
27281let isPseudo = 1;
27282let isCodeGenOnly = 1;
27283let DecoderNamespace = "EXT_mmvec";
27284}
27285def V6_stu0 : HInst<
27286(outs),
27287(ins IntRegs:$Rt32, HvxVR:$Vs32),
27288"vmemu($Rt32) = $Vs32",
27289PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27290let isCVI = 1;
27291let isPseudo = 1;
27292let isCodeGenOnly = 1;
27293let DecoderNamespace = "EXT_mmvec";
27294}
27295def V6_stunp0 : HInst<
27296(outs),
27297(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27298"if (!$Pv4) vmemu($Rt32) = $Vs32",
27299PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27300let isCVI = 1;
27301let isPseudo = 1;
27302let isCodeGenOnly = 1;
27303let DecoderNamespace = "EXT_mmvec";
27304}
27305def V6_stup0 : HInst<
27306(outs),
27307(ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32),
27308"if ($Pv4) vmemu($Rt32) = $Vs32",
27309PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> {
27310let isCVI = 1;
27311let isPseudo = 1;
27312let isCodeGenOnly = 1;
27313let DecoderNamespace = "EXT_mmvec";
27314}
27315def V6_v6mpyhubs10 : HInst<
27316(outs HvxWR:$Vdd32),
27317(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27318"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27319tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27320let Inst{7-7} = 0b1;
27321let Inst{13-13} = 0b1;
27322let Inst{31-21} = 0b00011111010;
27323let hasNewValue = 1;
27324let opNewValue = 0;
27325let isCVI = 1;
27326let DecoderNamespace = "EXT_mmvec";
27327}
27328def V6_v6mpyhubs10_alt : HInst<
27329(outs HvxWR:$Vdd32),
27330(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27331"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h",
27332PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27333let hasNewValue = 1;
27334let opNewValue = 0;
27335let isCVI = 1;
27336let isPseudo = 1;
27337let isCodeGenOnly = 1;
27338let DecoderNamespace = "EXT_mmvec";
27339}
27340def V6_v6mpyhubs10_vxx : HInst<
27341(outs HvxWR:$Vxx32),
27342(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27343"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h",
27344tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27345let Inst{7-7} = 0b1;
27346let Inst{13-13} = 0b1;
27347let Inst{31-21} = 0b00011111001;
27348let hasNewValue = 1;
27349let opNewValue = 0;
27350let isAccumulator = 1;
27351let isCVI = 1;
27352let DecoderNamespace = "EXT_mmvec";
27353let Constraints = "$Vxx32 = $Vxx32in";
27354}
27355def V6_v6mpyvubs10 : HInst<
27356(outs HvxWR:$Vdd32),
27357(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27358"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27359tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> {
27360let Inst{7-7} = 0b0;
27361let Inst{13-13} = 0b1;
27362let Inst{31-21} = 0b00011111010;
27363let hasNewValue = 1;
27364let opNewValue = 0;
27365let isCVI = 1;
27366let DecoderNamespace = "EXT_mmvec";
27367}
27368def V6_v6mpyvubs10_alt : HInst<
27369(outs HvxWR:$Vdd32),
27370(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27371"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v",
27372PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> {
27373let hasNewValue = 1;
27374let opNewValue = 0;
27375let isCVI = 1;
27376let isPseudo = 1;
27377let isCodeGenOnly = 1;
27378let DecoderNamespace = "EXT_mmvec";
27379}
27380def V6_v6mpyvubs10_vxx : HInst<
27381(outs HvxWR:$Vxx32),
27382(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii),
27383"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v",
27384tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> {
27385let Inst{7-7} = 0b0;
27386let Inst{13-13} = 0b1;
27387let Inst{31-21} = 0b00011111001;
27388let hasNewValue = 1;
27389let opNewValue = 0;
27390let isAccumulator = 1;
27391let isCVI = 1;
27392let DecoderNamespace = "EXT_mmvec";
27393let Constraints = "$Vxx32 = $Vxx32in";
27394}
27395def V6_vL32Ub_ai : HInst<
27396(outs HvxVR:$Vd32),
27397(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27398"$Vd32 = vmemu($Rt32+#$Ii)",
27399tc_a7e6707d, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> {
27400let Inst{7-5} = 0b111;
27401let Inst{12-11} = 0b00;
27402let Inst{31-21} = 0b00101000000;
27403let hasNewValue = 1;
27404let opNewValue = 0;
27405let addrMode = BaseImmOffset;
27406let accessSize = HVXVectorAccess;
27407let isCVLoad = 1;
27408let isCVI = 1;
27409let mayLoad = 1;
27410let isRestrictNoSlot1Store = 1;
27411let DecoderNamespace = "EXT_mmvec";
27412}
27413def V6_vL32Ub_pi : HInst<
27414(outs HvxVR:$Vd32, IntRegs:$Rx32),
27415(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27416"$Vd32 = vmemu($Rx32++#$Ii)",
27417tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> {
27418let Inst{7-5} = 0b111;
27419let Inst{13-11} = 0b000;
27420let Inst{31-21} = 0b00101001000;
27421let hasNewValue = 1;
27422let opNewValue = 0;
27423let addrMode = PostInc;
27424let accessSize = HVXVectorAccess;
27425let isCVLoad = 1;
27426let isCVI = 1;
27427let mayLoad = 1;
27428let isRestrictNoSlot1Store = 1;
27429let BaseOpcode = "V6_vL32b_pi";
27430let DecoderNamespace = "EXT_mmvec";
27431let Constraints = "$Rx32 = $Rx32in";
27432}
27433def V6_vL32Ub_ppu : HInst<
27434(outs HvxVR:$Vd32, IntRegs:$Rx32),
27435(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27436"$Vd32 = vmemu($Rx32++$Mu2)",
27437tc_3c56e5ce, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> {
27438let Inst{12-5} = 0b00000111;
27439let Inst{31-21} = 0b00101011000;
27440let hasNewValue = 1;
27441let opNewValue = 0;
27442let addrMode = PostInc;
27443let accessSize = HVXVectorAccess;
27444let isCVLoad = 1;
27445let isCVI = 1;
27446let mayLoad = 1;
27447let isRestrictNoSlot1Store = 1;
27448let DecoderNamespace = "EXT_mmvec";
27449let Constraints = "$Rx32 = $Rx32in";
27450}
27451def V6_vL32b_ai : HInst<
27452(outs HvxVR:$Vd32),
27453(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27454"$Vd32 = vmem($Rt32+#$Ii)",
27455tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27456let Inst{7-5} = 0b000;
27457let Inst{12-11} = 0b00;
27458let Inst{31-21} = 0b00101000000;
27459let hasNewValue = 1;
27460let opNewValue = 0;
27461let addrMode = BaseImmOffset;
27462let accessSize = HVXVectorAccess;
27463let isCVLoad = 1;
27464let isCVI = 1;
27465let mayLoad = 1;
27466let isRestrictNoSlot1Store = 1;
27467let BaseOpcode = "V6_vL32b_ai";
27468let isCVLoadable = 1;
27469let isPredicable = 1;
27470let DecoderNamespace = "EXT_mmvec";
27471}
27472def V6_vL32b_cur_ai : HInst<
27473(outs HvxVR:$Vd32),
27474(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27475"$Vd32.cur = vmem($Rt32+#$Ii)",
27476tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27477let Inst{7-5} = 0b001;
27478let Inst{12-11} = 0b00;
27479let Inst{31-21} = 0b00101000000;
27480let hasNewValue = 1;
27481let opNewValue = 0;
27482let addrMode = BaseImmOffset;
27483let accessSize = HVXVectorAccess;
27484let isCVLoad = 1;
27485let isCVI = 1;
27486let CVINew = 1;
27487let mayLoad = 1;
27488let isRestrictNoSlot1Store = 1;
27489let BaseOpcode = "V6_vL32b_cur_ai";
27490let isPredicable = 1;
27491let DecoderNamespace = "EXT_mmvec";
27492}
27493def V6_vL32b_cur_npred_ai : HInst<
27494(outs HvxVR:$Vd32),
27495(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27496"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27497tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27498let Inst{7-5} = 0b101;
27499let Inst{31-21} = 0b00101000100;
27500let isPredicated = 1;
27501let isPredicatedFalse = 1;
27502let hasNewValue = 1;
27503let opNewValue = 0;
27504let addrMode = BaseImmOffset;
27505let accessSize = HVXVectorAccess;
27506let isCVLoad = 1;
27507let isCVI = 1;
27508let CVINew = 1;
27509let mayLoad = 1;
27510let isRestrictNoSlot1Store = 1;
27511let BaseOpcode = "V6_vL32b_cur_ai";
27512let DecoderNamespace = "EXT_mmvec";
27513}
27514def V6_vL32b_cur_npred_pi : HInst<
27515(outs HvxVR:$Vd32, IntRegs:$Rx32),
27516(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27517"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27518tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27519let Inst{7-5} = 0b101;
27520let Inst{13-13} = 0b0;
27521let Inst{31-21} = 0b00101001100;
27522let isPredicated = 1;
27523let isPredicatedFalse = 1;
27524let hasNewValue = 1;
27525let opNewValue = 0;
27526let addrMode = PostInc;
27527let accessSize = HVXVectorAccess;
27528let isCVLoad = 1;
27529let isCVI = 1;
27530let CVINew = 1;
27531let mayLoad = 1;
27532let isRestrictNoSlot1Store = 1;
27533let BaseOpcode = "V6_vL32b_cur_pi";
27534let DecoderNamespace = "EXT_mmvec";
27535let Constraints = "$Rx32 = $Rx32in";
27536}
27537def V6_vL32b_cur_npred_ppu : HInst<
27538(outs HvxVR:$Vd32, IntRegs:$Rx32),
27539(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27540"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27541tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27542let Inst{10-5} = 0b000101;
27543let Inst{31-21} = 0b00101011100;
27544let isPredicated = 1;
27545let isPredicatedFalse = 1;
27546let hasNewValue = 1;
27547let opNewValue = 0;
27548let addrMode = PostInc;
27549let accessSize = HVXVectorAccess;
27550let isCVLoad = 1;
27551let isCVI = 1;
27552let CVINew = 1;
27553let mayLoad = 1;
27554let isRestrictNoSlot1Store = 1;
27555let BaseOpcode = "V6_vL32b_cur_ppu";
27556let DecoderNamespace = "EXT_mmvec";
27557let Constraints = "$Rx32 = $Rx32in";
27558}
27559def V6_vL32b_cur_pi : HInst<
27560(outs HvxVR:$Vd32, IntRegs:$Rx32),
27561(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27562"$Vd32.cur = vmem($Rx32++#$Ii)",
27563tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27564let Inst{7-5} = 0b001;
27565let Inst{13-11} = 0b000;
27566let Inst{31-21} = 0b00101001000;
27567let hasNewValue = 1;
27568let opNewValue = 0;
27569let addrMode = PostInc;
27570let accessSize = HVXVectorAccess;
27571let isCVLoad = 1;
27572let isCVI = 1;
27573let CVINew = 1;
27574let mayLoad = 1;
27575let isRestrictNoSlot1Store = 1;
27576let BaseOpcode = "V6_vL32b_cur_pi";
27577let isPredicable = 1;
27578let DecoderNamespace = "EXT_mmvec";
27579let Constraints = "$Rx32 = $Rx32in";
27580}
27581def V6_vL32b_cur_ppu : HInst<
27582(outs HvxVR:$Vd32, IntRegs:$Rx32),
27583(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27584"$Vd32.cur = vmem($Rx32++$Mu2)",
27585tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27586let Inst{12-5} = 0b00000001;
27587let Inst{31-21} = 0b00101011000;
27588let hasNewValue = 1;
27589let opNewValue = 0;
27590let addrMode = PostInc;
27591let accessSize = HVXVectorAccess;
27592let isCVLoad = 1;
27593let isCVI = 1;
27594let CVINew = 1;
27595let mayLoad = 1;
27596let isRestrictNoSlot1Store = 1;
27597let BaseOpcode = "V6_vL32b_cur_ppu";
27598let isPredicable = 1;
27599let DecoderNamespace = "EXT_mmvec";
27600let Constraints = "$Rx32 = $Rx32in";
27601}
27602def V6_vL32b_cur_pred_ai : HInst<
27603(outs HvxVR:$Vd32),
27604(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27605"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)",
27606tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27607let Inst{7-5} = 0b100;
27608let Inst{31-21} = 0b00101000100;
27609let isPredicated = 1;
27610let hasNewValue = 1;
27611let opNewValue = 0;
27612let addrMode = BaseImmOffset;
27613let accessSize = HVXVectorAccess;
27614let isCVLoad = 1;
27615let isCVI = 1;
27616let CVINew = 1;
27617let mayLoad = 1;
27618let isRestrictNoSlot1Store = 1;
27619let BaseOpcode = "V6_vL32b_cur_ai";
27620let DecoderNamespace = "EXT_mmvec";
27621}
27622def V6_vL32b_cur_pred_pi : HInst<
27623(outs HvxVR:$Vd32, IntRegs:$Rx32),
27624(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27625"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)",
27626tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27627let Inst{7-5} = 0b100;
27628let Inst{13-13} = 0b0;
27629let Inst{31-21} = 0b00101001100;
27630let isPredicated = 1;
27631let hasNewValue = 1;
27632let opNewValue = 0;
27633let addrMode = PostInc;
27634let accessSize = HVXVectorAccess;
27635let isCVLoad = 1;
27636let isCVI = 1;
27637let CVINew = 1;
27638let mayLoad = 1;
27639let isRestrictNoSlot1Store = 1;
27640let BaseOpcode = "V6_vL32b_cur_pi";
27641let DecoderNamespace = "EXT_mmvec";
27642let Constraints = "$Rx32 = $Rx32in";
27643}
27644def V6_vL32b_cur_pred_ppu : HInst<
27645(outs HvxVR:$Vd32, IntRegs:$Rx32),
27646(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27647"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)",
27648tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27649let Inst{10-5} = 0b000100;
27650let Inst{31-21} = 0b00101011100;
27651let isPredicated = 1;
27652let hasNewValue = 1;
27653let opNewValue = 0;
27654let addrMode = PostInc;
27655let accessSize = HVXVectorAccess;
27656let isCVLoad = 1;
27657let isCVI = 1;
27658let CVINew = 1;
27659let mayLoad = 1;
27660let isRestrictNoSlot1Store = 1;
27661let BaseOpcode = "V6_vL32b_cur_ppu";
27662let DecoderNamespace = "EXT_mmvec";
27663let Constraints = "$Rx32 = $Rx32in";
27664}
27665def V6_vL32b_npred_ai : HInst<
27666(outs HvxVR:$Vd32),
27667(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27668"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)",
27669tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27670let Inst{7-5} = 0b011;
27671let Inst{31-21} = 0b00101000100;
27672let isPredicated = 1;
27673let isPredicatedFalse = 1;
27674let hasNewValue = 1;
27675let opNewValue = 0;
27676let addrMode = BaseImmOffset;
27677let accessSize = HVXVectorAccess;
27678let isCVLoad = 1;
27679let isCVI = 1;
27680let mayLoad = 1;
27681let isRestrictNoSlot1Store = 1;
27682let BaseOpcode = "V6_vL32b_ai";
27683let DecoderNamespace = "EXT_mmvec";
27684}
27685def V6_vL32b_npred_pi : HInst<
27686(outs HvxVR:$Vd32, IntRegs:$Rx32),
27687(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27688"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)",
27689tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27690let Inst{7-5} = 0b011;
27691let Inst{13-13} = 0b0;
27692let Inst{31-21} = 0b00101001100;
27693let isPredicated = 1;
27694let isPredicatedFalse = 1;
27695let hasNewValue = 1;
27696let opNewValue = 0;
27697let addrMode = PostInc;
27698let accessSize = HVXVectorAccess;
27699let isCVLoad = 1;
27700let isCVI = 1;
27701let mayLoad = 1;
27702let isRestrictNoSlot1Store = 1;
27703let BaseOpcode = "V6_vL32b_pi";
27704let DecoderNamespace = "EXT_mmvec";
27705let Constraints = "$Rx32 = $Rx32in";
27706}
27707def V6_vL32b_npred_ppu : HInst<
27708(outs HvxVR:$Vd32, IntRegs:$Rx32),
27709(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27710"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)",
27711tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27712let Inst{10-5} = 0b000011;
27713let Inst{31-21} = 0b00101011100;
27714let isPredicated = 1;
27715let isPredicatedFalse = 1;
27716let hasNewValue = 1;
27717let opNewValue = 0;
27718let addrMode = PostInc;
27719let accessSize = HVXVectorAccess;
27720let isCVLoad = 1;
27721let isCVI = 1;
27722let mayLoad = 1;
27723let isRestrictNoSlot1Store = 1;
27724let BaseOpcode = "V6_vL32b_ppu";
27725let DecoderNamespace = "EXT_mmvec";
27726let Constraints = "$Rx32 = $Rx32in";
27727}
27728def V6_vL32b_nt_ai : HInst<
27729(outs HvxVR:$Vd32),
27730(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27731"$Vd32 = vmem($Rt32+#$Ii):nt",
27732tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27733let Inst{7-5} = 0b000;
27734let Inst{12-11} = 0b00;
27735let Inst{31-21} = 0b00101000010;
27736let hasNewValue = 1;
27737let opNewValue = 0;
27738let addrMode = BaseImmOffset;
27739let accessSize = HVXVectorAccess;
27740let isCVLoad = 1;
27741let isCVI = 1;
27742let mayLoad = 1;
27743let isNonTemporal = 1;
27744let isRestrictNoSlot1Store = 1;
27745let BaseOpcode = "V6_vL32b_nt_ai";
27746let isCVLoadable = 1;
27747let isPredicable = 1;
27748let DecoderNamespace = "EXT_mmvec";
27749}
27750def V6_vL32b_nt_cur_ai : HInst<
27751(outs HvxVR:$Vd32),
27752(ins IntRegs:$Rt32, s4_0Imm:$Ii),
27753"$Vd32.cur = vmem($Rt32+#$Ii):nt",
27754tc_c0749f3c, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
27755let Inst{7-5} = 0b001;
27756let Inst{12-11} = 0b00;
27757let Inst{31-21} = 0b00101000010;
27758let hasNewValue = 1;
27759let opNewValue = 0;
27760let addrMode = BaseImmOffset;
27761let accessSize = HVXVectorAccess;
27762let isCVLoad = 1;
27763let isCVI = 1;
27764let CVINew = 1;
27765let mayLoad = 1;
27766let isNonTemporal = 1;
27767let isRestrictNoSlot1Store = 1;
27768let BaseOpcode = "V6_vL32b_nt_cur_ai";
27769let isPredicable = 1;
27770let DecoderNamespace = "EXT_mmvec";
27771}
27772def V6_vL32b_nt_cur_npred_ai : HInst<
27773(outs HvxVR:$Vd32),
27774(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27775"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27776tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27777let Inst{7-5} = 0b101;
27778let Inst{31-21} = 0b00101000110;
27779let isPredicated = 1;
27780let isPredicatedFalse = 1;
27781let hasNewValue = 1;
27782let opNewValue = 0;
27783let addrMode = BaseImmOffset;
27784let accessSize = HVXVectorAccess;
27785let isCVLoad = 1;
27786let isCVI = 1;
27787let CVINew = 1;
27788let mayLoad = 1;
27789let isNonTemporal = 1;
27790let isRestrictNoSlot1Store = 1;
27791let BaseOpcode = "V6_vL32b_nt_cur_ai";
27792let DecoderNamespace = "EXT_mmvec";
27793}
27794def V6_vL32b_nt_cur_npred_pi : HInst<
27795(outs HvxVR:$Vd32, IntRegs:$Rx32),
27796(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27797"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27798tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27799let Inst{7-5} = 0b101;
27800let Inst{13-13} = 0b0;
27801let Inst{31-21} = 0b00101001110;
27802let isPredicated = 1;
27803let isPredicatedFalse = 1;
27804let hasNewValue = 1;
27805let opNewValue = 0;
27806let addrMode = PostInc;
27807let accessSize = HVXVectorAccess;
27808let isCVLoad = 1;
27809let isCVI = 1;
27810let CVINew = 1;
27811let mayLoad = 1;
27812let isNonTemporal = 1;
27813let isRestrictNoSlot1Store = 1;
27814let BaseOpcode = "V6_vL32b_nt_cur_pi";
27815let DecoderNamespace = "EXT_mmvec";
27816let Constraints = "$Rx32 = $Rx32in";
27817}
27818def V6_vL32b_nt_cur_npred_ppu : HInst<
27819(outs HvxVR:$Vd32, IntRegs:$Rx32),
27820(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27821"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27822tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27823let Inst{10-5} = 0b000101;
27824let Inst{31-21} = 0b00101011110;
27825let isPredicated = 1;
27826let isPredicatedFalse = 1;
27827let hasNewValue = 1;
27828let opNewValue = 0;
27829let addrMode = PostInc;
27830let accessSize = HVXVectorAccess;
27831let isCVLoad = 1;
27832let isCVI = 1;
27833let CVINew = 1;
27834let mayLoad = 1;
27835let isNonTemporal = 1;
27836let isRestrictNoSlot1Store = 1;
27837let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27838let DecoderNamespace = "EXT_mmvec";
27839let Constraints = "$Rx32 = $Rx32in";
27840}
27841def V6_vL32b_nt_cur_pi : HInst<
27842(outs HvxVR:$Vd32, IntRegs:$Rx32),
27843(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
27844"$Vd32.cur = vmem($Rx32++#$Ii):nt",
27845tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
27846let Inst{7-5} = 0b001;
27847let Inst{13-11} = 0b000;
27848let Inst{31-21} = 0b00101001010;
27849let hasNewValue = 1;
27850let opNewValue = 0;
27851let addrMode = PostInc;
27852let accessSize = HVXVectorAccess;
27853let isCVLoad = 1;
27854let isCVI = 1;
27855let CVINew = 1;
27856let mayLoad = 1;
27857let isNonTemporal = 1;
27858let isRestrictNoSlot1Store = 1;
27859let BaseOpcode = "V6_vL32b_nt_cur_pi";
27860let isPredicable = 1;
27861let DecoderNamespace = "EXT_mmvec";
27862let Constraints = "$Rx32 = $Rx32in";
27863}
27864def V6_vL32b_nt_cur_ppu : HInst<
27865(outs HvxVR:$Vd32, IntRegs:$Rx32),
27866(ins IntRegs:$Rx32in, ModRegs:$Mu2),
27867"$Vd32.cur = vmem($Rx32++$Mu2):nt",
27868tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
27869let Inst{12-5} = 0b00000001;
27870let Inst{31-21} = 0b00101011010;
27871let hasNewValue = 1;
27872let opNewValue = 0;
27873let addrMode = PostInc;
27874let accessSize = HVXVectorAccess;
27875let isCVLoad = 1;
27876let isCVI = 1;
27877let CVINew = 1;
27878let mayLoad = 1;
27879let isNonTemporal = 1;
27880let isRestrictNoSlot1Store = 1;
27881let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27882let isPredicable = 1;
27883let DecoderNamespace = "EXT_mmvec";
27884let Constraints = "$Rx32 = $Rx32in";
27885}
27886def V6_vL32b_nt_cur_pred_ai : HInst<
27887(outs HvxVR:$Vd32),
27888(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27889"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt",
27890tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27891let Inst{7-5} = 0b100;
27892let Inst{31-21} = 0b00101000110;
27893let isPredicated = 1;
27894let hasNewValue = 1;
27895let opNewValue = 0;
27896let addrMode = BaseImmOffset;
27897let accessSize = HVXVectorAccess;
27898let isCVLoad = 1;
27899let isCVI = 1;
27900let CVINew = 1;
27901let mayLoad = 1;
27902let isNonTemporal = 1;
27903let isRestrictNoSlot1Store = 1;
27904let BaseOpcode = "V6_vL32b_nt_cur_ai";
27905let DecoderNamespace = "EXT_mmvec";
27906}
27907def V6_vL32b_nt_cur_pred_pi : HInst<
27908(outs HvxVR:$Vd32, IntRegs:$Rx32),
27909(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27910"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt",
27911tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27912let Inst{7-5} = 0b100;
27913let Inst{13-13} = 0b0;
27914let Inst{31-21} = 0b00101001110;
27915let isPredicated = 1;
27916let hasNewValue = 1;
27917let opNewValue = 0;
27918let addrMode = PostInc;
27919let accessSize = HVXVectorAccess;
27920let isCVLoad = 1;
27921let isCVI = 1;
27922let CVINew = 1;
27923let mayLoad = 1;
27924let isNonTemporal = 1;
27925let isRestrictNoSlot1Store = 1;
27926let BaseOpcode = "V6_vL32b_nt_cur_pi";
27927let DecoderNamespace = "EXT_mmvec";
27928let Constraints = "$Rx32 = $Rx32in";
27929}
27930def V6_vL32b_nt_cur_pred_ppu : HInst<
27931(outs HvxVR:$Vd32, IntRegs:$Rx32),
27932(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27933"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt",
27934tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
27935let Inst{10-5} = 0b000100;
27936let Inst{31-21} = 0b00101011110;
27937let isPredicated = 1;
27938let hasNewValue = 1;
27939let opNewValue = 0;
27940let addrMode = PostInc;
27941let accessSize = HVXVectorAccess;
27942let isCVLoad = 1;
27943let isCVI = 1;
27944let CVINew = 1;
27945let mayLoad = 1;
27946let isNonTemporal = 1;
27947let isRestrictNoSlot1Store = 1;
27948let BaseOpcode = "V6_vL32b_nt_cur_ppu";
27949let DecoderNamespace = "EXT_mmvec";
27950let Constraints = "$Rx32 = $Rx32in";
27951}
27952def V6_vL32b_nt_npred_ai : HInst<
27953(outs HvxVR:$Vd32),
27954(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
27955"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
27956tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
27957let Inst{7-5} = 0b011;
27958let Inst{31-21} = 0b00101000110;
27959let isPredicated = 1;
27960let isPredicatedFalse = 1;
27961let hasNewValue = 1;
27962let opNewValue = 0;
27963let addrMode = BaseImmOffset;
27964let accessSize = HVXVectorAccess;
27965let isCVLoad = 1;
27966let isCVI = 1;
27967let mayLoad = 1;
27968let isNonTemporal = 1;
27969let isRestrictNoSlot1Store = 1;
27970let BaseOpcode = "V6_vL32b_nt_ai";
27971let DecoderNamespace = "EXT_mmvec";
27972}
27973def V6_vL32b_nt_npred_pi : HInst<
27974(outs HvxVR:$Vd32, IntRegs:$Rx32),
27975(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
27976"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
27977tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
27978let Inst{7-5} = 0b011;
27979let Inst{13-13} = 0b0;
27980let Inst{31-21} = 0b00101001110;
27981let isPredicated = 1;
27982let isPredicatedFalse = 1;
27983let hasNewValue = 1;
27984let opNewValue = 0;
27985let addrMode = PostInc;
27986let accessSize = HVXVectorAccess;
27987let isCVLoad = 1;
27988let isCVI = 1;
27989let mayLoad = 1;
27990let isNonTemporal = 1;
27991let isRestrictNoSlot1Store = 1;
27992let BaseOpcode = "V6_vL32b_nt_pi";
27993let DecoderNamespace = "EXT_mmvec";
27994let Constraints = "$Rx32 = $Rx32in";
27995}
27996def V6_vL32b_nt_npred_ppu : HInst<
27997(outs HvxVR:$Vd32, IntRegs:$Rx32),
27998(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
27999"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28000tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28001let Inst{10-5} = 0b000011;
28002let Inst{31-21} = 0b00101011110;
28003let isPredicated = 1;
28004let isPredicatedFalse = 1;
28005let hasNewValue = 1;
28006let opNewValue = 0;
28007let addrMode = PostInc;
28008let accessSize = HVXVectorAccess;
28009let isCVLoad = 1;
28010let isCVI = 1;
28011let mayLoad = 1;
28012let isNonTemporal = 1;
28013let isRestrictNoSlot1Store = 1;
28014let BaseOpcode = "V6_vL32b_nt_ppu";
28015let DecoderNamespace = "EXT_mmvec";
28016let Constraints = "$Rx32 = $Rx32in";
28017}
28018def V6_vL32b_nt_pi : HInst<
28019(outs HvxVR:$Vd32, IntRegs:$Rx32),
28020(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28021"$Vd32 = vmem($Rx32++#$Ii):nt",
28022tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28023let Inst{7-5} = 0b000;
28024let Inst{13-11} = 0b000;
28025let Inst{31-21} = 0b00101001010;
28026let hasNewValue = 1;
28027let opNewValue = 0;
28028let addrMode = PostInc;
28029let accessSize = HVXVectorAccess;
28030let isCVLoad = 1;
28031let isCVI = 1;
28032let mayLoad = 1;
28033let isNonTemporal = 1;
28034let isRestrictNoSlot1Store = 1;
28035let BaseOpcode = "V6_vL32b_nt_pi";
28036let isCVLoadable = 1;
28037let isPredicable = 1;
28038let DecoderNamespace = "EXT_mmvec";
28039let Constraints = "$Rx32 = $Rx32in";
28040}
28041def V6_vL32b_nt_ppu : HInst<
28042(outs HvxVR:$Vd32, IntRegs:$Rx32),
28043(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28044"$Vd32 = vmem($Rx32++$Mu2):nt",
28045tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28046let Inst{12-5} = 0b00000000;
28047let Inst{31-21} = 0b00101011010;
28048let hasNewValue = 1;
28049let opNewValue = 0;
28050let addrMode = PostInc;
28051let accessSize = HVXVectorAccess;
28052let isCVLoad = 1;
28053let isCVI = 1;
28054let mayLoad = 1;
28055let isNonTemporal = 1;
28056let isRestrictNoSlot1Store = 1;
28057let BaseOpcode = "V6_vL32b_nt_ppu";
28058let isCVLoadable = 1;
28059let isPredicable = 1;
28060let DecoderNamespace = "EXT_mmvec";
28061let Constraints = "$Rx32 = $Rx32in";
28062}
28063def V6_vL32b_nt_pred_ai : HInst<
28064(outs HvxVR:$Vd32),
28065(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28066"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt",
28067tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28068let Inst{7-5} = 0b010;
28069let Inst{31-21} = 0b00101000110;
28070let isPredicated = 1;
28071let hasNewValue = 1;
28072let opNewValue = 0;
28073let addrMode = BaseImmOffset;
28074let accessSize = HVXVectorAccess;
28075let isCVLoad = 1;
28076let isCVI = 1;
28077let mayLoad = 1;
28078let isNonTemporal = 1;
28079let isRestrictNoSlot1Store = 1;
28080let BaseOpcode = "V6_vL32b_nt_ai";
28081let DecoderNamespace = "EXT_mmvec";
28082}
28083def V6_vL32b_nt_pred_pi : HInst<
28084(outs HvxVR:$Vd32, IntRegs:$Rx32),
28085(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28086"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt",
28087tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28088let Inst{7-5} = 0b010;
28089let Inst{13-13} = 0b0;
28090let Inst{31-21} = 0b00101001110;
28091let isPredicated = 1;
28092let hasNewValue = 1;
28093let opNewValue = 0;
28094let addrMode = PostInc;
28095let accessSize = HVXVectorAccess;
28096let isCVLoad = 1;
28097let isCVI = 1;
28098let mayLoad = 1;
28099let isNonTemporal = 1;
28100let isRestrictNoSlot1Store = 1;
28101let BaseOpcode = "V6_vL32b_nt_pi";
28102let DecoderNamespace = "EXT_mmvec";
28103let Constraints = "$Rx32 = $Rx32in";
28104}
28105def V6_vL32b_nt_pred_ppu : HInst<
28106(outs HvxVR:$Vd32, IntRegs:$Rx32),
28107(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28108"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt",
28109tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28110let Inst{10-5} = 0b000010;
28111let Inst{31-21} = 0b00101011110;
28112let isPredicated = 1;
28113let hasNewValue = 1;
28114let opNewValue = 0;
28115let addrMode = PostInc;
28116let accessSize = HVXVectorAccess;
28117let isCVLoad = 1;
28118let isCVI = 1;
28119let mayLoad = 1;
28120let isNonTemporal = 1;
28121let isRestrictNoSlot1Store = 1;
28122let BaseOpcode = "V6_vL32b_nt_ppu";
28123let DecoderNamespace = "EXT_mmvec";
28124let Constraints = "$Rx32 = $Rx32in";
28125}
28126def V6_vL32b_nt_tmp_ai : HInst<
28127(outs HvxVR:$Vd32),
28128(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28129"$Vd32.tmp = vmem($Rt32+#$Ii):nt",
28130tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
28131let Inst{7-5} = 0b010;
28132let Inst{12-11} = 0b00;
28133let Inst{31-21} = 0b00101000010;
28134let hasNewValue = 1;
28135let opNewValue = 0;
28136let addrMode = BaseImmOffset;
28137let accessSize = HVXVectorAccess;
28138let isCVLoad = 1;
28139let isCVI = 1;
28140let hasTmpDst = 1;
28141let mayLoad = 1;
28142let isNonTemporal = 1;
28143let isRestrictNoSlot1Store = 1;
28144let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28145let isPredicable = 1;
28146let DecoderNamespace = "EXT_mmvec";
28147}
28148def V6_vL32b_nt_tmp_npred_ai : HInst<
28149(outs HvxVR:$Vd32),
28150(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28151"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28152tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28153let Inst{7-5} = 0b111;
28154let Inst{31-21} = 0b00101000110;
28155let isPredicated = 1;
28156let isPredicatedFalse = 1;
28157let hasNewValue = 1;
28158let opNewValue = 0;
28159let addrMode = BaseImmOffset;
28160let accessSize = HVXVectorAccess;
28161let isCVLoad = 1;
28162let isCVI = 1;
28163let hasTmpDst = 1;
28164let mayLoad = 1;
28165let isNonTemporal = 1;
28166let isRestrictNoSlot1Store = 1;
28167let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28168let DecoderNamespace = "EXT_mmvec";
28169}
28170def V6_vL32b_nt_tmp_npred_pi : HInst<
28171(outs HvxVR:$Vd32, IntRegs:$Rx32),
28172(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28173"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28174tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28175let Inst{7-5} = 0b111;
28176let Inst{13-13} = 0b0;
28177let Inst{31-21} = 0b00101001110;
28178let isPredicated = 1;
28179let isPredicatedFalse = 1;
28180let hasNewValue = 1;
28181let opNewValue = 0;
28182let addrMode = PostInc;
28183let accessSize = HVXVectorAccess;
28184let isCVLoad = 1;
28185let isCVI = 1;
28186let hasTmpDst = 1;
28187let mayLoad = 1;
28188let isNonTemporal = 1;
28189let isRestrictNoSlot1Store = 1;
28190let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28191let DecoderNamespace = "EXT_mmvec";
28192let Constraints = "$Rx32 = $Rx32in";
28193}
28194def V6_vL32b_nt_tmp_npred_ppu : HInst<
28195(outs HvxVR:$Vd32, IntRegs:$Rx32),
28196(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28197"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28198tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28199let Inst{10-5} = 0b000111;
28200let Inst{31-21} = 0b00101011110;
28201let isPredicated = 1;
28202let isPredicatedFalse = 1;
28203let hasNewValue = 1;
28204let opNewValue = 0;
28205let addrMode = PostInc;
28206let accessSize = HVXVectorAccess;
28207let isCVLoad = 1;
28208let isCVI = 1;
28209let hasTmpDst = 1;
28210let mayLoad = 1;
28211let isNonTemporal = 1;
28212let isRestrictNoSlot1Store = 1;
28213let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28214let DecoderNamespace = "EXT_mmvec";
28215let Constraints = "$Rx32 = $Rx32in";
28216}
28217def V6_vL32b_nt_tmp_pi : HInst<
28218(outs HvxVR:$Vd32, IntRegs:$Rx32),
28219(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28220"$Vd32.tmp = vmem($Rx32++#$Ii):nt",
28221tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28222let Inst{7-5} = 0b010;
28223let Inst{13-11} = 0b000;
28224let Inst{31-21} = 0b00101001010;
28225let hasNewValue = 1;
28226let opNewValue = 0;
28227let addrMode = PostInc;
28228let accessSize = HVXVectorAccess;
28229let isCVLoad = 1;
28230let isCVI = 1;
28231let hasTmpDst = 1;
28232let mayLoad = 1;
28233let isNonTemporal = 1;
28234let isRestrictNoSlot1Store = 1;
28235let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28236let isPredicable = 1;
28237let DecoderNamespace = "EXT_mmvec";
28238let Constraints = "$Rx32 = $Rx32in";
28239}
28240def V6_vL32b_nt_tmp_ppu : HInst<
28241(outs HvxVR:$Vd32, IntRegs:$Rx32),
28242(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28243"$Vd32.tmp = vmem($Rx32++$Mu2):nt",
28244tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28245let Inst{12-5} = 0b00000010;
28246let Inst{31-21} = 0b00101011010;
28247let hasNewValue = 1;
28248let opNewValue = 0;
28249let addrMode = PostInc;
28250let accessSize = HVXVectorAccess;
28251let isCVLoad = 1;
28252let isCVI = 1;
28253let hasTmpDst = 1;
28254let mayLoad = 1;
28255let isNonTemporal = 1;
28256let isRestrictNoSlot1Store = 1;
28257let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28258let isPredicable = 1;
28259let DecoderNamespace = "EXT_mmvec";
28260let Constraints = "$Rx32 = $Rx32in";
28261}
28262def V6_vL32b_nt_tmp_pred_ai : HInst<
28263(outs HvxVR:$Vd32),
28264(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28265"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt",
28266tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28267let Inst{7-5} = 0b110;
28268let Inst{31-21} = 0b00101000110;
28269let isPredicated = 1;
28270let hasNewValue = 1;
28271let opNewValue = 0;
28272let addrMode = BaseImmOffset;
28273let accessSize = HVXVectorAccess;
28274let isCVLoad = 1;
28275let isCVI = 1;
28276let hasTmpDst = 1;
28277let mayLoad = 1;
28278let isNonTemporal = 1;
28279let isRestrictNoSlot1Store = 1;
28280let BaseOpcode = "V6_vL32b_nt_tmp_ai";
28281let DecoderNamespace = "EXT_mmvec";
28282}
28283def V6_vL32b_nt_tmp_pred_pi : HInst<
28284(outs HvxVR:$Vd32, IntRegs:$Rx32),
28285(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28286"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt",
28287tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28288let Inst{7-5} = 0b110;
28289let Inst{13-13} = 0b0;
28290let Inst{31-21} = 0b00101001110;
28291let isPredicated = 1;
28292let hasNewValue = 1;
28293let opNewValue = 0;
28294let addrMode = PostInc;
28295let accessSize = HVXVectorAccess;
28296let isCVLoad = 1;
28297let isCVI = 1;
28298let hasTmpDst = 1;
28299let mayLoad = 1;
28300let isNonTemporal = 1;
28301let isRestrictNoSlot1Store = 1;
28302let BaseOpcode = "V6_vL32b_nt_tmp_pi";
28303let DecoderNamespace = "EXT_mmvec";
28304let Constraints = "$Rx32 = $Rx32in";
28305}
28306def V6_vL32b_nt_tmp_pred_ppu : HInst<
28307(outs HvxVR:$Vd32, IntRegs:$Rx32),
28308(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28309"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt",
28310tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28311let Inst{10-5} = 0b000110;
28312let Inst{31-21} = 0b00101011110;
28313let isPredicated = 1;
28314let hasNewValue = 1;
28315let opNewValue = 0;
28316let addrMode = PostInc;
28317let accessSize = HVXVectorAccess;
28318let isCVLoad = 1;
28319let isCVI = 1;
28320let hasTmpDst = 1;
28321let mayLoad = 1;
28322let isNonTemporal = 1;
28323let isRestrictNoSlot1Store = 1;
28324let BaseOpcode = "V6_vL32b_nt_tmp_ppu";
28325let DecoderNamespace = "EXT_mmvec";
28326let Constraints = "$Rx32 = $Rx32in";
28327}
28328def V6_vL32b_pi : HInst<
28329(outs HvxVR:$Vd32, IntRegs:$Rx32),
28330(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28331"$Vd32 = vmem($Rx32++#$Ii)",
28332tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28333let Inst{7-5} = 0b000;
28334let Inst{13-11} = 0b000;
28335let Inst{31-21} = 0b00101001000;
28336let hasNewValue = 1;
28337let opNewValue = 0;
28338let addrMode = PostInc;
28339let accessSize = HVXVectorAccess;
28340let isCVLoad = 1;
28341let isCVI = 1;
28342let mayLoad = 1;
28343let isRestrictNoSlot1Store = 1;
28344let BaseOpcode = "V6_vL32b_pi";
28345let isCVLoadable = 1;
28346let isPredicable = 1;
28347let DecoderNamespace = "EXT_mmvec";
28348let Constraints = "$Rx32 = $Rx32in";
28349}
28350def V6_vL32b_ppu : HInst<
28351(outs HvxVR:$Vd32, IntRegs:$Rx32),
28352(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28353"$Vd32 = vmem($Rx32++$Mu2)",
28354tc_1ba8a0cd, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28355let Inst{12-5} = 0b00000000;
28356let Inst{31-21} = 0b00101011000;
28357let hasNewValue = 1;
28358let opNewValue = 0;
28359let addrMode = PostInc;
28360let accessSize = HVXVectorAccess;
28361let isCVLoad = 1;
28362let isCVI = 1;
28363let mayLoad = 1;
28364let isRestrictNoSlot1Store = 1;
28365let BaseOpcode = "V6_vL32b_ppu";
28366let isCVLoadable = 1;
28367let isPredicable = 1;
28368let DecoderNamespace = "EXT_mmvec";
28369let Constraints = "$Rx32 = $Rx32in";
28370}
28371def V6_vL32b_pred_ai : HInst<
28372(outs HvxVR:$Vd32),
28373(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28374"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)",
28375tc_abe8c3b2, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28376let Inst{7-5} = 0b010;
28377let Inst{31-21} = 0b00101000100;
28378let isPredicated = 1;
28379let hasNewValue = 1;
28380let opNewValue = 0;
28381let addrMode = BaseImmOffset;
28382let accessSize = HVXVectorAccess;
28383let isCVLoad = 1;
28384let isCVI = 1;
28385let mayLoad = 1;
28386let isRestrictNoSlot1Store = 1;
28387let BaseOpcode = "V6_vL32b_ai";
28388let DecoderNamespace = "EXT_mmvec";
28389}
28390def V6_vL32b_pred_pi : HInst<
28391(outs HvxVR:$Vd32, IntRegs:$Rx32),
28392(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28393"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)",
28394tc_453fe68d, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28395let Inst{7-5} = 0b010;
28396let Inst{13-13} = 0b0;
28397let Inst{31-21} = 0b00101001100;
28398let isPredicated = 1;
28399let hasNewValue = 1;
28400let opNewValue = 0;
28401let addrMode = PostInc;
28402let accessSize = HVXVectorAccess;
28403let isCVLoad = 1;
28404let isCVI = 1;
28405let mayLoad = 1;
28406let isRestrictNoSlot1Store = 1;
28407let BaseOpcode = "V6_vL32b_pi";
28408let DecoderNamespace = "EXT_mmvec";
28409let Constraints = "$Rx32 = $Rx32in";
28410}
28411def V6_vL32b_pred_ppu : HInst<
28412(outs HvxVR:$Vd32, IntRegs:$Rx32),
28413(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28414"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)",
28415tc_453fe68d, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28416let Inst{10-5} = 0b000010;
28417let Inst{31-21} = 0b00101011100;
28418let isPredicated = 1;
28419let hasNewValue = 1;
28420let opNewValue = 0;
28421let addrMode = PostInc;
28422let accessSize = HVXVectorAccess;
28423let isCVLoad = 1;
28424let isCVI = 1;
28425let mayLoad = 1;
28426let isRestrictNoSlot1Store = 1;
28427let BaseOpcode = "V6_vL32b_ppu";
28428let DecoderNamespace = "EXT_mmvec";
28429let Constraints = "$Rx32 = $Rx32in";
28430}
28431def V6_vL32b_tmp_ai : HInst<
28432(outs HvxVR:$Vd32),
28433(ins IntRegs:$Rt32, s4_0Imm:$Ii),
28434"$Vd32.tmp = vmem($Rt32+#$Ii)",
28435tc_52447ecc, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel {
28436let Inst{7-5} = 0b010;
28437let Inst{12-11} = 0b00;
28438let Inst{31-21} = 0b00101000000;
28439let hasNewValue = 1;
28440let opNewValue = 0;
28441let addrMode = BaseImmOffset;
28442let accessSize = HVXVectorAccess;
28443let isCVLoad = 1;
28444let isCVI = 1;
28445let hasTmpDst = 1;
28446let mayLoad = 1;
28447let isRestrictNoSlot1Store = 1;
28448let BaseOpcode = "V6_vL32b_tmp_ai";
28449let isPredicable = 1;
28450let DecoderNamespace = "EXT_mmvec";
28451}
28452def V6_vL32b_tmp_npred_ai : HInst<
28453(outs HvxVR:$Vd32),
28454(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28455"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28456tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28457let Inst{7-5} = 0b111;
28458let Inst{31-21} = 0b00101000100;
28459let isPredicated = 1;
28460let isPredicatedFalse = 1;
28461let hasNewValue = 1;
28462let opNewValue = 0;
28463let addrMode = BaseImmOffset;
28464let accessSize = HVXVectorAccess;
28465let isCVLoad = 1;
28466let isCVI = 1;
28467let hasTmpDst = 1;
28468let mayLoad = 1;
28469let isRestrictNoSlot1Store = 1;
28470let BaseOpcode = "V6_vL32b_tmp_ai";
28471let DecoderNamespace = "EXT_mmvec";
28472}
28473def V6_vL32b_tmp_npred_pi : HInst<
28474(outs HvxVR:$Vd32, IntRegs:$Rx32),
28475(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28476"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28477tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28478let Inst{7-5} = 0b111;
28479let Inst{13-13} = 0b0;
28480let Inst{31-21} = 0b00101001100;
28481let isPredicated = 1;
28482let isPredicatedFalse = 1;
28483let hasNewValue = 1;
28484let opNewValue = 0;
28485let addrMode = PostInc;
28486let accessSize = HVXVectorAccess;
28487let isCVLoad = 1;
28488let isCVI = 1;
28489let hasTmpDst = 1;
28490let mayLoad = 1;
28491let isRestrictNoSlot1Store = 1;
28492let BaseOpcode = "V6_vL32b_tmp_pi";
28493let DecoderNamespace = "EXT_mmvec";
28494let Constraints = "$Rx32 = $Rx32in";
28495}
28496def V6_vL32b_tmp_npred_ppu : HInst<
28497(outs HvxVR:$Vd32, IntRegs:$Rx32),
28498(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28499"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28500tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28501let Inst{10-5} = 0b000111;
28502let Inst{31-21} = 0b00101011100;
28503let isPredicated = 1;
28504let isPredicatedFalse = 1;
28505let hasNewValue = 1;
28506let opNewValue = 0;
28507let addrMode = PostInc;
28508let accessSize = HVXVectorAccess;
28509let isCVLoad = 1;
28510let isCVI = 1;
28511let hasTmpDst = 1;
28512let mayLoad = 1;
28513let isRestrictNoSlot1Store = 1;
28514let BaseOpcode = "V6_vL32b_tmp_ppu";
28515let DecoderNamespace = "EXT_mmvec";
28516let Constraints = "$Rx32 = $Rx32in";
28517}
28518def V6_vL32b_tmp_pi : HInst<
28519(outs HvxVR:$Vd32, IntRegs:$Rx32),
28520(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
28521"$Vd32.tmp = vmem($Rx32++#$Ii)",
28522tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel {
28523let Inst{7-5} = 0b010;
28524let Inst{13-11} = 0b000;
28525let Inst{31-21} = 0b00101001000;
28526let hasNewValue = 1;
28527let opNewValue = 0;
28528let addrMode = PostInc;
28529let accessSize = HVXVectorAccess;
28530let isCVLoad = 1;
28531let isCVI = 1;
28532let hasTmpDst = 1;
28533let mayLoad = 1;
28534let isRestrictNoSlot1Store = 1;
28535let BaseOpcode = "V6_vL32b_tmp_pi";
28536let isPredicable = 1;
28537let DecoderNamespace = "EXT_mmvec";
28538let Constraints = "$Rx32 = $Rx32in";
28539}
28540def V6_vL32b_tmp_ppu : HInst<
28541(outs HvxVR:$Vd32, IntRegs:$Rx32),
28542(ins IntRegs:$Rx32in, ModRegs:$Mu2),
28543"$Vd32.tmp = vmem($Rx32++$Mu2)",
28544tc_663c80a7, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel {
28545let Inst{12-5} = 0b00000010;
28546let Inst{31-21} = 0b00101011000;
28547let hasNewValue = 1;
28548let opNewValue = 0;
28549let addrMode = PostInc;
28550let accessSize = HVXVectorAccess;
28551let isCVLoad = 1;
28552let isCVI = 1;
28553let hasTmpDst = 1;
28554let mayLoad = 1;
28555let isRestrictNoSlot1Store = 1;
28556let BaseOpcode = "V6_vL32b_tmp_ppu";
28557let isPredicable = 1;
28558let DecoderNamespace = "EXT_mmvec";
28559let Constraints = "$Rx32 = $Rx32in";
28560}
28561def V6_vL32b_tmp_pred_ai : HInst<
28562(outs HvxVR:$Vd32),
28563(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
28564"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)",
28565tc_3904b926, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel {
28566let Inst{7-5} = 0b110;
28567let Inst{31-21} = 0b00101000100;
28568let isPredicated = 1;
28569let hasNewValue = 1;
28570let opNewValue = 0;
28571let addrMode = BaseImmOffset;
28572let accessSize = HVXVectorAccess;
28573let isCVLoad = 1;
28574let isCVI = 1;
28575let hasTmpDst = 1;
28576let mayLoad = 1;
28577let isRestrictNoSlot1Store = 1;
28578let BaseOpcode = "V6_vL32b_tmp_ai";
28579let DecoderNamespace = "EXT_mmvec";
28580}
28581def V6_vL32b_tmp_pred_pi : HInst<
28582(outs HvxVR:$Vd32, IntRegs:$Rx32),
28583(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
28584"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)",
28585tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel {
28586let Inst{7-5} = 0b110;
28587let Inst{13-13} = 0b0;
28588let Inst{31-21} = 0b00101001100;
28589let isPredicated = 1;
28590let hasNewValue = 1;
28591let opNewValue = 0;
28592let addrMode = PostInc;
28593let accessSize = HVXVectorAccess;
28594let isCVLoad = 1;
28595let isCVI = 1;
28596let hasTmpDst = 1;
28597let mayLoad = 1;
28598let isRestrictNoSlot1Store = 1;
28599let BaseOpcode = "V6_vL32b_tmp_pi";
28600let DecoderNamespace = "EXT_mmvec";
28601let Constraints = "$Rx32 = $Rx32in";
28602}
28603def V6_vL32b_tmp_pred_ppu : HInst<
28604(outs HvxVR:$Vd32, IntRegs:$Rx32),
28605(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
28606"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)",
28607tc_b9db8205, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel {
28608let Inst{10-5} = 0b000110;
28609let Inst{31-21} = 0b00101011100;
28610let isPredicated = 1;
28611let hasNewValue = 1;
28612let opNewValue = 0;
28613let addrMode = PostInc;
28614let accessSize = HVXVectorAccess;
28615let isCVLoad = 1;
28616let isCVI = 1;
28617let hasTmpDst = 1;
28618let mayLoad = 1;
28619let isRestrictNoSlot1Store = 1;
28620let BaseOpcode = "V6_vL32b_tmp_ppu";
28621let DecoderNamespace = "EXT_mmvec";
28622let Constraints = "$Rx32 = $Rx32in";
28623}
28624def V6_vS32Ub_ai : HInst<
28625(outs),
28626(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28627"vmemu($Rt32+#$Ii) = $Vs32",
28628tc_f21e8abb, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28629let Inst{7-5} = 0b111;
28630let Inst{12-11} = 0b00;
28631let Inst{31-21} = 0b00101000001;
28632let addrMode = BaseImmOffset;
28633let accessSize = HVXVectorAccess;
28634let isCVI = 1;
28635let mayStore = 1;
28636let BaseOpcode = "V6_vS32Ub_ai";
28637let isPredicable = 1;
28638let DecoderNamespace = "EXT_mmvec";
28639}
28640def V6_vS32Ub_npred_ai : HInst<
28641(outs),
28642(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28643"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28644tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28645let Inst{7-5} = 0b111;
28646let Inst{31-21} = 0b00101000101;
28647let isPredicated = 1;
28648let isPredicatedFalse = 1;
28649let addrMode = BaseImmOffset;
28650let accessSize = HVXVectorAccess;
28651let isCVI = 1;
28652let mayStore = 1;
28653let BaseOpcode = "V6_vS32Ub_ai";
28654let DecoderNamespace = "EXT_mmvec";
28655}
28656def V6_vS32Ub_npred_pi : HInst<
28657(outs IntRegs:$Rx32),
28658(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28659"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28660tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28661let Inst{7-5} = 0b111;
28662let Inst{13-13} = 0b0;
28663let Inst{31-21} = 0b00101001101;
28664let isPredicated = 1;
28665let isPredicatedFalse = 1;
28666let addrMode = PostInc;
28667let accessSize = HVXVectorAccess;
28668let isCVI = 1;
28669let mayStore = 1;
28670let BaseOpcode = "V6_vS32Ub_pi";
28671let DecoderNamespace = "EXT_mmvec";
28672let Constraints = "$Rx32 = $Rx32in";
28673}
28674def V6_vS32Ub_npred_ppu : HInst<
28675(outs IntRegs:$Rx32),
28676(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28677"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28678tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28679let Inst{10-5} = 0b000111;
28680let Inst{31-21} = 0b00101011101;
28681let isPredicated = 1;
28682let isPredicatedFalse = 1;
28683let addrMode = PostInc;
28684let accessSize = HVXVectorAccess;
28685let isCVI = 1;
28686let mayStore = 1;
28687let BaseOpcode = "V6_vS32Ub_ppu";
28688let DecoderNamespace = "EXT_mmvec";
28689let Constraints = "$Rx32 = $Rx32in";
28690}
28691def V6_vS32Ub_pi : HInst<
28692(outs IntRegs:$Rx32),
28693(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28694"vmemu($Rx32++#$Ii) = $Vs32",
28695tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
28696let Inst{7-5} = 0b111;
28697let Inst{13-11} = 0b000;
28698let Inst{31-21} = 0b00101001001;
28699let addrMode = PostInc;
28700let accessSize = HVXVectorAccess;
28701let isCVI = 1;
28702let mayStore = 1;
28703let BaseOpcode = "V6_vS32Ub_pi";
28704let isPredicable = 1;
28705let DecoderNamespace = "EXT_mmvec";
28706let Constraints = "$Rx32 = $Rx32in";
28707}
28708def V6_vS32Ub_ppu : HInst<
28709(outs IntRegs:$Rx32),
28710(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28711"vmemu($Rx32++$Mu2) = $Vs32",
28712tc_e2d2e9e5, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
28713let Inst{12-5} = 0b00000111;
28714let Inst{31-21} = 0b00101011001;
28715let addrMode = PostInc;
28716let accessSize = HVXVectorAccess;
28717let isCVI = 1;
28718let mayStore = 1;
28719let BaseOpcode = "V6_vS32Ub_ppu";
28720let isPredicable = 1;
28721let DecoderNamespace = "EXT_mmvec";
28722let Constraints = "$Rx32 = $Rx32in";
28723}
28724def V6_vS32Ub_pred_ai : HInst<
28725(outs),
28726(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28727"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32",
28728tc_131f1c81, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28729let Inst{7-5} = 0b110;
28730let Inst{31-21} = 0b00101000101;
28731let isPredicated = 1;
28732let addrMode = BaseImmOffset;
28733let accessSize = HVXVectorAccess;
28734let isCVI = 1;
28735let mayStore = 1;
28736let BaseOpcode = "V6_vS32Ub_ai";
28737let DecoderNamespace = "EXT_mmvec";
28738}
28739def V6_vS32Ub_pred_pi : HInst<
28740(outs IntRegs:$Rx32),
28741(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28742"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32",
28743tc_c7039829, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28744let Inst{7-5} = 0b110;
28745let Inst{13-13} = 0b0;
28746let Inst{31-21} = 0b00101001101;
28747let isPredicated = 1;
28748let addrMode = PostInc;
28749let accessSize = HVXVectorAccess;
28750let isCVI = 1;
28751let mayStore = 1;
28752let BaseOpcode = "V6_vS32Ub_pi";
28753let DecoderNamespace = "EXT_mmvec";
28754let Constraints = "$Rx32 = $Rx32in";
28755}
28756def V6_vS32Ub_pred_ppu : HInst<
28757(outs IntRegs:$Rx32),
28758(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
28759"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32",
28760tc_c7039829, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
28761let Inst{10-5} = 0b000110;
28762let Inst{31-21} = 0b00101011101;
28763let isPredicated = 1;
28764let addrMode = PostInc;
28765let accessSize = HVXVectorAccess;
28766let isCVI = 1;
28767let mayStore = 1;
28768let BaseOpcode = "V6_vS32Ub_ppu";
28769let DecoderNamespace = "EXT_mmvec";
28770let Constraints = "$Rx32 = $Rx32in";
28771}
28772def V6_vS32b_ai : HInst<
28773(outs),
28774(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28775"vmem($Rt32+#$Ii) = $Vs32",
28776tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
28777let Inst{7-5} = 0b000;
28778let Inst{12-11} = 0b00;
28779let Inst{31-21} = 0b00101000001;
28780let addrMode = BaseImmOffset;
28781let accessSize = HVXVectorAccess;
28782let isCVI = 1;
28783let mayStore = 1;
28784let BaseOpcode = "V6_vS32b_ai";
28785let isNVStorable = 1;
28786let isPredicable = 1;
28787let DecoderNamespace = "EXT_mmvec";
28788}
28789def V6_vS32b_new_ai : HInst<
28790(outs),
28791(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28792"vmem($Rt32+#$Ii) = $Os8.new",
28793tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
28794let Inst{7-3} = 0b00100;
28795let Inst{12-11} = 0b00;
28796let Inst{31-21} = 0b00101000001;
28797let addrMode = BaseImmOffset;
28798let accessSize = HVXVectorAccess;
28799let isNVStore = 1;
28800let isCVI = 1;
28801let CVINew = 1;
28802let isNewValue = 1;
28803let mayStore = 1;
28804let BaseOpcode = "V6_vS32b_ai";
28805let isPredicable = 1;
28806let DecoderNamespace = "EXT_mmvec";
28807let opNewValue = 2;
28808}
28809def V6_vS32b_new_npred_ai : HInst<
28810(outs),
28811(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28812"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28813tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28814let Inst{7-3} = 0b01101;
28815let Inst{31-21} = 0b00101000101;
28816let isPredicated = 1;
28817let isPredicatedFalse = 1;
28818let addrMode = BaseImmOffset;
28819let accessSize = HVXVectorAccess;
28820let isNVStore = 1;
28821let isCVI = 1;
28822let CVINew = 1;
28823let isNewValue = 1;
28824let mayStore = 1;
28825let BaseOpcode = "V6_vS32b_ai";
28826let DecoderNamespace = "EXT_mmvec";
28827let opNewValue = 3;
28828}
28829def V6_vS32b_new_npred_pi : HInst<
28830(outs IntRegs:$Rx32),
28831(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28832"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28833tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28834let Inst{7-3} = 0b01101;
28835let Inst{13-13} = 0b0;
28836let Inst{31-21} = 0b00101001101;
28837let isPredicated = 1;
28838let isPredicatedFalse = 1;
28839let addrMode = PostInc;
28840let accessSize = HVXVectorAccess;
28841let isNVStore = 1;
28842let isCVI = 1;
28843let CVINew = 1;
28844let isNewValue = 1;
28845let mayStore = 1;
28846let BaseOpcode = "V6_vS32b_pi";
28847let DecoderNamespace = "EXT_mmvec";
28848let opNewValue = 4;
28849let Constraints = "$Rx32 = $Rx32in";
28850}
28851def V6_vS32b_new_npred_ppu : HInst<
28852(outs IntRegs:$Rx32),
28853(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28854"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28855tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28856let Inst{10-3} = 0b00001101;
28857let Inst{31-21} = 0b00101011101;
28858let isPredicated = 1;
28859let isPredicatedFalse = 1;
28860let addrMode = PostInc;
28861let accessSize = HVXVectorAccess;
28862let isNVStore = 1;
28863let isCVI = 1;
28864let CVINew = 1;
28865let isNewValue = 1;
28866let mayStore = 1;
28867let BaseOpcode = "V6_vS32b_ppu";
28868let DecoderNamespace = "EXT_mmvec";
28869let opNewValue = 4;
28870let Constraints = "$Rx32 = $Rx32in";
28871}
28872def V6_vS32b_new_pi : HInst<
28873(outs IntRegs:$Rx32),
28874(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28875"vmem($Rx32++#$Ii) = $Os8.new",
28876tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
28877let Inst{7-3} = 0b00100;
28878let Inst{13-11} = 0b000;
28879let Inst{31-21} = 0b00101001001;
28880let addrMode = PostInc;
28881let accessSize = HVXVectorAccess;
28882let isNVStore = 1;
28883let isCVI = 1;
28884let CVINew = 1;
28885let isNewValue = 1;
28886let mayStore = 1;
28887let BaseOpcode = "V6_vS32b_pi";
28888let isPredicable = 1;
28889let DecoderNamespace = "EXT_mmvec";
28890let opNewValue = 3;
28891let Constraints = "$Rx32 = $Rx32in";
28892}
28893def V6_vS32b_new_ppu : HInst<
28894(outs IntRegs:$Rx32),
28895(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28896"vmem($Rx32++$Mu2) = $Os8.new",
28897tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
28898let Inst{12-3} = 0b0000000100;
28899let Inst{31-21} = 0b00101011001;
28900let addrMode = PostInc;
28901let accessSize = HVXVectorAccess;
28902let isNVStore = 1;
28903let isCVI = 1;
28904let CVINew = 1;
28905let isNewValue = 1;
28906let mayStore = 1;
28907let BaseOpcode = "V6_vS32b_ppu";
28908let isPredicable = 1;
28909let DecoderNamespace = "EXT_mmvec";
28910let opNewValue = 3;
28911let Constraints = "$Rx32 = $Rx32in";
28912}
28913def V6_vS32b_new_pred_ai : HInst<
28914(outs),
28915(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
28916"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new",
28917tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
28918let Inst{7-3} = 0b01000;
28919let Inst{31-21} = 0b00101000101;
28920let isPredicated = 1;
28921let addrMode = BaseImmOffset;
28922let accessSize = HVXVectorAccess;
28923let isNVStore = 1;
28924let isCVI = 1;
28925let CVINew = 1;
28926let isNewValue = 1;
28927let mayStore = 1;
28928let BaseOpcode = "V6_vS32b_ai";
28929let DecoderNamespace = "EXT_mmvec";
28930let opNewValue = 3;
28931}
28932def V6_vS32b_new_pred_pi : HInst<
28933(outs IntRegs:$Rx32),
28934(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
28935"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new",
28936tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
28937let Inst{7-3} = 0b01000;
28938let Inst{13-13} = 0b0;
28939let Inst{31-21} = 0b00101001101;
28940let isPredicated = 1;
28941let addrMode = PostInc;
28942let accessSize = HVXVectorAccess;
28943let isNVStore = 1;
28944let isCVI = 1;
28945let CVINew = 1;
28946let isNewValue = 1;
28947let mayStore = 1;
28948let BaseOpcode = "V6_vS32b_pi";
28949let DecoderNamespace = "EXT_mmvec";
28950let opNewValue = 4;
28951let Constraints = "$Rx32 = $Rx32in";
28952}
28953def V6_vS32b_new_pred_ppu : HInst<
28954(outs IntRegs:$Rx32),
28955(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
28956"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new",
28957tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
28958let Inst{10-3} = 0b00001000;
28959let Inst{31-21} = 0b00101011101;
28960let isPredicated = 1;
28961let addrMode = PostInc;
28962let accessSize = HVXVectorAccess;
28963let isNVStore = 1;
28964let isCVI = 1;
28965let CVINew = 1;
28966let isNewValue = 1;
28967let mayStore = 1;
28968let BaseOpcode = "V6_vS32b_ppu";
28969let DecoderNamespace = "EXT_mmvec";
28970let opNewValue = 4;
28971let Constraints = "$Rx32 = $Rx32in";
28972}
28973def V6_vS32b_npred_ai : HInst<
28974(outs),
28975(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
28976"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32",
28977tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
28978let Inst{7-5} = 0b001;
28979let Inst{31-21} = 0b00101000101;
28980let isPredicated = 1;
28981let isPredicatedFalse = 1;
28982let addrMode = BaseImmOffset;
28983let accessSize = HVXVectorAccess;
28984let isCVI = 1;
28985let mayStore = 1;
28986let BaseOpcode = "V6_vS32b_ai";
28987let isNVStorable = 1;
28988let DecoderNamespace = "EXT_mmvec";
28989}
28990def V6_vS32b_npred_pi : HInst<
28991(outs IntRegs:$Rx32),
28992(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
28993"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32",
28994tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
28995let Inst{7-5} = 0b001;
28996let Inst{13-13} = 0b0;
28997let Inst{31-21} = 0b00101001101;
28998let isPredicated = 1;
28999let isPredicatedFalse = 1;
29000let addrMode = PostInc;
29001let accessSize = HVXVectorAccess;
29002let isCVI = 1;
29003let mayStore = 1;
29004let BaseOpcode = "V6_vS32b_pi";
29005let isNVStorable = 1;
29006let DecoderNamespace = "EXT_mmvec";
29007let Constraints = "$Rx32 = $Rx32in";
29008}
29009def V6_vS32b_npred_ppu : HInst<
29010(outs IntRegs:$Rx32),
29011(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29012"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32",
29013tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29014let Inst{10-5} = 0b000001;
29015let Inst{31-21} = 0b00101011101;
29016let isPredicated = 1;
29017let isPredicatedFalse = 1;
29018let addrMode = PostInc;
29019let accessSize = HVXVectorAccess;
29020let isCVI = 1;
29021let mayStore = 1;
29022let BaseOpcode = "V6_vS32b_ppu";
29023let isNVStorable = 1;
29024let DecoderNamespace = "EXT_mmvec";
29025let Constraints = "$Rx32 = $Rx32in";
29026}
29027def V6_vS32b_nqpred_ai : HInst<
29028(outs),
29029(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29030"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32",
29031tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29032let Inst{7-5} = 0b001;
29033let Inst{31-21} = 0b00101000100;
29034let addrMode = BaseImmOffset;
29035let accessSize = HVXVectorAccess;
29036let isCVI = 1;
29037let mayStore = 1;
29038let DecoderNamespace = "EXT_mmvec";
29039}
29040def V6_vS32b_nqpred_pi : HInst<
29041(outs IntRegs:$Rx32),
29042(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29043"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32",
29044tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29045let Inst{7-5} = 0b001;
29046let Inst{13-13} = 0b0;
29047let Inst{31-21} = 0b00101001100;
29048let addrMode = PostInc;
29049let accessSize = HVXVectorAccess;
29050let isCVI = 1;
29051let mayStore = 1;
29052let DecoderNamespace = "EXT_mmvec";
29053let Constraints = "$Rx32 = $Rx32in";
29054}
29055def V6_vS32b_nqpred_ppu : HInst<
29056(outs IntRegs:$Rx32),
29057(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29058"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32",
29059tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29060let Inst{10-5} = 0b000001;
29061let Inst{31-21} = 0b00101011100;
29062let addrMode = PostInc;
29063let accessSize = HVXVectorAccess;
29064let isCVI = 1;
29065let mayStore = 1;
29066let DecoderNamespace = "EXT_mmvec";
29067let Constraints = "$Rx32 = $Rx32in";
29068}
29069def V6_vS32b_nt_ai : HInst<
29070(outs),
29071(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29072"vmem($Rt32+#$Ii):nt = $Vs32",
29073tc_c5dba46e, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel {
29074let Inst{7-5} = 0b000;
29075let Inst{12-11} = 0b00;
29076let Inst{31-21} = 0b00101000011;
29077let addrMode = BaseImmOffset;
29078let accessSize = HVXVectorAccess;
29079let isCVI = 1;
29080let isNonTemporal = 1;
29081let mayStore = 1;
29082let BaseOpcode = "V6_vS32b_ai";
29083let isNVStorable = 1;
29084let isPredicable = 1;
29085let DecoderNamespace = "EXT_mmvec";
29086}
29087def V6_vS32b_nt_new_ai : HInst<
29088(outs),
29089(ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29090"vmem($Rt32+#$Ii):nt = $Os8.new",
29091tc_ab23f776, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel {
29092let Inst{7-3} = 0b00100;
29093let Inst{12-11} = 0b00;
29094let Inst{31-21} = 0b00101000011;
29095let addrMode = BaseImmOffset;
29096let accessSize = HVXVectorAccess;
29097let isNVStore = 1;
29098let isCVI = 1;
29099let CVINew = 1;
29100let isNewValue = 1;
29101let isNonTemporal = 1;
29102let mayStore = 1;
29103let BaseOpcode = "V6_vS32b_ai";
29104let isPredicable = 1;
29105let DecoderNamespace = "EXT_mmvec";
29106let opNewValue = 2;
29107}
29108def V6_vS32b_nt_new_npred_ai : HInst<
29109(outs),
29110(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29111"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29112tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29113let Inst{7-3} = 0b01111;
29114let Inst{31-21} = 0b00101000111;
29115let isPredicated = 1;
29116let isPredicatedFalse = 1;
29117let addrMode = BaseImmOffset;
29118let accessSize = HVXVectorAccess;
29119let isNVStore = 1;
29120let isCVI = 1;
29121let CVINew = 1;
29122let isNewValue = 1;
29123let isNonTemporal = 1;
29124let mayStore = 1;
29125let BaseOpcode = "V6_vS32b_ai";
29126let DecoderNamespace = "EXT_mmvec";
29127let opNewValue = 3;
29128}
29129def V6_vS32b_nt_new_npred_pi : HInst<
29130(outs IntRegs:$Rx32),
29131(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29132"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29133tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29134let Inst{7-3} = 0b01111;
29135let Inst{13-13} = 0b0;
29136let Inst{31-21} = 0b00101001111;
29137let isPredicated = 1;
29138let isPredicatedFalse = 1;
29139let addrMode = PostInc;
29140let accessSize = HVXVectorAccess;
29141let isNVStore = 1;
29142let isCVI = 1;
29143let CVINew = 1;
29144let isNewValue = 1;
29145let isNonTemporal = 1;
29146let mayStore = 1;
29147let BaseOpcode = "V6_vS32b_pi";
29148let DecoderNamespace = "EXT_mmvec";
29149let opNewValue = 4;
29150let Constraints = "$Rx32 = $Rx32in";
29151}
29152def V6_vS32b_nt_new_npred_ppu : HInst<
29153(outs IntRegs:$Rx32),
29154(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29155"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29156tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29157let Inst{10-3} = 0b00001111;
29158let Inst{31-21} = 0b00101011111;
29159let isPredicated = 1;
29160let isPredicatedFalse = 1;
29161let addrMode = PostInc;
29162let accessSize = HVXVectorAccess;
29163let isNVStore = 1;
29164let isCVI = 1;
29165let CVINew = 1;
29166let isNewValue = 1;
29167let isNonTemporal = 1;
29168let mayStore = 1;
29169let BaseOpcode = "V6_vS32b_ppu";
29170let DecoderNamespace = "EXT_mmvec";
29171let opNewValue = 4;
29172let Constraints = "$Rx32 = $Rx32in";
29173}
29174def V6_vS32b_nt_new_pi : HInst<
29175(outs IntRegs:$Rx32),
29176(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29177"vmem($Rx32++#$Ii):nt = $Os8.new",
29178tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel {
29179let Inst{7-3} = 0b00100;
29180let Inst{13-11} = 0b000;
29181let Inst{31-21} = 0b00101001011;
29182let addrMode = PostInc;
29183let accessSize = HVXVectorAccess;
29184let isNVStore = 1;
29185let isCVI = 1;
29186let CVINew = 1;
29187let isNewValue = 1;
29188let isNonTemporal = 1;
29189let mayStore = 1;
29190let BaseOpcode = "V6_vS32b_pi";
29191let isPredicable = 1;
29192let DecoderNamespace = "EXT_mmvec";
29193let opNewValue = 3;
29194let Constraints = "$Rx32 = $Rx32in";
29195}
29196def V6_vS32b_nt_new_ppu : HInst<
29197(outs IntRegs:$Rx32),
29198(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29199"vmem($Rx32++$Mu2):nt = $Os8.new",
29200tc_6942b6e0, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel {
29201let Inst{12-3} = 0b0000000100;
29202let Inst{31-21} = 0b00101011011;
29203let addrMode = PostInc;
29204let accessSize = HVXVectorAccess;
29205let isNVStore = 1;
29206let isCVI = 1;
29207let CVINew = 1;
29208let isNewValue = 1;
29209let isNonTemporal = 1;
29210let mayStore = 1;
29211let BaseOpcode = "V6_vS32b_ppu";
29212let isPredicable = 1;
29213let DecoderNamespace = "EXT_mmvec";
29214let opNewValue = 3;
29215let Constraints = "$Rx32 = $Rx32in";
29216}
29217def V6_vS32b_nt_new_pred_ai : HInst<
29218(outs),
29219(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8),
29220"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new",
29221tc_7177e272, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel {
29222let Inst{7-3} = 0b01010;
29223let Inst{31-21} = 0b00101000111;
29224let isPredicated = 1;
29225let addrMode = BaseImmOffset;
29226let accessSize = HVXVectorAccess;
29227let isNVStore = 1;
29228let isCVI = 1;
29229let CVINew = 1;
29230let isNewValue = 1;
29231let isNonTemporal = 1;
29232let mayStore = 1;
29233let BaseOpcode = "V6_vS32b_ai";
29234let DecoderNamespace = "EXT_mmvec";
29235let opNewValue = 3;
29236}
29237def V6_vS32b_nt_new_pred_pi : HInst<
29238(outs IntRegs:$Rx32),
29239(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8),
29240"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new",
29241tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel {
29242let Inst{7-3} = 0b01010;
29243let Inst{13-13} = 0b0;
29244let Inst{31-21} = 0b00101001111;
29245let isPredicated = 1;
29246let addrMode = PostInc;
29247let accessSize = HVXVectorAccess;
29248let isNVStore = 1;
29249let isCVI = 1;
29250let CVINew = 1;
29251let isNewValue = 1;
29252let isNonTemporal = 1;
29253let mayStore = 1;
29254let BaseOpcode = "V6_vS32b_pi";
29255let DecoderNamespace = "EXT_mmvec";
29256let opNewValue = 4;
29257let Constraints = "$Rx32 = $Rx32in";
29258}
29259def V6_vS32b_nt_new_pred_ppu : HInst<
29260(outs IntRegs:$Rx32),
29261(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8),
29262"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new",
29263tc_e99d4c2e, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel {
29264let Inst{10-3} = 0b00001010;
29265let Inst{31-21} = 0b00101011111;
29266let isPredicated = 1;
29267let addrMode = PostInc;
29268let accessSize = HVXVectorAccess;
29269let isNVStore = 1;
29270let isCVI = 1;
29271let CVINew = 1;
29272let isNewValue = 1;
29273let isNonTemporal = 1;
29274let mayStore = 1;
29275let BaseOpcode = "V6_vS32b_ppu";
29276let DecoderNamespace = "EXT_mmvec";
29277let opNewValue = 4;
29278let Constraints = "$Rx32 = $Rx32in";
29279}
29280def V6_vS32b_nt_npred_ai : HInst<
29281(outs),
29282(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29283"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29284tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29285let Inst{7-5} = 0b001;
29286let Inst{31-21} = 0b00101000111;
29287let isPredicated = 1;
29288let isPredicatedFalse = 1;
29289let addrMode = BaseImmOffset;
29290let accessSize = HVXVectorAccess;
29291let isCVI = 1;
29292let isNonTemporal = 1;
29293let mayStore = 1;
29294let BaseOpcode = "V6_vS32b_ai";
29295let isNVStorable = 1;
29296let DecoderNamespace = "EXT_mmvec";
29297}
29298def V6_vS32b_nt_npred_pi : HInst<
29299(outs IntRegs:$Rx32),
29300(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29301"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29302tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29303let Inst{7-5} = 0b001;
29304let Inst{13-13} = 0b0;
29305let Inst{31-21} = 0b00101001111;
29306let isPredicated = 1;
29307let isPredicatedFalse = 1;
29308let addrMode = PostInc;
29309let accessSize = HVXVectorAccess;
29310let isCVI = 1;
29311let isNonTemporal = 1;
29312let mayStore = 1;
29313let BaseOpcode = "V6_vS32b_pi";
29314let isNVStorable = 1;
29315let DecoderNamespace = "EXT_mmvec";
29316let Constraints = "$Rx32 = $Rx32in";
29317}
29318def V6_vS32b_nt_npred_ppu : HInst<
29319(outs IntRegs:$Rx32),
29320(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29321"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29322tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29323let Inst{10-5} = 0b000001;
29324let Inst{31-21} = 0b00101011111;
29325let isPredicated = 1;
29326let isPredicatedFalse = 1;
29327let addrMode = PostInc;
29328let accessSize = HVXVectorAccess;
29329let isCVI = 1;
29330let isNonTemporal = 1;
29331let mayStore = 1;
29332let BaseOpcode = "V6_vS32b_ppu";
29333let isNVStorable = 1;
29334let DecoderNamespace = "EXT_mmvec";
29335let Constraints = "$Rx32 = $Rx32in";
29336}
29337def V6_vS32b_nt_nqpred_ai : HInst<
29338(outs),
29339(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29340"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29341tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29342let Inst{7-5} = 0b001;
29343let Inst{31-21} = 0b00101000110;
29344let addrMode = BaseImmOffset;
29345let accessSize = HVXVectorAccess;
29346let isCVI = 1;
29347let isNonTemporal = 1;
29348let mayStore = 1;
29349let DecoderNamespace = "EXT_mmvec";
29350}
29351def V6_vS32b_nt_nqpred_pi : HInst<
29352(outs IntRegs:$Rx32),
29353(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29354"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29355tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29356let Inst{7-5} = 0b001;
29357let Inst{13-13} = 0b0;
29358let Inst{31-21} = 0b00101001110;
29359let addrMode = PostInc;
29360let accessSize = HVXVectorAccess;
29361let isCVI = 1;
29362let isNonTemporal = 1;
29363let mayStore = 1;
29364let DecoderNamespace = "EXT_mmvec";
29365let Constraints = "$Rx32 = $Rx32in";
29366}
29367def V6_vS32b_nt_nqpred_ppu : HInst<
29368(outs IntRegs:$Rx32),
29369(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29370"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29371tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29372let Inst{10-5} = 0b000001;
29373let Inst{31-21} = 0b00101011110;
29374let addrMode = PostInc;
29375let accessSize = HVXVectorAccess;
29376let isCVI = 1;
29377let isNonTemporal = 1;
29378let mayStore = 1;
29379let DecoderNamespace = "EXT_mmvec";
29380let Constraints = "$Rx32 = $Rx32in";
29381}
29382def V6_vS32b_nt_pi : HInst<
29383(outs IntRegs:$Rx32),
29384(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29385"vmem($Rx32++#$Ii):nt = $Vs32",
29386tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
29387let Inst{7-5} = 0b000;
29388let Inst{13-11} = 0b000;
29389let Inst{31-21} = 0b00101001011;
29390let addrMode = PostInc;
29391let accessSize = HVXVectorAccess;
29392let isCVI = 1;
29393let isNonTemporal = 1;
29394let mayStore = 1;
29395let BaseOpcode = "V6_vS32b_pi";
29396let isNVStorable = 1;
29397let isPredicable = 1;
29398let DecoderNamespace = "EXT_mmvec";
29399let Constraints = "$Rx32 = $Rx32in";
29400}
29401def V6_vS32b_nt_ppu : HInst<
29402(outs IntRegs:$Rx32),
29403(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29404"vmem($Rx32++$Mu2):nt = $Vs32",
29405tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29406let Inst{12-5} = 0b00000000;
29407let Inst{31-21} = 0b00101011011;
29408let addrMode = PostInc;
29409let accessSize = HVXVectorAccess;
29410let isCVI = 1;
29411let isNonTemporal = 1;
29412let mayStore = 1;
29413let BaseOpcode = "V6_vS32b_ppu";
29414let isNVStorable = 1;
29415let isPredicable = 1;
29416let DecoderNamespace = "EXT_mmvec";
29417let Constraints = "$Rx32 = $Rx32in";
29418}
29419def V6_vS32b_nt_pred_ai : HInst<
29420(outs),
29421(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29422"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32",
29423tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29424let Inst{7-5} = 0b000;
29425let Inst{31-21} = 0b00101000111;
29426let isPredicated = 1;
29427let addrMode = BaseImmOffset;
29428let accessSize = HVXVectorAccess;
29429let isCVI = 1;
29430let isNonTemporal = 1;
29431let mayStore = 1;
29432let BaseOpcode = "V6_vS32b_ai";
29433let isNVStorable = 1;
29434let DecoderNamespace = "EXT_mmvec";
29435}
29436def V6_vS32b_nt_pred_pi : HInst<
29437(outs IntRegs:$Rx32),
29438(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29439"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32",
29440tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29441let Inst{7-5} = 0b000;
29442let Inst{13-13} = 0b0;
29443let Inst{31-21} = 0b00101001111;
29444let isPredicated = 1;
29445let addrMode = PostInc;
29446let accessSize = HVXVectorAccess;
29447let isCVI = 1;
29448let isNonTemporal = 1;
29449let mayStore = 1;
29450let BaseOpcode = "V6_vS32b_pi";
29451let isNVStorable = 1;
29452let DecoderNamespace = "EXT_mmvec";
29453let Constraints = "$Rx32 = $Rx32in";
29454}
29455def V6_vS32b_nt_pred_ppu : HInst<
29456(outs IntRegs:$Rx32),
29457(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29458"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32",
29459tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29460let Inst{10-5} = 0b000000;
29461let Inst{31-21} = 0b00101011111;
29462let isPredicated = 1;
29463let addrMode = PostInc;
29464let accessSize = HVXVectorAccess;
29465let isCVI = 1;
29466let isNonTemporal = 1;
29467let mayStore = 1;
29468let BaseOpcode = "V6_vS32b_ppu";
29469let isNVStorable = 1;
29470let DecoderNamespace = "EXT_mmvec";
29471let Constraints = "$Rx32 = $Rx32in";
29472}
29473def V6_vS32b_nt_qpred_ai : HInst<
29474(outs),
29475(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29476"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32",
29477tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29478let Inst{7-5} = 0b000;
29479let Inst{31-21} = 0b00101000110;
29480let addrMode = BaseImmOffset;
29481let accessSize = HVXVectorAccess;
29482let isCVI = 1;
29483let isNonTemporal = 1;
29484let mayStore = 1;
29485let DecoderNamespace = "EXT_mmvec";
29486}
29487def V6_vS32b_nt_qpred_pi : HInst<
29488(outs IntRegs:$Rx32),
29489(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29490"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32",
29491tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29492let Inst{7-5} = 0b000;
29493let Inst{13-13} = 0b0;
29494let Inst{31-21} = 0b00101001110;
29495let addrMode = PostInc;
29496let accessSize = HVXVectorAccess;
29497let isCVI = 1;
29498let isNonTemporal = 1;
29499let mayStore = 1;
29500let DecoderNamespace = "EXT_mmvec";
29501let Constraints = "$Rx32 = $Rx32in";
29502}
29503def V6_vS32b_nt_qpred_ppu : HInst<
29504(outs IntRegs:$Rx32),
29505(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29506"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32",
29507tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29508let Inst{10-5} = 0b000000;
29509let Inst{31-21} = 0b00101011110;
29510let addrMode = PostInc;
29511let accessSize = HVXVectorAccess;
29512let isCVI = 1;
29513let isNonTemporal = 1;
29514let mayStore = 1;
29515let DecoderNamespace = "EXT_mmvec";
29516let Constraints = "$Rx32 = $Rx32in";
29517}
29518def V6_vS32b_pi : HInst<
29519(outs IntRegs:$Rx32),
29520(ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29521"vmem($Rx32++#$Ii) = $Vs32",
29522tc_3e2aaafc, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel {
29523let Inst{7-5} = 0b000;
29524let Inst{13-11} = 0b000;
29525let Inst{31-21} = 0b00101001001;
29526let addrMode = PostInc;
29527let accessSize = HVXVectorAccess;
29528let isCVI = 1;
29529let mayStore = 1;
29530let BaseOpcode = "V6_vS32b_pi";
29531let isNVStorable = 1;
29532let isPredicable = 1;
29533let DecoderNamespace = "EXT_mmvec";
29534let Constraints = "$Rx32 = $Rx32in";
29535}
29536def V6_vS32b_ppu : HInst<
29537(outs IntRegs:$Rx32),
29538(ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29539"vmem($Rx32++$Mu2) = $Vs32",
29540tc_3e2aaafc, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel {
29541let Inst{12-5} = 0b00000000;
29542let Inst{31-21} = 0b00101011001;
29543let addrMode = PostInc;
29544let accessSize = HVXVectorAccess;
29545let isCVI = 1;
29546let mayStore = 1;
29547let BaseOpcode = "V6_vS32b_ppu";
29548let isNVStorable = 1;
29549let isPredicable = 1;
29550let DecoderNamespace = "EXT_mmvec";
29551let Constraints = "$Rx32 = $Rx32in";
29552}
29553def V6_vS32b_pred_ai : HInst<
29554(outs),
29555(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29556"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32",
29557tc_a02a10a8, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel {
29558let Inst{7-5} = 0b000;
29559let Inst{31-21} = 0b00101000101;
29560let isPredicated = 1;
29561let addrMode = BaseImmOffset;
29562let accessSize = HVXVectorAccess;
29563let isCVI = 1;
29564let mayStore = 1;
29565let BaseOpcode = "V6_vS32b_ai";
29566let isNVStorable = 1;
29567let DecoderNamespace = "EXT_mmvec";
29568}
29569def V6_vS32b_pred_pi : HInst<
29570(outs IntRegs:$Rx32),
29571(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29572"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32",
29573tc_54a0dc47, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel {
29574let Inst{7-5} = 0b000;
29575let Inst{13-13} = 0b0;
29576let Inst{31-21} = 0b00101001101;
29577let isPredicated = 1;
29578let addrMode = PostInc;
29579let accessSize = HVXVectorAccess;
29580let isCVI = 1;
29581let mayStore = 1;
29582let BaseOpcode = "V6_vS32b_pi";
29583let isNVStorable = 1;
29584let DecoderNamespace = "EXT_mmvec";
29585let Constraints = "$Rx32 = $Rx32in";
29586}
29587def V6_vS32b_pred_ppu : HInst<
29588(outs IntRegs:$Rx32),
29589(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29590"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32",
29591tc_54a0dc47, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel {
29592let Inst{10-5} = 0b000000;
29593let Inst{31-21} = 0b00101011101;
29594let isPredicated = 1;
29595let addrMode = PostInc;
29596let accessSize = HVXVectorAccess;
29597let isCVI = 1;
29598let mayStore = 1;
29599let BaseOpcode = "V6_vS32b_ppu";
29600let isNVStorable = 1;
29601let DecoderNamespace = "EXT_mmvec";
29602let Constraints = "$Rx32 = $Rx32in";
29603}
29604def V6_vS32b_qpred_ai : HInst<
29605(outs),
29606(ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32),
29607"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32",
29608tc_447d9895, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> {
29609let Inst{7-5} = 0b000;
29610let Inst{31-21} = 0b00101000100;
29611let addrMode = BaseImmOffset;
29612let accessSize = HVXVectorAccess;
29613let isCVI = 1;
29614let mayStore = 1;
29615let DecoderNamespace = "EXT_mmvec";
29616}
29617def V6_vS32b_qpred_pi : HInst<
29618(outs IntRegs:$Rx32),
29619(ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32),
29620"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32",
29621tc_191381c1, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> {
29622let Inst{7-5} = 0b000;
29623let Inst{13-13} = 0b0;
29624let Inst{31-21} = 0b00101001100;
29625let addrMode = PostInc;
29626let accessSize = HVXVectorAccess;
29627let isCVI = 1;
29628let mayStore = 1;
29629let DecoderNamespace = "EXT_mmvec";
29630let Constraints = "$Rx32 = $Rx32in";
29631}
29632def V6_vS32b_qpred_ppu : HInst<
29633(outs IntRegs:$Rx32),
29634(ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32),
29635"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32",
29636tc_191381c1, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> {
29637let Inst{10-5} = 0b000000;
29638let Inst{31-21} = 0b00101011100;
29639let addrMode = PostInc;
29640let accessSize = HVXVectorAccess;
29641let isCVI = 1;
29642let mayStore = 1;
29643let DecoderNamespace = "EXT_mmvec";
29644let Constraints = "$Rx32 = $Rx32in";
29645}
29646def V6_vS32b_srls_ai : HInst<
29647(outs),
29648(ins IntRegs:$Rt32, s4_0Imm:$Ii),
29649"vmem($Rt32+#$Ii):scatter_release",
29650tc_3ce09744, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> {
29651let Inst{7-0} = 0b00101000;
29652let Inst{12-11} = 0b00;
29653let Inst{31-21} = 0b00101000001;
29654let addrMode = BaseImmOffset;
29655let accessSize = HVXVectorAccess;
29656let isCVI = 1;
29657let CVINew = 1;
29658let mayStore = 1;
29659let DecoderNamespace = "EXT_mmvec";
29660}
29661def V6_vS32b_srls_pi : HInst<
29662(outs IntRegs:$Rx32),
29663(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
29664"vmem($Rx32++#$Ii):scatter_release",
29665tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> {
29666let Inst{7-0} = 0b00101000;
29667let Inst{13-11} = 0b000;
29668let Inst{31-21} = 0b00101001001;
29669let addrMode = PostInc;
29670let accessSize = HVXVectorAccess;
29671let isCVI = 1;
29672let CVINew = 1;
29673let mayStore = 1;
29674let DecoderNamespace = "EXT_mmvec";
29675let Constraints = "$Rx32 = $Rx32in";
29676}
29677def V6_vS32b_srls_ppu : HInst<
29678(outs IntRegs:$Rx32),
29679(ins IntRegs:$Rx32in, ModRegs:$Mu2),
29680"vmem($Rx32++$Mu2):scatter_release",
29681tc_20a4bbec, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> {
29682let Inst{12-0} = 0b0000000101000;
29683let Inst{31-21} = 0b00101011001;
29684let addrMode = PostInc;
29685let accessSize = HVXVectorAccess;
29686let isCVI = 1;
29687let CVINew = 1;
29688let mayStore = 1;
29689let DecoderNamespace = "EXT_mmvec";
29690let Constraints = "$Rx32 = $Rx32in";
29691}
29692def V6_vabsb : HInst<
29693(outs HvxVR:$Vd32),
29694(ins HvxVR:$Vu32),
29695"$Vd32.b = vabs($Vu32.b)",
29696tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29697let Inst{7-5} = 0b100;
29698let Inst{13-13} = 0b0;
29699let Inst{31-16} = 0b0001111000000001;
29700let hasNewValue = 1;
29701let opNewValue = 0;
29702let isCVI = 1;
29703let DecoderNamespace = "EXT_mmvec";
29704}
29705def V6_vabsb_alt : HInst<
29706(outs HvxVR:$Vd32),
29707(ins HvxVR:$Vu32),
29708"$Vd32 = vabsb($Vu32)",
29709PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29710let hasNewValue = 1;
29711let opNewValue = 0;
29712let isCVI = 1;
29713let isPseudo = 1;
29714let isCodeGenOnly = 1;
29715let DecoderNamespace = "EXT_mmvec";
29716}
29717def V6_vabsb_sat : HInst<
29718(outs HvxVR:$Vd32),
29719(ins HvxVR:$Vu32),
29720"$Vd32.b = vabs($Vu32.b):sat",
29721tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> {
29722let Inst{7-5} = 0b101;
29723let Inst{13-13} = 0b0;
29724let Inst{31-16} = 0b0001111000000001;
29725let hasNewValue = 1;
29726let opNewValue = 0;
29727let isCVI = 1;
29728let DecoderNamespace = "EXT_mmvec";
29729}
29730def V6_vabsb_sat_alt : HInst<
29731(outs HvxVR:$Vd32),
29732(ins HvxVR:$Vu32),
29733"$Vd32 = vabsb($Vu32):sat",
29734PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
29735let hasNewValue = 1;
29736let opNewValue = 0;
29737let isCVI = 1;
29738let isPseudo = 1;
29739let isCodeGenOnly = 1;
29740let DecoderNamespace = "EXT_mmvec";
29741}
29742def V6_vabsdiffh : HInst<
29743(outs HvxVR:$Vd32),
29744(ins HvxVR:$Vu32, HvxVR:$Vv32),
29745"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)",
29746tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29747let Inst{7-5} = 0b001;
29748let Inst{13-13} = 0b0;
29749let Inst{31-21} = 0b00011100110;
29750let hasNewValue = 1;
29751let opNewValue = 0;
29752let isCVI = 1;
29753let DecoderNamespace = "EXT_mmvec";
29754}
29755def V6_vabsdiffh_alt : HInst<
29756(outs HvxVR:$Vd32),
29757(ins HvxVR:$Vu32, HvxVR:$Vv32),
29758"$Vd32 = vabsdiffh($Vu32,$Vv32)",
29759PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29760let hasNewValue = 1;
29761let opNewValue = 0;
29762let isCVI = 1;
29763let isPseudo = 1;
29764let isCodeGenOnly = 1;
29765let DecoderNamespace = "EXT_mmvec";
29766}
29767def V6_vabsdiffub : HInst<
29768(outs HvxVR:$Vd32),
29769(ins HvxVR:$Vu32, HvxVR:$Vv32),
29770"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)",
29771tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29772let Inst{7-5} = 0b000;
29773let Inst{13-13} = 0b0;
29774let Inst{31-21} = 0b00011100110;
29775let hasNewValue = 1;
29776let opNewValue = 0;
29777let isCVI = 1;
29778let DecoderNamespace = "EXT_mmvec";
29779}
29780def V6_vabsdiffub_alt : HInst<
29781(outs HvxVR:$Vd32),
29782(ins HvxVR:$Vu32, HvxVR:$Vv32),
29783"$Vd32 = vabsdiffub($Vu32,$Vv32)",
29784PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29785let hasNewValue = 1;
29786let opNewValue = 0;
29787let isCVI = 1;
29788let isPseudo = 1;
29789let isCodeGenOnly = 1;
29790let DecoderNamespace = "EXT_mmvec";
29791}
29792def V6_vabsdiffuh : HInst<
29793(outs HvxVR:$Vd32),
29794(ins HvxVR:$Vu32, HvxVR:$Vv32),
29795"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)",
29796tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29797let Inst{7-5} = 0b010;
29798let Inst{13-13} = 0b0;
29799let Inst{31-21} = 0b00011100110;
29800let hasNewValue = 1;
29801let opNewValue = 0;
29802let isCVI = 1;
29803let DecoderNamespace = "EXT_mmvec";
29804}
29805def V6_vabsdiffuh_alt : HInst<
29806(outs HvxVR:$Vd32),
29807(ins HvxVR:$Vu32, HvxVR:$Vv32),
29808"$Vd32 = vabsdiffuh($Vu32,$Vv32)",
29809PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29810let hasNewValue = 1;
29811let opNewValue = 0;
29812let isCVI = 1;
29813let isPseudo = 1;
29814let isCodeGenOnly = 1;
29815let DecoderNamespace = "EXT_mmvec";
29816}
29817def V6_vabsdiffw : HInst<
29818(outs HvxVR:$Vd32),
29819(ins HvxVR:$Vu32, HvxVR:$Vv32),
29820"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)",
29821tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
29822let Inst{7-5} = 0b011;
29823let Inst{13-13} = 0b0;
29824let Inst{31-21} = 0b00011100110;
29825let hasNewValue = 1;
29826let opNewValue = 0;
29827let isCVI = 1;
29828let DecoderNamespace = "EXT_mmvec";
29829}
29830def V6_vabsdiffw_alt : HInst<
29831(outs HvxVR:$Vd32),
29832(ins HvxVR:$Vu32, HvxVR:$Vv32),
29833"$Vd32 = vabsdiffw($Vu32,$Vv32)",
29834PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29835let hasNewValue = 1;
29836let opNewValue = 0;
29837let isCVI = 1;
29838let isPseudo = 1;
29839let isCodeGenOnly = 1;
29840let DecoderNamespace = "EXT_mmvec";
29841}
29842def V6_vabsh : HInst<
29843(outs HvxVR:$Vd32),
29844(ins HvxVR:$Vu32),
29845"$Vd32.h = vabs($Vu32.h)",
29846tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29847let Inst{7-5} = 0b000;
29848let Inst{13-13} = 0b0;
29849let Inst{31-16} = 0b0001111000000000;
29850let hasNewValue = 1;
29851let opNewValue = 0;
29852let isCVI = 1;
29853let DecoderNamespace = "EXT_mmvec";
29854}
29855def V6_vabsh_alt : HInst<
29856(outs HvxVR:$Vd32),
29857(ins HvxVR:$Vu32),
29858"$Vd32 = vabsh($Vu32)",
29859PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29860let hasNewValue = 1;
29861let opNewValue = 0;
29862let isCVI = 1;
29863let isPseudo = 1;
29864let isCodeGenOnly = 1;
29865let DecoderNamespace = "EXT_mmvec";
29866}
29867def V6_vabsh_sat : HInst<
29868(outs HvxVR:$Vd32),
29869(ins HvxVR:$Vu32),
29870"$Vd32.h = vabs($Vu32.h):sat",
29871tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29872let Inst{7-5} = 0b001;
29873let Inst{13-13} = 0b0;
29874let Inst{31-16} = 0b0001111000000000;
29875let hasNewValue = 1;
29876let opNewValue = 0;
29877let isCVI = 1;
29878let DecoderNamespace = "EXT_mmvec";
29879}
29880def V6_vabsh_sat_alt : HInst<
29881(outs HvxVR:$Vd32),
29882(ins HvxVR:$Vu32),
29883"$Vd32 = vabsh($Vu32):sat",
29884PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29885let hasNewValue = 1;
29886let opNewValue = 0;
29887let isCVI = 1;
29888let isPseudo = 1;
29889let isCodeGenOnly = 1;
29890let DecoderNamespace = "EXT_mmvec";
29891}
29892def V6_vabsub_alt : HInst<
29893(outs HvxVR:$Vd32),
29894(ins HvxVR:$Vu32),
29895"$Vd32.ub = vabs($Vu32.b)",
29896tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29897let hasNewValue = 1;
29898let opNewValue = 0;
29899let isCVI = 1;
29900let isPseudo = 1;
29901let isCodeGenOnly = 1;
29902let DecoderNamespace = "EXT_mmvec";
29903}
29904def V6_vabsuh_alt : HInst<
29905(outs HvxVR:$Vd32),
29906(ins HvxVR:$Vu32),
29907"$Vd32.uh = vabs($Vu32.h)",
29908tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29909let hasNewValue = 1;
29910let opNewValue = 0;
29911let isCVI = 1;
29912let isPseudo = 1;
29913let isCodeGenOnly = 1;
29914let DecoderNamespace = "EXT_mmvec";
29915}
29916def V6_vabsuw_alt : HInst<
29917(outs HvxVR:$Vd32),
29918(ins HvxVR:$Vu32),
29919"$Vd32.uw = vabs($Vu32.w)",
29920tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> {
29921let hasNewValue = 1;
29922let opNewValue = 0;
29923let isCVI = 1;
29924let isPseudo = 1;
29925let isCodeGenOnly = 1;
29926let DecoderNamespace = "EXT_mmvec";
29927}
29928def V6_vabsw : HInst<
29929(outs HvxVR:$Vd32),
29930(ins HvxVR:$Vu32),
29931"$Vd32.w = vabs($Vu32.w)",
29932tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29933let Inst{7-5} = 0b010;
29934let Inst{13-13} = 0b0;
29935let Inst{31-16} = 0b0001111000000000;
29936let hasNewValue = 1;
29937let opNewValue = 0;
29938let isCVI = 1;
29939let DecoderNamespace = "EXT_mmvec";
29940}
29941def V6_vabsw_alt : HInst<
29942(outs HvxVR:$Vd32),
29943(ins HvxVR:$Vu32),
29944"$Vd32 = vabsw($Vu32)",
29945PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29946let hasNewValue = 1;
29947let opNewValue = 0;
29948let isCVI = 1;
29949let isPseudo = 1;
29950let isCodeGenOnly = 1;
29951let DecoderNamespace = "EXT_mmvec";
29952}
29953def V6_vabsw_sat : HInst<
29954(outs HvxVR:$Vd32),
29955(ins HvxVR:$Vu32),
29956"$Vd32.w = vabs($Vu32.w):sat",
29957tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
29958let Inst{7-5} = 0b011;
29959let Inst{13-13} = 0b0;
29960let Inst{31-16} = 0b0001111000000000;
29961let hasNewValue = 1;
29962let opNewValue = 0;
29963let isCVI = 1;
29964let DecoderNamespace = "EXT_mmvec";
29965}
29966def V6_vabsw_sat_alt : HInst<
29967(outs HvxVR:$Vd32),
29968(ins HvxVR:$Vu32),
29969"$Vd32 = vabsw($Vu32):sat",
29970PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29971let hasNewValue = 1;
29972let opNewValue = 0;
29973let isCVI = 1;
29974let isPseudo = 1;
29975let isCodeGenOnly = 1;
29976let DecoderNamespace = "EXT_mmvec";
29977}
29978def V6_vaddb : HInst<
29979(outs HvxVR:$Vd32),
29980(ins HvxVR:$Vu32, HvxVR:$Vv32),
29981"$Vd32.b = vadd($Vu32.b,$Vv32.b)",
29982tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
29983let Inst{7-5} = 0b110;
29984let Inst{13-13} = 0b0;
29985let Inst{31-21} = 0b00011111101;
29986let hasNewValue = 1;
29987let opNewValue = 0;
29988let isCVI = 1;
29989let DecoderNamespace = "EXT_mmvec";
29990}
29991def V6_vaddb_alt : HInst<
29992(outs HvxVR:$Vd32),
29993(ins HvxVR:$Vu32, HvxVR:$Vv32),
29994"$Vd32 = vaddb($Vu32,$Vv32)",
29995PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
29996let hasNewValue = 1;
29997let opNewValue = 0;
29998let isCVI = 1;
29999let isPseudo = 1;
30000let isCodeGenOnly = 1;
30001let DecoderNamespace = "EXT_mmvec";
30002}
30003def V6_vaddb_dv : HInst<
30004(outs HvxWR:$Vdd32),
30005(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30006"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)",
30007tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30008let Inst{7-5} = 0b100;
30009let Inst{13-13} = 0b0;
30010let Inst{31-21} = 0b00011100011;
30011let hasNewValue = 1;
30012let opNewValue = 0;
30013let isCVI = 1;
30014let DecoderNamespace = "EXT_mmvec";
30015}
30016def V6_vaddb_dv_alt : HInst<
30017(outs HvxWR:$Vdd32),
30018(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30019"$Vdd32 = vaddb($Vuu32,$Vvv32)",
30020PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30021let hasNewValue = 1;
30022let opNewValue = 0;
30023let isCVI = 1;
30024let isPseudo = 1;
30025let isCodeGenOnly = 1;
30026let DecoderNamespace = "EXT_mmvec";
30027}
30028def V6_vaddbnq : HInst<
30029(outs HvxVR:$Vx32),
30030(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30031"if (!$Qv4) $Vx32.b += $Vu32.b",
30032tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30033let Inst{7-5} = 0b011;
30034let Inst{13-13} = 0b1;
30035let Inst{21-16} = 0b000001;
30036let Inst{31-24} = 0b00011110;
30037let hasNewValue = 1;
30038let opNewValue = 0;
30039let isAccumulator = 1;
30040let isCVI = 1;
30041let DecoderNamespace = "EXT_mmvec";
30042let Constraints = "$Vx32 = $Vx32in";
30043}
30044def V6_vaddbnq_alt : HInst<
30045(outs HvxVR:$Vx32),
30046(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30047"if (!$Qv4.b) $Vx32.b += $Vu32.b",
30048PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30049let hasNewValue = 1;
30050let opNewValue = 0;
30051let isAccumulator = 1;
30052let isCVI = 1;
30053let isPseudo = 1;
30054let isCodeGenOnly = 1;
30055let DecoderNamespace = "EXT_mmvec";
30056let Constraints = "$Vx32 = $Vx32in";
30057}
30058def V6_vaddbq : HInst<
30059(outs HvxVR:$Vx32),
30060(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30061"if ($Qv4) $Vx32.b += $Vu32.b",
30062tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30063let Inst{7-5} = 0b000;
30064let Inst{13-13} = 0b1;
30065let Inst{21-16} = 0b000001;
30066let Inst{31-24} = 0b00011110;
30067let hasNewValue = 1;
30068let opNewValue = 0;
30069let isAccumulator = 1;
30070let isCVI = 1;
30071let DecoderNamespace = "EXT_mmvec";
30072let Constraints = "$Vx32 = $Vx32in";
30073}
30074def V6_vaddbq_alt : HInst<
30075(outs HvxVR:$Vx32),
30076(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30077"if ($Qv4.b) $Vx32.b += $Vu32.b",
30078PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30079let hasNewValue = 1;
30080let opNewValue = 0;
30081let isAccumulator = 1;
30082let isCVI = 1;
30083let isPseudo = 1;
30084let isCodeGenOnly = 1;
30085let DecoderNamespace = "EXT_mmvec";
30086let Constraints = "$Vx32 = $Vx32in";
30087}
30088def V6_vaddbsat : HInst<
30089(outs HvxVR:$Vd32),
30090(ins HvxVR:$Vu32, HvxVR:$Vv32),
30091"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat",
30092tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30093let Inst{7-5} = 0b000;
30094let Inst{13-13} = 0b0;
30095let Inst{31-21} = 0b00011111000;
30096let hasNewValue = 1;
30097let opNewValue = 0;
30098let isCVI = 1;
30099let DecoderNamespace = "EXT_mmvec";
30100}
30101def V6_vaddbsat_alt : HInst<
30102(outs HvxVR:$Vd32),
30103(ins HvxVR:$Vu32, HvxVR:$Vv32),
30104"$Vd32 = vaddb($Vu32,$Vv32):sat",
30105PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30106let hasNewValue = 1;
30107let opNewValue = 0;
30108let isCVI = 1;
30109let isPseudo = 1;
30110let isCodeGenOnly = 1;
30111let DecoderNamespace = "EXT_mmvec";
30112}
30113def V6_vaddbsat_dv : HInst<
30114(outs HvxWR:$Vdd32),
30115(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30116"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat",
30117tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30118let Inst{7-5} = 0b000;
30119let Inst{13-13} = 0b0;
30120let Inst{31-21} = 0b00011110101;
30121let hasNewValue = 1;
30122let opNewValue = 0;
30123let isCVI = 1;
30124let DecoderNamespace = "EXT_mmvec";
30125}
30126def V6_vaddbsat_dv_alt : HInst<
30127(outs HvxWR:$Vdd32),
30128(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30129"$Vdd32 = vaddb($Vuu32,$Vvv32):sat",
30130PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30131let hasNewValue = 1;
30132let opNewValue = 0;
30133let isCVI = 1;
30134let isPseudo = 1;
30135let isCodeGenOnly = 1;
30136let DecoderNamespace = "EXT_mmvec";
30137}
30138def V6_vaddcarry : HInst<
30139(outs HvxVR:$Vd32, HvxQR:$Qx4),
30140(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
30141"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry",
30142tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
30143let Inst{7-7} = 0b0;
30144let Inst{13-13} = 0b1;
30145let Inst{31-21} = 0b00011100101;
30146let hasNewValue = 1;
30147let opNewValue = 0;
30148let isCVI = 1;
30149let DecoderNamespace = "EXT_mmvec";
30150let Constraints = "$Qx4 = $Qx4in";
30151}
30152def V6_vaddcarryo : HInst<
30153(outs HvxVR:$Vd32, HvxQR:$Qe4),
30154(ins HvxVR:$Vu32, HvxVR:$Vv32),
30155"$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry",
30156tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
30157let Inst{7-7} = 0b0;
30158let Inst{13-13} = 0b1;
30159let Inst{31-21} = 0b00011101101;
30160let hasNewValue = 1;
30161let opNewValue = 0;
30162let hasNewValue2 = 1;
30163let opNewValue2 = 1;
30164let isCVI = 1;
30165let DecoderNamespace = "EXT_mmvec";
30166}
30167def V6_vaddcarrysat : HInst<
30168(outs HvxVR:$Vd32),
30169(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qs4),
30170"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qs4):carry:sat",
30171tc_257f6f7c, TypeCVI_VA>, Enc_e0820b, Requires<[UseHVXV66]> {
30172let Inst{7-7} = 0b0;
30173let Inst{13-13} = 0b1;
30174let Inst{31-21} = 0b00011101100;
30175let hasNewValue = 1;
30176let opNewValue = 0;
30177let isCVI = 1;
30178let DecoderNamespace = "EXT_mmvec";
30179}
30180def V6_vaddclbh : HInst<
30181(outs HvxVR:$Vd32),
30182(ins HvxVR:$Vu32, HvxVR:$Vv32),
30183"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)",
30184tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30185let Inst{7-5} = 0b000;
30186let Inst{13-13} = 0b1;
30187let Inst{31-21} = 0b00011111000;
30188let hasNewValue = 1;
30189let opNewValue = 0;
30190let isCVI = 1;
30191let DecoderNamespace = "EXT_mmvec";
30192}
30193def V6_vaddclbw : HInst<
30194(outs HvxVR:$Vd32),
30195(ins HvxVR:$Vu32, HvxVR:$Vv32),
30196"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)",
30197tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
30198let Inst{7-5} = 0b001;
30199let Inst{13-13} = 0b1;
30200let Inst{31-21} = 0b00011111000;
30201let hasNewValue = 1;
30202let opNewValue = 0;
30203let isCVI = 1;
30204let DecoderNamespace = "EXT_mmvec";
30205}
30206def V6_vaddh : HInst<
30207(outs HvxVR:$Vd32),
30208(ins HvxVR:$Vu32, HvxVR:$Vv32),
30209"$Vd32.h = vadd($Vu32.h,$Vv32.h)",
30210tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30211let Inst{7-5} = 0b111;
30212let Inst{13-13} = 0b0;
30213let Inst{31-21} = 0b00011111101;
30214let hasNewValue = 1;
30215let opNewValue = 0;
30216let isCVI = 1;
30217let DecoderNamespace = "EXT_mmvec";
30218}
30219def V6_vaddh_alt : HInst<
30220(outs HvxVR:$Vd32),
30221(ins HvxVR:$Vu32, HvxVR:$Vv32),
30222"$Vd32 = vaddh($Vu32,$Vv32)",
30223PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30224let hasNewValue = 1;
30225let opNewValue = 0;
30226let isCVI = 1;
30227let isPseudo = 1;
30228let isCodeGenOnly = 1;
30229let DecoderNamespace = "EXT_mmvec";
30230}
30231def V6_vaddh_dv : HInst<
30232(outs HvxWR:$Vdd32),
30233(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30234"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)",
30235tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30236let Inst{7-5} = 0b101;
30237let Inst{13-13} = 0b0;
30238let Inst{31-21} = 0b00011100011;
30239let hasNewValue = 1;
30240let opNewValue = 0;
30241let isCVI = 1;
30242let DecoderNamespace = "EXT_mmvec";
30243}
30244def V6_vaddh_dv_alt : HInst<
30245(outs HvxWR:$Vdd32),
30246(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30247"$Vdd32 = vaddh($Vuu32,$Vvv32)",
30248PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30249let hasNewValue = 1;
30250let opNewValue = 0;
30251let isCVI = 1;
30252let isPseudo = 1;
30253let isCodeGenOnly = 1;
30254let DecoderNamespace = "EXT_mmvec";
30255}
30256def V6_vaddhnq : HInst<
30257(outs HvxVR:$Vx32),
30258(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30259"if (!$Qv4) $Vx32.h += $Vu32.h",
30260tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30261let Inst{7-5} = 0b100;
30262let Inst{13-13} = 0b1;
30263let Inst{21-16} = 0b000001;
30264let Inst{31-24} = 0b00011110;
30265let hasNewValue = 1;
30266let opNewValue = 0;
30267let isAccumulator = 1;
30268let isCVI = 1;
30269let DecoderNamespace = "EXT_mmvec";
30270let Constraints = "$Vx32 = $Vx32in";
30271}
30272def V6_vaddhnq_alt : HInst<
30273(outs HvxVR:$Vx32),
30274(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30275"if (!$Qv4.h) $Vx32.h += $Vu32.h",
30276PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30277let hasNewValue = 1;
30278let opNewValue = 0;
30279let isAccumulator = 1;
30280let isCVI = 1;
30281let isPseudo = 1;
30282let isCodeGenOnly = 1;
30283let DecoderNamespace = "EXT_mmvec";
30284let Constraints = "$Vx32 = $Vx32in";
30285}
30286def V6_vaddhq : HInst<
30287(outs HvxVR:$Vx32),
30288(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30289"if ($Qv4) $Vx32.h += $Vu32.h",
30290tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30291let Inst{7-5} = 0b001;
30292let Inst{13-13} = 0b1;
30293let Inst{21-16} = 0b000001;
30294let Inst{31-24} = 0b00011110;
30295let hasNewValue = 1;
30296let opNewValue = 0;
30297let isAccumulator = 1;
30298let isCVI = 1;
30299let DecoderNamespace = "EXT_mmvec";
30300let Constraints = "$Vx32 = $Vx32in";
30301}
30302def V6_vaddhq_alt : HInst<
30303(outs HvxVR:$Vx32),
30304(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30305"if ($Qv4.h) $Vx32.h += $Vu32.h",
30306PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30307let hasNewValue = 1;
30308let opNewValue = 0;
30309let isAccumulator = 1;
30310let isCVI = 1;
30311let isPseudo = 1;
30312let isCodeGenOnly = 1;
30313let DecoderNamespace = "EXT_mmvec";
30314let Constraints = "$Vx32 = $Vx32in";
30315}
30316def V6_vaddhsat : HInst<
30317(outs HvxVR:$Vd32),
30318(ins HvxVR:$Vu32, HvxVR:$Vv32),
30319"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat",
30320tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30321let Inst{7-5} = 0b011;
30322let Inst{13-13} = 0b0;
30323let Inst{31-21} = 0b00011100010;
30324let hasNewValue = 1;
30325let opNewValue = 0;
30326let isCVI = 1;
30327let DecoderNamespace = "EXT_mmvec";
30328}
30329def V6_vaddhsat_alt : HInst<
30330(outs HvxVR:$Vd32),
30331(ins HvxVR:$Vu32, HvxVR:$Vv32),
30332"$Vd32 = vaddh($Vu32,$Vv32):sat",
30333PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30334let hasNewValue = 1;
30335let opNewValue = 0;
30336let isCVI = 1;
30337let isPseudo = 1;
30338let isCodeGenOnly = 1;
30339let DecoderNamespace = "EXT_mmvec";
30340}
30341def V6_vaddhsat_dv : HInst<
30342(outs HvxWR:$Vdd32),
30343(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30344"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat",
30345tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30346let Inst{7-5} = 0b001;
30347let Inst{13-13} = 0b0;
30348let Inst{31-21} = 0b00011100100;
30349let hasNewValue = 1;
30350let opNewValue = 0;
30351let isCVI = 1;
30352let DecoderNamespace = "EXT_mmvec";
30353}
30354def V6_vaddhsat_dv_alt : HInst<
30355(outs HvxWR:$Vdd32),
30356(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30357"$Vdd32 = vaddh($Vuu32,$Vvv32):sat",
30358PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30359let hasNewValue = 1;
30360let opNewValue = 0;
30361let isCVI = 1;
30362let isPseudo = 1;
30363let isCodeGenOnly = 1;
30364let DecoderNamespace = "EXT_mmvec";
30365}
30366def V6_vaddhw : HInst<
30367(outs HvxWR:$Vdd32),
30368(ins HvxVR:$Vu32, HvxVR:$Vv32),
30369"$Vdd32.w = vadd($Vu32.h,$Vv32.h)",
30370tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30371let Inst{7-5} = 0b100;
30372let Inst{13-13} = 0b0;
30373let Inst{31-21} = 0b00011100101;
30374let hasNewValue = 1;
30375let opNewValue = 0;
30376let isCVI = 1;
30377let DecoderNamespace = "EXT_mmvec";
30378}
30379def V6_vaddhw_acc : HInst<
30380(outs HvxWR:$Vxx32),
30381(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30382"$Vxx32.w += vadd($Vu32.h,$Vv32.h)",
30383tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30384let Inst{7-5} = 0b010;
30385let Inst{13-13} = 0b1;
30386let Inst{31-21} = 0b00011100001;
30387let hasNewValue = 1;
30388let opNewValue = 0;
30389let isAccumulator = 1;
30390let isCVI = 1;
30391let DecoderNamespace = "EXT_mmvec";
30392let Constraints = "$Vxx32 = $Vxx32in";
30393}
30394def V6_vaddhw_acc_alt : HInst<
30395(outs HvxWR:$Vxx32),
30396(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30397"$Vxx32 += vaddh($Vu32,$Vv32)",
30398PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30399let hasNewValue = 1;
30400let opNewValue = 0;
30401let isAccumulator = 1;
30402let isCVI = 1;
30403let isPseudo = 1;
30404let isCodeGenOnly = 1;
30405let DecoderNamespace = "EXT_mmvec";
30406let Constraints = "$Vxx32 = $Vxx32in";
30407}
30408def V6_vaddhw_alt : HInst<
30409(outs HvxWR:$Vdd32),
30410(ins HvxVR:$Vu32, HvxVR:$Vv32),
30411"$Vdd32 = vaddh($Vu32,$Vv32)",
30412PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30413let hasNewValue = 1;
30414let opNewValue = 0;
30415let isCVI = 1;
30416let isPseudo = 1;
30417let isCodeGenOnly = 1;
30418let DecoderNamespace = "EXT_mmvec";
30419}
30420def V6_vaddubh : HInst<
30421(outs HvxWR:$Vdd32),
30422(ins HvxVR:$Vu32, HvxVR:$Vv32),
30423"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)",
30424tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30425let Inst{7-5} = 0b010;
30426let Inst{13-13} = 0b0;
30427let Inst{31-21} = 0b00011100101;
30428let hasNewValue = 1;
30429let opNewValue = 0;
30430let isCVI = 1;
30431let DecoderNamespace = "EXT_mmvec";
30432}
30433def V6_vaddubh_acc : HInst<
30434(outs HvxWR:$Vxx32),
30435(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30436"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)",
30437tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30438let Inst{7-5} = 0b101;
30439let Inst{13-13} = 0b1;
30440let Inst{31-21} = 0b00011100010;
30441let hasNewValue = 1;
30442let opNewValue = 0;
30443let isAccumulator = 1;
30444let isCVI = 1;
30445let DecoderNamespace = "EXT_mmvec";
30446let Constraints = "$Vxx32 = $Vxx32in";
30447}
30448def V6_vaddubh_acc_alt : HInst<
30449(outs HvxWR:$Vxx32),
30450(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30451"$Vxx32 += vaddub($Vu32,$Vv32)",
30452PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30453let hasNewValue = 1;
30454let opNewValue = 0;
30455let isAccumulator = 1;
30456let isCVI = 1;
30457let isPseudo = 1;
30458let isCodeGenOnly = 1;
30459let DecoderNamespace = "EXT_mmvec";
30460let Constraints = "$Vxx32 = $Vxx32in";
30461}
30462def V6_vaddubh_alt : HInst<
30463(outs HvxWR:$Vdd32),
30464(ins HvxVR:$Vu32, HvxVR:$Vv32),
30465"$Vdd32 = vaddub($Vu32,$Vv32)",
30466PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30467let hasNewValue = 1;
30468let opNewValue = 0;
30469let isCVI = 1;
30470let isPseudo = 1;
30471let isCodeGenOnly = 1;
30472let DecoderNamespace = "EXT_mmvec";
30473}
30474def V6_vaddubsat : HInst<
30475(outs HvxVR:$Vd32),
30476(ins HvxVR:$Vu32, HvxVR:$Vv32),
30477"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat",
30478tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30479let Inst{7-5} = 0b001;
30480let Inst{13-13} = 0b0;
30481let Inst{31-21} = 0b00011100010;
30482let hasNewValue = 1;
30483let opNewValue = 0;
30484let isCVI = 1;
30485let DecoderNamespace = "EXT_mmvec";
30486}
30487def V6_vaddubsat_alt : HInst<
30488(outs HvxVR:$Vd32),
30489(ins HvxVR:$Vu32, HvxVR:$Vv32),
30490"$Vd32 = vaddub($Vu32,$Vv32):sat",
30491PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30492let hasNewValue = 1;
30493let opNewValue = 0;
30494let isCVI = 1;
30495let isPseudo = 1;
30496let isCodeGenOnly = 1;
30497let DecoderNamespace = "EXT_mmvec";
30498}
30499def V6_vaddubsat_dv : HInst<
30500(outs HvxWR:$Vdd32),
30501(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30502"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat",
30503tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30504let Inst{7-5} = 0b111;
30505let Inst{13-13} = 0b0;
30506let Inst{31-21} = 0b00011100011;
30507let hasNewValue = 1;
30508let opNewValue = 0;
30509let isCVI = 1;
30510let DecoderNamespace = "EXT_mmvec";
30511}
30512def V6_vaddubsat_dv_alt : HInst<
30513(outs HvxWR:$Vdd32),
30514(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30515"$Vdd32 = vaddub($Vuu32,$Vvv32):sat",
30516PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30517let hasNewValue = 1;
30518let opNewValue = 0;
30519let isCVI = 1;
30520let isPseudo = 1;
30521let isCodeGenOnly = 1;
30522let DecoderNamespace = "EXT_mmvec";
30523}
30524def V6_vaddububb_sat : HInst<
30525(outs HvxVR:$Vd32),
30526(ins HvxVR:$Vu32, HvxVR:$Vv32),
30527"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat",
30528tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30529let Inst{7-5} = 0b100;
30530let Inst{13-13} = 0b0;
30531let Inst{31-21} = 0b00011110101;
30532let hasNewValue = 1;
30533let opNewValue = 0;
30534let isCVI = 1;
30535let DecoderNamespace = "EXT_mmvec";
30536}
30537def V6_vadduhsat : HInst<
30538(outs HvxVR:$Vd32),
30539(ins HvxVR:$Vu32, HvxVR:$Vv32),
30540"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat",
30541tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30542let Inst{7-5} = 0b010;
30543let Inst{13-13} = 0b0;
30544let Inst{31-21} = 0b00011100010;
30545let hasNewValue = 1;
30546let opNewValue = 0;
30547let isCVI = 1;
30548let DecoderNamespace = "EXT_mmvec";
30549}
30550def V6_vadduhsat_alt : HInst<
30551(outs HvxVR:$Vd32),
30552(ins HvxVR:$Vu32, HvxVR:$Vv32),
30553"$Vd32 = vadduh($Vu32,$Vv32):sat",
30554PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30555let hasNewValue = 1;
30556let opNewValue = 0;
30557let isCVI = 1;
30558let isPseudo = 1;
30559let isCodeGenOnly = 1;
30560let DecoderNamespace = "EXT_mmvec";
30561}
30562def V6_vadduhsat_dv : HInst<
30563(outs HvxWR:$Vdd32),
30564(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30565"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat",
30566tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30567let Inst{7-5} = 0b000;
30568let Inst{13-13} = 0b0;
30569let Inst{31-21} = 0b00011100100;
30570let hasNewValue = 1;
30571let opNewValue = 0;
30572let isCVI = 1;
30573let DecoderNamespace = "EXT_mmvec";
30574}
30575def V6_vadduhsat_dv_alt : HInst<
30576(outs HvxWR:$Vdd32),
30577(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30578"$Vdd32 = vadduh($Vuu32,$Vvv32):sat",
30579PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30580let hasNewValue = 1;
30581let opNewValue = 0;
30582let isCVI = 1;
30583let isPseudo = 1;
30584let isCodeGenOnly = 1;
30585let DecoderNamespace = "EXT_mmvec";
30586}
30587def V6_vadduhw : HInst<
30588(outs HvxWR:$Vdd32),
30589(ins HvxVR:$Vu32, HvxVR:$Vv32),
30590"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)",
30591tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
30592let Inst{7-5} = 0b011;
30593let Inst{13-13} = 0b0;
30594let Inst{31-21} = 0b00011100101;
30595let hasNewValue = 1;
30596let opNewValue = 0;
30597let isCVI = 1;
30598let DecoderNamespace = "EXT_mmvec";
30599}
30600def V6_vadduhw_acc : HInst<
30601(outs HvxWR:$Vxx32),
30602(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30603"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)",
30604tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
30605let Inst{7-5} = 0b100;
30606let Inst{13-13} = 0b1;
30607let Inst{31-21} = 0b00011100010;
30608let hasNewValue = 1;
30609let opNewValue = 0;
30610let isAccumulator = 1;
30611let isCVI = 1;
30612let DecoderNamespace = "EXT_mmvec";
30613let Constraints = "$Vxx32 = $Vxx32in";
30614}
30615def V6_vadduhw_acc_alt : HInst<
30616(outs HvxWR:$Vxx32),
30617(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
30618"$Vxx32 += vadduh($Vu32,$Vv32)",
30619PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30620let hasNewValue = 1;
30621let opNewValue = 0;
30622let isAccumulator = 1;
30623let isCVI = 1;
30624let isPseudo = 1;
30625let isCodeGenOnly = 1;
30626let DecoderNamespace = "EXT_mmvec";
30627let Constraints = "$Vxx32 = $Vxx32in";
30628}
30629def V6_vadduhw_alt : HInst<
30630(outs HvxWR:$Vdd32),
30631(ins HvxVR:$Vu32, HvxVR:$Vv32),
30632"$Vdd32 = vadduh($Vu32,$Vv32)",
30633PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30634let hasNewValue = 1;
30635let opNewValue = 0;
30636let isCVI = 1;
30637let isPseudo = 1;
30638let isCodeGenOnly = 1;
30639let DecoderNamespace = "EXT_mmvec";
30640}
30641def V6_vadduwsat : HInst<
30642(outs HvxVR:$Vd32),
30643(ins HvxVR:$Vu32, HvxVR:$Vv32),
30644"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat",
30645tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
30646let Inst{7-5} = 0b001;
30647let Inst{13-13} = 0b0;
30648let Inst{31-21} = 0b00011111011;
30649let hasNewValue = 1;
30650let opNewValue = 0;
30651let isCVI = 1;
30652let DecoderNamespace = "EXT_mmvec";
30653}
30654def V6_vadduwsat_alt : HInst<
30655(outs HvxVR:$Vd32),
30656(ins HvxVR:$Vu32, HvxVR:$Vv32),
30657"$Vd32 = vadduw($Vu32,$Vv32):sat",
30658PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30659let hasNewValue = 1;
30660let opNewValue = 0;
30661let isCVI = 1;
30662let isPseudo = 1;
30663let isCodeGenOnly = 1;
30664let DecoderNamespace = "EXT_mmvec";
30665}
30666def V6_vadduwsat_dv : HInst<
30667(outs HvxWR:$Vdd32),
30668(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30669"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat",
30670tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
30671let Inst{7-5} = 0b010;
30672let Inst{13-13} = 0b0;
30673let Inst{31-21} = 0b00011110101;
30674let hasNewValue = 1;
30675let opNewValue = 0;
30676let isCVI = 1;
30677let DecoderNamespace = "EXT_mmvec";
30678}
30679def V6_vadduwsat_dv_alt : HInst<
30680(outs HvxWR:$Vdd32),
30681(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30682"$Vdd32 = vadduw($Vuu32,$Vvv32):sat",
30683PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30684let hasNewValue = 1;
30685let opNewValue = 0;
30686let isCVI = 1;
30687let isPseudo = 1;
30688let isCodeGenOnly = 1;
30689let DecoderNamespace = "EXT_mmvec";
30690}
30691def V6_vaddw : HInst<
30692(outs HvxVR:$Vd32),
30693(ins HvxVR:$Vu32, HvxVR:$Vv32),
30694"$Vd32.w = vadd($Vu32.w,$Vv32.w)",
30695tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30696let Inst{7-5} = 0b000;
30697let Inst{13-13} = 0b0;
30698let Inst{31-21} = 0b00011100010;
30699let hasNewValue = 1;
30700let opNewValue = 0;
30701let isCVI = 1;
30702let DecoderNamespace = "EXT_mmvec";
30703}
30704def V6_vaddw_alt : HInst<
30705(outs HvxVR:$Vd32),
30706(ins HvxVR:$Vu32, HvxVR:$Vv32),
30707"$Vd32 = vaddw($Vu32,$Vv32)",
30708PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30709let hasNewValue = 1;
30710let opNewValue = 0;
30711let isCVI = 1;
30712let isPseudo = 1;
30713let isCodeGenOnly = 1;
30714let DecoderNamespace = "EXT_mmvec";
30715}
30716def V6_vaddw_dv : HInst<
30717(outs HvxWR:$Vdd32),
30718(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30719"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)",
30720tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30721let Inst{7-5} = 0b110;
30722let Inst{13-13} = 0b0;
30723let Inst{31-21} = 0b00011100011;
30724let hasNewValue = 1;
30725let opNewValue = 0;
30726let isCVI = 1;
30727let DecoderNamespace = "EXT_mmvec";
30728}
30729def V6_vaddw_dv_alt : HInst<
30730(outs HvxWR:$Vdd32),
30731(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30732"$Vdd32 = vaddw($Vuu32,$Vvv32)",
30733PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30734let hasNewValue = 1;
30735let opNewValue = 0;
30736let isCVI = 1;
30737let isPseudo = 1;
30738let isCodeGenOnly = 1;
30739let DecoderNamespace = "EXT_mmvec";
30740}
30741def V6_vaddwnq : HInst<
30742(outs HvxVR:$Vx32),
30743(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30744"if (!$Qv4) $Vx32.w += $Vu32.w",
30745tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30746let Inst{7-5} = 0b101;
30747let Inst{13-13} = 0b1;
30748let Inst{21-16} = 0b000001;
30749let Inst{31-24} = 0b00011110;
30750let hasNewValue = 1;
30751let opNewValue = 0;
30752let isAccumulator = 1;
30753let isCVI = 1;
30754let DecoderNamespace = "EXT_mmvec";
30755let Constraints = "$Vx32 = $Vx32in";
30756}
30757def V6_vaddwnq_alt : HInst<
30758(outs HvxVR:$Vx32),
30759(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30760"if (!$Qv4.w) $Vx32.w += $Vu32.w",
30761PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30762let hasNewValue = 1;
30763let opNewValue = 0;
30764let isAccumulator = 1;
30765let isCVI = 1;
30766let isPseudo = 1;
30767let isCodeGenOnly = 1;
30768let DecoderNamespace = "EXT_mmvec";
30769let Constraints = "$Vx32 = $Vx32in";
30770}
30771def V6_vaddwq : HInst<
30772(outs HvxVR:$Vx32),
30773(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30774"if ($Qv4) $Vx32.w += $Vu32.w",
30775tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
30776let Inst{7-5} = 0b010;
30777let Inst{13-13} = 0b1;
30778let Inst{21-16} = 0b000001;
30779let Inst{31-24} = 0b00011110;
30780let hasNewValue = 1;
30781let opNewValue = 0;
30782let isAccumulator = 1;
30783let isCVI = 1;
30784let DecoderNamespace = "EXT_mmvec";
30785let Constraints = "$Vx32 = $Vx32in";
30786}
30787def V6_vaddwq_alt : HInst<
30788(outs HvxVR:$Vx32),
30789(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
30790"if ($Qv4.w) $Vx32.w += $Vu32.w",
30791PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30792let hasNewValue = 1;
30793let opNewValue = 0;
30794let isAccumulator = 1;
30795let isCVI = 1;
30796let isPseudo = 1;
30797let isCodeGenOnly = 1;
30798let DecoderNamespace = "EXT_mmvec";
30799let Constraints = "$Vx32 = $Vx32in";
30800}
30801def V6_vaddwsat : HInst<
30802(outs HvxVR:$Vd32),
30803(ins HvxVR:$Vu32, HvxVR:$Vv32),
30804"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat",
30805tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30806let Inst{7-5} = 0b100;
30807let Inst{13-13} = 0b0;
30808let Inst{31-21} = 0b00011100010;
30809let hasNewValue = 1;
30810let opNewValue = 0;
30811let isCVI = 1;
30812let DecoderNamespace = "EXT_mmvec";
30813}
30814def V6_vaddwsat_alt : HInst<
30815(outs HvxVR:$Vd32),
30816(ins HvxVR:$Vu32, HvxVR:$Vv32),
30817"$Vd32 = vaddw($Vu32,$Vv32):sat",
30818PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30819let hasNewValue = 1;
30820let opNewValue = 0;
30821let isCVI = 1;
30822let isPseudo = 1;
30823let isCodeGenOnly = 1;
30824let DecoderNamespace = "EXT_mmvec";
30825}
30826def V6_vaddwsat_dv : HInst<
30827(outs HvxWR:$Vdd32),
30828(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30829"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat",
30830tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
30831let Inst{7-5} = 0b010;
30832let Inst{13-13} = 0b0;
30833let Inst{31-21} = 0b00011100100;
30834let hasNewValue = 1;
30835let opNewValue = 0;
30836let isCVI = 1;
30837let DecoderNamespace = "EXT_mmvec";
30838}
30839def V6_vaddwsat_dv_alt : HInst<
30840(outs HvxWR:$Vdd32),
30841(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
30842"$Vdd32 = vaddw($Vuu32,$Vvv32):sat",
30843PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30844let hasNewValue = 1;
30845let opNewValue = 0;
30846let isCVI = 1;
30847let isPseudo = 1;
30848let isCodeGenOnly = 1;
30849let DecoderNamespace = "EXT_mmvec";
30850}
30851def V6_valignb : HInst<
30852(outs HvxVR:$Vd32),
30853(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
30854"$Vd32 = valign($Vu32,$Vv32,$Rt8)",
30855tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
30856let Inst{7-5} = 0b000;
30857let Inst{13-13} = 0b0;
30858let Inst{31-24} = 0b00011011;
30859let hasNewValue = 1;
30860let opNewValue = 0;
30861let isCVI = 1;
30862let DecoderNamespace = "EXT_mmvec";
30863}
30864def V6_valignbi : HInst<
30865(outs HvxVR:$Vd32),
30866(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
30867"$Vd32 = valign($Vu32,$Vv32,#$Ii)",
30868tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
30869let Inst{13-13} = 0b1;
30870let Inst{31-21} = 0b00011110001;
30871let hasNewValue = 1;
30872let opNewValue = 0;
30873let isCVI = 1;
30874let DecoderNamespace = "EXT_mmvec";
30875}
30876def V6_vand : HInst<
30877(outs HvxVR:$Vd32),
30878(ins HvxVR:$Vu32, HvxVR:$Vv32),
30879"$Vd32 = vand($Vu32,$Vv32)",
30880tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
30881let Inst{7-5} = 0b101;
30882let Inst{13-13} = 0b0;
30883let Inst{31-21} = 0b00011100001;
30884let hasNewValue = 1;
30885let opNewValue = 0;
30886let isCVI = 1;
30887let DecoderNamespace = "EXT_mmvec";
30888}
30889def V6_vandnqrt : HInst<
30890(outs HvxVR:$Vd32),
30891(ins HvxQR:$Qu4, IntRegs:$Rt32),
30892"$Vd32 = vand(!$Qu4,$Rt32)",
30893tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> {
30894let Inst{7-5} = 0b101;
30895let Inst{13-10} = 0b0001;
30896let Inst{31-21} = 0b00011001101;
30897let hasNewValue = 1;
30898let opNewValue = 0;
30899let isCVI = 1;
30900let DecoderNamespace = "EXT_mmvec";
30901}
30902def V6_vandnqrt_acc : HInst<
30903(outs HvxVR:$Vx32),
30904(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30905"$Vx32 |= vand(!$Qu4,$Rt32)",
30906tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> {
30907let Inst{7-5} = 0b011;
30908let Inst{13-10} = 0b1001;
30909let Inst{31-21} = 0b00011001011;
30910let hasNewValue = 1;
30911let opNewValue = 0;
30912let isAccumulator = 1;
30913let isCVI = 1;
30914let DecoderNamespace = "EXT_mmvec";
30915let Constraints = "$Vx32 = $Vx32in";
30916}
30917def V6_vandnqrt_acc_alt : HInst<
30918(outs HvxVR:$Vx32),
30919(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30920"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)",
30921PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30922let hasNewValue = 1;
30923let opNewValue = 0;
30924let isAccumulator = 1;
30925let isCVI = 1;
30926let isPseudo = 1;
30927let isCodeGenOnly = 1;
30928let DecoderNamespace = "EXT_mmvec";
30929let Constraints = "$Vx32 = $Vx32in";
30930}
30931def V6_vandnqrt_alt : HInst<
30932(outs HvxVR:$Vd32),
30933(ins HvxQR:$Qu4, IntRegs:$Rt32),
30934"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)",
30935PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
30936let hasNewValue = 1;
30937let opNewValue = 0;
30938let isCVI = 1;
30939let isPseudo = 1;
30940let isCodeGenOnly = 1;
30941let DecoderNamespace = "EXT_mmvec";
30942}
30943def V6_vandqrt : HInst<
30944(outs HvxVR:$Vd32),
30945(ins HvxQR:$Qu4, IntRegs:$Rt32),
30946"$Vd32 = vand($Qu4,$Rt32)",
30947tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> {
30948let Inst{7-5} = 0b101;
30949let Inst{13-10} = 0b0000;
30950let Inst{31-21} = 0b00011001101;
30951let hasNewValue = 1;
30952let opNewValue = 0;
30953let isCVI = 1;
30954let DecoderNamespace = "EXT_mmvec";
30955}
30956def V6_vandqrt_acc : HInst<
30957(outs HvxVR:$Vx32),
30958(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30959"$Vx32 |= vand($Qu4,$Rt32)",
30960tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> {
30961let Inst{7-5} = 0b011;
30962let Inst{13-10} = 0b1000;
30963let Inst{31-21} = 0b00011001011;
30964let hasNewValue = 1;
30965let opNewValue = 0;
30966let isAccumulator = 1;
30967let isCVI = 1;
30968let DecoderNamespace = "EXT_mmvec";
30969let Constraints = "$Vx32 = $Vx32in";
30970}
30971def V6_vandqrt_acc_alt : HInst<
30972(outs HvxVR:$Vx32),
30973(ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32),
30974"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)",
30975PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30976let hasNewValue = 1;
30977let opNewValue = 0;
30978let isAccumulator = 1;
30979let isCVI = 1;
30980let isPseudo = 1;
30981let isCodeGenOnly = 1;
30982let DecoderNamespace = "EXT_mmvec";
30983let Constraints = "$Vx32 = $Vx32in";
30984}
30985def V6_vandqrt_alt : HInst<
30986(outs HvxVR:$Vd32),
30987(ins HvxQR:$Qu4, IntRegs:$Rt32),
30988"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)",
30989PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
30990let hasNewValue = 1;
30991let opNewValue = 0;
30992let isCVI = 1;
30993let isPseudo = 1;
30994let isCodeGenOnly = 1;
30995let DecoderNamespace = "EXT_mmvec";
30996}
30997def V6_vandvnqv : HInst<
30998(outs HvxVR:$Vd32),
30999(ins HvxQR:$Qv4, HvxVR:$Vu32),
31000"$Vd32 = vand(!$Qv4,$Vu32)",
31001tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31002let Inst{7-5} = 0b001;
31003let Inst{13-13} = 0b1;
31004let Inst{21-16} = 0b000011;
31005let Inst{31-24} = 0b00011110;
31006let hasNewValue = 1;
31007let opNewValue = 0;
31008let isCVI = 1;
31009let DecoderNamespace = "EXT_mmvec";
31010}
31011def V6_vandvqv : HInst<
31012(outs HvxVR:$Vd32),
31013(ins HvxQR:$Qv4, HvxVR:$Vu32),
31014"$Vd32 = vand($Qv4,$Vu32)",
31015tc_56c4f9fe, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> {
31016let Inst{7-5} = 0b000;
31017let Inst{13-13} = 0b1;
31018let Inst{21-16} = 0b000011;
31019let Inst{31-24} = 0b00011110;
31020let hasNewValue = 1;
31021let opNewValue = 0;
31022let isCVI = 1;
31023let DecoderNamespace = "EXT_mmvec";
31024}
31025def V6_vandvrt : HInst<
31026(outs HvxQR:$Qd4),
31027(ins HvxVR:$Vu32, IntRegs:$Rt32),
31028"$Qd4 = vand($Vu32,$Rt32)",
31029tc_ac4046bc, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> {
31030let Inst{7-2} = 0b010010;
31031let Inst{13-13} = 0b0;
31032let Inst{31-21} = 0b00011001101;
31033let hasNewValue = 1;
31034let opNewValue = 0;
31035let isCVI = 1;
31036let DecoderNamespace = "EXT_mmvec";
31037}
31038def V6_vandvrt_acc : HInst<
31039(outs HvxQR:$Qx4),
31040(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31041"$Qx4 |= vand($Vu32,$Rt32)",
31042tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> {
31043let Inst{7-2} = 0b100000;
31044let Inst{13-13} = 0b1;
31045let Inst{31-21} = 0b00011001011;
31046let isAccumulator = 1;
31047let isCVI = 1;
31048let DecoderNamespace = "EXT_mmvec";
31049let Constraints = "$Qx4 = $Qx4in";
31050}
31051def V6_vandvrt_acc_alt : HInst<
31052(outs HvxQR:$Qx4),
31053(ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32),
31054"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)",
31055PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31056let isAccumulator = 1;
31057let isCVI = 1;
31058let isPseudo = 1;
31059let isCodeGenOnly = 1;
31060let DecoderNamespace = "EXT_mmvec";
31061let Constraints = "$Qx4 = $Qx4in";
31062}
31063def V6_vandvrt_alt : HInst<
31064(outs HvxQR:$Qd4),
31065(ins HvxVR:$Vu32, IntRegs:$Rt32),
31066"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)",
31067PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31068let hasNewValue = 1;
31069let opNewValue = 0;
31070let isCVI = 1;
31071let isPseudo = 1;
31072let isCodeGenOnly = 1;
31073let DecoderNamespace = "EXT_mmvec";
31074}
31075def V6_vaslh : HInst<
31076(outs HvxVR:$Vd32),
31077(ins HvxVR:$Vu32, IntRegs:$Rt32),
31078"$Vd32.h = vasl($Vu32.h,$Rt32)",
31079tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31080let Inst{7-5} = 0b000;
31081let Inst{13-13} = 0b0;
31082let Inst{31-21} = 0b00011001100;
31083let hasNewValue = 1;
31084let opNewValue = 0;
31085let isCVI = 1;
31086let DecoderNamespace = "EXT_mmvec";
31087}
31088def V6_vaslh_acc : HInst<
31089(outs HvxVR:$Vx32),
31090(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31091"$Vx32.h += vasl($Vu32.h,$Rt32)",
31092tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31093let Inst{7-5} = 0b101;
31094let Inst{13-13} = 0b1;
31095let Inst{31-21} = 0b00011001101;
31096let hasNewValue = 1;
31097let opNewValue = 0;
31098let isAccumulator = 1;
31099let isCVI = 1;
31100let DecoderNamespace = "EXT_mmvec";
31101let Constraints = "$Vx32 = $Vx32in";
31102}
31103def V6_vaslh_acc_alt : HInst<
31104(outs HvxVR:$Vx32),
31105(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31106"$Vx32 += vaslh($Vu32,$Rt32)",
31107PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31108let hasNewValue = 1;
31109let opNewValue = 0;
31110let isAccumulator = 1;
31111let isCVI = 1;
31112let isPseudo = 1;
31113let isCodeGenOnly = 1;
31114let DecoderNamespace = "EXT_mmvec";
31115let Constraints = "$Vx32 = $Vx32in";
31116}
31117def V6_vaslh_alt : HInst<
31118(outs HvxVR:$Vd32),
31119(ins HvxVR:$Vu32, IntRegs:$Rt32),
31120"$Vd32 = vaslh($Vu32,$Rt32)",
31121PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31122let hasNewValue = 1;
31123let opNewValue = 0;
31124let isCVI = 1;
31125let isPseudo = 1;
31126let isCodeGenOnly = 1;
31127let DecoderNamespace = "EXT_mmvec";
31128}
31129def V6_vaslhv : HInst<
31130(outs HvxVR:$Vd32),
31131(ins HvxVR:$Vu32, HvxVR:$Vv32),
31132"$Vd32.h = vasl($Vu32.h,$Vv32.h)",
31133tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31134let Inst{7-5} = 0b101;
31135let Inst{13-13} = 0b0;
31136let Inst{31-21} = 0b00011111101;
31137let hasNewValue = 1;
31138let opNewValue = 0;
31139let isCVI = 1;
31140let DecoderNamespace = "EXT_mmvec";
31141}
31142def V6_vaslhv_alt : HInst<
31143(outs HvxVR:$Vd32),
31144(ins HvxVR:$Vu32, HvxVR:$Vv32),
31145"$Vd32 = vaslh($Vu32,$Vv32)",
31146PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31147let hasNewValue = 1;
31148let opNewValue = 0;
31149let isCVI = 1;
31150let isPseudo = 1;
31151let isCodeGenOnly = 1;
31152let DecoderNamespace = "EXT_mmvec";
31153}
31154def V6_vaslw : HInst<
31155(outs HvxVR:$Vd32),
31156(ins HvxVR:$Vu32, IntRegs:$Rt32),
31157"$Vd32.w = vasl($Vu32.w,$Rt32)",
31158tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31159let Inst{7-5} = 0b111;
31160let Inst{13-13} = 0b0;
31161let Inst{31-21} = 0b00011001011;
31162let hasNewValue = 1;
31163let opNewValue = 0;
31164let isCVI = 1;
31165let DecoderNamespace = "EXT_mmvec";
31166}
31167def V6_vaslw_acc : HInst<
31168(outs HvxVR:$Vx32),
31169(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31170"$Vx32.w += vasl($Vu32.w,$Rt32)",
31171tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31172let Inst{7-5} = 0b010;
31173let Inst{13-13} = 0b1;
31174let Inst{31-21} = 0b00011001011;
31175let hasNewValue = 1;
31176let opNewValue = 0;
31177let isAccumulator = 1;
31178let isCVI = 1;
31179let DecoderNamespace = "EXT_mmvec";
31180let Constraints = "$Vx32 = $Vx32in";
31181}
31182def V6_vaslw_acc_alt : HInst<
31183(outs HvxVR:$Vx32),
31184(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31185"$Vx32 += vaslw($Vu32,$Rt32)",
31186PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31187let hasNewValue = 1;
31188let opNewValue = 0;
31189let isAccumulator = 1;
31190let isCVI = 1;
31191let isPseudo = 1;
31192let isCodeGenOnly = 1;
31193let DecoderNamespace = "EXT_mmvec";
31194let Constraints = "$Vx32 = $Vx32in";
31195}
31196def V6_vaslw_alt : HInst<
31197(outs HvxVR:$Vd32),
31198(ins HvxVR:$Vu32, IntRegs:$Rt32),
31199"$Vd32 = vaslw($Vu32,$Rt32)",
31200PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31201let hasNewValue = 1;
31202let opNewValue = 0;
31203let isCVI = 1;
31204let isPseudo = 1;
31205let isCodeGenOnly = 1;
31206let DecoderNamespace = "EXT_mmvec";
31207}
31208def V6_vaslwv : HInst<
31209(outs HvxVR:$Vd32),
31210(ins HvxVR:$Vu32, HvxVR:$Vv32),
31211"$Vd32.w = vasl($Vu32.w,$Vv32.w)",
31212tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31213let Inst{7-5} = 0b100;
31214let Inst{13-13} = 0b0;
31215let Inst{31-21} = 0b00011111101;
31216let hasNewValue = 1;
31217let opNewValue = 0;
31218let isCVI = 1;
31219let DecoderNamespace = "EXT_mmvec";
31220}
31221def V6_vaslwv_alt : HInst<
31222(outs HvxVR:$Vd32),
31223(ins HvxVR:$Vu32, HvxVR:$Vv32),
31224"$Vd32 = vaslw($Vu32,$Vv32)",
31225PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31226let hasNewValue = 1;
31227let opNewValue = 0;
31228let isCVI = 1;
31229let isPseudo = 1;
31230let isCodeGenOnly = 1;
31231let DecoderNamespace = "EXT_mmvec";
31232}
31233def V6_vasr_into : HInst<
31234(outs HvxWR:$Vxx32),
31235(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31236"$Vxx32.w = vasrinto($Vu32.w,$Vv32.w)",
31237tc_df80eeb0, TypeCVI_VP_VS>, Enc_3fc427, Requires<[UseHVXV66]> {
31238let Inst{7-5} = 0b111;
31239let Inst{13-13} = 0b1;
31240let Inst{31-21} = 0b00011010101;
31241let hasNewValue = 1;
31242let opNewValue = 0;
31243let isCVI = 1;
31244let DecoderNamespace = "EXT_mmvec";
31245let Constraints = "$Vxx32 = $Vxx32in";
31246}
31247def V6_vasr_into_alt : HInst<
31248(outs HvxWR:$Vxx32),
31249(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
31250"$Vxx32 = vasrinto($Vu32,$Vv32)",
31251PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
31252let hasNewValue = 1;
31253let opNewValue = 0;
31254let isCVI = 1;
31255let isPseudo = 1;
31256let isCodeGenOnly = 1;
31257let DecoderNamespace = "EXT_mmvec";
31258let Constraints = "$Vxx32 = $Vxx32in";
31259}
31260def V6_vasrh : HInst<
31261(outs HvxVR:$Vd32),
31262(ins HvxVR:$Vu32, IntRegs:$Rt32),
31263"$Vd32.h = vasr($Vu32.h,$Rt32)",
31264tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31265let Inst{7-5} = 0b110;
31266let Inst{13-13} = 0b0;
31267let Inst{31-21} = 0b00011001011;
31268let hasNewValue = 1;
31269let opNewValue = 0;
31270let isCVI = 1;
31271let DecoderNamespace = "EXT_mmvec";
31272}
31273def V6_vasrh_acc : HInst<
31274(outs HvxVR:$Vx32),
31275(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31276"$Vx32.h += vasr($Vu32.h,$Rt32)",
31277tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> {
31278let Inst{7-5} = 0b111;
31279let Inst{13-13} = 0b1;
31280let Inst{31-21} = 0b00011001100;
31281let hasNewValue = 1;
31282let opNewValue = 0;
31283let isAccumulator = 1;
31284let isCVI = 1;
31285let DecoderNamespace = "EXT_mmvec";
31286let Constraints = "$Vx32 = $Vx32in";
31287}
31288def V6_vasrh_acc_alt : HInst<
31289(outs HvxVR:$Vx32),
31290(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31291"$Vx32 += vasrh($Vu32,$Rt32)",
31292PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31293let hasNewValue = 1;
31294let opNewValue = 0;
31295let isAccumulator = 1;
31296let isCVI = 1;
31297let isPseudo = 1;
31298let isCodeGenOnly = 1;
31299let DecoderNamespace = "EXT_mmvec";
31300let Constraints = "$Vx32 = $Vx32in";
31301}
31302def V6_vasrh_alt : HInst<
31303(outs HvxVR:$Vd32),
31304(ins HvxVR:$Vu32, IntRegs:$Rt32),
31305"$Vd32 = vasrh($Vu32,$Rt32)",
31306PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31307let hasNewValue = 1;
31308let opNewValue = 0;
31309let isCVI = 1;
31310let isPseudo = 1;
31311let isCodeGenOnly = 1;
31312let DecoderNamespace = "EXT_mmvec";
31313}
31314def V6_vasrhbrndsat : HInst<
31315(outs HvxVR:$Vd32),
31316(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31317"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31318tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31319let Inst{7-5} = 0b000;
31320let Inst{13-13} = 0b1;
31321let Inst{31-24} = 0b00011011;
31322let hasNewValue = 1;
31323let opNewValue = 0;
31324let isCVI = 1;
31325let DecoderNamespace = "EXT_mmvec";
31326}
31327def V6_vasrhbsat : HInst<
31328(outs HvxVR:$Vd32),
31329(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31330"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31331tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31332let Inst{7-5} = 0b000;
31333let Inst{13-13} = 0b0;
31334let Inst{31-24} = 0b00011000;
31335let hasNewValue = 1;
31336let opNewValue = 0;
31337let isCVI = 1;
31338let DecoderNamespace = "EXT_mmvec";
31339}
31340def V6_vasrhubrndsat : HInst<
31341(outs HvxVR:$Vd32),
31342(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31343"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat",
31344tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31345let Inst{7-5} = 0b111;
31346let Inst{13-13} = 0b0;
31347let Inst{31-24} = 0b00011011;
31348let hasNewValue = 1;
31349let opNewValue = 0;
31350let isCVI = 1;
31351let DecoderNamespace = "EXT_mmvec";
31352}
31353def V6_vasrhubsat : HInst<
31354(outs HvxVR:$Vd32),
31355(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31356"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat",
31357tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31358let Inst{7-5} = 0b110;
31359let Inst{13-13} = 0b0;
31360let Inst{31-24} = 0b00011011;
31361let hasNewValue = 1;
31362let opNewValue = 0;
31363let isCVI = 1;
31364let DecoderNamespace = "EXT_mmvec";
31365}
31366def V6_vasrhv : HInst<
31367(outs HvxVR:$Vd32),
31368(ins HvxVR:$Vu32, HvxVR:$Vv32),
31369"$Vd32.h = vasr($Vu32.h,$Vv32.h)",
31370tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31371let Inst{7-5} = 0b011;
31372let Inst{13-13} = 0b0;
31373let Inst{31-21} = 0b00011111101;
31374let hasNewValue = 1;
31375let opNewValue = 0;
31376let isCVI = 1;
31377let DecoderNamespace = "EXT_mmvec";
31378}
31379def V6_vasrhv_alt : HInst<
31380(outs HvxVR:$Vd32),
31381(ins HvxVR:$Vu32, HvxVR:$Vv32),
31382"$Vd32 = vasrh($Vu32,$Vv32)",
31383PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31384let hasNewValue = 1;
31385let opNewValue = 0;
31386let isCVI = 1;
31387let isPseudo = 1;
31388let isCodeGenOnly = 1;
31389let DecoderNamespace = "EXT_mmvec";
31390}
31391def V6_vasruhubrndsat : HInst<
31392(outs HvxVR:$Vd32),
31393(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31394"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat",
31395tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31396let Inst{7-5} = 0b111;
31397let Inst{13-13} = 0b0;
31398let Inst{31-24} = 0b00011000;
31399let hasNewValue = 1;
31400let opNewValue = 0;
31401let isCVI = 1;
31402let DecoderNamespace = "EXT_mmvec";
31403}
31404def V6_vasruhubsat : HInst<
31405(outs HvxVR:$Vd32),
31406(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31407"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat",
31408tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31409let Inst{7-5} = 0b101;
31410let Inst{13-13} = 0b1;
31411let Inst{31-24} = 0b00011000;
31412let hasNewValue = 1;
31413let opNewValue = 0;
31414let isCVI = 1;
31415let DecoderNamespace = "EXT_mmvec";
31416}
31417def V6_vasruwuhrndsat : HInst<
31418(outs HvxVR:$Vd32),
31419(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31420"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat",
31421tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31422let Inst{7-5} = 0b001;
31423let Inst{13-13} = 0b0;
31424let Inst{31-24} = 0b00011000;
31425let hasNewValue = 1;
31426let opNewValue = 0;
31427let isCVI = 1;
31428let DecoderNamespace = "EXT_mmvec";
31429}
31430def V6_vasruwuhsat : HInst<
31431(outs HvxVR:$Vd32),
31432(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31433"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat",
31434tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> {
31435let Inst{7-5} = 0b100;
31436let Inst{13-13} = 0b1;
31437let Inst{31-24} = 0b00011000;
31438let hasNewValue = 1;
31439let opNewValue = 0;
31440let isCVI = 1;
31441let DecoderNamespace = "EXT_mmvec";
31442}
31443def V6_vasrw : HInst<
31444(outs HvxVR:$Vd32),
31445(ins HvxVR:$Vu32, IntRegs:$Rt32),
31446"$Vd32.w = vasr($Vu32.w,$Rt32)",
31447tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
31448let Inst{7-5} = 0b101;
31449let Inst{13-13} = 0b0;
31450let Inst{31-21} = 0b00011001011;
31451let hasNewValue = 1;
31452let opNewValue = 0;
31453let isCVI = 1;
31454let DecoderNamespace = "EXT_mmvec";
31455}
31456def V6_vasrw_acc : HInst<
31457(outs HvxVR:$Vx32),
31458(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31459"$Vx32.w += vasr($Vu32.w,$Rt32)",
31460tc_309dbb4f, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> {
31461let Inst{7-5} = 0b101;
31462let Inst{13-13} = 0b1;
31463let Inst{31-21} = 0b00011001011;
31464let hasNewValue = 1;
31465let opNewValue = 0;
31466let isAccumulator = 1;
31467let isCVI = 1;
31468let DecoderNamespace = "EXT_mmvec";
31469let Constraints = "$Vx32 = $Vx32in";
31470}
31471def V6_vasrw_acc_alt : HInst<
31472(outs HvxVR:$Vx32),
31473(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
31474"$Vx32 += vasrw($Vu32,$Rt32)",
31475PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31476let hasNewValue = 1;
31477let opNewValue = 0;
31478let isAccumulator = 1;
31479let isCVI = 1;
31480let isPseudo = 1;
31481let isCodeGenOnly = 1;
31482let DecoderNamespace = "EXT_mmvec";
31483let Constraints = "$Vx32 = $Vx32in";
31484}
31485def V6_vasrw_alt : HInst<
31486(outs HvxVR:$Vd32),
31487(ins HvxVR:$Vu32, IntRegs:$Rt32),
31488"$Vd32 = vasrw($Vu32,$Rt32)",
31489PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31490let hasNewValue = 1;
31491let opNewValue = 0;
31492let isCVI = 1;
31493let isPseudo = 1;
31494let isCodeGenOnly = 1;
31495let DecoderNamespace = "EXT_mmvec";
31496}
31497def V6_vasrwh : HInst<
31498(outs HvxVR:$Vd32),
31499(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31500"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)",
31501tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31502let Inst{7-5} = 0b010;
31503let Inst{13-13} = 0b0;
31504let Inst{31-24} = 0b00011011;
31505let hasNewValue = 1;
31506let opNewValue = 0;
31507let isCVI = 1;
31508let DecoderNamespace = "EXT_mmvec";
31509}
31510def V6_vasrwhrndsat : HInst<
31511(outs HvxVR:$Vd32),
31512(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31513"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31514tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31515let Inst{7-5} = 0b100;
31516let Inst{13-13} = 0b0;
31517let Inst{31-24} = 0b00011011;
31518let hasNewValue = 1;
31519let opNewValue = 0;
31520let isCVI = 1;
31521let DecoderNamespace = "EXT_mmvec";
31522}
31523def V6_vasrwhsat : HInst<
31524(outs HvxVR:$Vd32),
31525(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31526"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31527tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31528let Inst{7-5} = 0b011;
31529let Inst{13-13} = 0b0;
31530let Inst{31-24} = 0b00011011;
31531let hasNewValue = 1;
31532let opNewValue = 0;
31533let isCVI = 1;
31534let DecoderNamespace = "EXT_mmvec";
31535}
31536def V6_vasrwuhrndsat : HInst<
31537(outs HvxVR:$Vd32),
31538(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31539"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat",
31540tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> {
31541let Inst{7-5} = 0b010;
31542let Inst{13-13} = 0b0;
31543let Inst{31-24} = 0b00011000;
31544let hasNewValue = 1;
31545let opNewValue = 0;
31546let isCVI = 1;
31547let DecoderNamespace = "EXT_mmvec";
31548}
31549def V6_vasrwuhsat : HInst<
31550(outs HvxVR:$Vd32),
31551(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
31552"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat",
31553tc_16ff9ef8, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> {
31554let Inst{7-5} = 0b101;
31555let Inst{13-13} = 0b0;
31556let Inst{31-24} = 0b00011011;
31557let hasNewValue = 1;
31558let opNewValue = 0;
31559let isCVI = 1;
31560let DecoderNamespace = "EXT_mmvec";
31561}
31562def V6_vasrwv : HInst<
31563(outs HvxVR:$Vd32),
31564(ins HvxVR:$Vu32, HvxVR:$Vv32),
31565"$Vd32.w = vasr($Vu32.w,$Vv32.w)",
31566tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
31567let Inst{7-5} = 0b000;
31568let Inst{13-13} = 0b0;
31569let Inst{31-21} = 0b00011111101;
31570let hasNewValue = 1;
31571let opNewValue = 0;
31572let isCVI = 1;
31573let DecoderNamespace = "EXT_mmvec";
31574}
31575def V6_vasrwv_alt : HInst<
31576(outs HvxVR:$Vd32),
31577(ins HvxVR:$Vu32, HvxVR:$Vv32),
31578"$Vd32 = vasrw($Vu32,$Vv32)",
31579PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31580let hasNewValue = 1;
31581let opNewValue = 0;
31582let isCVI = 1;
31583let isPseudo = 1;
31584let isCodeGenOnly = 1;
31585let DecoderNamespace = "EXT_mmvec";
31586}
31587def V6_vassign : HInst<
31588(outs HvxVR:$Vd32),
31589(ins HvxVR:$Vu32),
31590"$Vd32 = $Vu32",
31591tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
31592let Inst{7-5} = 0b111;
31593let Inst{13-13} = 0b1;
31594let Inst{31-16} = 0b0001111000000011;
31595let hasNewValue = 1;
31596let opNewValue = 0;
31597let isCVI = 1;
31598let DecoderNamespace = "EXT_mmvec";
31599}
31600def V6_vassignp : HInst<
31601(outs HvxWR:$Vdd32),
31602(ins HvxWR:$Vuu32),
31603"$Vdd32 = $Vuu32",
31604CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> {
31605let hasNewValue = 1;
31606let opNewValue = 0;
31607let isCVI = 1;
31608let isPseudo = 1;
31609let DecoderNamespace = "EXT_mmvec";
31610}
31611def V6_vavgb : HInst<
31612(outs HvxVR:$Vd32),
31613(ins HvxVR:$Vu32, HvxVR:$Vv32),
31614"$Vd32.b = vavg($Vu32.b,$Vv32.b)",
31615tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31616let Inst{7-5} = 0b100;
31617let Inst{13-13} = 0b1;
31618let Inst{31-21} = 0b00011111000;
31619let hasNewValue = 1;
31620let opNewValue = 0;
31621let isCVI = 1;
31622let DecoderNamespace = "EXT_mmvec";
31623}
31624def V6_vavgb_alt : HInst<
31625(outs HvxVR:$Vd32),
31626(ins HvxVR:$Vu32, HvxVR:$Vv32),
31627"$Vd32 = vavgb($Vu32,$Vv32)",
31628PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31629let hasNewValue = 1;
31630let opNewValue = 0;
31631let isCVI = 1;
31632let isPseudo = 1;
31633let isCodeGenOnly = 1;
31634let DecoderNamespace = "EXT_mmvec";
31635}
31636def V6_vavgbrnd : HInst<
31637(outs HvxVR:$Vd32),
31638(ins HvxVR:$Vu32, HvxVR:$Vv32),
31639"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd",
31640tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31641let Inst{7-5} = 0b101;
31642let Inst{13-13} = 0b1;
31643let Inst{31-21} = 0b00011111000;
31644let hasNewValue = 1;
31645let opNewValue = 0;
31646let isCVI = 1;
31647let DecoderNamespace = "EXT_mmvec";
31648}
31649def V6_vavgbrnd_alt : HInst<
31650(outs HvxVR:$Vd32),
31651(ins HvxVR:$Vu32, HvxVR:$Vv32),
31652"$Vd32 = vavgb($Vu32,$Vv32):rnd",
31653PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31654let hasNewValue = 1;
31655let opNewValue = 0;
31656let isCVI = 1;
31657let isPseudo = 1;
31658let isCodeGenOnly = 1;
31659let DecoderNamespace = "EXT_mmvec";
31660}
31661def V6_vavgh : HInst<
31662(outs HvxVR:$Vd32),
31663(ins HvxVR:$Vu32, HvxVR:$Vv32),
31664"$Vd32.h = vavg($Vu32.h,$Vv32.h)",
31665tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31666let Inst{7-5} = 0b110;
31667let Inst{13-13} = 0b0;
31668let Inst{31-21} = 0b00011100110;
31669let hasNewValue = 1;
31670let opNewValue = 0;
31671let isCVI = 1;
31672let DecoderNamespace = "EXT_mmvec";
31673}
31674def V6_vavgh_alt : HInst<
31675(outs HvxVR:$Vd32),
31676(ins HvxVR:$Vu32, HvxVR:$Vv32),
31677"$Vd32 = vavgh($Vu32,$Vv32)",
31678PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31679let hasNewValue = 1;
31680let opNewValue = 0;
31681let isCVI = 1;
31682let isPseudo = 1;
31683let isCodeGenOnly = 1;
31684let DecoderNamespace = "EXT_mmvec";
31685}
31686def V6_vavghrnd : HInst<
31687(outs HvxVR:$Vd32),
31688(ins HvxVR:$Vu32, HvxVR:$Vv32),
31689"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd",
31690tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31691let Inst{7-5} = 0b101;
31692let Inst{13-13} = 0b0;
31693let Inst{31-21} = 0b00011100111;
31694let hasNewValue = 1;
31695let opNewValue = 0;
31696let isCVI = 1;
31697let DecoderNamespace = "EXT_mmvec";
31698}
31699def V6_vavghrnd_alt : HInst<
31700(outs HvxVR:$Vd32),
31701(ins HvxVR:$Vu32, HvxVR:$Vv32),
31702"$Vd32 = vavgh($Vu32,$Vv32):rnd",
31703PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31704let hasNewValue = 1;
31705let opNewValue = 0;
31706let isCVI = 1;
31707let isPseudo = 1;
31708let isCodeGenOnly = 1;
31709let DecoderNamespace = "EXT_mmvec";
31710}
31711def V6_vavgub : HInst<
31712(outs HvxVR:$Vd32),
31713(ins HvxVR:$Vu32, HvxVR:$Vv32),
31714"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)",
31715tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31716let Inst{7-5} = 0b100;
31717let Inst{13-13} = 0b0;
31718let Inst{31-21} = 0b00011100110;
31719let hasNewValue = 1;
31720let opNewValue = 0;
31721let isCVI = 1;
31722let DecoderNamespace = "EXT_mmvec";
31723}
31724def V6_vavgub_alt : HInst<
31725(outs HvxVR:$Vd32),
31726(ins HvxVR:$Vu32, HvxVR:$Vv32),
31727"$Vd32 = vavgub($Vu32,$Vv32)",
31728PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31729let hasNewValue = 1;
31730let opNewValue = 0;
31731let isCVI = 1;
31732let isPseudo = 1;
31733let isCodeGenOnly = 1;
31734let DecoderNamespace = "EXT_mmvec";
31735}
31736def V6_vavgubrnd : HInst<
31737(outs HvxVR:$Vd32),
31738(ins HvxVR:$Vu32, HvxVR:$Vv32),
31739"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd",
31740tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31741let Inst{7-5} = 0b011;
31742let Inst{13-13} = 0b0;
31743let Inst{31-21} = 0b00011100111;
31744let hasNewValue = 1;
31745let opNewValue = 0;
31746let isCVI = 1;
31747let DecoderNamespace = "EXT_mmvec";
31748}
31749def V6_vavgubrnd_alt : HInst<
31750(outs HvxVR:$Vd32),
31751(ins HvxVR:$Vu32, HvxVR:$Vv32),
31752"$Vd32 = vavgub($Vu32,$Vv32):rnd",
31753PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31754let hasNewValue = 1;
31755let opNewValue = 0;
31756let isCVI = 1;
31757let isPseudo = 1;
31758let isCodeGenOnly = 1;
31759let DecoderNamespace = "EXT_mmvec";
31760}
31761def V6_vavguh : HInst<
31762(outs HvxVR:$Vd32),
31763(ins HvxVR:$Vu32, HvxVR:$Vv32),
31764"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)",
31765tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31766let Inst{7-5} = 0b101;
31767let Inst{13-13} = 0b0;
31768let Inst{31-21} = 0b00011100110;
31769let hasNewValue = 1;
31770let opNewValue = 0;
31771let isCVI = 1;
31772let DecoderNamespace = "EXT_mmvec";
31773}
31774def V6_vavguh_alt : HInst<
31775(outs HvxVR:$Vd32),
31776(ins HvxVR:$Vu32, HvxVR:$Vv32),
31777"$Vd32 = vavguh($Vu32,$Vv32)",
31778PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31779let hasNewValue = 1;
31780let opNewValue = 0;
31781let isCVI = 1;
31782let isPseudo = 1;
31783let isCodeGenOnly = 1;
31784let DecoderNamespace = "EXT_mmvec";
31785}
31786def V6_vavguhrnd : HInst<
31787(outs HvxVR:$Vd32),
31788(ins HvxVR:$Vu32, HvxVR:$Vv32),
31789"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd",
31790tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31791let Inst{7-5} = 0b100;
31792let Inst{13-13} = 0b0;
31793let Inst{31-21} = 0b00011100111;
31794let hasNewValue = 1;
31795let opNewValue = 0;
31796let isCVI = 1;
31797let DecoderNamespace = "EXT_mmvec";
31798}
31799def V6_vavguhrnd_alt : HInst<
31800(outs HvxVR:$Vd32),
31801(ins HvxVR:$Vu32, HvxVR:$Vv32),
31802"$Vd32 = vavguh($Vu32,$Vv32):rnd",
31803PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31804let hasNewValue = 1;
31805let opNewValue = 0;
31806let isCVI = 1;
31807let isPseudo = 1;
31808let isCodeGenOnly = 1;
31809let DecoderNamespace = "EXT_mmvec";
31810}
31811def V6_vavguw : HInst<
31812(outs HvxVR:$Vd32),
31813(ins HvxVR:$Vu32, HvxVR:$Vv32),
31814"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)",
31815tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31816let Inst{7-5} = 0b010;
31817let Inst{13-13} = 0b1;
31818let Inst{31-21} = 0b00011111000;
31819let hasNewValue = 1;
31820let opNewValue = 0;
31821let isCVI = 1;
31822let DecoderNamespace = "EXT_mmvec";
31823}
31824def V6_vavguw_alt : HInst<
31825(outs HvxVR:$Vd32),
31826(ins HvxVR:$Vu32, HvxVR:$Vv32),
31827"$Vd32 = vavguw($Vu32,$Vv32)",
31828PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31829let hasNewValue = 1;
31830let opNewValue = 0;
31831let isCVI = 1;
31832let isPseudo = 1;
31833let isCodeGenOnly = 1;
31834let DecoderNamespace = "EXT_mmvec";
31835}
31836def V6_vavguwrnd : HInst<
31837(outs HvxVR:$Vd32),
31838(ins HvxVR:$Vu32, HvxVR:$Vv32),
31839"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd",
31840tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
31841let Inst{7-5} = 0b011;
31842let Inst{13-13} = 0b1;
31843let Inst{31-21} = 0b00011111000;
31844let hasNewValue = 1;
31845let opNewValue = 0;
31846let isCVI = 1;
31847let DecoderNamespace = "EXT_mmvec";
31848}
31849def V6_vavguwrnd_alt : HInst<
31850(outs HvxVR:$Vd32),
31851(ins HvxVR:$Vu32, HvxVR:$Vv32),
31852"$Vd32 = vavguw($Vu32,$Vv32):rnd",
31853PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
31854let hasNewValue = 1;
31855let opNewValue = 0;
31856let isCVI = 1;
31857let isPseudo = 1;
31858let isCodeGenOnly = 1;
31859let DecoderNamespace = "EXT_mmvec";
31860}
31861def V6_vavgw : HInst<
31862(outs HvxVR:$Vd32),
31863(ins HvxVR:$Vu32, HvxVR:$Vv32),
31864"$Vd32.w = vavg($Vu32.w,$Vv32.w)",
31865tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31866let Inst{7-5} = 0b111;
31867let Inst{13-13} = 0b0;
31868let Inst{31-21} = 0b00011100110;
31869let hasNewValue = 1;
31870let opNewValue = 0;
31871let isCVI = 1;
31872let DecoderNamespace = "EXT_mmvec";
31873}
31874def V6_vavgw_alt : HInst<
31875(outs HvxVR:$Vd32),
31876(ins HvxVR:$Vu32, HvxVR:$Vv32),
31877"$Vd32 = vavgw($Vu32,$Vv32)",
31878PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31879let hasNewValue = 1;
31880let opNewValue = 0;
31881let isCVI = 1;
31882let isPseudo = 1;
31883let isCodeGenOnly = 1;
31884let DecoderNamespace = "EXT_mmvec";
31885}
31886def V6_vavgwrnd : HInst<
31887(outs HvxVR:$Vd32),
31888(ins HvxVR:$Vu32, HvxVR:$Vv32),
31889"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd",
31890tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
31891let Inst{7-5} = 0b110;
31892let Inst{13-13} = 0b0;
31893let Inst{31-21} = 0b00011100111;
31894let hasNewValue = 1;
31895let opNewValue = 0;
31896let isCVI = 1;
31897let DecoderNamespace = "EXT_mmvec";
31898}
31899def V6_vavgwrnd_alt : HInst<
31900(outs HvxVR:$Vd32),
31901(ins HvxVR:$Vu32, HvxVR:$Vv32),
31902"$Vd32 = vavgw($Vu32,$Vv32):rnd",
31903PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31904let hasNewValue = 1;
31905let opNewValue = 0;
31906let isCVI = 1;
31907let isPseudo = 1;
31908let isCodeGenOnly = 1;
31909let DecoderNamespace = "EXT_mmvec";
31910}
31911def V6_vccombine : HInst<
31912(outs HvxWR:$Vdd32),
31913(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
31914"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
31915tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
31916let Inst{7-7} = 0b0;
31917let Inst{13-13} = 0b0;
31918let Inst{31-21} = 0b00011010011;
31919let isPredicated = 1;
31920let hasNewValue = 1;
31921let opNewValue = 0;
31922let isCVI = 1;
31923let DecoderNamespace = "EXT_mmvec";
31924}
31925def V6_vcl0h : HInst<
31926(outs HvxVR:$Vd32),
31927(ins HvxVR:$Vu32),
31928"$Vd32.uh = vcl0($Vu32.uh)",
31929tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31930let Inst{7-5} = 0b111;
31931let Inst{13-13} = 0b0;
31932let Inst{31-16} = 0b0001111000000010;
31933let hasNewValue = 1;
31934let opNewValue = 0;
31935let isCVI = 1;
31936let DecoderNamespace = "EXT_mmvec";
31937}
31938def V6_vcl0h_alt : HInst<
31939(outs HvxVR:$Vd32),
31940(ins HvxVR:$Vu32),
31941"$Vd32 = vcl0h($Vu32)",
31942PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31943let hasNewValue = 1;
31944let opNewValue = 0;
31945let isCVI = 1;
31946let isPseudo = 1;
31947let isCodeGenOnly = 1;
31948let DecoderNamespace = "EXT_mmvec";
31949}
31950def V6_vcl0w : HInst<
31951(outs HvxVR:$Vd32),
31952(ins HvxVR:$Vu32),
31953"$Vd32.uw = vcl0($Vu32.uw)",
31954tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
31955let Inst{7-5} = 0b101;
31956let Inst{13-13} = 0b0;
31957let Inst{31-16} = 0b0001111000000010;
31958let hasNewValue = 1;
31959let opNewValue = 0;
31960let isCVI = 1;
31961let DecoderNamespace = "EXT_mmvec";
31962}
31963def V6_vcl0w_alt : HInst<
31964(outs HvxVR:$Vd32),
31965(ins HvxVR:$Vu32),
31966"$Vd32 = vcl0w($Vu32)",
31967PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
31968let hasNewValue = 1;
31969let opNewValue = 0;
31970let isCVI = 1;
31971let isPseudo = 1;
31972let isCodeGenOnly = 1;
31973let DecoderNamespace = "EXT_mmvec";
31974}
31975def V6_vcmov : HInst<
31976(outs HvxVR:$Vd32),
31977(ins PredRegs:$Ps4, HvxVR:$Vu32),
31978"if ($Ps4) $Vd32 = $Vu32",
31979tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
31980let Inst{7-7} = 0b0;
31981let Inst{13-13} = 0b0;
31982let Inst{31-16} = 0b0001101000000000;
31983let isPredicated = 1;
31984let hasNewValue = 1;
31985let opNewValue = 0;
31986let isCVI = 1;
31987let DecoderNamespace = "EXT_mmvec";
31988}
31989def V6_vcombine : HInst<
31990(outs HvxWR:$Vdd32),
31991(ins HvxVR:$Vu32, HvxVR:$Vv32),
31992"$Vdd32 = vcombine($Vu32,$Vv32)",
31993tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
31994let Inst{7-5} = 0b111;
31995let Inst{13-13} = 0b0;
31996let Inst{31-21} = 0b00011111010;
31997let hasNewValue = 1;
31998let opNewValue = 0;
31999let isCVI = 1;
32000let isRegSequence = 1;
32001let DecoderNamespace = "EXT_mmvec";
32002}
32003def V6_vd0 : HInst<
32004(outs HvxVR:$Vd32),
32005(ins),
32006"$Vd32 = #0",
32007CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> {
32008let hasNewValue = 1;
32009let opNewValue = 0;
32010let isCVI = 1;
32011let isPseudo = 1;
32012let isCodeGenOnly = 1;
32013let DecoderNamespace = "EXT_mmvec";
32014}
32015def V6_vdd0 : HInst<
32016(outs HvxWR:$Vdd32),
32017(ins),
32018"$Vdd32 = #0",
32019tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> {
32020let hasNewValue = 1;
32021let opNewValue = 0;
32022let isCVI = 1;
32023let isPseudo = 1;
32024let isCodeGenOnly = 1;
32025let DecoderNamespace = "EXT_mmvec";
32026}
32027def V6_vdeal : HInst<
32028(outs HvxVR:$Vy32, HvxVR:$Vx32),
32029(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
32030"vdeal($Vy32,$Vx32,$Rt32)",
32031tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
32032let Inst{7-5} = 0b010;
32033let Inst{13-13} = 0b1;
32034let Inst{31-21} = 0b00011001111;
32035let hasNewValue = 1;
32036let opNewValue = 0;
32037let hasNewValue2 = 1;
32038let opNewValue2 = 1;
32039let isCVI = 1;
32040let DecoderNamespace = "EXT_mmvec";
32041let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
32042}
32043def V6_vdealb : HInst<
32044(outs HvxVR:$Vd32),
32045(ins HvxVR:$Vu32),
32046"$Vd32.b = vdeal($Vu32.b)",
32047tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32048let Inst{7-5} = 0b111;
32049let Inst{13-13} = 0b0;
32050let Inst{31-16} = 0b0001111000000000;
32051let hasNewValue = 1;
32052let opNewValue = 0;
32053let isCVI = 1;
32054let DecoderNamespace = "EXT_mmvec";
32055}
32056def V6_vdealb4w : HInst<
32057(outs HvxVR:$Vd32),
32058(ins HvxVR:$Vu32, HvxVR:$Vv32),
32059"$Vd32.b = vdeale($Vu32.b,$Vv32.b)",
32060tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32061let Inst{7-5} = 0b111;
32062let Inst{13-13} = 0b0;
32063let Inst{31-21} = 0b00011111001;
32064let hasNewValue = 1;
32065let opNewValue = 0;
32066let isCVI = 1;
32067let DecoderNamespace = "EXT_mmvec";
32068}
32069def V6_vdealb4w_alt : HInst<
32070(outs HvxVR:$Vd32),
32071(ins HvxVR:$Vu32, HvxVR:$Vv32),
32072"$Vd32 = vdealb4w($Vu32,$Vv32)",
32073PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32074let hasNewValue = 1;
32075let opNewValue = 0;
32076let isCVI = 1;
32077let isPseudo = 1;
32078let isCodeGenOnly = 1;
32079let DecoderNamespace = "EXT_mmvec";
32080}
32081def V6_vdealb_alt : HInst<
32082(outs HvxVR:$Vd32),
32083(ins HvxVR:$Vu32),
32084"$Vd32 = vdealb($Vu32)",
32085PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32086let hasNewValue = 1;
32087let opNewValue = 0;
32088let isCVI = 1;
32089let isPseudo = 1;
32090let isCodeGenOnly = 1;
32091let DecoderNamespace = "EXT_mmvec";
32092}
32093def V6_vdealh : HInst<
32094(outs HvxVR:$Vd32),
32095(ins HvxVR:$Vu32),
32096"$Vd32.h = vdeal($Vu32.h)",
32097tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
32098let Inst{7-5} = 0b110;
32099let Inst{13-13} = 0b0;
32100let Inst{31-16} = 0b0001111000000000;
32101let hasNewValue = 1;
32102let opNewValue = 0;
32103let isCVI = 1;
32104let DecoderNamespace = "EXT_mmvec";
32105}
32106def V6_vdealh_alt : HInst<
32107(outs HvxVR:$Vd32),
32108(ins HvxVR:$Vu32),
32109"$Vd32 = vdealh($Vu32)",
32110PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32111let hasNewValue = 1;
32112let opNewValue = 0;
32113let isCVI = 1;
32114let isPseudo = 1;
32115let isCodeGenOnly = 1;
32116let DecoderNamespace = "EXT_mmvec";
32117}
32118def V6_vdealvdd : HInst<
32119(outs HvxWR:$Vdd32),
32120(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
32121"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)",
32122tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
32123let Inst{7-5} = 0b100;
32124let Inst{13-13} = 0b1;
32125let Inst{31-24} = 0b00011011;
32126let hasNewValue = 1;
32127let opNewValue = 0;
32128let isCVI = 1;
32129let DecoderNamespace = "EXT_mmvec";
32130}
32131def V6_vdelta : HInst<
32132(outs HvxVR:$Vd32),
32133(ins HvxVR:$Vu32, HvxVR:$Vv32),
32134"$Vd32 = vdelta($Vu32,$Vv32)",
32135tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
32136let Inst{7-5} = 0b001;
32137let Inst{13-13} = 0b0;
32138let Inst{31-21} = 0b00011111001;
32139let hasNewValue = 1;
32140let opNewValue = 0;
32141let isCVI = 1;
32142let DecoderNamespace = "EXT_mmvec";
32143}
32144def V6_vdmpybus : HInst<
32145(outs HvxVR:$Vd32),
32146(ins HvxVR:$Vu32, IntRegs:$Rt32),
32147"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)",
32148tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32149let Inst{7-5} = 0b110;
32150let Inst{13-13} = 0b0;
32151let Inst{31-21} = 0b00011001000;
32152let hasNewValue = 1;
32153let opNewValue = 0;
32154let isCVI = 1;
32155let DecoderNamespace = "EXT_mmvec";
32156}
32157def V6_vdmpybus_acc : HInst<
32158(outs HvxVR:$Vx32),
32159(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32160"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)",
32161tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32162let Inst{7-5} = 0b110;
32163let Inst{13-13} = 0b1;
32164let Inst{31-21} = 0b00011001000;
32165let hasNewValue = 1;
32166let opNewValue = 0;
32167let isAccumulator = 1;
32168let isCVI = 1;
32169let DecoderNamespace = "EXT_mmvec";
32170let Constraints = "$Vx32 = $Vx32in";
32171}
32172def V6_vdmpybus_acc_alt : HInst<
32173(outs HvxVR:$Vx32),
32174(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32175"$Vx32 += vdmpybus($Vu32,$Rt32)",
32176PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32177let hasNewValue = 1;
32178let opNewValue = 0;
32179let isAccumulator = 1;
32180let isCVI = 1;
32181let isPseudo = 1;
32182let isCodeGenOnly = 1;
32183let DecoderNamespace = "EXT_mmvec";
32184let Constraints = "$Vx32 = $Vx32in";
32185}
32186def V6_vdmpybus_alt : HInst<
32187(outs HvxVR:$Vd32),
32188(ins HvxVR:$Vu32, IntRegs:$Rt32),
32189"$Vd32 = vdmpybus($Vu32,$Rt32)",
32190PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32191let hasNewValue = 1;
32192let opNewValue = 0;
32193let isCVI = 1;
32194let isPseudo = 1;
32195let isCodeGenOnly = 1;
32196let DecoderNamespace = "EXT_mmvec";
32197}
32198def V6_vdmpybus_dv : HInst<
32199(outs HvxWR:$Vdd32),
32200(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32201"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)",
32202tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32203let Inst{7-5} = 0b111;
32204let Inst{13-13} = 0b0;
32205let Inst{31-21} = 0b00011001000;
32206let hasNewValue = 1;
32207let opNewValue = 0;
32208let isCVI = 1;
32209let DecoderNamespace = "EXT_mmvec";
32210}
32211def V6_vdmpybus_dv_acc : HInst<
32212(outs HvxWR:$Vxx32),
32213(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32214"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)",
32215tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32216let Inst{7-5} = 0b111;
32217let Inst{13-13} = 0b1;
32218let Inst{31-21} = 0b00011001000;
32219let hasNewValue = 1;
32220let opNewValue = 0;
32221let isAccumulator = 1;
32222let isCVI = 1;
32223let DecoderNamespace = "EXT_mmvec";
32224let Constraints = "$Vxx32 = $Vxx32in";
32225}
32226def V6_vdmpybus_dv_acc_alt : HInst<
32227(outs HvxWR:$Vxx32),
32228(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32229"$Vxx32 += vdmpybus($Vuu32,$Rt32)",
32230PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32231let hasNewValue = 1;
32232let opNewValue = 0;
32233let isAccumulator = 1;
32234let isCVI = 1;
32235let isPseudo = 1;
32236let isCodeGenOnly = 1;
32237let DecoderNamespace = "EXT_mmvec";
32238let Constraints = "$Vxx32 = $Vxx32in";
32239}
32240def V6_vdmpybus_dv_alt : HInst<
32241(outs HvxWR:$Vdd32),
32242(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32243"$Vdd32 = vdmpybus($Vuu32,$Rt32)",
32244PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32245let hasNewValue = 1;
32246let opNewValue = 0;
32247let isCVI = 1;
32248let isPseudo = 1;
32249let isCodeGenOnly = 1;
32250let DecoderNamespace = "EXT_mmvec";
32251}
32252def V6_vdmpyhb : HInst<
32253(outs HvxVR:$Vd32),
32254(ins HvxVR:$Vu32, IntRegs:$Rt32),
32255"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)",
32256tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
32257let Inst{7-5} = 0b010;
32258let Inst{13-13} = 0b0;
32259let Inst{31-21} = 0b00011001000;
32260let hasNewValue = 1;
32261let opNewValue = 0;
32262let isCVI = 1;
32263let DecoderNamespace = "EXT_mmvec";
32264}
32265def V6_vdmpyhb_acc : HInst<
32266(outs HvxVR:$Vx32),
32267(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32268"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)",
32269tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
32270let Inst{7-5} = 0b011;
32271let Inst{13-13} = 0b1;
32272let Inst{31-21} = 0b00011001000;
32273let hasNewValue = 1;
32274let opNewValue = 0;
32275let isAccumulator = 1;
32276let isCVI = 1;
32277let DecoderNamespace = "EXT_mmvec";
32278let Constraints = "$Vx32 = $Vx32in";
32279}
32280def V6_vdmpyhb_acc_alt : HInst<
32281(outs HvxVR:$Vx32),
32282(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32283"$Vx32 += vdmpyhb($Vu32,$Rt32)",
32284PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32285let hasNewValue = 1;
32286let opNewValue = 0;
32287let isAccumulator = 1;
32288let isCVI = 1;
32289let isPseudo = 1;
32290let isCodeGenOnly = 1;
32291let DecoderNamespace = "EXT_mmvec";
32292let Constraints = "$Vx32 = $Vx32in";
32293}
32294def V6_vdmpyhb_alt : HInst<
32295(outs HvxVR:$Vd32),
32296(ins HvxVR:$Vu32, IntRegs:$Rt32),
32297"$Vd32 = vdmpyhb($Vu32,$Rt32)",
32298PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32299let hasNewValue = 1;
32300let opNewValue = 0;
32301let isCVI = 1;
32302let isPseudo = 1;
32303let isCodeGenOnly = 1;
32304let DecoderNamespace = "EXT_mmvec";
32305}
32306def V6_vdmpyhb_dv : HInst<
32307(outs HvxWR:$Vdd32),
32308(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32309"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)",
32310tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32311let Inst{7-5} = 0b100;
32312let Inst{13-13} = 0b0;
32313let Inst{31-21} = 0b00011001001;
32314let hasNewValue = 1;
32315let opNewValue = 0;
32316let isCVI = 1;
32317let DecoderNamespace = "EXT_mmvec";
32318}
32319def V6_vdmpyhb_dv_acc : HInst<
32320(outs HvxWR:$Vxx32),
32321(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32322"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)",
32323tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32324let Inst{7-5} = 0b100;
32325let Inst{13-13} = 0b1;
32326let Inst{31-21} = 0b00011001001;
32327let hasNewValue = 1;
32328let opNewValue = 0;
32329let isAccumulator = 1;
32330let isCVI = 1;
32331let DecoderNamespace = "EXT_mmvec";
32332let Constraints = "$Vxx32 = $Vxx32in";
32333}
32334def V6_vdmpyhb_dv_acc_alt : HInst<
32335(outs HvxWR:$Vxx32),
32336(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32337"$Vxx32 += vdmpyhb($Vuu32,$Rt32)",
32338PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32339let hasNewValue = 1;
32340let opNewValue = 0;
32341let isAccumulator = 1;
32342let isCVI = 1;
32343let isPseudo = 1;
32344let isCodeGenOnly = 1;
32345let DecoderNamespace = "EXT_mmvec";
32346let Constraints = "$Vxx32 = $Vxx32in";
32347}
32348def V6_vdmpyhb_dv_alt : HInst<
32349(outs HvxWR:$Vdd32),
32350(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32351"$Vdd32 = vdmpyhb($Vuu32,$Rt32)",
32352PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32353let hasNewValue = 1;
32354let opNewValue = 0;
32355let isCVI = 1;
32356let isPseudo = 1;
32357let isCodeGenOnly = 1;
32358let DecoderNamespace = "EXT_mmvec";
32359}
32360def V6_vdmpyhisat : HInst<
32361(outs HvxVR:$Vd32),
32362(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32363"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat",
32364tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32365let Inst{7-5} = 0b011;
32366let Inst{13-13} = 0b0;
32367let Inst{31-21} = 0b00011001001;
32368let hasNewValue = 1;
32369let opNewValue = 0;
32370let isCVI = 1;
32371let DecoderNamespace = "EXT_mmvec";
32372}
32373def V6_vdmpyhisat_acc : HInst<
32374(outs HvxVR:$Vx32),
32375(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32376"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat",
32377tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32378let Inst{7-5} = 0b010;
32379let Inst{13-13} = 0b1;
32380let Inst{31-21} = 0b00011001001;
32381let hasNewValue = 1;
32382let opNewValue = 0;
32383let isAccumulator = 1;
32384let isCVI = 1;
32385let DecoderNamespace = "EXT_mmvec";
32386let Constraints = "$Vx32 = $Vx32in";
32387}
32388def V6_vdmpyhisat_acc_alt : HInst<
32389(outs HvxVR:$Vx32),
32390(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32391"$Vx32 += vdmpyh($Vuu32,$Rt32):sat",
32392PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32393let hasNewValue = 1;
32394let opNewValue = 0;
32395let isAccumulator = 1;
32396let isCVI = 1;
32397let isPseudo = 1;
32398let isCodeGenOnly = 1;
32399let DecoderNamespace = "EXT_mmvec";
32400let Constraints = "$Vx32 = $Vx32in";
32401}
32402def V6_vdmpyhisat_alt : HInst<
32403(outs HvxVR:$Vd32),
32404(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32405"$Vd32 = vdmpyh($Vuu32,$Rt32):sat",
32406PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32407let hasNewValue = 1;
32408let opNewValue = 0;
32409let isCVI = 1;
32410let isPseudo = 1;
32411let isCodeGenOnly = 1;
32412let DecoderNamespace = "EXT_mmvec";
32413}
32414def V6_vdmpyhsat : HInst<
32415(outs HvxVR:$Vd32),
32416(ins HvxVR:$Vu32, IntRegs:$Rt32),
32417"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat",
32418tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
32419let Inst{7-5} = 0b010;
32420let Inst{13-13} = 0b0;
32421let Inst{31-21} = 0b00011001001;
32422let hasNewValue = 1;
32423let opNewValue = 0;
32424let isCVI = 1;
32425let DecoderNamespace = "EXT_mmvec";
32426}
32427def V6_vdmpyhsat_acc : HInst<
32428(outs HvxVR:$Vx32),
32429(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32430"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat",
32431tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
32432let Inst{7-5} = 0b011;
32433let Inst{13-13} = 0b1;
32434let Inst{31-21} = 0b00011001001;
32435let hasNewValue = 1;
32436let opNewValue = 0;
32437let isAccumulator = 1;
32438let isCVI = 1;
32439let DecoderNamespace = "EXT_mmvec";
32440let Constraints = "$Vx32 = $Vx32in";
32441}
32442def V6_vdmpyhsat_acc_alt : HInst<
32443(outs HvxVR:$Vx32),
32444(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32445"$Vx32 += vdmpyh($Vu32,$Rt32):sat",
32446PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32447let hasNewValue = 1;
32448let opNewValue = 0;
32449let isAccumulator = 1;
32450let isCVI = 1;
32451let isPseudo = 1;
32452let isCodeGenOnly = 1;
32453let DecoderNamespace = "EXT_mmvec";
32454let Constraints = "$Vx32 = $Vx32in";
32455}
32456def V6_vdmpyhsat_alt : HInst<
32457(outs HvxVR:$Vd32),
32458(ins HvxVR:$Vu32, IntRegs:$Rt32),
32459"$Vd32 = vdmpyh($Vu32,$Rt32):sat",
32460PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32461let hasNewValue = 1;
32462let opNewValue = 0;
32463let isCVI = 1;
32464let isPseudo = 1;
32465let isCodeGenOnly = 1;
32466let DecoderNamespace = "EXT_mmvec";
32467}
32468def V6_vdmpyhsuisat : HInst<
32469(outs HvxVR:$Vd32),
32470(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32471"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32472tc_0b04c6c7, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> {
32473let Inst{7-5} = 0b001;
32474let Inst{13-13} = 0b0;
32475let Inst{31-21} = 0b00011001001;
32476let hasNewValue = 1;
32477let opNewValue = 0;
32478let isCVI = 1;
32479let DecoderNamespace = "EXT_mmvec";
32480}
32481def V6_vdmpyhsuisat_acc : HInst<
32482(outs HvxVR:$Vx32),
32483(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32484"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat",
32485tc_660769f1, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> {
32486let Inst{7-5} = 0b001;
32487let Inst{13-13} = 0b1;
32488let Inst{31-21} = 0b00011001001;
32489let hasNewValue = 1;
32490let opNewValue = 0;
32491let isAccumulator = 1;
32492let isCVI = 1;
32493let DecoderNamespace = "EXT_mmvec";
32494let Constraints = "$Vx32 = $Vx32in";
32495}
32496def V6_vdmpyhsuisat_acc_alt : HInst<
32497(outs HvxVR:$Vx32),
32498(ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32499"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat",
32500PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32501let hasNewValue = 1;
32502let opNewValue = 0;
32503let isAccumulator = 1;
32504let isCVI = 1;
32505let isPseudo = 1;
32506let isCodeGenOnly = 1;
32507let DecoderNamespace = "EXT_mmvec";
32508let Constraints = "$Vx32 = $Vx32in";
32509}
32510def V6_vdmpyhsuisat_alt : HInst<
32511(outs HvxVR:$Vd32),
32512(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32513"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat",
32514PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32515let hasNewValue = 1;
32516let opNewValue = 0;
32517let isCVI = 1;
32518let isPseudo = 1;
32519let isCodeGenOnly = 1;
32520let DecoderNamespace = "EXT_mmvec";
32521}
32522def V6_vdmpyhsusat : HInst<
32523(outs HvxVR:$Vd32),
32524(ins HvxVR:$Vu32, IntRegs:$Rt32),
32525"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat",
32526tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
32527let Inst{7-5} = 0b000;
32528let Inst{13-13} = 0b0;
32529let Inst{31-21} = 0b00011001001;
32530let hasNewValue = 1;
32531let opNewValue = 0;
32532let isCVI = 1;
32533let DecoderNamespace = "EXT_mmvec";
32534}
32535def V6_vdmpyhsusat_acc : HInst<
32536(outs HvxVR:$Vx32),
32537(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32538"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat",
32539tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
32540let Inst{7-5} = 0b000;
32541let Inst{13-13} = 0b1;
32542let Inst{31-21} = 0b00011001001;
32543let hasNewValue = 1;
32544let opNewValue = 0;
32545let isAccumulator = 1;
32546let isCVI = 1;
32547let DecoderNamespace = "EXT_mmvec";
32548let Constraints = "$Vx32 = $Vx32in";
32549}
32550def V6_vdmpyhsusat_acc_alt : HInst<
32551(outs HvxVR:$Vx32),
32552(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
32553"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat",
32554PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32555let hasNewValue = 1;
32556let opNewValue = 0;
32557let isAccumulator = 1;
32558let isCVI = 1;
32559let isPseudo = 1;
32560let isCodeGenOnly = 1;
32561let DecoderNamespace = "EXT_mmvec";
32562let Constraints = "$Vx32 = $Vx32in";
32563}
32564def V6_vdmpyhsusat_alt : HInst<
32565(outs HvxVR:$Vd32),
32566(ins HvxVR:$Vu32, IntRegs:$Rt32),
32567"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat",
32568PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32569let hasNewValue = 1;
32570let opNewValue = 0;
32571let isCVI = 1;
32572let isPseudo = 1;
32573let isCodeGenOnly = 1;
32574let DecoderNamespace = "EXT_mmvec";
32575}
32576def V6_vdmpyhvsat : HInst<
32577(outs HvxVR:$Vd32),
32578(ins HvxVR:$Vu32, HvxVR:$Vv32),
32579"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat",
32580tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
32581let Inst{7-5} = 0b011;
32582let Inst{13-13} = 0b0;
32583let Inst{31-21} = 0b00011100000;
32584let hasNewValue = 1;
32585let opNewValue = 0;
32586let isCVI = 1;
32587let DecoderNamespace = "EXT_mmvec";
32588}
32589def V6_vdmpyhvsat_acc : HInst<
32590(outs HvxVR:$Vx32),
32591(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32592"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat",
32593tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
32594let Inst{7-5} = 0b011;
32595let Inst{13-13} = 0b1;
32596let Inst{31-21} = 0b00011100000;
32597let hasNewValue = 1;
32598let opNewValue = 0;
32599let isAccumulator = 1;
32600let isCVI = 1;
32601let DecoderNamespace = "EXT_mmvec";
32602let Constraints = "$Vx32 = $Vx32in";
32603}
32604def V6_vdmpyhvsat_acc_alt : HInst<
32605(outs HvxVR:$Vx32),
32606(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
32607"$Vx32 += vdmpyh($Vu32,$Vv32):sat",
32608PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32609let hasNewValue = 1;
32610let opNewValue = 0;
32611let isAccumulator = 1;
32612let isCVI = 1;
32613let isPseudo = 1;
32614let isCodeGenOnly = 1;
32615let DecoderNamespace = "EXT_mmvec";
32616let Constraints = "$Vx32 = $Vx32in";
32617}
32618def V6_vdmpyhvsat_alt : HInst<
32619(outs HvxVR:$Vd32),
32620(ins HvxVR:$Vu32, HvxVR:$Vv32),
32621"$Vd32 = vdmpyh($Vu32,$Vv32):sat",
32622PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32623let hasNewValue = 1;
32624let opNewValue = 0;
32625let isCVI = 1;
32626let isPseudo = 1;
32627let isCodeGenOnly = 1;
32628let DecoderNamespace = "EXT_mmvec";
32629}
32630def V6_vdsaduh : HInst<
32631(outs HvxWR:$Vdd32),
32632(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32633"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)",
32634tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
32635let Inst{7-5} = 0b101;
32636let Inst{13-13} = 0b0;
32637let Inst{31-21} = 0b00011001000;
32638let hasNewValue = 1;
32639let opNewValue = 0;
32640let isCVI = 1;
32641let DecoderNamespace = "EXT_mmvec";
32642}
32643def V6_vdsaduh_acc : HInst<
32644(outs HvxWR:$Vxx32),
32645(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32646"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)",
32647tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
32648let Inst{7-5} = 0b000;
32649let Inst{13-13} = 0b1;
32650let Inst{31-21} = 0b00011001011;
32651let hasNewValue = 1;
32652let opNewValue = 0;
32653let isAccumulator = 1;
32654let isCVI = 1;
32655let DecoderNamespace = "EXT_mmvec";
32656let Constraints = "$Vxx32 = $Vxx32in";
32657}
32658def V6_vdsaduh_acc_alt : HInst<
32659(outs HvxWR:$Vxx32),
32660(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
32661"$Vxx32 += vdsaduh($Vuu32,$Rt32)",
32662PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32663let hasNewValue = 1;
32664let opNewValue = 0;
32665let isAccumulator = 1;
32666let isCVI = 1;
32667let isPseudo = 1;
32668let isCodeGenOnly = 1;
32669let DecoderNamespace = "EXT_mmvec";
32670let Constraints = "$Vxx32 = $Vxx32in";
32671}
32672def V6_vdsaduh_alt : HInst<
32673(outs HvxWR:$Vdd32),
32674(ins HvxWR:$Vuu32, IntRegs:$Rt32),
32675"$Vdd32 = vdsaduh($Vuu32,$Rt32)",
32676PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
32677let hasNewValue = 1;
32678let opNewValue = 0;
32679let isCVI = 1;
32680let isPseudo = 1;
32681let isCodeGenOnly = 1;
32682let DecoderNamespace = "EXT_mmvec";
32683}
32684def V6_veqb : HInst<
32685(outs HvxQR:$Qd4),
32686(ins HvxVR:$Vu32, HvxVR:$Vv32),
32687"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)",
32688tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32689let Inst{7-2} = 0b000000;
32690let Inst{13-13} = 0b0;
32691let Inst{31-21} = 0b00011111100;
32692let hasNewValue = 1;
32693let opNewValue = 0;
32694let isCVI = 1;
32695let DecoderNamespace = "EXT_mmvec";
32696}
32697def V6_veqb_and : HInst<
32698(outs HvxQR:$Qx4),
32699(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32700"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)",
32701tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32702let Inst{7-2} = 0b000000;
32703let Inst{13-13} = 0b1;
32704let Inst{31-21} = 0b00011100100;
32705let isCVI = 1;
32706let DecoderNamespace = "EXT_mmvec";
32707let Constraints = "$Qx4 = $Qx4in";
32708}
32709def V6_veqb_or : HInst<
32710(outs HvxQR:$Qx4),
32711(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32712"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)",
32713tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32714let Inst{7-2} = 0b010000;
32715let Inst{13-13} = 0b1;
32716let Inst{31-21} = 0b00011100100;
32717let isAccumulator = 1;
32718let isCVI = 1;
32719let DecoderNamespace = "EXT_mmvec";
32720let Constraints = "$Qx4 = $Qx4in";
32721}
32722def V6_veqb_xor : HInst<
32723(outs HvxQR:$Qx4),
32724(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32725"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)",
32726tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32727let Inst{7-2} = 0b100000;
32728let Inst{13-13} = 0b1;
32729let Inst{31-21} = 0b00011100100;
32730let isCVI = 1;
32731let DecoderNamespace = "EXT_mmvec";
32732let Constraints = "$Qx4 = $Qx4in";
32733}
32734def V6_veqh : HInst<
32735(outs HvxQR:$Qd4),
32736(ins HvxVR:$Vu32, HvxVR:$Vv32),
32737"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)",
32738tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32739let Inst{7-2} = 0b000001;
32740let Inst{13-13} = 0b0;
32741let Inst{31-21} = 0b00011111100;
32742let hasNewValue = 1;
32743let opNewValue = 0;
32744let isCVI = 1;
32745let DecoderNamespace = "EXT_mmvec";
32746}
32747def V6_veqh_and : HInst<
32748(outs HvxQR:$Qx4),
32749(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32750"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)",
32751tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32752let Inst{7-2} = 0b000001;
32753let Inst{13-13} = 0b1;
32754let Inst{31-21} = 0b00011100100;
32755let isCVI = 1;
32756let DecoderNamespace = "EXT_mmvec";
32757let Constraints = "$Qx4 = $Qx4in";
32758}
32759def V6_veqh_or : HInst<
32760(outs HvxQR:$Qx4),
32761(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32762"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)",
32763tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32764let Inst{7-2} = 0b010001;
32765let Inst{13-13} = 0b1;
32766let Inst{31-21} = 0b00011100100;
32767let isAccumulator = 1;
32768let isCVI = 1;
32769let DecoderNamespace = "EXT_mmvec";
32770let Constraints = "$Qx4 = $Qx4in";
32771}
32772def V6_veqh_xor : HInst<
32773(outs HvxQR:$Qx4),
32774(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32775"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)",
32776tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32777let Inst{7-2} = 0b100001;
32778let Inst{13-13} = 0b1;
32779let Inst{31-21} = 0b00011100100;
32780let isCVI = 1;
32781let DecoderNamespace = "EXT_mmvec";
32782let Constraints = "$Qx4 = $Qx4in";
32783}
32784def V6_veqw : HInst<
32785(outs HvxQR:$Qd4),
32786(ins HvxVR:$Vu32, HvxVR:$Vv32),
32787"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)",
32788tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32789let Inst{7-2} = 0b000010;
32790let Inst{13-13} = 0b0;
32791let Inst{31-21} = 0b00011111100;
32792let hasNewValue = 1;
32793let opNewValue = 0;
32794let isCVI = 1;
32795let DecoderNamespace = "EXT_mmvec";
32796}
32797def V6_veqw_and : HInst<
32798(outs HvxQR:$Qx4),
32799(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32800"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)",
32801tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32802let Inst{7-2} = 0b000010;
32803let Inst{13-13} = 0b1;
32804let Inst{31-21} = 0b00011100100;
32805let isCVI = 1;
32806let DecoderNamespace = "EXT_mmvec";
32807let Constraints = "$Qx4 = $Qx4in";
32808}
32809def V6_veqw_or : HInst<
32810(outs HvxQR:$Qx4),
32811(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32812"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)",
32813tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32814let Inst{7-2} = 0b010010;
32815let Inst{13-13} = 0b1;
32816let Inst{31-21} = 0b00011100100;
32817let isAccumulator = 1;
32818let isCVI = 1;
32819let DecoderNamespace = "EXT_mmvec";
32820let Constraints = "$Qx4 = $Qx4in";
32821}
32822def V6_veqw_xor : HInst<
32823(outs HvxQR:$Qx4),
32824(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32825"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)",
32826tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32827let Inst{7-2} = 0b100010;
32828let Inst{13-13} = 0b1;
32829let Inst{31-21} = 0b00011100100;
32830let isCVI = 1;
32831let DecoderNamespace = "EXT_mmvec";
32832let Constraints = "$Qx4 = $Qx4in";
32833}
32834def V6_vgathermh : HInst<
32835(outs),
32836(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32837"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
32838tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
32839let Inst{12-5} = 0b00001000;
32840let Inst{31-21} = 0b00101111000;
32841let hasNewValue = 1;
32842let opNewValue = 0;
32843let accessSize = HalfWordAccess;
32844let isCVLoad = 1;
32845let isCVI = 1;
32846let hasTmpDst = 1;
32847let mayLoad = 1;
32848let Defs = [VTMP];
32849let DecoderNamespace = "EXT_mmvec";
32850}
32851def V6_vgathermhq : HInst<
32852(outs),
32853(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32854"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h",
32855tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
32856let Inst{12-7} = 0b001010;
32857let Inst{31-21} = 0b00101111000;
32858let hasNewValue = 1;
32859let opNewValue = 0;
32860let accessSize = HalfWordAccess;
32861let isCVLoad = 1;
32862let isCVI = 1;
32863let hasTmpDst = 1;
32864let mayLoad = 1;
32865let Defs = [VTMP];
32866let DecoderNamespace = "EXT_mmvec";
32867}
32868def V6_vgathermhw : HInst<
32869(outs),
32870(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32871"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32872tc_7095ecba, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> {
32873let Inst{12-5} = 0b00010000;
32874let Inst{31-21} = 0b00101111000;
32875let hasNewValue = 1;
32876let opNewValue = 0;
32877let accessSize = HalfWordAccess;
32878let isCVLoad = 1;
32879let isCVI = 1;
32880let hasTmpDst = 1;
32881let mayLoad = 1;
32882let Defs = [VTMP];
32883let DecoderNamespace = "EXT_mmvec";
32884}
32885def V6_vgathermhwq : HInst<
32886(outs),
32887(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32),
32888"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h",
32889tc_a69eeee1, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> {
32890let Inst{12-7} = 0b001100;
32891let Inst{31-21} = 0b00101111000;
32892let hasNewValue = 1;
32893let opNewValue = 0;
32894let accessSize = HalfWordAccess;
32895let isCVLoad = 1;
32896let isCVI = 1;
32897let hasTmpDst = 1;
32898let mayLoad = 1;
32899let Defs = [VTMP];
32900let DecoderNamespace = "EXT_mmvec";
32901}
32902def V6_vgathermw : HInst<
32903(outs),
32904(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32905"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32906tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> {
32907let Inst{12-5} = 0b00000000;
32908let Inst{31-21} = 0b00101111000;
32909let hasNewValue = 1;
32910let opNewValue = 0;
32911let accessSize = WordAccess;
32912let isCVLoad = 1;
32913let isCVI = 1;
32914let hasTmpDst = 1;
32915let mayLoad = 1;
32916let Defs = [VTMP];
32917let DecoderNamespace = "EXT_mmvec";
32918}
32919def V6_vgathermwq : HInst<
32920(outs),
32921(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32),
32922"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w",
32923tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> {
32924let Inst{12-7} = 0b001000;
32925let Inst{31-21} = 0b00101111000;
32926let hasNewValue = 1;
32927let opNewValue = 0;
32928let accessSize = WordAccess;
32929let isCVLoad = 1;
32930let isCVI = 1;
32931let hasTmpDst = 1;
32932let mayLoad = 1;
32933let Defs = [VTMP];
32934let DecoderNamespace = "EXT_mmvec";
32935}
32936def V6_vgtb : HInst<
32937(outs HvxQR:$Qd4),
32938(ins HvxVR:$Vu32, HvxVR:$Vv32),
32939"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)",
32940tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32941let Inst{7-2} = 0b000100;
32942let Inst{13-13} = 0b0;
32943let Inst{31-21} = 0b00011111100;
32944let hasNewValue = 1;
32945let opNewValue = 0;
32946let isCVI = 1;
32947let DecoderNamespace = "EXT_mmvec";
32948}
32949def V6_vgtb_and : HInst<
32950(outs HvxQR:$Qx4),
32951(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32952"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)",
32953tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32954let Inst{7-2} = 0b000100;
32955let Inst{13-13} = 0b1;
32956let Inst{31-21} = 0b00011100100;
32957let isCVI = 1;
32958let DecoderNamespace = "EXT_mmvec";
32959let Constraints = "$Qx4 = $Qx4in";
32960}
32961def V6_vgtb_or : HInst<
32962(outs HvxQR:$Qx4),
32963(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32964"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)",
32965tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32966let Inst{7-2} = 0b010100;
32967let Inst{13-13} = 0b1;
32968let Inst{31-21} = 0b00011100100;
32969let isAccumulator = 1;
32970let isCVI = 1;
32971let DecoderNamespace = "EXT_mmvec";
32972let Constraints = "$Qx4 = $Qx4in";
32973}
32974def V6_vgtb_xor : HInst<
32975(outs HvxQR:$Qx4),
32976(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
32977"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)",
32978tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
32979let Inst{7-2} = 0b100100;
32980let Inst{13-13} = 0b1;
32981let Inst{31-21} = 0b00011100100;
32982let isCVI = 1;
32983let DecoderNamespace = "EXT_mmvec";
32984let Constraints = "$Qx4 = $Qx4in";
32985}
32986def V6_vgth : HInst<
32987(outs HvxQR:$Qd4),
32988(ins HvxVR:$Vu32, HvxVR:$Vv32),
32989"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)",
32990tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
32991let Inst{7-2} = 0b000101;
32992let Inst{13-13} = 0b0;
32993let Inst{31-21} = 0b00011111100;
32994let hasNewValue = 1;
32995let opNewValue = 0;
32996let isCVI = 1;
32997let DecoderNamespace = "EXT_mmvec";
32998}
32999def V6_vgth_and : HInst<
33000(outs HvxQR:$Qx4),
33001(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33002"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)",
33003tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33004let Inst{7-2} = 0b000101;
33005let Inst{13-13} = 0b1;
33006let Inst{31-21} = 0b00011100100;
33007let isCVI = 1;
33008let DecoderNamespace = "EXT_mmvec";
33009let Constraints = "$Qx4 = $Qx4in";
33010}
33011def V6_vgth_or : HInst<
33012(outs HvxQR:$Qx4),
33013(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33014"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)",
33015tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33016let Inst{7-2} = 0b010101;
33017let Inst{13-13} = 0b1;
33018let Inst{31-21} = 0b00011100100;
33019let isAccumulator = 1;
33020let isCVI = 1;
33021let DecoderNamespace = "EXT_mmvec";
33022let Constraints = "$Qx4 = $Qx4in";
33023}
33024def V6_vgth_xor : HInst<
33025(outs HvxQR:$Qx4),
33026(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33027"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)",
33028tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33029let Inst{7-2} = 0b100101;
33030let Inst{13-13} = 0b1;
33031let Inst{31-21} = 0b00011100100;
33032let isCVI = 1;
33033let DecoderNamespace = "EXT_mmvec";
33034let Constraints = "$Qx4 = $Qx4in";
33035}
33036def V6_vgtub : HInst<
33037(outs HvxQR:$Qd4),
33038(ins HvxVR:$Vu32, HvxVR:$Vv32),
33039"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)",
33040tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33041let Inst{7-2} = 0b001000;
33042let Inst{13-13} = 0b0;
33043let Inst{31-21} = 0b00011111100;
33044let hasNewValue = 1;
33045let opNewValue = 0;
33046let isCVI = 1;
33047let DecoderNamespace = "EXT_mmvec";
33048}
33049def V6_vgtub_and : HInst<
33050(outs HvxQR:$Qx4),
33051(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33052"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)",
33053tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33054let Inst{7-2} = 0b001000;
33055let Inst{13-13} = 0b1;
33056let Inst{31-21} = 0b00011100100;
33057let isCVI = 1;
33058let DecoderNamespace = "EXT_mmvec";
33059let Constraints = "$Qx4 = $Qx4in";
33060}
33061def V6_vgtub_or : HInst<
33062(outs HvxQR:$Qx4),
33063(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33064"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)",
33065tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33066let Inst{7-2} = 0b011000;
33067let Inst{13-13} = 0b1;
33068let Inst{31-21} = 0b00011100100;
33069let isAccumulator = 1;
33070let isCVI = 1;
33071let DecoderNamespace = "EXT_mmvec";
33072let Constraints = "$Qx4 = $Qx4in";
33073}
33074def V6_vgtub_xor : HInst<
33075(outs HvxQR:$Qx4),
33076(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33077"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)",
33078tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33079let Inst{7-2} = 0b101000;
33080let Inst{13-13} = 0b1;
33081let Inst{31-21} = 0b00011100100;
33082let isCVI = 1;
33083let DecoderNamespace = "EXT_mmvec";
33084let Constraints = "$Qx4 = $Qx4in";
33085}
33086def V6_vgtuh : HInst<
33087(outs HvxQR:$Qd4),
33088(ins HvxVR:$Vu32, HvxVR:$Vv32),
33089"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)",
33090tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33091let Inst{7-2} = 0b001001;
33092let Inst{13-13} = 0b0;
33093let Inst{31-21} = 0b00011111100;
33094let hasNewValue = 1;
33095let opNewValue = 0;
33096let isCVI = 1;
33097let DecoderNamespace = "EXT_mmvec";
33098}
33099def V6_vgtuh_and : HInst<
33100(outs HvxQR:$Qx4),
33101(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33102"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)",
33103tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33104let Inst{7-2} = 0b001001;
33105let Inst{13-13} = 0b1;
33106let Inst{31-21} = 0b00011100100;
33107let isCVI = 1;
33108let DecoderNamespace = "EXT_mmvec";
33109let Constraints = "$Qx4 = $Qx4in";
33110}
33111def V6_vgtuh_or : HInst<
33112(outs HvxQR:$Qx4),
33113(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33114"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)",
33115tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33116let Inst{7-2} = 0b011001;
33117let Inst{13-13} = 0b1;
33118let Inst{31-21} = 0b00011100100;
33119let isAccumulator = 1;
33120let isCVI = 1;
33121let DecoderNamespace = "EXT_mmvec";
33122let Constraints = "$Qx4 = $Qx4in";
33123}
33124def V6_vgtuh_xor : HInst<
33125(outs HvxQR:$Qx4),
33126(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33127"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)",
33128tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33129let Inst{7-2} = 0b101001;
33130let Inst{13-13} = 0b1;
33131let Inst{31-21} = 0b00011100100;
33132let isCVI = 1;
33133let DecoderNamespace = "EXT_mmvec";
33134let Constraints = "$Qx4 = $Qx4in";
33135}
33136def V6_vgtuw : HInst<
33137(outs HvxQR:$Qd4),
33138(ins HvxVR:$Vu32, HvxVR:$Vv32),
33139"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)",
33140tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33141let Inst{7-2} = 0b001010;
33142let Inst{13-13} = 0b0;
33143let Inst{31-21} = 0b00011111100;
33144let hasNewValue = 1;
33145let opNewValue = 0;
33146let isCVI = 1;
33147let DecoderNamespace = "EXT_mmvec";
33148}
33149def V6_vgtuw_and : HInst<
33150(outs HvxQR:$Qx4),
33151(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33152"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)",
33153tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33154let Inst{7-2} = 0b001010;
33155let Inst{13-13} = 0b1;
33156let Inst{31-21} = 0b00011100100;
33157let isCVI = 1;
33158let DecoderNamespace = "EXT_mmvec";
33159let Constraints = "$Qx4 = $Qx4in";
33160}
33161def V6_vgtuw_or : HInst<
33162(outs HvxQR:$Qx4),
33163(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33164"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)",
33165tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33166let Inst{7-2} = 0b011010;
33167let Inst{13-13} = 0b1;
33168let Inst{31-21} = 0b00011100100;
33169let isAccumulator = 1;
33170let isCVI = 1;
33171let DecoderNamespace = "EXT_mmvec";
33172let Constraints = "$Qx4 = $Qx4in";
33173}
33174def V6_vgtuw_xor : HInst<
33175(outs HvxQR:$Qx4),
33176(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33177"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)",
33178tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33179let Inst{7-2} = 0b101010;
33180let Inst{13-13} = 0b1;
33181let Inst{31-21} = 0b00011100100;
33182let isCVI = 1;
33183let DecoderNamespace = "EXT_mmvec";
33184let Constraints = "$Qx4 = $Qx4in";
33185}
33186def V6_vgtw : HInst<
33187(outs HvxQR:$Qd4),
33188(ins HvxVR:$Vu32, HvxVR:$Vv32),
33189"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)",
33190tc_56c4f9fe, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> {
33191let Inst{7-2} = 0b000110;
33192let Inst{13-13} = 0b0;
33193let Inst{31-21} = 0b00011111100;
33194let hasNewValue = 1;
33195let opNewValue = 0;
33196let isCVI = 1;
33197let DecoderNamespace = "EXT_mmvec";
33198}
33199def V6_vgtw_and : HInst<
33200(outs HvxQR:$Qx4),
33201(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33202"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)",
33203tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33204let Inst{7-2} = 0b000110;
33205let Inst{13-13} = 0b1;
33206let Inst{31-21} = 0b00011100100;
33207let isCVI = 1;
33208let DecoderNamespace = "EXT_mmvec";
33209let Constraints = "$Qx4 = $Qx4in";
33210}
33211def V6_vgtw_or : HInst<
33212(outs HvxQR:$Qx4),
33213(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33214"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)",
33215tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33216let Inst{7-2} = 0b010110;
33217let Inst{13-13} = 0b1;
33218let Inst{31-21} = 0b00011100100;
33219let isAccumulator = 1;
33220let isCVI = 1;
33221let DecoderNamespace = "EXT_mmvec";
33222let Constraints = "$Qx4 = $Qx4in";
33223}
33224def V6_vgtw_xor : HInst<
33225(outs HvxQR:$Qx4),
33226(ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32),
33227"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)",
33228tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> {
33229let Inst{7-2} = 0b100110;
33230let Inst{13-13} = 0b1;
33231let Inst{31-21} = 0b00011100100;
33232let isCVI = 1;
33233let DecoderNamespace = "EXT_mmvec";
33234let Constraints = "$Qx4 = $Qx4in";
33235}
33236def V6_vhist : HInst<
33237(outs),
33238(ins),
33239"vhist",
33240tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> {
33241let Inst{13-0} = 0b10000010000000;
33242let Inst{31-16} = 0b0001111000000000;
33243let isCVI = 1;
33244let DecoderNamespace = "EXT_mmvec";
33245}
33246def V6_vhistq : HInst<
33247(outs),
33248(ins HvxQR:$Qv4),
33249"vhist($Qv4)",
33250tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> {
33251let Inst{13-0} = 0b10000010000000;
33252let Inst{21-16} = 0b000010;
33253let Inst{31-24} = 0b00011110;
33254let isCVI = 1;
33255let DecoderNamespace = "EXT_mmvec";
33256}
33257def V6_vinsertwr : HInst<
33258(outs HvxVR:$Vx32),
33259(ins HvxVR:$Vx32in, IntRegs:$Rt32),
33260"$Vx32.w = vinsert($Rt32)",
33261tc_ac4046bc, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> {
33262let Inst{13-5} = 0b100000001;
33263let Inst{31-21} = 0b00011001101;
33264let hasNewValue = 1;
33265let opNewValue = 0;
33266let isCVI = 1;
33267let DecoderNamespace = "EXT_mmvec";
33268let Constraints = "$Vx32 = $Vx32in";
33269}
33270def V6_vlalignb : HInst<
33271(outs HvxVR:$Vd32),
33272(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33273"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)",
33274tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
33275let Inst{7-5} = 0b001;
33276let Inst{13-13} = 0b0;
33277let Inst{31-24} = 0b00011011;
33278let hasNewValue = 1;
33279let opNewValue = 0;
33280let isCVI = 1;
33281let DecoderNamespace = "EXT_mmvec";
33282}
33283def V6_vlalignbi : HInst<
33284(outs HvxVR:$Vd32),
33285(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33286"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)",
33287tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> {
33288let Inst{13-13} = 0b1;
33289let Inst{31-21} = 0b00011110011;
33290let hasNewValue = 1;
33291let opNewValue = 0;
33292let isCVI = 1;
33293let DecoderNamespace = "EXT_mmvec";
33294}
33295def V6_vlsrb : HInst<
33296(outs HvxVR:$Vd32),
33297(ins HvxVR:$Vu32, IntRegs:$Rt32),
33298"$Vd32.ub = vlsr($Vu32.ub,$Rt32)",
33299tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> {
33300let Inst{7-5} = 0b011;
33301let Inst{13-13} = 0b0;
33302let Inst{31-21} = 0b00011001100;
33303let hasNewValue = 1;
33304let opNewValue = 0;
33305let isCVI = 1;
33306let DecoderNamespace = "EXT_mmvec";
33307}
33308def V6_vlsrh : HInst<
33309(outs HvxVR:$Vd32),
33310(ins HvxVR:$Vu32, IntRegs:$Rt32),
33311"$Vd32.uh = vlsr($Vu32.uh,$Rt32)",
33312tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33313let Inst{7-5} = 0b010;
33314let Inst{13-13} = 0b0;
33315let Inst{31-21} = 0b00011001100;
33316let hasNewValue = 1;
33317let opNewValue = 0;
33318let isCVI = 1;
33319let DecoderNamespace = "EXT_mmvec";
33320}
33321def V6_vlsrh_alt : HInst<
33322(outs HvxVR:$Vd32),
33323(ins HvxVR:$Vu32, IntRegs:$Rt32),
33324"$Vd32 = vlsrh($Vu32,$Rt32)",
33325PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33326let hasNewValue = 1;
33327let opNewValue = 0;
33328let isCVI = 1;
33329let isPseudo = 1;
33330let isCodeGenOnly = 1;
33331let DecoderNamespace = "EXT_mmvec";
33332}
33333def V6_vlsrhv : HInst<
33334(outs HvxVR:$Vd32),
33335(ins HvxVR:$Vu32, HvxVR:$Vv32),
33336"$Vd32.h = vlsr($Vu32.h,$Vv32.h)",
33337tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
33338let Inst{7-5} = 0b010;
33339let Inst{13-13} = 0b0;
33340let Inst{31-21} = 0b00011111101;
33341let hasNewValue = 1;
33342let opNewValue = 0;
33343let isCVI = 1;
33344let DecoderNamespace = "EXT_mmvec";
33345}
33346def V6_vlsrhv_alt : HInst<
33347(outs HvxVR:$Vd32),
33348(ins HvxVR:$Vu32, HvxVR:$Vv32),
33349"$Vd32 = vlsrh($Vu32,$Vv32)",
33350PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33351let hasNewValue = 1;
33352let opNewValue = 0;
33353let isCVI = 1;
33354let isPseudo = 1;
33355let isCodeGenOnly = 1;
33356let DecoderNamespace = "EXT_mmvec";
33357}
33358def V6_vlsrw : HInst<
33359(outs HvxVR:$Vd32),
33360(ins HvxVR:$Vu32, IntRegs:$Rt32),
33361"$Vd32.uw = vlsr($Vu32.uw,$Rt32)",
33362tc_7417e785, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> {
33363let Inst{7-5} = 0b001;
33364let Inst{13-13} = 0b0;
33365let Inst{31-21} = 0b00011001100;
33366let hasNewValue = 1;
33367let opNewValue = 0;
33368let isCVI = 1;
33369let DecoderNamespace = "EXT_mmvec";
33370}
33371def V6_vlsrw_alt : HInst<
33372(outs HvxVR:$Vd32),
33373(ins HvxVR:$Vu32, IntRegs:$Rt32),
33374"$Vd32 = vlsrw($Vu32,$Rt32)",
33375PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33376let hasNewValue = 1;
33377let opNewValue = 0;
33378let isCVI = 1;
33379let isPseudo = 1;
33380let isCodeGenOnly = 1;
33381let DecoderNamespace = "EXT_mmvec";
33382}
33383def V6_vlsrwv : HInst<
33384(outs HvxVR:$Vd32),
33385(ins HvxVR:$Vu32, HvxVR:$Vv32),
33386"$Vd32.w = vlsr($Vu32.w,$Vv32.w)",
33387tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
33388let Inst{7-5} = 0b001;
33389let Inst{13-13} = 0b0;
33390let Inst{31-21} = 0b00011111101;
33391let hasNewValue = 1;
33392let opNewValue = 0;
33393let isCVI = 1;
33394let DecoderNamespace = "EXT_mmvec";
33395}
33396def V6_vlsrwv_alt : HInst<
33397(outs HvxVR:$Vd32),
33398(ins HvxVR:$Vu32, HvxVR:$Vv32),
33399"$Vd32 = vlsrw($Vu32,$Vv32)",
33400PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33401let hasNewValue = 1;
33402let opNewValue = 0;
33403let isCVI = 1;
33404let isPseudo = 1;
33405let isCodeGenOnly = 1;
33406let DecoderNamespace = "EXT_mmvec";
33407}
33408def V6_vlut4 : HInst<
33409(outs HvxVR:$Vd32),
33410(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
33411"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)",
33412tc_f1de44ef, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> {
33413let Inst{7-5} = 0b100;
33414let Inst{13-13} = 0b0;
33415let Inst{31-21} = 0b00011001011;
33416let hasNewValue = 1;
33417let opNewValue = 0;
33418let isCVI = 1;
33419let DecoderNamespace = "EXT_mmvec";
33420}
33421def V6_vlutvvb : HInst<
33422(outs HvxVR:$Vd32),
33423(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33424"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)",
33425tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> {
33426let Inst{7-5} = 0b001;
33427let Inst{13-13} = 0b1;
33428let Inst{31-24} = 0b00011011;
33429let hasNewValue = 1;
33430let opNewValue = 0;
33431let isCVI = 1;
33432let DecoderNamespace = "EXT_mmvec";
33433}
33434def V6_vlutvvb_nm : HInst<
33435(outs HvxVR:$Vd32),
33436(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33437"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch",
33438tc_56e64202, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> {
33439let Inst{7-5} = 0b011;
33440let Inst{13-13} = 0b0;
33441let Inst{31-24} = 0b00011000;
33442let hasNewValue = 1;
33443let opNewValue = 0;
33444let isCVI = 1;
33445let DecoderNamespace = "EXT_mmvec";
33446}
33447def V6_vlutvvb_oracc : HInst<
33448(outs HvxVR:$Vx32),
33449(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33450"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)",
33451tc_9d1dc972, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> {
33452let Inst{7-5} = 0b101;
33453let Inst{13-13} = 0b1;
33454let Inst{31-24} = 0b00011011;
33455let hasNewValue = 1;
33456let opNewValue = 0;
33457let isAccumulator = 1;
33458let isCVI = 1;
33459let DecoderNamespace = "EXT_mmvec";
33460let Constraints = "$Vx32 = $Vx32in";
33461}
33462def V6_vlutvvb_oracci : HInst<
33463(outs HvxVR:$Vx32),
33464(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33465"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)",
33466tc_9d1dc972, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> {
33467let Inst{13-13} = 0b1;
33468let Inst{31-21} = 0b00011100110;
33469let hasNewValue = 1;
33470let opNewValue = 0;
33471let isAccumulator = 1;
33472let isCVI = 1;
33473let DecoderNamespace = "EXT_mmvec";
33474let Constraints = "$Vx32 = $Vx32in";
33475}
33476def V6_vlutvvbi : HInst<
33477(outs HvxVR:$Vd32),
33478(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33479"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)",
33480tc_56e64202, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> {
33481let Inst{13-13} = 0b0;
33482let Inst{31-21} = 0b00011110001;
33483let hasNewValue = 1;
33484let opNewValue = 0;
33485let isCVI = 1;
33486let DecoderNamespace = "EXT_mmvec";
33487}
33488def V6_vlutvwh : HInst<
33489(outs HvxWR:$Vdd32),
33490(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33491"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)",
33492tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
33493let Inst{7-5} = 0b110;
33494let Inst{13-13} = 0b1;
33495let Inst{31-24} = 0b00011011;
33496let hasNewValue = 1;
33497let opNewValue = 0;
33498let isCVI = 1;
33499let DecoderNamespace = "EXT_mmvec";
33500}
33501def V6_vlutvwh_nm : HInst<
33502(outs HvxWR:$Vdd32),
33503(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33504"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch",
33505tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> {
33506let Inst{7-5} = 0b100;
33507let Inst{13-13} = 0b0;
33508let Inst{31-24} = 0b00011000;
33509let hasNewValue = 1;
33510let opNewValue = 0;
33511let isCVI = 1;
33512let DecoderNamespace = "EXT_mmvec";
33513}
33514def V6_vlutvwh_oracc : HInst<
33515(outs HvxWR:$Vxx32),
33516(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
33517"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)",
33518tc_9d1dc972, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> {
33519let Inst{7-5} = 0b111;
33520let Inst{13-13} = 0b1;
33521let Inst{31-24} = 0b00011011;
33522let hasNewValue = 1;
33523let opNewValue = 0;
33524let isAccumulator = 1;
33525let isCVI = 1;
33526let DecoderNamespace = "EXT_mmvec";
33527let Constraints = "$Vxx32 = $Vxx32in";
33528}
33529def V6_vlutvwh_oracci : HInst<
33530(outs HvxWR:$Vxx32),
33531(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33532"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)",
33533tc_9d1dc972, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> {
33534let Inst{13-13} = 0b1;
33535let Inst{31-21} = 0b00011100111;
33536let hasNewValue = 1;
33537let opNewValue = 0;
33538let isAccumulator = 1;
33539let isCVI = 1;
33540let DecoderNamespace = "EXT_mmvec";
33541let Constraints = "$Vxx32 = $Vxx32in";
33542}
33543def V6_vlutvwhi : HInst<
33544(outs HvxWR:$Vdd32),
33545(ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii),
33546"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)",
33547tc_87adc037, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> {
33548let Inst{13-13} = 0b0;
33549let Inst{31-21} = 0b00011110011;
33550let hasNewValue = 1;
33551let opNewValue = 0;
33552let isCVI = 1;
33553let DecoderNamespace = "EXT_mmvec";
33554}
33555def V6_vmaxb : HInst<
33556(outs HvxVR:$Vd32),
33557(ins HvxVR:$Vu32, HvxVR:$Vv32),
33558"$Vd32.b = vmax($Vu32.b,$Vv32.b)",
33559tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
33560let Inst{7-5} = 0b101;
33561let Inst{13-13} = 0b0;
33562let Inst{31-21} = 0b00011111001;
33563let hasNewValue = 1;
33564let opNewValue = 0;
33565let isCVI = 1;
33566let DecoderNamespace = "EXT_mmvec";
33567}
33568def V6_vmaxb_alt : HInst<
33569(outs HvxVR:$Vd32),
33570(ins HvxVR:$Vu32, HvxVR:$Vv32),
33571"$Vd32 = vmaxb($Vu32,$Vv32)",
33572PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33573let hasNewValue = 1;
33574let opNewValue = 0;
33575let isCVI = 1;
33576let isPseudo = 1;
33577let isCodeGenOnly = 1;
33578let DecoderNamespace = "EXT_mmvec";
33579}
33580def V6_vmaxh : HInst<
33581(outs HvxVR:$Vd32),
33582(ins HvxVR:$Vu32, HvxVR:$Vv32),
33583"$Vd32.h = vmax($Vu32.h,$Vv32.h)",
33584tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33585let Inst{7-5} = 0b111;
33586let Inst{13-13} = 0b0;
33587let Inst{31-21} = 0b00011111000;
33588let hasNewValue = 1;
33589let opNewValue = 0;
33590let isCVI = 1;
33591let DecoderNamespace = "EXT_mmvec";
33592}
33593def V6_vmaxh_alt : HInst<
33594(outs HvxVR:$Vd32),
33595(ins HvxVR:$Vu32, HvxVR:$Vv32),
33596"$Vd32 = vmaxh($Vu32,$Vv32)",
33597PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33598let hasNewValue = 1;
33599let opNewValue = 0;
33600let isCVI = 1;
33601let isPseudo = 1;
33602let isCodeGenOnly = 1;
33603let DecoderNamespace = "EXT_mmvec";
33604}
33605def V6_vmaxub : HInst<
33606(outs HvxVR:$Vd32),
33607(ins HvxVR:$Vu32, HvxVR:$Vv32),
33608"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)",
33609tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33610let Inst{7-5} = 0b101;
33611let Inst{13-13} = 0b0;
33612let Inst{31-21} = 0b00011111000;
33613let hasNewValue = 1;
33614let opNewValue = 0;
33615let isCVI = 1;
33616let DecoderNamespace = "EXT_mmvec";
33617}
33618def V6_vmaxub_alt : HInst<
33619(outs HvxVR:$Vd32),
33620(ins HvxVR:$Vu32, HvxVR:$Vv32),
33621"$Vd32 = vmaxub($Vu32,$Vv32)",
33622PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33623let hasNewValue = 1;
33624let opNewValue = 0;
33625let isCVI = 1;
33626let isPseudo = 1;
33627let isCodeGenOnly = 1;
33628let DecoderNamespace = "EXT_mmvec";
33629}
33630def V6_vmaxuh : HInst<
33631(outs HvxVR:$Vd32),
33632(ins HvxVR:$Vu32, HvxVR:$Vv32),
33633"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)",
33634tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33635let Inst{7-5} = 0b110;
33636let Inst{13-13} = 0b0;
33637let Inst{31-21} = 0b00011111000;
33638let hasNewValue = 1;
33639let opNewValue = 0;
33640let isCVI = 1;
33641let DecoderNamespace = "EXT_mmvec";
33642}
33643def V6_vmaxuh_alt : HInst<
33644(outs HvxVR:$Vd32),
33645(ins HvxVR:$Vu32, HvxVR:$Vv32),
33646"$Vd32 = vmaxuh($Vu32,$Vv32)",
33647PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33648let hasNewValue = 1;
33649let opNewValue = 0;
33650let isCVI = 1;
33651let isPseudo = 1;
33652let isCodeGenOnly = 1;
33653let DecoderNamespace = "EXT_mmvec";
33654}
33655def V6_vmaxw : HInst<
33656(outs HvxVR:$Vd32),
33657(ins HvxVR:$Vu32, HvxVR:$Vv32),
33658"$Vd32.w = vmax($Vu32.w,$Vv32.w)",
33659tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33660let Inst{7-5} = 0b000;
33661let Inst{13-13} = 0b0;
33662let Inst{31-21} = 0b00011111001;
33663let hasNewValue = 1;
33664let opNewValue = 0;
33665let isCVI = 1;
33666let DecoderNamespace = "EXT_mmvec";
33667}
33668def V6_vmaxw_alt : HInst<
33669(outs HvxVR:$Vd32),
33670(ins HvxVR:$Vu32, HvxVR:$Vv32),
33671"$Vd32 = vmaxw($Vu32,$Vv32)",
33672PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33673let hasNewValue = 1;
33674let opNewValue = 0;
33675let isCVI = 1;
33676let isPseudo = 1;
33677let isCodeGenOnly = 1;
33678let DecoderNamespace = "EXT_mmvec";
33679}
33680def V6_vminb : HInst<
33681(outs HvxVR:$Vd32),
33682(ins HvxVR:$Vu32, HvxVR:$Vv32),
33683"$Vd32.b = vmin($Vu32.b,$Vv32.b)",
33684tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
33685let Inst{7-5} = 0b100;
33686let Inst{13-13} = 0b0;
33687let Inst{31-21} = 0b00011111001;
33688let hasNewValue = 1;
33689let opNewValue = 0;
33690let isCVI = 1;
33691let DecoderNamespace = "EXT_mmvec";
33692}
33693def V6_vminb_alt : HInst<
33694(outs HvxVR:$Vd32),
33695(ins HvxVR:$Vu32, HvxVR:$Vv32),
33696"$Vd32 = vminb($Vu32,$Vv32)",
33697PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
33698let hasNewValue = 1;
33699let opNewValue = 0;
33700let isCVI = 1;
33701let isPseudo = 1;
33702let isCodeGenOnly = 1;
33703let DecoderNamespace = "EXT_mmvec";
33704}
33705def V6_vminh : HInst<
33706(outs HvxVR:$Vd32),
33707(ins HvxVR:$Vu32, HvxVR:$Vv32),
33708"$Vd32.h = vmin($Vu32.h,$Vv32.h)",
33709tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33710let Inst{7-5} = 0b011;
33711let Inst{13-13} = 0b0;
33712let Inst{31-21} = 0b00011111000;
33713let hasNewValue = 1;
33714let opNewValue = 0;
33715let isCVI = 1;
33716let DecoderNamespace = "EXT_mmvec";
33717}
33718def V6_vminh_alt : HInst<
33719(outs HvxVR:$Vd32),
33720(ins HvxVR:$Vu32, HvxVR:$Vv32),
33721"$Vd32 = vminh($Vu32,$Vv32)",
33722PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33723let hasNewValue = 1;
33724let opNewValue = 0;
33725let isCVI = 1;
33726let isPseudo = 1;
33727let isCodeGenOnly = 1;
33728let DecoderNamespace = "EXT_mmvec";
33729}
33730def V6_vminub : HInst<
33731(outs HvxVR:$Vd32),
33732(ins HvxVR:$Vu32, HvxVR:$Vv32),
33733"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)",
33734tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33735let Inst{7-5} = 0b001;
33736let Inst{13-13} = 0b0;
33737let Inst{31-21} = 0b00011111000;
33738let hasNewValue = 1;
33739let opNewValue = 0;
33740let isCVI = 1;
33741let DecoderNamespace = "EXT_mmvec";
33742}
33743def V6_vminub_alt : HInst<
33744(outs HvxVR:$Vd32),
33745(ins HvxVR:$Vu32, HvxVR:$Vv32),
33746"$Vd32 = vminub($Vu32,$Vv32)",
33747PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33748let hasNewValue = 1;
33749let opNewValue = 0;
33750let isCVI = 1;
33751let isPseudo = 1;
33752let isCodeGenOnly = 1;
33753let DecoderNamespace = "EXT_mmvec";
33754}
33755def V6_vminuh : HInst<
33756(outs HvxVR:$Vd32),
33757(ins HvxVR:$Vu32, HvxVR:$Vv32),
33758"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)",
33759tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33760let Inst{7-5} = 0b010;
33761let Inst{13-13} = 0b0;
33762let Inst{31-21} = 0b00011111000;
33763let hasNewValue = 1;
33764let opNewValue = 0;
33765let isCVI = 1;
33766let DecoderNamespace = "EXT_mmvec";
33767}
33768def V6_vminuh_alt : HInst<
33769(outs HvxVR:$Vd32),
33770(ins HvxVR:$Vu32, HvxVR:$Vv32),
33771"$Vd32 = vminuh($Vu32,$Vv32)",
33772PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33773let hasNewValue = 1;
33774let opNewValue = 0;
33775let isCVI = 1;
33776let isPseudo = 1;
33777let isCodeGenOnly = 1;
33778let DecoderNamespace = "EXT_mmvec";
33779}
33780def V6_vminw : HInst<
33781(outs HvxVR:$Vd32),
33782(ins HvxVR:$Vu32, HvxVR:$Vv32),
33783"$Vd32.w = vmin($Vu32.w,$Vv32.w)",
33784tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
33785let Inst{7-5} = 0b100;
33786let Inst{13-13} = 0b0;
33787let Inst{31-21} = 0b00011111000;
33788let hasNewValue = 1;
33789let opNewValue = 0;
33790let isCVI = 1;
33791let DecoderNamespace = "EXT_mmvec";
33792}
33793def V6_vminw_alt : HInst<
33794(outs HvxVR:$Vd32),
33795(ins HvxVR:$Vu32, HvxVR:$Vv32),
33796"$Vd32 = vminw($Vu32,$Vv32)",
33797PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33798let hasNewValue = 1;
33799let opNewValue = 0;
33800let isCVI = 1;
33801let isPseudo = 1;
33802let isCodeGenOnly = 1;
33803let DecoderNamespace = "EXT_mmvec";
33804}
33805def V6_vmpabus : HInst<
33806(outs HvxWR:$Vdd32),
33807(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33808"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)",
33809tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33810let Inst{7-5} = 0b110;
33811let Inst{13-13} = 0b0;
33812let Inst{31-21} = 0b00011001001;
33813let hasNewValue = 1;
33814let opNewValue = 0;
33815let isCVI = 1;
33816let DecoderNamespace = "EXT_mmvec";
33817}
33818def V6_vmpabus_acc : HInst<
33819(outs HvxWR:$Vxx32),
33820(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33821"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)",
33822tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33823let Inst{7-5} = 0b110;
33824let Inst{13-13} = 0b1;
33825let Inst{31-21} = 0b00011001001;
33826let hasNewValue = 1;
33827let opNewValue = 0;
33828let isAccumulator = 1;
33829let isCVI = 1;
33830let DecoderNamespace = "EXT_mmvec";
33831let Constraints = "$Vxx32 = $Vxx32in";
33832}
33833def V6_vmpabus_acc_alt : HInst<
33834(outs HvxWR:$Vxx32),
33835(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33836"$Vxx32 += vmpabus($Vuu32,$Rt32)",
33837PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33838let hasNewValue = 1;
33839let opNewValue = 0;
33840let isAccumulator = 1;
33841let isCVI = 1;
33842let isPseudo = 1;
33843let isCodeGenOnly = 1;
33844let DecoderNamespace = "EXT_mmvec";
33845let Constraints = "$Vxx32 = $Vxx32in";
33846}
33847def V6_vmpabus_alt : HInst<
33848(outs HvxWR:$Vdd32),
33849(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33850"$Vdd32 = vmpabus($Vuu32,$Rt32)",
33851PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33852let hasNewValue = 1;
33853let opNewValue = 0;
33854let isCVI = 1;
33855let isPseudo = 1;
33856let isCodeGenOnly = 1;
33857let DecoderNamespace = "EXT_mmvec";
33858}
33859def V6_vmpabusv : HInst<
33860(outs HvxWR:$Vdd32),
33861(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33862"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)",
33863tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
33864let Inst{7-5} = 0b011;
33865let Inst{13-13} = 0b0;
33866let Inst{31-21} = 0b00011100001;
33867let hasNewValue = 1;
33868let opNewValue = 0;
33869let isCVI = 1;
33870let DecoderNamespace = "EXT_mmvec";
33871}
33872def V6_vmpabusv_alt : HInst<
33873(outs HvxWR:$Vdd32),
33874(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33875"$Vdd32 = vmpabus($Vuu32,$Vvv32)",
33876PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33877let hasNewValue = 1;
33878let opNewValue = 0;
33879let isCVI = 1;
33880let isPseudo = 1;
33881let isCodeGenOnly = 1;
33882let DecoderNamespace = "EXT_mmvec";
33883}
33884def V6_vmpabuu : HInst<
33885(outs HvxWR:$Vdd32),
33886(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33887"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)",
33888tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> {
33889let Inst{7-5} = 0b011;
33890let Inst{13-13} = 0b0;
33891let Inst{31-21} = 0b00011001011;
33892let hasNewValue = 1;
33893let opNewValue = 0;
33894let isCVI = 1;
33895let DecoderNamespace = "EXT_mmvec";
33896}
33897def V6_vmpabuu_acc : HInst<
33898(outs HvxWR:$Vxx32),
33899(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33900"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)",
33901tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> {
33902let Inst{7-5} = 0b100;
33903let Inst{13-13} = 0b1;
33904let Inst{31-21} = 0b00011001101;
33905let hasNewValue = 1;
33906let opNewValue = 0;
33907let isAccumulator = 1;
33908let isCVI = 1;
33909let DecoderNamespace = "EXT_mmvec";
33910let Constraints = "$Vxx32 = $Vxx32in";
33911}
33912def V6_vmpabuu_acc_alt : HInst<
33913(outs HvxWR:$Vxx32),
33914(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33915"$Vxx32 += vmpabuu($Vuu32,$Rt32)",
33916PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33917let hasNewValue = 1;
33918let opNewValue = 0;
33919let isAccumulator = 1;
33920let isCVI = 1;
33921let isPseudo = 1;
33922let isCodeGenOnly = 1;
33923let DecoderNamespace = "EXT_mmvec";
33924let Constraints = "$Vxx32 = $Vxx32in";
33925}
33926def V6_vmpabuu_alt : HInst<
33927(outs HvxWR:$Vdd32),
33928(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33929"$Vdd32 = vmpabuu($Vuu32,$Rt32)",
33930PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
33931let hasNewValue = 1;
33932let opNewValue = 0;
33933let isCVI = 1;
33934let isPseudo = 1;
33935let isCodeGenOnly = 1;
33936let DecoderNamespace = "EXT_mmvec";
33937}
33938def V6_vmpabuuv : HInst<
33939(outs HvxWR:$Vdd32),
33940(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33941"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)",
33942tc_d8287c14, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
33943let Inst{7-5} = 0b111;
33944let Inst{13-13} = 0b0;
33945let Inst{31-21} = 0b00011100111;
33946let hasNewValue = 1;
33947let opNewValue = 0;
33948let isCVI = 1;
33949let DecoderNamespace = "EXT_mmvec";
33950}
33951def V6_vmpabuuv_alt : HInst<
33952(outs HvxWR:$Vdd32),
33953(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
33954"$Vdd32 = vmpabuu($Vuu32,$Vvv32)",
33955PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33956let hasNewValue = 1;
33957let opNewValue = 0;
33958let isCVI = 1;
33959let isPseudo = 1;
33960let isCodeGenOnly = 1;
33961let DecoderNamespace = "EXT_mmvec";
33962}
33963def V6_vmpahb : HInst<
33964(outs HvxWR:$Vdd32),
33965(ins HvxWR:$Vuu32, IntRegs:$Rt32),
33966"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)",
33967tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
33968let Inst{7-5} = 0b111;
33969let Inst{13-13} = 0b0;
33970let Inst{31-21} = 0b00011001001;
33971let hasNewValue = 1;
33972let opNewValue = 0;
33973let isCVI = 1;
33974let DecoderNamespace = "EXT_mmvec";
33975}
33976def V6_vmpahb_acc : HInst<
33977(outs HvxWR:$Vxx32),
33978(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33979"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)",
33980tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
33981let Inst{7-5} = 0b111;
33982let Inst{13-13} = 0b1;
33983let Inst{31-21} = 0b00011001001;
33984let hasNewValue = 1;
33985let opNewValue = 0;
33986let isAccumulator = 1;
33987let isCVI = 1;
33988let DecoderNamespace = "EXT_mmvec";
33989let Constraints = "$Vxx32 = $Vxx32in";
33990}
33991def V6_vmpahb_acc_alt : HInst<
33992(outs HvxWR:$Vxx32),
33993(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
33994"$Vxx32 += vmpahb($Vuu32,$Rt32)",
33995PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
33996let hasNewValue = 1;
33997let opNewValue = 0;
33998let isAccumulator = 1;
33999let isCVI = 1;
34000let isPseudo = 1;
34001let isCodeGenOnly = 1;
34002let DecoderNamespace = "EXT_mmvec";
34003let Constraints = "$Vxx32 = $Vxx32in";
34004}
34005def V6_vmpahb_alt : HInst<
34006(outs HvxWR:$Vdd32),
34007(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34008"$Vdd32 = vmpahb($Vuu32,$Rt32)",
34009PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34010let hasNewValue = 1;
34011let opNewValue = 0;
34012let isCVI = 1;
34013let isPseudo = 1;
34014let isCodeGenOnly = 1;
34015let DecoderNamespace = "EXT_mmvec";
34016}
34017def V6_vmpahhsat : HInst<
34018(outs HvxVR:$Vx32),
34019(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34020"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat",
34021tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34022let Inst{7-5} = 0b100;
34023let Inst{13-13} = 0b1;
34024let Inst{31-21} = 0b00011001100;
34025let hasNewValue = 1;
34026let opNewValue = 0;
34027let isCVI = 1;
34028let DecoderNamespace = "EXT_mmvec";
34029let Constraints = "$Vx32 = $Vx32in";
34030}
34031def V6_vmpauhb : HInst<
34032(outs HvxWR:$Vdd32),
34033(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34034"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)",
34035tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> {
34036let Inst{7-5} = 0b101;
34037let Inst{13-13} = 0b0;
34038let Inst{31-21} = 0b00011001100;
34039let hasNewValue = 1;
34040let opNewValue = 0;
34041let isCVI = 1;
34042let DecoderNamespace = "EXT_mmvec";
34043}
34044def V6_vmpauhb_acc : HInst<
34045(outs HvxWR:$Vxx32),
34046(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34047"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)",
34048tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> {
34049let Inst{7-5} = 0b010;
34050let Inst{13-13} = 0b1;
34051let Inst{31-21} = 0b00011001100;
34052let hasNewValue = 1;
34053let opNewValue = 0;
34054let isAccumulator = 1;
34055let isCVI = 1;
34056let DecoderNamespace = "EXT_mmvec";
34057let Constraints = "$Vxx32 = $Vxx32in";
34058}
34059def V6_vmpauhb_acc_alt : HInst<
34060(outs HvxWR:$Vxx32),
34061(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
34062"$Vxx32 += vmpauhb($Vuu32,$Rt32)",
34063PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34064let hasNewValue = 1;
34065let opNewValue = 0;
34066let isAccumulator = 1;
34067let isCVI = 1;
34068let isPseudo = 1;
34069let isCodeGenOnly = 1;
34070let DecoderNamespace = "EXT_mmvec";
34071let Constraints = "$Vxx32 = $Vxx32in";
34072}
34073def V6_vmpauhb_alt : HInst<
34074(outs HvxWR:$Vdd32),
34075(ins HvxWR:$Vuu32, IntRegs:$Rt32),
34076"$Vdd32 = vmpauhb($Vuu32,$Rt32)",
34077PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34078let hasNewValue = 1;
34079let opNewValue = 0;
34080let isCVI = 1;
34081let isPseudo = 1;
34082let isCodeGenOnly = 1;
34083let DecoderNamespace = "EXT_mmvec";
34084}
34085def V6_vmpauhuhsat : HInst<
34086(outs HvxVR:$Vx32),
34087(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34088"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
34089tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34090let Inst{7-5} = 0b101;
34091let Inst{13-13} = 0b1;
34092let Inst{31-21} = 0b00011001100;
34093let hasNewValue = 1;
34094let opNewValue = 0;
34095let isCVI = 1;
34096let DecoderNamespace = "EXT_mmvec";
34097let Constraints = "$Vx32 = $Vx32in";
34098}
34099def V6_vmpsuhuhsat : HInst<
34100(outs HvxVR:$Vx32),
34101(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
34102"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat",
34103tc_90bcc1db, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> {
34104let Inst{7-5} = 0b110;
34105let Inst{13-13} = 0b1;
34106let Inst{31-21} = 0b00011001100;
34107let hasNewValue = 1;
34108let opNewValue = 0;
34109let isCVI = 1;
34110let DecoderNamespace = "EXT_mmvec";
34111let Constraints = "$Vx32 = $Vx32in";
34112}
34113def V6_vmpybus : HInst<
34114(outs HvxWR:$Vdd32),
34115(ins HvxVR:$Vu32, IntRegs:$Rt32),
34116"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)",
34117tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34118let Inst{7-5} = 0b101;
34119let Inst{13-13} = 0b0;
34120let Inst{31-21} = 0b00011001001;
34121let hasNewValue = 1;
34122let opNewValue = 0;
34123let isCVI = 1;
34124let DecoderNamespace = "EXT_mmvec";
34125}
34126def V6_vmpybus_acc : HInst<
34127(outs HvxWR:$Vxx32),
34128(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34129"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)",
34130tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34131let Inst{7-5} = 0b101;
34132let Inst{13-13} = 0b1;
34133let Inst{31-21} = 0b00011001001;
34134let hasNewValue = 1;
34135let opNewValue = 0;
34136let isAccumulator = 1;
34137let isCVI = 1;
34138let DecoderNamespace = "EXT_mmvec";
34139let Constraints = "$Vxx32 = $Vxx32in";
34140}
34141def V6_vmpybus_acc_alt : HInst<
34142(outs HvxWR:$Vxx32),
34143(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34144"$Vxx32 += vmpybus($Vu32,$Rt32)",
34145PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34146let hasNewValue = 1;
34147let opNewValue = 0;
34148let isAccumulator = 1;
34149let isCVI = 1;
34150let isPseudo = 1;
34151let isCodeGenOnly = 1;
34152let DecoderNamespace = "EXT_mmvec";
34153let Constraints = "$Vxx32 = $Vxx32in";
34154}
34155def V6_vmpybus_alt : HInst<
34156(outs HvxWR:$Vdd32),
34157(ins HvxVR:$Vu32, IntRegs:$Rt32),
34158"$Vdd32 = vmpybus($Vu32,$Rt32)",
34159PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34160let hasNewValue = 1;
34161let opNewValue = 0;
34162let isCVI = 1;
34163let isPseudo = 1;
34164let isCodeGenOnly = 1;
34165let DecoderNamespace = "EXT_mmvec";
34166}
34167def V6_vmpybusv : HInst<
34168(outs HvxWR:$Vdd32),
34169(ins HvxVR:$Vu32, HvxVR:$Vv32),
34170"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)",
34171tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34172let Inst{7-5} = 0b110;
34173let Inst{13-13} = 0b0;
34174let Inst{31-21} = 0b00011100000;
34175let hasNewValue = 1;
34176let opNewValue = 0;
34177let isCVI = 1;
34178let DecoderNamespace = "EXT_mmvec";
34179}
34180def V6_vmpybusv_acc : HInst<
34181(outs HvxWR:$Vxx32),
34182(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34183"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)",
34184tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34185let Inst{7-5} = 0b110;
34186let Inst{13-13} = 0b1;
34187let Inst{31-21} = 0b00011100000;
34188let hasNewValue = 1;
34189let opNewValue = 0;
34190let isAccumulator = 1;
34191let isCVI = 1;
34192let DecoderNamespace = "EXT_mmvec";
34193let Constraints = "$Vxx32 = $Vxx32in";
34194}
34195def V6_vmpybusv_acc_alt : HInst<
34196(outs HvxWR:$Vxx32),
34197(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34198"$Vxx32 += vmpybus($Vu32,$Vv32)",
34199PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34200let hasNewValue = 1;
34201let opNewValue = 0;
34202let isAccumulator = 1;
34203let isCVI = 1;
34204let isPseudo = 1;
34205let isCodeGenOnly = 1;
34206let DecoderNamespace = "EXT_mmvec";
34207let Constraints = "$Vxx32 = $Vxx32in";
34208}
34209def V6_vmpybusv_alt : HInst<
34210(outs HvxWR:$Vdd32),
34211(ins HvxVR:$Vu32, HvxVR:$Vv32),
34212"$Vdd32 = vmpybus($Vu32,$Vv32)",
34213PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34214let hasNewValue = 1;
34215let opNewValue = 0;
34216let isCVI = 1;
34217let isPseudo = 1;
34218let isCodeGenOnly = 1;
34219let DecoderNamespace = "EXT_mmvec";
34220}
34221def V6_vmpybv : HInst<
34222(outs HvxWR:$Vdd32),
34223(ins HvxVR:$Vu32, HvxVR:$Vv32),
34224"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)",
34225tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34226let Inst{7-5} = 0b100;
34227let Inst{13-13} = 0b0;
34228let Inst{31-21} = 0b00011100000;
34229let hasNewValue = 1;
34230let opNewValue = 0;
34231let isCVI = 1;
34232let DecoderNamespace = "EXT_mmvec";
34233}
34234def V6_vmpybv_acc : HInst<
34235(outs HvxWR:$Vxx32),
34236(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34237"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)",
34238tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34239let Inst{7-5} = 0b100;
34240let Inst{13-13} = 0b1;
34241let Inst{31-21} = 0b00011100000;
34242let hasNewValue = 1;
34243let opNewValue = 0;
34244let isAccumulator = 1;
34245let isCVI = 1;
34246let DecoderNamespace = "EXT_mmvec";
34247let Constraints = "$Vxx32 = $Vxx32in";
34248}
34249def V6_vmpybv_acc_alt : HInst<
34250(outs HvxWR:$Vxx32),
34251(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34252"$Vxx32 += vmpyb($Vu32,$Vv32)",
34253PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34254let hasNewValue = 1;
34255let opNewValue = 0;
34256let isAccumulator = 1;
34257let isCVI = 1;
34258let isPseudo = 1;
34259let isCodeGenOnly = 1;
34260let DecoderNamespace = "EXT_mmvec";
34261let Constraints = "$Vxx32 = $Vxx32in";
34262}
34263def V6_vmpybv_alt : HInst<
34264(outs HvxWR:$Vdd32),
34265(ins HvxVR:$Vu32, HvxVR:$Vv32),
34266"$Vdd32 = vmpyb($Vu32,$Vv32)",
34267PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34268let hasNewValue = 1;
34269let opNewValue = 0;
34270let isCVI = 1;
34271let isPseudo = 1;
34272let isCodeGenOnly = 1;
34273let DecoderNamespace = "EXT_mmvec";
34274}
34275def V6_vmpyewuh : HInst<
34276(outs HvxVR:$Vd32),
34277(ins HvxVR:$Vu32, HvxVR:$Vv32),
34278"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)",
34279tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34280let Inst{7-5} = 0b101;
34281let Inst{13-13} = 0b0;
34282let Inst{31-21} = 0b00011111111;
34283let hasNewValue = 1;
34284let opNewValue = 0;
34285let isCVI = 1;
34286let DecoderNamespace = "EXT_mmvec";
34287}
34288def V6_vmpyewuh_64 : HInst<
34289(outs HvxWR:$Vdd32),
34290(ins HvxVR:$Vu32, HvxVR:$Vv32),
34291"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)",
34292tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> {
34293let Inst{7-5} = 0b110;
34294let Inst{13-13} = 0b0;
34295let Inst{31-21} = 0b00011110101;
34296let hasNewValue = 1;
34297let opNewValue = 0;
34298let isCVI = 1;
34299let DecoderNamespace = "EXT_mmvec";
34300}
34301def V6_vmpyewuh_alt : HInst<
34302(outs HvxVR:$Vd32),
34303(ins HvxVR:$Vu32, HvxVR:$Vv32),
34304"$Vd32 = vmpyewuh($Vu32,$Vv32)",
34305PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34306let hasNewValue = 1;
34307let opNewValue = 0;
34308let isCVI = 1;
34309let isPseudo = 1;
34310let isCodeGenOnly = 1;
34311let DecoderNamespace = "EXT_mmvec";
34312}
34313def V6_vmpyh : HInst<
34314(outs HvxWR:$Vdd32),
34315(ins HvxVR:$Vu32, IntRegs:$Rt32),
34316"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)",
34317tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
34318let Inst{7-5} = 0b000;
34319let Inst{13-13} = 0b0;
34320let Inst{31-21} = 0b00011001010;
34321let hasNewValue = 1;
34322let opNewValue = 0;
34323let isCVI = 1;
34324let DecoderNamespace = "EXT_mmvec";
34325}
34326def V6_vmpyh_acc : HInst<
34327(outs HvxWR:$Vxx32),
34328(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34329"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)",
34330tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> {
34331let Inst{7-5} = 0b110;
34332let Inst{13-13} = 0b1;
34333let Inst{31-21} = 0b00011001101;
34334let hasNewValue = 1;
34335let opNewValue = 0;
34336let isAccumulator = 1;
34337let isCVI = 1;
34338let DecoderNamespace = "EXT_mmvec";
34339let Constraints = "$Vxx32 = $Vxx32in";
34340}
34341def V6_vmpyh_acc_alt : HInst<
34342(outs HvxWR:$Vxx32),
34343(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34344"$Vxx32 += vmpyh($Vu32,$Rt32)",
34345PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
34346let hasNewValue = 1;
34347let opNewValue = 0;
34348let isAccumulator = 1;
34349let isCVI = 1;
34350let isPseudo = 1;
34351let isCodeGenOnly = 1;
34352let DecoderNamespace = "EXT_mmvec";
34353let Constraints = "$Vxx32 = $Vxx32in";
34354}
34355def V6_vmpyh_alt : HInst<
34356(outs HvxWR:$Vdd32),
34357(ins HvxVR:$Vu32, IntRegs:$Rt32),
34358"$Vdd32 = vmpyh($Vu32,$Rt32)",
34359PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34360let hasNewValue = 1;
34361let opNewValue = 0;
34362let isCVI = 1;
34363let isPseudo = 1;
34364let isCodeGenOnly = 1;
34365let DecoderNamespace = "EXT_mmvec";
34366}
34367def V6_vmpyhsat_acc : HInst<
34368(outs HvxWR:$Vxx32),
34369(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34370"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat",
34371tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
34372let Inst{7-5} = 0b000;
34373let Inst{13-13} = 0b1;
34374let Inst{31-21} = 0b00011001010;
34375let hasNewValue = 1;
34376let opNewValue = 0;
34377let isAccumulator = 1;
34378let isCVI = 1;
34379let DecoderNamespace = "EXT_mmvec";
34380let Constraints = "$Vxx32 = $Vxx32in";
34381}
34382def V6_vmpyhsat_acc_alt : HInst<
34383(outs HvxWR:$Vxx32),
34384(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34385"$Vxx32 += vmpyh($Vu32,$Rt32):sat",
34386PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34387let hasNewValue = 1;
34388let opNewValue = 0;
34389let isAccumulator = 1;
34390let isCVI = 1;
34391let isPseudo = 1;
34392let isCodeGenOnly = 1;
34393let DecoderNamespace = "EXT_mmvec";
34394let Constraints = "$Vxx32 = $Vxx32in";
34395}
34396def V6_vmpyhsrs : HInst<
34397(outs HvxVR:$Vd32),
34398(ins HvxVR:$Vu32, IntRegs:$Rt32),
34399"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat",
34400tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34401let Inst{7-5} = 0b010;
34402let Inst{13-13} = 0b0;
34403let Inst{31-21} = 0b00011001010;
34404let hasNewValue = 1;
34405let opNewValue = 0;
34406let isCVI = 1;
34407let DecoderNamespace = "EXT_mmvec";
34408}
34409def V6_vmpyhsrs_alt : HInst<
34410(outs HvxVR:$Vd32),
34411(ins HvxVR:$Vu32, IntRegs:$Rt32),
34412"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat",
34413PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34414let hasNewValue = 1;
34415let opNewValue = 0;
34416let isCVI = 1;
34417let isPseudo = 1;
34418let isCodeGenOnly = 1;
34419let DecoderNamespace = "EXT_mmvec";
34420}
34421def V6_vmpyhss : HInst<
34422(outs HvxVR:$Vd32),
34423(ins HvxVR:$Vu32, IntRegs:$Rt32),
34424"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat",
34425tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34426let Inst{7-5} = 0b001;
34427let Inst{13-13} = 0b0;
34428let Inst{31-21} = 0b00011001010;
34429let hasNewValue = 1;
34430let opNewValue = 0;
34431let isCVI = 1;
34432let DecoderNamespace = "EXT_mmvec";
34433}
34434def V6_vmpyhss_alt : HInst<
34435(outs HvxVR:$Vd32),
34436(ins HvxVR:$Vu32, IntRegs:$Rt32),
34437"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat",
34438PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34439let hasNewValue = 1;
34440let opNewValue = 0;
34441let isCVI = 1;
34442let isPseudo = 1;
34443let isCodeGenOnly = 1;
34444let DecoderNamespace = "EXT_mmvec";
34445}
34446def V6_vmpyhus : HInst<
34447(outs HvxWR:$Vdd32),
34448(ins HvxVR:$Vu32, HvxVR:$Vv32),
34449"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)",
34450tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34451let Inst{7-5} = 0b010;
34452let Inst{13-13} = 0b0;
34453let Inst{31-21} = 0b00011100001;
34454let hasNewValue = 1;
34455let opNewValue = 0;
34456let isCVI = 1;
34457let DecoderNamespace = "EXT_mmvec";
34458}
34459def V6_vmpyhus_acc : HInst<
34460(outs HvxWR:$Vxx32),
34461(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34462"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)",
34463tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34464let Inst{7-5} = 0b001;
34465let Inst{13-13} = 0b1;
34466let Inst{31-21} = 0b00011100001;
34467let hasNewValue = 1;
34468let opNewValue = 0;
34469let isAccumulator = 1;
34470let isCVI = 1;
34471let DecoderNamespace = "EXT_mmvec";
34472let Constraints = "$Vxx32 = $Vxx32in";
34473}
34474def V6_vmpyhus_acc_alt : HInst<
34475(outs HvxWR:$Vxx32),
34476(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34477"$Vxx32 += vmpyhus($Vu32,$Vv32)",
34478PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34479let hasNewValue = 1;
34480let opNewValue = 0;
34481let isAccumulator = 1;
34482let isCVI = 1;
34483let isPseudo = 1;
34484let isCodeGenOnly = 1;
34485let DecoderNamespace = "EXT_mmvec";
34486let Constraints = "$Vxx32 = $Vxx32in";
34487}
34488def V6_vmpyhus_alt : HInst<
34489(outs HvxWR:$Vdd32),
34490(ins HvxVR:$Vu32, HvxVR:$Vv32),
34491"$Vdd32 = vmpyhus($Vu32,$Vv32)",
34492PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34493let hasNewValue = 1;
34494let opNewValue = 0;
34495let isCVI = 1;
34496let isPseudo = 1;
34497let isCodeGenOnly = 1;
34498let DecoderNamespace = "EXT_mmvec";
34499}
34500def V6_vmpyhv : HInst<
34501(outs HvxWR:$Vdd32),
34502(ins HvxVR:$Vu32, HvxVR:$Vv32),
34503"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)",
34504tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
34505let Inst{7-5} = 0b111;
34506let Inst{13-13} = 0b0;
34507let Inst{31-21} = 0b00011100000;
34508let hasNewValue = 1;
34509let opNewValue = 0;
34510let isCVI = 1;
34511let DecoderNamespace = "EXT_mmvec";
34512}
34513def V6_vmpyhv_acc : HInst<
34514(outs HvxWR:$Vxx32),
34515(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34516"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)",
34517tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
34518let Inst{7-5} = 0b111;
34519let Inst{13-13} = 0b1;
34520let Inst{31-21} = 0b00011100000;
34521let hasNewValue = 1;
34522let opNewValue = 0;
34523let isAccumulator = 1;
34524let isCVI = 1;
34525let DecoderNamespace = "EXT_mmvec";
34526let Constraints = "$Vxx32 = $Vxx32in";
34527}
34528def V6_vmpyhv_acc_alt : HInst<
34529(outs HvxWR:$Vxx32),
34530(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34531"$Vxx32 += vmpyh($Vu32,$Vv32)",
34532PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34533let hasNewValue = 1;
34534let opNewValue = 0;
34535let isAccumulator = 1;
34536let isCVI = 1;
34537let isPseudo = 1;
34538let isCodeGenOnly = 1;
34539let DecoderNamespace = "EXT_mmvec";
34540let Constraints = "$Vxx32 = $Vxx32in";
34541}
34542def V6_vmpyhv_alt : HInst<
34543(outs HvxWR:$Vdd32),
34544(ins HvxVR:$Vu32, HvxVR:$Vv32),
34545"$Vdd32 = vmpyh($Vu32,$Vv32)",
34546PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34547let hasNewValue = 1;
34548let opNewValue = 0;
34549let isCVI = 1;
34550let isPseudo = 1;
34551let isCodeGenOnly = 1;
34552let DecoderNamespace = "EXT_mmvec";
34553}
34554def V6_vmpyhvsrs : HInst<
34555(outs HvxVR:$Vd32),
34556(ins HvxVR:$Vu32, HvxVR:$Vv32),
34557"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat",
34558tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34559let Inst{7-5} = 0b001;
34560let Inst{13-13} = 0b0;
34561let Inst{31-21} = 0b00011100001;
34562let hasNewValue = 1;
34563let opNewValue = 0;
34564let isCVI = 1;
34565let DecoderNamespace = "EXT_mmvec";
34566}
34567def V6_vmpyhvsrs_alt : HInst<
34568(outs HvxVR:$Vd32),
34569(ins HvxVR:$Vu32, HvxVR:$Vv32),
34570"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat",
34571PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34572let hasNewValue = 1;
34573let opNewValue = 0;
34574let isCVI = 1;
34575let isPseudo = 1;
34576let isCodeGenOnly = 1;
34577let DecoderNamespace = "EXT_mmvec";
34578}
34579def V6_vmpyieoh : HInst<
34580(outs HvxVR:$Vd32),
34581(ins HvxVR:$Vu32, HvxVR:$Vv32),
34582"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)",
34583tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
34584let Inst{7-5} = 0b000;
34585let Inst{13-13} = 0b0;
34586let Inst{31-21} = 0b00011111011;
34587let hasNewValue = 1;
34588let opNewValue = 0;
34589let isCVI = 1;
34590let DecoderNamespace = "EXT_mmvec";
34591}
34592def V6_vmpyiewh_acc : HInst<
34593(outs HvxVR:$Vx32),
34594(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34595"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)",
34596tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34597let Inst{7-5} = 0b000;
34598let Inst{13-13} = 0b1;
34599let Inst{31-21} = 0b00011100010;
34600let hasNewValue = 1;
34601let opNewValue = 0;
34602let isAccumulator = 1;
34603let isCVI = 1;
34604let DecoderNamespace = "EXT_mmvec";
34605let Constraints = "$Vx32 = $Vx32in";
34606}
34607def V6_vmpyiewh_acc_alt : HInst<
34608(outs HvxVR:$Vx32),
34609(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34610"$Vx32 += vmpyiewh($Vu32,$Vv32)",
34611PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34612let hasNewValue = 1;
34613let opNewValue = 0;
34614let isAccumulator = 1;
34615let isCVI = 1;
34616let isPseudo = 1;
34617let isCodeGenOnly = 1;
34618let DecoderNamespace = "EXT_mmvec";
34619let Constraints = "$Vx32 = $Vx32in";
34620}
34621def V6_vmpyiewuh : HInst<
34622(outs HvxVR:$Vd32),
34623(ins HvxVR:$Vu32, HvxVR:$Vv32),
34624"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)",
34625tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34626let Inst{7-5} = 0b000;
34627let Inst{13-13} = 0b0;
34628let Inst{31-21} = 0b00011111110;
34629let hasNewValue = 1;
34630let opNewValue = 0;
34631let isCVI = 1;
34632let DecoderNamespace = "EXT_mmvec";
34633}
34634def V6_vmpyiewuh_acc : HInst<
34635(outs HvxVR:$Vx32),
34636(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34637"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)",
34638tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34639let Inst{7-5} = 0b101;
34640let Inst{13-13} = 0b1;
34641let Inst{31-21} = 0b00011100001;
34642let hasNewValue = 1;
34643let opNewValue = 0;
34644let isAccumulator = 1;
34645let isCVI = 1;
34646let DecoderNamespace = "EXT_mmvec";
34647let Constraints = "$Vx32 = $Vx32in";
34648}
34649def V6_vmpyiewuh_acc_alt : HInst<
34650(outs HvxVR:$Vx32),
34651(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34652"$Vx32 += vmpyiewuh($Vu32,$Vv32)",
34653PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34654let hasNewValue = 1;
34655let opNewValue = 0;
34656let isAccumulator = 1;
34657let isCVI = 1;
34658let isPseudo = 1;
34659let isCodeGenOnly = 1;
34660let DecoderNamespace = "EXT_mmvec";
34661let Constraints = "$Vx32 = $Vx32in";
34662}
34663def V6_vmpyiewuh_alt : HInst<
34664(outs HvxVR:$Vd32),
34665(ins HvxVR:$Vu32, HvxVR:$Vv32),
34666"$Vd32 = vmpyiewuh($Vu32,$Vv32)",
34667PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34668let hasNewValue = 1;
34669let opNewValue = 0;
34670let isCVI = 1;
34671let isPseudo = 1;
34672let isCodeGenOnly = 1;
34673let DecoderNamespace = "EXT_mmvec";
34674}
34675def V6_vmpyih : HInst<
34676(outs HvxVR:$Vd32),
34677(ins HvxVR:$Vu32, HvxVR:$Vv32),
34678"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)",
34679tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34680let Inst{7-5} = 0b100;
34681let Inst{13-13} = 0b0;
34682let Inst{31-21} = 0b00011100001;
34683let hasNewValue = 1;
34684let opNewValue = 0;
34685let isCVI = 1;
34686let DecoderNamespace = "EXT_mmvec";
34687}
34688def V6_vmpyih_acc : HInst<
34689(outs HvxVR:$Vx32),
34690(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34691"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)",
34692tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
34693let Inst{7-5} = 0b100;
34694let Inst{13-13} = 0b1;
34695let Inst{31-21} = 0b00011100001;
34696let hasNewValue = 1;
34697let opNewValue = 0;
34698let isAccumulator = 1;
34699let isCVI = 1;
34700let DecoderNamespace = "EXT_mmvec";
34701let Constraints = "$Vx32 = $Vx32in";
34702}
34703def V6_vmpyih_acc_alt : HInst<
34704(outs HvxVR:$Vx32),
34705(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34706"$Vx32 += vmpyih($Vu32,$Vv32)",
34707PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34708let hasNewValue = 1;
34709let opNewValue = 0;
34710let isAccumulator = 1;
34711let isCVI = 1;
34712let isPseudo = 1;
34713let isCodeGenOnly = 1;
34714let DecoderNamespace = "EXT_mmvec";
34715let Constraints = "$Vx32 = $Vx32in";
34716}
34717def V6_vmpyih_alt : HInst<
34718(outs HvxVR:$Vd32),
34719(ins HvxVR:$Vu32, HvxVR:$Vv32),
34720"$Vd32 = vmpyih($Vu32,$Vv32)",
34721PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34722let hasNewValue = 1;
34723let opNewValue = 0;
34724let isCVI = 1;
34725let isPseudo = 1;
34726let isCodeGenOnly = 1;
34727let DecoderNamespace = "EXT_mmvec";
34728}
34729def V6_vmpyihb : HInst<
34730(outs HvxVR:$Vd32),
34731(ins HvxVR:$Vu32, IntRegs:$Rt32),
34732"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)",
34733tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34734let Inst{7-5} = 0b000;
34735let Inst{13-13} = 0b0;
34736let Inst{31-21} = 0b00011001011;
34737let hasNewValue = 1;
34738let opNewValue = 0;
34739let isCVI = 1;
34740let DecoderNamespace = "EXT_mmvec";
34741}
34742def V6_vmpyihb_acc : HInst<
34743(outs HvxVR:$Vx32),
34744(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34745"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)",
34746tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34747let Inst{7-5} = 0b001;
34748let Inst{13-13} = 0b1;
34749let Inst{31-21} = 0b00011001011;
34750let hasNewValue = 1;
34751let opNewValue = 0;
34752let isAccumulator = 1;
34753let isCVI = 1;
34754let DecoderNamespace = "EXT_mmvec";
34755let Constraints = "$Vx32 = $Vx32in";
34756}
34757def V6_vmpyihb_acc_alt : HInst<
34758(outs HvxVR:$Vx32),
34759(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34760"$Vx32 += vmpyihb($Vu32,$Rt32)",
34761PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34762let hasNewValue = 1;
34763let opNewValue = 0;
34764let isAccumulator = 1;
34765let isCVI = 1;
34766let isPseudo = 1;
34767let isCodeGenOnly = 1;
34768let DecoderNamespace = "EXT_mmvec";
34769let Constraints = "$Vx32 = $Vx32in";
34770}
34771def V6_vmpyihb_alt : HInst<
34772(outs HvxVR:$Vd32),
34773(ins HvxVR:$Vu32, IntRegs:$Rt32),
34774"$Vd32 = vmpyihb($Vu32,$Rt32)",
34775PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34776let hasNewValue = 1;
34777let opNewValue = 0;
34778let isCVI = 1;
34779let isPseudo = 1;
34780let isCodeGenOnly = 1;
34781let DecoderNamespace = "EXT_mmvec";
34782}
34783def V6_vmpyiowh : HInst<
34784(outs HvxVR:$Vd32),
34785(ins HvxVR:$Vu32, HvxVR:$Vv32),
34786"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)",
34787tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34788let Inst{7-5} = 0b001;
34789let Inst{13-13} = 0b0;
34790let Inst{31-21} = 0b00011111110;
34791let hasNewValue = 1;
34792let opNewValue = 0;
34793let isCVI = 1;
34794let DecoderNamespace = "EXT_mmvec";
34795}
34796def V6_vmpyiowh_alt : HInst<
34797(outs HvxVR:$Vd32),
34798(ins HvxVR:$Vu32, HvxVR:$Vv32),
34799"$Vd32 = vmpyiowh($Vu32,$Vv32)",
34800PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34801let hasNewValue = 1;
34802let opNewValue = 0;
34803let isCVI = 1;
34804let isPseudo = 1;
34805let isCodeGenOnly = 1;
34806let DecoderNamespace = "EXT_mmvec";
34807}
34808def V6_vmpyiwb : HInst<
34809(outs HvxVR:$Vd32),
34810(ins HvxVR:$Vu32, IntRegs:$Rt32),
34811"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)",
34812tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
34813let Inst{7-5} = 0b000;
34814let Inst{13-13} = 0b0;
34815let Inst{31-21} = 0b00011001101;
34816let hasNewValue = 1;
34817let opNewValue = 0;
34818let isCVI = 1;
34819let DecoderNamespace = "EXT_mmvec";
34820}
34821def V6_vmpyiwb_acc : HInst<
34822(outs HvxVR:$Vx32),
34823(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34824"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)",
34825tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
34826let Inst{7-5} = 0b010;
34827let Inst{13-13} = 0b1;
34828let Inst{31-21} = 0b00011001010;
34829let hasNewValue = 1;
34830let opNewValue = 0;
34831let isAccumulator = 1;
34832let isCVI = 1;
34833let DecoderNamespace = "EXT_mmvec";
34834let Constraints = "$Vx32 = $Vx32in";
34835}
34836def V6_vmpyiwb_acc_alt : HInst<
34837(outs HvxVR:$Vx32),
34838(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34839"$Vx32 += vmpyiwb($Vu32,$Rt32)",
34840PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34841let hasNewValue = 1;
34842let opNewValue = 0;
34843let isAccumulator = 1;
34844let isCVI = 1;
34845let isPseudo = 1;
34846let isCodeGenOnly = 1;
34847let DecoderNamespace = "EXT_mmvec";
34848let Constraints = "$Vx32 = $Vx32in";
34849}
34850def V6_vmpyiwb_alt : HInst<
34851(outs HvxVR:$Vd32),
34852(ins HvxVR:$Vu32, IntRegs:$Rt32),
34853"$Vd32 = vmpyiwb($Vu32,$Rt32)",
34854PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34855let hasNewValue = 1;
34856let opNewValue = 0;
34857let isCVI = 1;
34858let isPseudo = 1;
34859let isCodeGenOnly = 1;
34860let DecoderNamespace = "EXT_mmvec";
34861}
34862def V6_vmpyiwh : HInst<
34863(outs HvxVR:$Vd32),
34864(ins HvxVR:$Vu32, IntRegs:$Rt32),
34865"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)",
34866tc_0b04c6c7, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> {
34867let Inst{7-5} = 0b111;
34868let Inst{13-13} = 0b0;
34869let Inst{31-21} = 0b00011001100;
34870let hasNewValue = 1;
34871let opNewValue = 0;
34872let isCVI = 1;
34873let DecoderNamespace = "EXT_mmvec";
34874}
34875def V6_vmpyiwh_acc : HInst<
34876(outs HvxVR:$Vx32),
34877(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34878"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)",
34879tc_660769f1, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> {
34880let Inst{7-5} = 0b011;
34881let Inst{13-13} = 0b1;
34882let Inst{31-21} = 0b00011001010;
34883let hasNewValue = 1;
34884let opNewValue = 0;
34885let isAccumulator = 1;
34886let isCVI = 1;
34887let DecoderNamespace = "EXT_mmvec";
34888let Constraints = "$Vx32 = $Vx32in";
34889}
34890def V6_vmpyiwh_acc_alt : HInst<
34891(outs HvxVR:$Vx32),
34892(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34893"$Vx32 += vmpyiwh($Vu32,$Rt32)",
34894PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34895let hasNewValue = 1;
34896let opNewValue = 0;
34897let isAccumulator = 1;
34898let isCVI = 1;
34899let isPseudo = 1;
34900let isCodeGenOnly = 1;
34901let DecoderNamespace = "EXT_mmvec";
34902let Constraints = "$Vx32 = $Vx32in";
34903}
34904def V6_vmpyiwh_alt : HInst<
34905(outs HvxVR:$Vd32),
34906(ins HvxVR:$Vu32, IntRegs:$Rt32),
34907"$Vd32 = vmpyiwh($Vu32,$Rt32)",
34908PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
34909let hasNewValue = 1;
34910let opNewValue = 0;
34911let isCVI = 1;
34912let isPseudo = 1;
34913let isCodeGenOnly = 1;
34914let DecoderNamespace = "EXT_mmvec";
34915}
34916def V6_vmpyiwub : HInst<
34917(outs HvxVR:$Vd32),
34918(ins HvxVR:$Vu32, IntRegs:$Rt32),
34919"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)",
34920tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> {
34921let Inst{7-5} = 0b110;
34922let Inst{13-13} = 0b0;
34923let Inst{31-21} = 0b00011001100;
34924let hasNewValue = 1;
34925let opNewValue = 0;
34926let isCVI = 1;
34927let DecoderNamespace = "EXT_mmvec";
34928}
34929def V6_vmpyiwub_acc : HInst<
34930(outs HvxVR:$Vx32),
34931(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34932"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)",
34933tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> {
34934let Inst{7-5} = 0b001;
34935let Inst{13-13} = 0b1;
34936let Inst{31-21} = 0b00011001100;
34937let hasNewValue = 1;
34938let opNewValue = 0;
34939let isAccumulator = 1;
34940let isCVI = 1;
34941let DecoderNamespace = "EXT_mmvec";
34942let Constraints = "$Vx32 = $Vx32in";
34943}
34944def V6_vmpyiwub_acc_alt : HInst<
34945(outs HvxVR:$Vx32),
34946(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
34947"$Vx32 += vmpyiwub($Vu32,$Rt32)",
34948PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34949let hasNewValue = 1;
34950let opNewValue = 0;
34951let isAccumulator = 1;
34952let isCVI = 1;
34953let isPseudo = 1;
34954let isCodeGenOnly = 1;
34955let DecoderNamespace = "EXT_mmvec";
34956let Constraints = "$Vx32 = $Vx32in";
34957}
34958def V6_vmpyiwub_alt : HInst<
34959(outs HvxVR:$Vd32),
34960(ins HvxVR:$Vu32, IntRegs:$Rt32),
34961"$Vd32 = vmpyiwub($Vu32,$Rt32)",
34962PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
34963let hasNewValue = 1;
34964let opNewValue = 0;
34965let isCVI = 1;
34966let isPseudo = 1;
34967let isCodeGenOnly = 1;
34968let DecoderNamespace = "EXT_mmvec";
34969}
34970def V6_vmpyowh : HInst<
34971(outs HvxVR:$Vd32),
34972(ins HvxVR:$Vu32, HvxVR:$Vv32),
34973"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat",
34974tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
34975let Inst{7-5} = 0b111;
34976let Inst{13-13} = 0b0;
34977let Inst{31-21} = 0b00011111111;
34978let hasNewValue = 1;
34979let opNewValue = 0;
34980let isCVI = 1;
34981let DecoderNamespace = "EXT_mmvec";
34982}
34983def V6_vmpyowh_64_acc : HInst<
34984(outs HvxWR:$Vxx32),
34985(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
34986"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)",
34987tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> {
34988let Inst{7-5} = 0b011;
34989let Inst{13-13} = 0b1;
34990let Inst{31-21} = 0b00011100001;
34991let hasNewValue = 1;
34992let opNewValue = 0;
34993let isAccumulator = 1;
34994let isCVI = 1;
34995let DecoderNamespace = "EXT_mmvec";
34996let Constraints = "$Vxx32 = $Vxx32in";
34997}
34998def V6_vmpyowh_alt : HInst<
34999(outs HvxVR:$Vd32),
35000(ins HvxVR:$Vu32, HvxVR:$Vv32),
35001"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat",
35002PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35003let hasNewValue = 1;
35004let opNewValue = 0;
35005let isCVI = 1;
35006let isPseudo = 1;
35007let isCodeGenOnly = 1;
35008let DecoderNamespace = "EXT_mmvec";
35009}
35010def V6_vmpyowh_rnd : HInst<
35011(outs HvxVR:$Vd32),
35012(ins HvxVR:$Vu32, HvxVR:$Vv32),
35013"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat",
35014tc_d8287c14, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> {
35015let Inst{7-5} = 0b000;
35016let Inst{13-13} = 0b0;
35017let Inst{31-21} = 0b00011111010;
35018let hasNewValue = 1;
35019let opNewValue = 0;
35020let isCVI = 1;
35021let DecoderNamespace = "EXT_mmvec";
35022}
35023def V6_vmpyowh_rnd_alt : HInst<
35024(outs HvxVR:$Vd32),
35025(ins HvxVR:$Vu32, HvxVR:$Vv32),
35026"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat",
35027PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35028let hasNewValue = 1;
35029let opNewValue = 0;
35030let isCVI = 1;
35031let isPseudo = 1;
35032let isCodeGenOnly = 1;
35033let DecoderNamespace = "EXT_mmvec";
35034}
35035def V6_vmpyowh_rnd_sacc : HInst<
35036(outs HvxVR:$Vx32),
35037(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35038"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift",
35039tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35040let Inst{7-5} = 0b111;
35041let Inst{13-13} = 0b1;
35042let Inst{31-21} = 0b00011100001;
35043let hasNewValue = 1;
35044let opNewValue = 0;
35045let isAccumulator = 1;
35046let isCVI = 1;
35047let DecoderNamespace = "EXT_mmvec";
35048let Constraints = "$Vx32 = $Vx32in";
35049}
35050def V6_vmpyowh_rnd_sacc_alt : HInst<
35051(outs HvxVR:$Vx32),
35052(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35053"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift",
35054PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35055let hasNewValue = 1;
35056let opNewValue = 0;
35057let isAccumulator = 1;
35058let isCVI = 1;
35059let isPseudo = 1;
35060let DecoderNamespace = "EXT_mmvec";
35061let Constraints = "$Vx32 = $Vx32in";
35062}
35063def V6_vmpyowh_sacc : HInst<
35064(outs HvxVR:$Vx32),
35065(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35066"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift",
35067tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
35068let Inst{7-5} = 0b110;
35069let Inst{13-13} = 0b1;
35070let Inst{31-21} = 0b00011100001;
35071let hasNewValue = 1;
35072let opNewValue = 0;
35073let isAccumulator = 1;
35074let isCVI = 1;
35075let DecoderNamespace = "EXT_mmvec";
35076let Constraints = "$Vx32 = $Vx32in";
35077}
35078def V6_vmpyowh_sacc_alt : HInst<
35079(outs HvxVR:$Vx32),
35080(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35081"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift",
35082PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35083let hasNewValue = 1;
35084let opNewValue = 0;
35085let isAccumulator = 1;
35086let isCVI = 1;
35087let isPseudo = 1;
35088let DecoderNamespace = "EXT_mmvec";
35089let Constraints = "$Vx32 = $Vx32in";
35090}
35091def V6_vmpyub : HInst<
35092(outs HvxWR:$Vdd32),
35093(ins HvxVR:$Vu32, IntRegs:$Rt32),
35094"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)",
35095tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35096let Inst{7-5} = 0b000;
35097let Inst{13-13} = 0b0;
35098let Inst{31-21} = 0b00011001110;
35099let hasNewValue = 1;
35100let opNewValue = 0;
35101let isCVI = 1;
35102let DecoderNamespace = "EXT_mmvec";
35103}
35104def V6_vmpyub_acc : HInst<
35105(outs HvxWR:$Vxx32),
35106(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35107"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)",
35108tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35109let Inst{7-5} = 0b000;
35110let Inst{13-13} = 0b1;
35111let Inst{31-21} = 0b00011001100;
35112let hasNewValue = 1;
35113let opNewValue = 0;
35114let isAccumulator = 1;
35115let isCVI = 1;
35116let DecoderNamespace = "EXT_mmvec";
35117let Constraints = "$Vxx32 = $Vxx32in";
35118}
35119def V6_vmpyub_acc_alt : HInst<
35120(outs HvxWR:$Vxx32),
35121(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35122"$Vxx32 += vmpyub($Vu32,$Rt32)",
35123PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35124let hasNewValue = 1;
35125let opNewValue = 0;
35126let isAccumulator = 1;
35127let isCVI = 1;
35128let isPseudo = 1;
35129let isCodeGenOnly = 1;
35130let DecoderNamespace = "EXT_mmvec";
35131let Constraints = "$Vxx32 = $Vxx32in";
35132}
35133def V6_vmpyub_alt : HInst<
35134(outs HvxWR:$Vdd32),
35135(ins HvxVR:$Vu32, IntRegs:$Rt32),
35136"$Vdd32 = vmpyub($Vu32,$Rt32)",
35137PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35138let hasNewValue = 1;
35139let opNewValue = 0;
35140let isCVI = 1;
35141let isPseudo = 1;
35142let isCodeGenOnly = 1;
35143let DecoderNamespace = "EXT_mmvec";
35144}
35145def V6_vmpyubv : HInst<
35146(outs HvxWR:$Vdd32),
35147(ins HvxVR:$Vu32, HvxVR:$Vv32),
35148"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)",
35149tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35150let Inst{7-5} = 0b101;
35151let Inst{13-13} = 0b0;
35152let Inst{31-21} = 0b00011100000;
35153let hasNewValue = 1;
35154let opNewValue = 0;
35155let isCVI = 1;
35156let DecoderNamespace = "EXT_mmvec";
35157}
35158def V6_vmpyubv_acc : HInst<
35159(outs HvxWR:$Vxx32),
35160(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35161"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)",
35162tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35163let Inst{7-5} = 0b101;
35164let Inst{13-13} = 0b1;
35165let Inst{31-21} = 0b00011100000;
35166let hasNewValue = 1;
35167let opNewValue = 0;
35168let isAccumulator = 1;
35169let isCVI = 1;
35170let DecoderNamespace = "EXT_mmvec";
35171let Constraints = "$Vxx32 = $Vxx32in";
35172}
35173def V6_vmpyubv_acc_alt : HInst<
35174(outs HvxWR:$Vxx32),
35175(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35176"$Vxx32 += vmpyub($Vu32,$Vv32)",
35177PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35178let hasNewValue = 1;
35179let opNewValue = 0;
35180let isAccumulator = 1;
35181let isCVI = 1;
35182let isPseudo = 1;
35183let isCodeGenOnly = 1;
35184let DecoderNamespace = "EXT_mmvec";
35185let Constraints = "$Vxx32 = $Vxx32in";
35186}
35187def V6_vmpyubv_alt : HInst<
35188(outs HvxWR:$Vdd32),
35189(ins HvxVR:$Vu32, HvxVR:$Vv32),
35190"$Vdd32 = vmpyub($Vu32,$Vv32)",
35191PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35192let hasNewValue = 1;
35193let opNewValue = 0;
35194let isCVI = 1;
35195let isPseudo = 1;
35196let isCodeGenOnly = 1;
35197let DecoderNamespace = "EXT_mmvec";
35198}
35199def V6_vmpyuh : HInst<
35200(outs HvxWR:$Vdd32),
35201(ins HvxVR:$Vu32, IntRegs:$Rt32),
35202"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)",
35203tc_0b04c6c7, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> {
35204let Inst{7-5} = 0b011;
35205let Inst{13-13} = 0b0;
35206let Inst{31-21} = 0b00011001010;
35207let hasNewValue = 1;
35208let opNewValue = 0;
35209let isCVI = 1;
35210let DecoderNamespace = "EXT_mmvec";
35211}
35212def V6_vmpyuh_acc : HInst<
35213(outs HvxWR:$Vxx32),
35214(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35215"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)",
35216tc_660769f1, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> {
35217let Inst{7-5} = 0b001;
35218let Inst{13-13} = 0b1;
35219let Inst{31-21} = 0b00011001010;
35220let hasNewValue = 1;
35221let opNewValue = 0;
35222let isAccumulator = 1;
35223let isCVI = 1;
35224let DecoderNamespace = "EXT_mmvec";
35225let Constraints = "$Vxx32 = $Vxx32in";
35226}
35227def V6_vmpyuh_acc_alt : HInst<
35228(outs HvxWR:$Vxx32),
35229(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35230"$Vxx32 += vmpyuh($Vu32,$Rt32)",
35231PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35232let hasNewValue = 1;
35233let opNewValue = 0;
35234let isAccumulator = 1;
35235let isCVI = 1;
35236let isPseudo = 1;
35237let isCodeGenOnly = 1;
35238let DecoderNamespace = "EXT_mmvec";
35239let Constraints = "$Vxx32 = $Vxx32in";
35240}
35241def V6_vmpyuh_alt : HInst<
35242(outs HvxWR:$Vdd32),
35243(ins HvxVR:$Vu32, IntRegs:$Rt32),
35244"$Vdd32 = vmpyuh($Vu32,$Rt32)",
35245PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35246let hasNewValue = 1;
35247let opNewValue = 0;
35248let isCVI = 1;
35249let isPseudo = 1;
35250let isCodeGenOnly = 1;
35251let DecoderNamespace = "EXT_mmvec";
35252}
35253def V6_vmpyuhe : HInst<
35254(outs HvxVR:$Vd32),
35255(ins HvxVR:$Vu32, IntRegs:$Rt32),
35256"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)",
35257tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> {
35258let Inst{7-5} = 0b010;
35259let Inst{13-13} = 0b0;
35260let Inst{31-21} = 0b00011001011;
35261let hasNewValue = 1;
35262let opNewValue = 0;
35263let isCVI = 1;
35264let DecoderNamespace = "EXT_mmvec";
35265}
35266def V6_vmpyuhe_acc : HInst<
35267(outs HvxVR:$Vx32),
35268(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35269"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)",
35270tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> {
35271let Inst{7-5} = 0b011;
35272let Inst{13-13} = 0b1;
35273let Inst{31-21} = 0b00011001100;
35274let hasNewValue = 1;
35275let opNewValue = 0;
35276let isAccumulator = 1;
35277let isCVI = 1;
35278let DecoderNamespace = "EXT_mmvec";
35279let Constraints = "$Vx32 = $Vx32in";
35280}
35281def V6_vmpyuhv : HInst<
35282(outs HvxWR:$Vdd32),
35283(ins HvxVR:$Vu32, HvxVR:$Vv32),
35284"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)",
35285tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
35286let Inst{7-5} = 0b000;
35287let Inst{13-13} = 0b0;
35288let Inst{31-21} = 0b00011100001;
35289let hasNewValue = 1;
35290let opNewValue = 0;
35291let isCVI = 1;
35292let DecoderNamespace = "EXT_mmvec";
35293}
35294def V6_vmpyuhv_acc : HInst<
35295(outs HvxWR:$Vxx32),
35296(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35297"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)",
35298tc_08a4f1b6, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> {
35299let Inst{7-5} = 0b000;
35300let Inst{13-13} = 0b1;
35301let Inst{31-21} = 0b00011100001;
35302let hasNewValue = 1;
35303let opNewValue = 0;
35304let isAccumulator = 1;
35305let isCVI = 1;
35306let DecoderNamespace = "EXT_mmvec";
35307let Constraints = "$Vxx32 = $Vxx32in";
35308}
35309def V6_vmpyuhv_acc_alt : HInst<
35310(outs HvxWR:$Vxx32),
35311(ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32),
35312"$Vxx32 += vmpyuh($Vu32,$Vv32)",
35313PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35314let hasNewValue = 1;
35315let opNewValue = 0;
35316let isAccumulator = 1;
35317let isCVI = 1;
35318let isPseudo = 1;
35319let isCodeGenOnly = 1;
35320let DecoderNamespace = "EXT_mmvec";
35321let Constraints = "$Vxx32 = $Vxx32in";
35322}
35323def V6_vmpyuhv_alt : HInst<
35324(outs HvxWR:$Vdd32),
35325(ins HvxVR:$Vu32, HvxVR:$Vv32),
35326"$Vdd32 = vmpyuh($Vu32,$Vv32)",
35327PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35328let hasNewValue = 1;
35329let opNewValue = 0;
35330let isCVI = 1;
35331let isPseudo = 1;
35332let isCodeGenOnly = 1;
35333let DecoderNamespace = "EXT_mmvec";
35334}
35335def V6_vmux : HInst<
35336(outs HvxVR:$Vd32),
35337(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
35338"$Vd32 = vmux($Qt4,$Vu32,$Vv32)",
35339tc_257f6f7c, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> {
35340let Inst{7-7} = 0b0;
35341let Inst{13-13} = 0b1;
35342let Inst{31-21} = 0b00011110111;
35343let hasNewValue = 1;
35344let opNewValue = 0;
35345let isCVI = 1;
35346let DecoderNamespace = "EXT_mmvec";
35347}
35348def V6_vnavgb : HInst<
35349(outs HvxVR:$Vd32),
35350(ins HvxVR:$Vu32, HvxVR:$Vv32),
35351"$Vd32.b = vnavg($Vu32.b,$Vv32.b)",
35352tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> {
35353let Inst{7-5} = 0b110;
35354let Inst{13-13} = 0b1;
35355let Inst{31-21} = 0b00011111000;
35356let hasNewValue = 1;
35357let opNewValue = 0;
35358let isCVI = 1;
35359let DecoderNamespace = "EXT_mmvec";
35360}
35361def V6_vnavgb_alt : HInst<
35362(outs HvxVR:$Vd32),
35363(ins HvxVR:$Vu32, HvxVR:$Vv32),
35364"$Vd32 = vnavgb($Vu32,$Vv32)",
35365PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35366let hasNewValue = 1;
35367let opNewValue = 0;
35368let isCVI = 1;
35369let isPseudo = 1;
35370let isCodeGenOnly = 1;
35371let DecoderNamespace = "EXT_mmvec";
35372}
35373def V6_vnavgh : HInst<
35374(outs HvxVR:$Vd32),
35375(ins HvxVR:$Vu32, HvxVR:$Vv32),
35376"$Vd32.h = vnavg($Vu32.h,$Vv32.h)",
35377tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35378let Inst{7-5} = 0b001;
35379let Inst{13-13} = 0b0;
35380let Inst{31-21} = 0b00011100111;
35381let hasNewValue = 1;
35382let opNewValue = 0;
35383let isCVI = 1;
35384let DecoderNamespace = "EXT_mmvec";
35385}
35386def V6_vnavgh_alt : HInst<
35387(outs HvxVR:$Vd32),
35388(ins HvxVR:$Vu32, HvxVR:$Vv32),
35389"$Vd32 = vnavgh($Vu32,$Vv32)",
35390PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35391let hasNewValue = 1;
35392let opNewValue = 0;
35393let isCVI = 1;
35394let isPseudo = 1;
35395let isCodeGenOnly = 1;
35396let DecoderNamespace = "EXT_mmvec";
35397}
35398def V6_vnavgub : HInst<
35399(outs HvxVR:$Vd32),
35400(ins HvxVR:$Vu32, HvxVR:$Vv32),
35401"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)",
35402tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35403let Inst{7-5} = 0b000;
35404let Inst{13-13} = 0b0;
35405let Inst{31-21} = 0b00011100111;
35406let hasNewValue = 1;
35407let opNewValue = 0;
35408let isCVI = 1;
35409let DecoderNamespace = "EXT_mmvec";
35410}
35411def V6_vnavgub_alt : HInst<
35412(outs HvxVR:$Vd32),
35413(ins HvxVR:$Vu32, HvxVR:$Vv32),
35414"$Vd32 = vnavgub($Vu32,$Vv32)",
35415PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35416let hasNewValue = 1;
35417let opNewValue = 0;
35418let isCVI = 1;
35419let isPseudo = 1;
35420let isCodeGenOnly = 1;
35421let DecoderNamespace = "EXT_mmvec";
35422}
35423def V6_vnavgw : HInst<
35424(outs HvxVR:$Vd32),
35425(ins HvxVR:$Vu32, HvxVR:$Vv32),
35426"$Vd32.w = vnavg($Vu32.w,$Vv32.w)",
35427tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35428let Inst{7-5} = 0b010;
35429let Inst{13-13} = 0b0;
35430let Inst{31-21} = 0b00011100111;
35431let hasNewValue = 1;
35432let opNewValue = 0;
35433let isCVI = 1;
35434let DecoderNamespace = "EXT_mmvec";
35435}
35436def V6_vnavgw_alt : HInst<
35437(outs HvxVR:$Vd32),
35438(ins HvxVR:$Vu32, HvxVR:$Vv32),
35439"$Vd32 = vnavgw($Vu32,$Vv32)",
35440PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35441let hasNewValue = 1;
35442let opNewValue = 0;
35443let isCVI = 1;
35444let isPseudo = 1;
35445let isCodeGenOnly = 1;
35446let DecoderNamespace = "EXT_mmvec";
35447}
35448def V6_vnccombine : HInst<
35449(outs HvxWR:$Vdd32),
35450(ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32),
35451"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)",
35452tc_af25efd9, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> {
35453let Inst{7-7} = 0b0;
35454let Inst{13-13} = 0b0;
35455let Inst{31-21} = 0b00011010010;
35456let isPredicated = 1;
35457let isPredicatedFalse = 1;
35458let hasNewValue = 1;
35459let opNewValue = 0;
35460let isCVI = 1;
35461let DecoderNamespace = "EXT_mmvec";
35462}
35463def V6_vncmov : HInst<
35464(outs HvxVR:$Vd32),
35465(ins PredRegs:$Ps4, HvxVR:$Vu32),
35466"if (!$Ps4) $Vd32 = $Vu32",
35467tc_3aacf4a8, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> {
35468let Inst{7-7} = 0b0;
35469let Inst{13-13} = 0b0;
35470let Inst{31-16} = 0b0001101000100000;
35471let isPredicated = 1;
35472let isPredicatedFalse = 1;
35473let hasNewValue = 1;
35474let opNewValue = 0;
35475let isCVI = 1;
35476let DecoderNamespace = "EXT_mmvec";
35477}
35478def V6_vnormamth : HInst<
35479(outs HvxVR:$Vd32),
35480(ins HvxVR:$Vu32),
35481"$Vd32.h = vnormamt($Vu32.h)",
35482tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35483let Inst{7-5} = 0b101;
35484let Inst{13-13} = 0b0;
35485let Inst{31-16} = 0b0001111000000011;
35486let hasNewValue = 1;
35487let opNewValue = 0;
35488let isCVI = 1;
35489let DecoderNamespace = "EXT_mmvec";
35490}
35491def V6_vnormamth_alt : HInst<
35492(outs HvxVR:$Vd32),
35493(ins HvxVR:$Vu32),
35494"$Vd32 = vnormamth($Vu32)",
35495PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35496let hasNewValue = 1;
35497let opNewValue = 0;
35498let isCVI = 1;
35499let isPseudo = 1;
35500let isCodeGenOnly = 1;
35501let DecoderNamespace = "EXT_mmvec";
35502}
35503def V6_vnormamtw : HInst<
35504(outs HvxVR:$Vd32),
35505(ins HvxVR:$Vu32),
35506"$Vd32.w = vnormamt($Vu32.w)",
35507tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35508let Inst{7-5} = 0b100;
35509let Inst{13-13} = 0b0;
35510let Inst{31-16} = 0b0001111000000011;
35511let hasNewValue = 1;
35512let opNewValue = 0;
35513let isCVI = 1;
35514let DecoderNamespace = "EXT_mmvec";
35515}
35516def V6_vnormamtw_alt : HInst<
35517(outs HvxVR:$Vd32),
35518(ins HvxVR:$Vu32),
35519"$Vd32 = vnormamtw($Vu32)",
35520PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35521let hasNewValue = 1;
35522let opNewValue = 0;
35523let isCVI = 1;
35524let isPseudo = 1;
35525let isCodeGenOnly = 1;
35526let DecoderNamespace = "EXT_mmvec";
35527}
35528def V6_vnot : HInst<
35529(outs HvxVR:$Vd32),
35530(ins HvxVR:$Vu32),
35531"$Vd32 = vnot($Vu32)",
35532tc_0ec46cf9, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> {
35533let Inst{7-5} = 0b100;
35534let Inst{13-13} = 0b0;
35535let Inst{31-16} = 0b0001111000000000;
35536let hasNewValue = 1;
35537let opNewValue = 0;
35538let isCVI = 1;
35539let DecoderNamespace = "EXT_mmvec";
35540}
35541def V6_vor : HInst<
35542(outs HvxVR:$Vd32),
35543(ins HvxVR:$Vu32, HvxVR:$Vv32),
35544"$Vd32 = vor($Vu32,$Vv32)",
35545tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
35546let Inst{7-5} = 0b110;
35547let Inst{13-13} = 0b0;
35548let Inst{31-21} = 0b00011100001;
35549let hasNewValue = 1;
35550let opNewValue = 0;
35551let isCVI = 1;
35552let DecoderNamespace = "EXT_mmvec";
35553}
35554def V6_vpackeb : HInst<
35555(outs HvxVR:$Vd32),
35556(ins HvxVR:$Vu32, HvxVR:$Vv32),
35557"$Vd32.b = vpacke($Vu32.h,$Vv32.h)",
35558tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35559let Inst{7-5} = 0b010;
35560let Inst{13-13} = 0b0;
35561let Inst{31-21} = 0b00011111110;
35562let hasNewValue = 1;
35563let opNewValue = 0;
35564let isCVI = 1;
35565let DecoderNamespace = "EXT_mmvec";
35566}
35567def V6_vpackeb_alt : HInst<
35568(outs HvxVR:$Vd32),
35569(ins HvxVR:$Vu32, HvxVR:$Vv32),
35570"$Vd32 = vpackeb($Vu32,$Vv32)",
35571PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35572let hasNewValue = 1;
35573let opNewValue = 0;
35574let isCVI = 1;
35575let isPseudo = 1;
35576let isCodeGenOnly = 1;
35577let DecoderNamespace = "EXT_mmvec";
35578}
35579def V6_vpackeh : HInst<
35580(outs HvxVR:$Vd32),
35581(ins HvxVR:$Vu32, HvxVR:$Vv32),
35582"$Vd32.h = vpacke($Vu32.w,$Vv32.w)",
35583tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35584let Inst{7-5} = 0b011;
35585let Inst{13-13} = 0b0;
35586let Inst{31-21} = 0b00011111110;
35587let hasNewValue = 1;
35588let opNewValue = 0;
35589let isCVI = 1;
35590let DecoderNamespace = "EXT_mmvec";
35591}
35592def V6_vpackeh_alt : HInst<
35593(outs HvxVR:$Vd32),
35594(ins HvxVR:$Vu32, HvxVR:$Vv32),
35595"$Vd32 = vpackeh($Vu32,$Vv32)",
35596PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35597let hasNewValue = 1;
35598let opNewValue = 0;
35599let isCVI = 1;
35600let isPseudo = 1;
35601let isCodeGenOnly = 1;
35602let DecoderNamespace = "EXT_mmvec";
35603}
35604def V6_vpackhb_sat : HInst<
35605(outs HvxVR:$Vd32),
35606(ins HvxVR:$Vu32, HvxVR:$Vv32),
35607"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat",
35608tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35609let Inst{7-5} = 0b110;
35610let Inst{13-13} = 0b0;
35611let Inst{31-21} = 0b00011111110;
35612let hasNewValue = 1;
35613let opNewValue = 0;
35614let isCVI = 1;
35615let DecoderNamespace = "EXT_mmvec";
35616}
35617def V6_vpackhb_sat_alt : HInst<
35618(outs HvxVR:$Vd32),
35619(ins HvxVR:$Vu32, HvxVR:$Vv32),
35620"$Vd32 = vpackhb($Vu32,$Vv32):sat",
35621PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35622let hasNewValue = 1;
35623let opNewValue = 0;
35624let isCVI = 1;
35625let isPseudo = 1;
35626let isCodeGenOnly = 1;
35627let DecoderNamespace = "EXT_mmvec";
35628}
35629def V6_vpackhub_sat : HInst<
35630(outs HvxVR:$Vd32),
35631(ins HvxVR:$Vu32, HvxVR:$Vv32),
35632"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat",
35633tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35634let Inst{7-5} = 0b101;
35635let Inst{13-13} = 0b0;
35636let Inst{31-21} = 0b00011111110;
35637let hasNewValue = 1;
35638let opNewValue = 0;
35639let isCVI = 1;
35640let DecoderNamespace = "EXT_mmvec";
35641}
35642def V6_vpackhub_sat_alt : HInst<
35643(outs HvxVR:$Vd32),
35644(ins HvxVR:$Vu32, HvxVR:$Vv32),
35645"$Vd32 = vpackhub($Vu32,$Vv32):sat",
35646PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35647let hasNewValue = 1;
35648let opNewValue = 0;
35649let isCVI = 1;
35650let isPseudo = 1;
35651let isCodeGenOnly = 1;
35652let DecoderNamespace = "EXT_mmvec";
35653}
35654def V6_vpackob : HInst<
35655(outs HvxVR:$Vd32),
35656(ins HvxVR:$Vu32, HvxVR:$Vv32),
35657"$Vd32.b = vpacko($Vu32.h,$Vv32.h)",
35658tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35659let Inst{7-5} = 0b001;
35660let Inst{13-13} = 0b0;
35661let Inst{31-21} = 0b00011111111;
35662let hasNewValue = 1;
35663let opNewValue = 0;
35664let isCVI = 1;
35665let DecoderNamespace = "EXT_mmvec";
35666}
35667def V6_vpackob_alt : HInst<
35668(outs HvxVR:$Vd32),
35669(ins HvxVR:$Vu32, HvxVR:$Vv32),
35670"$Vd32 = vpackob($Vu32,$Vv32)",
35671PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35672let hasNewValue = 1;
35673let opNewValue = 0;
35674let isCVI = 1;
35675let isPseudo = 1;
35676let isCodeGenOnly = 1;
35677let DecoderNamespace = "EXT_mmvec";
35678}
35679def V6_vpackoh : HInst<
35680(outs HvxVR:$Vd32),
35681(ins HvxVR:$Vu32, HvxVR:$Vv32),
35682"$Vd32.h = vpacko($Vu32.w,$Vv32.w)",
35683tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35684let Inst{7-5} = 0b010;
35685let Inst{13-13} = 0b0;
35686let Inst{31-21} = 0b00011111111;
35687let hasNewValue = 1;
35688let opNewValue = 0;
35689let isCVI = 1;
35690let DecoderNamespace = "EXT_mmvec";
35691}
35692def V6_vpackoh_alt : HInst<
35693(outs HvxVR:$Vd32),
35694(ins HvxVR:$Vu32, HvxVR:$Vv32),
35695"$Vd32 = vpackoh($Vu32,$Vv32)",
35696PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35697let hasNewValue = 1;
35698let opNewValue = 0;
35699let isCVI = 1;
35700let isPseudo = 1;
35701let isCodeGenOnly = 1;
35702let DecoderNamespace = "EXT_mmvec";
35703}
35704def V6_vpackwh_sat : HInst<
35705(outs HvxVR:$Vd32),
35706(ins HvxVR:$Vu32, HvxVR:$Vv32),
35707"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat",
35708tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35709let Inst{7-5} = 0b000;
35710let Inst{13-13} = 0b0;
35711let Inst{31-21} = 0b00011111111;
35712let hasNewValue = 1;
35713let opNewValue = 0;
35714let isCVI = 1;
35715let DecoderNamespace = "EXT_mmvec";
35716}
35717def V6_vpackwh_sat_alt : HInst<
35718(outs HvxVR:$Vd32),
35719(ins HvxVR:$Vu32, HvxVR:$Vv32),
35720"$Vd32 = vpackwh($Vu32,$Vv32):sat",
35721PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35722let hasNewValue = 1;
35723let opNewValue = 0;
35724let isCVI = 1;
35725let isPseudo = 1;
35726let isCodeGenOnly = 1;
35727let DecoderNamespace = "EXT_mmvec";
35728}
35729def V6_vpackwuh_sat : HInst<
35730(outs HvxVR:$Vd32),
35731(ins HvxVR:$Vu32, HvxVR:$Vv32),
35732"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat",
35733tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35734let Inst{7-5} = 0b111;
35735let Inst{13-13} = 0b0;
35736let Inst{31-21} = 0b00011111110;
35737let hasNewValue = 1;
35738let opNewValue = 0;
35739let isCVI = 1;
35740let DecoderNamespace = "EXT_mmvec";
35741}
35742def V6_vpackwuh_sat_alt : HInst<
35743(outs HvxVR:$Vd32),
35744(ins HvxVR:$Vu32, HvxVR:$Vv32),
35745"$Vd32 = vpackwuh($Vu32,$Vv32):sat",
35746PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35747let hasNewValue = 1;
35748let opNewValue = 0;
35749let isCVI = 1;
35750let isPseudo = 1;
35751let isCodeGenOnly = 1;
35752let DecoderNamespace = "EXT_mmvec";
35753}
35754def V6_vpopcounth : HInst<
35755(outs HvxVR:$Vd32),
35756(ins HvxVR:$Vu32),
35757"$Vd32.h = vpopcount($Vu32.h)",
35758tc_51d0ecc3, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> {
35759let Inst{7-5} = 0b110;
35760let Inst{13-13} = 0b0;
35761let Inst{31-16} = 0b0001111000000010;
35762let hasNewValue = 1;
35763let opNewValue = 0;
35764let isCVI = 1;
35765let DecoderNamespace = "EXT_mmvec";
35766}
35767def V6_vpopcounth_alt : HInst<
35768(outs HvxVR:$Vd32),
35769(ins HvxVR:$Vu32),
35770"$Vd32 = vpopcounth($Vu32)",
35771PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35772let hasNewValue = 1;
35773let opNewValue = 0;
35774let isCVI = 1;
35775let isPseudo = 1;
35776let isCodeGenOnly = 1;
35777let DecoderNamespace = "EXT_mmvec";
35778}
35779def V6_vprefixqb : HInst<
35780(outs HvxVR:$Vd32),
35781(ins HvxQR:$Qv4),
35782"$Vd32.b = prefixsum($Qv4)",
35783tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35784let Inst{13-5} = 0b100000010;
35785let Inst{21-16} = 0b000011;
35786let Inst{31-24} = 0b00011110;
35787let hasNewValue = 1;
35788let opNewValue = 0;
35789let isCVI = 1;
35790let DecoderNamespace = "EXT_mmvec";
35791}
35792def V6_vprefixqh : HInst<
35793(outs HvxVR:$Vd32),
35794(ins HvxQR:$Qv4),
35795"$Vd32.h = prefixsum($Qv4)",
35796tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35797let Inst{13-5} = 0b100001010;
35798let Inst{21-16} = 0b000011;
35799let Inst{31-24} = 0b00011110;
35800let hasNewValue = 1;
35801let opNewValue = 0;
35802let isCVI = 1;
35803let DecoderNamespace = "EXT_mmvec";
35804}
35805def V6_vprefixqw : HInst<
35806(outs HvxVR:$Vd32),
35807(ins HvxQR:$Qv4),
35808"$Vd32.w = prefixsum($Qv4)",
35809tc_51d0ecc3, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> {
35810let Inst{13-5} = 0b100010010;
35811let Inst{21-16} = 0b000011;
35812let Inst{31-24} = 0b00011110;
35813let hasNewValue = 1;
35814let opNewValue = 0;
35815let isCVI = 1;
35816let DecoderNamespace = "EXT_mmvec";
35817}
35818def V6_vrdelta : HInst<
35819(outs HvxVR:$Vd32),
35820(ins HvxVR:$Vu32, HvxVR:$Vv32),
35821"$Vd32 = vrdelta($Vu32,$Vv32)",
35822tc_46d6c3e0, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> {
35823let Inst{7-5} = 0b011;
35824let Inst{13-13} = 0b0;
35825let Inst{31-21} = 0b00011111001;
35826let hasNewValue = 1;
35827let opNewValue = 0;
35828let isCVI = 1;
35829let DecoderNamespace = "EXT_mmvec";
35830}
35831def V6_vrmpybub_rtt : HInst<
35832(outs HvxWR:$Vdd32),
35833(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35834"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
35835tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
35836let Inst{7-5} = 0b101;
35837let Inst{13-13} = 0b0;
35838let Inst{31-21} = 0b00011001110;
35839let hasNewValue = 1;
35840let opNewValue = 0;
35841let isCVI = 1;
35842let DecoderNamespace = "EXT_mmvec";
35843}
35844def V6_vrmpybub_rtt_acc : HInst<
35845(outs HvxWR:$Vxx32),
35846(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35847"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
35848tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
35849let Inst{7-5} = 0b000;
35850let Inst{13-13} = 0b1;
35851let Inst{31-21} = 0b00011001101;
35852let hasNewValue = 1;
35853let opNewValue = 0;
35854let isAccumulator = 1;
35855let isCVI = 1;
35856let DecoderNamespace = "EXT_mmvec";
35857let Constraints = "$Vxx32 = $Vxx32in";
35858}
35859def V6_vrmpybub_rtt_acc_alt : HInst<
35860(outs HvxWR:$Vxx32),
35861(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
35862"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)",
35863PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35864let hasNewValue = 1;
35865let opNewValue = 0;
35866let isAccumulator = 1;
35867let isCVI = 1;
35868let isPseudo = 1;
35869let isCodeGenOnly = 1;
35870let DecoderNamespace = "EXT_mmvec";
35871let Constraints = "$Vxx32 = $Vxx32in";
35872}
35873def V6_vrmpybub_rtt_alt : HInst<
35874(outs HvxWR:$Vdd32),
35875(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
35876"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)",
35877PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
35878let hasNewValue = 1;
35879let opNewValue = 0;
35880let isCVI = 1;
35881let isPseudo = 1;
35882let isCodeGenOnly = 1;
35883let DecoderNamespace = "EXT_mmvec";
35884}
35885def V6_vrmpybus : HInst<
35886(outs HvxVR:$Vd32),
35887(ins HvxVR:$Vu32, IntRegs:$Rt32),
35888"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)",
35889tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
35890let Inst{7-5} = 0b100;
35891let Inst{13-13} = 0b0;
35892let Inst{31-21} = 0b00011001000;
35893let hasNewValue = 1;
35894let opNewValue = 0;
35895let isCVI = 1;
35896let DecoderNamespace = "EXT_mmvec";
35897}
35898def V6_vrmpybus_acc : HInst<
35899(outs HvxVR:$Vx32),
35900(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35901"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)",
35902tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
35903let Inst{7-5} = 0b101;
35904let Inst{13-13} = 0b1;
35905let Inst{31-21} = 0b00011001000;
35906let hasNewValue = 1;
35907let opNewValue = 0;
35908let isAccumulator = 1;
35909let isCVI = 1;
35910let DecoderNamespace = "EXT_mmvec";
35911let Constraints = "$Vx32 = $Vx32in";
35912}
35913def V6_vrmpybus_acc_alt : HInst<
35914(outs HvxVR:$Vx32),
35915(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
35916"$Vx32 += vrmpybus($Vu32,$Rt32)",
35917PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35918let hasNewValue = 1;
35919let opNewValue = 0;
35920let isAccumulator = 1;
35921let isCVI = 1;
35922let isPseudo = 1;
35923let isCodeGenOnly = 1;
35924let DecoderNamespace = "EXT_mmvec";
35925let Constraints = "$Vx32 = $Vx32in";
35926}
35927def V6_vrmpybus_alt : HInst<
35928(outs HvxVR:$Vd32),
35929(ins HvxVR:$Vu32, IntRegs:$Rt32),
35930"$Vd32 = vrmpybus($Vu32,$Rt32)",
35931PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35932let hasNewValue = 1;
35933let opNewValue = 0;
35934let isCVI = 1;
35935let isPseudo = 1;
35936let isCodeGenOnly = 1;
35937let DecoderNamespace = "EXT_mmvec";
35938}
35939def V6_vrmpybusi : HInst<
35940(outs HvxWR:$Vdd32),
35941(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35942"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
35943tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
35944let Inst{7-6} = 0b10;
35945let Inst{13-13} = 0b0;
35946let Inst{31-21} = 0b00011001010;
35947let hasNewValue = 1;
35948let opNewValue = 0;
35949let isCVI = 1;
35950let DecoderNamespace = "EXT_mmvec";
35951}
35952def V6_vrmpybusi_acc : HInst<
35953(outs HvxWR:$Vxx32),
35954(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35955"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)",
35956tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
35957let Inst{7-6} = 0b10;
35958let Inst{13-13} = 0b1;
35959let Inst{31-21} = 0b00011001010;
35960let hasNewValue = 1;
35961let opNewValue = 0;
35962let isAccumulator = 1;
35963let isCVI = 1;
35964let DecoderNamespace = "EXT_mmvec";
35965let Constraints = "$Vxx32 = $Vxx32in";
35966}
35967def V6_vrmpybusi_acc_alt : HInst<
35968(outs HvxWR:$Vxx32),
35969(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35970"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)",
35971PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35972let hasNewValue = 1;
35973let opNewValue = 0;
35974let isAccumulator = 1;
35975let isCVI = 1;
35976let isPseudo = 1;
35977let isCodeGenOnly = 1;
35978let DecoderNamespace = "EXT_mmvec";
35979let Constraints = "$Vxx32 = $Vxx32in";
35980}
35981def V6_vrmpybusi_alt : HInst<
35982(outs HvxWR:$Vdd32),
35983(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
35984"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)",
35985PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
35986let hasNewValue = 1;
35987let opNewValue = 0;
35988let isCVI = 1;
35989let isPseudo = 1;
35990let isCodeGenOnly = 1;
35991let DecoderNamespace = "EXT_mmvec";
35992}
35993def V6_vrmpybusv : HInst<
35994(outs HvxVR:$Vd32),
35995(ins HvxVR:$Vu32, HvxVR:$Vv32),
35996"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)",
35997tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
35998let Inst{7-5} = 0b010;
35999let Inst{13-13} = 0b0;
36000let Inst{31-21} = 0b00011100000;
36001let hasNewValue = 1;
36002let opNewValue = 0;
36003let isCVI = 1;
36004let DecoderNamespace = "EXT_mmvec";
36005}
36006def V6_vrmpybusv_acc : HInst<
36007(outs HvxVR:$Vx32),
36008(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36009"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)",
36010tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36011let Inst{7-5} = 0b010;
36012let Inst{13-13} = 0b1;
36013let Inst{31-21} = 0b00011100000;
36014let hasNewValue = 1;
36015let opNewValue = 0;
36016let isAccumulator = 1;
36017let isCVI = 1;
36018let DecoderNamespace = "EXT_mmvec";
36019let Constraints = "$Vx32 = $Vx32in";
36020}
36021def V6_vrmpybusv_acc_alt : HInst<
36022(outs HvxVR:$Vx32),
36023(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36024"$Vx32 += vrmpybus($Vu32,$Vv32)",
36025PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36026let hasNewValue = 1;
36027let opNewValue = 0;
36028let isAccumulator = 1;
36029let isCVI = 1;
36030let isPseudo = 1;
36031let isCodeGenOnly = 1;
36032let DecoderNamespace = "EXT_mmvec";
36033let Constraints = "$Vx32 = $Vx32in";
36034}
36035def V6_vrmpybusv_alt : HInst<
36036(outs HvxVR:$Vd32),
36037(ins HvxVR:$Vu32, HvxVR:$Vv32),
36038"$Vd32 = vrmpybus($Vu32,$Vv32)",
36039PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36040let hasNewValue = 1;
36041let opNewValue = 0;
36042let isCVI = 1;
36043let isPseudo = 1;
36044let isCodeGenOnly = 1;
36045let DecoderNamespace = "EXT_mmvec";
36046}
36047def V6_vrmpybv : HInst<
36048(outs HvxVR:$Vd32),
36049(ins HvxVR:$Vu32, HvxVR:$Vv32),
36050"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)",
36051tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
36052let Inst{7-5} = 0b001;
36053let Inst{13-13} = 0b0;
36054let Inst{31-21} = 0b00011100000;
36055let hasNewValue = 1;
36056let opNewValue = 0;
36057let isCVI = 1;
36058let DecoderNamespace = "EXT_mmvec";
36059}
36060def V6_vrmpybv_acc : HInst<
36061(outs HvxVR:$Vx32),
36062(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36063"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)",
36064tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36065let Inst{7-5} = 0b001;
36066let Inst{13-13} = 0b1;
36067let Inst{31-21} = 0b00011100000;
36068let hasNewValue = 1;
36069let opNewValue = 0;
36070let isAccumulator = 1;
36071let isCVI = 1;
36072let DecoderNamespace = "EXT_mmvec";
36073let Constraints = "$Vx32 = $Vx32in";
36074}
36075def V6_vrmpybv_acc_alt : HInst<
36076(outs HvxVR:$Vx32),
36077(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36078"$Vx32 += vrmpyb($Vu32,$Vv32)",
36079PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36080let hasNewValue = 1;
36081let opNewValue = 0;
36082let isAccumulator = 1;
36083let isCVI = 1;
36084let isPseudo = 1;
36085let isCodeGenOnly = 1;
36086let DecoderNamespace = "EXT_mmvec";
36087let Constraints = "$Vx32 = $Vx32in";
36088}
36089def V6_vrmpybv_alt : HInst<
36090(outs HvxVR:$Vd32),
36091(ins HvxVR:$Vu32, HvxVR:$Vv32),
36092"$Vd32 = vrmpyb($Vu32,$Vv32)",
36093PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36094let hasNewValue = 1;
36095let opNewValue = 0;
36096let isCVI = 1;
36097let isPseudo = 1;
36098let isCodeGenOnly = 1;
36099let DecoderNamespace = "EXT_mmvec";
36100}
36101def V6_vrmpyub : HInst<
36102(outs HvxVR:$Vd32),
36103(ins HvxVR:$Vu32, IntRegs:$Rt32),
36104"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)",
36105tc_649072c2, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> {
36106let Inst{7-5} = 0b011;
36107let Inst{13-13} = 0b0;
36108let Inst{31-21} = 0b00011001000;
36109let hasNewValue = 1;
36110let opNewValue = 0;
36111let isCVI = 1;
36112let DecoderNamespace = "EXT_mmvec";
36113}
36114def V6_vrmpyub_acc : HInst<
36115(outs HvxVR:$Vx32),
36116(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36117"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)",
36118tc_b091f1c6, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> {
36119let Inst{7-5} = 0b100;
36120let Inst{13-13} = 0b1;
36121let Inst{31-21} = 0b00011001000;
36122let hasNewValue = 1;
36123let opNewValue = 0;
36124let isAccumulator = 1;
36125let isCVI = 1;
36126let DecoderNamespace = "EXT_mmvec";
36127let Constraints = "$Vx32 = $Vx32in";
36128}
36129def V6_vrmpyub_acc_alt : HInst<
36130(outs HvxVR:$Vx32),
36131(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32),
36132"$Vx32 += vrmpyub($Vu32,$Rt32)",
36133PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36134let hasNewValue = 1;
36135let opNewValue = 0;
36136let isAccumulator = 1;
36137let isCVI = 1;
36138let isPseudo = 1;
36139let isCodeGenOnly = 1;
36140let DecoderNamespace = "EXT_mmvec";
36141let Constraints = "$Vx32 = $Vx32in";
36142}
36143def V6_vrmpyub_alt : HInst<
36144(outs HvxVR:$Vd32),
36145(ins HvxVR:$Vu32, IntRegs:$Rt32),
36146"$Vd32 = vrmpyub($Vu32,$Rt32)",
36147PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36148let hasNewValue = 1;
36149let opNewValue = 0;
36150let isCVI = 1;
36151let isPseudo = 1;
36152let isCodeGenOnly = 1;
36153let DecoderNamespace = "EXT_mmvec";
36154}
36155def V6_vrmpyub_rtt : HInst<
36156(outs HvxWR:$Vdd32),
36157(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
36158"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
36159tc_cd94bfe0, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> {
36160let Inst{7-5} = 0b100;
36161let Inst{13-13} = 0b0;
36162let Inst{31-21} = 0b00011001110;
36163let hasNewValue = 1;
36164let opNewValue = 0;
36165let isCVI = 1;
36166let DecoderNamespace = "EXT_mmvec";
36167}
36168def V6_vrmpyub_rtt_acc : HInst<
36169(outs HvxWR:$Vxx32),
36170(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
36171"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
36172tc_15fdf750, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> {
36173let Inst{7-5} = 0b111;
36174let Inst{13-13} = 0b1;
36175let Inst{31-21} = 0b00011001101;
36176let hasNewValue = 1;
36177let opNewValue = 0;
36178let isAccumulator = 1;
36179let isCVI = 1;
36180let DecoderNamespace = "EXT_mmvec";
36181let Constraints = "$Vxx32 = $Vxx32in";
36182}
36183def V6_vrmpyub_rtt_acc_alt : HInst<
36184(outs HvxWR:$Vxx32),
36185(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32),
36186"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)",
36187PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36188let hasNewValue = 1;
36189let opNewValue = 0;
36190let isAccumulator = 1;
36191let isCVI = 1;
36192let isPseudo = 1;
36193let isCodeGenOnly = 1;
36194let DecoderNamespace = "EXT_mmvec";
36195let Constraints = "$Vxx32 = $Vxx32in";
36196}
36197def V6_vrmpyub_rtt_alt : HInst<
36198(outs HvxWR:$Vdd32),
36199(ins HvxVR:$Vu32, DoubleRegs:$Rtt32),
36200"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)",
36201PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36202let hasNewValue = 1;
36203let opNewValue = 0;
36204let isCVI = 1;
36205let isPseudo = 1;
36206let isCodeGenOnly = 1;
36207let DecoderNamespace = "EXT_mmvec";
36208}
36209def V6_vrmpyubi : HInst<
36210(outs HvxWR:$Vdd32),
36211(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36212"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
36213tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
36214let Inst{7-6} = 0b11;
36215let Inst{13-13} = 0b0;
36216let Inst{31-21} = 0b00011001101;
36217let hasNewValue = 1;
36218let opNewValue = 0;
36219let isCVI = 1;
36220let DecoderNamespace = "EXT_mmvec";
36221}
36222def V6_vrmpyubi_acc : HInst<
36223(outs HvxWR:$Vxx32),
36224(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36225"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)",
36226tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
36227let Inst{7-6} = 0b11;
36228let Inst{13-13} = 0b1;
36229let Inst{31-21} = 0b00011001011;
36230let hasNewValue = 1;
36231let opNewValue = 0;
36232let isAccumulator = 1;
36233let isCVI = 1;
36234let DecoderNamespace = "EXT_mmvec";
36235let Constraints = "$Vxx32 = $Vxx32in";
36236}
36237def V6_vrmpyubi_acc_alt : HInst<
36238(outs HvxWR:$Vxx32),
36239(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36240"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)",
36241PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36242let hasNewValue = 1;
36243let opNewValue = 0;
36244let isAccumulator = 1;
36245let isCVI = 1;
36246let isPseudo = 1;
36247let isCodeGenOnly = 1;
36248let DecoderNamespace = "EXT_mmvec";
36249let Constraints = "$Vxx32 = $Vxx32in";
36250}
36251def V6_vrmpyubi_alt : HInst<
36252(outs HvxWR:$Vdd32),
36253(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36254"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)",
36255PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36256let hasNewValue = 1;
36257let opNewValue = 0;
36258let isCVI = 1;
36259let isPseudo = 1;
36260let isCodeGenOnly = 1;
36261let DecoderNamespace = "EXT_mmvec";
36262}
36263def V6_vrmpyubv : HInst<
36264(outs HvxVR:$Vd32),
36265(ins HvxVR:$Vu32, HvxVR:$Vv32),
36266"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)",
36267tc_c127de3a, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> {
36268let Inst{7-5} = 0b000;
36269let Inst{13-13} = 0b0;
36270let Inst{31-21} = 0b00011100000;
36271let hasNewValue = 1;
36272let opNewValue = 0;
36273let isCVI = 1;
36274let DecoderNamespace = "EXT_mmvec";
36275}
36276def V6_vrmpyubv_acc : HInst<
36277(outs HvxVR:$Vx32),
36278(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36279"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)",
36280tc_08a4f1b6, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> {
36281let Inst{7-5} = 0b000;
36282let Inst{13-13} = 0b1;
36283let Inst{31-21} = 0b00011100000;
36284let hasNewValue = 1;
36285let opNewValue = 0;
36286let isAccumulator = 1;
36287let isCVI = 1;
36288let DecoderNamespace = "EXT_mmvec";
36289let Constraints = "$Vx32 = $Vx32in";
36290}
36291def V6_vrmpyubv_acc_alt : HInst<
36292(outs HvxVR:$Vx32),
36293(ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32),
36294"$Vx32 += vrmpyub($Vu32,$Vv32)",
36295PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36296let hasNewValue = 1;
36297let opNewValue = 0;
36298let isAccumulator = 1;
36299let isCVI = 1;
36300let isPseudo = 1;
36301let isCodeGenOnly = 1;
36302let DecoderNamespace = "EXT_mmvec";
36303let Constraints = "$Vx32 = $Vx32in";
36304}
36305def V6_vrmpyubv_alt : HInst<
36306(outs HvxVR:$Vd32),
36307(ins HvxVR:$Vu32, HvxVR:$Vv32),
36308"$Vd32 = vrmpyub($Vu32,$Vv32)",
36309PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36310let hasNewValue = 1;
36311let opNewValue = 0;
36312let isCVI = 1;
36313let isPseudo = 1;
36314let isCodeGenOnly = 1;
36315let DecoderNamespace = "EXT_mmvec";
36316}
36317def V6_vrmpyzbb_rt : HInst<
36318(outs HvxVQR:$Vdddd32),
36319(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36320"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.b)",
36321tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36322let Inst{7-5} = 0b000;
36323let Inst{13-13} = 0b0;
36324let Inst{31-19} = 0b0001100111101;
36325let hasNewValue = 1;
36326let opNewValue = 0;
36327let isCVI = 1;
36328let DecoderNamespace = "EXT_mmvec";
36329}
36330def V6_vrmpyzbb_rt_acc : HInst<
36331(outs HvxVQR:$Vyyyy32),
36332(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36333"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.b)",
36334tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36335let Inst{7-5} = 0b010;
36336let Inst{13-13} = 0b1;
36337let Inst{31-19} = 0b0001100111000;
36338let hasNewValue = 1;
36339let opNewValue = 0;
36340let isAccumulator = 1;
36341let isCVI = 1;
36342let DecoderNamespace = "EXT_mmvec";
36343let Constraints = "$Vyyyy32 = $Vyyyy32in";
36344}
36345def V6_vrmpyzbb_rx : HInst<
36346(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36347(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36348"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)",
36349tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36350let Inst{7-5} = 0b000;
36351let Inst{13-13} = 0b0;
36352let Inst{31-19} = 0b0001100111100;
36353let hasNewValue = 1;
36354let opNewValue = 0;
36355let isCVI = 1;
36356let DecoderNamespace = "EXT_mmvec";
36357let Constraints = "$Rx8 = $Rx8in";
36358}
36359def V6_vrmpyzbb_rx_acc : HInst<
36360(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36361(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36362"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)",
36363tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36364let Inst{7-5} = 0b010;
36365let Inst{13-13} = 0b1;
36366let Inst{31-19} = 0b0001100111001;
36367let hasNewValue = 1;
36368let opNewValue = 0;
36369let isAccumulator = 1;
36370let isCVI = 1;
36371let DecoderNamespace = "EXT_mmvec";
36372let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36373}
36374def V6_vrmpyzbub_rt : HInst<
36375(outs HvxVQR:$Vdddd32),
36376(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36377"$Vdddd32.w = vrmpyz($Vu32.b,$Rt8.ub)",
36378tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36379let Inst{7-5} = 0b010;
36380let Inst{13-13} = 0b0;
36381let Inst{31-19} = 0b0001100111111;
36382let hasNewValue = 1;
36383let opNewValue = 0;
36384let isCVI = 1;
36385let DecoderNamespace = "EXT_mmvec";
36386}
36387def V6_vrmpyzbub_rt_acc : HInst<
36388(outs HvxVQR:$Vyyyy32),
36389(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36390"$Vyyyy32.w += vrmpyz($Vu32.b,$Rt8.ub)",
36391tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36392let Inst{7-5} = 0b001;
36393let Inst{13-13} = 0b1;
36394let Inst{31-19} = 0b0001100111010;
36395let hasNewValue = 1;
36396let opNewValue = 0;
36397let isAccumulator = 1;
36398let isCVI = 1;
36399let DecoderNamespace = "EXT_mmvec";
36400let Constraints = "$Vyyyy32 = $Vyyyy32in";
36401}
36402def V6_vrmpyzbub_rx : HInst<
36403(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36404(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36405"$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)",
36406tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36407let Inst{7-5} = 0b010;
36408let Inst{13-13} = 0b0;
36409let Inst{31-19} = 0b0001100111110;
36410let hasNewValue = 1;
36411let opNewValue = 0;
36412let isCVI = 1;
36413let DecoderNamespace = "EXT_mmvec";
36414let Constraints = "$Rx8 = $Rx8in";
36415}
36416def V6_vrmpyzbub_rx_acc : HInst<
36417(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36418(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36419"$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)",
36420tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36421let Inst{7-5} = 0b001;
36422let Inst{13-13} = 0b1;
36423let Inst{31-19} = 0b0001100111011;
36424let hasNewValue = 1;
36425let opNewValue = 0;
36426let isAccumulator = 1;
36427let isCVI = 1;
36428let DecoderNamespace = "EXT_mmvec";
36429let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36430}
36431def V6_vrmpyzcb_rt : HInst<
36432(outs HvxVQR:$Vdddd32),
36433(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36434"$Vdddd32.w = vr16mpyz($Vu32.c,$Rt8.b)",
36435tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36436let Inst{7-5} = 0b001;
36437let Inst{13-13} = 0b0;
36438let Inst{31-19} = 0b0001100111101;
36439let hasNewValue = 1;
36440let opNewValue = 0;
36441let isCVI = 1;
36442let DecoderNamespace = "EXT_mmvec";
36443}
36444def V6_vrmpyzcb_rt_acc : HInst<
36445(outs HvxVQR:$Vyyyy32),
36446(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36447"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rt8.b)",
36448tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36449let Inst{7-5} = 0b011;
36450let Inst{13-13} = 0b1;
36451let Inst{31-19} = 0b0001100111000;
36452let hasNewValue = 1;
36453let opNewValue = 0;
36454let isAccumulator = 1;
36455let isCVI = 1;
36456let DecoderNamespace = "EXT_mmvec";
36457let Constraints = "$Vyyyy32 = $Vyyyy32in";
36458}
36459def V6_vrmpyzcb_rx : HInst<
36460(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36461(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36462"$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)",
36463tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36464let Inst{7-5} = 0b001;
36465let Inst{13-13} = 0b0;
36466let Inst{31-19} = 0b0001100111100;
36467let hasNewValue = 1;
36468let opNewValue = 0;
36469let isCVI = 1;
36470let DecoderNamespace = "EXT_mmvec";
36471let Constraints = "$Rx8 = $Rx8in";
36472}
36473def V6_vrmpyzcb_rx_acc : HInst<
36474(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36475(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36476"$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)",
36477tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36478let Inst{7-5} = 0b011;
36479let Inst{13-13} = 0b1;
36480let Inst{31-19} = 0b0001100111001;
36481let hasNewValue = 1;
36482let opNewValue = 0;
36483let isAccumulator = 1;
36484let isCVI = 1;
36485let DecoderNamespace = "EXT_mmvec";
36486let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36487}
36488def V6_vrmpyzcbs_rt : HInst<
36489(outs HvxVQR:$Vdddd32),
36490(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36491"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rt8.b)",
36492tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36493let Inst{7-5} = 0b010;
36494let Inst{13-13} = 0b0;
36495let Inst{31-19} = 0b0001100111101;
36496let hasNewValue = 1;
36497let opNewValue = 0;
36498let isCVI = 1;
36499let DecoderNamespace = "EXT_mmvec";
36500}
36501def V6_vrmpyzcbs_rt_acc : HInst<
36502(outs HvxVQR:$Vyyyy32),
36503(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36504"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rt8.b)",
36505tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36506let Inst{7-5} = 0b001;
36507let Inst{13-13} = 0b1;
36508let Inst{31-19} = 0b0001100111000;
36509let hasNewValue = 1;
36510let opNewValue = 0;
36511let isAccumulator = 1;
36512let isCVI = 1;
36513let DecoderNamespace = "EXT_mmvec";
36514let Constraints = "$Vyyyy32 = $Vyyyy32in";
36515}
36516def V6_vrmpyzcbs_rx : HInst<
36517(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36518(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36519"$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)",
36520tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36521let Inst{7-5} = 0b010;
36522let Inst{13-13} = 0b0;
36523let Inst{31-19} = 0b0001100111100;
36524let hasNewValue = 1;
36525let opNewValue = 0;
36526let isCVI = 1;
36527let DecoderNamespace = "EXT_mmvec";
36528let Constraints = "$Rx8 = $Rx8in";
36529}
36530def V6_vrmpyzcbs_rx_acc : HInst<
36531(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36532(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36533"$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)",
36534tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36535let Inst{7-5} = 0b001;
36536let Inst{13-13} = 0b1;
36537let Inst{31-19} = 0b0001100111001;
36538let hasNewValue = 1;
36539let opNewValue = 0;
36540let isAccumulator = 1;
36541let isCVI = 1;
36542let DecoderNamespace = "EXT_mmvec";
36543let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36544}
36545def V6_vrmpyznb_rt : HInst<
36546(outs HvxVQR:$Vdddd32),
36547(ins HvxVR:$Vu32, IntRegsLow8:$Rt8),
36548"$Vdddd32.w = vr8mpyz($Vu32.n,$Rt8.b)",
36549tc_61bf7c03, TypeCVI_4SLOT_MPY>, Enc_1bd127, Requires<[UseHVXV66,UseZReg]> {
36550let Inst{7-5} = 0b000;
36551let Inst{13-13} = 0b0;
36552let Inst{31-19} = 0b0001100111111;
36553let hasNewValue = 1;
36554let opNewValue = 0;
36555let isCVI = 1;
36556let DecoderNamespace = "EXT_mmvec";
36557}
36558def V6_vrmpyznb_rt_acc : HInst<
36559(outs HvxVQR:$Vyyyy32),
36560(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rt8),
36561"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rt8.b)",
36562tc_933f2b39, TypeCVI_4SLOT_MPY>, Enc_d7bc34, Requires<[UseHVXV66,UseZReg]> {
36563let Inst{7-5} = 0b010;
36564let Inst{13-13} = 0b1;
36565let Inst{31-19} = 0b0001100111010;
36566let hasNewValue = 1;
36567let opNewValue = 0;
36568let isAccumulator = 1;
36569let isCVI = 1;
36570let DecoderNamespace = "EXT_mmvec";
36571let Constraints = "$Vyyyy32 = $Vyyyy32in";
36572}
36573def V6_vrmpyznb_rx : HInst<
36574(outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8),
36575(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36576"$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)",
36577tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> {
36578let Inst{7-5} = 0b000;
36579let Inst{13-13} = 0b0;
36580let Inst{31-19} = 0b0001100111110;
36581let hasNewValue = 1;
36582let opNewValue = 0;
36583let isCVI = 1;
36584let DecoderNamespace = "EXT_mmvec";
36585let Constraints = "$Rx8 = $Rx8in";
36586}
36587def V6_vrmpyznb_rx_acc : HInst<
36588(outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8),
36589(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in),
36590"$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)",
36591tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> {
36592let Inst{7-5} = 0b010;
36593let Inst{13-13} = 0b1;
36594let Inst{31-19} = 0b0001100111011;
36595let hasNewValue = 1;
36596let opNewValue = 0;
36597let isAccumulator = 1;
36598let isCVI = 1;
36599let DecoderNamespace = "EXT_mmvec";
36600let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in";
36601}
36602def V6_vror : HInst<
36603(outs HvxVR:$Vd32),
36604(ins HvxVR:$Vu32, IntRegs:$Rt32),
36605"$Vd32 = vror($Vu32,$Rt32)",
36606tc_6e7fa133, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> {
36607let Inst{7-5} = 0b001;
36608let Inst{13-13} = 0b0;
36609let Inst{31-21} = 0b00011001011;
36610let hasNewValue = 1;
36611let opNewValue = 0;
36612let isCVI = 1;
36613let DecoderNamespace = "EXT_mmvec";
36614}
36615def V6_vrotr : HInst<
36616(outs HvxVR:$Vd32),
36617(ins HvxVR:$Vu32, HvxVR:$Vv32),
36618"$Vd32.uw = vrotr($Vu32.uw,$Vv32.uw)",
36619tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV66]> {
36620let Inst{7-5} = 0b111;
36621let Inst{13-13} = 0b1;
36622let Inst{31-21} = 0b00011010100;
36623let hasNewValue = 1;
36624let opNewValue = 0;
36625let isCVI = 1;
36626let DecoderNamespace = "EXT_mmvec";
36627}
36628def V6_vrotr_alt : HInst<
36629(outs HvxVR:$Vd32),
36630(ins HvxVR:$Vu32, HvxVR:$Vv32),
36631"$Vd32 = vrotr($Vu32,$Vv32)",
36632PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
36633let hasNewValue = 1;
36634let opNewValue = 0;
36635let isCVI = 1;
36636let isPseudo = 1;
36637let isCodeGenOnly = 1;
36638let DecoderNamespace = "EXT_mmvec";
36639}
36640def V6_vroundhb : HInst<
36641(outs HvxVR:$Vd32),
36642(ins HvxVR:$Vu32, HvxVR:$Vv32),
36643"$Vd32.b = vround($Vu32.h,$Vv32.h):sat",
36644tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36645let Inst{7-5} = 0b110;
36646let Inst{13-13} = 0b0;
36647let Inst{31-21} = 0b00011111011;
36648let hasNewValue = 1;
36649let opNewValue = 0;
36650let isCVI = 1;
36651let DecoderNamespace = "EXT_mmvec";
36652}
36653def V6_vroundhb_alt : HInst<
36654(outs HvxVR:$Vd32),
36655(ins HvxVR:$Vu32, HvxVR:$Vv32),
36656"$Vd32 = vroundhb($Vu32,$Vv32):sat",
36657PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36658let hasNewValue = 1;
36659let opNewValue = 0;
36660let isCVI = 1;
36661let isPseudo = 1;
36662let isCodeGenOnly = 1;
36663let DecoderNamespace = "EXT_mmvec";
36664}
36665def V6_vroundhub : HInst<
36666(outs HvxVR:$Vd32),
36667(ins HvxVR:$Vu32, HvxVR:$Vv32),
36668"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat",
36669tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36670let Inst{7-5} = 0b111;
36671let Inst{13-13} = 0b0;
36672let Inst{31-21} = 0b00011111011;
36673let hasNewValue = 1;
36674let opNewValue = 0;
36675let isCVI = 1;
36676let DecoderNamespace = "EXT_mmvec";
36677}
36678def V6_vroundhub_alt : HInst<
36679(outs HvxVR:$Vd32),
36680(ins HvxVR:$Vu32, HvxVR:$Vv32),
36681"$Vd32 = vroundhub($Vu32,$Vv32):sat",
36682PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36683let hasNewValue = 1;
36684let opNewValue = 0;
36685let isCVI = 1;
36686let isPseudo = 1;
36687let isCodeGenOnly = 1;
36688let DecoderNamespace = "EXT_mmvec";
36689}
36690def V6_vrounduhub : HInst<
36691(outs HvxVR:$Vd32),
36692(ins HvxVR:$Vu32, HvxVR:$Vv32),
36693"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat",
36694tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
36695let Inst{7-5} = 0b011;
36696let Inst{13-13} = 0b0;
36697let Inst{31-21} = 0b00011111111;
36698let hasNewValue = 1;
36699let opNewValue = 0;
36700let isCVI = 1;
36701let DecoderNamespace = "EXT_mmvec";
36702}
36703def V6_vrounduhub_alt : HInst<
36704(outs HvxVR:$Vd32),
36705(ins HvxVR:$Vu32, HvxVR:$Vv32),
36706"$Vd32 = vrounduhub($Vu32,$Vv32):sat",
36707PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36708let hasNewValue = 1;
36709let opNewValue = 0;
36710let isCVI = 1;
36711let isPseudo = 1;
36712let isCodeGenOnly = 1;
36713let DecoderNamespace = "EXT_mmvec";
36714}
36715def V6_vrounduwuh : HInst<
36716(outs HvxVR:$Vd32),
36717(ins HvxVR:$Vu32, HvxVR:$Vv32),
36718"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat",
36719tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> {
36720let Inst{7-5} = 0b100;
36721let Inst{13-13} = 0b0;
36722let Inst{31-21} = 0b00011111111;
36723let hasNewValue = 1;
36724let opNewValue = 0;
36725let isCVI = 1;
36726let DecoderNamespace = "EXT_mmvec";
36727}
36728def V6_vrounduwuh_alt : HInst<
36729(outs HvxVR:$Vd32),
36730(ins HvxVR:$Vu32, HvxVR:$Vv32),
36731"$Vd32 = vrounduwuh($Vu32,$Vv32):sat",
36732PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36733let hasNewValue = 1;
36734let opNewValue = 0;
36735let isCVI = 1;
36736let isPseudo = 1;
36737let isCodeGenOnly = 1;
36738let DecoderNamespace = "EXT_mmvec";
36739}
36740def V6_vroundwh : HInst<
36741(outs HvxVR:$Vd32),
36742(ins HvxVR:$Vu32, HvxVR:$Vv32),
36743"$Vd32.h = vround($Vu32.w,$Vv32.w):sat",
36744tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36745let Inst{7-5} = 0b100;
36746let Inst{13-13} = 0b0;
36747let Inst{31-21} = 0b00011111011;
36748let hasNewValue = 1;
36749let opNewValue = 0;
36750let isCVI = 1;
36751let DecoderNamespace = "EXT_mmvec";
36752}
36753def V6_vroundwh_alt : HInst<
36754(outs HvxVR:$Vd32),
36755(ins HvxVR:$Vu32, HvxVR:$Vv32),
36756"$Vd32 = vroundwh($Vu32,$Vv32):sat",
36757PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36758let hasNewValue = 1;
36759let opNewValue = 0;
36760let isCVI = 1;
36761let isPseudo = 1;
36762let isCodeGenOnly = 1;
36763let DecoderNamespace = "EXT_mmvec";
36764}
36765def V6_vroundwuh : HInst<
36766(outs HvxVR:$Vd32),
36767(ins HvxVR:$Vu32, HvxVR:$Vv32),
36768"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat",
36769tc_05ca8cfd, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> {
36770let Inst{7-5} = 0b101;
36771let Inst{13-13} = 0b0;
36772let Inst{31-21} = 0b00011111011;
36773let hasNewValue = 1;
36774let opNewValue = 0;
36775let isCVI = 1;
36776let DecoderNamespace = "EXT_mmvec";
36777}
36778def V6_vroundwuh_alt : HInst<
36779(outs HvxVR:$Vd32),
36780(ins HvxVR:$Vu32, HvxVR:$Vv32),
36781"$Vd32 = vroundwuh($Vu32,$Vv32):sat",
36782PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36783let hasNewValue = 1;
36784let opNewValue = 0;
36785let isCVI = 1;
36786let isPseudo = 1;
36787let isCodeGenOnly = 1;
36788let DecoderNamespace = "EXT_mmvec";
36789}
36790def V6_vrsadubi : HInst<
36791(outs HvxWR:$Vdd32),
36792(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36793"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
36794tc_1ad8a370, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> {
36795let Inst{7-6} = 0b11;
36796let Inst{13-13} = 0b0;
36797let Inst{31-21} = 0b00011001010;
36798let hasNewValue = 1;
36799let opNewValue = 0;
36800let isCVI = 1;
36801let DecoderNamespace = "EXT_mmvec";
36802}
36803def V6_vrsadubi_acc : HInst<
36804(outs HvxWR:$Vxx32),
36805(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36806"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)",
36807tc_e675c45a, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> {
36808let Inst{7-6} = 0b11;
36809let Inst{13-13} = 0b1;
36810let Inst{31-21} = 0b00011001010;
36811let hasNewValue = 1;
36812let opNewValue = 0;
36813let isAccumulator = 1;
36814let isCVI = 1;
36815let DecoderNamespace = "EXT_mmvec";
36816let Constraints = "$Vxx32 = $Vxx32in";
36817}
36818def V6_vrsadubi_acc_alt : HInst<
36819(outs HvxWR:$Vxx32),
36820(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36821"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)",
36822PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36823let hasNewValue = 1;
36824let opNewValue = 0;
36825let isAccumulator = 1;
36826let isCVI = 1;
36827let isPseudo = 1;
36828let isCodeGenOnly = 1;
36829let DecoderNamespace = "EXT_mmvec";
36830let Constraints = "$Vxx32 = $Vxx32in";
36831}
36832def V6_vrsadubi_alt : HInst<
36833(outs HvxWR:$Vdd32),
36834(ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii),
36835"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)",
36836PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36837let hasNewValue = 1;
36838let opNewValue = 0;
36839let isCVI = 1;
36840let isPseudo = 1;
36841let isCodeGenOnly = 1;
36842let DecoderNamespace = "EXT_mmvec";
36843}
36844def V6_vsatdw : HInst<
36845(outs HvxVR:$Vd32),
36846(ins HvxVR:$Vu32, HvxVR:$Vv32),
36847"$Vd32.w = vsatdw($Vu32.w,$Vv32.w)",
36848tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV66]> {
36849let Inst{7-5} = 0b111;
36850let Inst{13-13} = 0b1;
36851let Inst{31-21} = 0b00011101100;
36852let hasNewValue = 1;
36853let opNewValue = 0;
36854let isCVI = 1;
36855let DecoderNamespace = "EXT_mmvec";
36856}
36857def V6_vsathub : HInst<
36858(outs HvxVR:$Vd32),
36859(ins HvxVR:$Vu32, HvxVR:$Vv32),
36860"$Vd32.ub = vsat($Vu32.h,$Vv32.h)",
36861tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36862let Inst{7-5} = 0b010;
36863let Inst{13-13} = 0b0;
36864let Inst{31-21} = 0b00011111011;
36865let hasNewValue = 1;
36866let opNewValue = 0;
36867let isCVI = 1;
36868let DecoderNamespace = "EXT_mmvec";
36869}
36870def V6_vsathub_alt : HInst<
36871(outs HvxVR:$Vd32),
36872(ins HvxVR:$Vu32, HvxVR:$Vv32),
36873"$Vd32 = vsathub($Vu32,$Vv32)",
36874PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36875let hasNewValue = 1;
36876let opNewValue = 0;
36877let isCVI = 1;
36878let isPseudo = 1;
36879let isCodeGenOnly = 1;
36880let DecoderNamespace = "EXT_mmvec";
36881}
36882def V6_vsatuwuh : HInst<
36883(outs HvxVR:$Vd32),
36884(ins HvxVR:$Vu32, HvxVR:$Vv32),
36885"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)",
36886tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
36887let Inst{7-5} = 0b110;
36888let Inst{13-13} = 0b0;
36889let Inst{31-21} = 0b00011111001;
36890let hasNewValue = 1;
36891let opNewValue = 0;
36892let isCVI = 1;
36893let DecoderNamespace = "EXT_mmvec";
36894}
36895def V6_vsatuwuh_alt : HInst<
36896(outs HvxVR:$Vd32),
36897(ins HvxVR:$Vu32, HvxVR:$Vv32),
36898"$Vd32 = vsatuwuh($Vu32,$Vv32)",
36899PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
36900let hasNewValue = 1;
36901let opNewValue = 0;
36902let isCVI = 1;
36903let isPseudo = 1;
36904let isCodeGenOnly = 1;
36905let DecoderNamespace = "EXT_mmvec";
36906}
36907def V6_vsatwh : HInst<
36908(outs HvxVR:$Vd32),
36909(ins HvxVR:$Vu32, HvxVR:$Vv32),
36910"$Vd32.h = vsat($Vu32.w,$Vv32.w)",
36911tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
36912let Inst{7-5} = 0b011;
36913let Inst{13-13} = 0b0;
36914let Inst{31-21} = 0b00011111011;
36915let hasNewValue = 1;
36916let opNewValue = 0;
36917let isCVI = 1;
36918let DecoderNamespace = "EXT_mmvec";
36919}
36920def V6_vsatwh_alt : HInst<
36921(outs HvxVR:$Vd32),
36922(ins HvxVR:$Vu32, HvxVR:$Vv32),
36923"$Vd32 = vsatwh($Vu32,$Vv32)",
36924PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36925let hasNewValue = 1;
36926let opNewValue = 0;
36927let isCVI = 1;
36928let isPseudo = 1;
36929let isCodeGenOnly = 1;
36930let DecoderNamespace = "EXT_mmvec";
36931}
36932def V6_vsb : HInst<
36933(outs HvxWR:$Vdd32),
36934(ins HvxVR:$Vu32),
36935"$Vdd32.h = vsxt($Vu32.b)",
36936tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
36937let Inst{7-5} = 0b011;
36938let Inst{13-13} = 0b0;
36939let Inst{31-16} = 0b0001111000000010;
36940let hasNewValue = 1;
36941let opNewValue = 0;
36942let isCVI = 1;
36943let DecoderNamespace = "EXT_mmvec";
36944}
36945def V6_vsb_alt : HInst<
36946(outs HvxWR:$Vdd32),
36947(ins HvxVR:$Vu32),
36948"$Vdd32 = vsxtb($Vu32)",
36949PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
36950let hasNewValue = 1;
36951let opNewValue = 0;
36952let isCVI = 1;
36953let isPseudo = 1;
36954let isCodeGenOnly = 1;
36955let DecoderNamespace = "EXT_mmvec";
36956}
36957def V6_vscattermh : HInst<
36958(outs),
36959(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36960"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
36961tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36962let Inst{7-5} = 0b001;
36963let Inst{31-21} = 0b00101111001;
36964let accessSize = HalfWordAccess;
36965let isCVI = 1;
36966let mayStore = 1;
36967let DecoderNamespace = "EXT_mmvec";
36968}
36969def V6_vscattermh_add : HInst<
36970(outs),
36971(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36972"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32",
36973tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
36974let Inst{7-5} = 0b101;
36975let Inst{31-21} = 0b00101111001;
36976let accessSize = HalfWordAccess;
36977let isAccumulator = 1;
36978let isCVI = 1;
36979let mayStore = 1;
36980let DecoderNamespace = "EXT_mmvec";
36981}
36982def V6_vscattermh_add_alt : HInst<
36983(outs),
36984(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36985"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h",
36986PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36987let isAccumulator = 1;
36988let isCVI = 1;
36989let isPseudo = 1;
36990let isCodeGenOnly = 1;
36991let DecoderNamespace = "EXT_mmvec";
36992}
36993def V6_vscattermh_alt : HInst<
36994(outs),
36995(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
36996"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
36997PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
36998let isCVI = 1;
36999let isPseudo = 1;
37000let isCodeGenOnly = 1;
37001let DecoderNamespace = "EXT_mmvec";
37002}
37003def V6_vscattermhq : HInst<
37004(outs),
37005(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37006"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32",
37007tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
37008let Inst{7-7} = 0b1;
37009let Inst{31-21} = 0b00101111100;
37010let accessSize = HalfWordAccess;
37011let isCVI = 1;
37012let mayStore = 1;
37013let DecoderNamespace = "EXT_mmvec";
37014}
37015def V6_vscattermhq_alt : HInst<
37016(outs),
37017(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37018"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h",
37019PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37020let isCVI = 1;
37021let isPseudo = 1;
37022let isCodeGenOnly = 1;
37023let DecoderNamespace = "EXT_mmvec";
37024}
37025def V6_vscattermhw : HInst<
37026(outs),
37027(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37028"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
37029tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
37030let Inst{7-5} = 0b010;
37031let Inst{31-21} = 0b00101111001;
37032let accessSize = HalfWordAccess;
37033let isCVI = 1;
37034let mayStore = 1;
37035let DecoderNamespace = "EXT_mmvec";
37036}
37037def V6_vscattermhw_add : HInst<
37038(outs),
37039(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37040"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32",
37041tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> {
37042let Inst{7-5} = 0b110;
37043let Inst{31-21} = 0b00101111001;
37044let accessSize = HalfWordAccess;
37045let isAccumulator = 1;
37046let isCVI = 1;
37047let mayStore = 1;
37048let DecoderNamespace = "EXT_mmvec";
37049}
37050def V6_vscattermhwq : HInst<
37051(outs),
37052(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37053"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32",
37054tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> {
37055let Inst{7-7} = 0b0;
37056let Inst{31-21} = 0b00101111101;
37057let accessSize = HalfWordAccess;
37058let isCVI = 1;
37059let mayStore = 1;
37060let DecoderNamespace = "EXT_mmvec";
37061}
37062def V6_vscattermw : HInst<
37063(outs),
37064(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37065"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
37066tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37067let Inst{7-5} = 0b000;
37068let Inst{31-21} = 0b00101111001;
37069let accessSize = WordAccess;
37070let isCVI = 1;
37071let mayStore = 1;
37072let DecoderNamespace = "EXT_mmvec";
37073}
37074def V6_vscattermw_add : HInst<
37075(outs),
37076(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37077"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32",
37078tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> {
37079let Inst{7-5} = 0b100;
37080let Inst{31-21} = 0b00101111001;
37081let accessSize = WordAccess;
37082let isAccumulator = 1;
37083let isCVI = 1;
37084let mayStore = 1;
37085let DecoderNamespace = "EXT_mmvec";
37086}
37087def V6_vscattermw_add_alt : HInst<
37088(outs),
37089(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37090"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w",
37091PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37092let isAccumulator = 1;
37093let isCVI = 1;
37094let isPseudo = 1;
37095let isCodeGenOnly = 1;
37096let DecoderNamespace = "EXT_mmvec";
37097}
37098def V6_vscattermw_alt : HInst<
37099(outs),
37100(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37101"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
37102PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37103let isCVI = 1;
37104let isPseudo = 1;
37105let isCodeGenOnly = 1;
37106let DecoderNamespace = "EXT_mmvec";
37107}
37108def V6_vscattermwh_add_alt : HInst<
37109(outs),
37110(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37111"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h",
37112PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37113let isAccumulator = 1;
37114let isCVI = 1;
37115let isPseudo = 1;
37116let isCodeGenOnly = 1;
37117let DecoderNamespace = "EXT_mmvec";
37118}
37119def V6_vscattermwh_alt : HInst<
37120(outs),
37121(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37122"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
37123PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37124let isCVI = 1;
37125let isPseudo = 1;
37126let isCodeGenOnly = 1;
37127let DecoderNamespace = "EXT_mmvec";
37128}
37129def V6_vscattermwhq_alt : HInst<
37130(outs),
37131(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32),
37132"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h",
37133PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37134let isCVI = 1;
37135let isPseudo = 1;
37136let isCodeGenOnly = 1;
37137let DecoderNamespace = "EXT_mmvec";
37138}
37139def V6_vscattermwq : HInst<
37140(outs),
37141(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37142"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32",
37143tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> {
37144let Inst{7-7} = 0b0;
37145let Inst{31-21} = 0b00101111100;
37146let accessSize = WordAccess;
37147let isCVI = 1;
37148let mayStore = 1;
37149let DecoderNamespace = "EXT_mmvec";
37150}
37151def V6_vscattermwq_alt : HInst<
37152(outs),
37153(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32),
37154"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w",
37155PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> {
37156let isCVI = 1;
37157let isPseudo = 1;
37158let isCodeGenOnly = 1;
37159let DecoderNamespace = "EXT_mmvec";
37160}
37161def V6_vsh : HInst<
37162(outs HvxWR:$Vdd32),
37163(ins HvxVR:$Vu32),
37164"$Vdd32.w = vsxt($Vu32.h)",
37165tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
37166let Inst{7-5} = 0b100;
37167let Inst{13-13} = 0b0;
37168let Inst{31-16} = 0b0001111000000010;
37169let hasNewValue = 1;
37170let opNewValue = 0;
37171let isCVI = 1;
37172let DecoderNamespace = "EXT_mmvec";
37173}
37174def V6_vsh_alt : HInst<
37175(outs HvxWR:$Vdd32),
37176(ins HvxVR:$Vu32),
37177"$Vdd32 = vsxth($Vu32)",
37178PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37179let hasNewValue = 1;
37180let opNewValue = 0;
37181let isCVI = 1;
37182let isPseudo = 1;
37183let isCodeGenOnly = 1;
37184let DecoderNamespace = "EXT_mmvec";
37185}
37186def V6_vshufeh : HInst<
37187(outs HvxVR:$Vd32),
37188(ins HvxVR:$Vu32, HvxVR:$Vv32),
37189"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)",
37190tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37191let Inst{7-5} = 0b011;
37192let Inst{13-13} = 0b0;
37193let Inst{31-21} = 0b00011111010;
37194let hasNewValue = 1;
37195let opNewValue = 0;
37196let isCVI = 1;
37197let DecoderNamespace = "EXT_mmvec";
37198}
37199def V6_vshufeh_alt : HInst<
37200(outs HvxVR:$Vd32),
37201(ins HvxVR:$Vu32, HvxVR:$Vv32),
37202"$Vd32 = vshuffeh($Vu32,$Vv32)",
37203PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37204let hasNewValue = 1;
37205let opNewValue = 0;
37206let isCVI = 1;
37207let isPseudo = 1;
37208let isCodeGenOnly = 1;
37209let DecoderNamespace = "EXT_mmvec";
37210}
37211def V6_vshuff : HInst<
37212(outs HvxVR:$Vy32, HvxVR:$Vx32),
37213(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
37214"vshuff($Vy32,$Vx32,$Rt32)",
37215tc_561aaa58, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> {
37216let Inst{7-5} = 0b001;
37217let Inst{13-13} = 0b1;
37218let Inst{31-21} = 0b00011001111;
37219let hasNewValue = 1;
37220let opNewValue = 0;
37221let hasNewValue2 = 1;
37222let opNewValue2 = 1;
37223let isCVI = 1;
37224let DecoderNamespace = "EXT_mmvec";
37225let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
37226}
37227def V6_vshuffb : HInst<
37228(outs HvxVR:$Vd32),
37229(ins HvxVR:$Vu32),
37230"$Vd32.b = vshuff($Vu32.b)",
37231tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
37232let Inst{7-5} = 0b000;
37233let Inst{13-13} = 0b0;
37234let Inst{31-16} = 0b0001111000000010;
37235let hasNewValue = 1;
37236let opNewValue = 0;
37237let isCVI = 1;
37238let DecoderNamespace = "EXT_mmvec";
37239}
37240def V6_vshuffb_alt : HInst<
37241(outs HvxVR:$Vd32),
37242(ins HvxVR:$Vu32),
37243"$Vd32 = vshuffb($Vu32)",
37244PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37245let hasNewValue = 1;
37246let opNewValue = 0;
37247let isCVI = 1;
37248let isPseudo = 1;
37249let isCodeGenOnly = 1;
37250let DecoderNamespace = "EXT_mmvec";
37251}
37252def V6_vshuffeb : HInst<
37253(outs HvxVR:$Vd32),
37254(ins HvxVR:$Vu32, HvxVR:$Vv32),
37255"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)",
37256tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37257let Inst{7-5} = 0b001;
37258let Inst{13-13} = 0b0;
37259let Inst{31-21} = 0b00011111010;
37260let hasNewValue = 1;
37261let opNewValue = 0;
37262let isCVI = 1;
37263let DecoderNamespace = "EXT_mmvec";
37264}
37265def V6_vshuffeb_alt : HInst<
37266(outs HvxVR:$Vd32),
37267(ins HvxVR:$Vu32, HvxVR:$Vv32),
37268"$Vd32 = vshuffeb($Vu32,$Vv32)",
37269PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37270let hasNewValue = 1;
37271let opNewValue = 0;
37272let isCVI = 1;
37273let isPseudo = 1;
37274let isCodeGenOnly = 1;
37275let DecoderNamespace = "EXT_mmvec";
37276}
37277def V6_vshuffh : HInst<
37278(outs HvxVR:$Vd32),
37279(ins HvxVR:$Vu32),
37280"$Vd32.h = vshuff($Vu32.h)",
37281tc_946013d8, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> {
37282let Inst{7-5} = 0b111;
37283let Inst{13-13} = 0b0;
37284let Inst{31-16} = 0b0001111000000001;
37285let hasNewValue = 1;
37286let opNewValue = 0;
37287let isCVI = 1;
37288let DecoderNamespace = "EXT_mmvec";
37289}
37290def V6_vshuffh_alt : HInst<
37291(outs HvxVR:$Vd32),
37292(ins HvxVR:$Vu32),
37293"$Vd32 = vshuffh($Vu32)",
37294PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37295let hasNewValue = 1;
37296let opNewValue = 0;
37297let isCVI = 1;
37298let isPseudo = 1;
37299let isCodeGenOnly = 1;
37300let DecoderNamespace = "EXT_mmvec";
37301}
37302def V6_vshuffob : HInst<
37303(outs HvxVR:$Vd32),
37304(ins HvxVR:$Vu32, HvxVR:$Vv32),
37305"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)",
37306tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37307let Inst{7-5} = 0b010;
37308let Inst{13-13} = 0b0;
37309let Inst{31-21} = 0b00011111010;
37310let hasNewValue = 1;
37311let opNewValue = 0;
37312let isCVI = 1;
37313let DecoderNamespace = "EXT_mmvec";
37314}
37315def V6_vshuffob_alt : HInst<
37316(outs HvxVR:$Vd32),
37317(ins HvxVR:$Vu32, HvxVR:$Vv32),
37318"$Vd32 = vshuffob($Vu32,$Vv32)",
37319PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37320let hasNewValue = 1;
37321let opNewValue = 0;
37322let isCVI = 1;
37323let isPseudo = 1;
37324let isCodeGenOnly = 1;
37325let DecoderNamespace = "EXT_mmvec";
37326}
37327def V6_vshuffvdd : HInst<
37328(outs HvxWR:$Vdd32),
37329(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8),
37330"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)",
37331tc_87adc037, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> {
37332let Inst{7-5} = 0b011;
37333let Inst{13-13} = 0b1;
37334let Inst{31-24} = 0b00011011;
37335let hasNewValue = 1;
37336let opNewValue = 0;
37337let isCVI = 1;
37338let DecoderNamespace = "EXT_mmvec";
37339}
37340def V6_vshufoeb : HInst<
37341(outs HvxWR:$Vdd32),
37342(ins HvxVR:$Vu32, HvxVR:$Vv32),
37343"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)",
37344tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37345let Inst{7-5} = 0b110;
37346let Inst{13-13} = 0b0;
37347let Inst{31-21} = 0b00011111010;
37348let hasNewValue = 1;
37349let opNewValue = 0;
37350let isCVI = 1;
37351let DecoderNamespace = "EXT_mmvec";
37352}
37353def V6_vshufoeb_alt : HInst<
37354(outs HvxWR:$Vdd32),
37355(ins HvxVR:$Vu32, HvxVR:$Vv32),
37356"$Vdd32 = vshuffoeb($Vu32,$Vv32)",
37357PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37358let hasNewValue = 1;
37359let opNewValue = 0;
37360let isCVI = 1;
37361let isPseudo = 1;
37362let isCodeGenOnly = 1;
37363let DecoderNamespace = "EXT_mmvec";
37364}
37365def V6_vshufoeh : HInst<
37366(outs HvxWR:$Vdd32),
37367(ins HvxVR:$Vu32, HvxVR:$Vv32),
37368"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)",
37369tc_db5555f3, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37370let Inst{7-5} = 0b101;
37371let Inst{13-13} = 0b0;
37372let Inst{31-21} = 0b00011111010;
37373let hasNewValue = 1;
37374let opNewValue = 0;
37375let isCVI = 1;
37376let DecoderNamespace = "EXT_mmvec";
37377}
37378def V6_vshufoeh_alt : HInst<
37379(outs HvxWR:$Vdd32),
37380(ins HvxVR:$Vu32, HvxVR:$Vv32),
37381"$Vdd32 = vshuffoeh($Vu32,$Vv32)",
37382PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37383let hasNewValue = 1;
37384let opNewValue = 0;
37385let isCVI = 1;
37386let isPseudo = 1;
37387let isCodeGenOnly = 1;
37388let DecoderNamespace = "EXT_mmvec";
37389}
37390def V6_vshufoh : HInst<
37391(outs HvxVR:$Vd32),
37392(ins HvxVR:$Vu32, HvxVR:$Vv32),
37393"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)",
37394tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37395let Inst{7-5} = 0b100;
37396let Inst{13-13} = 0b0;
37397let Inst{31-21} = 0b00011111010;
37398let hasNewValue = 1;
37399let opNewValue = 0;
37400let isCVI = 1;
37401let DecoderNamespace = "EXT_mmvec";
37402}
37403def V6_vshufoh_alt : HInst<
37404(outs HvxVR:$Vd32),
37405(ins HvxVR:$Vu32, HvxVR:$Vv32),
37406"$Vd32 = vshuffoh($Vu32,$Vv32)",
37407PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37408let hasNewValue = 1;
37409let opNewValue = 0;
37410let isCVI = 1;
37411let isPseudo = 1;
37412let isCodeGenOnly = 1;
37413let DecoderNamespace = "EXT_mmvec";
37414}
37415def V6_vsubb : HInst<
37416(outs HvxVR:$Vd32),
37417(ins HvxVR:$Vu32, HvxVR:$Vv32),
37418"$Vd32.b = vsub($Vu32.b,$Vv32.b)",
37419tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37420let Inst{7-5} = 0b101;
37421let Inst{13-13} = 0b0;
37422let Inst{31-21} = 0b00011100010;
37423let hasNewValue = 1;
37424let opNewValue = 0;
37425let isCVI = 1;
37426let DecoderNamespace = "EXT_mmvec";
37427}
37428def V6_vsubb_alt : HInst<
37429(outs HvxVR:$Vd32),
37430(ins HvxVR:$Vu32, HvxVR:$Vv32),
37431"$Vd32 = vsubb($Vu32,$Vv32)",
37432PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37433let hasNewValue = 1;
37434let opNewValue = 0;
37435let isCVI = 1;
37436let isPseudo = 1;
37437let isCodeGenOnly = 1;
37438let DecoderNamespace = "EXT_mmvec";
37439}
37440def V6_vsubb_dv : HInst<
37441(outs HvxWR:$Vdd32),
37442(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37443"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)",
37444tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37445let Inst{7-5} = 0b011;
37446let Inst{13-13} = 0b0;
37447let Inst{31-21} = 0b00011100100;
37448let hasNewValue = 1;
37449let opNewValue = 0;
37450let isCVI = 1;
37451let DecoderNamespace = "EXT_mmvec";
37452}
37453def V6_vsubb_dv_alt : HInst<
37454(outs HvxWR:$Vdd32),
37455(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37456"$Vdd32 = vsubb($Vuu32,$Vvv32)",
37457PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37458let hasNewValue = 1;
37459let opNewValue = 0;
37460let isCVI = 1;
37461let isPseudo = 1;
37462let isCodeGenOnly = 1;
37463let DecoderNamespace = "EXT_mmvec";
37464}
37465def V6_vsubbnq : HInst<
37466(outs HvxVR:$Vx32),
37467(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37468"if (!$Qv4) $Vx32.b -= $Vu32.b",
37469tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37470let Inst{7-5} = 0b001;
37471let Inst{13-13} = 0b1;
37472let Inst{21-16} = 0b000010;
37473let Inst{31-24} = 0b00011110;
37474let hasNewValue = 1;
37475let opNewValue = 0;
37476let isCVI = 1;
37477let DecoderNamespace = "EXT_mmvec";
37478let Constraints = "$Vx32 = $Vx32in";
37479}
37480def V6_vsubbnq_alt : HInst<
37481(outs HvxVR:$Vx32),
37482(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37483"if (!$Qv4.b) $Vx32.b -= $Vu32.b",
37484PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37485let hasNewValue = 1;
37486let opNewValue = 0;
37487let isCVI = 1;
37488let isPseudo = 1;
37489let isCodeGenOnly = 1;
37490let DecoderNamespace = "EXT_mmvec";
37491let Constraints = "$Vx32 = $Vx32in";
37492}
37493def V6_vsubbq : HInst<
37494(outs HvxVR:$Vx32),
37495(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37496"if ($Qv4) $Vx32.b -= $Vu32.b",
37497tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37498let Inst{7-5} = 0b110;
37499let Inst{13-13} = 0b1;
37500let Inst{21-16} = 0b000001;
37501let Inst{31-24} = 0b00011110;
37502let hasNewValue = 1;
37503let opNewValue = 0;
37504let isCVI = 1;
37505let DecoderNamespace = "EXT_mmvec";
37506let Constraints = "$Vx32 = $Vx32in";
37507}
37508def V6_vsubbq_alt : HInst<
37509(outs HvxVR:$Vx32),
37510(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37511"if ($Qv4.b) $Vx32.b -= $Vu32.b",
37512PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37513let hasNewValue = 1;
37514let opNewValue = 0;
37515let isCVI = 1;
37516let isPseudo = 1;
37517let isCodeGenOnly = 1;
37518let DecoderNamespace = "EXT_mmvec";
37519let Constraints = "$Vx32 = $Vx32in";
37520}
37521def V6_vsubbsat : HInst<
37522(outs HvxVR:$Vd32),
37523(ins HvxVR:$Vu32, HvxVR:$Vv32),
37524"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat",
37525tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37526let Inst{7-5} = 0b010;
37527let Inst{13-13} = 0b0;
37528let Inst{31-21} = 0b00011111001;
37529let hasNewValue = 1;
37530let opNewValue = 0;
37531let isCVI = 1;
37532let DecoderNamespace = "EXT_mmvec";
37533}
37534def V6_vsubbsat_alt : HInst<
37535(outs HvxVR:$Vd32),
37536(ins HvxVR:$Vu32, HvxVR:$Vv32),
37537"$Vd32 = vsubb($Vu32,$Vv32):sat",
37538PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37539let hasNewValue = 1;
37540let opNewValue = 0;
37541let isCVI = 1;
37542let isPseudo = 1;
37543let isCodeGenOnly = 1;
37544let DecoderNamespace = "EXT_mmvec";
37545}
37546def V6_vsubbsat_dv : HInst<
37547(outs HvxWR:$Vdd32),
37548(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37549"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat",
37550tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
37551let Inst{7-5} = 0b001;
37552let Inst{13-13} = 0b0;
37553let Inst{31-21} = 0b00011110101;
37554let hasNewValue = 1;
37555let opNewValue = 0;
37556let isCVI = 1;
37557let DecoderNamespace = "EXT_mmvec";
37558}
37559def V6_vsubbsat_dv_alt : HInst<
37560(outs HvxWR:$Vdd32),
37561(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37562"$Vdd32 = vsubb($Vuu32,$Vvv32):sat",
37563PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37564let hasNewValue = 1;
37565let opNewValue = 0;
37566let isCVI = 1;
37567let isPseudo = 1;
37568let isCodeGenOnly = 1;
37569let DecoderNamespace = "EXT_mmvec";
37570}
37571def V6_vsubcarry : HInst<
37572(outs HvxVR:$Vd32, HvxQR:$Qx4),
37573(ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in),
37574"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry",
37575tc_7e6a3e89, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> {
37576let Inst{7-7} = 0b1;
37577let Inst{13-13} = 0b1;
37578let Inst{31-21} = 0b00011100101;
37579let hasNewValue = 1;
37580let opNewValue = 0;
37581let isCVI = 1;
37582let DecoderNamespace = "EXT_mmvec";
37583let Constraints = "$Qx4 = $Qx4in";
37584}
37585def V6_vsubcarryo : HInst<
37586(outs HvxVR:$Vd32, HvxQR:$Qe4),
37587(ins HvxVR:$Vu32, HvxVR:$Vv32),
37588"$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry",
37589tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> {
37590let Inst{7-7} = 0b1;
37591let Inst{13-13} = 0b1;
37592let Inst{31-21} = 0b00011101101;
37593let hasNewValue = 1;
37594let opNewValue = 0;
37595let hasNewValue2 = 1;
37596let opNewValue2 = 1;
37597let isCVI = 1;
37598let DecoderNamespace = "EXT_mmvec";
37599}
37600def V6_vsubh : HInst<
37601(outs HvxVR:$Vd32),
37602(ins HvxVR:$Vu32, HvxVR:$Vv32),
37603"$Vd32.h = vsub($Vu32.h,$Vv32.h)",
37604tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37605let Inst{7-5} = 0b110;
37606let Inst{13-13} = 0b0;
37607let Inst{31-21} = 0b00011100010;
37608let hasNewValue = 1;
37609let opNewValue = 0;
37610let isCVI = 1;
37611let DecoderNamespace = "EXT_mmvec";
37612}
37613def V6_vsubh_alt : HInst<
37614(outs HvxVR:$Vd32),
37615(ins HvxVR:$Vu32, HvxVR:$Vv32),
37616"$Vd32 = vsubh($Vu32,$Vv32)",
37617PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37618let hasNewValue = 1;
37619let opNewValue = 0;
37620let isCVI = 1;
37621let isPseudo = 1;
37622let isCodeGenOnly = 1;
37623let DecoderNamespace = "EXT_mmvec";
37624}
37625def V6_vsubh_dv : HInst<
37626(outs HvxWR:$Vdd32),
37627(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37628"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)",
37629tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37630let Inst{7-5} = 0b100;
37631let Inst{13-13} = 0b0;
37632let Inst{31-21} = 0b00011100100;
37633let hasNewValue = 1;
37634let opNewValue = 0;
37635let isCVI = 1;
37636let DecoderNamespace = "EXT_mmvec";
37637}
37638def V6_vsubh_dv_alt : HInst<
37639(outs HvxWR:$Vdd32),
37640(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37641"$Vdd32 = vsubh($Vuu32,$Vvv32)",
37642PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37643let hasNewValue = 1;
37644let opNewValue = 0;
37645let isCVI = 1;
37646let isPseudo = 1;
37647let isCodeGenOnly = 1;
37648let DecoderNamespace = "EXT_mmvec";
37649}
37650def V6_vsubhnq : HInst<
37651(outs HvxVR:$Vx32),
37652(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37653"if (!$Qv4) $Vx32.h -= $Vu32.h",
37654tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37655let Inst{7-5} = 0b010;
37656let Inst{13-13} = 0b1;
37657let Inst{21-16} = 0b000010;
37658let Inst{31-24} = 0b00011110;
37659let hasNewValue = 1;
37660let opNewValue = 0;
37661let isCVI = 1;
37662let DecoderNamespace = "EXT_mmvec";
37663let Constraints = "$Vx32 = $Vx32in";
37664}
37665def V6_vsubhnq_alt : HInst<
37666(outs HvxVR:$Vx32),
37667(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37668"if (!$Qv4.h) $Vx32.h -= $Vu32.h",
37669PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37670let hasNewValue = 1;
37671let opNewValue = 0;
37672let isCVI = 1;
37673let isPseudo = 1;
37674let isCodeGenOnly = 1;
37675let DecoderNamespace = "EXT_mmvec";
37676let Constraints = "$Vx32 = $Vx32in";
37677}
37678def V6_vsubhq : HInst<
37679(outs HvxVR:$Vx32),
37680(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37681"if ($Qv4) $Vx32.h -= $Vu32.h",
37682tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
37683let Inst{7-5} = 0b111;
37684let Inst{13-13} = 0b1;
37685let Inst{21-16} = 0b000001;
37686let Inst{31-24} = 0b00011110;
37687let hasNewValue = 1;
37688let opNewValue = 0;
37689let isCVI = 1;
37690let DecoderNamespace = "EXT_mmvec";
37691let Constraints = "$Vx32 = $Vx32in";
37692}
37693def V6_vsubhq_alt : HInst<
37694(outs HvxVR:$Vx32),
37695(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
37696"if ($Qv4.h) $Vx32.h -= $Vu32.h",
37697PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37698let hasNewValue = 1;
37699let opNewValue = 0;
37700let isCVI = 1;
37701let isPseudo = 1;
37702let isCodeGenOnly = 1;
37703let DecoderNamespace = "EXT_mmvec";
37704let Constraints = "$Vx32 = $Vx32in";
37705}
37706def V6_vsubhsat : HInst<
37707(outs HvxVR:$Vd32),
37708(ins HvxVR:$Vu32, HvxVR:$Vv32),
37709"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat",
37710tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37711let Inst{7-5} = 0b010;
37712let Inst{13-13} = 0b0;
37713let Inst{31-21} = 0b00011100011;
37714let hasNewValue = 1;
37715let opNewValue = 0;
37716let isCVI = 1;
37717let DecoderNamespace = "EXT_mmvec";
37718}
37719def V6_vsubhsat_alt : HInst<
37720(outs HvxVR:$Vd32),
37721(ins HvxVR:$Vu32, HvxVR:$Vv32),
37722"$Vd32 = vsubh($Vu32,$Vv32):sat",
37723PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37724let hasNewValue = 1;
37725let opNewValue = 0;
37726let isCVI = 1;
37727let isPseudo = 1;
37728let isCodeGenOnly = 1;
37729let DecoderNamespace = "EXT_mmvec";
37730}
37731def V6_vsubhsat_dv : HInst<
37732(outs HvxWR:$Vdd32),
37733(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37734"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat",
37735tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37736let Inst{7-5} = 0b000;
37737let Inst{13-13} = 0b0;
37738let Inst{31-21} = 0b00011100101;
37739let hasNewValue = 1;
37740let opNewValue = 0;
37741let isCVI = 1;
37742let DecoderNamespace = "EXT_mmvec";
37743}
37744def V6_vsubhsat_dv_alt : HInst<
37745(outs HvxWR:$Vdd32),
37746(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37747"$Vdd32 = vsubh($Vuu32,$Vvv32):sat",
37748PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37749let hasNewValue = 1;
37750let opNewValue = 0;
37751let isCVI = 1;
37752let isPseudo = 1;
37753let isCodeGenOnly = 1;
37754let DecoderNamespace = "EXT_mmvec";
37755}
37756def V6_vsubhw : HInst<
37757(outs HvxWR:$Vdd32),
37758(ins HvxVR:$Vu32, HvxVR:$Vv32),
37759"$Vdd32.w = vsub($Vu32.h,$Vv32.h)",
37760tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37761let Inst{7-5} = 0b111;
37762let Inst{13-13} = 0b0;
37763let Inst{31-21} = 0b00011100101;
37764let hasNewValue = 1;
37765let opNewValue = 0;
37766let isCVI = 1;
37767let DecoderNamespace = "EXT_mmvec";
37768}
37769def V6_vsubhw_alt : HInst<
37770(outs HvxWR:$Vdd32),
37771(ins HvxVR:$Vu32, HvxVR:$Vv32),
37772"$Vdd32 = vsubh($Vu32,$Vv32)",
37773PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37774let hasNewValue = 1;
37775let opNewValue = 0;
37776let isCVI = 1;
37777let isPseudo = 1;
37778let isCodeGenOnly = 1;
37779let DecoderNamespace = "EXT_mmvec";
37780}
37781def V6_vsububh : HInst<
37782(outs HvxWR:$Vdd32),
37783(ins HvxVR:$Vu32, HvxVR:$Vv32),
37784"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)",
37785tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37786let Inst{7-5} = 0b101;
37787let Inst{13-13} = 0b0;
37788let Inst{31-21} = 0b00011100101;
37789let hasNewValue = 1;
37790let opNewValue = 0;
37791let isCVI = 1;
37792let DecoderNamespace = "EXT_mmvec";
37793}
37794def V6_vsububh_alt : HInst<
37795(outs HvxWR:$Vdd32),
37796(ins HvxVR:$Vu32, HvxVR:$Vv32),
37797"$Vdd32 = vsubub($Vu32,$Vv32)",
37798PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37799let hasNewValue = 1;
37800let opNewValue = 0;
37801let isCVI = 1;
37802let isPseudo = 1;
37803let isCodeGenOnly = 1;
37804let DecoderNamespace = "EXT_mmvec";
37805}
37806def V6_vsububsat : HInst<
37807(outs HvxVR:$Vd32),
37808(ins HvxVR:$Vu32, HvxVR:$Vv32),
37809"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat",
37810tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37811let Inst{7-5} = 0b000;
37812let Inst{13-13} = 0b0;
37813let Inst{31-21} = 0b00011100011;
37814let hasNewValue = 1;
37815let opNewValue = 0;
37816let isCVI = 1;
37817let DecoderNamespace = "EXT_mmvec";
37818}
37819def V6_vsububsat_alt : HInst<
37820(outs HvxVR:$Vd32),
37821(ins HvxVR:$Vu32, HvxVR:$Vv32),
37822"$Vd32 = vsubub($Vu32,$Vv32):sat",
37823PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37824let hasNewValue = 1;
37825let opNewValue = 0;
37826let isCVI = 1;
37827let isPseudo = 1;
37828let isCodeGenOnly = 1;
37829let DecoderNamespace = "EXT_mmvec";
37830}
37831def V6_vsububsat_dv : HInst<
37832(outs HvxWR:$Vdd32),
37833(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37834"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat",
37835tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37836let Inst{7-5} = 0b110;
37837let Inst{13-13} = 0b0;
37838let Inst{31-21} = 0b00011100100;
37839let hasNewValue = 1;
37840let opNewValue = 0;
37841let isCVI = 1;
37842let DecoderNamespace = "EXT_mmvec";
37843}
37844def V6_vsububsat_dv_alt : HInst<
37845(outs HvxWR:$Vdd32),
37846(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37847"$Vdd32 = vsubub($Vuu32,$Vvv32):sat",
37848PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37849let hasNewValue = 1;
37850let opNewValue = 0;
37851let isCVI = 1;
37852let isPseudo = 1;
37853let isCodeGenOnly = 1;
37854let DecoderNamespace = "EXT_mmvec";
37855}
37856def V6_vsubububb_sat : HInst<
37857(outs HvxVR:$Vd32),
37858(ins HvxVR:$Vu32, HvxVR:$Vv32),
37859"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat",
37860tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37861let Inst{7-5} = 0b101;
37862let Inst{13-13} = 0b0;
37863let Inst{31-21} = 0b00011110101;
37864let hasNewValue = 1;
37865let opNewValue = 0;
37866let isCVI = 1;
37867let DecoderNamespace = "EXT_mmvec";
37868}
37869def V6_vsubuhsat : HInst<
37870(outs HvxVR:$Vd32),
37871(ins HvxVR:$Vu32, HvxVR:$Vv32),
37872"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat",
37873tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37874let Inst{7-5} = 0b001;
37875let Inst{13-13} = 0b0;
37876let Inst{31-21} = 0b00011100011;
37877let hasNewValue = 1;
37878let opNewValue = 0;
37879let isCVI = 1;
37880let DecoderNamespace = "EXT_mmvec";
37881}
37882def V6_vsubuhsat_alt : HInst<
37883(outs HvxVR:$Vd32),
37884(ins HvxVR:$Vu32, HvxVR:$Vv32),
37885"$Vd32 = vsubuh($Vu32,$Vv32):sat",
37886PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37887let hasNewValue = 1;
37888let opNewValue = 0;
37889let isCVI = 1;
37890let isPseudo = 1;
37891let isCodeGenOnly = 1;
37892let DecoderNamespace = "EXT_mmvec";
37893}
37894def V6_vsubuhsat_dv : HInst<
37895(outs HvxWR:$Vdd32),
37896(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37897"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat",
37898tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
37899let Inst{7-5} = 0b111;
37900let Inst{13-13} = 0b0;
37901let Inst{31-21} = 0b00011100100;
37902let hasNewValue = 1;
37903let opNewValue = 0;
37904let isCVI = 1;
37905let DecoderNamespace = "EXT_mmvec";
37906}
37907def V6_vsubuhsat_dv_alt : HInst<
37908(outs HvxWR:$Vdd32),
37909(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37910"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat",
37911PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37912let hasNewValue = 1;
37913let opNewValue = 0;
37914let isCVI = 1;
37915let isPseudo = 1;
37916let isCodeGenOnly = 1;
37917let DecoderNamespace = "EXT_mmvec";
37918}
37919def V6_vsubuhw : HInst<
37920(outs HvxWR:$Vdd32),
37921(ins HvxVR:$Vu32, HvxVR:$Vv32),
37922"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)",
37923tc_d8287c14, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> {
37924let Inst{7-5} = 0b110;
37925let Inst{13-13} = 0b0;
37926let Inst{31-21} = 0b00011100101;
37927let hasNewValue = 1;
37928let opNewValue = 0;
37929let isCVI = 1;
37930let DecoderNamespace = "EXT_mmvec";
37931}
37932def V6_vsubuhw_alt : HInst<
37933(outs HvxWR:$Vdd32),
37934(ins HvxVR:$Vu32, HvxVR:$Vv32),
37935"$Vdd32 = vsubuh($Vu32,$Vv32)",
37936PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
37937let hasNewValue = 1;
37938let opNewValue = 0;
37939let isCVI = 1;
37940let isPseudo = 1;
37941let isCodeGenOnly = 1;
37942let DecoderNamespace = "EXT_mmvec";
37943}
37944def V6_vsubuwsat : HInst<
37945(outs HvxVR:$Vd32),
37946(ins HvxVR:$Vu32, HvxVR:$Vv32),
37947"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat",
37948tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> {
37949let Inst{7-5} = 0b100;
37950let Inst{13-13} = 0b0;
37951let Inst{31-21} = 0b00011111110;
37952let hasNewValue = 1;
37953let opNewValue = 0;
37954let isCVI = 1;
37955let DecoderNamespace = "EXT_mmvec";
37956}
37957def V6_vsubuwsat_alt : HInst<
37958(outs HvxVR:$Vd32),
37959(ins HvxVR:$Vu32, HvxVR:$Vv32),
37960"$Vd32 = vsubuw($Vu32,$Vv32):sat",
37961PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37962let hasNewValue = 1;
37963let opNewValue = 0;
37964let isCVI = 1;
37965let isPseudo = 1;
37966let isCodeGenOnly = 1;
37967let DecoderNamespace = "EXT_mmvec";
37968}
37969def V6_vsubuwsat_dv : HInst<
37970(outs HvxWR:$Vdd32),
37971(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37972"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat",
37973tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> {
37974let Inst{7-5} = 0b011;
37975let Inst{13-13} = 0b0;
37976let Inst{31-21} = 0b00011110101;
37977let hasNewValue = 1;
37978let opNewValue = 0;
37979let isCVI = 1;
37980let DecoderNamespace = "EXT_mmvec";
37981}
37982def V6_vsubuwsat_dv_alt : HInst<
37983(outs HvxWR:$Vdd32),
37984(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
37985"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat",
37986PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> {
37987let hasNewValue = 1;
37988let opNewValue = 0;
37989let isCVI = 1;
37990let isPseudo = 1;
37991let isCodeGenOnly = 1;
37992let DecoderNamespace = "EXT_mmvec";
37993}
37994def V6_vsubw : HInst<
37995(outs HvxVR:$Vd32),
37996(ins HvxVR:$Vu32, HvxVR:$Vv32),
37997"$Vd32.w = vsub($Vu32.w,$Vv32.w)",
37998tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
37999let Inst{7-5} = 0b111;
38000let Inst{13-13} = 0b0;
38001let Inst{31-21} = 0b00011100010;
38002let hasNewValue = 1;
38003let opNewValue = 0;
38004let isCVI = 1;
38005let DecoderNamespace = "EXT_mmvec";
38006}
38007def V6_vsubw_alt : HInst<
38008(outs HvxVR:$Vd32),
38009(ins HvxVR:$Vu32, HvxVR:$Vv32),
38010"$Vd32 = vsubw($Vu32,$Vv32)",
38011PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38012let hasNewValue = 1;
38013let opNewValue = 0;
38014let isCVI = 1;
38015let isPseudo = 1;
38016let isCodeGenOnly = 1;
38017let DecoderNamespace = "EXT_mmvec";
38018}
38019def V6_vsubw_dv : HInst<
38020(outs HvxWR:$Vdd32),
38021(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38022"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)",
38023tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38024let Inst{7-5} = 0b101;
38025let Inst{13-13} = 0b0;
38026let Inst{31-21} = 0b00011100100;
38027let hasNewValue = 1;
38028let opNewValue = 0;
38029let isCVI = 1;
38030let DecoderNamespace = "EXT_mmvec";
38031}
38032def V6_vsubw_dv_alt : HInst<
38033(outs HvxWR:$Vdd32),
38034(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38035"$Vdd32 = vsubw($Vuu32,$Vvv32)",
38036PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38037let hasNewValue = 1;
38038let opNewValue = 0;
38039let isCVI = 1;
38040let isPseudo = 1;
38041let isCodeGenOnly = 1;
38042let DecoderNamespace = "EXT_mmvec";
38043}
38044def V6_vsubwnq : HInst<
38045(outs HvxVR:$Vx32),
38046(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38047"if (!$Qv4) $Vx32.w -= $Vu32.w",
38048tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38049let Inst{7-5} = 0b011;
38050let Inst{13-13} = 0b1;
38051let Inst{21-16} = 0b000010;
38052let Inst{31-24} = 0b00011110;
38053let hasNewValue = 1;
38054let opNewValue = 0;
38055let isCVI = 1;
38056let DecoderNamespace = "EXT_mmvec";
38057let Constraints = "$Vx32 = $Vx32in";
38058}
38059def V6_vsubwnq_alt : HInst<
38060(outs HvxVR:$Vx32),
38061(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38062"if (!$Qv4.w) $Vx32.w -= $Vu32.w",
38063PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38064let hasNewValue = 1;
38065let opNewValue = 0;
38066let isCVI = 1;
38067let isPseudo = 1;
38068let isCodeGenOnly = 1;
38069let DecoderNamespace = "EXT_mmvec";
38070let Constraints = "$Vx32 = $Vx32in";
38071}
38072def V6_vsubwq : HInst<
38073(outs HvxVR:$Vx32),
38074(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38075"if ($Qv4) $Vx32.w -= $Vu32.w",
38076tc_257f6f7c, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> {
38077let Inst{7-5} = 0b000;
38078let Inst{13-13} = 0b1;
38079let Inst{21-16} = 0b000010;
38080let Inst{31-24} = 0b00011110;
38081let hasNewValue = 1;
38082let opNewValue = 0;
38083let isCVI = 1;
38084let DecoderNamespace = "EXT_mmvec";
38085let Constraints = "$Vx32 = $Vx32in";
38086}
38087def V6_vsubwq_alt : HInst<
38088(outs HvxVR:$Vx32),
38089(ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32),
38090"if ($Qv4.w) $Vx32.w -= $Vu32.w",
38091PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38092let hasNewValue = 1;
38093let opNewValue = 0;
38094let isCVI = 1;
38095let isPseudo = 1;
38096let isCodeGenOnly = 1;
38097let DecoderNamespace = "EXT_mmvec";
38098let Constraints = "$Vx32 = $Vx32in";
38099}
38100def V6_vsubwsat : HInst<
38101(outs HvxVR:$Vd32),
38102(ins HvxVR:$Vu32, HvxVR:$Vv32),
38103"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat",
38104tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38105let Inst{7-5} = 0b011;
38106let Inst{13-13} = 0b0;
38107let Inst{31-21} = 0b00011100011;
38108let hasNewValue = 1;
38109let opNewValue = 0;
38110let isCVI = 1;
38111let DecoderNamespace = "EXT_mmvec";
38112}
38113def V6_vsubwsat_alt : HInst<
38114(outs HvxVR:$Vd32),
38115(ins HvxVR:$Vu32, HvxVR:$Vv32),
38116"$Vd32 = vsubw($Vu32,$Vv32):sat",
38117PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38118let hasNewValue = 1;
38119let opNewValue = 0;
38120let isCVI = 1;
38121let isPseudo = 1;
38122let isCodeGenOnly = 1;
38123let DecoderNamespace = "EXT_mmvec";
38124}
38125def V6_vsubwsat_dv : HInst<
38126(outs HvxWR:$Vdd32),
38127(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38128"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat",
38129tc_db5555f3, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> {
38130let Inst{7-5} = 0b001;
38131let Inst{13-13} = 0b0;
38132let Inst{31-21} = 0b00011100101;
38133let hasNewValue = 1;
38134let opNewValue = 0;
38135let isCVI = 1;
38136let DecoderNamespace = "EXT_mmvec";
38137}
38138def V6_vsubwsat_dv_alt : HInst<
38139(outs HvxWR:$Vdd32),
38140(ins HvxWR:$Vuu32, HvxWR:$Vvv32),
38141"$Vdd32 = vsubw($Vuu32,$Vvv32):sat",
38142PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38143let hasNewValue = 1;
38144let opNewValue = 0;
38145let isCVI = 1;
38146let isPseudo = 1;
38147let isCodeGenOnly = 1;
38148let DecoderNamespace = "EXT_mmvec";
38149}
38150def V6_vswap : HInst<
38151(outs HvxWR:$Vdd32),
38152(ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32),
38153"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)",
38154tc_71646d06, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> {
38155let Inst{7-7} = 0b0;
38156let Inst{13-13} = 0b1;
38157let Inst{31-21} = 0b00011110101;
38158let hasNewValue = 1;
38159let opNewValue = 0;
38160let isCVI = 1;
38161let DecoderNamespace = "EXT_mmvec";
38162}
38163def V6_vtmpyb : HInst<
38164(outs HvxWR:$Vdd32),
38165(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38166"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)",
38167tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
38168let Inst{7-5} = 0b000;
38169let Inst{13-13} = 0b0;
38170let Inst{31-21} = 0b00011001000;
38171let hasNewValue = 1;
38172let opNewValue = 0;
38173let isCVI = 1;
38174let DecoderNamespace = "EXT_mmvec";
38175}
38176def V6_vtmpyb_acc : HInst<
38177(outs HvxWR:$Vxx32),
38178(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38179"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)",
38180tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
38181let Inst{7-5} = 0b000;
38182let Inst{13-13} = 0b1;
38183let Inst{31-21} = 0b00011001000;
38184let hasNewValue = 1;
38185let opNewValue = 0;
38186let isAccumulator = 1;
38187let isCVI = 1;
38188let DecoderNamespace = "EXT_mmvec";
38189let Constraints = "$Vxx32 = $Vxx32in";
38190}
38191def V6_vtmpyb_acc_alt : HInst<
38192(outs HvxWR:$Vxx32),
38193(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38194"$Vxx32 += vtmpyb($Vuu32,$Rt32)",
38195PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38196let hasNewValue = 1;
38197let opNewValue = 0;
38198let isAccumulator = 1;
38199let isCVI = 1;
38200let isPseudo = 1;
38201let isCodeGenOnly = 1;
38202let DecoderNamespace = "EXT_mmvec";
38203let Constraints = "$Vxx32 = $Vxx32in";
38204}
38205def V6_vtmpyb_alt : HInst<
38206(outs HvxWR:$Vdd32),
38207(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38208"$Vdd32 = vtmpyb($Vuu32,$Rt32)",
38209PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38210let hasNewValue = 1;
38211let opNewValue = 0;
38212let isCVI = 1;
38213let isPseudo = 1;
38214let isCodeGenOnly = 1;
38215let DecoderNamespace = "EXT_mmvec";
38216}
38217def V6_vtmpybus : HInst<
38218(outs HvxWR:$Vdd32),
38219(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38220"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)",
38221tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
38222let Inst{7-5} = 0b001;
38223let Inst{13-13} = 0b0;
38224let Inst{31-21} = 0b00011001000;
38225let hasNewValue = 1;
38226let opNewValue = 0;
38227let isCVI = 1;
38228let DecoderNamespace = "EXT_mmvec";
38229}
38230def V6_vtmpybus_acc : HInst<
38231(outs HvxWR:$Vxx32),
38232(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38233"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)",
38234tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
38235let Inst{7-5} = 0b001;
38236let Inst{13-13} = 0b1;
38237let Inst{31-21} = 0b00011001000;
38238let hasNewValue = 1;
38239let opNewValue = 0;
38240let isAccumulator = 1;
38241let isCVI = 1;
38242let DecoderNamespace = "EXT_mmvec";
38243let Constraints = "$Vxx32 = $Vxx32in";
38244}
38245def V6_vtmpybus_acc_alt : HInst<
38246(outs HvxWR:$Vxx32),
38247(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38248"$Vxx32 += vtmpybus($Vuu32,$Rt32)",
38249PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38250let hasNewValue = 1;
38251let opNewValue = 0;
38252let isAccumulator = 1;
38253let isCVI = 1;
38254let isPseudo = 1;
38255let isCodeGenOnly = 1;
38256let DecoderNamespace = "EXT_mmvec";
38257let Constraints = "$Vxx32 = $Vxx32in";
38258}
38259def V6_vtmpybus_alt : HInst<
38260(outs HvxWR:$Vdd32),
38261(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38262"$Vdd32 = vtmpybus($Vuu32,$Rt32)",
38263PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38264let hasNewValue = 1;
38265let opNewValue = 0;
38266let isCVI = 1;
38267let isPseudo = 1;
38268let isCodeGenOnly = 1;
38269let DecoderNamespace = "EXT_mmvec";
38270}
38271def V6_vtmpyhb : HInst<
38272(outs HvxWR:$Vdd32),
38273(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38274"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)",
38275tc_0b04c6c7, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> {
38276let Inst{7-5} = 0b100;
38277let Inst{13-13} = 0b0;
38278let Inst{31-21} = 0b00011001101;
38279let hasNewValue = 1;
38280let opNewValue = 0;
38281let isCVI = 1;
38282let DecoderNamespace = "EXT_mmvec";
38283}
38284def V6_vtmpyhb_acc : HInst<
38285(outs HvxWR:$Vxx32),
38286(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38287"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)",
38288tc_660769f1, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> {
38289let Inst{7-5} = 0b010;
38290let Inst{13-13} = 0b1;
38291let Inst{31-21} = 0b00011001000;
38292let hasNewValue = 1;
38293let opNewValue = 0;
38294let isAccumulator = 1;
38295let isCVI = 1;
38296let DecoderNamespace = "EXT_mmvec";
38297let Constraints = "$Vxx32 = $Vxx32in";
38298}
38299def V6_vtmpyhb_acc_alt : HInst<
38300(outs HvxWR:$Vxx32),
38301(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32),
38302"$Vxx32 += vtmpyhb($Vuu32,$Rt32)",
38303PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38304let hasNewValue = 1;
38305let opNewValue = 0;
38306let isAccumulator = 1;
38307let isCVI = 1;
38308let isPseudo = 1;
38309let isCodeGenOnly = 1;
38310let DecoderNamespace = "EXT_mmvec";
38311let Constraints = "$Vxx32 = $Vxx32in";
38312}
38313def V6_vtmpyhb_alt : HInst<
38314(outs HvxWR:$Vdd32),
38315(ins HvxWR:$Vuu32, IntRegs:$Rt32),
38316"$Vdd32 = vtmpyhb($Vuu32,$Rt32)",
38317PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38318let hasNewValue = 1;
38319let opNewValue = 0;
38320let isCVI = 1;
38321let isPseudo = 1;
38322let isCodeGenOnly = 1;
38323let DecoderNamespace = "EXT_mmvec";
38324}
38325def V6_vtran2x2_map : HInst<
38326(outs HvxVR:$Vy32, HvxVR:$Vx32),
38327(ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32),
38328"vtrans2x2($Vy32,$Vx32,$Rt32)",
38329PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38330let hasNewValue = 1;
38331let opNewValue = 0;
38332let hasNewValue2 = 1;
38333let opNewValue2 = 1;
38334let isCVI = 1;
38335let isPseudo = 1;
38336let isCodeGenOnly = 1;
38337let DecoderNamespace = "EXT_mmvec";
38338let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in";
38339}
38340def V6_vunpackb : HInst<
38341(outs HvxWR:$Vdd32),
38342(ins HvxVR:$Vu32),
38343"$Vdd32.h = vunpack($Vu32.b)",
38344tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38345let Inst{7-5} = 0b010;
38346let Inst{13-13} = 0b0;
38347let Inst{31-16} = 0b0001111000000001;
38348let hasNewValue = 1;
38349let opNewValue = 0;
38350let isCVI = 1;
38351let DecoderNamespace = "EXT_mmvec";
38352}
38353def V6_vunpackb_alt : HInst<
38354(outs HvxWR:$Vdd32),
38355(ins HvxVR:$Vu32),
38356"$Vdd32 = vunpackb($Vu32)",
38357PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38358let hasNewValue = 1;
38359let opNewValue = 0;
38360let isCVI = 1;
38361let isPseudo = 1;
38362let isCodeGenOnly = 1;
38363let DecoderNamespace = "EXT_mmvec";
38364}
38365def V6_vunpackh : HInst<
38366(outs HvxWR:$Vdd32),
38367(ins HvxVR:$Vu32),
38368"$Vdd32.w = vunpack($Vu32.h)",
38369tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38370let Inst{7-5} = 0b011;
38371let Inst{13-13} = 0b0;
38372let Inst{31-16} = 0b0001111000000001;
38373let hasNewValue = 1;
38374let opNewValue = 0;
38375let isCVI = 1;
38376let DecoderNamespace = "EXT_mmvec";
38377}
38378def V6_vunpackh_alt : HInst<
38379(outs HvxWR:$Vdd32),
38380(ins HvxVR:$Vu32),
38381"$Vdd32 = vunpackh($Vu32)",
38382PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38383let hasNewValue = 1;
38384let opNewValue = 0;
38385let isCVI = 1;
38386let isPseudo = 1;
38387let isCodeGenOnly = 1;
38388let DecoderNamespace = "EXT_mmvec";
38389}
38390def V6_vunpackob : HInst<
38391(outs HvxWR:$Vxx32),
38392(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38393"$Vxx32.h |= vunpacko($Vu32.b)",
38394tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
38395let Inst{7-5} = 0b000;
38396let Inst{13-13} = 0b1;
38397let Inst{31-16} = 0b0001111000000000;
38398let hasNewValue = 1;
38399let opNewValue = 0;
38400let isAccumulator = 1;
38401let isCVI = 1;
38402let DecoderNamespace = "EXT_mmvec";
38403let Constraints = "$Vxx32 = $Vxx32in";
38404}
38405def V6_vunpackob_alt : HInst<
38406(outs HvxWR:$Vxx32),
38407(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38408"$Vxx32 |= vunpackob($Vu32)",
38409PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38410let hasNewValue = 1;
38411let opNewValue = 0;
38412let isAccumulator = 1;
38413let isCVI = 1;
38414let isPseudo = 1;
38415let DecoderNamespace = "EXT_mmvec";
38416let Constraints = "$Vxx32 = $Vxx32in";
38417}
38418def V6_vunpackoh : HInst<
38419(outs HvxWR:$Vxx32),
38420(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38421"$Vxx32.w |= vunpacko($Vu32.h)",
38422tc_2c745bb8, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> {
38423let Inst{7-5} = 0b001;
38424let Inst{13-13} = 0b1;
38425let Inst{31-16} = 0b0001111000000000;
38426let hasNewValue = 1;
38427let opNewValue = 0;
38428let isAccumulator = 1;
38429let isCVI = 1;
38430let DecoderNamespace = "EXT_mmvec";
38431let Constraints = "$Vxx32 = $Vxx32in";
38432}
38433def V6_vunpackoh_alt : HInst<
38434(outs HvxWR:$Vxx32),
38435(ins HvxWR:$Vxx32in, HvxVR:$Vu32),
38436"$Vxx32 |= vunpackoh($Vu32)",
38437PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38438let hasNewValue = 1;
38439let opNewValue = 0;
38440let isAccumulator = 1;
38441let isCVI = 1;
38442let isPseudo = 1;
38443let isCodeGenOnly = 1;
38444let DecoderNamespace = "EXT_mmvec";
38445let Constraints = "$Vxx32 = $Vxx32in";
38446}
38447def V6_vunpackub : HInst<
38448(outs HvxWR:$Vdd32),
38449(ins HvxVR:$Vu32),
38450"$Vdd32.uh = vunpack($Vu32.ub)",
38451tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38452let Inst{7-5} = 0b000;
38453let Inst{13-13} = 0b0;
38454let Inst{31-16} = 0b0001111000000001;
38455let hasNewValue = 1;
38456let opNewValue = 0;
38457let isCVI = 1;
38458let DecoderNamespace = "EXT_mmvec";
38459}
38460def V6_vunpackub_alt : HInst<
38461(outs HvxWR:$Vdd32),
38462(ins HvxVR:$Vu32),
38463"$Vdd32 = vunpackub($Vu32)",
38464PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38465let hasNewValue = 1;
38466let opNewValue = 0;
38467let isCVI = 1;
38468let isPseudo = 1;
38469let isCodeGenOnly = 1;
38470let DecoderNamespace = "EXT_mmvec";
38471}
38472def V6_vunpackuh : HInst<
38473(outs HvxWR:$Vdd32),
38474(ins HvxVR:$Vu32),
38475"$Vdd32.uw = vunpack($Vu32.uh)",
38476tc_04da405a, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> {
38477let Inst{7-5} = 0b001;
38478let Inst{13-13} = 0b0;
38479let Inst{31-16} = 0b0001111000000001;
38480let hasNewValue = 1;
38481let opNewValue = 0;
38482let isCVI = 1;
38483let DecoderNamespace = "EXT_mmvec";
38484}
38485def V6_vunpackuh_alt : HInst<
38486(outs HvxWR:$Vdd32),
38487(ins HvxVR:$Vu32),
38488"$Vdd32 = vunpackuh($Vu32)",
38489PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38490let hasNewValue = 1;
38491let opNewValue = 0;
38492let isCVI = 1;
38493let isPseudo = 1;
38494let isCodeGenOnly = 1;
38495let DecoderNamespace = "EXT_mmvec";
38496}
38497def V6_vwhist128 : HInst<
38498(outs),
38499(ins),
38500"vwhist128",
38501tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38502let Inst{13-0} = 0b10010010000000;
38503let Inst{31-16} = 0b0001111000000000;
38504let isCVI = 1;
38505let DecoderNamespace = "EXT_mmvec";
38506}
38507def V6_vwhist128m : HInst<
38508(outs),
38509(ins u1_0Imm:$Ii),
38510"vwhist128(#$Ii)",
38511tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> {
38512let Inst{7-0} = 0b10000000;
38513let Inst{13-9} = 0b10011;
38514let Inst{31-16} = 0b0001111000000000;
38515let isCVI = 1;
38516let DecoderNamespace = "EXT_mmvec";
38517}
38518def V6_vwhist128q : HInst<
38519(outs),
38520(ins HvxQR:$Qv4),
38521"vwhist128($Qv4)",
38522tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38523let Inst{13-0} = 0b10010010000000;
38524let Inst{21-16} = 0b000010;
38525let Inst{31-24} = 0b00011110;
38526let isCVI = 1;
38527let DecoderNamespace = "EXT_mmvec";
38528}
38529def V6_vwhist128qm : HInst<
38530(outs),
38531(ins HvxQR:$Qv4, u1_0Imm:$Ii),
38532"vwhist128($Qv4,#$Ii)",
38533tc_767c4e9d, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> {
38534let Inst{7-0} = 0b10000000;
38535let Inst{13-9} = 0b10011;
38536let Inst{21-16} = 0b000010;
38537let Inst{31-24} = 0b00011110;
38538let isCVI = 1;
38539let DecoderNamespace = "EXT_mmvec";
38540}
38541def V6_vwhist256 : HInst<
38542(outs),
38543(ins),
38544"vwhist256",
38545tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38546let Inst{13-0} = 0b10001010000000;
38547let Inst{31-16} = 0b0001111000000000;
38548let isCVI = 1;
38549let DecoderNamespace = "EXT_mmvec";
38550}
38551def V6_vwhist256_sat : HInst<
38552(outs),
38553(ins),
38554"vwhist256:sat",
38555tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> {
38556let Inst{13-0} = 0b10001110000000;
38557let Inst{31-16} = 0b0001111000000000;
38558let isCVI = 1;
38559let DecoderNamespace = "EXT_mmvec";
38560}
38561def V6_vwhist256q : HInst<
38562(outs),
38563(ins HvxQR:$Qv4),
38564"vwhist256($Qv4)",
38565tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38566let Inst{13-0} = 0b10001010000000;
38567let Inst{21-16} = 0b000010;
38568let Inst{31-24} = 0b00011110;
38569let isCVI = 1;
38570let DecoderNamespace = "EXT_mmvec";
38571}
38572def V6_vwhist256q_sat : HInst<
38573(outs),
38574(ins HvxQR:$Qv4),
38575"vwhist256($Qv4):sat",
38576tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> {
38577let Inst{13-0} = 0b10001110000000;
38578let Inst{21-16} = 0b000010;
38579let Inst{31-24} = 0b00011110;
38580let isCVI = 1;
38581let DecoderNamespace = "EXT_mmvec";
38582}
38583def V6_vxor : HInst<
38584(outs HvxVR:$Vd32),
38585(ins HvxVR:$Vu32, HvxVR:$Vv32),
38586"$Vd32 = vxor($Vu32,$Vv32)",
38587tc_56c4f9fe, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> {
38588let Inst{7-5} = 0b111;
38589let Inst{13-13} = 0b0;
38590let Inst{31-21} = 0b00011100001;
38591let hasNewValue = 1;
38592let opNewValue = 0;
38593let isCVI = 1;
38594let DecoderNamespace = "EXT_mmvec";
38595}
38596def V6_vzb : HInst<
38597(outs HvxWR:$Vdd32),
38598(ins HvxVR:$Vu32),
38599"$Vdd32.uh = vzxt($Vu32.ub)",
38600tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38601let Inst{7-5} = 0b001;
38602let Inst{13-13} = 0b0;
38603let Inst{31-16} = 0b0001111000000010;
38604let hasNewValue = 1;
38605let opNewValue = 0;
38606let isCVI = 1;
38607let DecoderNamespace = "EXT_mmvec";
38608}
38609def V6_vzb_alt : HInst<
38610(outs HvxWR:$Vdd32),
38611(ins HvxVR:$Vu32),
38612"$Vdd32 = vzxtb($Vu32)",
38613PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38614let hasNewValue = 1;
38615let opNewValue = 0;
38616let isCVI = 1;
38617let isPseudo = 1;
38618let isCodeGenOnly = 1;
38619let DecoderNamespace = "EXT_mmvec";
38620}
38621def V6_vzh : HInst<
38622(outs HvxWR:$Vdd32),
38623(ins HvxVR:$Vu32),
38624"$Vdd32.uw = vzxt($Vu32.uh)",
38625tc_b4416217, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> {
38626let Inst{7-5} = 0b010;
38627let Inst{13-13} = 0b0;
38628let Inst{31-16} = 0b0001111000000010;
38629let hasNewValue = 1;
38630let opNewValue = 0;
38631let isCVI = 1;
38632let DecoderNamespace = "EXT_mmvec";
38633}
38634def V6_vzh_alt : HInst<
38635(outs HvxWR:$Vdd32),
38636(ins HvxVR:$Vu32),
38637"$Vdd32 = vzxth($Vu32)",
38638PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> {
38639let hasNewValue = 1;
38640let opNewValue = 0;
38641let isCVI = 1;
38642let isPseudo = 1;
38643let isCodeGenOnly = 1;
38644let DecoderNamespace = "EXT_mmvec";
38645}
38646def V6_zLd_ai : HInst<
38647(outs),
38648(ins IntRegs:$Rt32, s4_0Imm:$Ii),
38649"z = vmem($Rt32+#$Ii)",
38650tc_e699ae41, TypeCVI_ZW>, Enc_ff3442, Requires<[UseHVXV66,UseZReg]> {
38651let Inst{7-0} = 0b00000000;
38652let Inst{12-11} = 0b00;
38653let Inst{31-21} = 0b00101100000;
38654let addrMode = BaseImmOffset;
38655let isCVI = 1;
38656let mayLoad = 1;
38657let isRestrictNoSlot1Store = 1;
38658let DecoderNamespace = "EXT_mmvec";
38659}
38660def V6_zLd_pi : HInst<
38661(outs IntRegs:$Rx32),
38662(ins IntRegs:$Rx32in, s3_0Imm:$Ii),
38663"z = vmem($Rx32++#$Ii)",
38664tc_a0dbea28, TypeCVI_ZW>, Enc_6c9ee0, Requires<[UseHVXV66,UseZReg]> {
38665let Inst{7-0} = 0b00000000;
38666let Inst{13-11} = 0b000;
38667let Inst{31-21} = 0b00101101000;
38668let addrMode = PostInc;
38669let isCVI = 1;
38670let mayLoad = 1;
38671let isRestrictNoSlot1Store = 1;
38672let DecoderNamespace = "EXT_mmvec";
38673let Constraints = "$Rx32 = $Rx32in";
38674}
38675def V6_zLd_ppu : HInst<
38676(outs IntRegs:$Rx32),
38677(ins IntRegs:$Rx32in, ModRegs:$Mu2),
38678"z = vmem($Rx32++$Mu2)",
38679tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> {
38680let Inst{12-0} = 0b0000000000001;
38681let Inst{31-21} = 0b00101101000;
38682let addrMode = PostInc;
38683let isCVI = 1;
38684let mayLoad = 1;
38685let isRestrictNoSlot1Store = 1;
38686let DecoderNamespace = "EXT_mmvec";
38687let Constraints = "$Rx32 = $Rx32in";
38688}
38689def V6_zLd_pred_ai : HInst<
38690(outs),
38691(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii),
38692"if ($Pv4) z = vmem($Rt32+#$Ii)",
38693tc_dd5b0695, TypeCVI_ZW>, Enc_ef601b, Requires<[UseHVXV66,UseZReg]> {
38694let Inst{7-0} = 0b00000000;
38695let Inst{31-21} = 0b00101100100;
38696let isPredicated = 1;
38697let addrMode = BaseImmOffset;
38698let isCVI = 1;
38699let mayLoad = 1;
38700let isRestrictNoSlot1Store = 1;
38701let DecoderNamespace = "EXT_mmvec";
38702}
38703def V6_zLd_pred_pi : HInst<
38704(outs IntRegs:$Rx32),
38705(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii),
38706"if ($Pv4) z = vmem($Rx32++#$Ii)",
38707tc_3ad719fb, TypeCVI_ZW>, Enc_6baed4, Requires<[UseHVXV66,UseZReg]> {
38708let Inst{7-0} = 0b00000000;
38709let Inst{13-13} = 0b0;
38710let Inst{31-21} = 0b00101101100;
38711let isPredicated = 1;
38712let addrMode = PostInc;
38713let isCVI = 1;
38714let mayLoad = 1;
38715let isRestrictNoSlot1Store = 1;
38716let DecoderNamespace = "EXT_mmvec";
38717let Constraints = "$Rx32 = $Rx32in";
38718}
38719def V6_zLd_pred_ppu : HInst<
38720(outs IntRegs:$Rx32),
38721(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2),
38722"if ($Pv4) z = vmem($Rx32++$Mu2)",
38723tc_3ad719fb, TypeCVI_ZW>, Enc_691712, Requires<[UseHVXV66,UseZReg]> {
38724let Inst{10-0} = 0b00000000001;
38725let Inst{31-21} = 0b00101101100;
38726let isPredicated = 1;
38727let addrMode = PostInc;
38728let isCVI = 1;
38729let mayLoad = 1;
38730let isRestrictNoSlot1Store = 1;
38731let DecoderNamespace = "EXT_mmvec";
38732let Constraints = "$Rx32 = $Rx32in";
38733}
38734def V6_zextract : HInst<
38735(outs HvxVR:$Vd32),
38736(ins IntRegs:$Rt32),
38737"$Vd32 = zextract($Rt32)",
38738tc_5bf8afbb, TypeCVI_VP>, Enc_a5ed8a, Requires<[UseHVXV66,UseZReg]> {
38739let Inst{13-5} = 0b000001001;
38740let Inst{31-21} = 0b00011001101;
38741let hasNewValue = 1;
38742let opNewValue = 0;
38743let isCVI = 1;
38744let DecoderNamespace = "EXT_mmvec";
38745}
38746def V6_zld0 : HInst<
38747(outs),
38748(ins IntRegs:$Rt32),
38749"z = vmem($Rt32)",
38750PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38751let isCVI = 1;
38752let isPseudo = 1;
38753let isCodeGenOnly = 1;
38754let DecoderNamespace = "EXT_mmvec";
38755}
38756def V6_zldp0 : HInst<
38757(outs),
38758(ins PredRegs:$Pv4, IntRegs:$Rt32),
38759"if ($Pv4) z = vmem($Rt32)",
38760PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> {
38761let isCVI = 1;
38762let isPseudo = 1;
38763let isCodeGenOnly = 1;
38764let DecoderNamespace = "EXT_mmvec";
38765}
38766def Y2_barrier : HInst<
38767(outs),
38768(ins),
38769"barrier",
38770tc_77f94a5e, TypeST>, Enc_e3b0c4 {
38771let Inst{13-0} = 0b00000000000000;
38772let Inst{31-16} = 0b1010100000000000;
38773let isSoloAX = 1;
38774let hasSideEffects = 1;
38775}
38776def Y2_break : HInst<
38777(outs),
38778(ins),
38779"brkpt",
38780tc_55255f2b, TypeCR>, Enc_e3b0c4 {
38781let Inst{13-0} = 0b00000000000000;
38782let Inst{31-16} = 0b0110110000100000;
38783let isSolo = 1;
38784}
38785def Y2_dccleana : HInst<
38786(outs),
38787(ins IntRegs:$Rs32),
38788"dccleana($Rs32)",
38789tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38790let Inst{13-0} = 0b00000000000000;
38791let Inst{31-21} = 0b10100000000;
38792let isRestrictSlot1AOK = 1;
38793let hasSideEffects = 1;
38794}
38795def Y2_dccleaninva : HInst<
38796(outs),
38797(ins IntRegs:$Rs32),
38798"dccleaninva($Rs32)",
38799tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38800let Inst{13-0} = 0b00000000000000;
38801let Inst{31-21} = 0b10100000010;
38802let isRestrictSlot1AOK = 1;
38803let hasSideEffects = 1;
38804}
38805def Y2_dcfetch : HInst<
38806(outs),
38807(ins IntRegs:$Rs32),
38808"dcfetch($Rs32)",
38809tc_d45ba9cd, TypeMAPPING> {
38810let hasSideEffects = 1;
38811let isPseudo = 1;
38812let isCodeGenOnly = 1;
38813}
38814def Y2_dcfetchbo : HInst<
38815(outs),
38816(ins IntRegs:$Rs32, u11_3Imm:$Ii),
38817"dcfetch($Rs32+#$Ii)",
38818tc_2237d952, TypeLD>, Enc_2d829e {
38819let Inst{13-11} = 0b000;
38820let Inst{31-21} = 0b10010100000;
38821let addrMode = BaseImmOffset;
38822let isRestrictNoSlot1Store = 1;
38823let hasSideEffects = 1;
38824}
38825def Y2_dcinva : HInst<
38826(outs),
38827(ins IntRegs:$Rs32),
38828"dcinva($Rs32)",
38829tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38830let Inst{13-0} = 0b00000000000000;
38831let Inst{31-21} = 0b10100000001;
38832let isRestrictSlot1AOK = 1;
38833let hasSideEffects = 1;
38834}
38835def Y2_dczeroa : HInst<
38836(outs),
38837(ins IntRegs:$Rs32),
38838"dczeroa($Rs32)",
38839tc_b1ae5f67, TypeST>, Enc_ecbcc8 {
38840let Inst{13-0} = 0b00000000000000;
38841let Inst{31-21} = 0b10100000110;
38842let isRestrictSlot1AOK = 1;
38843let mayStore = 1;
38844let hasSideEffects = 1;
38845}
38846def Y2_icinva : HInst<
38847(outs),
38848(ins IntRegs:$Rs32),
38849"icinva($Rs32)",
38850tc_0ba0d5da, TypeJ>, Enc_ecbcc8 {
38851let Inst{13-0} = 0b00000000000000;
38852let Inst{31-21} = 0b01010110110;
38853let isSolo = 1;
38854}
38855def Y2_isync : HInst<
38856(outs),
38857(ins),
38858"isync",
38859tc_9b34f5e0, TypeJ>, Enc_e3b0c4 {
38860let Inst{13-0} = 0b00000000000010;
38861let Inst{31-16} = 0b0101011111000000;
38862let isSolo = 1;
38863}
38864def Y2_syncht : HInst<
38865(outs),
38866(ins),
38867"syncht",
38868tc_77f94a5e, TypeST>, Enc_e3b0c4 {
38869let Inst{13-0} = 0b00000000000000;
38870let Inst{31-16} = 0b1010100001000000;
38871let isSolo = 1;
38872}
38873def Y2_wait : HInst<
38874(outs),
38875(ins IntRegs:$Rs32),
38876"wait($Rs32)",
38877tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> {
38878let Inst{13-0} = 0b00000000000000;
38879let Inst{31-21} = 0b01100100010;
38880let isSolo = 1;
38881}
38882def Y4_l2fetch : HInst<
38883(outs),
38884(ins IntRegs:$Rs32, IntRegs:$Rt32),
38885"l2fetch($Rs32,$Rt32)",
38886tc_a3070909, TypeST>, Enc_ca3887 {
38887let Inst{7-0} = 0b00000000;
38888let Inst{13-13} = 0b0;
38889let Inst{31-21} = 0b10100110000;
38890let isSoloAX = 1;
38891let hasSideEffects = 1;
38892let mayStore = 1;
38893}
38894def Y4_trace : HInst<
38895(outs),
38896(ins IntRegs:$Rs32),
38897"trace($Rs32)",
38898tc_d7718fbe, TypeCR>, Enc_ecbcc8 {
38899let Inst{13-0} = 0b00000000000000;
38900let Inst{31-21} = 0b01100010010;
38901let isSoloAX = 1;
38902}
38903def Y5_l2fetch : HInst<
38904(outs),
38905(ins IntRegs:$Rs32, DoubleRegs:$Rtt32),
38906"l2fetch($Rs32,$Rtt32)",
38907tc_a3070909, TypeST>, Enc_e6abcf {
38908let Inst{7-0} = 0b00000000;
38909let Inst{13-13} = 0b0;
38910let Inst{31-21} = 0b10100110100;
38911let isSoloAX = 1;
38912let hasSideEffects = 1;
38913let mayStore = 1;
38914}
38915def Y6_diag : HInst<
38916(outs),
38917(ins IntRegs:$Rs32),
38918"diag($Rs32)",
38919tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> {
38920let Inst{13-0} = 0b00000000100000;
38921let Inst{31-21} = 0b01100010010;
38922}
38923def Y6_diag0 : HInst<
38924(outs),
38925(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
38926"diag0($Rss32,$Rtt32)",
38927tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
38928let Inst{7-0} = 0b01000000;
38929let Inst{13-13} = 0b0;
38930let Inst{31-21} = 0b01100010010;
38931}
38932def Y6_diag1 : HInst<
38933(outs),
38934(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32),
38935"diag1($Rss32,$Rtt32)",
38936tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> {
38937let Inst{7-0} = 0b01100000;
38938let Inst{13-13} = 0b0;
38939let Inst{31-21} = 0b01100010010;
38940}
38941def Y6_dmlink : HInst<
38942(outs),
38943(ins IntRegs:$Rs32, IntRegs:$Rt32),
38944"dmlink($Rs32,$Rt32)",
38945tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> {
38946let Inst{7-0} = 0b01000000;
38947let Inst{13-13} = 0b0;
38948let Inst{31-21} = 0b10100110000;
38949let hasSideEffects = 1;
38950let isSolo = 1;
38951let mayStore = 1;
38952}
38953def Y6_dmpause : HInst<
38954(outs IntRegs:$Rd32),
38955(ins),
38956"$Rd32 = dmpause",
38957tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
38958let Inst{13-5} = 0b000000011;
38959let Inst{31-16} = 0b1010100000000000;
38960let hasNewValue = 1;
38961let opNewValue = 0;
38962let hasSideEffects = 1;
38963let isSolo = 1;
38964}
38965def Y6_dmpoll : HInst<
38966(outs IntRegs:$Rd32),
38967(ins),
38968"$Rd32 = dmpoll",
38969tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
38970let Inst{13-5} = 0b000000010;
38971let Inst{31-16} = 0b1010100000000000;
38972let hasNewValue = 1;
38973let opNewValue = 0;
38974let hasSideEffects = 1;
38975let isSolo = 1;
38976}
38977def Y6_dmresume : HInst<
38978(outs),
38979(ins IntRegs:$Rs32),
38980"dmresume($Rs32)",
38981tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
38982let Inst{13-0} = 0b00000010000000;
38983let Inst{31-21} = 0b10100110000;
38984let hasSideEffects = 1;
38985let isSolo = 1;
38986}
38987def Y6_dmstart : HInst<
38988(outs),
38989(ins IntRegs:$Rs32),
38990"dmstart($Rs32)",
38991tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> {
38992let Inst{13-0} = 0b00000000100000;
38993let Inst{31-21} = 0b10100110000;
38994let hasSideEffects = 1;
38995let isSolo = 1;
38996}
38997def Y6_dmwait : HInst<
38998(outs IntRegs:$Rd32),
38999(ins),
39000"$Rd32 = dmwait",
39001tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> {
39002let Inst{13-5} = 0b000000001;
39003let Inst{31-16} = 0b1010100000000000;
39004let hasNewValue = 1;
39005let opNewValue = 0;
39006let hasSideEffects = 1;
39007let isSolo = 1;
39008}
39009def dep_A2_addsat : HInst<
39010(outs IntRegs:$Rd32),
39011(ins IntRegs:$Rs32, IntRegs:$Rt32),
39012"$Rd32 = add($Rs32,$Rt32):sat:deprecated",
39013tc_8a825db2, TypeALU64>, Enc_5ab2be {
39014let Inst{7-5} = 0b000;
39015let Inst{13-13} = 0b0;
39016let Inst{31-21} = 0b11010101100;
39017let hasNewValue = 1;
39018let opNewValue = 0;
39019let prefersSlot3 = 1;
39020let Defs = [USR_OVF];
39021}
39022def dep_A2_subsat : HInst<
39023(outs IntRegs:$Rd32),
39024(ins IntRegs:$Rt32, IntRegs:$Rs32),
39025"$Rd32 = sub($Rt32,$Rs32):sat:deprecated",
39026tc_8a825db2, TypeALU64>, Enc_bd6011 {
39027let Inst{7-5} = 0b100;
39028let Inst{13-13} = 0b0;
39029let Inst{31-21} = 0b11010101100;
39030let hasNewValue = 1;
39031let opNewValue = 0;
39032let prefersSlot3 = 1;
39033let Defs = [USR_OVF];
39034}
39035def dep_S2_packhl : HInst<
39036(outs DoubleRegs:$Rdd32),
39037(ins IntRegs:$Rs32, IntRegs:$Rt32),
39038"$Rdd32 = packhl($Rs32,$Rt32):deprecated",
39039tc_5da50c4b, TypeALU64>, Enc_be32a5 {
39040let Inst{7-5} = 0b000;
39041let Inst{13-13} = 0b0;
39042let Inst{31-21} = 0b11010100000;
39043}
39044def dup_A2_add : HInst<
39045(outs IntRegs:$Rd32),
39046(ins IntRegs:$Rs32, IntRegs:$Rt32),
39047"$Rd32 = add($Rs32,$Rt32)",
39048tc_388f9897, TypeALU32_3op>, Requires<[HasV68]> {
39049let hasNewValue = 1;
39050let opNewValue = 0;
39051let AsmVariantName = "NonParsable";
39052let isPseudo = 1;
39053}
39054def dup_A2_addi : HInst<
39055(outs IntRegs:$Rd32),
39056(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39057"$Rd32 = add($Rs32,#$Ii)",
39058tc_388f9897, TypeALU32_ADDI>, Requires<[HasV68]> {
39059let hasNewValue = 1;
39060let opNewValue = 0;
39061let AsmVariantName = "NonParsable";
39062let isPseudo = 1;
39063let isExtendable = 1;
39064let opExtendable = 2;
39065let isExtentSigned = 1;
39066let opExtentBits = 16;
39067let opExtentAlign = 0;
39068}
39069def dup_A2_andir : HInst<
39070(outs IntRegs:$Rd32),
39071(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39072"$Rd32 = and($Rs32,#$Ii)",
39073tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39074let hasNewValue = 1;
39075let opNewValue = 0;
39076let AsmVariantName = "NonParsable";
39077let isPseudo = 1;
39078let isExtendable = 1;
39079let opExtendable = 2;
39080let isExtentSigned = 1;
39081let opExtentBits = 10;
39082let opExtentAlign = 0;
39083}
39084def dup_A2_combineii : HInst<
39085(outs DoubleRegs:$Rdd32),
39086(ins s32_0Imm:$Ii, s8_0Imm:$II),
39087"$Rdd32 = combine(#$Ii,#$II)",
39088tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39089let AsmVariantName = "NonParsable";
39090let isPseudo = 1;
39091let isExtendable = 1;
39092let opExtendable = 1;
39093let isExtentSigned = 1;
39094let opExtentBits = 8;
39095let opExtentAlign = 0;
39096}
39097def dup_A2_sxtb : HInst<
39098(outs IntRegs:$Rd32),
39099(ins IntRegs:$Rs32),
39100"$Rd32 = sxtb($Rs32)",
39101tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> {
39102let hasNewValue = 1;
39103let opNewValue = 0;
39104let AsmVariantName = "NonParsable";
39105let isPseudo = 1;
39106}
39107def dup_A2_sxth : HInst<
39108(outs IntRegs:$Rd32),
39109(ins IntRegs:$Rs32),
39110"$Rd32 = sxth($Rs32)",
39111tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> {
39112let hasNewValue = 1;
39113let opNewValue = 0;
39114let AsmVariantName = "NonParsable";
39115let isPseudo = 1;
39116}
39117def dup_A2_tfr : HInst<
39118(outs IntRegs:$Rd32),
39119(ins IntRegs:$Rs32),
39120"$Rd32 = $Rs32",
39121tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> {
39122let hasNewValue = 1;
39123let opNewValue = 0;
39124let AsmVariantName = "NonParsable";
39125let isPseudo = 1;
39126}
39127def dup_A2_tfrsi : HInst<
39128(outs IntRegs:$Rd32),
39129(ins s32_0Imm:$Ii),
39130"$Rd32 = #$Ii",
39131tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> {
39132let hasNewValue = 1;
39133let opNewValue = 0;
39134let AsmVariantName = "NonParsable";
39135let isPseudo = 1;
39136let isExtendable = 1;
39137let opExtendable = 1;
39138let isExtentSigned = 1;
39139let opExtentBits = 16;
39140let opExtentAlign = 0;
39141}
39142def dup_A2_zxtb : HInst<
39143(outs IntRegs:$Rd32),
39144(ins IntRegs:$Rs32),
39145"$Rd32 = zxtb($Rs32)",
39146PSEUDO, TypeMAPPING>, Requires<[HasV68]> {
39147let hasNewValue = 1;
39148let opNewValue = 0;
39149let AsmVariantName = "NonParsable";
39150let isPseudo = 1;
39151}
39152def dup_A2_zxth : HInst<
39153(outs IntRegs:$Rd32),
39154(ins IntRegs:$Rs32),
39155"$Rd32 = zxth($Rs32)",
39156tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> {
39157let hasNewValue = 1;
39158let opNewValue = 0;
39159let AsmVariantName = "NonParsable";
39160let isPseudo = 1;
39161}
39162def dup_A4_combineii : HInst<
39163(outs DoubleRegs:$Rdd32),
39164(ins s8_0Imm:$Ii, u32_0Imm:$II),
39165"$Rdd32 = combine(#$Ii,#$II)",
39166tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39167let AsmVariantName = "NonParsable";
39168let isPseudo = 1;
39169let isExtendable = 1;
39170let opExtendable = 2;
39171let isExtentSigned = 0;
39172let opExtentBits = 6;
39173let opExtentAlign = 0;
39174}
39175def dup_A4_combineir : HInst<
39176(outs DoubleRegs:$Rdd32),
39177(ins s32_0Imm:$Ii, IntRegs:$Rs32),
39178"$Rdd32 = combine(#$Ii,$Rs32)",
39179tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39180let AsmVariantName = "NonParsable";
39181let isPseudo = 1;
39182let isExtendable = 1;
39183let opExtendable = 1;
39184let isExtentSigned = 1;
39185let opExtentBits = 8;
39186let opExtentAlign = 0;
39187}
39188def dup_A4_combineri : HInst<
39189(outs DoubleRegs:$Rdd32),
39190(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39191"$Rdd32 = combine($Rs32,#$Ii)",
39192tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39193let AsmVariantName = "NonParsable";
39194let isPseudo = 1;
39195let isExtendable = 1;
39196let opExtendable = 2;
39197let isExtentSigned = 1;
39198let opExtentBits = 8;
39199let opExtentAlign = 0;
39200}
39201def dup_C2_cmoveif : HInst<
39202(outs IntRegs:$Rd32),
39203(ins PredRegs:$Pu4, s32_0Imm:$Ii),
39204"if (!$Pu4) $Rd32 = #$Ii",
39205tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39206let isPredicated = 1;
39207let isPredicatedFalse = 1;
39208let hasNewValue = 1;
39209let opNewValue = 0;
39210let AsmVariantName = "NonParsable";
39211let isPseudo = 1;
39212let isExtendable = 1;
39213let opExtendable = 2;
39214let isExtentSigned = 1;
39215let opExtentBits = 12;
39216let opExtentAlign = 0;
39217}
39218def dup_C2_cmoveit : HInst<
39219(outs IntRegs:$Rd32),
39220(ins PredRegs:$Pu4, s32_0Imm:$Ii),
39221"if ($Pu4) $Rd32 = #$Ii",
39222tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39223let isPredicated = 1;
39224let hasNewValue = 1;
39225let opNewValue = 0;
39226let AsmVariantName = "NonParsable";
39227let isPseudo = 1;
39228let isExtendable = 1;
39229let opExtendable = 2;
39230let isExtentSigned = 1;
39231let opExtentBits = 12;
39232let opExtentAlign = 0;
39233}
39234def dup_C2_cmovenewif : HInst<
39235(outs IntRegs:$Rd32),
39236(ins PredRegs:$Pu4, s32_0Imm:$Ii),
39237"if (!$Pu4.new) $Rd32 = #$Ii",
39238tc_4ac61d92, TypeALU32_2op>, Requires<[HasV68]> {
39239let isPredicated = 1;
39240let isPredicatedFalse = 1;
39241let hasNewValue = 1;
39242let opNewValue = 0;
39243let AsmVariantName = "NonParsable";
39244let isPredicatedNew = 1;
39245let isPseudo = 1;
39246let isExtendable = 1;
39247let opExtendable = 2;
39248let isExtentSigned = 1;
39249let opExtentBits = 12;
39250let opExtentAlign = 0;
39251}
39252def dup_C2_cmovenewit : HInst<
39253(outs IntRegs:$Rd32),
39254(ins PredRegs:$Pu4, s32_0Imm:$Ii),
39255"if ($Pu4.new) $Rd32 = #$Ii",
39256tc_4ac61d92, TypeALU32_2op>, Requires<[HasV68]> {
39257let isPredicated = 1;
39258let hasNewValue = 1;
39259let opNewValue = 0;
39260let AsmVariantName = "NonParsable";
39261let isPredicatedNew = 1;
39262let isPseudo = 1;
39263let isExtendable = 1;
39264let opExtendable = 2;
39265let isExtentSigned = 1;
39266let opExtentBits = 12;
39267let opExtentAlign = 0;
39268}
39269def dup_C2_cmpeqi : HInst<
39270(outs PredRegs:$Pd4),
39271(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39272"$Pd4 = cmp.eq($Rs32,#$Ii)",
39273tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> {
39274let AsmVariantName = "NonParsable";
39275let isPseudo = 1;
39276let isExtendable = 1;
39277let opExtendable = 2;
39278let isExtentSigned = 1;
39279let opExtentBits = 10;
39280let opExtentAlign = 0;
39281}
39282def dup_L2_deallocframe : HInst<
39283(outs DoubleRegs:$Rdd32),
39284(ins IntRegs:$Rs32),
39285"$Rdd32 = deallocframe($Rs32):raw",
39286tc_aee6250c, TypeLD>, Requires<[HasV68]> {
39287let accessSize = DoubleWordAccess;
39288let AsmVariantName = "NonParsable";
39289let mayLoad = 1;
39290let Uses = [FRAMEKEY];
39291let Defs = [R29];
39292let isPseudo = 1;
39293}
39294def dup_L2_loadrb_io : HInst<
39295(outs IntRegs:$Rd32),
39296(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39297"$Rd32 = memb($Rs32+#$Ii)",
39298tc_eed07714, TypeLD>, Requires<[HasV68]> {
39299let hasNewValue = 1;
39300let opNewValue = 0;
39301let addrMode = BaseImmOffset;
39302let accessSize = ByteAccess;
39303let AsmVariantName = "NonParsable";
39304let mayLoad = 1;
39305let isPseudo = 1;
39306let isExtendable = 1;
39307let opExtendable = 2;
39308let isExtentSigned = 1;
39309let opExtentBits = 11;
39310let opExtentAlign = 0;
39311}
39312def dup_L2_loadrd_io : HInst<
39313(outs DoubleRegs:$Rdd32),
39314(ins IntRegs:$Rs32, s29_3Imm:$Ii),
39315"$Rdd32 = memd($Rs32+#$Ii)",
39316tc_eed07714, TypeLD>, Requires<[HasV68]> {
39317let addrMode = BaseImmOffset;
39318let accessSize = DoubleWordAccess;
39319let AsmVariantName = "NonParsable";
39320let mayLoad = 1;
39321let isPseudo = 1;
39322let isExtendable = 1;
39323let opExtendable = 2;
39324let isExtentSigned = 1;
39325let opExtentBits = 14;
39326let opExtentAlign = 3;
39327}
39328def dup_L2_loadrh_io : HInst<
39329(outs IntRegs:$Rd32),
39330(ins IntRegs:$Rs32, s31_1Imm:$Ii),
39331"$Rd32 = memh($Rs32+#$Ii)",
39332tc_eed07714, TypeLD>, Requires<[HasV68]> {
39333let hasNewValue = 1;
39334let opNewValue = 0;
39335let addrMode = BaseImmOffset;
39336let accessSize = HalfWordAccess;
39337let AsmVariantName = "NonParsable";
39338let mayLoad = 1;
39339let isPseudo = 1;
39340let isExtendable = 1;
39341let opExtendable = 2;
39342let isExtentSigned = 1;
39343let opExtentBits = 12;
39344let opExtentAlign = 1;
39345}
39346def dup_L2_loadri_io : HInst<
39347(outs IntRegs:$Rd32),
39348(ins IntRegs:$Rs32, s30_2Imm:$Ii),
39349"$Rd32 = memw($Rs32+#$Ii)",
39350tc_eed07714, TypeLD>, Requires<[HasV68]> {
39351let hasNewValue = 1;
39352let opNewValue = 0;
39353let addrMode = BaseImmOffset;
39354let accessSize = WordAccess;
39355let AsmVariantName = "NonParsable";
39356let mayLoad = 1;
39357let isPseudo = 1;
39358let isExtendable = 1;
39359let opExtendable = 2;
39360let isExtentSigned = 1;
39361let opExtentBits = 13;
39362let opExtentAlign = 2;
39363}
39364def dup_L2_loadrub_io : HInst<
39365(outs IntRegs:$Rd32),
39366(ins IntRegs:$Rs32, s32_0Imm:$Ii),
39367"$Rd32 = memub($Rs32+#$Ii)",
39368tc_eed07714, TypeLD>, Requires<[HasV68]> {
39369let hasNewValue = 1;
39370let opNewValue = 0;
39371let addrMode = BaseImmOffset;
39372let accessSize = ByteAccess;
39373let AsmVariantName = "NonParsable";
39374let mayLoad = 1;
39375let isPseudo = 1;
39376let isExtendable = 1;
39377let opExtendable = 2;
39378let isExtentSigned = 1;
39379let opExtentBits = 11;
39380let opExtentAlign = 0;
39381}
39382def dup_L2_loadruh_io : HInst<
39383(outs IntRegs:$Rd32),
39384(ins IntRegs:$Rs32, s31_1Imm:$Ii),
39385"$Rd32 = memuh($Rs32+#$Ii)",
39386tc_eed07714, TypeLD>, Requires<[HasV68]> {
39387let hasNewValue = 1;
39388let opNewValue = 0;
39389let addrMode = BaseImmOffset;
39390let accessSize = HalfWordAccess;
39391let AsmVariantName = "NonParsable";
39392let mayLoad = 1;
39393let isPseudo = 1;
39394let isExtendable = 1;
39395let opExtendable = 2;
39396let isExtentSigned = 1;
39397let opExtentBits = 12;
39398let opExtentAlign = 1;
39399}
39400def dup_S2_allocframe : HInst<
39401(outs IntRegs:$Rx32),
39402(ins IntRegs:$Rx32in, u11_3Imm:$Ii),
39403"allocframe($Rx32,#$Ii):raw",
39404tc_74a42bda, TypeST>, Requires<[HasV68]> {
39405let hasNewValue = 1;
39406let opNewValue = 0;
39407let addrMode = BaseImmOffset;
39408let accessSize = DoubleWordAccess;
39409let AsmVariantName = "NonParsable";
39410let mayStore = 1;
39411let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31];
39412let Defs = [R30];
39413let isPseudo = 1;
39414let Constraints = "$Rx32 = $Rx32in";
39415}
39416def dup_S2_storerb_io : HInst<
39417(outs),
39418(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32),
39419"memb($Rs32+#$Ii) = $Rt32",
39420tc_a9edeffa, TypeST>, Requires<[HasV68]> {
39421let addrMode = BaseImmOffset;
39422let accessSize = ByteAccess;
39423let AsmVariantName = "NonParsable";
39424let mayStore = 1;
39425let isPseudo = 1;
39426let isExtendable = 1;
39427let opExtendable = 1;
39428let isExtentSigned = 1;
39429let opExtentBits = 11;
39430let opExtentAlign = 0;
39431}
39432def dup_S2_storerd_io : HInst<
39433(outs),
39434(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32),
39435"memd($Rs32+#$Ii) = $Rtt32",
39436tc_a9edeffa, TypeST>, Requires<[HasV68]> {
39437let addrMode = BaseImmOffset;
39438let accessSize = DoubleWordAccess;
39439let AsmVariantName = "NonParsable";
39440let mayStore = 1;
39441let isPseudo = 1;
39442let isExtendable = 1;
39443let opExtendable = 1;
39444let isExtentSigned = 1;
39445let opExtentBits = 14;
39446let opExtentAlign = 3;
39447}
39448def dup_S2_storerh_io : HInst<
39449(outs),
39450(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32),
39451"memh($Rs32+#$Ii) = $Rt32",
39452tc_a9edeffa, TypeST>, Requires<[HasV68]> {
39453let addrMode = BaseImmOffset;
39454let accessSize = HalfWordAccess;
39455let AsmVariantName = "NonParsable";
39456let mayStore = 1;
39457let isPseudo = 1;
39458let isExtendable = 1;
39459let opExtendable = 1;
39460let isExtentSigned = 1;
39461let opExtentBits = 12;
39462let opExtentAlign = 1;
39463}
39464def dup_S2_storeri_io : HInst<
39465(outs),
39466(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32),
39467"memw($Rs32+#$Ii) = $Rt32",
39468tc_a9edeffa, TypeST>, Requires<[HasV68]> {
39469let addrMode = BaseImmOffset;
39470let accessSize = WordAccess;
39471let AsmVariantName = "NonParsable";
39472let mayStore = 1;
39473let isPseudo = 1;
39474let isExtendable = 1;
39475let opExtendable = 1;
39476let isExtentSigned = 1;
39477let opExtentBits = 13;
39478let opExtentAlign = 2;
39479}
39480def dup_S4_storeirb_io : HInst<
39481(outs),
39482(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II),
39483"memb($Rs32+#$Ii) = #$II",
39484tc_838c4d7a, TypeV4LDST>, Requires<[HasV68]> {
39485let addrMode = BaseImmOffset;
39486let accessSize = ByteAccess;
39487let AsmVariantName = "NonParsable";
39488let mayStore = 1;
39489let isPseudo = 1;
39490let isExtendable = 1;
39491let opExtendable = 2;
39492let isExtentSigned = 1;
39493let opExtentBits = 8;
39494let opExtentAlign = 0;
39495}
39496def dup_S4_storeiri_io : HInst<
39497(outs),
39498(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II),
39499"memw($Rs32+#$Ii) = #$II",
39500tc_838c4d7a, TypeV4LDST>, Requires<[HasV68]> {
39501let addrMode = BaseImmOffset;
39502let accessSize = WordAccess;
39503let AsmVariantName = "NonParsable";
39504let mayStore = 1;
39505let isPseudo = 1;
39506let isExtendable = 1;
39507let opExtendable = 2;
39508let isExtentSigned = 1;
39509let opExtentBits = 8;
39510let opExtentAlign = 0;
39511}
39512