xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td (revision 744bfb213144c63cbaf38d91a1c4f7aebb9b9fbc) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11class Enc_01d3d0 : OpcodeHexagon {
12  bits <5> Vu32;
13  let Inst{12-8} = Vu32{4-0};
14  bits <5> Rt32;
15  let Inst{20-16} = Rt32{4-0};
16  bits <5> Vdd32;
17  let Inst{4-0} = Vdd32{4-0};
18}
19class Enc_02553a : OpcodeHexagon {
20  bits <7> Ii;
21  let Inst{11-5} = Ii{6-0};
22  bits <5> Rs32;
23  let Inst{20-16} = Rs32{4-0};
24  bits <2> Pd4;
25  let Inst{1-0} = Pd4{1-0};
26}
27class Enc_03833b : OpcodeHexagon {
28  bits <5> Rss32;
29  let Inst{20-16} = Rss32{4-0};
30  bits <5> Rt32;
31  let Inst{12-8} = Rt32{4-0};
32  bits <2> Pd4;
33  let Inst{1-0} = Pd4{1-0};
34}
35class Enc_041d7b : OpcodeHexagon {
36  bits <11> Ii;
37  let Inst{21-20} = Ii{10-9};
38  let Inst{7-1} = Ii{8-2};
39  bits <4> Rs16;
40  let Inst{19-16} = Rs16{3-0};
41  bits <5> n1;
42  let Inst{28-28} = n1{4-4};
43  let Inst{24-23} = n1{3-2};
44  let Inst{13-13} = n1{1-1};
45  let Inst{8-8} = n1{0-0};
46}
47class Enc_04c959 : OpcodeHexagon {
48  bits <2> Ii;
49  let Inst{13-13} = Ii{1-1};
50  let Inst{7-7} = Ii{0-0};
51  bits <6> II;
52  let Inst{11-8} = II{5-2};
53  let Inst{6-5} = II{1-0};
54  bits <5> Rt32;
55  let Inst{20-16} = Rt32{4-0};
56  bits <5> Ryy32;
57  let Inst{4-0} = Ryy32{4-0};
58}
59class Enc_0527db : OpcodeHexagon {
60  bits <4> Rs16;
61  let Inst{7-4} = Rs16{3-0};
62  bits <4> Rx16;
63  let Inst{3-0} = Rx16{3-0};
64}
65class Enc_052c7d : OpcodeHexagon {
66  bits <5> Ii;
67  let Inst{6-3} = Ii{4-1};
68  bits <5> Rt32;
69  let Inst{12-8} = Rt32{4-0};
70  bits <5> Rx32;
71  let Inst{20-16} = Rx32{4-0};
72}
73class Enc_08d755 : OpcodeHexagon {
74  bits <8> Ii;
75  let Inst{12-5} = Ii{7-0};
76  bits <5> Rs32;
77  let Inst{20-16} = Rs32{4-0};
78  bits <2> Pd4;
79  let Inst{1-0} = Pd4{1-0};
80}
81class Enc_0aa344 : OpcodeHexagon {
82  bits <5> Gss32;
83  let Inst{20-16} = Gss32{4-0};
84  bits <5> Rdd32;
85  let Inst{4-0} = Rdd32{4-0};
86}
87class Enc_0b2e5b : OpcodeHexagon {
88  bits <3> Ii;
89  let Inst{7-5} = Ii{2-0};
90  bits <5> Vu32;
91  let Inst{12-8} = Vu32{4-0};
92  bits <5> Vv32;
93  let Inst{20-16} = Vv32{4-0};
94  bits <5> Vd32;
95  let Inst{4-0} = Vd32{4-0};
96}
97class Enc_0b51ce : OpcodeHexagon {
98  bits <3> Ii;
99  let Inst{10-8} = Ii{2-0};
100  bits <2> Qv4;
101  let Inst{12-11} = Qv4{1-0};
102  bits <5> Vs32;
103  let Inst{4-0} = Vs32{4-0};
104  bits <5> Rx32;
105  let Inst{20-16} = Rx32{4-0};
106}
107class Enc_0cb018 : OpcodeHexagon {
108  bits <5> Cs32;
109  let Inst{20-16} = Cs32{4-0};
110  bits <5> Rd32;
111  let Inst{4-0} = Rd32{4-0};
112}
113class Enc_0d8870 : OpcodeHexagon {
114  bits <12> Ii;
115  let Inst{26-25} = Ii{11-10};
116  let Inst{13-13} = Ii{9-9};
117  let Inst{7-0} = Ii{8-1};
118  bits <5> Rs32;
119  let Inst{20-16} = Rs32{4-0};
120  bits <3> Nt8;
121  let Inst{10-8} = Nt8{2-0};
122}
123class Enc_0d8adb : OpcodeHexagon {
124  bits <8> Ii;
125  let Inst{12-5} = Ii{7-0};
126  bits <5> Rss32;
127  let Inst{20-16} = Rss32{4-0};
128  bits <2> Pd4;
129  let Inst{1-0} = Pd4{1-0};
130}
131class Enc_0e41fa : OpcodeHexagon {
132  bits <5> Vuu32;
133  let Inst{12-8} = Vuu32{4-0};
134  bits <5> Rt32;
135  let Inst{20-16} = Rt32{4-0};
136  bits <5> Vd32;
137  let Inst{4-0} = Vd32{4-0};
138}
139class Enc_0ed752 : OpcodeHexagon {
140  bits <5> Rss32;
141  let Inst{20-16} = Rss32{4-0};
142  bits <5> Cdd32;
143  let Inst{4-0} = Cdd32{4-0};
144}
145class Enc_0f8bab : OpcodeHexagon {
146  bits <5> Vu32;
147  let Inst{12-8} = Vu32{4-0};
148  bits <5> Rt32;
149  let Inst{20-16} = Rt32{4-0};
150  bits <2> Qd4;
151  let Inst{1-0} = Qd4{1-0};
152}
153class Enc_0fa531 : OpcodeHexagon {
154  bits <15> Ii;
155  let Inst{21-21} = Ii{14-14};
156  let Inst{13-13} = Ii{13-13};
157  let Inst{11-1} = Ii{12-2};
158  bits <5> Rs32;
159  let Inst{20-16} = Rs32{4-0};
160}
161class Enc_10bc21 : OpcodeHexagon {
162  bits <4> Ii;
163  let Inst{6-3} = Ii{3-0};
164  bits <5> Rt32;
165  let Inst{12-8} = Rt32{4-0};
166  bits <5> Rx32;
167  let Inst{20-16} = Rx32{4-0};
168}
169class Enc_1178da : OpcodeHexagon {
170  bits <3> Ii;
171  let Inst{7-5} = Ii{2-0};
172  bits <5> Vu32;
173  let Inst{12-8} = Vu32{4-0};
174  bits <5> Vv32;
175  let Inst{20-16} = Vv32{4-0};
176  bits <5> Vxx32;
177  let Inst{4-0} = Vxx32{4-0};
178}
179class Enc_11a146 : OpcodeHexagon {
180  bits <4> Ii;
181  let Inst{11-8} = Ii{3-0};
182  bits <5> Rss32;
183  let Inst{20-16} = Rss32{4-0};
184  bits <5> Rd32;
185  let Inst{4-0} = Rd32{4-0};
186}
187class Enc_12b6e9 : OpcodeHexagon {
188  bits <4> Ii;
189  let Inst{11-8} = Ii{3-0};
190  bits <5> Rss32;
191  let Inst{20-16} = Rss32{4-0};
192  bits <5> Rdd32;
193  let Inst{4-0} = Rdd32{4-0};
194}
195class Enc_134437 : OpcodeHexagon {
196  bits <2> Qs4;
197  let Inst{9-8} = Qs4{1-0};
198  bits <2> Qt4;
199  let Inst{23-22} = Qt4{1-0};
200  bits <2> Qd4;
201  let Inst{1-0} = Qd4{1-0};
202}
203class Enc_140c83 : OpcodeHexagon {
204  bits <10> Ii;
205  let Inst{21-21} = Ii{9-9};
206  let Inst{13-5} = Ii{8-0};
207  bits <5> Rs32;
208  let Inst{20-16} = Rs32{4-0};
209  bits <5> Rd32;
210  let Inst{4-0} = Rd32{4-0};
211}
212class Enc_143445 : OpcodeHexagon {
213  bits <13> Ii;
214  let Inst{26-25} = Ii{12-11};
215  let Inst{13-13} = Ii{10-10};
216  let Inst{7-0} = Ii{9-2};
217  bits <5> Rs32;
218  let Inst{20-16} = Rs32{4-0};
219  bits <5> Rt32;
220  let Inst{12-8} = Rt32{4-0};
221}
222class Enc_143a3c : OpcodeHexagon {
223  bits <6> Ii;
224  let Inst{13-8} = Ii{5-0};
225  bits <6> II;
226  let Inst{23-21} = II{5-3};
227  let Inst{7-5} = II{2-0};
228  bits <5> Rss32;
229  let Inst{20-16} = Rss32{4-0};
230  bits <5> Rxx32;
231  let Inst{4-0} = Rxx32{4-0};
232}
233class Enc_14640c : OpcodeHexagon {
234  bits <11> Ii;
235  let Inst{21-20} = Ii{10-9};
236  let Inst{7-1} = Ii{8-2};
237  bits <4> Rs16;
238  let Inst{19-16} = Rs16{3-0};
239  bits <5> n1;
240  let Inst{28-28} = n1{4-4};
241  let Inst{24-22} = n1{3-1};
242  let Inst{13-13} = n1{0-0};
243}
244class Enc_14d27a : OpcodeHexagon {
245  bits <5> II;
246  let Inst{12-8} = II{4-0};
247  bits <11> Ii;
248  let Inst{21-20} = Ii{10-9};
249  let Inst{7-1} = Ii{8-2};
250  bits <4> Rs16;
251  let Inst{19-16} = Rs16{3-0};
252}
253class Enc_152467 : OpcodeHexagon {
254  bits <5> Ii;
255  let Inst{8-5} = Ii{4-1};
256  bits <5> Rd32;
257  let Inst{4-0} = Rd32{4-0};
258  bits <5> Rx32;
259  let Inst{20-16} = Rx32{4-0};
260}
261class Enc_158beb : OpcodeHexagon {
262  bits <2> Qs4;
263  let Inst{6-5} = Qs4{1-0};
264  bits <5> Rt32;
265  let Inst{20-16} = Rt32{4-0};
266  bits <1> Mu2;
267  let Inst{13-13} = Mu2{0-0};
268  bits <5> Vv32;
269  let Inst{4-0} = Vv32{4-0};
270}
271class Enc_163a3c : OpcodeHexagon {
272  bits <7> Ii;
273  let Inst{12-7} = Ii{6-1};
274  bits <5> Rs32;
275  let Inst{20-16} = Rs32{4-0};
276  bits <5> Rt32;
277  let Inst{4-0} = Rt32{4-0};
278}
279class Enc_16c48b : OpcodeHexagon {
280  bits <5> Rt32;
281  let Inst{20-16} = Rt32{4-0};
282  bits <1> Mu2;
283  let Inst{13-13} = Mu2{0-0};
284  bits <5> Vv32;
285  let Inst{12-8} = Vv32{4-0};
286  bits <5> Vw32;
287  let Inst{4-0} = Vw32{4-0};
288}
289class Enc_178717 : OpcodeHexagon {
290  bits <11> Ii;
291  let Inst{21-20} = Ii{10-9};
292  let Inst{7-1} = Ii{8-2};
293  bits <4> Rs16;
294  let Inst{19-16} = Rs16{3-0};
295  bits <6> n1;
296  let Inst{28-28} = n1{5-5};
297  let Inst{25-23} = n1{4-2};
298  let Inst{13-13} = n1{1-1};
299  let Inst{8-8} = n1{0-0};
300}
301class Enc_179b35 : OpcodeHexagon {
302  bits <5> Rs32;
303  let Inst{20-16} = Rs32{4-0};
304  bits <5> Rtt32;
305  let Inst{12-8} = Rtt32{4-0};
306  bits <5> Rx32;
307  let Inst{4-0} = Rx32{4-0};
308}
309class Enc_18c338 : OpcodeHexagon {
310  bits <8> Ii;
311  let Inst{12-5} = Ii{7-0};
312  bits <8> II;
313  let Inst{22-16} = II{7-1};
314  let Inst{13-13} = II{0-0};
315  bits <5> Rdd32;
316  let Inst{4-0} = Rdd32{4-0};
317}
318class Enc_1a9974 : OpcodeHexagon {
319  bits <2> Ii;
320  let Inst{13-13} = Ii{1-1};
321  let Inst{7-7} = Ii{0-0};
322  bits <2> Pv4;
323  let Inst{6-5} = Pv4{1-0};
324  bits <5> Rs32;
325  let Inst{20-16} = Rs32{4-0};
326  bits <5> Ru32;
327  let Inst{12-8} = Ru32{4-0};
328  bits <5> Rtt32;
329  let Inst{4-0} = Rtt32{4-0};
330}
331class Enc_1aa186 : OpcodeHexagon {
332  bits <5> Rss32;
333  let Inst{20-16} = Rss32{4-0};
334  bits <5> Rt32;
335  let Inst{12-8} = Rt32{4-0};
336  bits <5> Rxx32;
337  let Inst{4-0} = Rxx32{4-0};
338}
339class Enc_1aaec1 : OpcodeHexagon {
340  bits <3> Ii;
341  let Inst{10-8} = Ii{2-0};
342  bits <3> Os8;
343  let Inst{2-0} = Os8{2-0};
344  bits <5> Rx32;
345  let Inst{20-16} = Rx32{4-0};
346}
347class Enc_1b64fb : OpcodeHexagon {
348  bits <16> Ii;
349  let Inst{26-25} = Ii{15-14};
350  let Inst{20-16} = Ii{13-9};
351  let Inst{13-13} = Ii{8-8};
352  let Inst{7-0} = Ii{7-0};
353  bits <5> Rt32;
354  let Inst{12-8} = Rt32{4-0};
355}
356class Enc_1bd127 : OpcodeHexagon {
357  bits <5> Vu32;
358  let Inst{12-8} = Vu32{4-0};
359  bits <3> Rt8;
360  let Inst{18-16} = Rt8{2-0};
361  bits <5> Vdddd32;
362  let Inst{4-0} = Vdddd32{4-0};
363}
364class Enc_1cf4ca : OpcodeHexagon {
365  bits <6> Ii;
366  let Inst{17-16} = Ii{5-4};
367  let Inst{6-3} = Ii{3-0};
368  bits <2> Pv4;
369  let Inst{1-0} = Pv4{1-0};
370  bits <5> Rt32;
371  let Inst{12-8} = Rt32{4-0};
372}
373class Enc_1de724 : OpcodeHexagon {
374  bits <11> Ii;
375  let Inst{21-20} = Ii{10-9};
376  let Inst{7-1} = Ii{8-2};
377  bits <4> Rs16;
378  let Inst{19-16} = Rs16{3-0};
379  bits <4> n1;
380  let Inst{28-28} = n1{3-3};
381  let Inst{24-22} = n1{2-0};
382}
383class Enc_1ef990 : OpcodeHexagon {
384  bits <2> Pv4;
385  let Inst{12-11} = Pv4{1-0};
386  bits <1> Mu2;
387  let Inst{13-13} = Mu2{0-0};
388  bits <5> Vs32;
389  let Inst{4-0} = Vs32{4-0};
390  bits <5> Rx32;
391  let Inst{20-16} = Rx32{4-0};
392}
393class Enc_1f19b5 : OpcodeHexagon {
394  bits <5> Ii;
395  let Inst{9-5} = Ii{4-0};
396  bits <5> Rss32;
397  let Inst{20-16} = Rss32{4-0};
398  bits <2> Pd4;
399  let Inst{1-0} = Pd4{1-0};
400}
401class Enc_1f5ba6 : OpcodeHexagon {
402  bits <4> Rd16;
403  let Inst{3-0} = Rd16{3-0};
404}
405class Enc_1f5d8f : OpcodeHexagon {
406  bits <1> Mu2;
407  let Inst{13-13} = Mu2{0-0};
408  bits <5> Ryy32;
409  let Inst{4-0} = Ryy32{4-0};
410  bits <5> Rx32;
411  let Inst{20-16} = Rx32{4-0};
412}
413class Enc_211aaa : OpcodeHexagon {
414  bits <11> Ii;
415  let Inst{26-25} = Ii{10-9};
416  let Inst{13-5} = Ii{8-0};
417  bits <5> Rs32;
418  let Inst{20-16} = Rs32{4-0};
419  bits <5> Rd32;
420  let Inst{4-0} = Rd32{4-0};
421}
422class Enc_217147 : OpcodeHexagon {
423  bits <2> Qv4;
424  let Inst{23-22} = Qv4{1-0};
425}
426class Enc_222336 : OpcodeHexagon {
427  bits <4> Ii;
428  let Inst{8-5} = Ii{3-0};
429  bits <5> Rd32;
430  let Inst{4-0} = Rd32{4-0};
431  bits <5> Rx32;
432  let Inst{20-16} = Rx32{4-0};
433}
434class Enc_223005 : OpcodeHexagon {
435  bits <6> Ii;
436  let Inst{6-3} = Ii{5-2};
437  bits <3> Nt8;
438  let Inst{10-8} = Nt8{2-0};
439  bits <5> Rx32;
440  let Inst{20-16} = Rx32{4-0};
441}
442class Enc_226535 : OpcodeHexagon {
443  bits <8> Ii;
444  let Inst{12-7} = Ii{7-2};
445  bits <5> Rs32;
446  let Inst{20-16} = Rs32{4-0};
447  bits <5> Rt32;
448  let Inst{4-0} = Rt32{4-0};
449}
450class Enc_22c845 : OpcodeHexagon {
451  bits <14> Ii;
452  let Inst{10-0} = Ii{13-3};
453  bits <5> Rx32;
454  let Inst{20-16} = Rx32{4-0};
455}
456class Enc_2301d6 : OpcodeHexagon {
457  bits <6> Ii;
458  let Inst{20-16} = Ii{5-1};
459  let Inst{8-8} = Ii{0-0};
460  bits <2> Pt4;
461  let Inst{10-9} = Pt4{1-0};
462  bits <5> Rd32;
463  let Inst{4-0} = Rd32{4-0};
464}
465class Enc_245865 : OpcodeHexagon {
466  bits <5> Vu32;
467  let Inst{12-8} = Vu32{4-0};
468  bits <5> Vv32;
469  let Inst{23-19} = Vv32{4-0};
470  bits <3> Rt8;
471  let Inst{18-16} = Rt8{2-0};
472  bits <5> Vx32;
473  let Inst{4-0} = Vx32{4-0};
474}
475class Enc_24a7dc : OpcodeHexagon {
476  bits <5> Vu32;
477  let Inst{12-8} = Vu32{4-0};
478  bits <5> Vv32;
479  let Inst{23-19} = Vv32{4-0};
480  bits <3> Rt8;
481  let Inst{18-16} = Rt8{2-0};
482  bits <5> Vdd32;
483  let Inst{4-0} = Vdd32{4-0};
484}
485class Enc_25bef0 : OpcodeHexagon {
486  bits <16> Ii;
487  let Inst{26-25} = Ii{15-14};
488  let Inst{20-16} = Ii{13-9};
489  let Inst{13-5} = Ii{8-0};
490  bits <5> Rd32;
491  let Inst{4-0} = Rd32{4-0};
492}
493class Enc_263841 : OpcodeHexagon {
494  bits <5> Vu32;
495  let Inst{12-8} = Vu32{4-0};
496  bits <5> Rtt32;
497  let Inst{20-16} = Rtt32{4-0};
498  bits <5> Vd32;
499  let Inst{4-0} = Vd32{4-0};
500}
501class Enc_277737 : OpcodeHexagon {
502  bits <8> Ii;
503  let Inst{22-21} = Ii{7-6};
504  let Inst{13-13} = Ii{5-5};
505  let Inst{7-5} = Ii{4-2};
506  bits <5> Ru32;
507  let Inst{4-0} = Ru32{4-0};
508  bits <5> Rs32;
509  let Inst{20-16} = Rs32{4-0};
510  bits <5> Rd32;
511  let Inst{12-8} = Rd32{4-0};
512}
513class Enc_27b757 : OpcodeHexagon {
514  bits <4> Ii;
515  let Inst{13-13} = Ii{3-3};
516  let Inst{10-8} = Ii{2-0};
517  bits <2> Pv4;
518  let Inst{12-11} = Pv4{1-0};
519  bits <5> Rt32;
520  let Inst{20-16} = Rt32{4-0};
521  bits <5> Vs32;
522  let Inst{4-0} = Vs32{4-0};
523}
524class Enc_27fd0e : OpcodeHexagon {
525  bits <6> Ii;
526  let Inst{8-5} = Ii{5-2};
527  bits <1> Mu2;
528  let Inst{13-13} = Mu2{0-0};
529  bits <5> Rd32;
530  let Inst{4-0} = Rd32{4-0};
531  bits <5> Rx32;
532  let Inst{20-16} = Rx32{4-0};
533}
534class Enc_284ebb : OpcodeHexagon {
535  bits <2> Ps4;
536  let Inst{17-16} = Ps4{1-0};
537  bits <2> Pt4;
538  let Inst{9-8} = Pt4{1-0};
539  bits <2> Pd4;
540  let Inst{1-0} = Pd4{1-0};
541}
542class Enc_28a2dc : OpcodeHexagon {
543  bits <5> Ii;
544  let Inst{12-8} = Ii{4-0};
545  bits <5> Rs32;
546  let Inst{20-16} = Rs32{4-0};
547  bits <5> Rx32;
548  let Inst{4-0} = Rx32{4-0};
549}
550class Enc_28dcbb : OpcodeHexagon {
551  bits <5> Rt32;
552  let Inst{20-16} = Rt32{4-0};
553  bits <1> Mu2;
554  let Inst{13-13} = Mu2{0-0};
555  bits <5> Vvv32;
556  let Inst{4-0} = Vvv32{4-0};
557}
558class Enc_2a3787 : OpcodeHexagon {
559  bits <13> Ii;
560  let Inst{26-25} = Ii{12-11};
561  let Inst{13-5} = Ii{10-2};
562  bits <5> Rs32;
563  let Inst{20-16} = Rs32{4-0};
564  bits <5> Rd32;
565  let Inst{4-0} = Rd32{4-0};
566}
567class Enc_2a7b91 : OpcodeHexagon {
568  bits <6> Ii;
569  let Inst{20-16} = Ii{5-1};
570  let Inst{8-8} = Ii{0-0};
571  bits <2> Pt4;
572  let Inst{10-9} = Pt4{1-0};
573  bits <5> Rdd32;
574  let Inst{4-0} = Rdd32{4-0};
575}
576class Enc_2ae154 : OpcodeHexagon {
577  bits <5> Rs32;
578  let Inst{20-16} = Rs32{4-0};
579  bits <5> Rt32;
580  let Inst{12-8} = Rt32{4-0};
581  bits <5> Rx32;
582  let Inst{4-0} = Rx32{4-0};
583}
584class Enc_2b3f60 : OpcodeHexagon {
585  bits <5> Rss32;
586  let Inst{20-16} = Rss32{4-0};
587  bits <5> Rtt32;
588  let Inst{12-8} = Rtt32{4-0};
589  bits <5> Rdd32;
590  let Inst{4-0} = Rdd32{4-0};
591  bits <2> Px4;
592  let Inst{6-5} = Px4{1-0};
593}
594class Enc_2b518f : OpcodeHexagon {
595  bits <32> Ii;
596  let Inst{27-16} = Ii{31-20};
597  let Inst{13-0} = Ii{19-6};
598}
599class Enc_2bae10 : OpcodeHexagon {
600  bits <4> Ii;
601  let Inst{10-8} = Ii{3-1};
602  bits <4> Rs16;
603  let Inst{7-4} = Rs16{3-0};
604  bits <4> Rd16;
605  let Inst{3-0} = Rd16{3-0};
606}
607class Enc_2d7491 : OpcodeHexagon {
608  bits <13> Ii;
609  let Inst{26-25} = Ii{12-11};
610  let Inst{13-5} = Ii{10-2};
611  bits <5> Rs32;
612  let Inst{20-16} = Rs32{4-0};
613  bits <5> Rdd32;
614  let Inst{4-0} = Rdd32{4-0};
615}
616class Enc_2d829e : OpcodeHexagon {
617  bits <14> Ii;
618  let Inst{10-0} = Ii{13-3};
619  bits <5> Rs32;
620  let Inst{20-16} = Rs32{4-0};
621}
622class Enc_2df31d : OpcodeHexagon {
623  bits <8> Ii;
624  let Inst{9-4} = Ii{7-2};
625  bits <4> Rd16;
626  let Inst{3-0} = Rd16{3-0};
627}
628class Enc_2e1979 : OpcodeHexagon {
629  bits <2> Ii;
630  let Inst{13-13} = Ii{1-1};
631  let Inst{7-7} = Ii{0-0};
632  bits <2> Pv4;
633  let Inst{6-5} = Pv4{1-0};
634  bits <5> Rs32;
635  let Inst{20-16} = Rs32{4-0};
636  bits <5> Rt32;
637  let Inst{12-8} = Rt32{4-0};
638  bits <5> Rd32;
639  let Inst{4-0} = Rd32{4-0};
640}
641class Enc_2ea740 : OpcodeHexagon {
642  bits <4> Ii;
643  let Inst{13-13} = Ii{3-3};
644  let Inst{10-8} = Ii{2-0};
645  bits <2> Qv4;
646  let Inst{12-11} = Qv4{1-0};
647  bits <5> Rt32;
648  let Inst{20-16} = Rt32{4-0};
649  bits <5> Vs32;
650  let Inst{4-0} = Vs32{4-0};
651}
652class Enc_2ebe3b : OpcodeHexagon {
653  bits <1> Mu2;
654  let Inst{13-13} = Mu2{0-0};
655  bits <5> Vd32;
656  let Inst{4-0} = Vd32{4-0};
657  bits <5> Rx32;
658  let Inst{20-16} = Rx32{4-0};
659}
660class Enc_2f2f04 : OpcodeHexagon {
661  bits <1> Ii;
662  let Inst{5-5} = Ii{0-0};
663  bits <5> Vuu32;
664  let Inst{12-8} = Vuu32{4-0};
665  bits <5> Rt32;
666  let Inst{20-16} = Rt32{4-0};
667  bits <5> Vdd32;
668  let Inst{4-0} = Vdd32{4-0};
669}
670class Enc_2fbf3c : OpcodeHexagon {
671  bits <3> Ii;
672  let Inst{10-8} = Ii{2-0};
673  bits <4> Rs16;
674  let Inst{7-4} = Rs16{3-0};
675  bits <4> Rd16;
676  let Inst{3-0} = Rd16{3-0};
677}
678class Enc_310ba1 : OpcodeHexagon {
679  bits <5> Vu32;
680  let Inst{12-8} = Vu32{4-0};
681  bits <5> Rtt32;
682  let Inst{20-16} = Rtt32{4-0};
683  bits <5> Vx32;
684  let Inst{4-0} = Vx32{4-0};
685}
686class Enc_311abd : OpcodeHexagon {
687  bits <5> Ii;
688  let Inst{12-8} = Ii{4-0};
689  bits <5> Rs32;
690  let Inst{20-16} = Rs32{4-0};
691  bits <5> Rdd32;
692  let Inst{4-0} = Rdd32{4-0};
693}
694class Enc_31aa6a : OpcodeHexagon {
695  bits <5> Ii;
696  let Inst{6-3} = Ii{4-1};
697  bits <2> Pv4;
698  let Inst{1-0} = Pv4{1-0};
699  bits <3> Nt8;
700  let Inst{10-8} = Nt8{2-0};
701  bits <5> Rx32;
702  let Inst{20-16} = Rx32{4-0};
703}
704class Enc_31db33 : OpcodeHexagon {
705  bits <2> Qt4;
706  let Inst{6-5} = Qt4{1-0};
707  bits <5> Vu32;
708  let Inst{12-8} = Vu32{4-0};
709  bits <5> Vv32;
710  let Inst{20-16} = Vv32{4-0};
711  bits <5> Vd32;
712  let Inst{4-0} = Vd32{4-0};
713}
714class Enc_322e1b : OpcodeHexagon {
715  bits <6> Ii;
716  let Inst{22-21} = Ii{5-4};
717  let Inst{13-13} = Ii{3-3};
718  let Inst{7-5} = Ii{2-0};
719  bits <6> II;
720  let Inst{23-23} = II{5-5};
721  let Inst{4-0} = II{4-0};
722  bits <5> Rs32;
723  let Inst{20-16} = Rs32{4-0};
724  bits <5> Rd32;
725  let Inst{12-8} = Rd32{4-0};
726}
727class Enc_323f2d : OpcodeHexagon {
728  bits <6> II;
729  let Inst{11-8} = II{5-2};
730  let Inst{6-5} = II{1-0};
731  bits <5> Rd32;
732  let Inst{4-0} = Rd32{4-0};
733  bits <5> Re32;
734  let Inst{20-16} = Re32{4-0};
735}
736class Enc_329361 : OpcodeHexagon {
737  bits <2> Pu4;
738  let Inst{6-5} = Pu4{1-0};
739  bits <5> Rss32;
740  let Inst{20-16} = Rss32{4-0};
741  bits <5> Rtt32;
742  let Inst{12-8} = Rtt32{4-0};
743  bits <5> Rdd32;
744  let Inst{4-0} = Rdd32{4-0};
745}
746class Enc_33f8ba : OpcodeHexagon {
747  bits <8> Ii;
748  let Inst{12-8} = Ii{7-3};
749  let Inst{4-2} = Ii{2-0};
750  bits <5> Rx32;
751  let Inst{20-16} = Rx32{4-0};
752}
753class Enc_3680c2 : OpcodeHexagon {
754  bits <7> Ii;
755  let Inst{11-5} = Ii{6-0};
756  bits <5> Rss32;
757  let Inst{20-16} = Rss32{4-0};
758  bits <2> Pd4;
759  let Inst{1-0} = Pd4{1-0};
760}
761class Enc_3694bd : OpcodeHexagon {
762  bits <11> Ii;
763  let Inst{21-20} = Ii{10-9};
764  let Inst{7-1} = Ii{8-2};
765  bits <3> Ns8;
766  let Inst{18-16} = Ns8{2-0};
767  bits <5> n1;
768  let Inst{29-29} = n1{4-4};
769  let Inst{26-25} = n1{3-2};
770  let Inst{23-22} = n1{1-0};
771}
772class Enc_372c9d : OpcodeHexagon {
773  bits <2> Pv4;
774  let Inst{12-11} = Pv4{1-0};
775  bits <1> Mu2;
776  let Inst{13-13} = Mu2{0-0};
777  bits <3> Os8;
778  let Inst{2-0} = Os8{2-0};
779  bits <5> Rx32;
780  let Inst{20-16} = Rx32{4-0};
781}
782class Enc_395cc4 : OpcodeHexagon {
783  bits <7> Ii;
784  let Inst{6-3} = Ii{6-3};
785  bits <1> Mu2;
786  let Inst{13-13} = Mu2{0-0};
787  bits <5> Rtt32;
788  let Inst{12-8} = Rtt32{4-0};
789  bits <5> Rx32;
790  let Inst{20-16} = Rx32{4-0};
791}
792class Enc_397f23 : OpcodeHexagon {
793  bits <8> Ii;
794  let Inst{13-13} = Ii{7-7};
795  let Inst{7-3} = Ii{6-2};
796  bits <2> Pv4;
797  let Inst{1-0} = Pv4{1-0};
798  bits <5> Rs32;
799  let Inst{20-16} = Rs32{4-0};
800  bits <5> Rt32;
801  let Inst{12-8} = Rt32{4-0};
802}
803class Enc_399e12 : OpcodeHexagon {
804  bits <4> Rs16;
805  let Inst{7-4} = Rs16{3-0};
806  bits <3> Rdd8;
807  let Inst{2-0} = Rdd8{2-0};
808}
809class Enc_3a2484 : OpcodeHexagon {
810  bits <11> Ii;
811  let Inst{21-20} = Ii{10-9};
812  let Inst{7-1} = Ii{8-2};
813  bits <4> Rs16;
814  let Inst{19-16} = Rs16{3-0};
815  bits <4> n1;
816  let Inst{28-28} = n1{3-3};
817  let Inst{24-23} = n1{2-1};
818  let Inst{13-13} = n1{0-0};
819}
820class Enc_3a3d62 : OpcodeHexagon {
821  bits <5> Rs32;
822  let Inst{20-16} = Rs32{4-0};
823  bits <5> Rdd32;
824  let Inst{4-0} = Rdd32{4-0};
825}
826class Enc_3b7631 : OpcodeHexagon {
827  bits <5> Vu32;
828  let Inst{12-8} = Vu32{4-0};
829  bits <5> Vdddd32;
830  let Inst{4-0} = Vdddd32{4-0};
831  bits <3> Rx8;
832  let Inst{18-16} = Rx8{2-0};
833}
834class Enc_3d5b28 : OpcodeHexagon {
835  bits <5> Rss32;
836  let Inst{20-16} = Rss32{4-0};
837  bits <5> Rt32;
838  let Inst{12-8} = Rt32{4-0};
839  bits <5> Rd32;
840  let Inst{4-0} = Rd32{4-0};
841}
842class Enc_3d6d37 : OpcodeHexagon {
843  bits <2> Qs4;
844  let Inst{6-5} = Qs4{1-0};
845  bits <5> Rt32;
846  let Inst{20-16} = Rt32{4-0};
847  bits <1> Mu2;
848  let Inst{13-13} = Mu2{0-0};
849  bits <5> Vvv32;
850  let Inst{12-8} = Vvv32{4-0};
851  bits <5> Vw32;
852  let Inst{4-0} = Vw32{4-0};
853}
854class Enc_3d920a : OpcodeHexagon {
855  bits <6> Ii;
856  let Inst{8-5} = Ii{5-2};
857  bits <5> Rd32;
858  let Inst{4-0} = Rd32{4-0};
859  bits <5> Rx32;
860  let Inst{20-16} = Rx32{4-0};
861}
862class Enc_3dac0b : OpcodeHexagon {
863  bits <2> Qt4;
864  let Inst{6-5} = Qt4{1-0};
865  bits <5> Vu32;
866  let Inst{12-8} = Vu32{4-0};
867  bits <5> Vv32;
868  let Inst{20-16} = Vv32{4-0};
869  bits <5> Vdd32;
870  let Inst{4-0} = Vdd32{4-0};
871}
872class Enc_3e3989 : OpcodeHexagon {
873  bits <11> Ii;
874  let Inst{21-20} = Ii{10-9};
875  let Inst{7-1} = Ii{8-2};
876  bits <4> Rs16;
877  let Inst{19-16} = Rs16{3-0};
878  bits <6> n1;
879  let Inst{28-28} = n1{5-5};
880  let Inst{25-22} = n1{4-1};
881  let Inst{8-8} = n1{0-0};
882}
883class Enc_3f97c8 : OpcodeHexagon {
884  bits <6> Ii;
885  let Inst{6-3} = Ii{5-2};
886  bits <1> Mu2;
887  let Inst{13-13} = Mu2{0-0};
888  bits <3> Nt8;
889  let Inst{10-8} = Nt8{2-0};
890  bits <5> Rx32;
891  let Inst{20-16} = Rx32{4-0};
892}
893class Enc_3fc427 : OpcodeHexagon {
894  bits <5> Vu32;
895  let Inst{12-8} = Vu32{4-0};
896  bits <5> Vv32;
897  let Inst{20-16} = Vv32{4-0};
898  bits <5> Vxx32;
899  let Inst{4-0} = Vxx32{4-0};
900}
901class Enc_405228 : OpcodeHexagon {
902  bits <11> Ii;
903  let Inst{21-20} = Ii{10-9};
904  let Inst{7-1} = Ii{8-2};
905  bits <4> Rs16;
906  let Inst{19-16} = Rs16{3-0};
907  bits <3> n1;
908  let Inst{28-28} = n1{2-2};
909  let Inst{24-23} = n1{1-0};
910}
911class Enc_412ff0 : OpcodeHexagon {
912  bits <5> Rss32;
913  let Inst{20-16} = Rss32{4-0};
914  bits <5> Ru32;
915  let Inst{4-0} = Ru32{4-0};
916  bits <5> Rxx32;
917  let Inst{12-8} = Rxx32{4-0};
918}
919class Enc_420cf3 : OpcodeHexagon {
920  bits <6> Ii;
921  let Inst{22-21} = Ii{5-4};
922  let Inst{13-13} = Ii{3-3};
923  let Inst{7-5} = Ii{2-0};
924  bits <5> Ru32;
925  let Inst{4-0} = Ru32{4-0};
926  bits <5> Rs32;
927  let Inst{20-16} = Rs32{4-0};
928  bits <5> Rd32;
929  let Inst{12-8} = Rd32{4-0};
930}
931class Enc_437f33 : OpcodeHexagon {
932  bits <5> Rs32;
933  let Inst{20-16} = Rs32{4-0};
934  bits <5> Rt32;
935  let Inst{12-8} = Rt32{4-0};
936  bits <2> Pu4;
937  let Inst{6-5} = Pu4{1-0};
938  bits <5> Rx32;
939  let Inst{4-0} = Rx32{4-0};
940}
941class Enc_44215c : OpcodeHexagon {
942  bits <6> Ii;
943  let Inst{17-16} = Ii{5-4};
944  let Inst{6-3} = Ii{3-0};
945  bits <2> Pv4;
946  let Inst{1-0} = Pv4{1-0};
947  bits <3> Nt8;
948  let Inst{10-8} = Nt8{2-0};
949}
950class Enc_44271f : OpcodeHexagon {
951  bits <5> Gs32;
952  let Inst{20-16} = Gs32{4-0};
953  bits <5> Rd32;
954  let Inst{4-0} = Rd32{4-0};
955}
956class Enc_44661f : OpcodeHexagon {
957  bits <1> Mu2;
958  let Inst{13-13} = Mu2{0-0};
959  bits <5> Rx32;
960  let Inst{20-16} = Rx32{4-0};
961}
962class Enc_448f7f : OpcodeHexagon {
963  bits <11> Ii;
964  let Inst{26-25} = Ii{10-9};
965  let Inst{13-13} = Ii{8-8};
966  let Inst{7-0} = Ii{7-0};
967  bits <5> Rs32;
968  let Inst{20-16} = Rs32{4-0};
969  bits <5> Rt32;
970  let Inst{12-8} = Rt32{4-0};
971}
972class Enc_45364e : OpcodeHexagon {
973  bits <5> Vu32;
974  let Inst{12-8} = Vu32{4-0};
975  bits <5> Vv32;
976  let Inst{20-16} = Vv32{4-0};
977  bits <5> Vd32;
978  let Inst{4-0} = Vd32{4-0};
979}
980class Enc_454a26 : OpcodeHexagon {
981  bits <2> Pt4;
982  let Inst{9-8} = Pt4{1-0};
983  bits <2> Ps4;
984  let Inst{17-16} = Ps4{1-0};
985  bits <2> Pd4;
986  let Inst{1-0} = Pd4{1-0};
987}
988class Enc_46c951 : OpcodeHexagon {
989  bits <6> Ii;
990  let Inst{12-7} = Ii{5-0};
991  bits <5> II;
992  let Inst{4-0} = II{4-0};
993  bits <5> Rs32;
994  let Inst{20-16} = Rs32{4-0};
995}
996class Enc_47ee5e : OpcodeHexagon {
997  bits <2> Ii;
998  let Inst{13-13} = Ii{1-1};
999  let Inst{7-7} = Ii{0-0};
1000  bits <2> Pv4;
1001  let Inst{6-5} = Pv4{1-0};
1002  bits <5> Rs32;
1003  let Inst{20-16} = Rs32{4-0};
1004  bits <5> Ru32;
1005  let Inst{12-8} = Ru32{4-0};
1006  bits <3> Nt8;
1007  let Inst{2-0} = Nt8{2-0};
1008}
1009class Enc_47ef61 : OpcodeHexagon {
1010  bits <3> Ii;
1011  let Inst{7-5} = Ii{2-0};
1012  bits <5> Rt32;
1013  let Inst{12-8} = Rt32{4-0};
1014  bits <5> Rs32;
1015  let Inst{20-16} = Rs32{4-0};
1016  bits <5> Rd32;
1017  let Inst{4-0} = Rd32{4-0};
1018}
1019class Enc_48b75f : OpcodeHexagon {
1020  bits <5> Rs32;
1021  let Inst{20-16} = Rs32{4-0};
1022  bits <2> Pd4;
1023  let Inst{1-0} = Pd4{1-0};
1024}
1025class Enc_4aca3a : OpcodeHexagon {
1026  bits <11> Ii;
1027  let Inst{21-20} = Ii{10-9};
1028  let Inst{7-1} = Ii{8-2};
1029  bits <3> Ns8;
1030  let Inst{18-16} = Ns8{2-0};
1031  bits <3> n1;
1032  let Inst{29-29} = n1{2-2};
1033  let Inst{26-25} = n1{1-0};
1034}
1035class Enc_4b39e4 : OpcodeHexagon {
1036  bits <3> Ii;
1037  let Inst{7-5} = Ii{2-0};
1038  bits <5> Vu32;
1039  let Inst{12-8} = Vu32{4-0};
1040  bits <5> Vv32;
1041  let Inst{20-16} = Vv32{4-0};
1042  bits <5> Vdd32;
1043  let Inst{4-0} = Vdd32{4-0};
1044}
1045class Enc_4dc228 : OpcodeHexagon {
1046  bits <9> Ii;
1047  let Inst{12-8} = Ii{8-4};
1048  let Inst{4-3} = Ii{3-2};
1049  bits <10> II;
1050  let Inst{20-16} = II{9-5};
1051  let Inst{7-5} = II{4-2};
1052  let Inst{1-0} = II{1-0};
1053}
1054class Enc_4df4e9 : OpcodeHexagon {
1055  bits <11> Ii;
1056  let Inst{26-25} = Ii{10-9};
1057  let Inst{13-13} = Ii{8-8};
1058  let Inst{7-0} = Ii{7-0};
1059  bits <5> Rs32;
1060  let Inst{20-16} = Rs32{4-0};
1061  bits <3> Nt8;
1062  let Inst{10-8} = Nt8{2-0};
1063}
1064class Enc_4dff07 : OpcodeHexagon {
1065  bits <2> Qv4;
1066  let Inst{12-11} = Qv4{1-0};
1067  bits <1> Mu2;
1068  let Inst{13-13} = Mu2{0-0};
1069  bits <5> Vs32;
1070  let Inst{4-0} = Vs32{4-0};
1071  bits <5> Rx32;
1072  let Inst{20-16} = Rx32{4-0};
1073}
1074class Enc_4e4a80 : OpcodeHexagon {
1075  bits <2> Qs4;
1076  let Inst{6-5} = Qs4{1-0};
1077  bits <5> Rt32;
1078  let Inst{20-16} = Rt32{4-0};
1079  bits <1> Mu2;
1080  let Inst{13-13} = Mu2{0-0};
1081  bits <5> Vvv32;
1082  let Inst{4-0} = Vvv32{4-0};
1083}
1084class Enc_4f4ed7 : OpcodeHexagon {
1085  bits <18> Ii;
1086  let Inst{26-25} = Ii{17-16};
1087  let Inst{20-16} = Ii{15-11};
1088  let Inst{13-5} = Ii{10-2};
1089  bits <5> Rd32;
1090  let Inst{4-0} = Rd32{4-0};
1091}
1092class Enc_4f677b : OpcodeHexagon {
1093  bits <2> Ii;
1094  let Inst{13-13} = Ii{1-1};
1095  let Inst{7-7} = Ii{0-0};
1096  bits <6> II;
1097  let Inst{11-8} = II{5-2};
1098  let Inst{6-5} = II{1-0};
1099  bits <5> Rt32;
1100  let Inst{20-16} = Rt32{4-0};
1101  bits <5> Rd32;
1102  let Inst{4-0} = Rd32{4-0};
1103}
1104class Enc_500cb0 : OpcodeHexagon {
1105  bits <5> Vu32;
1106  let Inst{12-8} = Vu32{4-0};
1107  bits <5> Vxx32;
1108  let Inst{4-0} = Vxx32{4-0};
1109}
1110class Enc_509701 : OpcodeHexagon {
1111  bits <19> Ii;
1112  let Inst{26-25} = Ii{18-17};
1113  let Inst{20-16} = Ii{16-12};
1114  let Inst{13-5} = Ii{11-3};
1115  bits <5> Rdd32;
1116  let Inst{4-0} = Rdd32{4-0};
1117}
1118class Enc_50b5ac : OpcodeHexagon {
1119  bits <6> Ii;
1120  let Inst{17-16} = Ii{5-4};
1121  let Inst{6-3} = Ii{3-0};
1122  bits <2> Pv4;
1123  let Inst{1-0} = Pv4{1-0};
1124  bits <5> Rtt32;
1125  let Inst{12-8} = Rtt32{4-0};
1126}
1127class Enc_50e578 : OpcodeHexagon {
1128  bits <5> Vu32;
1129  let Inst{12-8} = Vu32{4-0};
1130  bits <5> Rs32;
1131  let Inst{20-16} = Rs32{4-0};
1132  bits <5> Rd32;
1133  let Inst{4-0} = Rd32{4-0};
1134}
1135class Enc_5138b3 : OpcodeHexagon {
1136  bits <5> Vu32;
1137  let Inst{12-8} = Vu32{4-0};
1138  bits <5> Rt32;
1139  let Inst{20-16} = Rt32{4-0};
1140  bits <5> Vx32;
1141  let Inst{4-0} = Vx32{4-0};
1142}
1143class Enc_51436c : OpcodeHexagon {
1144  bits <16> Ii;
1145  let Inst{23-22} = Ii{15-14};
1146  let Inst{13-0} = Ii{13-0};
1147  bits <5> Rx32;
1148  let Inst{20-16} = Rx32{4-0};
1149}
1150class Enc_51635c : OpcodeHexagon {
1151  bits <7> Ii;
1152  let Inst{8-4} = Ii{6-2};
1153  bits <4> Rd16;
1154  let Inst{3-0} = Rd16{3-0};
1155}
1156class Enc_527412 : OpcodeHexagon {
1157  bits <2> Ps4;
1158  let Inst{17-16} = Ps4{1-0};
1159  bits <2> Pt4;
1160  let Inst{9-8} = Pt4{1-0};
1161  bits <5> Rd32;
1162  let Inst{4-0} = Rd32{4-0};
1163}
1164class Enc_52a5dd : OpcodeHexagon {
1165  bits <4> Ii;
1166  let Inst{6-3} = Ii{3-0};
1167  bits <2> Pv4;
1168  let Inst{1-0} = Pv4{1-0};
1169  bits <3> Nt8;
1170  let Inst{10-8} = Nt8{2-0};
1171  bits <5> Rx32;
1172  let Inst{20-16} = Rx32{4-0};
1173}
1174class Enc_53dca9 : OpcodeHexagon {
1175  bits <6> Ii;
1176  let Inst{11-8} = Ii{5-2};
1177  bits <4> Rs16;
1178  let Inst{7-4} = Rs16{3-0};
1179  bits <4> Rd16;
1180  let Inst{3-0} = Rd16{3-0};
1181}
1182class Enc_541f26 : OpcodeHexagon {
1183  bits <18> Ii;
1184  let Inst{26-25} = Ii{17-16};
1185  let Inst{20-16} = Ii{15-11};
1186  let Inst{13-13} = Ii{10-10};
1187  let Inst{7-0} = Ii{9-2};
1188  bits <5> Rt32;
1189  let Inst{12-8} = Rt32{4-0};
1190}
1191class Enc_55355c : OpcodeHexagon {
1192  bits <2> Ii;
1193  let Inst{13-13} = Ii{1-1};
1194  let Inst{7-7} = Ii{0-0};
1195  bits <5> Rs32;
1196  let Inst{20-16} = Rs32{4-0};
1197  bits <5> Ru32;
1198  let Inst{12-8} = Ru32{4-0};
1199  bits <5> Rtt32;
1200  let Inst{4-0} = Rtt32{4-0};
1201}
1202class Enc_569cfe : OpcodeHexagon {
1203  bits <5> Rt32;
1204  let Inst{20-16} = Rt32{4-0};
1205  bits <5> Vx32;
1206  let Inst{4-0} = Vx32{4-0};
1207}
1208class Enc_57a33e : OpcodeHexagon {
1209  bits <9> Ii;
1210  let Inst{13-13} = Ii{8-8};
1211  let Inst{7-3} = Ii{7-3};
1212  bits <2> Pv4;
1213  let Inst{1-0} = Pv4{1-0};
1214  bits <5> Rs32;
1215  let Inst{20-16} = Rs32{4-0};
1216  bits <5> Rtt32;
1217  let Inst{12-8} = Rtt32{4-0};
1218}
1219class Enc_585242 : OpcodeHexagon {
1220  bits <6> Ii;
1221  let Inst{13-13} = Ii{5-5};
1222  let Inst{7-3} = Ii{4-0};
1223  bits <2> Pv4;
1224  let Inst{1-0} = Pv4{1-0};
1225  bits <5> Rs32;
1226  let Inst{20-16} = Rs32{4-0};
1227  bits <3> Nt8;
1228  let Inst{10-8} = Nt8{2-0};
1229}
1230class Enc_58a8bf : OpcodeHexagon {
1231  bits <3> Ii;
1232  let Inst{10-8} = Ii{2-0};
1233  bits <2> Pv4;
1234  let Inst{12-11} = Pv4{1-0};
1235  bits <5> Vd32;
1236  let Inst{4-0} = Vd32{4-0};
1237  bits <5> Rx32;
1238  let Inst{20-16} = Rx32{4-0};
1239}
1240class Enc_5a18b3 : OpcodeHexagon {
1241  bits <11> Ii;
1242  let Inst{21-20} = Ii{10-9};
1243  let Inst{7-1} = Ii{8-2};
1244  bits <3> Ns8;
1245  let Inst{18-16} = Ns8{2-0};
1246  bits <5> n1;
1247  let Inst{29-29} = n1{4-4};
1248  let Inst{26-25} = n1{3-2};
1249  let Inst{22-22} = n1{1-1};
1250  let Inst{13-13} = n1{0-0};
1251}
1252class Enc_5ab2be : OpcodeHexagon {
1253  bits <5> Rs32;
1254  let Inst{20-16} = Rs32{4-0};
1255  bits <5> Rt32;
1256  let Inst{12-8} = Rt32{4-0};
1257  bits <5> Rd32;
1258  let Inst{4-0} = Rd32{4-0};
1259}
1260class Enc_5bdd42 : OpcodeHexagon {
1261  bits <7> Ii;
1262  let Inst{8-5} = Ii{6-3};
1263  bits <5> Rdd32;
1264  let Inst{4-0} = Rdd32{4-0};
1265  bits <5> Rx32;
1266  let Inst{20-16} = Rx32{4-0};
1267}
1268class Enc_5c124a : OpcodeHexagon {
1269  bits <19> Ii;
1270  let Inst{26-25} = Ii{18-17};
1271  let Inst{20-16} = Ii{16-12};
1272  let Inst{13-13} = Ii{11-11};
1273  let Inst{7-0} = Ii{10-3};
1274  bits <5> Rtt32;
1275  let Inst{12-8} = Rtt32{4-0};
1276}
1277class Enc_5ccba9 : OpcodeHexagon {
1278  bits <8> Ii;
1279  let Inst{12-7} = Ii{7-2};
1280  bits <6> II;
1281  let Inst{13-13} = II{5-5};
1282  let Inst{4-0} = II{4-0};
1283  bits <2> Pv4;
1284  let Inst{6-5} = Pv4{1-0};
1285  bits <5> Rs32;
1286  let Inst{20-16} = Rs32{4-0};
1287}
1288class Enc_5cd7e9 : OpcodeHexagon {
1289  bits <12> Ii;
1290  let Inst{26-25} = Ii{11-10};
1291  let Inst{13-5} = Ii{9-1};
1292  bits <5> Rs32;
1293  let Inst{20-16} = Rs32{4-0};
1294  bits <5> Ryy32;
1295  let Inst{4-0} = Ryy32{4-0};
1296}
1297class Enc_5d6c34 : OpcodeHexagon {
1298  bits <6> Ii;
1299  let Inst{13-8} = Ii{5-0};
1300  bits <5> Rs32;
1301  let Inst{20-16} = Rs32{4-0};
1302  bits <2> Pd4;
1303  let Inst{1-0} = Pd4{1-0};
1304}
1305class Enc_5de85f : OpcodeHexagon {
1306  bits <11> Ii;
1307  let Inst{21-20} = Ii{10-9};
1308  let Inst{7-1} = Ii{8-2};
1309  bits <5> Rt32;
1310  let Inst{12-8} = Rt32{4-0};
1311  bits <3> Ns8;
1312  let Inst{18-16} = Ns8{2-0};
1313}
1314class Enc_5e2823 : OpcodeHexagon {
1315  bits <5> Rs32;
1316  let Inst{20-16} = Rs32{4-0};
1317  bits <5> Rd32;
1318  let Inst{4-0} = Rd32{4-0};
1319}
1320class Enc_5e8512 : OpcodeHexagon {
1321  bits <5> Vu32;
1322  let Inst{12-8} = Vu32{4-0};
1323  bits <5> Rt32;
1324  let Inst{20-16} = Rt32{4-0};
1325  bits <5> Vxx32;
1326  let Inst{4-0} = Vxx32{4-0};
1327}
1328class Enc_5e87ce : OpcodeHexagon {
1329  bits <16> Ii;
1330  let Inst{23-22} = Ii{15-14};
1331  let Inst{20-16} = Ii{13-9};
1332  let Inst{13-5} = Ii{8-0};
1333  bits <5> Rd32;
1334  let Inst{4-0} = Rd32{4-0};
1335}
1336class Enc_5eac98 : OpcodeHexagon {
1337  bits <6> Ii;
1338  let Inst{13-8} = Ii{5-0};
1339  bits <5> Rss32;
1340  let Inst{20-16} = Rss32{4-0};
1341  bits <5> Rdd32;
1342  let Inst{4-0} = Rdd32{4-0};
1343}
1344class Enc_607661 : OpcodeHexagon {
1345  bits <6> Ii;
1346  let Inst{12-7} = Ii{5-0};
1347  bits <5> Rd32;
1348  let Inst{4-0} = Rd32{4-0};
1349}
1350class Enc_6185fe : OpcodeHexagon {
1351  bits <2> Ii;
1352  let Inst{13-13} = Ii{1-1};
1353  let Inst{7-7} = Ii{0-0};
1354  bits <6> II;
1355  let Inst{11-8} = II{5-2};
1356  let Inst{6-5} = II{1-0};
1357  bits <5> Rt32;
1358  let Inst{20-16} = Rt32{4-0};
1359  bits <5> Rdd32;
1360  let Inst{4-0} = Rdd32{4-0};
1361}
1362class Enc_61f0b0 : OpcodeHexagon {
1363  bits <5> Rs32;
1364  let Inst{20-16} = Rs32{4-0};
1365  bits <5> Rt32;
1366  let Inst{12-8} = Rt32{4-0};
1367  bits <5> Rxx32;
1368  let Inst{4-0} = Rxx32{4-0};
1369}
1370class Enc_621fba : OpcodeHexagon {
1371  bits <5> Rs32;
1372  let Inst{20-16} = Rs32{4-0};
1373  bits <5> Gd32;
1374  let Inst{4-0} = Gd32{4-0};
1375}
1376class Enc_625deb : OpcodeHexagon {
1377  bits <4> Ii;
1378  let Inst{10-8} = Ii{3-1};
1379  bits <4> Rs16;
1380  let Inst{7-4} = Rs16{3-0};
1381  bits <4> Rt16;
1382  let Inst{3-0} = Rt16{3-0};
1383}
1384class Enc_6339d5 : OpcodeHexagon {
1385  bits <2> Ii;
1386  let Inst{13-13} = Ii{1-1};
1387  let Inst{7-7} = Ii{0-0};
1388  bits <2> Pv4;
1389  let Inst{6-5} = Pv4{1-0};
1390  bits <5> Rs32;
1391  let Inst{20-16} = Rs32{4-0};
1392  bits <5> Ru32;
1393  let Inst{12-8} = Ru32{4-0};
1394  bits <5> Rt32;
1395  let Inst{4-0} = Rt32{4-0};
1396}
1397class Enc_63eaeb : OpcodeHexagon {
1398  bits <2> Ii;
1399  let Inst{1-0} = Ii{1-0};
1400  bits <4> Rs16;
1401  let Inst{7-4} = Rs16{3-0};
1402}
1403class Enc_6413b6 : OpcodeHexagon {
1404  bits <11> Ii;
1405  let Inst{21-20} = Ii{10-9};
1406  let Inst{7-1} = Ii{8-2};
1407  bits <3> Ns8;
1408  let Inst{18-16} = Ns8{2-0};
1409  bits <5> n1;
1410  let Inst{29-29} = n1{4-4};
1411  let Inst{26-25} = n1{3-2};
1412  let Inst{23-23} = n1{1-1};
1413  let Inst{13-13} = n1{0-0};
1414}
1415class Enc_645d54 : OpcodeHexagon {
1416  bits <2> Ii;
1417  let Inst{13-13} = Ii{1-1};
1418  let Inst{5-5} = Ii{0-0};
1419  bits <5> Rss32;
1420  let Inst{20-16} = Rss32{4-0};
1421  bits <5> Rt32;
1422  let Inst{12-8} = Rt32{4-0};
1423  bits <5> Rdd32;
1424  let Inst{4-0} = Rdd32{4-0};
1425}
1426class Enc_65d691 : OpcodeHexagon {
1427  bits <2> Ps4;
1428  let Inst{17-16} = Ps4{1-0};
1429  bits <2> Pd4;
1430  let Inst{1-0} = Pd4{1-0};
1431}
1432class Enc_65f095 : OpcodeHexagon {
1433  bits <6> Ii;
1434  let Inst{6-3} = Ii{5-2};
1435  bits <2> Pv4;
1436  let Inst{1-0} = Pv4{1-0};
1437  bits <3> Nt8;
1438  let Inst{10-8} = Nt8{2-0};
1439  bits <5> Rx32;
1440  let Inst{20-16} = Rx32{4-0};
1441}
1442class Enc_667b39 : OpcodeHexagon {
1443  bits <5> Css32;
1444  let Inst{20-16} = Css32{4-0};
1445  bits <5> Rdd32;
1446  let Inst{4-0} = Rdd32{4-0};
1447}
1448class Enc_668704 : OpcodeHexagon {
1449  bits <11> Ii;
1450  let Inst{21-20} = Ii{10-9};
1451  let Inst{7-1} = Ii{8-2};
1452  bits <4> Rs16;
1453  let Inst{19-16} = Rs16{3-0};
1454  bits <5> n1;
1455  let Inst{28-28} = n1{4-4};
1456  let Inst{25-22} = n1{3-0};
1457}
1458class Enc_66bce1 : OpcodeHexagon {
1459  bits <11> Ii;
1460  let Inst{21-20} = Ii{10-9};
1461  let Inst{7-1} = Ii{8-2};
1462  bits <4> Rs16;
1463  let Inst{19-16} = Rs16{3-0};
1464  bits <4> Rd16;
1465  let Inst{11-8} = Rd16{3-0};
1466}
1467class Enc_690862 : OpcodeHexagon {
1468  bits <13> Ii;
1469  let Inst{26-25} = Ii{12-11};
1470  let Inst{13-13} = Ii{10-10};
1471  let Inst{7-0} = Ii{9-2};
1472  bits <5> Rs32;
1473  let Inst{20-16} = Rs32{4-0};
1474  bits <3> Nt8;
1475  let Inst{10-8} = Nt8{2-0};
1476}
1477class Enc_691712 : OpcodeHexagon {
1478  bits <2> Pv4;
1479  let Inst{12-11} = Pv4{1-0};
1480  bits <1> Mu2;
1481  let Inst{13-13} = Mu2{0-0};
1482  bits <5> Rx32;
1483  let Inst{20-16} = Rx32{4-0};
1484}
1485class Enc_69d63b : OpcodeHexagon {
1486  bits <11> Ii;
1487  let Inst{21-20} = Ii{10-9};
1488  let Inst{7-1} = Ii{8-2};
1489  bits <3> Ns8;
1490  let Inst{18-16} = Ns8{2-0};
1491}
1492class Enc_6a5972 : OpcodeHexagon {
1493  bits <11> Ii;
1494  let Inst{21-20} = Ii{10-9};
1495  let Inst{7-1} = Ii{8-2};
1496  bits <4> Rs16;
1497  let Inst{19-16} = Rs16{3-0};
1498  bits <4> Rt16;
1499  let Inst{11-8} = Rt16{3-0};
1500}
1501class Enc_6b197f : OpcodeHexagon {
1502  bits <4> Ii;
1503  let Inst{8-5} = Ii{3-0};
1504  bits <5> Ryy32;
1505  let Inst{4-0} = Ryy32{4-0};
1506  bits <5> Rx32;
1507  let Inst{20-16} = Rx32{4-0};
1508}
1509class Enc_6baed4 : OpcodeHexagon {
1510  bits <3> Ii;
1511  let Inst{10-8} = Ii{2-0};
1512  bits <2> Pv4;
1513  let Inst{12-11} = Pv4{1-0};
1514  bits <5> Rx32;
1515  let Inst{20-16} = Rx32{4-0};
1516}
1517class Enc_6c9440 : OpcodeHexagon {
1518  bits <10> Ii;
1519  let Inst{21-21} = Ii{9-9};
1520  let Inst{13-5} = Ii{8-0};
1521  bits <5> Rd32;
1522  let Inst{4-0} = Rd32{4-0};
1523}
1524class Enc_6c9ee0 : OpcodeHexagon {
1525  bits <3> Ii;
1526  let Inst{10-8} = Ii{2-0};
1527  bits <5> Rx32;
1528  let Inst{20-16} = Rx32{4-0};
1529}
1530class Enc_6f70ca : OpcodeHexagon {
1531  bits <8> Ii;
1532  let Inst{8-4} = Ii{7-3};
1533}
1534class Enc_6f83e7 : OpcodeHexagon {
1535  bits <2> Qv4;
1536  let Inst{23-22} = Qv4{1-0};
1537  bits <5> Vd32;
1538  let Inst{4-0} = Vd32{4-0};
1539}
1540class Enc_70b24b : OpcodeHexagon {
1541  bits <6> Ii;
1542  let Inst{8-5} = Ii{5-2};
1543  bits <1> Mu2;
1544  let Inst{13-13} = Mu2{0-0};
1545  bits <5> Rdd32;
1546  let Inst{4-0} = Rdd32{4-0};
1547  bits <5> Rx32;
1548  let Inst{20-16} = Rx32{4-0};
1549}
1550class Enc_70fb07 : OpcodeHexagon {
1551  bits <6> Ii;
1552  let Inst{13-8} = Ii{5-0};
1553  bits <5> Rss32;
1554  let Inst{20-16} = Rss32{4-0};
1555  bits <5> Rxx32;
1556  let Inst{4-0} = Rxx32{4-0};
1557}
1558class Enc_71bb9b : OpcodeHexagon {
1559  bits <5> Vu32;
1560  let Inst{12-8} = Vu32{4-0};
1561  bits <5> Vv32;
1562  let Inst{20-16} = Vv32{4-0};
1563  bits <5> Vdd32;
1564  let Inst{4-0} = Vdd32{4-0};
1565}
1566class Enc_71f1b4 : OpcodeHexagon {
1567  bits <6> Ii;
1568  let Inst{8-5} = Ii{5-2};
1569  bits <5> Rdd32;
1570  let Inst{4-0} = Rdd32{4-0};
1571  bits <5> Rx32;
1572  let Inst{20-16} = Rx32{4-0};
1573}
1574class Enc_7222b7 : OpcodeHexagon {
1575  bits <5> Rt32;
1576  let Inst{20-16} = Rt32{4-0};
1577  bits <2> Qd4;
1578  let Inst{1-0} = Qd4{1-0};
1579}
1580class Enc_724154 : OpcodeHexagon {
1581  bits <6> II;
1582  let Inst{5-0} = II{5-0};
1583  bits <3> Nt8;
1584  let Inst{10-8} = Nt8{2-0};
1585  bits <5> Re32;
1586  let Inst{20-16} = Re32{4-0};
1587}
1588class Enc_729ff7 : OpcodeHexagon {
1589  bits <3> Ii;
1590  let Inst{7-5} = Ii{2-0};
1591  bits <5> Rtt32;
1592  let Inst{12-8} = Rtt32{4-0};
1593  bits <5> Rss32;
1594  let Inst{20-16} = Rss32{4-0};
1595  bits <5> Rdd32;
1596  let Inst{4-0} = Rdd32{4-0};
1597}
1598class Enc_733b27 : OpcodeHexagon {
1599  bits <5> Ii;
1600  let Inst{8-5} = Ii{4-1};
1601  bits <2> Pt4;
1602  let Inst{10-9} = Pt4{1-0};
1603  bits <5> Rd32;
1604  let Inst{4-0} = Rd32{4-0};
1605  bits <5> Rx32;
1606  let Inst{20-16} = Rx32{4-0};
1607}
1608class Enc_736575 : OpcodeHexagon {
1609  bits <11> Ii;
1610  let Inst{21-20} = Ii{10-9};
1611  let Inst{7-1} = Ii{8-2};
1612  bits <4> Rs16;
1613  let Inst{19-16} = Rs16{3-0};
1614  bits <4> n1;
1615  let Inst{28-28} = n1{3-3};
1616  let Inst{25-23} = n1{2-0};
1617}
1618class Enc_74aef2 : OpcodeHexagon {
1619  bits <4> Ii;
1620  let Inst{8-5} = Ii{3-0};
1621  bits <1> Mu2;
1622  let Inst{13-13} = Mu2{0-0};
1623  bits <5> Ryy32;
1624  let Inst{4-0} = Ryy32{4-0};
1625  bits <5> Rx32;
1626  let Inst{20-16} = Rx32{4-0};
1627}
1628class Enc_74d4e5 : OpcodeHexagon {
1629  bits <1> Mu2;
1630  let Inst{13-13} = Mu2{0-0};
1631  bits <5> Rd32;
1632  let Inst{4-0} = Rd32{4-0};
1633  bits <5> Rx32;
1634  let Inst{20-16} = Rx32{4-0};
1635}
1636class Enc_770858 : OpcodeHexagon {
1637  bits <2> Ps4;
1638  let Inst{6-5} = Ps4{1-0};
1639  bits <5> Vu32;
1640  let Inst{12-8} = Vu32{4-0};
1641  bits <5> Vd32;
1642  let Inst{4-0} = Vd32{4-0};
1643}
1644class Enc_784502 : OpcodeHexagon {
1645  bits <3> Ii;
1646  let Inst{10-8} = Ii{2-0};
1647  bits <2> Pv4;
1648  let Inst{12-11} = Pv4{1-0};
1649  bits <3> Os8;
1650  let Inst{2-0} = Os8{2-0};
1651  bits <5> Rx32;
1652  let Inst{20-16} = Rx32{4-0};
1653}
1654class Enc_78cbf0 : OpcodeHexagon {
1655  bits <18> Ii;
1656  let Inst{26-25} = Ii{17-16};
1657  let Inst{20-16} = Ii{15-11};
1658  let Inst{13-13} = Ii{10-10};
1659  let Inst{7-0} = Ii{9-2};
1660  bits <3> Nt8;
1661  let Inst{10-8} = Nt8{2-0};
1662}
1663class Enc_78e566 : OpcodeHexagon {
1664  bits <2> Pt4;
1665  let Inst{9-8} = Pt4{1-0};
1666  bits <5> Rdd32;
1667  let Inst{4-0} = Rdd32{4-0};
1668}
1669class Enc_79b8c8 : OpcodeHexagon {
1670  bits <6> Ii;
1671  let Inst{6-3} = Ii{5-2};
1672  bits <1> Mu2;
1673  let Inst{13-13} = Mu2{0-0};
1674  bits <5> Rt32;
1675  let Inst{12-8} = Rt32{4-0};
1676  bits <5> Rx32;
1677  let Inst{20-16} = Rx32{4-0};
1678}
1679class Enc_7a0ea6 : OpcodeHexagon {
1680  bits <4> Rd16;
1681  let Inst{3-0} = Rd16{3-0};
1682  bits <1> n1;
1683  let Inst{9-9} = n1{0-0};
1684}
1685class Enc_7b523d : OpcodeHexagon {
1686  bits <5> Vu32;
1687  let Inst{12-8} = Vu32{4-0};
1688  bits <5> Vv32;
1689  let Inst{23-19} = Vv32{4-0};
1690  bits <3> Rt8;
1691  let Inst{18-16} = Rt8{2-0};
1692  bits <5> Vxx32;
1693  let Inst{4-0} = Vxx32{4-0};
1694}
1695class Enc_7b7ba8 : OpcodeHexagon {
1696  bits <2> Qu4;
1697  let Inst{9-8} = Qu4{1-0};
1698  bits <5> Rt32;
1699  let Inst{20-16} = Rt32{4-0};
1700  bits <5> Vd32;
1701  let Inst{4-0} = Vd32{4-0};
1702}
1703class Enc_7d1542 : OpcodeHexagon {
1704  bits <7> Ss128;
1705  let Inst{22-16} = Ss128{6-0};
1706  bits <5> Rd32;
1707  let Inst{4-0} = Rd32{4-0};
1708}
1709class Enc_7e5a82 : OpcodeHexagon {
1710  bits <5> Ii;
1711  let Inst{12-8} = Ii{4-0};
1712  bits <5> Rss32;
1713  let Inst{20-16} = Rss32{4-0};
1714  bits <5> Rdd32;
1715  let Inst{4-0} = Rdd32{4-0};
1716}
1717class Enc_7eaeb6 : OpcodeHexagon {
1718  bits <6> Ii;
1719  let Inst{6-3} = Ii{5-2};
1720  bits <2> Pv4;
1721  let Inst{1-0} = Pv4{1-0};
1722  bits <5> Rt32;
1723  let Inst{12-8} = Rt32{4-0};
1724  bits <5> Rx32;
1725  let Inst{20-16} = Rx32{4-0};
1726}
1727class Enc_7eb485 : OpcodeHexagon {
1728  bits <2> Ii;
1729  let Inst{13-13} = Ii{1-1};
1730  let Inst{6-6} = Ii{0-0};
1731  bits <6> II;
1732  let Inst{5-0} = II{5-0};
1733  bits <5> Ru32;
1734  let Inst{20-16} = Ru32{4-0};
1735  bits <3> Nt8;
1736  let Inst{10-8} = Nt8{2-0};
1737}
1738class Enc_7eee72 : OpcodeHexagon {
1739  bits <1> Mu2;
1740  let Inst{13-13} = Mu2{0-0};
1741  bits <5> Rdd32;
1742  let Inst{4-0} = Rdd32{4-0};
1743  bits <5> Rx32;
1744  let Inst{20-16} = Rx32{4-0};
1745}
1746class Enc_7f1a05 : OpcodeHexagon {
1747  bits <5> Ru32;
1748  let Inst{4-0} = Ru32{4-0};
1749  bits <5> Rs32;
1750  let Inst{20-16} = Rs32{4-0};
1751  bits <5> Ry32;
1752  let Inst{12-8} = Ry32{4-0};
1753}
1754class Enc_7fa7f6 : OpcodeHexagon {
1755  bits <6> II;
1756  let Inst{11-8} = II{5-2};
1757  let Inst{6-5} = II{1-0};
1758  bits <5> Rdd32;
1759  let Inst{4-0} = Rdd32{4-0};
1760  bits <5> Re32;
1761  let Inst{20-16} = Re32{4-0};
1762}
1763class Enc_800e04 : OpcodeHexagon {
1764  bits <11> Ii;
1765  let Inst{21-20} = Ii{10-9};
1766  let Inst{7-1} = Ii{8-2};
1767  bits <4> Rs16;
1768  let Inst{19-16} = Rs16{3-0};
1769  bits <6> n1;
1770  let Inst{28-28} = n1{5-5};
1771  let Inst{25-22} = n1{4-1};
1772  let Inst{13-13} = n1{0-0};
1773}
1774class Enc_802dc0 : OpcodeHexagon {
1775  bits <1> Ii;
1776  let Inst{8-8} = Ii{0-0};
1777  bits <2> Qv4;
1778  let Inst{23-22} = Qv4{1-0};
1779}
1780class Enc_81ac1d : OpcodeHexagon {
1781  bits <24> Ii;
1782  let Inst{24-16} = Ii{23-15};
1783  let Inst{13-1} = Ii{14-2};
1784}
1785class Enc_8203bb : OpcodeHexagon {
1786  bits <6> Ii;
1787  let Inst{12-7} = Ii{5-0};
1788  bits <8> II;
1789  let Inst{13-13} = II{7-7};
1790  let Inst{6-0} = II{6-0};
1791  bits <5> Rs32;
1792  let Inst{20-16} = Rs32{4-0};
1793}
1794class Enc_830e5d : OpcodeHexagon {
1795  bits <8> Ii;
1796  let Inst{12-5} = Ii{7-0};
1797  bits <8> II;
1798  let Inst{22-16} = II{7-1};
1799  let Inst{13-13} = II{0-0};
1800  bits <2> Pu4;
1801  let Inst{24-23} = Pu4{1-0};
1802  bits <5> Rd32;
1803  let Inst{4-0} = Rd32{4-0};
1804}
1805class Enc_831a7d : OpcodeHexagon {
1806  bits <5> Rss32;
1807  let Inst{20-16} = Rss32{4-0};
1808  bits <5> Rtt32;
1809  let Inst{12-8} = Rtt32{4-0};
1810  bits <5> Rxx32;
1811  let Inst{4-0} = Rxx32{4-0};
1812  bits <2> Pe4;
1813  let Inst{6-5} = Pe4{1-0};
1814}
1815class Enc_83ee64 : OpcodeHexagon {
1816  bits <5> Ii;
1817  let Inst{12-8} = Ii{4-0};
1818  bits <5> Rs32;
1819  let Inst{20-16} = Rs32{4-0};
1820  bits <2> Pd4;
1821  let Inst{1-0} = Pd4{1-0};
1822}
1823class Enc_84b2cd : OpcodeHexagon {
1824  bits <8> Ii;
1825  let Inst{12-7} = Ii{7-2};
1826  bits <5> II;
1827  let Inst{4-0} = II{4-0};
1828  bits <5> Rs32;
1829  let Inst{20-16} = Rs32{4-0};
1830}
1831class Enc_84bff1 : OpcodeHexagon {
1832  bits <2> Ii;
1833  let Inst{13-13} = Ii{1-1};
1834  let Inst{7-7} = Ii{0-0};
1835  bits <5> Rs32;
1836  let Inst{20-16} = Rs32{4-0};
1837  bits <5> Rt32;
1838  let Inst{12-8} = Rt32{4-0};
1839  bits <5> Rdd32;
1840  let Inst{4-0} = Rdd32{4-0};
1841}
1842class Enc_84d359 : OpcodeHexagon {
1843  bits <4> Ii;
1844  let Inst{3-0} = Ii{3-0};
1845  bits <4> Rs16;
1846  let Inst{7-4} = Rs16{3-0};
1847}
1848class Enc_85bf58 : OpcodeHexagon {
1849  bits <7> Ii;
1850  let Inst{6-3} = Ii{6-3};
1851  bits <5> Rtt32;
1852  let Inst{12-8} = Rtt32{4-0};
1853  bits <5> Rx32;
1854  let Inst{20-16} = Rx32{4-0};
1855}
1856class Enc_864a5a : OpcodeHexagon {
1857  bits <9> Ii;
1858  let Inst{12-8} = Ii{8-4};
1859  let Inst{4-3} = Ii{3-2};
1860  bits <5> Rs32;
1861  let Inst{20-16} = Rs32{4-0};
1862}
1863class Enc_865390 : OpcodeHexagon {
1864  bits <3> Ii;
1865  let Inst{10-8} = Ii{2-0};
1866  bits <2> Pv4;
1867  let Inst{12-11} = Pv4{1-0};
1868  bits <5> Vs32;
1869  let Inst{4-0} = Vs32{4-0};
1870  bits <5> Rx32;
1871  let Inst{20-16} = Rx32{4-0};
1872}
1873class Enc_86a14b : OpcodeHexagon {
1874  bits <8> Ii;
1875  let Inst{7-3} = Ii{7-3};
1876  bits <3> Rdd8;
1877  let Inst{2-0} = Rdd8{2-0};
1878}
1879class Enc_87c142 : OpcodeHexagon {
1880  bits <7> Ii;
1881  let Inst{8-4} = Ii{6-2};
1882  bits <4> Rt16;
1883  let Inst{3-0} = Rt16{3-0};
1884}
1885class Enc_88c16c : OpcodeHexagon {
1886  bits <5> Rss32;
1887  let Inst{20-16} = Rss32{4-0};
1888  bits <5> Rtt32;
1889  let Inst{12-8} = Rtt32{4-0};
1890  bits <5> Rxx32;
1891  let Inst{4-0} = Rxx32{4-0};
1892}
1893class Enc_88d4d9 : OpcodeHexagon {
1894  bits <2> Pu4;
1895  let Inst{9-8} = Pu4{1-0};
1896  bits <5> Rs32;
1897  let Inst{20-16} = Rs32{4-0};
1898}
1899class Enc_890909 : OpcodeHexagon {
1900  bits <5> Rs32;
1901  let Inst{20-16} = Rs32{4-0};
1902  bits <5> Rd32;
1903  let Inst{4-0} = Rd32{4-0};
1904  bits <2> Pe4;
1905  let Inst{6-5} = Pe4{1-0};
1906}
1907class Enc_895bd9 : OpcodeHexagon {
1908  bits <2> Qu4;
1909  let Inst{9-8} = Qu4{1-0};
1910  bits <5> Rt32;
1911  let Inst{20-16} = Rt32{4-0};
1912  bits <5> Vx32;
1913  let Inst{4-0} = Vx32{4-0};
1914}
1915class Enc_8b8927 : OpcodeHexagon {
1916  bits <5> Rt32;
1917  let Inst{20-16} = Rt32{4-0};
1918  bits <1> Mu2;
1919  let Inst{13-13} = Mu2{0-0};
1920  bits <5> Vv32;
1921  let Inst{4-0} = Vv32{4-0};
1922}
1923class Enc_8b8d61 : OpcodeHexagon {
1924  bits <6> Ii;
1925  let Inst{22-21} = Ii{5-4};
1926  let Inst{13-13} = Ii{3-3};
1927  let Inst{7-5} = Ii{2-0};
1928  bits <5> Rs32;
1929  let Inst{20-16} = Rs32{4-0};
1930  bits <5> Ru32;
1931  let Inst{4-0} = Ru32{4-0};
1932  bits <5> Rd32;
1933  let Inst{12-8} = Rd32{4-0};
1934}
1935class Enc_8bcba4 : OpcodeHexagon {
1936  bits <6> II;
1937  let Inst{5-0} = II{5-0};
1938  bits <5> Rt32;
1939  let Inst{12-8} = Rt32{4-0};
1940  bits <5> Re32;
1941  let Inst{20-16} = Re32{4-0};
1942}
1943class Enc_8c2412 : OpcodeHexagon {
1944  bits <2> Ps4;
1945  let Inst{6-5} = Ps4{1-0};
1946  bits <5> Vu32;
1947  let Inst{12-8} = Vu32{4-0};
1948  bits <5> Vv32;
1949  let Inst{20-16} = Vv32{4-0};
1950  bits <5> Vdd32;
1951  let Inst{4-0} = Vdd32{4-0};
1952}
1953class Enc_8c6530 : OpcodeHexagon {
1954  bits <5> Rtt32;
1955  let Inst{12-8} = Rtt32{4-0};
1956  bits <5> Rss32;
1957  let Inst{20-16} = Rss32{4-0};
1958  bits <2> Pu4;
1959  let Inst{6-5} = Pu4{1-0};
1960  bits <5> Rdd32;
1961  let Inst{4-0} = Rdd32{4-0};
1962}
1963class Enc_8d8a30 : OpcodeHexagon {
1964  bits <4> Ii;
1965  let Inst{13-13} = Ii{3-3};
1966  let Inst{10-8} = Ii{2-0};
1967  bits <2> Pv4;
1968  let Inst{12-11} = Pv4{1-0};
1969  bits <5> Rt32;
1970  let Inst{20-16} = Rt32{4-0};
1971  bits <5> Vd32;
1972  let Inst{4-0} = Vd32{4-0};
1973}
1974class Enc_8dbdfe : OpcodeHexagon {
1975  bits <8> Ii;
1976  let Inst{13-13} = Ii{7-7};
1977  let Inst{7-3} = Ii{6-2};
1978  bits <2> Pv4;
1979  let Inst{1-0} = Pv4{1-0};
1980  bits <5> Rs32;
1981  let Inst{20-16} = Rs32{4-0};
1982  bits <3> Nt8;
1983  let Inst{10-8} = Nt8{2-0};
1984}
1985class Enc_8dbe85 : OpcodeHexagon {
1986  bits <1> Mu2;
1987  let Inst{13-13} = Mu2{0-0};
1988  bits <3> Nt8;
1989  let Inst{10-8} = Nt8{2-0};
1990  bits <5> Rx32;
1991  let Inst{20-16} = Rx32{4-0};
1992}
1993class Enc_8dec2e : OpcodeHexagon {
1994  bits <5> Ii;
1995  let Inst{12-8} = Ii{4-0};
1996  bits <5> Rss32;
1997  let Inst{20-16} = Rss32{4-0};
1998  bits <5> Rd32;
1999  let Inst{4-0} = Rd32{4-0};
2000}
2001class Enc_8df4be : OpcodeHexagon {
2002  bits <17> Ii;
2003  let Inst{26-25} = Ii{16-15};
2004  let Inst{20-16} = Ii{14-10};
2005  let Inst{13-5} = Ii{9-1};
2006  bits <5> Rd32;
2007  let Inst{4-0} = Rd32{4-0};
2008}
2009class Enc_8e583a : OpcodeHexagon {
2010  bits <11> Ii;
2011  let Inst{21-20} = Ii{10-9};
2012  let Inst{7-1} = Ii{8-2};
2013  bits <4> Rs16;
2014  let Inst{19-16} = Rs16{3-0};
2015  bits <5> n1;
2016  let Inst{28-28} = n1{4-4};
2017  let Inst{25-23} = n1{3-1};
2018  let Inst{13-13} = n1{0-0};
2019}
2020class Enc_8f7633 : OpcodeHexagon {
2021  bits <5> Rs32;
2022  let Inst{20-16} = Rs32{4-0};
2023  bits <7> Sd128;
2024  let Inst{6-0} = Sd128{6-0};
2025}
2026class Enc_90cd8b : OpcodeHexagon {
2027  bits <5> Rss32;
2028  let Inst{20-16} = Rss32{4-0};
2029  bits <5> Rd32;
2030  let Inst{4-0} = Rd32{4-0};
2031}
2032class Enc_91b9fe : OpcodeHexagon {
2033  bits <5> Ii;
2034  let Inst{6-3} = Ii{4-1};
2035  bits <1> Mu2;
2036  let Inst{13-13} = Mu2{0-0};
2037  bits <3> Nt8;
2038  let Inst{10-8} = Nt8{2-0};
2039  bits <5> Rx32;
2040  let Inst{20-16} = Rx32{4-0};
2041}
2042class Enc_927852 : OpcodeHexagon {
2043  bits <5> Rss32;
2044  let Inst{20-16} = Rss32{4-0};
2045  bits <5> Rt32;
2046  let Inst{12-8} = Rt32{4-0};
2047  bits <5> Rdd32;
2048  let Inst{4-0} = Rdd32{4-0};
2049}
2050class Enc_928ca1 : OpcodeHexagon {
2051  bits <1> Mu2;
2052  let Inst{13-13} = Mu2{0-0};
2053  bits <5> Rtt32;
2054  let Inst{12-8} = Rtt32{4-0};
2055  bits <5> Rx32;
2056  let Inst{20-16} = Rx32{4-0};
2057}
2058class Enc_935d9b : OpcodeHexagon {
2059  bits <5> Ii;
2060  let Inst{6-3} = Ii{4-1};
2061  bits <1> Mu2;
2062  let Inst{13-13} = Mu2{0-0};
2063  bits <5> Rt32;
2064  let Inst{12-8} = Rt32{4-0};
2065  bits <5> Rx32;
2066  let Inst{20-16} = Rx32{4-0};
2067}
2068class Enc_93af4c : OpcodeHexagon {
2069  bits <7> Ii;
2070  let Inst{10-4} = Ii{6-0};
2071  bits <4> Rx16;
2072  let Inst{3-0} = Rx16{3-0};
2073}
2074class Enc_95441f : OpcodeHexagon {
2075  bits <5> Vu32;
2076  let Inst{12-8} = Vu32{4-0};
2077  bits <5> Vv32;
2078  let Inst{20-16} = Vv32{4-0};
2079  bits <2> Qd4;
2080  let Inst{1-0} = Qd4{1-0};
2081}
2082class Enc_96ce4f : OpcodeHexagon {
2083  bits <4> Ii;
2084  let Inst{6-3} = Ii{3-0};
2085  bits <1> Mu2;
2086  let Inst{13-13} = Mu2{0-0};
2087  bits <3> Nt8;
2088  let Inst{10-8} = Nt8{2-0};
2089  bits <5> Rx32;
2090  let Inst{20-16} = Rx32{4-0};
2091}
2092class Enc_97d666 : OpcodeHexagon {
2093  bits <4> Rs16;
2094  let Inst{7-4} = Rs16{3-0};
2095  bits <4> Rd16;
2096  let Inst{3-0} = Rd16{3-0};
2097}
2098class Enc_989021 : OpcodeHexagon {
2099  bits <5> Rt32;
2100  let Inst{20-16} = Rt32{4-0};
2101  bits <5> Vy32;
2102  let Inst{12-8} = Vy32{4-0};
2103  bits <5> Vx32;
2104  let Inst{4-0} = Vx32{4-0};
2105}
2106class Enc_98c0b8 : OpcodeHexagon {
2107  bits <2> Ii;
2108  let Inst{13-13} = Ii{1-1};
2109  let Inst{7-7} = Ii{0-0};
2110  bits <2> Pv4;
2111  let Inst{6-5} = Pv4{1-0};
2112  bits <5> Rs32;
2113  let Inst{20-16} = Rs32{4-0};
2114  bits <5> Rt32;
2115  let Inst{12-8} = Rt32{4-0};
2116  bits <5> Rdd32;
2117  let Inst{4-0} = Rdd32{4-0};
2118}
2119class Enc_9a33d5 : OpcodeHexagon {
2120  bits <7> Ii;
2121  let Inst{6-3} = Ii{6-3};
2122  bits <2> Pv4;
2123  let Inst{1-0} = Pv4{1-0};
2124  bits <5> Rtt32;
2125  let Inst{12-8} = Rtt32{4-0};
2126  bits <5> Rx32;
2127  let Inst{20-16} = Rx32{4-0};
2128}
2129class Enc_9ac432 : OpcodeHexagon {
2130  bits <2> Ps4;
2131  let Inst{17-16} = Ps4{1-0};
2132  bits <2> Pt4;
2133  let Inst{9-8} = Pt4{1-0};
2134  bits <2> Pu4;
2135  let Inst{7-6} = Pu4{1-0};
2136  bits <2> Pd4;
2137  let Inst{1-0} = Pd4{1-0};
2138}
2139class Enc_9b0bc1 : OpcodeHexagon {
2140  bits <2> Pu4;
2141  let Inst{6-5} = Pu4{1-0};
2142  bits <5> Rt32;
2143  let Inst{12-8} = Rt32{4-0};
2144  bits <5> Rs32;
2145  let Inst{20-16} = Rs32{4-0};
2146  bits <5> Rd32;
2147  let Inst{4-0} = Rd32{4-0};
2148}
2149class Enc_9be1de : OpcodeHexagon {
2150  bits <2> Qs4;
2151  let Inst{6-5} = Qs4{1-0};
2152  bits <5> Rt32;
2153  let Inst{20-16} = Rt32{4-0};
2154  bits <1> Mu2;
2155  let Inst{13-13} = Mu2{0-0};
2156  bits <5> Vv32;
2157  let Inst{12-8} = Vv32{4-0};
2158  bits <5> Vw32;
2159  let Inst{4-0} = Vw32{4-0};
2160}
2161class Enc_9cdba7 : OpcodeHexagon {
2162  bits <8> Ii;
2163  let Inst{12-5} = Ii{7-0};
2164  bits <5> Rs32;
2165  let Inst{20-16} = Rs32{4-0};
2166  bits <5> Rdd32;
2167  let Inst{4-0} = Rdd32{4-0};
2168}
2169class Enc_9d1247 : OpcodeHexagon {
2170  bits <7> Ii;
2171  let Inst{8-5} = Ii{6-3};
2172  bits <2> Pt4;
2173  let Inst{10-9} = Pt4{1-0};
2174  bits <5> Rdd32;
2175  let Inst{4-0} = Rdd32{4-0};
2176  bits <5> Rx32;
2177  let Inst{20-16} = Rx32{4-0};
2178}
2179class Enc_9e2e1c : OpcodeHexagon {
2180  bits <5> Ii;
2181  let Inst{8-5} = Ii{4-1};
2182  bits <1> Mu2;
2183  let Inst{13-13} = Mu2{0-0};
2184  bits <5> Ryy32;
2185  let Inst{4-0} = Ryy32{4-0};
2186  bits <5> Rx32;
2187  let Inst{20-16} = Rx32{4-0};
2188}
2189class Enc_9e4c3f : OpcodeHexagon {
2190  bits <6> II;
2191  let Inst{13-8} = II{5-0};
2192  bits <11> Ii;
2193  let Inst{21-20} = Ii{10-9};
2194  let Inst{7-1} = Ii{8-2};
2195  bits <4> Rd16;
2196  let Inst{19-16} = Rd16{3-0};
2197}
2198class Enc_9ea4cf : OpcodeHexagon {
2199  bits <2> Ii;
2200  let Inst{13-13} = Ii{1-1};
2201  let Inst{6-6} = Ii{0-0};
2202  bits <6> II;
2203  let Inst{5-0} = II{5-0};
2204  bits <5> Ru32;
2205  let Inst{20-16} = Ru32{4-0};
2206  bits <5> Rt32;
2207  let Inst{12-8} = Rt32{4-0};
2208}
2209class Enc_9fae8a : OpcodeHexagon {
2210  bits <6> Ii;
2211  let Inst{13-8} = Ii{5-0};
2212  bits <5> Rs32;
2213  let Inst{20-16} = Rs32{4-0};
2214  bits <5> Rd32;
2215  let Inst{4-0} = Rd32{4-0};
2216}
2217class Enc_a05677 : OpcodeHexagon {
2218  bits <5> Ii;
2219  let Inst{12-8} = Ii{4-0};
2220  bits <5> Rs32;
2221  let Inst{20-16} = Rs32{4-0};
2222  bits <5> Rd32;
2223  let Inst{4-0} = Rd32{4-0};
2224}
2225class Enc_a1640c : OpcodeHexagon {
2226  bits <6> Ii;
2227  let Inst{13-8} = Ii{5-0};
2228  bits <5> Rss32;
2229  let Inst{20-16} = Rss32{4-0};
2230  bits <5> Rd32;
2231  let Inst{4-0} = Rd32{4-0};
2232}
2233class Enc_a198f6 : OpcodeHexagon {
2234  bits <7> Ii;
2235  let Inst{10-5} = Ii{6-1};
2236  bits <2> Pt4;
2237  let Inst{12-11} = Pt4{1-0};
2238  bits <5> Rs32;
2239  let Inst{20-16} = Rs32{4-0};
2240  bits <5> Rd32;
2241  let Inst{4-0} = Rd32{4-0};
2242}
2243class Enc_a1e29d : OpcodeHexagon {
2244  bits <5> Ii;
2245  let Inst{12-8} = Ii{4-0};
2246  bits <5> II;
2247  let Inst{22-21} = II{4-3};
2248  let Inst{7-5} = II{2-0};
2249  bits <5> Rs32;
2250  let Inst{20-16} = Rs32{4-0};
2251  bits <5> Rx32;
2252  let Inst{4-0} = Rx32{4-0};
2253}
2254class Enc_a21d47 : OpcodeHexagon {
2255  bits <6> Ii;
2256  let Inst{10-5} = Ii{5-0};
2257  bits <2> Pt4;
2258  let Inst{12-11} = Pt4{1-0};
2259  bits <5> Rs32;
2260  let Inst{20-16} = Rs32{4-0};
2261  bits <5> Rd32;
2262  let Inst{4-0} = Rd32{4-0};
2263}
2264class Enc_a255dc : OpcodeHexagon {
2265  bits <3> Ii;
2266  let Inst{10-8} = Ii{2-0};
2267  bits <5> Vd32;
2268  let Inst{4-0} = Vd32{4-0};
2269  bits <5> Rx32;
2270  let Inst{20-16} = Rx32{4-0};
2271}
2272class Enc_a27588 : OpcodeHexagon {
2273  bits <11> Ii;
2274  let Inst{26-25} = Ii{10-9};
2275  let Inst{13-5} = Ii{8-0};
2276  bits <5> Rs32;
2277  let Inst{20-16} = Rs32{4-0};
2278  bits <5> Ryy32;
2279  let Inst{4-0} = Ryy32{4-0};
2280}
2281class Enc_a30110 : OpcodeHexagon {
2282  bits <5> Vu32;
2283  let Inst{12-8} = Vu32{4-0};
2284  bits <5> Vv32;
2285  let Inst{23-19} = Vv32{4-0};
2286  bits <3> Rt8;
2287  let Inst{18-16} = Rt8{2-0};
2288  bits <5> Vd32;
2289  let Inst{4-0} = Vd32{4-0};
2290}
2291class Enc_a33d04 : OpcodeHexagon {
2292  bits <5> Vuu32;
2293  let Inst{12-8} = Vuu32{4-0};
2294  bits <5> Vd32;
2295  let Inst{4-0} = Vd32{4-0};
2296}
2297class Enc_a42857 : OpcodeHexagon {
2298  bits <11> Ii;
2299  let Inst{21-20} = Ii{10-9};
2300  let Inst{7-1} = Ii{8-2};
2301  bits <4> Rs16;
2302  let Inst{19-16} = Rs16{3-0};
2303  bits <5> n1;
2304  let Inst{28-28} = n1{4-4};
2305  let Inst{24-22} = n1{3-1};
2306  let Inst{8-8} = n1{0-0};
2307}
2308class Enc_a4ef14 : OpcodeHexagon {
2309  bits <5> Rd32;
2310  let Inst{4-0} = Rd32{4-0};
2311}
2312class Enc_a51a9a : OpcodeHexagon {
2313  bits <8> Ii;
2314  let Inst{12-8} = Ii{7-3};
2315  let Inst{4-2} = Ii{2-0};
2316}
2317class Enc_a56825 : OpcodeHexagon {
2318  bits <5> Rss32;
2319  let Inst{20-16} = Rss32{4-0};
2320  bits <5> Rtt32;
2321  let Inst{12-8} = Rtt32{4-0};
2322  bits <5> Rdd32;
2323  let Inst{4-0} = Rdd32{4-0};
2324}
2325class Enc_a568d4 : OpcodeHexagon {
2326  bits <5> Rt32;
2327  let Inst{12-8} = Rt32{4-0};
2328  bits <5> Rs32;
2329  let Inst{20-16} = Rs32{4-0};
2330  bits <5> Rx32;
2331  let Inst{4-0} = Rx32{4-0};
2332}
2333class Enc_a5ed8a : OpcodeHexagon {
2334  bits <5> Rt32;
2335  let Inst{20-16} = Rt32{4-0};
2336  bits <5> Vd32;
2337  let Inst{4-0} = Vd32{4-0};
2338}
2339class Enc_a641d0 : OpcodeHexagon {
2340  bits <5> Rt32;
2341  let Inst{20-16} = Rt32{4-0};
2342  bits <1> Mu2;
2343  let Inst{13-13} = Mu2{0-0};
2344  bits <5> Vvv32;
2345  let Inst{12-8} = Vvv32{4-0};
2346  bits <5> Vw32;
2347  let Inst{4-0} = Vw32{4-0};
2348}
2349class Enc_a6853f : OpcodeHexagon {
2350  bits <11> Ii;
2351  let Inst{21-20} = Ii{10-9};
2352  let Inst{7-1} = Ii{8-2};
2353  bits <3> Ns8;
2354  let Inst{18-16} = Ns8{2-0};
2355  bits <6> n1;
2356  let Inst{29-29} = n1{5-5};
2357  let Inst{26-25} = n1{4-3};
2358  let Inst{23-22} = n1{2-1};
2359  let Inst{13-13} = n1{0-0};
2360}
2361class Enc_a6ce9c : OpcodeHexagon {
2362  bits <6> Ii;
2363  let Inst{3-0} = Ii{5-2};
2364  bits <4> Rs16;
2365  let Inst{7-4} = Rs16{3-0};
2366}
2367class Enc_a705fc : OpcodeHexagon {
2368  bits <5> Rss32;
2369  let Inst{20-16} = Rss32{4-0};
2370  bits <7> Sdd128;
2371  let Inst{6-0} = Sdd128{6-0};
2372}
2373class Enc_a7341a : OpcodeHexagon {
2374  bits <5> Vu32;
2375  let Inst{12-8} = Vu32{4-0};
2376  bits <5> Vv32;
2377  let Inst{20-16} = Vv32{4-0};
2378  bits <5> Vx32;
2379  let Inst{4-0} = Vx32{4-0};
2380}
2381class Enc_a75aa6 : OpcodeHexagon {
2382  bits <5> Rs32;
2383  let Inst{20-16} = Rs32{4-0};
2384  bits <5> Rt32;
2385  let Inst{12-8} = Rt32{4-0};
2386  bits <1> Mu2;
2387  let Inst{13-13} = Mu2{0-0};
2388}
2389class Enc_a7b8e8 : OpcodeHexagon {
2390  bits <6> Ii;
2391  let Inst{22-21} = Ii{5-4};
2392  let Inst{13-13} = Ii{3-3};
2393  let Inst{7-5} = Ii{2-0};
2394  bits <5> Rs32;
2395  let Inst{20-16} = Rs32{4-0};
2396  bits <5> Rt32;
2397  let Inst{12-8} = Rt32{4-0};
2398  bits <5> Rd32;
2399  let Inst{4-0} = Rd32{4-0};
2400}
2401class Enc_a803e0 : OpcodeHexagon {
2402  bits <7> Ii;
2403  let Inst{12-7} = Ii{6-1};
2404  bits <8> II;
2405  let Inst{13-13} = II{7-7};
2406  let Inst{6-0} = II{6-0};
2407  bits <5> Rs32;
2408  let Inst{20-16} = Rs32{4-0};
2409}
2410class Enc_a90628 : OpcodeHexagon {
2411  bits <2> Qv4;
2412  let Inst{23-22} = Qv4{1-0};
2413  bits <5> Vu32;
2414  let Inst{12-8} = Vu32{4-0};
2415  bits <5> Vx32;
2416  let Inst{4-0} = Vx32{4-0};
2417}
2418class Enc_a94f3b : OpcodeHexagon {
2419  bits <5> Rs32;
2420  let Inst{20-16} = Rs32{4-0};
2421  bits <5> Rt32;
2422  let Inst{12-8} = Rt32{4-0};
2423  bits <5> Rd32;
2424  let Inst{4-0} = Rd32{4-0};
2425  bits <2> Pe4;
2426  let Inst{6-5} = Pe4{1-0};
2427}
2428class Enc_aad80c : OpcodeHexagon {
2429  bits <5> Vuu32;
2430  let Inst{12-8} = Vuu32{4-0};
2431  bits <5> Rt32;
2432  let Inst{20-16} = Rt32{4-0};
2433  bits <5> Vdd32;
2434  let Inst{4-0} = Vdd32{4-0};
2435}
2436class Enc_acd6ed : OpcodeHexagon {
2437  bits <9> Ii;
2438  let Inst{10-5} = Ii{8-3};
2439  bits <2> Pt4;
2440  let Inst{12-11} = Pt4{1-0};
2441  bits <5> Rs32;
2442  let Inst{20-16} = Rs32{4-0};
2443  bits <5> Rdd32;
2444  let Inst{4-0} = Rdd32{4-0};
2445}
2446class Enc_ad1831 : OpcodeHexagon {
2447  bits <16> Ii;
2448  let Inst{26-25} = Ii{15-14};
2449  let Inst{20-16} = Ii{13-9};
2450  let Inst{13-13} = Ii{8-8};
2451  let Inst{7-0} = Ii{7-0};
2452  bits <3> Nt8;
2453  let Inst{10-8} = Nt8{2-0};
2454}
2455class Enc_ad1c74 : OpcodeHexagon {
2456  bits <11> Ii;
2457  let Inst{21-20} = Ii{10-9};
2458  let Inst{7-1} = Ii{8-2};
2459  bits <4> Rs16;
2460  let Inst{19-16} = Rs16{3-0};
2461}
2462class Enc_ad9bef : OpcodeHexagon {
2463  bits <5> Vu32;
2464  let Inst{12-8} = Vu32{4-0};
2465  bits <5> Rtt32;
2466  let Inst{20-16} = Rtt32{4-0};
2467  bits <5> Vxx32;
2468  let Inst{4-0} = Vxx32{4-0};
2469}
2470class Enc_adf111 : OpcodeHexagon {
2471  bits <5> Vu32;
2472  let Inst{12-8} = Vu32{4-0};
2473  bits <5> Rt32;
2474  let Inst{20-16} = Rt32{4-0};
2475  bits <2> Qx4;
2476  let Inst{1-0} = Qx4{1-0};
2477}
2478class Enc_b00112 : OpcodeHexagon {
2479  bits <5> Rss32;
2480  let Inst{20-16} = Rss32{4-0};
2481  bits <5> Rtt32;
2482  let Inst{12-8} = Rtt32{4-0};
2483}
2484class Enc_b05839 : OpcodeHexagon {
2485  bits <7> Ii;
2486  let Inst{8-5} = Ii{6-3};
2487  bits <1> Mu2;
2488  let Inst{13-13} = Mu2{0-0};
2489  bits <5> Rdd32;
2490  let Inst{4-0} = Rdd32{4-0};
2491  bits <5> Rx32;
2492  let Inst{20-16} = Rx32{4-0};
2493}
2494class Enc_b087ac : OpcodeHexagon {
2495  bits <5> Vu32;
2496  let Inst{12-8} = Vu32{4-0};
2497  bits <5> Rt32;
2498  let Inst{20-16} = Rt32{4-0};
2499  bits <5> Vd32;
2500  let Inst{4-0} = Vd32{4-0};
2501}
2502class Enc_b0e9d8 : OpcodeHexagon {
2503  bits <10> Ii;
2504  let Inst{21-21} = Ii{9-9};
2505  let Inst{13-5} = Ii{8-0};
2506  bits <5> Rs32;
2507  let Inst{20-16} = Rs32{4-0};
2508  bits <5> Rx32;
2509  let Inst{4-0} = Rx32{4-0};
2510}
2511class Enc_b15941 : OpcodeHexagon {
2512  bits <4> Ii;
2513  let Inst{6-3} = Ii{3-0};
2514  bits <1> Mu2;
2515  let Inst{13-13} = Mu2{0-0};
2516  bits <5> Rt32;
2517  let Inst{12-8} = Rt32{4-0};
2518  bits <5> Rx32;
2519  let Inst{20-16} = Rx32{4-0};
2520}
2521class Enc_b1e1fb : OpcodeHexagon {
2522  bits <11> Ii;
2523  let Inst{21-20} = Ii{10-9};
2524  let Inst{7-1} = Ii{8-2};
2525  bits <4> Rs16;
2526  let Inst{19-16} = Rs16{3-0};
2527  bits <5> n1;
2528  let Inst{28-28} = n1{4-4};
2529  let Inst{25-23} = n1{3-1};
2530  let Inst{8-8} = n1{0-0};
2531}
2532class Enc_b388cf : OpcodeHexagon {
2533  bits <5> Ii;
2534  let Inst{12-8} = Ii{4-0};
2535  bits <5> II;
2536  let Inst{22-21} = II{4-3};
2537  let Inst{7-5} = II{2-0};
2538  bits <5> Rs32;
2539  let Inst{20-16} = Rs32{4-0};
2540  bits <5> Rd32;
2541  let Inst{4-0} = Rd32{4-0};
2542}
2543class Enc_b38ffc : OpcodeHexagon {
2544  bits <4> Ii;
2545  let Inst{11-8} = Ii{3-0};
2546  bits <4> Rs16;
2547  let Inst{7-4} = Rs16{3-0};
2548  bits <4> Rt16;
2549  let Inst{3-0} = Rt16{3-0};
2550}
2551class Enc_b43b67 : OpcodeHexagon {
2552  bits <5> Vu32;
2553  let Inst{12-8} = Vu32{4-0};
2554  bits <5> Vv32;
2555  let Inst{20-16} = Vv32{4-0};
2556  bits <5> Vd32;
2557  let Inst{4-0} = Vd32{4-0};
2558  bits <2> Qx4;
2559  let Inst{6-5} = Qx4{1-0};
2560}
2561class Enc_b4e6cf : OpcodeHexagon {
2562  bits <10> Ii;
2563  let Inst{21-21} = Ii{9-9};
2564  let Inst{13-5} = Ii{8-0};
2565  bits <5> Ru32;
2566  let Inst{4-0} = Ru32{4-0};
2567  bits <5> Rx32;
2568  let Inst{20-16} = Rx32{4-0};
2569}
2570class Enc_b62ef7 : OpcodeHexagon {
2571  bits <3> Ii;
2572  let Inst{10-8} = Ii{2-0};
2573  bits <5> Vs32;
2574  let Inst{4-0} = Vs32{4-0};
2575  bits <5> Rx32;
2576  let Inst{20-16} = Rx32{4-0};
2577}
2578class Enc_b72622 : OpcodeHexagon {
2579  bits <2> Ii;
2580  let Inst{13-13} = Ii{1-1};
2581  let Inst{5-5} = Ii{0-0};
2582  bits <5> Rss32;
2583  let Inst{20-16} = Rss32{4-0};
2584  bits <5> Rt32;
2585  let Inst{12-8} = Rt32{4-0};
2586  bits <5> Rxx32;
2587  let Inst{4-0} = Rxx32{4-0};
2588}
2589class Enc_b78edd : OpcodeHexagon {
2590  bits <11> Ii;
2591  let Inst{21-20} = Ii{10-9};
2592  let Inst{7-1} = Ii{8-2};
2593  bits <4> Rs16;
2594  let Inst{19-16} = Rs16{3-0};
2595  bits <4> n1;
2596  let Inst{28-28} = n1{3-3};
2597  let Inst{24-23} = n1{2-1};
2598  let Inst{8-8} = n1{0-0};
2599}
2600class Enc_b7fad3 : OpcodeHexagon {
2601  bits <2> Pv4;
2602  let Inst{9-8} = Pv4{1-0};
2603  bits <5> Rs32;
2604  let Inst{20-16} = Rs32{4-0};
2605  bits <5> Rdd32;
2606  let Inst{4-0} = Rdd32{4-0};
2607}
2608class Enc_b8309d : OpcodeHexagon {
2609  bits <9> Ii;
2610  let Inst{8-3} = Ii{8-3};
2611  bits <3> Rtt8;
2612  let Inst{2-0} = Rtt8{2-0};
2613}
2614class Enc_b84c4c : OpcodeHexagon {
2615  bits <6> Ii;
2616  let Inst{13-8} = Ii{5-0};
2617  bits <6> II;
2618  let Inst{23-21} = II{5-3};
2619  let Inst{7-5} = II{2-0};
2620  bits <5> Rss32;
2621  let Inst{20-16} = Rss32{4-0};
2622  bits <5> Rdd32;
2623  let Inst{4-0} = Rdd32{4-0};
2624}
2625class Enc_b886fd : OpcodeHexagon {
2626  bits <5> Ii;
2627  let Inst{6-3} = Ii{4-1};
2628  bits <2> Pv4;
2629  let Inst{1-0} = Pv4{1-0};
2630  bits <5> Rt32;
2631  let Inst{12-8} = Rt32{4-0};
2632  bits <5> Rx32;
2633  let Inst{20-16} = Rx32{4-0};
2634}
2635class Enc_b8c967 : OpcodeHexagon {
2636  bits <8> Ii;
2637  let Inst{12-5} = Ii{7-0};
2638  bits <5> Rs32;
2639  let Inst{20-16} = Rs32{4-0};
2640  bits <5> Rd32;
2641  let Inst{4-0} = Rd32{4-0};
2642}
2643class Enc_b909d2 : OpcodeHexagon {
2644  bits <11> Ii;
2645  let Inst{21-20} = Ii{10-9};
2646  let Inst{7-1} = Ii{8-2};
2647  bits <4> Rs16;
2648  let Inst{19-16} = Rs16{3-0};
2649  bits <7> n1;
2650  let Inst{28-28} = n1{6-6};
2651  let Inst{25-22} = n1{5-2};
2652  let Inst{13-13} = n1{1-1};
2653  let Inst{8-8} = n1{0-0};
2654}
2655class Enc_b91167 : OpcodeHexagon {
2656  bits <2> Ii;
2657  let Inst{6-5} = Ii{1-0};
2658  bits <5> Vuu32;
2659  let Inst{12-8} = Vuu32{4-0};
2660  bits <5> Vvv32;
2661  let Inst{20-16} = Vvv32{4-0};
2662  bits <5> Vdd32;
2663  let Inst{4-0} = Vdd32{4-0};
2664}
2665class Enc_b97f71 : OpcodeHexagon {
2666  bits <6> Ii;
2667  let Inst{8-5} = Ii{5-2};
2668  bits <2> Pt4;
2669  let Inst{10-9} = Pt4{1-0};
2670  bits <5> Rd32;
2671  let Inst{4-0} = Rd32{4-0};
2672  bits <5> Rx32;
2673  let Inst{20-16} = Rx32{4-0};
2674}
2675class Enc_b9c5fb : OpcodeHexagon {
2676  bits <5> Rss32;
2677  let Inst{20-16} = Rss32{4-0};
2678  bits <5> Rdd32;
2679  let Inst{4-0} = Rdd32{4-0};
2680}
2681class Enc_bc03e5 : OpcodeHexagon {
2682  bits <17> Ii;
2683  let Inst{26-25} = Ii{16-15};
2684  let Inst{20-16} = Ii{14-10};
2685  let Inst{13-13} = Ii{9-9};
2686  let Inst{7-0} = Ii{8-1};
2687  bits <3> Nt8;
2688  let Inst{10-8} = Nt8{2-0};
2689}
2690class Enc_bd0b33 : OpcodeHexagon {
2691  bits <10> Ii;
2692  let Inst{21-21} = Ii{9-9};
2693  let Inst{13-5} = Ii{8-0};
2694  bits <5> Rs32;
2695  let Inst{20-16} = Rs32{4-0};
2696  bits <2> Pd4;
2697  let Inst{1-0} = Pd4{1-0};
2698}
2699class Enc_bd1cbc : OpcodeHexagon {
2700  bits <5> Ii;
2701  let Inst{8-5} = Ii{4-1};
2702  bits <5> Ryy32;
2703  let Inst{4-0} = Ryy32{4-0};
2704  bits <5> Rx32;
2705  let Inst{20-16} = Rx32{4-0};
2706}
2707class Enc_bd6011 : OpcodeHexagon {
2708  bits <5> Rt32;
2709  let Inst{12-8} = Rt32{4-0};
2710  bits <5> Rs32;
2711  let Inst{20-16} = Rs32{4-0};
2712  bits <5> Rd32;
2713  let Inst{4-0} = Rd32{4-0};
2714}
2715class Enc_bd811a : OpcodeHexagon {
2716  bits <5> Rs32;
2717  let Inst{20-16} = Rs32{4-0};
2718  bits <5> Cd32;
2719  let Inst{4-0} = Cd32{4-0};
2720}
2721class Enc_bddee3 : OpcodeHexagon {
2722  bits <5> Vu32;
2723  let Inst{12-8} = Vu32{4-0};
2724  bits <5> Vyyyy32;
2725  let Inst{4-0} = Vyyyy32{4-0};
2726  bits <3> Rx8;
2727  let Inst{18-16} = Rx8{2-0};
2728}
2729class Enc_be32a5 : OpcodeHexagon {
2730  bits <5> Rs32;
2731  let Inst{20-16} = Rs32{4-0};
2732  bits <5> Rt32;
2733  let Inst{12-8} = Rt32{4-0};
2734  bits <5> Rdd32;
2735  let Inst{4-0} = Rdd32{4-0};
2736}
2737class Enc_bfbf03 : OpcodeHexagon {
2738  bits <2> Qs4;
2739  let Inst{9-8} = Qs4{1-0};
2740  bits <2> Qd4;
2741  let Inst{1-0} = Qd4{1-0};
2742}
2743class Enc_c0cdde : OpcodeHexagon {
2744  bits <9> Ii;
2745  let Inst{13-5} = Ii{8-0};
2746  bits <5> Rs32;
2747  let Inst{20-16} = Rs32{4-0};
2748  bits <2> Pd4;
2749  let Inst{1-0} = Pd4{1-0};
2750}
2751class Enc_c175d0 : OpcodeHexagon {
2752  bits <4> Ii;
2753  let Inst{11-8} = Ii{3-0};
2754  bits <4> Rs16;
2755  let Inst{7-4} = Rs16{3-0};
2756  bits <4> Rd16;
2757  let Inst{3-0} = Rd16{3-0};
2758}
2759class Enc_c1d806 : OpcodeHexagon {
2760  bits <5> Vu32;
2761  let Inst{12-8} = Vu32{4-0};
2762  bits <5> Vv32;
2763  let Inst{20-16} = Vv32{4-0};
2764  bits <5> Vd32;
2765  let Inst{4-0} = Vd32{4-0};
2766  bits <2> Qe4;
2767  let Inst{6-5} = Qe4{1-0};
2768}
2769class Enc_c2b48e : OpcodeHexagon {
2770  bits <5> Rs32;
2771  let Inst{20-16} = Rs32{4-0};
2772  bits <5> Rt32;
2773  let Inst{12-8} = Rt32{4-0};
2774  bits <2> Pd4;
2775  let Inst{1-0} = Pd4{1-0};
2776}
2777class Enc_c31910 : OpcodeHexagon {
2778  bits <8> Ii;
2779  let Inst{23-21} = Ii{7-5};
2780  let Inst{13-13} = Ii{4-4};
2781  let Inst{7-5} = Ii{3-1};
2782  let Inst{3-3} = Ii{0-0};
2783  bits <5> II;
2784  let Inst{12-8} = II{4-0};
2785  bits <5> Rx32;
2786  let Inst{20-16} = Rx32{4-0};
2787}
2788class Enc_c4dc92 : OpcodeHexagon {
2789  bits <2> Qv4;
2790  let Inst{23-22} = Qv4{1-0};
2791  bits <5> Vu32;
2792  let Inst{12-8} = Vu32{4-0};
2793  bits <5> Vd32;
2794  let Inst{4-0} = Vd32{4-0};
2795}
2796class Enc_c6220b : OpcodeHexagon {
2797  bits <2> Ii;
2798  let Inst{13-13} = Ii{1-1};
2799  let Inst{7-7} = Ii{0-0};
2800  bits <5> Rs32;
2801  let Inst{20-16} = Rs32{4-0};
2802  bits <5> Ru32;
2803  let Inst{12-8} = Ru32{4-0};
2804  bits <3> Nt8;
2805  let Inst{2-0} = Nt8{2-0};
2806}
2807class Enc_c7a204 : OpcodeHexagon {
2808  bits <6> II;
2809  let Inst{5-0} = II{5-0};
2810  bits <5> Rtt32;
2811  let Inst{12-8} = Rtt32{4-0};
2812  bits <5> Re32;
2813  let Inst{20-16} = Re32{4-0};
2814}
2815class Enc_c7cd90 : OpcodeHexagon {
2816  bits <4> Ii;
2817  let Inst{6-3} = Ii{3-0};
2818  bits <3> Nt8;
2819  let Inst{10-8} = Nt8{2-0};
2820  bits <5> Rx32;
2821  let Inst{20-16} = Rx32{4-0};
2822}
2823class Enc_c85e2a : OpcodeHexagon {
2824  bits <5> Ii;
2825  let Inst{12-8} = Ii{4-0};
2826  bits <5> II;
2827  let Inst{22-21} = II{4-3};
2828  let Inst{7-5} = II{2-0};
2829  bits <5> Rd32;
2830  let Inst{4-0} = Rd32{4-0};
2831}
2832class Enc_c90aca : OpcodeHexagon {
2833  bits <8> Ii;
2834  let Inst{12-5} = Ii{7-0};
2835  bits <5> Rs32;
2836  let Inst{20-16} = Rs32{4-0};
2837  bits <5> Rx32;
2838  let Inst{4-0} = Rx32{4-0};
2839}
2840class Enc_c9a18e : OpcodeHexagon {
2841  bits <11> Ii;
2842  let Inst{21-20} = Ii{10-9};
2843  let Inst{7-1} = Ii{8-2};
2844  bits <3> Ns8;
2845  let Inst{18-16} = Ns8{2-0};
2846  bits <5> Rt32;
2847  let Inst{12-8} = Rt32{4-0};
2848}
2849class Enc_c9e3bc : OpcodeHexagon {
2850  bits <4> Ii;
2851  let Inst{13-13} = Ii{3-3};
2852  let Inst{10-8} = Ii{2-0};
2853  bits <5> Rt32;
2854  let Inst{20-16} = Rt32{4-0};
2855  bits <5> Vs32;
2856  let Inst{4-0} = Vs32{4-0};
2857}
2858class Enc_ca3887 : OpcodeHexagon {
2859  bits <5> Rs32;
2860  let Inst{20-16} = Rs32{4-0};
2861  bits <5> Rt32;
2862  let Inst{12-8} = Rt32{4-0};
2863}
2864class Enc_cb4b4e : OpcodeHexagon {
2865  bits <2> Pu4;
2866  let Inst{6-5} = Pu4{1-0};
2867  bits <5> Rs32;
2868  let Inst{20-16} = Rs32{4-0};
2869  bits <5> Rt32;
2870  let Inst{12-8} = Rt32{4-0};
2871  bits <5> Rdd32;
2872  let Inst{4-0} = Rdd32{4-0};
2873}
2874class Enc_cb785b : OpcodeHexagon {
2875  bits <5> Vu32;
2876  let Inst{12-8} = Vu32{4-0};
2877  bits <5> Rtt32;
2878  let Inst{20-16} = Rtt32{4-0};
2879  bits <5> Vdd32;
2880  let Inst{4-0} = Vdd32{4-0};
2881}
2882class Enc_cb9321 : OpcodeHexagon {
2883  bits <16> Ii;
2884  let Inst{27-21} = Ii{15-9};
2885  let Inst{13-5} = Ii{8-0};
2886  bits <5> Rs32;
2887  let Inst{20-16} = Rs32{4-0};
2888  bits <5> Rd32;
2889  let Inst{4-0} = Rd32{4-0};
2890}
2891class Enc_cc449f : OpcodeHexagon {
2892  bits <4> Ii;
2893  let Inst{6-3} = Ii{3-0};
2894  bits <2> Pv4;
2895  let Inst{1-0} = Pv4{1-0};
2896  bits <5> Rt32;
2897  let Inst{12-8} = Rt32{4-0};
2898  bits <5> Rx32;
2899  let Inst{20-16} = Rx32{4-0};
2900}
2901class Enc_cc857d : OpcodeHexagon {
2902  bits <5> Vuu32;
2903  let Inst{12-8} = Vuu32{4-0};
2904  bits <5> Rt32;
2905  let Inst{20-16} = Rt32{4-0};
2906  bits <5> Vx32;
2907  let Inst{4-0} = Vx32{4-0};
2908}
2909class Enc_cd4705 : OpcodeHexagon {
2910  bits <3> Ii;
2911  let Inst{7-5} = Ii{2-0};
2912  bits <5> Vu32;
2913  let Inst{12-8} = Vu32{4-0};
2914  bits <5> Vv32;
2915  let Inst{20-16} = Vv32{4-0};
2916  bits <5> Vx32;
2917  let Inst{4-0} = Vx32{4-0};
2918}
2919class Enc_cd82bc : OpcodeHexagon {
2920  bits <4> Ii;
2921  let Inst{21-21} = Ii{3-3};
2922  let Inst{7-5} = Ii{2-0};
2923  bits <6> II;
2924  let Inst{13-8} = II{5-0};
2925  bits <5> Rs32;
2926  let Inst{20-16} = Rs32{4-0};
2927  bits <5> Rx32;
2928  let Inst{4-0} = Rx32{4-0};
2929}
2930class Enc_cda00a : OpcodeHexagon {
2931  bits <12> Ii;
2932  let Inst{19-16} = Ii{11-8};
2933  let Inst{12-5} = Ii{7-0};
2934  bits <2> Pu4;
2935  let Inst{22-21} = Pu4{1-0};
2936  bits <5> Rd32;
2937  let Inst{4-0} = Rd32{4-0};
2938}
2939class Enc_ce6828 : OpcodeHexagon {
2940  bits <14> Ii;
2941  let Inst{26-25} = Ii{13-12};
2942  let Inst{13-13} = Ii{11-11};
2943  let Inst{7-0} = Ii{10-3};
2944  bits <5> Rs32;
2945  let Inst{20-16} = Rs32{4-0};
2946  bits <5> Rtt32;
2947  let Inst{12-8} = Rtt32{4-0};
2948}
2949class Enc_cf1927 : OpcodeHexagon {
2950  bits <1> Mu2;
2951  let Inst{13-13} = Mu2{0-0};
2952  bits <3> Os8;
2953  let Inst{2-0} = Os8{2-0};
2954  bits <5> Rx32;
2955  let Inst{20-16} = Rx32{4-0};
2956}
2957class Enc_d15d19 : OpcodeHexagon {
2958  bits <1> Mu2;
2959  let Inst{13-13} = Mu2{0-0};
2960  bits <5> Vs32;
2961  let Inst{4-0} = Vs32{4-0};
2962  bits <5> Rx32;
2963  let Inst{20-16} = Rx32{4-0};
2964}
2965class Enc_d2216a : OpcodeHexagon {
2966  bits <5> Rss32;
2967  let Inst{20-16} = Rss32{4-0};
2968  bits <5> Rtt32;
2969  let Inst{12-8} = Rtt32{4-0};
2970  bits <5> Rd32;
2971  let Inst{4-0} = Rd32{4-0};
2972}
2973class Enc_d2c7f1 : OpcodeHexagon {
2974  bits <5> Rtt32;
2975  let Inst{12-8} = Rtt32{4-0};
2976  bits <5> Rss32;
2977  let Inst{20-16} = Rss32{4-0};
2978  bits <5> Rdd32;
2979  let Inst{4-0} = Rdd32{4-0};
2980  bits <2> Pe4;
2981  let Inst{6-5} = Pe4{1-0};
2982}
2983class Enc_d44e31 : OpcodeHexagon {
2984  bits <6> Ii;
2985  let Inst{12-7} = Ii{5-0};
2986  bits <5> Rs32;
2987  let Inst{20-16} = Rs32{4-0};
2988  bits <5> Rt32;
2989  let Inst{4-0} = Rt32{4-0};
2990}
2991class Enc_d483b9 : OpcodeHexagon {
2992  bits <1> Ii;
2993  let Inst{5-5} = Ii{0-0};
2994  bits <5> Vuu32;
2995  let Inst{12-8} = Vuu32{4-0};
2996  bits <5> Rt32;
2997  let Inst{20-16} = Rt32{4-0};
2998  bits <5> Vxx32;
2999  let Inst{4-0} = Vxx32{4-0};
3000}
3001class Enc_d50cd3 : OpcodeHexagon {
3002  bits <3> Ii;
3003  let Inst{7-5} = Ii{2-0};
3004  bits <5> Rss32;
3005  let Inst{20-16} = Rss32{4-0};
3006  bits <5> Rtt32;
3007  let Inst{12-8} = Rtt32{4-0};
3008  bits <5> Rdd32;
3009  let Inst{4-0} = Rdd32{4-0};
3010}
3011class Enc_d5c73f : OpcodeHexagon {
3012  bits <1> Mu2;
3013  let Inst{13-13} = Mu2{0-0};
3014  bits <5> Rt32;
3015  let Inst{12-8} = Rt32{4-0};
3016  bits <5> Rx32;
3017  let Inst{20-16} = Rx32{4-0};
3018}
3019class Enc_d6990d : OpcodeHexagon {
3020  bits <5> Vuu32;
3021  let Inst{12-8} = Vuu32{4-0};
3022  bits <5> Rt32;
3023  let Inst{20-16} = Rt32{4-0};
3024  bits <5> Vxx32;
3025  let Inst{4-0} = Vxx32{4-0};
3026}
3027class Enc_d7a65e : OpcodeHexagon {
3028  bits <6> Ii;
3029  let Inst{12-7} = Ii{5-0};
3030  bits <6> II;
3031  let Inst{13-13} = II{5-5};
3032  let Inst{4-0} = II{4-0};
3033  bits <2> Pv4;
3034  let Inst{6-5} = Pv4{1-0};
3035  bits <5> Rs32;
3036  let Inst{20-16} = Rs32{4-0};
3037}
3038class Enc_d7bc34 : OpcodeHexagon {
3039  bits <5> Vu32;
3040  let Inst{12-8} = Vu32{4-0};
3041  bits <3> Rt8;
3042  let Inst{18-16} = Rt8{2-0};
3043  bits <5> Vyyyy32;
3044  let Inst{4-0} = Vyyyy32{4-0};
3045}
3046class Enc_d7dc10 : OpcodeHexagon {
3047  bits <5> Rs32;
3048  let Inst{20-16} = Rs32{4-0};
3049  bits <5> Rtt32;
3050  let Inst{12-8} = Rtt32{4-0};
3051  bits <2> Pd4;
3052  let Inst{1-0} = Pd4{1-0};
3053}
3054class Enc_da664b : OpcodeHexagon {
3055  bits <2> Ii;
3056  let Inst{13-13} = Ii{1-1};
3057  let Inst{7-7} = Ii{0-0};
3058  bits <5> Rs32;
3059  let Inst{20-16} = Rs32{4-0};
3060  bits <5> Rt32;
3061  let Inst{12-8} = Rt32{4-0};
3062  bits <5> Rd32;
3063  let Inst{4-0} = Rd32{4-0};
3064}
3065class Enc_da8d43 : OpcodeHexagon {
3066  bits <6> Ii;
3067  let Inst{13-13} = Ii{5-5};
3068  let Inst{7-3} = Ii{4-0};
3069  bits <2> Pv4;
3070  let Inst{1-0} = Pv4{1-0};
3071  bits <5> Rs32;
3072  let Inst{20-16} = Rs32{4-0};
3073  bits <5> Rt32;
3074  let Inst{12-8} = Rt32{4-0};
3075}
3076class Enc_daea09 : OpcodeHexagon {
3077  bits <17> Ii;
3078  let Inst{23-22} = Ii{16-15};
3079  let Inst{20-16} = Ii{14-10};
3080  let Inst{13-13} = Ii{9-9};
3081  let Inst{7-1} = Ii{8-2};
3082  bits <2> Pu4;
3083  let Inst{9-8} = Pu4{1-0};
3084}
3085class Enc_db40cd : OpcodeHexagon {
3086  bits <6> Ii;
3087  let Inst{6-3} = Ii{5-2};
3088  bits <5> Rt32;
3089  let Inst{12-8} = Rt32{4-0};
3090  bits <5> Rx32;
3091  let Inst{20-16} = Rx32{4-0};
3092}
3093class Enc_dbd70c : OpcodeHexagon {
3094  bits <5> Rss32;
3095  let Inst{20-16} = Rss32{4-0};
3096  bits <5> Rtt32;
3097  let Inst{12-8} = Rtt32{4-0};
3098  bits <2> Pu4;
3099  let Inst{6-5} = Pu4{1-0};
3100  bits <5> Rdd32;
3101  let Inst{4-0} = Rdd32{4-0};
3102}
3103class Enc_dd766a : OpcodeHexagon {
3104  bits <5> Vu32;
3105  let Inst{12-8} = Vu32{4-0};
3106  bits <5> Vdd32;
3107  let Inst{4-0} = Vdd32{4-0};
3108}
3109class Enc_de0214 : OpcodeHexagon {
3110  bits <12> Ii;
3111  let Inst{26-25} = Ii{11-10};
3112  let Inst{13-5} = Ii{9-1};
3113  bits <5> Rs32;
3114  let Inst{20-16} = Rs32{4-0};
3115  bits <5> Rd32;
3116  let Inst{4-0} = Rd32{4-0};
3117}
3118class Enc_de5ea0 : OpcodeHexagon {
3119  bits <5> Vuu32;
3120  let Inst{12-8} = Vuu32{4-0};
3121  bits <5> Vv32;
3122  let Inst{20-16} = Vv32{4-0};
3123  bits <5> Vd32;
3124  let Inst{4-0} = Vd32{4-0};
3125}
3126class Enc_e07374 : OpcodeHexagon {
3127  bits <5> Rs32;
3128  let Inst{20-16} = Rs32{4-0};
3129  bits <5> Rtt32;
3130  let Inst{12-8} = Rtt32{4-0};
3131  bits <5> Rd32;
3132  let Inst{4-0} = Rd32{4-0};
3133}
3134class Enc_e0820b : OpcodeHexagon {
3135  bits <5> Vu32;
3136  let Inst{12-8} = Vu32{4-0};
3137  bits <5> Vv32;
3138  let Inst{20-16} = Vv32{4-0};
3139  bits <2> Qs4;
3140  let Inst{6-5} = Qs4{1-0};
3141  bits <5> Vd32;
3142  let Inst{4-0} = Vd32{4-0};
3143}
3144class Enc_e0a47a : OpcodeHexagon {
3145  bits <4> Ii;
3146  let Inst{8-5} = Ii{3-0};
3147  bits <1> Mu2;
3148  let Inst{13-13} = Mu2{0-0};
3149  bits <5> Rd32;
3150  let Inst{4-0} = Rd32{4-0};
3151  bits <5> Rx32;
3152  let Inst{20-16} = Rx32{4-0};
3153}
3154class Enc_e26546 : OpcodeHexagon {
3155  bits <5> Ii;
3156  let Inst{6-3} = Ii{4-1};
3157  bits <3> Nt8;
3158  let Inst{10-8} = Nt8{2-0};
3159  bits <5> Rx32;
3160  let Inst{20-16} = Rx32{4-0};
3161}
3162class Enc_e32517 : OpcodeHexagon {
3163  bits <7> Sss128;
3164  let Inst{22-16} = Sss128{6-0};
3165  bits <5> Rdd32;
3166  let Inst{4-0} = Rdd32{4-0};
3167}
3168class Enc_e38e1f : OpcodeHexagon {
3169  bits <8> Ii;
3170  let Inst{12-5} = Ii{7-0};
3171  bits <2> Pu4;
3172  let Inst{22-21} = Pu4{1-0};
3173  bits <5> Rs32;
3174  let Inst{20-16} = Rs32{4-0};
3175  bits <5> Rd32;
3176  let Inst{4-0} = Rd32{4-0};
3177}
3178class Enc_e39bb2 : OpcodeHexagon {
3179  bits <6> Ii;
3180  let Inst{9-4} = Ii{5-0};
3181  bits <4> Rd16;
3182  let Inst{3-0} = Rd16{3-0};
3183}
3184class Enc_e3b0c4 : OpcodeHexagon {
3185
3186}
3187class Enc_e66a97 : OpcodeHexagon {
3188  bits <7> Ii;
3189  let Inst{12-7} = Ii{6-1};
3190  bits <5> II;
3191  let Inst{4-0} = II{4-0};
3192  bits <5> Rs32;
3193  let Inst{20-16} = Rs32{4-0};
3194}
3195class Enc_e6abcf : OpcodeHexagon {
3196  bits <5> Rs32;
3197  let Inst{20-16} = Rs32{4-0};
3198  bits <5> Rtt32;
3199  let Inst{12-8} = Rtt32{4-0};
3200}
3201class Enc_e6c957 : OpcodeHexagon {
3202  bits <10> Ii;
3203  let Inst{21-21} = Ii{9-9};
3204  let Inst{13-5} = Ii{8-0};
3205  bits <5> Rdd32;
3206  let Inst{4-0} = Rdd32{4-0};
3207}
3208class Enc_e7581c : OpcodeHexagon {
3209  bits <5> Vu32;
3210  let Inst{12-8} = Vu32{4-0};
3211  bits <5> Vd32;
3212  let Inst{4-0} = Vd32{4-0};
3213}
3214class Enc_e83554 : OpcodeHexagon {
3215  bits <5> Ii;
3216  let Inst{8-5} = Ii{4-1};
3217  bits <1> Mu2;
3218  let Inst{13-13} = Mu2{0-0};
3219  bits <5> Rd32;
3220  let Inst{4-0} = Rd32{4-0};
3221  bits <5> Rx32;
3222  let Inst{20-16} = Rx32{4-0};
3223}
3224class Enc_e8c45e : OpcodeHexagon {
3225  bits <7> Ii;
3226  let Inst{13-13} = Ii{6-6};
3227  let Inst{7-3} = Ii{5-1};
3228  bits <2> Pv4;
3229  let Inst{1-0} = Pv4{1-0};
3230  bits <5> Rs32;
3231  let Inst{20-16} = Rs32{4-0};
3232  bits <5> Rt32;
3233  let Inst{12-8} = Rt32{4-0};
3234}
3235class Enc_e90a15 : OpcodeHexagon {
3236  bits <11> Ii;
3237  let Inst{21-20} = Ii{10-9};
3238  let Inst{7-1} = Ii{8-2};
3239  bits <3> Ns8;
3240  let Inst{18-16} = Ns8{2-0};
3241  bits <4> n1;
3242  let Inst{29-29} = n1{3-3};
3243  let Inst{26-25} = n1{2-1};
3244  let Inst{22-22} = n1{0-0};
3245}
3246class Enc_e957fb : OpcodeHexagon {
3247  bits <12> Ii;
3248  let Inst{26-25} = Ii{11-10};
3249  let Inst{13-13} = Ii{9-9};
3250  let Inst{7-0} = Ii{8-1};
3251  bits <5> Rs32;
3252  let Inst{20-16} = Rs32{4-0};
3253  bits <5> Rt32;
3254  let Inst{12-8} = Rt32{4-0};
3255}
3256class Enc_ea23e4 : OpcodeHexagon {
3257  bits <5> Rtt32;
3258  let Inst{12-8} = Rtt32{4-0};
3259  bits <5> Rss32;
3260  let Inst{20-16} = Rss32{4-0};
3261  bits <5> Rdd32;
3262  let Inst{4-0} = Rdd32{4-0};
3263}
3264class Enc_ea4c54 : OpcodeHexagon {
3265  bits <2> Pu4;
3266  let Inst{6-5} = Pu4{1-0};
3267  bits <5> Rs32;
3268  let Inst{20-16} = Rs32{4-0};
3269  bits <5> Rt32;
3270  let Inst{12-8} = Rt32{4-0};
3271  bits <5> Rd32;
3272  let Inst{4-0} = Rd32{4-0};
3273}
3274class Enc_eaa9f8 : OpcodeHexagon {
3275  bits <5> Vu32;
3276  let Inst{12-8} = Vu32{4-0};
3277  bits <5> Vv32;
3278  let Inst{20-16} = Vv32{4-0};
3279  bits <2> Qx4;
3280  let Inst{1-0} = Qx4{1-0};
3281}
3282class Enc_eafd18 : OpcodeHexagon {
3283  bits <5> II;
3284  let Inst{12-8} = II{4-0};
3285  bits <11> Ii;
3286  let Inst{21-20} = Ii{10-9};
3287  let Inst{7-1} = Ii{8-2};
3288  bits <3> Ns8;
3289  let Inst{18-16} = Ns8{2-0};
3290}
3291class Enc_eca7c8 : OpcodeHexagon {
3292  bits <2> Ii;
3293  let Inst{13-13} = Ii{1-1};
3294  let Inst{7-7} = Ii{0-0};
3295  bits <5> Rs32;
3296  let Inst{20-16} = Rs32{4-0};
3297  bits <5> Ru32;
3298  let Inst{12-8} = Ru32{4-0};
3299  bits <5> Rt32;
3300  let Inst{4-0} = Rt32{4-0};
3301}
3302class Enc_ecbcc8 : OpcodeHexagon {
3303  bits <5> Rs32;
3304  let Inst{20-16} = Rs32{4-0};
3305}
3306class Enc_ed48be : OpcodeHexagon {
3307  bits <2> Ii;
3308  let Inst{6-5} = Ii{1-0};
3309  bits <3> Rdd8;
3310  let Inst{2-0} = Rdd8{2-0};
3311}
3312class Enc_ed5027 : OpcodeHexagon {
3313  bits <5> Rss32;
3314  let Inst{20-16} = Rss32{4-0};
3315  bits <5> Gdd32;
3316  let Inst{4-0} = Gdd32{4-0};
3317}
3318class Enc_ee5ed0 : OpcodeHexagon {
3319  bits <4> Rs16;
3320  let Inst{7-4} = Rs16{3-0};
3321  bits <4> Rd16;
3322  let Inst{3-0} = Rd16{3-0};
3323  bits <2> n1;
3324  let Inst{9-8} = n1{1-0};
3325}
3326class Enc_ef601b : OpcodeHexagon {
3327  bits <4> Ii;
3328  let Inst{13-13} = Ii{3-3};
3329  let Inst{10-8} = Ii{2-0};
3330  bits <2> Pv4;
3331  let Inst{12-11} = Pv4{1-0};
3332  bits <5> Rt32;
3333  let Inst{20-16} = Rt32{4-0};
3334}
3335class Enc_efaed8 : OpcodeHexagon {
3336  bits <1> Ii;
3337  let Inst{8-8} = Ii{0-0};
3338}
3339class Enc_f0cca7 : OpcodeHexagon {
3340  bits <8> Ii;
3341  let Inst{12-5} = Ii{7-0};
3342  bits <6> II;
3343  let Inst{20-16} = II{5-1};
3344  let Inst{13-13} = II{0-0};
3345  bits <5> Rdd32;
3346  let Inst{4-0} = Rdd32{4-0};
3347}
3348class Enc_f20719 : OpcodeHexagon {
3349  bits <7> Ii;
3350  let Inst{12-7} = Ii{6-1};
3351  bits <6> II;
3352  let Inst{13-13} = II{5-5};
3353  let Inst{4-0} = II{4-0};
3354  bits <2> Pv4;
3355  let Inst{6-5} = Pv4{1-0};
3356  bits <5> Rs32;
3357  let Inst{20-16} = Rs32{4-0};
3358}
3359class Enc_f37377 : OpcodeHexagon {
3360  bits <8> Ii;
3361  let Inst{12-7} = Ii{7-2};
3362  bits <8> II;
3363  let Inst{13-13} = II{7-7};
3364  let Inst{6-0} = II{6-0};
3365  bits <5> Rs32;
3366  let Inst{20-16} = Rs32{4-0};
3367}
3368class Enc_f394d3 : OpcodeHexagon {
3369  bits <6> II;
3370  let Inst{11-8} = II{5-2};
3371  let Inst{6-5} = II{1-0};
3372  bits <5> Ryy32;
3373  let Inst{4-0} = Ryy32{4-0};
3374  bits <5> Re32;
3375  let Inst{20-16} = Re32{4-0};
3376}
3377class Enc_f3f408 : OpcodeHexagon {
3378  bits <4> Ii;
3379  let Inst{13-13} = Ii{3-3};
3380  let Inst{10-8} = Ii{2-0};
3381  bits <5> Rt32;
3382  let Inst{20-16} = Rt32{4-0};
3383  bits <5> Vd32;
3384  let Inst{4-0} = Vd32{4-0};
3385}
3386class Enc_f4413a : OpcodeHexagon {
3387  bits <4> Ii;
3388  let Inst{8-5} = Ii{3-0};
3389  bits <2> Pt4;
3390  let Inst{10-9} = Pt4{1-0};
3391  bits <5> Rd32;
3392  let Inst{4-0} = Rd32{4-0};
3393  bits <5> Rx32;
3394  let Inst{20-16} = Rx32{4-0};
3395}
3396class Enc_f44229 : OpcodeHexagon {
3397  bits <7> Ii;
3398  let Inst{13-13} = Ii{6-6};
3399  let Inst{7-3} = Ii{5-1};
3400  bits <2> Pv4;
3401  let Inst{1-0} = Pv4{1-0};
3402  bits <5> Rs32;
3403  let Inst{20-16} = Rs32{4-0};
3404  bits <3> Nt8;
3405  let Inst{10-8} = Nt8{2-0};
3406}
3407class Enc_f4f57b : OpcodeHexagon {
3408  bits <2> Ii;
3409  let Inst{6-5} = Ii{1-0};
3410  bits <5> Vuu32;
3411  let Inst{12-8} = Vuu32{4-0};
3412  bits <5> Vvv32;
3413  let Inst{20-16} = Vvv32{4-0};
3414  bits <5> Vxx32;
3415  let Inst{4-0} = Vxx32{4-0};
3416}
3417class Enc_f55a0c : OpcodeHexagon {
3418  bits <6> Ii;
3419  let Inst{11-8} = Ii{5-2};
3420  bits <4> Rs16;
3421  let Inst{7-4} = Rs16{3-0};
3422  bits <4> Rt16;
3423  let Inst{3-0} = Rt16{3-0};
3424}
3425class Enc_f5e933 : OpcodeHexagon {
3426  bits <2> Ps4;
3427  let Inst{17-16} = Ps4{1-0};
3428  bits <5> Rd32;
3429  let Inst{4-0} = Rd32{4-0};
3430}
3431class Enc_f6fe0b : OpcodeHexagon {
3432  bits <11> Ii;
3433  let Inst{21-20} = Ii{10-9};
3434  let Inst{7-1} = Ii{8-2};
3435  bits <4> Rs16;
3436  let Inst{19-16} = Rs16{3-0};
3437  bits <6> n1;
3438  let Inst{28-28} = n1{5-5};
3439  let Inst{24-22} = n1{4-2};
3440  let Inst{13-13} = n1{1-1};
3441  let Inst{8-8} = n1{0-0};
3442}
3443class Enc_f7430e : OpcodeHexagon {
3444  bits <4> Ii;
3445  let Inst{13-13} = Ii{3-3};
3446  let Inst{10-8} = Ii{2-0};
3447  bits <2> Pv4;
3448  let Inst{12-11} = Pv4{1-0};
3449  bits <5> Rt32;
3450  let Inst{20-16} = Rt32{4-0};
3451  bits <3> Os8;
3452  let Inst{2-0} = Os8{2-0};
3453}
3454class Enc_f77fbc : OpcodeHexagon {
3455  bits <4> Ii;
3456  let Inst{13-13} = Ii{3-3};
3457  let Inst{10-8} = Ii{2-0};
3458  bits <5> Rt32;
3459  let Inst{20-16} = Rt32{4-0};
3460  bits <3> Os8;
3461  let Inst{2-0} = Os8{2-0};
3462}
3463class Enc_f79415 : OpcodeHexagon {
3464  bits <2> Ii;
3465  let Inst{13-13} = Ii{1-1};
3466  let Inst{6-6} = Ii{0-0};
3467  bits <6> II;
3468  let Inst{5-0} = II{5-0};
3469  bits <5> Ru32;
3470  let Inst{20-16} = Ru32{4-0};
3471  bits <5> Rtt32;
3472  let Inst{12-8} = Rtt32{4-0};
3473}
3474class Enc_f7ea77 : OpcodeHexagon {
3475  bits <11> Ii;
3476  let Inst{21-20} = Ii{10-9};
3477  let Inst{7-1} = Ii{8-2};
3478  bits <3> Ns8;
3479  let Inst{18-16} = Ns8{2-0};
3480  bits <4> n1;
3481  let Inst{29-29} = n1{3-3};
3482  let Inst{26-25} = n1{2-1};
3483  let Inst{13-13} = n1{0-0};
3484}
3485class Enc_f82302 : OpcodeHexagon {
3486  bits <11> Ii;
3487  let Inst{21-20} = Ii{10-9};
3488  let Inst{7-1} = Ii{8-2};
3489  bits <3> Ns8;
3490  let Inst{18-16} = Ns8{2-0};
3491  bits <4> n1;
3492  let Inst{29-29} = n1{3-3};
3493  let Inst{26-25} = n1{2-1};
3494  let Inst{23-23} = n1{0-0};
3495}
3496class Enc_f82eaf : OpcodeHexagon {
3497  bits <8> Ii;
3498  let Inst{10-5} = Ii{7-2};
3499  bits <2> Pt4;
3500  let Inst{12-11} = Pt4{1-0};
3501  bits <5> Rs32;
3502  let Inst{20-16} = Rs32{4-0};
3503  bits <5> Rd32;
3504  let Inst{4-0} = Rd32{4-0};
3505}
3506class Enc_f8c1c4 : OpcodeHexagon {
3507  bits <2> Pv4;
3508  let Inst{12-11} = Pv4{1-0};
3509  bits <1> Mu2;
3510  let Inst{13-13} = Mu2{0-0};
3511  bits <5> Vd32;
3512  let Inst{4-0} = Vd32{4-0};
3513  bits <5> Rx32;
3514  let Inst{20-16} = Rx32{4-0};
3515}
3516class Enc_f8ecf9 : OpcodeHexagon {
3517  bits <5> Vuu32;
3518  let Inst{12-8} = Vuu32{4-0};
3519  bits <5> Vvv32;
3520  let Inst{20-16} = Vvv32{4-0};
3521  bits <5> Vdd32;
3522  let Inst{4-0} = Vdd32{4-0};
3523}
3524class Enc_fa3ba4 : OpcodeHexagon {
3525  bits <14> Ii;
3526  let Inst{26-25} = Ii{13-12};
3527  let Inst{13-5} = Ii{11-3};
3528  bits <5> Rs32;
3529  let Inst{20-16} = Rs32{4-0};
3530  bits <5> Rdd32;
3531  let Inst{4-0} = Rdd32{4-0};
3532}
3533class Enc_fb6577 : OpcodeHexagon {
3534  bits <2> Pu4;
3535  let Inst{9-8} = Pu4{1-0};
3536  bits <5> Rs32;
3537  let Inst{20-16} = Rs32{4-0};
3538  bits <5> Rd32;
3539  let Inst{4-0} = Rd32{4-0};
3540}
3541class Enc_fcf7a7 : OpcodeHexagon {
3542  bits <5> Rss32;
3543  let Inst{20-16} = Rss32{4-0};
3544  bits <5> Rtt32;
3545  let Inst{12-8} = Rtt32{4-0};
3546  bits <2> Pd4;
3547  let Inst{1-0} = Pd4{1-0};
3548}
3549class Enc_fda92c : OpcodeHexagon {
3550  bits <17> Ii;
3551  let Inst{26-25} = Ii{16-15};
3552  let Inst{20-16} = Ii{14-10};
3553  let Inst{13-13} = Ii{9-9};
3554  let Inst{7-0} = Ii{8-1};
3555  bits <5> Rt32;
3556  let Inst{12-8} = Rt32{4-0};
3557}
3558class Enc_fef969 : OpcodeHexagon {
3559  bits <6> Ii;
3560  let Inst{20-16} = Ii{5-1};
3561  let Inst{5-5} = Ii{0-0};
3562  bits <5> Rt32;
3563  let Inst{12-8} = Rt32{4-0};
3564  bits <5> Rd32;
3565  let Inst{4-0} = Rd32{4-0};
3566}
3567class Enc_ff3442 : OpcodeHexagon {
3568  bits <4> Ii;
3569  let Inst{13-13} = Ii{3-3};
3570  let Inst{10-8} = Ii{2-0};
3571  bits <5> Rt32;
3572  let Inst{20-16} = Rt32{4-0};
3573}
3574