xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11class Enc_01d3d0 : OpcodeHexagon {
12  bits <5> Vu32;
13  let Inst{12-8} = Vu32{4-0};
14  bits <5> Rt32;
15  let Inst{20-16} = Rt32{4-0};
16  bits <5> Vdd32;
17  let Inst{4-0} = Vdd32{4-0};
18}
19class Enc_02553a : OpcodeHexagon {
20  bits <7> Ii;
21  let Inst{11-5} = Ii{6-0};
22  bits <5> Rs32;
23  let Inst{20-16} = Rs32{4-0};
24  bits <2> Pd4;
25  let Inst{1-0} = Pd4{1-0};
26}
27class Enc_03833b : OpcodeHexagon {
28  bits <5> Rss32;
29  let Inst{20-16} = Rss32{4-0};
30  bits <5> Rt32;
31  let Inst{12-8} = Rt32{4-0};
32  bits <2> Pd4;
33  let Inst{1-0} = Pd4{1-0};
34}
35class Enc_041d7b : OpcodeHexagon {
36  bits <11> Ii;
37  let Inst{21-20} = Ii{10-9};
38  let Inst{7-1} = Ii{8-2};
39  bits <4> Rs16;
40  let Inst{19-16} = Rs16{3-0};
41  bits <5> n1;
42  let Inst{28-28} = n1{4-4};
43  let Inst{24-23} = n1{3-2};
44  let Inst{13-13} = n1{1-1};
45  let Inst{8-8} = n1{0-0};
46}
47class Enc_046afa : OpcodeHexagon {
48  bits <1> Mu2;
49  let Inst{13-13} = Mu2{0-0};
50  bits <5> Vss32;
51  let Inst{4-0} = Vss32{4-0};
52  bits <5> Rx32;
53  let Inst{20-16} = Rx32{4-0};
54}
55class Enc_04c959 : OpcodeHexagon {
56  bits <2> Ii;
57  let Inst{13-13} = Ii{1-1};
58  let Inst{7-7} = Ii{0-0};
59  bits <6> II;
60  let Inst{11-8} = II{5-2};
61  let Inst{6-5} = II{1-0};
62  bits <5> Rt32;
63  let Inst{20-16} = Rt32{4-0};
64  bits <5> Ryy32;
65  let Inst{4-0} = Ryy32{4-0};
66}
67class Enc_0527db : OpcodeHexagon {
68  bits <4> Rs16;
69  let Inst{7-4} = Rs16{3-0};
70  bits <4> Rx16;
71  let Inst{3-0} = Rx16{3-0};
72}
73class Enc_052c7d : OpcodeHexagon {
74  bits <5> Ii;
75  let Inst{6-3} = Ii{4-1};
76  bits <5> Rt32;
77  let Inst{12-8} = Rt32{4-0};
78  bits <5> Rx32;
79  let Inst{20-16} = Rx32{4-0};
80}
81class Enc_08d755 : OpcodeHexagon {
82  bits <8> Ii;
83  let Inst{12-5} = Ii{7-0};
84  bits <5> Rs32;
85  let Inst{20-16} = Rs32{4-0};
86  bits <2> Pd4;
87  let Inst{1-0} = Pd4{1-0};
88}
89class Enc_0aa344 : OpcodeHexagon {
90  bits <5> Gss32;
91  let Inst{20-16} = Gss32{4-0};
92  bits <5> Rdd32;
93  let Inst{4-0} = Rdd32{4-0};
94}
95class Enc_0b2e5b : OpcodeHexagon {
96  bits <3> Ii;
97  let Inst{7-5} = Ii{2-0};
98  bits <5> Vu32;
99  let Inst{12-8} = Vu32{4-0};
100  bits <5> Vv32;
101  let Inst{20-16} = Vv32{4-0};
102  bits <5> Vd32;
103  let Inst{4-0} = Vd32{4-0};
104}
105class Enc_0b51ce : OpcodeHexagon {
106  bits <3> Ii;
107  let Inst{10-8} = Ii{2-0};
108  bits <2> Qv4;
109  let Inst{12-11} = Qv4{1-0};
110  bits <5> Vs32;
111  let Inst{4-0} = Vs32{4-0};
112  bits <5> Rx32;
113  let Inst{20-16} = Rx32{4-0};
114}
115class Enc_0cb018 : OpcodeHexagon {
116  bits <5> Cs32;
117  let Inst{20-16} = Cs32{4-0};
118  bits <5> Rd32;
119  let Inst{4-0} = Rd32{4-0};
120}
121class Enc_0d8870 : OpcodeHexagon {
122  bits <12> Ii;
123  let Inst{26-25} = Ii{11-10};
124  let Inst{13-13} = Ii{9-9};
125  let Inst{7-0} = Ii{8-1};
126  bits <5> Rs32;
127  let Inst{20-16} = Rs32{4-0};
128  bits <3> Nt8;
129  let Inst{10-8} = Nt8{2-0};
130}
131class Enc_0d8adb : OpcodeHexagon {
132  bits <8> Ii;
133  let Inst{12-5} = Ii{7-0};
134  bits <5> Rss32;
135  let Inst{20-16} = Rss32{4-0};
136  bits <2> Pd4;
137  let Inst{1-0} = Pd4{1-0};
138}
139class Enc_0e41fa : OpcodeHexagon {
140  bits <5> Vuu32;
141  let Inst{12-8} = Vuu32{4-0};
142  bits <5> Rt32;
143  let Inst{20-16} = Rt32{4-0};
144  bits <5> Vd32;
145  let Inst{4-0} = Vd32{4-0};
146}
147class Enc_0ed752 : OpcodeHexagon {
148  bits <5> Rss32;
149  let Inst{20-16} = Rss32{4-0};
150  bits <5> Cdd32;
151  let Inst{4-0} = Cdd32{4-0};
152}
153class Enc_0f8bab : OpcodeHexagon {
154  bits <5> Vu32;
155  let Inst{12-8} = Vu32{4-0};
156  bits <5> Rt32;
157  let Inst{20-16} = Rt32{4-0};
158  bits <2> Qd4;
159  let Inst{1-0} = Qd4{1-0};
160}
161class Enc_0fa531 : OpcodeHexagon {
162  bits <15> Ii;
163  let Inst{21-21} = Ii{14-14};
164  let Inst{13-13} = Ii{13-13};
165  let Inst{11-1} = Ii{12-2};
166  bits <5> Rs32;
167  let Inst{20-16} = Rs32{4-0};
168}
169class Enc_10bc21 : OpcodeHexagon {
170  bits <4> Ii;
171  let Inst{6-3} = Ii{3-0};
172  bits <5> Rt32;
173  let Inst{12-8} = Rt32{4-0};
174  bits <5> Rx32;
175  let Inst{20-16} = Rx32{4-0};
176}
177class Enc_1178da : OpcodeHexagon {
178  bits <3> Ii;
179  let Inst{7-5} = Ii{2-0};
180  bits <5> Vu32;
181  let Inst{12-8} = Vu32{4-0};
182  bits <5> Vv32;
183  let Inst{20-16} = Vv32{4-0};
184  bits <5> Vxx32;
185  let Inst{4-0} = Vxx32{4-0};
186}
187class Enc_11a146 : OpcodeHexagon {
188  bits <4> Ii;
189  let Inst{11-8} = Ii{3-0};
190  bits <5> Rss32;
191  let Inst{20-16} = Rss32{4-0};
192  bits <5> Rd32;
193  let Inst{4-0} = Rd32{4-0};
194}
195class Enc_12b6e9 : OpcodeHexagon {
196  bits <4> Ii;
197  let Inst{11-8} = Ii{3-0};
198  bits <5> Rss32;
199  let Inst{20-16} = Rss32{4-0};
200  bits <5> Rdd32;
201  let Inst{4-0} = Rdd32{4-0};
202}
203class Enc_134437 : OpcodeHexagon {
204  bits <2> Qs4;
205  let Inst{9-8} = Qs4{1-0};
206  bits <2> Qt4;
207  let Inst{23-22} = Qt4{1-0};
208  bits <2> Qd4;
209  let Inst{1-0} = Qd4{1-0};
210}
211class Enc_140c83 : OpcodeHexagon {
212  bits <10> Ii;
213  let Inst{21-21} = Ii{9-9};
214  let Inst{13-5} = Ii{8-0};
215  bits <5> Rs32;
216  let Inst{20-16} = Rs32{4-0};
217  bits <5> Rd32;
218  let Inst{4-0} = Rd32{4-0};
219}
220class Enc_143445 : OpcodeHexagon {
221  bits <13> Ii;
222  let Inst{26-25} = Ii{12-11};
223  let Inst{13-13} = Ii{10-10};
224  let Inst{7-0} = Ii{9-2};
225  bits <5> Rs32;
226  let Inst{20-16} = Rs32{4-0};
227  bits <5> Rt32;
228  let Inst{12-8} = Rt32{4-0};
229}
230class Enc_143a3c : OpcodeHexagon {
231  bits <6> Ii;
232  let Inst{13-8} = Ii{5-0};
233  bits <6> II;
234  let Inst{23-21} = II{5-3};
235  let Inst{7-5} = II{2-0};
236  bits <5> Rss32;
237  let Inst{20-16} = Rss32{4-0};
238  bits <5> Rxx32;
239  let Inst{4-0} = Rxx32{4-0};
240}
241class Enc_14640c : OpcodeHexagon {
242  bits <11> Ii;
243  let Inst{21-20} = Ii{10-9};
244  let Inst{7-1} = Ii{8-2};
245  bits <4> Rs16;
246  let Inst{19-16} = Rs16{3-0};
247  bits <5> n1;
248  let Inst{28-28} = n1{4-4};
249  let Inst{24-22} = n1{3-1};
250  let Inst{13-13} = n1{0-0};
251}
252class Enc_14d27a : OpcodeHexagon {
253  bits <5> II;
254  let Inst{12-8} = II{4-0};
255  bits <11> Ii;
256  let Inst{21-20} = Ii{10-9};
257  let Inst{7-1} = Ii{8-2};
258  bits <4> Rs16;
259  let Inst{19-16} = Rs16{3-0};
260}
261class Enc_152467 : OpcodeHexagon {
262  bits <5> Ii;
263  let Inst{8-5} = Ii{4-1};
264  bits <5> Rd32;
265  let Inst{4-0} = Rd32{4-0};
266  bits <5> Rx32;
267  let Inst{20-16} = Rx32{4-0};
268}
269class Enc_158beb : OpcodeHexagon {
270  bits <2> Qs4;
271  let Inst{6-5} = Qs4{1-0};
272  bits <5> Rt32;
273  let Inst{20-16} = Rt32{4-0};
274  bits <1> Mu2;
275  let Inst{13-13} = Mu2{0-0};
276  bits <5> Vv32;
277  let Inst{4-0} = Vv32{4-0};
278}
279class Enc_163a3c : OpcodeHexagon {
280  bits <7> Ii;
281  let Inst{12-7} = Ii{6-1};
282  bits <5> Rs32;
283  let Inst{20-16} = Rs32{4-0};
284  bits <5> Rt32;
285  let Inst{4-0} = Rt32{4-0};
286}
287class Enc_16c48b : OpcodeHexagon {
288  bits <5> Rt32;
289  let Inst{20-16} = Rt32{4-0};
290  bits <1> Mu2;
291  let Inst{13-13} = Mu2{0-0};
292  bits <5> Vv32;
293  let Inst{12-8} = Vv32{4-0};
294  bits <5> Vw32;
295  let Inst{4-0} = Vw32{4-0};
296}
297class Enc_178717 : OpcodeHexagon {
298  bits <11> Ii;
299  let Inst{21-20} = Ii{10-9};
300  let Inst{7-1} = Ii{8-2};
301  bits <4> Rs16;
302  let Inst{19-16} = Rs16{3-0};
303  bits <6> n1;
304  let Inst{28-28} = n1{5-5};
305  let Inst{25-23} = n1{4-2};
306  let Inst{13-13} = n1{1-1};
307  let Inst{8-8} = n1{0-0};
308}
309class Enc_179b35 : OpcodeHexagon {
310  bits <5> Rs32;
311  let Inst{20-16} = Rs32{4-0};
312  bits <5> Rtt32;
313  let Inst{12-8} = Rtt32{4-0};
314  bits <5> Rx32;
315  let Inst{4-0} = Rx32{4-0};
316}
317class Enc_18c338 : OpcodeHexagon {
318  bits <8> Ii;
319  let Inst{12-5} = Ii{7-0};
320  bits <8> II;
321  let Inst{22-16} = II{7-1};
322  let Inst{13-13} = II{0-0};
323  bits <5> Rdd32;
324  let Inst{4-0} = Rdd32{4-0};
325}
326class Enc_1a9974 : OpcodeHexagon {
327  bits <2> Ii;
328  let Inst{13-13} = Ii{1-1};
329  let Inst{7-7} = Ii{0-0};
330  bits <2> Pv4;
331  let Inst{6-5} = Pv4{1-0};
332  bits <5> Rs32;
333  let Inst{20-16} = Rs32{4-0};
334  bits <5> Ru32;
335  let Inst{12-8} = Ru32{4-0};
336  bits <5> Rtt32;
337  let Inst{4-0} = Rtt32{4-0};
338}
339class Enc_1aa186 : OpcodeHexagon {
340  bits <5> Rss32;
341  let Inst{20-16} = Rss32{4-0};
342  bits <5> Rt32;
343  let Inst{12-8} = Rt32{4-0};
344  bits <5> Rxx32;
345  let Inst{4-0} = Rxx32{4-0};
346}
347class Enc_1aaec1 : OpcodeHexagon {
348  bits <3> Ii;
349  let Inst{10-8} = Ii{2-0};
350  bits <3> Os8;
351  let Inst{2-0} = Os8{2-0};
352  bits <5> Rx32;
353  let Inst{20-16} = Rx32{4-0};
354}
355class Enc_1b64fb : OpcodeHexagon {
356  bits <16> Ii;
357  let Inst{26-25} = Ii{15-14};
358  let Inst{20-16} = Ii{13-9};
359  let Inst{13-13} = Ii{8-8};
360  let Inst{7-0} = Ii{7-0};
361  bits <5> Rt32;
362  let Inst{12-8} = Rt32{4-0};
363}
364class Enc_1bd127 : OpcodeHexagon {
365  bits <5> Vu32;
366  let Inst{12-8} = Vu32{4-0};
367  bits <3> Rt8;
368  let Inst{18-16} = Rt8{2-0};
369  bits <5> Vdddd32;
370  let Inst{4-0} = Vdddd32{4-0};
371}
372class Enc_1cf4ca : OpcodeHexagon {
373  bits <6> Ii;
374  let Inst{17-16} = Ii{5-4};
375  let Inst{6-3} = Ii{3-0};
376  bits <2> Pv4;
377  let Inst{1-0} = Pv4{1-0};
378  bits <5> Rt32;
379  let Inst{12-8} = Rt32{4-0};
380}
381class Enc_1de724 : OpcodeHexagon {
382  bits <11> Ii;
383  let Inst{21-20} = Ii{10-9};
384  let Inst{7-1} = Ii{8-2};
385  bits <4> Rs16;
386  let Inst{19-16} = Rs16{3-0};
387  bits <4> n1;
388  let Inst{28-28} = n1{3-3};
389  let Inst{24-22} = n1{2-0};
390}
391class Enc_1ef990 : OpcodeHexagon {
392  bits <2> Pv4;
393  let Inst{12-11} = Pv4{1-0};
394  bits <1> Mu2;
395  let Inst{13-13} = Mu2{0-0};
396  bits <5> Vs32;
397  let Inst{4-0} = Vs32{4-0};
398  bits <5> Rx32;
399  let Inst{20-16} = Rx32{4-0};
400}
401class Enc_1f19b5 : OpcodeHexagon {
402  bits <5> Ii;
403  let Inst{9-5} = Ii{4-0};
404  bits <5> Rss32;
405  let Inst{20-16} = Rss32{4-0};
406  bits <2> Pd4;
407  let Inst{1-0} = Pd4{1-0};
408}
409class Enc_1f5ba6 : OpcodeHexagon {
410  bits <4> Rd16;
411  let Inst{3-0} = Rd16{3-0};
412}
413class Enc_1f5d8f : OpcodeHexagon {
414  bits <1> Mu2;
415  let Inst{13-13} = Mu2{0-0};
416  bits <5> Ryy32;
417  let Inst{4-0} = Ryy32{4-0};
418  bits <5> Rx32;
419  let Inst{20-16} = Rx32{4-0};
420}
421class Enc_211aaa : OpcodeHexagon {
422  bits <11> Ii;
423  let Inst{26-25} = Ii{10-9};
424  let Inst{13-5} = Ii{8-0};
425  bits <5> Rs32;
426  let Inst{20-16} = Rs32{4-0};
427  bits <5> Rd32;
428  let Inst{4-0} = Rd32{4-0};
429}
430class Enc_217147 : OpcodeHexagon {
431  bits <2> Qv4;
432  let Inst{23-22} = Qv4{1-0};
433}
434class Enc_222336 : OpcodeHexagon {
435  bits <4> Ii;
436  let Inst{8-5} = Ii{3-0};
437  bits <5> Rd32;
438  let Inst{4-0} = Rd32{4-0};
439  bits <5> Rx32;
440  let Inst{20-16} = Rx32{4-0};
441}
442class Enc_223005 : OpcodeHexagon {
443  bits <6> Ii;
444  let Inst{6-3} = Ii{5-2};
445  bits <3> Nt8;
446  let Inst{10-8} = Nt8{2-0};
447  bits <5> Rx32;
448  let Inst{20-16} = Rx32{4-0};
449}
450class Enc_226535 : OpcodeHexagon {
451  bits <8> Ii;
452  let Inst{12-7} = Ii{7-2};
453  bits <5> Rs32;
454  let Inst{20-16} = Rs32{4-0};
455  bits <5> Rt32;
456  let Inst{4-0} = Rt32{4-0};
457}
458class Enc_22c845 : OpcodeHexagon {
459  bits <14> Ii;
460  let Inst{10-0} = Ii{13-3};
461  bits <5> Rx32;
462  let Inst{20-16} = Rx32{4-0};
463}
464class Enc_2301d6 : OpcodeHexagon {
465  bits <6> Ii;
466  let Inst{20-16} = Ii{5-1};
467  let Inst{8-8} = Ii{0-0};
468  bits <2> Pt4;
469  let Inst{10-9} = Pt4{1-0};
470  bits <5> Rd32;
471  let Inst{4-0} = Rd32{4-0};
472}
473class Enc_245865 : OpcodeHexagon {
474  bits <5> Vu32;
475  let Inst{12-8} = Vu32{4-0};
476  bits <5> Vv32;
477  let Inst{23-19} = Vv32{4-0};
478  bits <3> Rt8;
479  let Inst{18-16} = Rt8{2-0};
480  bits <5> Vx32;
481  let Inst{4-0} = Vx32{4-0};
482}
483class Enc_24a7dc : OpcodeHexagon {
484  bits <5> Vu32;
485  let Inst{12-8} = Vu32{4-0};
486  bits <5> Vv32;
487  let Inst{23-19} = Vv32{4-0};
488  bits <3> Rt8;
489  let Inst{18-16} = Rt8{2-0};
490  bits <5> Vdd32;
491  let Inst{4-0} = Vdd32{4-0};
492}
493class Enc_25bef0 : OpcodeHexagon {
494  bits <16> Ii;
495  let Inst{26-25} = Ii{15-14};
496  let Inst{20-16} = Ii{13-9};
497  let Inst{13-5} = Ii{8-0};
498  bits <5> Rd32;
499  let Inst{4-0} = Rd32{4-0};
500}
501class Enc_263841 : OpcodeHexagon {
502  bits <5> Vu32;
503  let Inst{12-8} = Vu32{4-0};
504  bits <5> Rtt32;
505  let Inst{20-16} = Rtt32{4-0};
506  bits <5> Vd32;
507  let Inst{4-0} = Vd32{4-0};
508}
509class Enc_277737 : OpcodeHexagon {
510  bits <8> Ii;
511  let Inst{22-21} = Ii{7-6};
512  let Inst{13-13} = Ii{5-5};
513  let Inst{7-5} = Ii{4-2};
514  bits <5> Ru32;
515  let Inst{4-0} = Ru32{4-0};
516  bits <5> Rs32;
517  let Inst{20-16} = Rs32{4-0};
518  bits <5> Rd32;
519  let Inst{12-8} = Rd32{4-0};
520}
521class Enc_27b757 : OpcodeHexagon {
522  bits <4> Ii;
523  let Inst{13-13} = Ii{3-3};
524  let Inst{10-8} = Ii{2-0};
525  bits <2> Pv4;
526  let Inst{12-11} = Pv4{1-0};
527  bits <5> Rt32;
528  let Inst{20-16} = Rt32{4-0};
529  bits <5> Vs32;
530  let Inst{4-0} = Vs32{4-0};
531}
532class Enc_27fd0e : OpcodeHexagon {
533  bits <6> Ii;
534  let Inst{8-5} = Ii{5-2};
535  bits <1> Mu2;
536  let Inst{13-13} = Mu2{0-0};
537  bits <5> Rd32;
538  let Inst{4-0} = Rd32{4-0};
539  bits <5> Rx32;
540  let Inst{20-16} = Rx32{4-0};
541}
542class Enc_284ebb : OpcodeHexagon {
543  bits <2> Ps4;
544  let Inst{17-16} = Ps4{1-0};
545  bits <2> Pt4;
546  let Inst{9-8} = Pt4{1-0};
547  bits <2> Pd4;
548  let Inst{1-0} = Pd4{1-0};
549}
550class Enc_28a2dc : OpcodeHexagon {
551  bits <5> Ii;
552  let Inst{12-8} = Ii{4-0};
553  bits <5> Rs32;
554  let Inst{20-16} = Rs32{4-0};
555  bits <5> Rx32;
556  let Inst{4-0} = Rx32{4-0};
557}
558class Enc_28dcbb : OpcodeHexagon {
559  bits <5> Rt32;
560  let Inst{20-16} = Rt32{4-0};
561  bits <1> Mu2;
562  let Inst{13-13} = Mu2{0-0};
563  bits <5> Vvv32;
564  let Inst{4-0} = Vvv32{4-0};
565}
566class Enc_2a3787 : OpcodeHexagon {
567  bits <13> Ii;
568  let Inst{26-25} = Ii{12-11};
569  let Inst{13-5} = Ii{10-2};
570  bits <5> Rs32;
571  let Inst{20-16} = Rs32{4-0};
572  bits <5> Rd32;
573  let Inst{4-0} = Rd32{4-0};
574}
575class Enc_2a7b91 : OpcodeHexagon {
576  bits <6> Ii;
577  let Inst{20-16} = Ii{5-1};
578  let Inst{8-8} = Ii{0-0};
579  bits <2> Pt4;
580  let Inst{10-9} = Pt4{1-0};
581  bits <5> Rdd32;
582  let Inst{4-0} = Rdd32{4-0};
583}
584class Enc_2ae154 : OpcodeHexagon {
585  bits <5> Rs32;
586  let Inst{20-16} = Rs32{4-0};
587  bits <5> Rt32;
588  let Inst{12-8} = Rt32{4-0};
589  bits <5> Rx32;
590  let Inst{4-0} = Rx32{4-0};
591}
592class Enc_2b3f60 : OpcodeHexagon {
593  bits <5> Rss32;
594  let Inst{20-16} = Rss32{4-0};
595  bits <5> Rtt32;
596  let Inst{12-8} = Rtt32{4-0};
597  bits <5> Rdd32;
598  let Inst{4-0} = Rdd32{4-0};
599  bits <2> Px4;
600  let Inst{6-5} = Px4{1-0};
601}
602class Enc_2b518f : OpcodeHexagon {
603  bits <32> Ii;
604  let Inst{27-16} = Ii{31-20};
605  let Inst{13-0} = Ii{19-6};
606}
607class Enc_2bae10 : OpcodeHexagon {
608  bits <4> Ii;
609  let Inst{10-8} = Ii{3-1};
610  bits <4> Rs16;
611  let Inst{7-4} = Rs16{3-0};
612  bits <4> Rd16;
613  let Inst{3-0} = Rd16{3-0};
614}
615class Enc_2d7491 : OpcodeHexagon {
616  bits <13> Ii;
617  let Inst{26-25} = Ii{12-11};
618  let Inst{13-5} = Ii{10-2};
619  bits <5> Rs32;
620  let Inst{20-16} = Rs32{4-0};
621  bits <5> Rdd32;
622  let Inst{4-0} = Rdd32{4-0};
623}
624class Enc_2d829e : OpcodeHexagon {
625  bits <14> Ii;
626  let Inst{10-0} = Ii{13-3};
627  bits <5> Rs32;
628  let Inst{20-16} = Rs32{4-0};
629}
630class Enc_2df31d : OpcodeHexagon {
631  bits <8> Ii;
632  let Inst{9-4} = Ii{7-2};
633  bits <4> Rd16;
634  let Inst{3-0} = Rd16{3-0};
635}
636class Enc_2e1979 : OpcodeHexagon {
637  bits <2> Ii;
638  let Inst{13-13} = Ii{1-1};
639  let Inst{7-7} = Ii{0-0};
640  bits <2> Pv4;
641  let Inst{6-5} = Pv4{1-0};
642  bits <5> Rs32;
643  let Inst{20-16} = Rs32{4-0};
644  bits <5> Rt32;
645  let Inst{12-8} = Rt32{4-0};
646  bits <5> Rd32;
647  let Inst{4-0} = Rd32{4-0};
648}
649class Enc_2ea740 : OpcodeHexagon {
650  bits <4> Ii;
651  let Inst{13-13} = Ii{3-3};
652  let Inst{10-8} = Ii{2-0};
653  bits <2> Qv4;
654  let Inst{12-11} = Qv4{1-0};
655  bits <5> Rt32;
656  let Inst{20-16} = Rt32{4-0};
657  bits <5> Vs32;
658  let Inst{4-0} = Vs32{4-0};
659}
660class Enc_2ebe3b : OpcodeHexagon {
661  bits <1> Mu2;
662  let Inst{13-13} = Mu2{0-0};
663  bits <5> Vd32;
664  let Inst{4-0} = Vd32{4-0};
665  bits <5> Rx32;
666  let Inst{20-16} = Rx32{4-0};
667}
668class Enc_2f2f04 : OpcodeHexagon {
669  bits <1> Ii;
670  let Inst{5-5} = Ii{0-0};
671  bits <5> Vuu32;
672  let Inst{12-8} = Vuu32{4-0};
673  bits <5> Rt32;
674  let Inst{20-16} = Rt32{4-0};
675  bits <5> Vdd32;
676  let Inst{4-0} = Vdd32{4-0};
677}
678class Enc_2fbf3c : OpcodeHexagon {
679  bits <3> Ii;
680  let Inst{10-8} = Ii{2-0};
681  bits <4> Rs16;
682  let Inst{7-4} = Rs16{3-0};
683  bits <4> Rd16;
684  let Inst{3-0} = Rd16{3-0};
685}
686class Enc_310ba1 : OpcodeHexagon {
687  bits <5> Vu32;
688  let Inst{12-8} = Vu32{4-0};
689  bits <5> Rtt32;
690  let Inst{20-16} = Rtt32{4-0};
691  bits <5> Vx32;
692  let Inst{4-0} = Vx32{4-0};
693}
694class Enc_311abd : OpcodeHexagon {
695  bits <5> Ii;
696  let Inst{12-8} = Ii{4-0};
697  bits <5> Rs32;
698  let Inst{20-16} = Rs32{4-0};
699  bits <5> Rdd32;
700  let Inst{4-0} = Rdd32{4-0};
701}
702class Enc_31aa6a : OpcodeHexagon {
703  bits <5> Ii;
704  let Inst{6-3} = Ii{4-1};
705  bits <2> Pv4;
706  let Inst{1-0} = Pv4{1-0};
707  bits <3> Nt8;
708  let Inst{10-8} = Nt8{2-0};
709  bits <5> Rx32;
710  let Inst{20-16} = Rx32{4-0};
711}
712class Enc_31db33 : OpcodeHexagon {
713  bits <2> Qt4;
714  let Inst{6-5} = Qt4{1-0};
715  bits <5> Vu32;
716  let Inst{12-8} = Vu32{4-0};
717  bits <5> Vv32;
718  let Inst{20-16} = Vv32{4-0};
719  bits <5> Vd32;
720  let Inst{4-0} = Vd32{4-0};
721}
722class Enc_322e1b : OpcodeHexagon {
723  bits <6> Ii;
724  let Inst{22-21} = Ii{5-4};
725  let Inst{13-13} = Ii{3-3};
726  let Inst{7-5} = Ii{2-0};
727  bits <6> II;
728  let Inst{23-23} = II{5-5};
729  let Inst{4-0} = II{4-0};
730  bits <5> Rs32;
731  let Inst{20-16} = Rs32{4-0};
732  bits <5> Rd32;
733  let Inst{12-8} = Rd32{4-0};
734}
735class Enc_323f2d : OpcodeHexagon {
736  bits <6> II;
737  let Inst{11-8} = II{5-2};
738  let Inst{6-5} = II{1-0};
739  bits <5> Rd32;
740  let Inst{4-0} = Rd32{4-0};
741  bits <5> Re32;
742  let Inst{20-16} = Re32{4-0};
743}
744class Enc_329361 : OpcodeHexagon {
745  bits <2> Pu4;
746  let Inst{6-5} = Pu4{1-0};
747  bits <5> Rss32;
748  let Inst{20-16} = Rss32{4-0};
749  bits <5> Rtt32;
750  let Inst{12-8} = Rtt32{4-0};
751  bits <5> Rdd32;
752  let Inst{4-0} = Rdd32{4-0};
753}
754class Enc_33f8ba : OpcodeHexagon {
755  bits <8> Ii;
756  let Inst{12-8} = Ii{7-3};
757  let Inst{4-2} = Ii{2-0};
758  bits <5> Rx32;
759  let Inst{20-16} = Rx32{4-0};
760}
761class Enc_3680c2 : OpcodeHexagon {
762  bits <7> Ii;
763  let Inst{11-5} = Ii{6-0};
764  bits <5> Rss32;
765  let Inst{20-16} = Rss32{4-0};
766  bits <2> Pd4;
767  let Inst{1-0} = Pd4{1-0};
768}
769class Enc_3694bd : OpcodeHexagon {
770  bits <11> Ii;
771  let Inst{21-20} = Ii{10-9};
772  let Inst{7-1} = Ii{8-2};
773  bits <3> Ns8;
774  let Inst{18-16} = Ns8{2-0};
775  bits <5> n1;
776  let Inst{29-29} = n1{4-4};
777  let Inst{26-25} = n1{3-2};
778  let Inst{23-22} = n1{1-0};
779}
780class Enc_372c9d : OpcodeHexagon {
781  bits <2> Pv4;
782  let Inst{12-11} = Pv4{1-0};
783  bits <1> Mu2;
784  let Inst{13-13} = Mu2{0-0};
785  bits <3> Os8;
786  let Inst{2-0} = Os8{2-0};
787  bits <5> Rx32;
788  let Inst{20-16} = Rx32{4-0};
789}
790class Enc_395cc4 : OpcodeHexagon {
791  bits <7> Ii;
792  let Inst{6-3} = Ii{6-3};
793  bits <1> Mu2;
794  let Inst{13-13} = Mu2{0-0};
795  bits <5> Rtt32;
796  let Inst{12-8} = Rtt32{4-0};
797  bits <5> Rx32;
798  let Inst{20-16} = Rx32{4-0};
799}
800class Enc_397f23 : OpcodeHexagon {
801  bits <8> Ii;
802  let Inst{13-13} = Ii{7-7};
803  let Inst{7-3} = Ii{6-2};
804  bits <2> Pv4;
805  let Inst{1-0} = Pv4{1-0};
806  bits <5> Rs32;
807  let Inst{20-16} = Rs32{4-0};
808  bits <5> Rt32;
809  let Inst{12-8} = Rt32{4-0};
810}
811class Enc_399e12 : OpcodeHexagon {
812  bits <4> Rs16;
813  let Inst{7-4} = Rs16{3-0};
814  bits <3> Rdd8;
815  let Inst{2-0} = Rdd8{2-0};
816}
817class Enc_3a2484 : OpcodeHexagon {
818  bits <11> Ii;
819  let Inst{21-20} = Ii{10-9};
820  let Inst{7-1} = Ii{8-2};
821  bits <4> Rs16;
822  let Inst{19-16} = Rs16{3-0};
823  bits <4> n1;
824  let Inst{28-28} = n1{3-3};
825  let Inst{24-23} = n1{2-1};
826  let Inst{13-13} = n1{0-0};
827}
828class Enc_3a3d62 : OpcodeHexagon {
829  bits <5> Rs32;
830  let Inst{20-16} = Rs32{4-0};
831  bits <5> Rdd32;
832  let Inst{4-0} = Rdd32{4-0};
833}
834class Enc_3b7631 : OpcodeHexagon {
835  bits <5> Vu32;
836  let Inst{12-8} = Vu32{4-0};
837  bits <5> Vdddd32;
838  let Inst{4-0} = Vdddd32{4-0};
839  bits <3> Rx8;
840  let Inst{18-16} = Rx8{2-0};
841}
842class Enc_3d5b28 : OpcodeHexagon {
843  bits <5> Rss32;
844  let Inst{20-16} = Rss32{4-0};
845  bits <5> Rt32;
846  let Inst{12-8} = Rt32{4-0};
847  bits <5> Rd32;
848  let Inst{4-0} = Rd32{4-0};
849}
850class Enc_3d6d37 : OpcodeHexagon {
851  bits <2> Qs4;
852  let Inst{6-5} = Qs4{1-0};
853  bits <5> Rt32;
854  let Inst{20-16} = Rt32{4-0};
855  bits <1> Mu2;
856  let Inst{13-13} = Mu2{0-0};
857  bits <5> Vvv32;
858  let Inst{12-8} = Vvv32{4-0};
859  bits <5> Vw32;
860  let Inst{4-0} = Vw32{4-0};
861}
862class Enc_3d920a : OpcodeHexagon {
863  bits <6> Ii;
864  let Inst{8-5} = Ii{5-2};
865  bits <5> Rd32;
866  let Inst{4-0} = Rd32{4-0};
867  bits <5> Rx32;
868  let Inst{20-16} = Rx32{4-0};
869}
870class Enc_3dac0b : OpcodeHexagon {
871  bits <2> Qt4;
872  let Inst{6-5} = Qt4{1-0};
873  bits <5> Vu32;
874  let Inst{12-8} = Vu32{4-0};
875  bits <5> Vv32;
876  let Inst{20-16} = Vv32{4-0};
877  bits <5> Vdd32;
878  let Inst{4-0} = Vdd32{4-0};
879}
880class Enc_3e3989 : OpcodeHexagon {
881  bits <11> Ii;
882  let Inst{21-20} = Ii{10-9};
883  let Inst{7-1} = Ii{8-2};
884  bits <4> Rs16;
885  let Inst{19-16} = Rs16{3-0};
886  bits <6> n1;
887  let Inst{28-28} = n1{5-5};
888  let Inst{25-22} = n1{4-1};
889  let Inst{8-8} = n1{0-0};
890}
891class Enc_3f97c8 : OpcodeHexagon {
892  bits <6> Ii;
893  let Inst{6-3} = Ii{5-2};
894  bits <1> Mu2;
895  let Inst{13-13} = Mu2{0-0};
896  bits <3> Nt8;
897  let Inst{10-8} = Nt8{2-0};
898  bits <5> Rx32;
899  let Inst{20-16} = Rx32{4-0};
900}
901class Enc_3fc427 : OpcodeHexagon {
902  bits <5> Vu32;
903  let Inst{12-8} = Vu32{4-0};
904  bits <5> Vv32;
905  let Inst{20-16} = Vv32{4-0};
906  bits <5> Vxx32;
907  let Inst{4-0} = Vxx32{4-0};
908}
909class Enc_403871 : OpcodeHexagon {
910  bits <5> Rx32;
911  let Inst{20-16} = Rx32{4-0};
912}
913class Enc_405228 : OpcodeHexagon {
914  bits <11> Ii;
915  let Inst{21-20} = Ii{10-9};
916  let Inst{7-1} = Ii{8-2};
917  bits <4> Rs16;
918  let Inst{19-16} = Rs16{3-0};
919  bits <3> n1;
920  let Inst{28-28} = n1{2-2};
921  let Inst{24-23} = n1{1-0};
922}
923class Enc_412ff0 : OpcodeHexagon {
924  bits <5> Rss32;
925  let Inst{20-16} = Rss32{4-0};
926  bits <5> Ru32;
927  let Inst{4-0} = Ru32{4-0};
928  bits <5> Rxx32;
929  let Inst{12-8} = Rxx32{4-0};
930}
931class Enc_420cf3 : OpcodeHexagon {
932  bits <6> Ii;
933  let Inst{22-21} = Ii{5-4};
934  let Inst{13-13} = Ii{3-3};
935  let Inst{7-5} = Ii{2-0};
936  bits <5> Ru32;
937  let Inst{4-0} = Ru32{4-0};
938  bits <5> Rs32;
939  let Inst{20-16} = Rs32{4-0};
940  bits <5> Rd32;
941  let Inst{12-8} = Rd32{4-0};
942}
943class Enc_437f33 : OpcodeHexagon {
944  bits <5> Rs32;
945  let Inst{20-16} = Rs32{4-0};
946  bits <5> Rt32;
947  let Inst{12-8} = Rt32{4-0};
948  bits <2> Pu4;
949  let Inst{6-5} = Pu4{1-0};
950  bits <5> Rx32;
951  let Inst{4-0} = Rx32{4-0};
952}
953class Enc_44215c : OpcodeHexagon {
954  bits <6> Ii;
955  let Inst{17-16} = Ii{5-4};
956  let Inst{6-3} = Ii{3-0};
957  bits <2> Pv4;
958  let Inst{1-0} = Pv4{1-0};
959  bits <3> Nt8;
960  let Inst{10-8} = Nt8{2-0};
961}
962class Enc_44271f : OpcodeHexagon {
963  bits <5> Gs32;
964  let Inst{20-16} = Gs32{4-0};
965  bits <5> Rd32;
966  let Inst{4-0} = Rd32{4-0};
967}
968class Enc_44661f : OpcodeHexagon {
969  bits <1> Mu2;
970  let Inst{13-13} = Mu2{0-0};
971  bits <5> Rx32;
972  let Inst{20-16} = Rx32{4-0};
973}
974class Enc_448f7f : OpcodeHexagon {
975  bits <11> Ii;
976  let Inst{26-25} = Ii{10-9};
977  let Inst{13-13} = Ii{8-8};
978  let Inst{7-0} = Ii{7-0};
979  bits <5> Rs32;
980  let Inst{20-16} = Rs32{4-0};
981  bits <5> Rt32;
982  let Inst{12-8} = Rt32{4-0};
983}
984class Enc_45364e : OpcodeHexagon {
985  bits <5> Vu32;
986  let Inst{12-8} = Vu32{4-0};
987  bits <5> Vv32;
988  let Inst{20-16} = Vv32{4-0};
989  bits <5> Vd32;
990  let Inst{4-0} = Vd32{4-0};
991}
992class Enc_454a26 : OpcodeHexagon {
993  bits <2> Pt4;
994  let Inst{9-8} = Pt4{1-0};
995  bits <2> Ps4;
996  let Inst{17-16} = Ps4{1-0};
997  bits <2> Pd4;
998  let Inst{1-0} = Pd4{1-0};
999}
1000class Enc_46c951 : OpcodeHexagon {
1001  bits <6> Ii;
1002  let Inst{12-7} = Ii{5-0};
1003  bits <5> II;
1004  let Inst{4-0} = II{4-0};
1005  bits <5> Rs32;
1006  let Inst{20-16} = Rs32{4-0};
1007}
1008class Enc_47ee5e : OpcodeHexagon {
1009  bits <2> Ii;
1010  let Inst{13-13} = Ii{1-1};
1011  let Inst{7-7} = Ii{0-0};
1012  bits <2> Pv4;
1013  let Inst{6-5} = Pv4{1-0};
1014  bits <5> Rs32;
1015  let Inst{20-16} = Rs32{4-0};
1016  bits <5> Ru32;
1017  let Inst{12-8} = Ru32{4-0};
1018  bits <3> Nt8;
1019  let Inst{2-0} = Nt8{2-0};
1020}
1021class Enc_47ef61 : OpcodeHexagon {
1022  bits <3> Ii;
1023  let Inst{7-5} = Ii{2-0};
1024  bits <5> Rt32;
1025  let Inst{12-8} = Rt32{4-0};
1026  bits <5> Rs32;
1027  let Inst{20-16} = Rs32{4-0};
1028  bits <5> Rd32;
1029  let Inst{4-0} = Rd32{4-0};
1030}
1031class Enc_48b75f : OpcodeHexagon {
1032  bits <5> Rs32;
1033  let Inst{20-16} = Rs32{4-0};
1034  bits <2> Pd4;
1035  let Inst{1-0} = Pd4{1-0};
1036}
1037class Enc_4aca3a : OpcodeHexagon {
1038  bits <11> Ii;
1039  let Inst{21-20} = Ii{10-9};
1040  let Inst{7-1} = Ii{8-2};
1041  bits <3> Ns8;
1042  let Inst{18-16} = Ns8{2-0};
1043  bits <3> n1;
1044  let Inst{29-29} = n1{2-2};
1045  let Inst{26-25} = n1{1-0};
1046}
1047class Enc_4b39e4 : OpcodeHexagon {
1048  bits <3> Ii;
1049  let Inst{7-5} = Ii{2-0};
1050  bits <5> Vu32;
1051  let Inst{12-8} = Vu32{4-0};
1052  bits <5> Vv32;
1053  let Inst{20-16} = Vv32{4-0};
1054  bits <5> Vdd32;
1055  let Inst{4-0} = Vdd32{4-0};
1056}
1057class Enc_4dc228 : OpcodeHexagon {
1058  bits <9> Ii;
1059  let Inst{12-8} = Ii{8-4};
1060  let Inst{4-3} = Ii{3-2};
1061  bits <10> II;
1062  let Inst{20-16} = II{9-5};
1063  let Inst{7-5} = II{4-2};
1064  let Inst{1-0} = II{1-0};
1065}
1066class Enc_4df4e9 : OpcodeHexagon {
1067  bits <11> Ii;
1068  let Inst{26-25} = Ii{10-9};
1069  let Inst{13-13} = Ii{8-8};
1070  let Inst{7-0} = Ii{7-0};
1071  bits <5> Rs32;
1072  let Inst{20-16} = Rs32{4-0};
1073  bits <3> Nt8;
1074  let Inst{10-8} = Nt8{2-0};
1075}
1076class Enc_4dff07 : OpcodeHexagon {
1077  bits <2> Qv4;
1078  let Inst{12-11} = Qv4{1-0};
1079  bits <1> Mu2;
1080  let Inst{13-13} = Mu2{0-0};
1081  bits <5> Vs32;
1082  let Inst{4-0} = Vs32{4-0};
1083  bits <5> Rx32;
1084  let Inst{20-16} = Rx32{4-0};
1085}
1086class Enc_4e4a80 : OpcodeHexagon {
1087  bits <2> Qs4;
1088  let Inst{6-5} = Qs4{1-0};
1089  bits <5> Rt32;
1090  let Inst{20-16} = Rt32{4-0};
1091  bits <1> Mu2;
1092  let Inst{13-13} = Mu2{0-0};
1093  bits <5> Vvv32;
1094  let Inst{4-0} = Vvv32{4-0};
1095}
1096class Enc_4f4ed7 : OpcodeHexagon {
1097  bits <18> Ii;
1098  let Inst{26-25} = Ii{17-16};
1099  let Inst{20-16} = Ii{15-11};
1100  let Inst{13-5} = Ii{10-2};
1101  bits <5> Rd32;
1102  let Inst{4-0} = Rd32{4-0};
1103}
1104class Enc_4f677b : OpcodeHexagon {
1105  bits <2> Ii;
1106  let Inst{13-13} = Ii{1-1};
1107  let Inst{7-7} = Ii{0-0};
1108  bits <6> II;
1109  let Inst{11-8} = II{5-2};
1110  let Inst{6-5} = II{1-0};
1111  bits <5> Rt32;
1112  let Inst{20-16} = Rt32{4-0};
1113  bits <5> Rd32;
1114  let Inst{4-0} = Rd32{4-0};
1115}
1116class Enc_500cb0 : OpcodeHexagon {
1117  bits <5> Vu32;
1118  let Inst{12-8} = Vu32{4-0};
1119  bits <5> Vxx32;
1120  let Inst{4-0} = Vxx32{4-0};
1121}
1122class Enc_509701 : OpcodeHexagon {
1123  bits <19> Ii;
1124  let Inst{26-25} = Ii{18-17};
1125  let Inst{20-16} = Ii{16-12};
1126  let Inst{13-5} = Ii{11-3};
1127  bits <5> Rdd32;
1128  let Inst{4-0} = Rdd32{4-0};
1129}
1130class Enc_50b5ac : OpcodeHexagon {
1131  bits <6> Ii;
1132  let Inst{17-16} = Ii{5-4};
1133  let Inst{6-3} = Ii{3-0};
1134  bits <2> Pv4;
1135  let Inst{1-0} = Pv4{1-0};
1136  bits <5> Rtt32;
1137  let Inst{12-8} = Rtt32{4-0};
1138}
1139class Enc_50e578 : OpcodeHexagon {
1140  bits <5> Vu32;
1141  let Inst{12-8} = Vu32{4-0};
1142  bits <5> Rs32;
1143  let Inst{20-16} = Rs32{4-0};
1144  bits <5> Rd32;
1145  let Inst{4-0} = Rd32{4-0};
1146}
1147class Enc_5138b3 : OpcodeHexagon {
1148  bits <5> Vu32;
1149  let Inst{12-8} = Vu32{4-0};
1150  bits <5> Rt32;
1151  let Inst{20-16} = Rt32{4-0};
1152  bits <5> Vx32;
1153  let Inst{4-0} = Vx32{4-0};
1154}
1155class Enc_51436c : OpcodeHexagon {
1156  bits <16> Ii;
1157  let Inst{23-22} = Ii{15-14};
1158  let Inst{13-0} = Ii{13-0};
1159  bits <5> Rx32;
1160  let Inst{20-16} = Rx32{4-0};
1161}
1162class Enc_51635c : OpcodeHexagon {
1163  bits <7> Ii;
1164  let Inst{8-4} = Ii{6-2};
1165  bits <4> Rd16;
1166  let Inst{3-0} = Rd16{3-0};
1167}
1168class Enc_527412 : OpcodeHexagon {
1169  bits <2> Ps4;
1170  let Inst{17-16} = Ps4{1-0};
1171  bits <2> Pt4;
1172  let Inst{9-8} = Pt4{1-0};
1173  bits <5> Rd32;
1174  let Inst{4-0} = Rd32{4-0};
1175}
1176class Enc_52a5dd : OpcodeHexagon {
1177  bits <4> Ii;
1178  let Inst{6-3} = Ii{3-0};
1179  bits <2> Pv4;
1180  let Inst{1-0} = Pv4{1-0};
1181  bits <3> Nt8;
1182  let Inst{10-8} = Nt8{2-0};
1183  bits <5> Rx32;
1184  let Inst{20-16} = Rx32{4-0};
1185}
1186class Enc_53dca9 : OpcodeHexagon {
1187  bits <6> Ii;
1188  let Inst{11-8} = Ii{5-2};
1189  bits <4> Rs16;
1190  let Inst{7-4} = Rs16{3-0};
1191  bits <4> Rd16;
1192  let Inst{3-0} = Rd16{3-0};
1193}
1194class Enc_541f26 : OpcodeHexagon {
1195  bits <18> Ii;
1196  let Inst{26-25} = Ii{17-16};
1197  let Inst{20-16} = Ii{15-11};
1198  let Inst{13-13} = Ii{10-10};
1199  let Inst{7-0} = Ii{9-2};
1200  bits <5> Rt32;
1201  let Inst{12-8} = Rt32{4-0};
1202}
1203class Enc_55355c : OpcodeHexagon {
1204  bits <2> Ii;
1205  let Inst{13-13} = Ii{1-1};
1206  let Inst{7-7} = Ii{0-0};
1207  bits <5> Rs32;
1208  let Inst{20-16} = Rs32{4-0};
1209  bits <5> Ru32;
1210  let Inst{12-8} = Ru32{4-0};
1211  bits <5> Rtt32;
1212  let Inst{4-0} = Rtt32{4-0};
1213}
1214class Enc_569cfe : OpcodeHexagon {
1215  bits <5> Rt32;
1216  let Inst{20-16} = Rt32{4-0};
1217  bits <5> Vx32;
1218  let Inst{4-0} = Vx32{4-0};
1219}
1220class Enc_57a33e : OpcodeHexagon {
1221  bits <9> Ii;
1222  let Inst{13-13} = Ii{8-8};
1223  let Inst{7-3} = Ii{7-3};
1224  bits <2> Pv4;
1225  let Inst{1-0} = Pv4{1-0};
1226  bits <5> Rs32;
1227  let Inst{20-16} = Rs32{4-0};
1228  bits <5> Rtt32;
1229  let Inst{12-8} = Rtt32{4-0};
1230}
1231class Enc_585242 : OpcodeHexagon {
1232  bits <6> Ii;
1233  let Inst{13-13} = Ii{5-5};
1234  let Inst{7-3} = Ii{4-0};
1235  bits <2> Pv4;
1236  let Inst{1-0} = Pv4{1-0};
1237  bits <5> Rs32;
1238  let Inst{20-16} = Rs32{4-0};
1239  bits <3> Nt8;
1240  let Inst{10-8} = Nt8{2-0};
1241}
1242class Enc_58a8bf : OpcodeHexagon {
1243  bits <3> Ii;
1244  let Inst{10-8} = Ii{2-0};
1245  bits <2> Pv4;
1246  let Inst{12-11} = Pv4{1-0};
1247  bits <5> Vd32;
1248  let Inst{4-0} = Vd32{4-0};
1249  bits <5> Rx32;
1250  let Inst{20-16} = Rx32{4-0};
1251}
1252class Enc_5a18b3 : OpcodeHexagon {
1253  bits <11> Ii;
1254  let Inst{21-20} = Ii{10-9};
1255  let Inst{7-1} = Ii{8-2};
1256  bits <3> Ns8;
1257  let Inst{18-16} = Ns8{2-0};
1258  bits <5> n1;
1259  let Inst{29-29} = n1{4-4};
1260  let Inst{26-25} = n1{3-2};
1261  let Inst{22-22} = n1{1-1};
1262  let Inst{13-13} = n1{0-0};
1263}
1264class Enc_5ab2be : OpcodeHexagon {
1265  bits <5> Rs32;
1266  let Inst{20-16} = Rs32{4-0};
1267  bits <5> Rt32;
1268  let Inst{12-8} = Rt32{4-0};
1269  bits <5> Rd32;
1270  let Inst{4-0} = Rd32{4-0};
1271}
1272class Enc_5bdd42 : OpcodeHexagon {
1273  bits <7> Ii;
1274  let Inst{8-5} = Ii{6-3};
1275  bits <5> Rdd32;
1276  let Inst{4-0} = Rdd32{4-0};
1277  bits <5> Rx32;
1278  let Inst{20-16} = Rx32{4-0};
1279}
1280class Enc_5c124a : OpcodeHexagon {
1281  bits <19> Ii;
1282  let Inst{26-25} = Ii{18-17};
1283  let Inst{20-16} = Ii{16-12};
1284  let Inst{13-13} = Ii{11-11};
1285  let Inst{7-0} = Ii{10-3};
1286  bits <5> Rtt32;
1287  let Inst{12-8} = Rtt32{4-0};
1288}
1289class Enc_5ccba9 : OpcodeHexagon {
1290  bits <8> Ii;
1291  let Inst{12-7} = Ii{7-2};
1292  bits <6> II;
1293  let Inst{13-13} = II{5-5};
1294  let Inst{4-0} = II{4-0};
1295  bits <2> Pv4;
1296  let Inst{6-5} = Pv4{1-0};
1297  bits <5> Rs32;
1298  let Inst{20-16} = Rs32{4-0};
1299}
1300class Enc_5cd7e9 : OpcodeHexagon {
1301  bits <12> Ii;
1302  let Inst{26-25} = Ii{11-10};
1303  let Inst{13-5} = Ii{9-1};
1304  bits <5> Rs32;
1305  let Inst{20-16} = Rs32{4-0};
1306  bits <5> Ryy32;
1307  let Inst{4-0} = Ryy32{4-0};
1308}
1309class Enc_5d6c34 : OpcodeHexagon {
1310  bits <6> Ii;
1311  let Inst{13-8} = Ii{5-0};
1312  bits <5> Rs32;
1313  let Inst{20-16} = Rs32{4-0};
1314  bits <2> Pd4;
1315  let Inst{1-0} = Pd4{1-0};
1316}
1317class Enc_5de85f : OpcodeHexagon {
1318  bits <11> Ii;
1319  let Inst{21-20} = Ii{10-9};
1320  let Inst{7-1} = Ii{8-2};
1321  bits <5> Rt32;
1322  let Inst{12-8} = Rt32{4-0};
1323  bits <3> Ns8;
1324  let Inst{18-16} = Ns8{2-0};
1325}
1326class Enc_5e2823 : OpcodeHexagon {
1327  bits <5> Rs32;
1328  let Inst{20-16} = Rs32{4-0};
1329  bits <5> Rd32;
1330  let Inst{4-0} = Rd32{4-0};
1331}
1332class Enc_5e8512 : OpcodeHexagon {
1333  bits <5> Vu32;
1334  let Inst{12-8} = Vu32{4-0};
1335  bits <5> Rt32;
1336  let Inst{20-16} = Rt32{4-0};
1337  bits <5> Vxx32;
1338  let Inst{4-0} = Vxx32{4-0};
1339}
1340class Enc_5e87ce : OpcodeHexagon {
1341  bits <16> Ii;
1342  let Inst{23-22} = Ii{15-14};
1343  let Inst{20-16} = Ii{13-9};
1344  let Inst{13-5} = Ii{8-0};
1345  bits <5> Rd32;
1346  let Inst{4-0} = Rd32{4-0};
1347}
1348class Enc_5eac98 : OpcodeHexagon {
1349  bits <6> Ii;
1350  let Inst{13-8} = Ii{5-0};
1351  bits <5> Rss32;
1352  let Inst{20-16} = Rss32{4-0};
1353  bits <5> Rdd32;
1354  let Inst{4-0} = Rdd32{4-0};
1355}
1356class Enc_5eb169 : OpcodeHexagon {
1357  bits <3> Ii;
1358  let Inst{10-8} = Ii{2-0};
1359  bits <5> Vdd32;
1360  let Inst{4-0} = Vdd32{4-0};
1361  bits <5> Rx32;
1362  let Inst{20-16} = Rx32{4-0};
1363}
1364class Enc_607661 : OpcodeHexagon {
1365  bits <6> Ii;
1366  let Inst{12-7} = Ii{5-0};
1367  bits <5> Rd32;
1368  let Inst{4-0} = Rd32{4-0};
1369}
1370class Enc_6185fe : OpcodeHexagon {
1371  bits <2> Ii;
1372  let Inst{13-13} = Ii{1-1};
1373  let Inst{7-7} = Ii{0-0};
1374  bits <6> II;
1375  let Inst{11-8} = II{5-2};
1376  let Inst{6-5} = II{1-0};
1377  bits <5> Rt32;
1378  let Inst{20-16} = Rt32{4-0};
1379  bits <5> Rdd32;
1380  let Inst{4-0} = Rdd32{4-0};
1381}
1382class Enc_61f0b0 : OpcodeHexagon {
1383  bits <5> Rs32;
1384  let Inst{20-16} = Rs32{4-0};
1385  bits <5> Rt32;
1386  let Inst{12-8} = Rt32{4-0};
1387  bits <5> Rxx32;
1388  let Inst{4-0} = Rxx32{4-0};
1389}
1390class Enc_621fba : OpcodeHexagon {
1391  bits <5> Rs32;
1392  let Inst{20-16} = Rs32{4-0};
1393  bits <5> Gd32;
1394  let Inst{4-0} = Gd32{4-0};
1395}
1396class Enc_625deb : OpcodeHexagon {
1397  bits <4> Ii;
1398  let Inst{10-8} = Ii{3-1};
1399  bits <4> Rs16;
1400  let Inst{7-4} = Rs16{3-0};
1401  bits <4> Rt16;
1402  let Inst{3-0} = Rt16{3-0};
1403}
1404class Enc_6339d5 : OpcodeHexagon {
1405  bits <2> Ii;
1406  let Inst{13-13} = Ii{1-1};
1407  let Inst{7-7} = Ii{0-0};
1408  bits <2> Pv4;
1409  let Inst{6-5} = Pv4{1-0};
1410  bits <5> Rs32;
1411  let Inst{20-16} = Rs32{4-0};
1412  bits <5> Ru32;
1413  let Inst{12-8} = Ru32{4-0};
1414  bits <5> Rt32;
1415  let Inst{4-0} = Rt32{4-0};
1416}
1417class Enc_634460 : OpcodeHexagon {
1418  bits <4> Ii;
1419  let Inst{13-13} = Ii{3-3};
1420  let Inst{10-8} = Ii{2-0};
1421  bits <5> Rt32;
1422  let Inst{20-16} = Rt32{4-0};
1423  bits <5> Vdd32;
1424  let Inst{4-0} = Vdd32{4-0};
1425}
1426class Enc_63eaeb : OpcodeHexagon {
1427  bits <2> Ii;
1428  let Inst{1-0} = Ii{1-0};
1429  bits <4> Rs16;
1430  let Inst{7-4} = Rs16{3-0};
1431}
1432class Enc_6413b6 : OpcodeHexagon {
1433  bits <11> Ii;
1434  let Inst{21-20} = Ii{10-9};
1435  let Inst{7-1} = Ii{8-2};
1436  bits <3> Ns8;
1437  let Inst{18-16} = Ns8{2-0};
1438  bits <5> n1;
1439  let Inst{29-29} = n1{4-4};
1440  let Inst{26-25} = n1{3-2};
1441  let Inst{23-23} = n1{1-1};
1442  let Inst{13-13} = n1{0-0};
1443}
1444class Enc_645d54 : OpcodeHexagon {
1445  bits <2> Ii;
1446  let Inst{13-13} = Ii{1-1};
1447  let Inst{5-5} = Ii{0-0};
1448  bits <5> Rss32;
1449  let Inst{20-16} = Rss32{4-0};
1450  bits <5> Rt32;
1451  let Inst{12-8} = Rt32{4-0};
1452  bits <5> Rdd32;
1453  let Inst{4-0} = Rdd32{4-0};
1454}
1455class Enc_65d691 : OpcodeHexagon {
1456  bits <2> Ps4;
1457  let Inst{17-16} = Ps4{1-0};
1458  bits <2> Pd4;
1459  let Inst{1-0} = Pd4{1-0};
1460}
1461class Enc_65f095 : OpcodeHexagon {
1462  bits <6> Ii;
1463  let Inst{6-3} = Ii{5-2};
1464  bits <2> Pv4;
1465  let Inst{1-0} = Pv4{1-0};
1466  bits <3> Nt8;
1467  let Inst{10-8} = Nt8{2-0};
1468  bits <5> Rx32;
1469  let Inst{20-16} = Rx32{4-0};
1470}
1471class Enc_667b39 : OpcodeHexagon {
1472  bits <5> Css32;
1473  let Inst{20-16} = Css32{4-0};
1474  bits <5> Rdd32;
1475  let Inst{4-0} = Rdd32{4-0};
1476}
1477class Enc_668704 : OpcodeHexagon {
1478  bits <11> Ii;
1479  let Inst{21-20} = Ii{10-9};
1480  let Inst{7-1} = Ii{8-2};
1481  bits <4> Rs16;
1482  let Inst{19-16} = Rs16{3-0};
1483  bits <5> n1;
1484  let Inst{28-28} = n1{4-4};
1485  let Inst{25-22} = n1{3-0};
1486}
1487class Enc_66bce1 : OpcodeHexagon {
1488  bits <11> Ii;
1489  let Inst{21-20} = Ii{10-9};
1490  let Inst{7-1} = Ii{8-2};
1491  bits <4> Rs16;
1492  let Inst{19-16} = Rs16{3-0};
1493  bits <4> Rd16;
1494  let Inst{11-8} = Rd16{3-0};
1495}
1496class Enc_690862 : OpcodeHexagon {
1497  bits <13> Ii;
1498  let Inst{26-25} = Ii{12-11};
1499  let Inst{13-13} = Ii{10-10};
1500  let Inst{7-0} = Ii{9-2};
1501  bits <5> Rs32;
1502  let Inst{20-16} = Rs32{4-0};
1503  bits <3> Nt8;
1504  let Inst{10-8} = Nt8{2-0};
1505}
1506class Enc_691712 : OpcodeHexagon {
1507  bits <2> Pv4;
1508  let Inst{12-11} = Pv4{1-0};
1509  bits <1> Mu2;
1510  let Inst{13-13} = Mu2{0-0};
1511  bits <5> Rx32;
1512  let Inst{20-16} = Rx32{4-0};
1513}
1514class Enc_69d63b : OpcodeHexagon {
1515  bits <11> Ii;
1516  let Inst{21-20} = Ii{10-9};
1517  let Inst{7-1} = Ii{8-2};
1518  bits <3> Ns8;
1519  let Inst{18-16} = Ns8{2-0};
1520}
1521class Enc_6a5972 : OpcodeHexagon {
1522  bits <11> Ii;
1523  let Inst{21-20} = Ii{10-9};
1524  let Inst{7-1} = Ii{8-2};
1525  bits <4> Rs16;
1526  let Inst{19-16} = Rs16{3-0};
1527  bits <4> Rt16;
1528  let Inst{11-8} = Rt16{3-0};
1529}
1530class Enc_6b197f : OpcodeHexagon {
1531  bits <4> Ii;
1532  let Inst{8-5} = Ii{3-0};
1533  bits <5> Ryy32;
1534  let Inst{4-0} = Ryy32{4-0};
1535  bits <5> Rx32;
1536  let Inst{20-16} = Rx32{4-0};
1537}
1538class Enc_6baed4 : OpcodeHexagon {
1539  bits <3> Ii;
1540  let Inst{10-8} = Ii{2-0};
1541  bits <2> Pv4;
1542  let Inst{12-11} = Pv4{1-0};
1543  bits <5> Rx32;
1544  let Inst{20-16} = Rx32{4-0};
1545}
1546class Enc_6c9440 : OpcodeHexagon {
1547  bits <10> Ii;
1548  let Inst{21-21} = Ii{9-9};
1549  let Inst{13-5} = Ii{8-0};
1550  bits <5> Rd32;
1551  let Inst{4-0} = Rd32{4-0};
1552}
1553class Enc_6c9ee0 : OpcodeHexagon {
1554  bits <3> Ii;
1555  let Inst{10-8} = Ii{2-0};
1556  bits <5> Rx32;
1557  let Inst{20-16} = Rx32{4-0};
1558}
1559class Enc_6f70ca : OpcodeHexagon {
1560  bits <8> Ii;
1561  let Inst{8-4} = Ii{7-3};
1562}
1563class Enc_6f83e7 : OpcodeHexagon {
1564  bits <2> Qv4;
1565  let Inst{23-22} = Qv4{1-0};
1566  bits <5> Vd32;
1567  let Inst{4-0} = Vd32{4-0};
1568}
1569class Enc_70b24b : OpcodeHexagon {
1570  bits <6> Ii;
1571  let Inst{8-5} = Ii{5-2};
1572  bits <1> Mu2;
1573  let Inst{13-13} = Mu2{0-0};
1574  bits <5> Rdd32;
1575  let Inst{4-0} = Rdd32{4-0};
1576  bits <5> Rx32;
1577  let Inst{20-16} = Rx32{4-0};
1578}
1579class Enc_70fb07 : OpcodeHexagon {
1580  bits <6> Ii;
1581  let Inst{13-8} = Ii{5-0};
1582  bits <5> Rss32;
1583  let Inst{20-16} = Rss32{4-0};
1584  bits <5> Rxx32;
1585  let Inst{4-0} = Rxx32{4-0};
1586}
1587class Enc_71bb9b : OpcodeHexagon {
1588  bits <5> Vu32;
1589  let Inst{12-8} = Vu32{4-0};
1590  bits <5> Vv32;
1591  let Inst{20-16} = Vv32{4-0};
1592  bits <5> Vdd32;
1593  let Inst{4-0} = Vdd32{4-0};
1594}
1595class Enc_71f1b4 : OpcodeHexagon {
1596  bits <6> Ii;
1597  let Inst{8-5} = Ii{5-2};
1598  bits <5> Rdd32;
1599  let Inst{4-0} = Rdd32{4-0};
1600  bits <5> Rx32;
1601  let Inst{20-16} = Rx32{4-0};
1602}
1603class Enc_7222b7 : OpcodeHexagon {
1604  bits <5> Rt32;
1605  let Inst{20-16} = Rt32{4-0};
1606  bits <2> Qd4;
1607  let Inst{1-0} = Qd4{1-0};
1608}
1609class Enc_724154 : OpcodeHexagon {
1610  bits <6> II;
1611  let Inst{5-0} = II{5-0};
1612  bits <3> Nt8;
1613  let Inst{10-8} = Nt8{2-0};
1614  bits <5> Re32;
1615  let Inst{20-16} = Re32{4-0};
1616}
1617class Enc_729ff7 : OpcodeHexagon {
1618  bits <3> Ii;
1619  let Inst{7-5} = Ii{2-0};
1620  bits <5> Rtt32;
1621  let Inst{12-8} = Rtt32{4-0};
1622  bits <5> Rss32;
1623  let Inst{20-16} = Rss32{4-0};
1624  bits <5> Rdd32;
1625  let Inst{4-0} = Rdd32{4-0};
1626}
1627class Enc_733b27 : OpcodeHexagon {
1628  bits <5> Ii;
1629  let Inst{8-5} = Ii{4-1};
1630  bits <2> Pt4;
1631  let Inst{10-9} = Pt4{1-0};
1632  bits <5> Rd32;
1633  let Inst{4-0} = Rd32{4-0};
1634  bits <5> Rx32;
1635  let Inst{20-16} = Rx32{4-0};
1636}
1637class Enc_736575 : OpcodeHexagon {
1638  bits <11> Ii;
1639  let Inst{21-20} = Ii{10-9};
1640  let Inst{7-1} = Ii{8-2};
1641  bits <4> Rs16;
1642  let Inst{19-16} = Rs16{3-0};
1643  bits <4> n1;
1644  let Inst{28-28} = n1{3-3};
1645  let Inst{25-23} = n1{2-0};
1646}
1647class Enc_74aef2 : OpcodeHexagon {
1648  bits <4> Ii;
1649  let Inst{8-5} = Ii{3-0};
1650  bits <1> Mu2;
1651  let Inst{13-13} = Mu2{0-0};
1652  bits <5> Ryy32;
1653  let Inst{4-0} = Ryy32{4-0};
1654  bits <5> Rx32;
1655  let Inst{20-16} = Rx32{4-0};
1656}
1657class Enc_74d4e5 : OpcodeHexagon {
1658  bits <1> Mu2;
1659  let Inst{13-13} = Mu2{0-0};
1660  bits <5> Rd32;
1661  let Inst{4-0} = Rd32{4-0};
1662  bits <5> Rx32;
1663  let Inst{20-16} = Rx32{4-0};
1664}
1665class Enc_770858 : OpcodeHexagon {
1666  bits <2> Ps4;
1667  let Inst{6-5} = Ps4{1-0};
1668  bits <5> Vu32;
1669  let Inst{12-8} = Vu32{4-0};
1670  bits <5> Vd32;
1671  let Inst{4-0} = Vd32{4-0};
1672}
1673class Enc_784502 : OpcodeHexagon {
1674  bits <3> Ii;
1675  let Inst{10-8} = Ii{2-0};
1676  bits <2> Pv4;
1677  let Inst{12-11} = Pv4{1-0};
1678  bits <3> Os8;
1679  let Inst{2-0} = Os8{2-0};
1680  bits <5> Rx32;
1681  let Inst{20-16} = Rx32{4-0};
1682}
1683class Enc_78cbf0 : OpcodeHexagon {
1684  bits <18> Ii;
1685  let Inst{26-25} = Ii{17-16};
1686  let Inst{20-16} = Ii{15-11};
1687  let Inst{13-13} = Ii{10-10};
1688  let Inst{7-0} = Ii{9-2};
1689  bits <3> Nt8;
1690  let Inst{10-8} = Nt8{2-0};
1691}
1692class Enc_78e566 : OpcodeHexagon {
1693  bits <2> Pt4;
1694  let Inst{9-8} = Pt4{1-0};
1695  bits <5> Rdd32;
1696  let Inst{4-0} = Rdd32{4-0};
1697}
1698class Enc_79b8c8 : OpcodeHexagon {
1699  bits <6> Ii;
1700  let Inst{6-3} = Ii{5-2};
1701  bits <1> Mu2;
1702  let Inst{13-13} = Mu2{0-0};
1703  bits <5> Rt32;
1704  let Inst{12-8} = Rt32{4-0};
1705  bits <5> Rx32;
1706  let Inst{20-16} = Rx32{4-0};
1707}
1708class Enc_7a0ea6 : OpcodeHexagon {
1709  bits <4> Rd16;
1710  let Inst{3-0} = Rd16{3-0};
1711  bits <1> n1;
1712  let Inst{9-9} = n1{0-0};
1713}
1714class Enc_7b523d : OpcodeHexagon {
1715  bits <5> Vu32;
1716  let Inst{12-8} = Vu32{4-0};
1717  bits <5> Vv32;
1718  let Inst{23-19} = Vv32{4-0};
1719  bits <3> Rt8;
1720  let Inst{18-16} = Rt8{2-0};
1721  bits <5> Vxx32;
1722  let Inst{4-0} = Vxx32{4-0};
1723}
1724class Enc_7b7ba8 : OpcodeHexagon {
1725  bits <2> Qu4;
1726  let Inst{9-8} = Qu4{1-0};
1727  bits <5> Rt32;
1728  let Inst{20-16} = Rt32{4-0};
1729  bits <5> Vd32;
1730  let Inst{4-0} = Vd32{4-0};
1731}
1732class Enc_7d1542 : OpcodeHexagon {
1733  bits <7> Ss128;
1734  let Inst{22-16} = Ss128{6-0};
1735  bits <5> Rd32;
1736  let Inst{4-0} = Rd32{4-0};
1737}
1738class Enc_7e5a82 : OpcodeHexagon {
1739  bits <5> Ii;
1740  let Inst{12-8} = Ii{4-0};
1741  bits <5> Rss32;
1742  let Inst{20-16} = Rss32{4-0};
1743  bits <5> Rdd32;
1744  let Inst{4-0} = Rdd32{4-0};
1745}
1746class Enc_7eaeb6 : OpcodeHexagon {
1747  bits <6> Ii;
1748  let Inst{6-3} = Ii{5-2};
1749  bits <2> Pv4;
1750  let Inst{1-0} = Pv4{1-0};
1751  bits <5> Rt32;
1752  let Inst{12-8} = Rt32{4-0};
1753  bits <5> Rx32;
1754  let Inst{20-16} = Rx32{4-0};
1755}
1756class Enc_7eb485 : OpcodeHexagon {
1757  bits <2> Ii;
1758  let Inst{13-13} = Ii{1-1};
1759  let Inst{6-6} = Ii{0-0};
1760  bits <6> II;
1761  let Inst{5-0} = II{5-0};
1762  bits <5> Ru32;
1763  let Inst{20-16} = Ru32{4-0};
1764  bits <3> Nt8;
1765  let Inst{10-8} = Nt8{2-0};
1766}
1767class Enc_7eee72 : OpcodeHexagon {
1768  bits <1> Mu2;
1769  let Inst{13-13} = Mu2{0-0};
1770  bits <5> Rdd32;
1771  let Inst{4-0} = Rdd32{4-0};
1772  bits <5> Rx32;
1773  let Inst{20-16} = Rx32{4-0};
1774}
1775class Enc_7f1a05 : OpcodeHexagon {
1776  bits <5> Ru32;
1777  let Inst{4-0} = Ru32{4-0};
1778  bits <5> Rs32;
1779  let Inst{20-16} = Rs32{4-0};
1780  bits <5> Ry32;
1781  let Inst{12-8} = Ry32{4-0};
1782}
1783class Enc_7fa7f6 : OpcodeHexagon {
1784  bits <6> II;
1785  let Inst{11-8} = II{5-2};
1786  let Inst{6-5} = II{1-0};
1787  bits <5> Rdd32;
1788  let Inst{4-0} = Rdd32{4-0};
1789  bits <5> Re32;
1790  let Inst{20-16} = Re32{4-0};
1791}
1792class Enc_800e04 : OpcodeHexagon {
1793  bits <11> Ii;
1794  let Inst{21-20} = Ii{10-9};
1795  let Inst{7-1} = Ii{8-2};
1796  bits <4> Rs16;
1797  let Inst{19-16} = Rs16{3-0};
1798  bits <6> n1;
1799  let Inst{28-28} = n1{5-5};
1800  let Inst{25-22} = n1{4-1};
1801  let Inst{13-13} = n1{0-0};
1802}
1803class Enc_80296d : OpcodeHexagon {
1804  bits <5> Rs32;
1805  let Inst{12-8} = Rs32{4-0};
1806  bits <5> Rtt32;
1807  let Inst{20-16} = Rtt32{4-0};
1808  bits <5> Rd32;
1809  let Inst{4-0} = Rd32{4-0};
1810}
1811class Enc_802dc0 : OpcodeHexagon {
1812  bits <1> Ii;
1813  let Inst{8-8} = Ii{0-0};
1814  bits <2> Qv4;
1815  let Inst{23-22} = Qv4{1-0};
1816}
1817class Enc_81ac1d : OpcodeHexagon {
1818  bits <24> Ii;
1819  let Inst{24-16} = Ii{23-15};
1820  let Inst{13-1} = Ii{14-2};
1821}
1822class Enc_8203bb : OpcodeHexagon {
1823  bits <6> Ii;
1824  let Inst{12-7} = Ii{5-0};
1825  bits <8> II;
1826  let Inst{13-13} = II{7-7};
1827  let Inst{6-0} = II{6-0};
1828  bits <5> Rs32;
1829  let Inst{20-16} = Rs32{4-0};
1830}
1831class Enc_829a68 : OpcodeHexagon {
1832  bits <1> Mu2;
1833  let Inst{13-13} = Mu2{0-0};
1834  bits <5> Vdd32;
1835  let Inst{4-0} = Vdd32{4-0};
1836  bits <5> Rx32;
1837  let Inst{20-16} = Rx32{4-0};
1838}
1839class Enc_830e5d : OpcodeHexagon {
1840  bits <8> Ii;
1841  let Inst{12-5} = Ii{7-0};
1842  bits <8> II;
1843  let Inst{22-16} = II{7-1};
1844  let Inst{13-13} = II{0-0};
1845  bits <2> Pu4;
1846  let Inst{24-23} = Pu4{1-0};
1847  bits <5> Rd32;
1848  let Inst{4-0} = Rd32{4-0};
1849}
1850class Enc_831a7d : OpcodeHexagon {
1851  bits <5> Rss32;
1852  let Inst{20-16} = Rss32{4-0};
1853  bits <5> Rtt32;
1854  let Inst{12-8} = Rtt32{4-0};
1855  bits <5> Rxx32;
1856  let Inst{4-0} = Rxx32{4-0};
1857  bits <2> Pe4;
1858  let Inst{6-5} = Pe4{1-0};
1859}
1860class Enc_83ee64 : OpcodeHexagon {
1861  bits <5> Ii;
1862  let Inst{12-8} = Ii{4-0};
1863  bits <5> Rs32;
1864  let Inst{20-16} = Rs32{4-0};
1865  bits <2> Pd4;
1866  let Inst{1-0} = Pd4{1-0};
1867}
1868class Enc_84b2cd : OpcodeHexagon {
1869  bits <8> Ii;
1870  let Inst{12-7} = Ii{7-2};
1871  bits <5> II;
1872  let Inst{4-0} = II{4-0};
1873  bits <5> Rs32;
1874  let Inst{20-16} = Rs32{4-0};
1875}
1876class Enc_84bff1 : OpcodeHexagon {
1877  bits <2> Ii;
1878  let Inst{13-13} = Ii{1-1};
1879  let Inst{7-7} = Ii{0-0};
1880  bits <5> Rs32;
1881  let Inst{20-16} = Rs32{4-0};
1882  bits <5> Rt32;
1883  let Inst{12-8} = Rt32{4-0};
1884  bits <5> Rdd32;
1885  let Inst{4-0} = Rdd32{4-0};
1886}
1887class Enc_84d359 : OpcodeHexagon {
1888  bits <4> Ii;
1889  let Inst{3-0} = Ii{3-0};
1890  bits <4> Rs16;
1891  let Inst{7-4} = Rs16{3-0};
1892}
1893class Enc_85bf58 : OpcodeHexagon {
1894  bits <7> Ii;
1895  let Inst{6-3} = Ii{6-3};
1896  bits <5> Rtt32;
1897  let Inst{12-8} = Rtt32{4-0};
1898  bits <5> Rx32;
1899  let Inst{20-16} = Rx32{4-0};
1900}
1901class Enc_864a5a : OpcodeHexagon {
1902  bits <9> Ii;
1903  let Inst{12-8} = Ii{8-4};
1904  let Inst{4-3} = Ii{3-2};
1905  bits <5> Rs32;
1906  let Inst{20-16} = Rs32{4-0};
1907}
1908class Enc_865390 : OpcodeHexagon {
1909  bits <3> Ii;
1910  let Inst{10-8} = Ii{2-0};
1911  bits <2> Pv4;
1912  let Inst{12-11} = Pv4{1-0};
1913  bits <5> Vs32;
1914  let Inst{4-0} = Vs32{4-0};
1915  bits <5> Rx32;
1916  let Inst{20-16} = Rx32{4-0};
1917}
1918class Enc_86a14b : OpcodeHexagon {
1919  bits <8> Ii;
1920  let Inst{7-3} = Ii{7-3};
1921  bits <3> Rdd8;
1922  let Inst{2-0} = Rdd8{2-0};
1923}
1924class Enc_87c142 : OpcodeHexagon {
1925  bits <7> Ii;
1926  let Inst{8-4} = Ii{6-2};
1927  bits <4> Rt16;
1928  let Inst{3-0} = Rt16{3-0};
1929}
1930class Enc_88c16c : OpcodeHexagon {
1931  bits <5> Rss32;
1932  let Inst{20-16} = Rss32{4-0};
1933  bits <5> Rtt32;
1934  let Inst{12-8} = Rtt32{4-0};
1935  bits <5> Rxx32;
1936  let Inst{4-0} = Rxx32{4-0};
1937}
1938class Enc_88d4d9 : OpcodeHexagon {
1939  bits <2> Pu4;
1940  let Inst{9-8} = Pu4{1-0};
1941  bits <5> Rs32;
1942  let Inst{20-16} = Rs32{4-0};
1943}
1944class Enc_890909 : OpcodeHexagon {
1945  bits <5> Rs32;
1946  let Inst{20-16} = Rs32{4-0};
1947  bits <5> Rd32;
1948  let Inst{4-0} = Rd32{4-0};
1949  bits <2> Pe4;
1950  let Inst{6-5} = Pe4{1-0};
1951}
1952class Enc_895bd9 : OpcodeHexagon {
1953  bits <2> Qu4;
1954  let Inst{9-8} = Qu4{1-0};
1955  bits <5> Rt32;
1956  let Inst{20-16} = Rt32{4-0};
1957  bits <5> Vx32;
1958  let Inst{4-0} = Vx32{4-0};
1959}
1960class Enc_8b8927 : OpcodeHexagon {
1961  bits <5> Rt32;
1962  let Inst{20-16} = Rt32{4-0};
1963  bits <1> Mu2;
1964  let Inst{13-13} = Mu2{0-0};
1965  bits <5> Vv32;
1966  let Inst{4-0} = Vv32{4-0};
1967}
1968class Enc_8b8d61 : OpcodeHexagon {
1969  bits <6> Ii;
1970  let Inst{22-21} = Ii{5-4};
1971  let Inst{13-13} = Ii{3-3};
1972  let Inst{7-5} = Ii{2-0};
1973  bits <5> Rs32;
1974  let Inst{20-16} = Rs32{4-0};
1975  bits <5> Ru32;
1976  let Inst{4-0} = Ru32{4-0};
1977  bits <5> Rd32;
1978  let Inst{12-8} = Rd32{4-0};
1979}
1980class Enc_8bcba4 : OpcodeHexagon {
1981  bits <6> II;
1982  let Inst{5-0} = II{5-0};
1983  bits <5> Rt32;
1984  let Inst{12-8} = Rt32{4-0};
1985  bits <5> Re32;
1986  let Inst{20-16} = Re32{4-0};
1987}
1988class Enc_8c2412 : OpcodeHexagon {
1989  bits <2> Ps4;
1990  let Inst{6-5} = Ps4{1-0};
1991  bits <5> Vu32;
1992  let Inst{12-8} = Vu32{4-0};
1993  bits <5> Vv32;
1994  let Inst{20-16} = Vv32{4-0};
1995  bits <5> Vdd32;
1996  let Inst{4-0} = Vdd32{4-0};
1997}
1998class Enc_8c6530 : OpcodeHexagon {
1999  bits <5> Rtt32;
2000  let Inst{12-8} = Rtt32{4-0};
2001  bits <5> Rss32;
2002  let Inst{20-16} = Rss32{4-0};
2003  bits <2> Pu4;
2004  let Inst{6-5} = Pu4{1-0};
2005  bits <5> Rdd32;
2006  let Inst{4-0} = Rdd32{4-0};
2007}
2008class Enc_8d8a30 : OpcodeHexagon {
2009  bits <4> Ii;
2010  let Inst{13-13} = Ii{3-3};
2011  let Inst{10-8} = Ii{2-0};
2012  bits <2> Pv4;
2013  let Inst{12-11} = Pv4{1-0};
2014  bits <5> Rt32;
2015  let Inst{20-16} = Rt32{4-0};
2016  bits <5> Vd32;
2017  let Inst{4-0} = Vd32{4-0};
2018}
2019class Enc_8dbdfe : OpcodeHexagon {
2020  bits <8> Ii;
2021  let Inst{13-13} = Ii{7-7};
2022  let Inst{7-3} = Ii{6-2};
2023  bits <2> Pv4;
2024  let Inst{1-0} = Pv4{1-0};
2025  bits <5> Rs32;
2026  let Inst{20-16} = Rs32{4-0};
2027  bits <3> Nt8;
2028  let Inst{10-8} = Nt8{2-0};
2029}
2030class Enc_8dbe85 : OpcodeHexagon {
2031  bits <1> Mu2;
2032  let Inst{13-13} = Mu2{0-0};
2033  bits <3> Nt8;
2034  let Inst{10-8} = Nt8{2-0};
2035  bits <5> Rx32;
2036  let Inst{20-16} = Rx32{4-0};
2037}
2038class Enc_8dec2e : OpcodeHexagon {
2039  bits <5> Ii;
2040  let Inst{12-8} = Ii{4-0};
2041  bits <5> Rss32;
2042  let Inst{20-16} = Rss32{4-0};
2043  bits <5> Rd32;
2044  let Inst{4-0} = Rd32{4-0};
2045}
2046class Enc_8df4be : OpcodeHexagon {
2047  bits <17> Ii;
2048  let Inst{26-25} = Ii{16-15};
2049  let Inst{20-16} = Ii{14-10};
2050  let Inst{13-5} = Ii{9-1};
2051  bits <5> Rd32;
2052  let Inst{4-0} = Rd32{4-0};
2053}
2054class Enc_8e583a : OpcodeHexagon {
2055  bits <11> Ii;
2056  let Inst{21-20} = Ii{10-9};
2057  let Inst{7-1} = Ii{8-2};
2058  bits <4> Rs16;
2059  let Inst{19-16} = Rs16{3-0};
2060  bits <5> n1;
2061  let Inst{28-28} = n1{4-4};
2062  let Inst{25-23} = n1{3-1};
2063  let Inst{13-13} = n1{0-0};
2064}
2065class Enc_8f7633 : OpcodeHexagon {
2066  bits <5> Rs32;
2067  let Inst{20-16} = Rs32{4-0};
2068  bits <7> Sd128;
2069  let Inst{6-0} = Sd128{6-0};
2070}
2071class Enc_90cd8b : OpcodeHexagon {
2072  bits <5> Rss32;
2073  let Inst{20-16} = Rss32{4-0};
2074  bits <5> Rd32;
2075  let Inst{4-0} = Rd32{4-0};
2076}
2077class Enc_91b9fe : OpcodeHexagon {
2078  bits <5> Ii;
2079  let Inst{6-3} = Ii{4-1};
2080  bits <1> Mu2;
2081  let Inst{13-13} = Mu2{0-0};
2082  bits <3> Nt8;
2083  let Inst{10-8} = Nt8{2-0};
2084  bits <5> Rx32;
2085  let Inst{20-16} = Rx32{4-0};
2086}
2087class Enc_927852 : OpcodeHexagon {
2088  bits <5> Rss32;
2089  let Inst{20-16} = Rss32{4-0};
2090  bits <5> Rt32;
2091  let Inst{12-8} = Rt32{4-0};
2092  bits <5> Rdd32;
2093  let Inst{4-0} = Rdd32{4-0};
2094}
2095class Enc_928ca1 : OpcodeHexagon {
2096  bits <1> Mu2;
2097  let Inst{13-13} = Mu2{0-0};
2098  bits <5> Rtt32;
2099  let Inst{12-8} = Rtt32{4-0};
2100  bits <5> Rx32;
2101  let Inst{20-16} = Rx32{4-0};
2102}
2103class Enc_935d9b : OpcodeHexagon {
2104  bits <5> Ii;
2105  let Inst{6-3} = Ii{4-1};
2106  bits <1> Mu2;
2107  let Inst{13-13} = Mu2{0-0};
2108  bits <5> Rt32;
2109  let Inst{12-8} = Rt32{4-0};
2110  bits <5> Rx32;
2111  let Inst{20-16} = Rx32{4-0};
2112}
2113class Enc_93af4c : OpcodeHexagon {
2114  bits <7> Ii;
2115  let Inst{10-4} = Ii{6-0};
2116  bits <4> Rx16;
2117  let Inst{3-0} = Rx16{3-0};
2118}
2119class Enc_95441f : OpcodeHexagon {
2120  bits <5> Vu32;
2121  let Inst{12-8} = Vu32{4-0};
2122  bits <5> Vv32;
2123  let Inst{20-16} = Vv32{4-0};
2124  bits <2> Qd4;
2125  let Inst{1-0} = Qd4{1-0};
2126}
2127class Enc_96ce4f : OpcodeHexagon {
2128  bits <4> Ii;
2129  let Inst{6-3} = Ii{3-0};
2130  bits <1> Mu2;
2131  let Inst{13-13} = Mu2{0-0};
2132  bits <3> Nt8;
2133  let Inst{10-8} = Nt8{2-0};
2134  bits <5> Rx32;
2135  let Inst{20-16} = Rx32{4-0};
2136}
2137class Enc_97d666 : OpcodeHexagon {
2138  bits <4> Rs16;
2139  let Inst{7-4} = Rs16{3-0};
2140  bits <4> Rd16;
2141  let Inst{3-0} = Rd16{3-0};
2142}
2143class Enc_989021 : OpcodeHexagon {
2144  bits <5> Rt32;
2145  let Inst{20-16} = Rt32{4-0};
2146  bits <5> Vy32;
2147  let Inst{12-8} = Vy32{4-0};
2148  bits <5> Vx32;
2149  let Inst{4-0} = Vx32{4-0};
2150}
2151class Enc_98c0b8 : OpcodeHexagon {
2152  bits <2> Ii;
2153  let Inst{13-13} = Ii{1-1};
2154  let Inst{7-7} = Ii{0-0};
2155  bits <2> Pv4;
2156  let Inst{6-5} = Pv4{1-0};
2157  bits <5> Rs32;
2158  let Inst{20-16} = Rs32{4-0};
2159  bits <5> Rt32;
2160  let Inst{12-8} = Rt32{4-0};
2161  bits <5> Rdd32;
2162  let Inst{4-0} = Rdd32{4-0};
2163}
2164class Enc_9a33d5 : OpcodeHexagon {
2165  bits <7> Ii;
2166  let Inst{6-3} = Ii{6-3};
2167  bits <2> Pv4;
2168  let Inst{1-0} = Pv4{1-0};
2169  bits <5> Rtt32;
2170  let Inst{12-8} = Rtt32{4-0};
2171  bits <5> Rx32;
2172  let Inst{20-16} = Rx32{4-0};
2173}
2174class Enc_9ac432 : OpcodeHexagon {
2175  bits <2> Ps4;
2176  let Inst{17-16} = Ps4{1-0};
2177  bits <2> Pt4;
2178  let Inst{9-8} = Pt4{1-0};
2179  bits <2> Pu4;
2180  let Inst{7-6} = Pu4{1-0};
2181  bits <2> Pd4;
2182  let Inst{1-0} = Pd4{1-0};
2183}
2184class Enc_9b0bc1 : OpcodeHexagon {
2185  bits <2> Pu4;
2186  let Inst{6-5} = Pu4{1-0};
2187  bits <5> Rt32;
2188  let Inst{12-8} = Rt32{4-0};
2189  bits <5> Rs32;
2190  let Inst{20-16} = Rs32{4-0};
2191  bits <5> Rd32;
2192  let Inst{4-0} = Rd32{4-0};
2193}
2194class Enc_9be1de : OpcodeHexagon {
2195  bits <2> Qs4;
2196  let Inst{6-5} = Qs4{1-0};
2197  bits <5> Rt32;
2198  let Inst{20-16} = Rt32{4-0};
2199  bits <1> Mu2;
2200  let Inst{13-13} = Mu2{0-0};
2201  bits <5> Vv32;
2202  let Inst{12-8} = Vv32{4-0};
2203  bits <5> Vw32;
2204  let Inst{4-0} = Vw32{4-0};
2205}
2206class Enc_9cdba7 : OpcodeHexagon {
2207  bits <8> Ii;
2208  let Inst{12-5} = Ii{7-0};
2209  bits <5> Rs32;
2210  let Inst{20-16} = Rs32{4-0};
2211  bits <5> Rdd32;
2212  let Inst{4-0} = Rdd32{4-0};
2213}
2214class Enc_9d1247 : OpcodeHexagon {
2215  bits <7> Ii;
2216  let Inst{8-5} = Ii{6-3};
2217  bits <2> Pt4;
2218  let Inst{10-9} = Pt4{1-0};
2219  bits <5> Rdd32;
2220  let Inst{4-0} = Rdd32{4-0};
2221  bits <5> Rx32;
2222  let Inst{20-16} = Rx32{4-0};
2223}
2224class Enc_9e2e1c : OpcodeHexagon {
2225  bits <5> Ii;
2226  let Inst{8-5} = Ii{4-1};
2227  bits <1> Mu2;
2228  let Inst{13-13} = Mu2{0-0};
2229  bits <5> Ryy32;
2230  let Inst{4-0} = Ryy32{4-0};
2231  bits <5> Rx32;
2232  let Inst{20-16} = Rx32{4-0};
2233}
2234class Enc_9e4c3f : OpcodeHexagon {
2235  bits <6> II;
2236  let Inst{13-8} = II{5-0};
2237  bits <11> Ii;
2238  let Inst{21-20} = Ii{10-9};
2239  let Inst{7-1} = Ii{8-2};
2240  bits <4> Rd16;
2241  let Inst{19-16} = Rd16{3-0};
2242}
2243class Enc_9ea4cf : OpcodeHexagon {
2244  bits <2> Ii;
2245  let Inst{13-13} = Ii{1-1};
2246  let Inst{6-6} = Ii{0-0};
2247  bits <6> II;
2248  let Inst{5-0} = II{5-0};
2249  bits <5> Ru32;
2250  let Inst{20-16} = Ru32{4-0};
2251  bits <5> Rt32;
2252  let Inst{12-8} = Rt32{4-0};
2253}
2254class Enc_9fae8a : OpcodeHexagon {
2255  bits <6> Ii;
2256  let Inst{13-8} = Ii{5-0};
2257  bits <5> Rs32;
2258  let Inst{20-16} = Rs32{4-0};
2259  bits <5> Rd32;
2260  let Inst{4-0} = Rd32{4-0};
2261}
2262class Enc_a05677 : OpcodeHexagon {
2263  bits <5> Ii;
2264  let Inst{12-8} = Ii{4-0};
2265  bits <5> Rs32;
2266  let Inst{20-16} = Rs32{4-0};
2267  bits <5> Rd32;
2268  let Inst{4-0} = Rd32{4-0};
2269}
2270class Enc_a1640c : OpcodeHexagon {
2271  bits <6> Ii;
2272  let Inst{13-8} = Ii{5-0};
2273  bits <5> Rss32;
2274  let Inst{20-16} = Rss32{4-0};
2275  bits <5> Rd32;
2276  let Inst{4-0} = Rd32{4-0};
2277}
2278class Enc_a198f6 : OpcodeHexagon {
2279  bits <7> Ii;
2280  let Inst{10-5} = Ii{6-1};
2281  bits <2> Pt4;
2282  let Inst{12-11} = Pt4{1-0};
2283  bits <5> Rs32;
2284  let Inst{20-16} = Rs32{4-0};
2285  bits <5> Rd32;
2286  let Inst{4-0} = Rd32{4-0};
2287}
2288class Enc_a1e29d : OpcodeHexagon {
2289  bits <5> Ii;
2290  let Inst{12-8} = Ii{4-0};
2291  bits <5> II;
2292  let Inst{22-21} = II{4-3};
2293  let Inst{7-5} = II{2-0};
2294  bits <5> Rs32;
2295  let Inst{20-16} = Rs32{4-0};
2296  bits <5> Rx32;
2297  let Inst{4-0} = Rx32{4-0};
2298}
2299class Enc_a21d47 : OpcodeHexagon {
2300  bits <6> Ii;
2301  let Inst{10-5} = Ii{5-0};
2302  bits <2> Pt4;
2303  let Inst{12-11} = Pt4{1-0};
2304  bits <5> Rs32;
2305  let Inst{20-16} = Rs32{4-0};
2306  bits <5> Rd32;
2307  let Inst{4-0} = Rd32{4-0};
2308}
2309class Enc_a255dc : OpcodeHexagon {
2310  bits <3> Ii;
2311  let Inst{10-8} = Ii{2-0};
2312  bits <5> Vd32;
2313  let Inst{4-0} = Vd32{4-0};
2314  bits <5> Rx32;
2315  let Inst{20-16} = Rx32{4-0};
2316}
2317class Enc_a27588 : OpcodeHexagon {
2318  bits <11> Ii;
2319  let Inst{26-25} = Ii{10-9};
2320  let Inst{13-5} = Ii{8-0};
2321  bits <5> Rs32;
2322  let Inst{20-16} = Rs32{4-0};
2323  bits <5> Ryy32;
2324  let Inst{4-0} = Ryy32{4-0};
2325}
2326class Enc_a30110 : OpcodeHexagon {
2327  bits <5> Vu32;
2328  let Inst{12-8} = Vu32{4-0};
2329  bits <5> Vv32;
2330  let Inst{23-19} = Vv32{4-0};
2331  bits <3> Rt8;
2332  let Inst{18-16} = Rt8{2-0};
2333  bits <5> Vd32;
2334  let Inst{4-0} = Vd32{4-0};
2335}
2336class Enc_a33d04 : OpcodeHexagon {
2337  bits <5> Vuu32;
2338  let Inst{12-8} = Vuu32{4-0};
2339  bits <5> Vd32;
2340  let Inst{4-0} = Vd32{4-0};
2341}
2342class Enc_a42857 : OpcodeHexagon {
2343  bits <11> Ii;
2344  let Inst{21-20} = Ii{10-9};
2345  let Inst{7-1} = Ii{8-2};
2346  bits <4> Rs16;
2347  let Inst{19-16} = Rs16{3-0};
2348  bits <5> n1;
2349  let Inst{28-28} = n1{4-4};
2350  let Inst{24-22} = n1{3-1};
2351  let Inst{8-8} = n1{0-0};
2352}
2353class Enc_a4ef14 : OpcodeHexagon {
2354  bits <5> Rd32;
2355  let Inst{4-0} = Rd32{4-0};
2356}
2357class Enc_a51a9a : OpcodeHexagon {
2358  bits <8> Ii;
2359  let Inst{12-8} = Ii{7-3};
2360  let Inst{4-2} = Ii{2-0};
2361}
2362class Enc_a56825 : OpcodeHexagon {
2363  bits <5> Rss32;
2364  let Inst{20-16} = Rss32{4-0};
2365  bits <5> Rtt32;
2366  let Inst{12-8} = Rtt32{4-0};
2367  bits <5> Rdd32;
2368  let Inst{4-0} = Rdd32{4-0};
2369}
2370class Enc_a568d4 : OpcodeHexagon {
2371  bits <5> Rt32;
2372  let Inst{12-8} = Rt32{4-0};
2373  bits <5> Rs32;
2374  let Inst{20-16} = Rs32{4-0};
2375  bits <5> Rx32;
2376  let Inst{4-0} = Rx32{4-0};
2377}
2378class Enc_a5ed8a : OpcodeHexagon {
2379  bits <5> Rt32;
2380  let Inst{20-16} = Rt32{4-0};
2381  bits <5> Vd32;
2382  let Inst{4-0} = Vd32{4-0};
2383}
2384class Enc_a641d0 : OpcodeHexagon {
2385  bits <5> Rt32;
2386  let Inst{20-16} = Rt32{4-0};
2387  bits <1> Mu2;
2388  let Inst{13-13} = Mu2{0-0};
2389  bits <5> Vvv32;
2390  let Inst{12-8} = Vvv32{4-0};
2391  bits <5> Vw32;
2392  let Inst{4-0} = Vw32{4-0};
2393}
2394class Enc_a6853f : OpcodeHexagon {
2395  bits <11> Ii;
2396  let Inst{21-20} = Ii{10-9};
2397  let Inst{7-1} = Ii{8-2};
2398  bits <3> Ns8;
2399  let Inst{18-16} = Ns8{2-0};
2400  bits <6> n1;
2401  let Inst{29-29} = n1{5-5};
2402  let Inst{26-25} = n1{4-3};
2403  let Inst{23-22} = n1{2-1};
2404  let Inst{13-13} = n1{0-0};
2405}
2406class Enc_a6ce9c : OpcodeHexagon {
2407  bits <6> Ii;
2408  let Inst{3-0} = Ii{5-2};
2409  bits <4> Rs16;
2410  let Inst{7-4} = Rs16{3-0};
2411}
2412class Enc_a705fc : OpcodeHexagon {
2413  bits <5> Rss32;
2414  let Inst{20-16} = Rss32{4-0};
2415  bits <7> Sdd128;
2416  let Inst{6-0} = Sdd128{6-0};
2417}
2418class Enc_a7341a : OpcodeHexagon {
2419  bits <5> Vu32;
2420  let Inst{12-8} = Vu32{4-0};
2421  bits <5> Vv32;
2422  let Inst{20-16} = Vv32{4-0};
2423  bits <5> Vx32;
2424  let Inst{4-0} = Vx32{4-0};
2425}
2426class Enc_a75aa6 : OpcodeHexagon {
2427  bits <5> Rs32;
2428  let Inst{20-16} = Rs32{4-0};
2429  bits <5> Rt32;
2430  let Inst{12-8} = Rt32{4-0};
2431  bits <1> Mu2;
2432  let Inst{13-13} = Mu2{0-0};
2433}
2434class Enc_a7b8e8 : OpcodeHexagon {
2435  bits <6> Ii;
2436  let Inst{22-21} = Ii{5-4};
2437  let Inst{13-13} = Ii{3-3};
2438  let Inst{7-5} = Ii{2-0};
2439  bits <5> Rs32;
2440  let Inst{20-16} = Rs32{4-0};
2441  bits <5> Rt32;
2442  let Inst{12-8} = Rt32{4-0};
2443  bits <5> Rd32;
2444  let Inst{4-0} = Rd32{4-0};
2445}
2446class Enc_a803e0 : OpcodeHexagon {
2447  bits <7> Ii;
2448  let Inst{12-7} = Ii{6-1};
2449  bits <8> II;
2450  let Inst{13-13} = II{7-7};
2451  let Inst{6-0} = II{6-0};
2452  bits <5> Rs32;
2453  let Inst{20-16} = Rs32{4-0};
2454}
2455class Enc_a90628 : OpcodeHexagon {
2456  bits <2> Qv4;
2457  let Inst{23-22} = Qv4{1-0};
2458  bits <5> Vu32;
2459  let Inst{12-8} = Vu32{4-0};
2460  bits <5> Vx32;
2461  let Inst{4-0} = Vx32{4-0};
2462}
2463class Enc_a94f3b : OpcodeHexagon {
2464  bits <5> Rs32;
2465  let Inst{20-16} = Rs32{4-0};
2466  bits <5> Rt32;
2467  let Inst{12-8} = Rt32{4-0};
2468  bits <5> Rd32;
2469  let Inst{4-0} = Rd32{4-0};
2470  bits <2> Pe4;
2471  let Inst{6-5} = Pe4{1-0};
2472}
2473class Enc_aad80c : OpcodeHexagon {
2474  bits <5> Vuu32;
2475  let Inst{12-8} = Vuu32{4-0};
2476  bits <5> Rt32;
2477  let Inst{20-16} = Rt32{4-0};
2478  bits <5> Vdd32;
2479  let Inst{4-0} = Vdd32{4-0};
2480}
2481class Enc_acd6ed : OpcodeHexagon {
2482  bits <9> Ii;
2483  let Inst{10-5} = Ii{8-3};
2484  bits <2> Pt4;
2485  let Inst{12-11} = Pt4{1-0};
2486  bits <5> Rs32;
2487  let Inst{20-16} = Rs32{4-0};
2488  bits <5> Rdd32;
2489  let Inst{4-0} = Rdd32{4-0};
2490}
2491class Enc_ad1831 : OpcodeHexagon {
2492  bits <16> Ii;
2493  let Inst{26-25} = Ii{15-14};
2494  let Inst{20-16} = Ii{13-9};
2495  let Inst{13-13} = Ii{8-8};
2496  let Inst{7-0} = Ii{7-0};
2497  bits <3> Nt8;
2498  let Inst{10-8} = Nt8{2-0};
2499}
2500class Enc_ad1c74 : OpcodeHexagon {
2501  bits <11> Ii;
2502  let Inst{21-20} = Ii{10-9};
2503  let Inst{7-1} = Ii{8-2};
2504  bits <4> Rs16;
2505  let Inst{19-16} = Rs16{3-0};
2506}
2507class Enc_ad9bef : OpcodeHexagon {
2508  bits <5> Vu32;
2509  let Inst{12-8} = Vu32{4-0};
2510  bits <5> Rtt32;
2511  let Inst{20-16} = Rtt32{4-0};
2512  bits <5> Vxx32;
2513  let Inst{4-0} = Vxx32{4-0};
2514}
2515class Enc_adf111 : OpcodeHexagon {
2516  bits <5> Vu32;
2517  let Inst{12-8} = Vu32{4-0};
2518  bits <5> Rt32;
2519  let Inst{20-16} = Rt32{4-0};
2520  bits <2> Qx4;
2521  let Inst{1-0} = Qx4{1-0};
2522}
2523class Enc_b00112 : OpcodeHexagon {
2524  bits <5> Rss32;
2525  let Inst{20-16} = Rss32{4-0};
2526  bits <5> Rtt32;
2527  let Inst{12-8} = Rtt32{4-0};
2528}
2529class Enc_b025d6 : OpcodeHexagon {
2530  bits <3> Ii;
2531  let Inst{10-8} = Ii{2-0};
2532  bits <5> Vss32;
2533  let Inst{4-0} = Vss32{4-0};
2534  bits <5> Rx32;
2535  let Inst{20-16} = Rx32{4-0};
2536}
2537class Enc_b05839 : OpcodeHexagon {
2538  bits <7> Ii;
2539  let Inst{8-5} = Ii{6-3};
2540  bits <1> Mu2;
2541  let Inst{13-13} = Mu2{0-0};
2542  bits <5> Rdd32;
2543  let Inst{4-0} = Rdd32{4-0};
2544  bits <5> Rx32;
2545  let Inst{20-16} = Rx32{4-0};
2546}
2547class Enc_b087ac : OpcodeHexagon {
2548  bits <5> Vu32;
2549  let Inst{12-8} = Vu32{4-0};
2550  bits <5> Rt32;
2551  let Inst{20-16} = Rt32{4-0};
2552  bits <5> Vd32;
2553  let Inst{4-0} = Vd32{4-0};
2554}
2555class Enc_b0e9d8 : OpcodeHexagon {
2556  bits <10> Ii;
2557  let Inst{21-21} = Ii{9-9};
2558  let Inst{13-5} = Ii{8-0};
2559  bits <5> Rs32;
2560  let Inst{20-16} = Rs32{4-0};
2561  bits <5> Rx32;
2562  let Inst{4-0} = Rx32{4-0};
2563}
2564class Enc_b15941 : OpcodeHexagon {
2565  bits <4> Ii;
2566  let Inst{6-3} = Ii{3-0};
2567  bits <1> Mu2;
2568  let Inst{13-13} = Mu2{0-0};
2569  bits <5> Rt32;
2570  let Inst{12-8} = Rt32{4-0};
2571  bits <5> Rx32;
2572  let Inst{20-16} = Rx32{4-0};
2573}
2574class Enc_b1e1fb : OpcodeHexagon {
2575  bits <11> Ii;
2576  let Inst{21-20} = Ii{10-9};
2577  let Inst{7-1} = Ii{8-2};
2578  bits <4> Rs16;
2579  let Inst{19-16} = Rs16{3-0};
2580  bits <5> n1;
2581  let Inst{28-28} = n1{4-4};
2582  let Inst{25-23} = n1{3-1};
2583  let Inst{8-8} = n1{0-0};
2584}
2585class Enc_b388cf : OpcodeHexagon {
2586  bits <5> Ii;
2587  let Inst{12-8} = Ii{4-0};
2588  bits <5> II;
2589  let Inst{22-21} = II{4-3};
2590  let Inst{7-5} = II{2-0};
2591  bits <5> Rs32;
2592  let Inst{20-16} = Rs32{4-0};
2593  bits <5> Rd32;
2594  let Inst{4-0} = Rd32{4-0};
2595}
2596class Enc_b38ffc : OpcodeHexagon {
2597  bits <4> Ii;
2598  let Inst{11-8} = Ii{3-0};
2599  bits <4> Rs16;
2600  let Inst{7-4} = Rs16{3-0};
2601  bits <4> Rt16;
2602  let Inst{3-0} = Rt16{3-0};
2603}
2604class Enc_b43b67 : OpcodeHexagon {
2605  bits <5> Vu32;
2606  let Inst{12-8} = Vu32{4-0};
2607  bits <5> Vv32;
2608  let Inst{20-16} = Vv32{4-0};
2609  bits <5> Vd32;
2610  let Inst{4-0} = Vd32{4-0};
2611  bits <2> Qx4;
2612  let Inst{6-5} = Qx4{1-0};
2613}
2614class Enc_b4e6cf : OpcodeHexagon {
2615  bits <10> Ii;
2616  let Inst{21-21} = Ii{9-9};
2617  let Inst{13-5} = Ii{8-0};
2618  bits <5> Ru32;
2619  let Inst{4-0} = Ru32{4-0};
2620  bits <5> Rx32;
2621  let Inst{20-16} = Rx32{4-0};
2622}
2623class Enc_b62ef7 : OpcodeHexagon {
2624  bits <3> Ii;
2625  let Inst{10-8} = Ii{2-0};
2626  bits <5> Vs32;
2627  let Inst{4-0} = Vs32{4-0};
2628  bits <5> Rx32;
2629  let Inst{20-16} = Rx32{4-0};
2630}
2631class Enc_b72622 : OpcodeHexagon {
2632  bits <2> Ii;
2633  let Inst{13-13} = Ii{1-1};
2634  let Inst{5-5} = Ii{0-0};
2635  bits <5> Rss32;
2636  let Inst{20-16} = Rss32{4-0};
2637  bits <5> Rt32;
2638  let Inst{12-8} = Rt32{4-0};
2639  bits <5> Rxx32;
2640  let Inst{4-0} = Rxx32{4-0};
2641}
2642class Enc_b78edd : OpcodeHexagon {
2643  bits <11> Ii;
2644  let Inst{21-20} = Ii{10-9};
2645  let Inst{7-1} = Ii{8-2};
2646  bits <4> Rs16;
2647  let Inst{19-16} = Rs16{3-0};
2648  bits <4> n1;
2649  let Inst{28-28} = n1{3-3};
2650  let Inst{24-23} = n1{2-1};
2651  let Inst{8-8} = n1{0-0};
2652}
2653class Enc_b7fad3 : OpcodeHexagon {
2654  bits <2> Pv4;
2655  let Inst{9-8} = Pv4{1-0};
2656  bits <5> Rs32;
2657  let Inst{20-16} = Rs32{4-0};
2658  bits <5> Rdd32;
2659  let Inst{4-0} = Rdd32{4-0};
2660}
2661class Enc_b8309d : OpcodeHexagon {
2662  bits <9> Ii;
2663  let Inst{8-3} = Ii{8-3};
2664  bits <3> Rtt8;
2665  let Inst{2-0} = Rtt8{2-0};
2666}
2667class Enc_b84c4c : OpcodeHexagon {
2668  bits <6> Ii;
2669  let Inst{13-8} = Ii{5-0};
2670  bits <6> II;
2671  let Inst{23-21} = II{5-3};
2672  let Inst{7-5} = II{2-0};
2673  bits <5> Rss32;
2674  let Inst{20-16} = Rss32{4-0};
2675  bits <5> Rdd32;
2676  let Inst{4-0} = Rdd32{4-0};
2677}
2678class Enc_b886fd : OpcodeHexagon {
2679  bits <5> Ii;
2680  let Inst{6-3} = Ii{4-1};
2681  bits <2> Pv4;
2682  let Inst{1-0} = Pv4{1-0};
2683  bits <5> Rt32;
2684  let Inst{12-8} = Rt32{4-0};
2685  bits <5> Rx32;
2686  let Inst{20-16} = Rx32{4-0};
2687}
2688class Enc_b8c967 : OpcodeHexagon {
2689  bits <8> Ii;
2690  let Inst{12-5} = Ii{7-0};
2691  bits <5> Rs32;
2692  let Inst{20-16} = Rs32{4-0};
2693  bits <5> Rd32;
2694  let Inst{4-0} = Rd32{4-0};
2695}
2696class Enc_b909d2 : OpcodeHexagon {
2697  bits <11> Ii;
2698  let Inst{21-20} = Ii{10-9};
2699  let Inst{7-1} = Ii{8-2};
2700  bits <4> Rs16;
2701  let Inst{19-16} = Rs16{3-0};
2702  bits <7> n1;
2703  let Inst{28-28} = n1{6-6};
2704  let Inst{25-22} = n1{5-2};
2705  let Inst{13-13} = n1{1-1};
2706  let Inst{8-8} = n1{0-0};
2707}
2708class Enc_b91167 : OpcodeHexagon {
2709  bits <2> Ii;
2710  let Inst{6-5} = Ii{1-0};
2711  bits <5> Vuu32;
2712  let Inst{12-8} = Vuu32{4-0};
2713  bits <5> Vvv32;
2714  let Inst{20-16} = Vvv32{4-0};
2715  bits <5> Vdd32;
2716  let Inst{4-0} = Vdd32{4-0};
2717}
2718class Enc_b97f71 : OpcodeHexagon {
2719  bits <6> Ii;
2720  let Inst{8-5} = Ii{5-2};
2721  bits <2> Pt4;
2722  let Inst{10-9} = Pt4{1-0};
2723  bits <5> Rd32;
2724  let Inst{4-0} = Rd32{4-0};
2725  bits <5> Rx32;
2726  let Inst{20-16} = Rx32{4-0};
2727}
2728class Enc_b98b95 : OpcodeHexagon {
2729  bits <4> Ii;
2730  let Inst{13-13} = Ii{3-3};
2731  let Inst{10-8} = Ii{2-0};
2732  bits <5> Rt32;
2733  let Inst{20-16} = Rt32{4-0};
2734  bits <5> Vss32;
2735  let Inst{4-0} = Vss32{4-0};
2736}
2737class Enc_b9c5fb : OpcodeHexagon {
2738  bits <5> Rss32;
2739  let Inst{20-16} = Rss32{4-0};
2740  bits <5> Rdd32;
2741  let Inst{4-0} = Rdd32{4-0};
2742}
2743class Enc_bc03e5 : OpcodeHexagon {
2744  bits <17> Ii;
2745  let Inst{26-25} = Ii{16-15};
2746  let Inst{20-16} = Ii{14-10};
2747  let Inst{13-13} = Ii{9-9};
2748  let Inst{7-0} = Ii{8-1};
2749  bits <3> Nt8;
2750  let Inst{10-8} = Nt8{2-0};
2751}
2752class Enc_bd0b33 : OpcodeHexagon {
2753  bits <10> Ii;
2754  let Inst{21-21} = Ii{9-9};
2755  let Inst{13-5} = Ii{8-0};
2756  bits <5> Rs32;
2757  let Inst{20-16} = Rs32{4-0};
2758  bits <2> Pd4;
2759  let Inst{1-0} = Pd4{1-0};
2760}
2761class Enc_bd1cbc : OpcodeHexagon {
2762  bits <5> Ii;
2763  let Inst{8-5} = Ii{4-1};
2764  bits <5> Ryy32;
2765  let Inst{4-0} = Ryy32{4-0};
2766  bits <5> Rx32;
2767  let Inst{20-16} = Rx32{4-0};
2768}
2769class Enc_bd6011 : OpcodeHexagon {
2770  bits <5> Rt32;
2771  let Inst{12-8} = Rt32{4-0};
2772  bits <5> Rs32;
2773  let Inst{20-16} = Rs32{4-0};
2774  bits <5> Rd32;
2775  let Inst{4-0} = Rd32{4-0};
2776}
2777class Enc_bd811a : OpcodeHexagon {
2778  bits <5> Rs32;
2779  let Inst{20-16} = Rs32{4-0};
2780  bits <5> Cd32;
2781  let Inst{4-0} = Cd32{4-0};
2782}
2783class Enc_bddee3 : OpcodeHexagon {
2784  bits <5> Vu32;
2785  let Inst{12-8} = Vu32{4-0};
2786  bits <5> Vyyyy32;
2787  let Inst{4-0} = Vyyyy32{4-0};
2788  bits <3> Rx8;
2789  let Inst{18-16} = Rx8{2-0};
2790}
2791class Enc_be32a5 : OpcodeHexagon {
2792  bits <5> Rs32;
2793  let Inst{20-16} = Rs32{4-0};
2794  bits <5> Rt32;
2795  let Inst{12-8} = Rt32{4-0};
2796  bits <5> Rdd32;
2797  let Inst{4-0} = Rdd32{4-0};
2798}
2799class Enc_bea5da : OpcodeHexagon {
2800  bits <10> Ii;
2801  let Inst{17-16} = Ii{9-8};
2802  let Inst{12-8} = Ii{7-3};
2803  let Inst{4-2} = Ii{2-0};
2804}
2805class Enc_bfbf03 : OpcodeHexagon {
2806  bits <2> Qs4;
2807  let Inst{9-8} = Qs4{1-0};
2808  bits <2> Qd4;
2809  let Inst{1-0} = Qd4{1-0};
2810}
2811class Enc_c0cdde : OpcodeHexagon {
2812  bits <9> Ii;
2813  let Inst{13-5} = Ii{8-0};
2814  bits <5> Rs32;
2815  let Inst{20-16} = Rs32{4-0};
2816  bits <2> Pd4;
2817  let Inst{1-0} = Pd4{1-0};
2818}
2819class Enc_c175d0 : OpcodeHexagon {
2820  bits <4> Ii;
2821  let Inst{11-8} = Ii{3-0};
2822  bits <4> Rs16;
2823  let Inst{7-4} = Rs16{3-0};
2824  bits <4> Rd16;
2825  let Inst{3-0} = Rd16{3-0};
2826}
2827class Enc_c1d806 : OpcodeHexagon {
2828  bits <5> Vu32;
2829  let Inst{12-8} = Vu32{4-0};
2830  bits <5> Vv32;
2831  let Inst{20-16} = Vv32{4-0};
2832  bits <5> Vd32;
2833  let Inst{4-0} = Vd32{4-0};
2834  bits <2> Qe4;
2835  let Inst{6-5} = Qe4{1-0};
2836}
2837class Enc_c2b48e : OpcodeHexagon {
2838  bits <5> Rs32;
2839  let Inst{20-16} = Rs32{4-0};
2840  bits <5> Rt32;
2841  let Inst{12-8} = Rt32{4-0};
2842  bits <2> Pd4;
2843  let Inst{1-0} = Pd4{1-0};
2844}
2845class Enc_c31910 : OpcodeHexagon {
2846  bits <8> Ii;
2847  let Inst{23-21} = Ii{7-5};
2848  let Inst{13-13} = Ii{4-4};
2849  let Inst{7-5} = Ii{3-1};
2850  let Inst{3-3} = Ii{0-0};
2851  bits <5> II;
2852  let Inst{12-8} = II{4-0};
2853  bits <5> Rx32;
2854  let Inst{20-16} = Rx32{4-0};
2855}
2856class Enc_c4dc92 : OpcodeHexagon {
2857  bits <2> Qv4;
2858  let Inst{23-22} = Qv4{1-0};
2859  bits <5> Vu32;
2860  let Inst{12-8} = Vu32{4-0};
2861  bits <5> Vd32;
2862  let Inst{4-0} = Vd32{4-0};
2863}
2864class Enc_c6220b : OpcodeHexagon {
2865  bits <2> Ii;
2866  let Inst{13-13} = Ii{1-1};
2867  let Inst{7-7} = Ii{0-0};
2868  bits <5> Rs32;
2869  let Inst{20-16} = Rs32{4-0};
2870  bits <5> Ru32;
2871  let Inst{12-8} = Ru32{4-0};
2872  bits <3> Nt8;
2873  let Inst{2-0} = Nt8{2-0};
2874}
2875class Enc_c7a204 : OpcodeHexagon {
2876  bits <6> II;
2877  let Inst{5-0} = II{5-0};
2878  bits <5> Rtt32;
2879  let Inst{12-8} = Rtt32{4-0};
2880  bits <5> Re32;
2881  let Inst{20-16} = Re32{4-0};
2882}
2883class Enc_c7cd90 : OpcodeHexagon {
2884  bits <4> Ii;
2885  let Inst{6-3} = Ii{3-0};
2886  bits <3> Nt8;
2887  let Inst{10-8} = Nt8{2-0};
2888  bits <5> Rx32;
2889  let Inst{20-16} = Rx32{4-0};
2890}
2891class Enc_c85e2a : OpcodeHexagon {
2892  bits <5> Ii;
2893  let Inst{12-8} = Ii{4-0};
2894  bits <5> II;
2895  let Inst{22-21} = II{4-3};
2896  let Inst{7-5} = II{2-0};
2897  bits <5> Rd32;
2898  let Inst{4-0} = Rd32{4-0};
2899}
2900class Enc_c89067 : OpcodeHexagon {
2901  bits <5> Rtt32;
2902  let Inst{20-16} = Rtt32{4-0};
2903  bits <5> Rdd32;
2904  let Inst{4-0} = Rdd32{4-0};
2905  bits <5> Rx32;
2906  let Inst{12-8} = Rx32{4-0};
2907}
2908class Enc_c90aca : OpcodeHexagon {
2909  bits <8> Ii;
2910  let Inst{12-5} = Ii{7-0};
2911  bits <5> Rs32;
2912  let Inst{20-16} = Rs32{4-0};
2913  bits <5> Rx32;
2914  let Inst{4-0} = Rx32{4-0};
2915}
2916class Enc_c9a18e : OpcodeHexagon {
2917  bits <11> Ii;
2918  let Inst{21-20} = Ii{10-9};
2919  let Inst{7-1} = Ii{8-2};
2920  bits <3> Ns8;
2921  let Inst{18-16} = Ns8{2-0};
2922  bits <5> Rt32;
2923  let Inst{12-8} = Rt32{4-0};
2924}
2925class Enc_c9e3bc : OpcodeHexagon {
2926  bits <4> Ii;
2927  let Inst{13-13} = Ii{3-3};
2928  let Inst{10-8} = Ii{2-0};
2929  bits <5> Rt32;
2930  let Inst{20-16} = Rt32{4-0};
2931  bits <5> Vs32;
2932  let Inst{4-0} = Vs32{4-0};
2933}
2934class Enc_ca3887 : OpcodeHexagon {
2935  bits <5> Rs32;
2936  let Inst{20-16} = Rs32{4-0};
2937  bits <5> Rt32;
2938  let Inst{12-8} = Rt32{4-0};
2939}
2940class Enc_cb4b4e : OpcodeHexagon {
2941  bits <2> Pu4;
2942  let Inst{6-5} = Pu4{1-0};
2943  bits <5> Rs32;
2944  let Inst{20-16} = Rs32{4-0};
2945  bits <5> Rt32;
2946  let Inst{12-8} = Rt32{4-0};
2947  bits <5> Rdd32;
2948  let Inst{4-0} = Rdd32{4-0};
2949}
2950class Enc_cb785b : OpcodeHexagon {
2951  bits <5> Vu32;
2952  let Inst{12-8} = Vu32{4-0};
2953  bits <5> Rtt32;
2954  let Inst{20-16} = Rtt32{4-0};
2955  bits <5> Vdd32;
2956  let Inst{4-0} = Vdd32{4-0};
2957}
2958class Enc_cb9321 : OpcodeHexagon {
2959  bits <16> Ii;
2960  let Inst{27-21} = Ii{15-9};
2961  let Inst{13-5} = Ii{8-0};
2962  bits <5> Rs32;
2963  let Inst{20-16} = Rs32{4-0};
2964  bits <5> Rd32;
2965  let Inst{4-0} = Rd32{4-0};
2966}
2967class Enc_cc449f : OpcodeHexagon {
2968  bits <4> Ii;
2969  let Inst{6-3} = Ii{3-0};
2970  bits <2> Pv4;
2971  let Inst{1-0} = Pv4{1-0};
2972  bits <5> Rt32;
2973  let Inst{12-8} = Rt32{4-0};
2974  bits <5> Rx32;
2975  let Inst{20-16} = Rx32{4-0};
2976}
2977class Enc_cc857d : OpcodeHexagon {
2978  bits <5> Vuu32;
2979  let Inst{12-8} = Vuu32{4-0};
2980  bits <5> Rt32;
2981  let Inst{20-16} = Rt32{4-0};
2982  bits <5> Vx32;
2983  let Inst{4-0} = Vx32{4-0};
2984}
2985class Enc_cd4705 : OpcodeHexagon {
2986  bits <3> Ii;
2987  let Inst{7-5} = Ii{2-0};
2988  bits <5> Vu32;
2989  let Inst{12-8} = Vu32{4-0};
2990  bits <5> Vv32;
2991  let Inst{20-16} = Vv32{4-0};
2992  bits <5> Vx32;
2993  let Inst{4-0} = Vx32{4-0};
2994}
2995class Enc_cd82bc : OpcodeHexagon {
2996  bits <4> Ii;
2997  let Inst{21-21} = Ii{3-3};
2998  let Inst{7-5} = Ii{2-0};
2999  bits <6> II;
3000  let Inst{13-8} = II{5-0};
3001  bits <5> Rs32;
3002  let Inst{20-16} = Rs32{4-0};
3003  bits <5> Rx32;
3004  let Inst{4-0} = Rx32{4-0};
3005}
3006class Enc_cda00a : OpcodeHexagon {
3007  bits <12> Ii;
3008  let Inst{19-16} = Ii{11-8};
3009  let Inst{12-5} = Ii{7-0};
3010  bits <2> Pu4;
3011  let Inst{22-21} = Pu4{1-0};
3012  bits <5> Rd32;
3013  let Inst{4-0} = Rd32{4-0};
3014}
3015class Enc_ce6828 : OpcodeHexagon {
3016  bits <14> Ii;
3017  let Inst{26-25} = Ii{13-12};
3018  let Inst{13-13} = Ii{11-11};
3019  let Inst{7-0} = Ii{10-3};
3020  bits <5> Rs32;
3021  let Inst{20-16} = Rs32{4-0};
3022  bits <5> Rtt32;
3023  let Inst{12-8} = Rtt32{4-0};
3024}
3025class Enc_cf1927 : OpcodeHexagon {
3026  bits <1> Mu2;
3027  let Inst{13-13} = Mu2{0-0};
3028  bits <3> Os8;
3029  let Inst{2-0} = Os8{2-0};
3030  bits <5> Rx32;
3031  let Inst{20-16} = Rx32{4-0};
3032}
3033class Enc_d0fe02 : OpcodeHexagon {
3034  bits <5> Rxx32;
3035  let Inst{20-16} = Rxx32{4-0};
3036  bits <0> sgp10;
3037}
3038class Enc_d15d19 : OpcodeHexagon {
3039  bits <1> Mu2;
3040  let Inst{13-13} = Mu2{0-0};
3041  bits <5> Vs32;
3042  let Inst{4-0} = Vs32{4-0};
3043  bits <5> Rx32;
3044  let Inst{20-16} = Rx32{4-0};
3045}
3046class Enc_d2216a : OpcodeHexagon {
3047  bits <5> Rss32;
3048  let Inst{20-16} = Rss32{4-0};
3049  bits <5> Rtt32;
3050  let Inst{12-8} = Rtt32{4-0};
3051  bits <5> Rd32;
3052  let Inst{4-0} = Rd32{4-0};
3053}
3054class Enc_d2c7f1 : OpcodeHexagon {
3055  bits <5> Rtt32;
3056  let Inst{12-8} = Rtt32{4-0};
3057  bits <5> Rss32;
3058  let Inst{20-16} = Rss32{4-0};
3059  bits <5> Rdd32;
3060  let Inst{4-0} = Rdd32{4-0};
3061  bits <2> Pe4;
3062  let Inst{6-5} = Pe4{1-0};
3063}
3064class Enc_d44e31 : OpcodeHexagon {
3065  bits <6> Ii;
3066  let Inst{12-7} = Ii{5-0};
3067  bits <5> Rs32;
3068  let Inst{20-16} = Rs32{4-0};
3069  bits <5> Rt32;
3070  let Inst{4-0} = Rt32{4-0};
3071}
3072class Enc_d483b9 : OpcodeHexagon {
3073  bits <1> Ii;
3074  let Inst{5-5} = Ii{0-0};
3075  bits <5> Vuu32;
3076  let Inst{12-8} = Vuu32{4-0};
3077  bits <5> Rt32;
3078  let Inst{20-16} = Rt32{4-0};
3079  bits <5> Vxx32;
3080  let Inst{4-0} = Vxx32{4-0};
3081}
3082class Enc_d50cd3 : OpcodeHexagon {
3083  bits <3> Ii;
3084  let Inst{7-5} = Ii{2-0};
3085  bits <5> Rss32;
3086  let Inst{20-16} = Rss32{4-0};
3087  bits <5> Rtt32;
3088  let Inst{12-8} = Rtt32{4-0};
3089  bits <5> Rdd32;
3090  let Inst{4-0} = Rdd32{4-0};
3091}
3092class Enc_d5c73f : OpcodeHexagon {
3093  bits <1> Mu2;
3094  let Inst{13-13} = Mu2{0-0};
3095  bits <5> Rt32;
3096  let Inst{12-8} = Rt32{4-0};
3097  bits <5> Rx32;
3098  let Inst{20-16} = Rx32{4-0};
3099}
3100class Enc_d6990d : OpcodeHexagon {
3101  bits <5> Vuu32;
3102  let Inst{12-8} = Vuu32{4-0};
3103  bits <5> Rt32;
3104  let Inst{20-16} = Rt32{4-0};
3105  bits <5> Vxx32;
3106  let Inst{4-0} = Vxx32{4-0};
3107}
3108class Enc_d7a65e : OpcodeHexagon {
3109  bits <6> Ii;
3110  let Inst{12-7} = Ii{5-0};
3111  bits <6> II;
3112  let Inst{13-13} = II{5-5};
3113  let Inst{4-0} = II{4-0};
3114  bits <2> Pv4;
3115  let Inst{6-5} = Pv4{1-0};
3116  bits <5> Rs32;
3117  let Inst{20-16} = Rs32{4-0};
3118}
3119class Enc_d7bc34 : OpcodeHexagon {
3120  bits <5> Vu32;
3121  let Inst{12-8} = Vu32{4-0};
3122  bits <3> Rt8;
3123  let Inst{18-16} = Rt8{2-0};
3124  bits <5> Vyyyy32;
3125  let Inst{4-0} = Vyyyy32{4-0};
3126}
3127class Enc_d7dc10 : OpcodeHexagon {
3128  bits <5> Rs32;
3129  let Inst{20-16} = Rs32{4-0};
3130  bits <5> Rtt32;
3131  let Inst{12-8} = Rtt32{4-0};
3132  bits <2> Pd4;
3133  let Inst{1-0} = Pd4{1-0};
3134}
3135class Enc_da664b : OpcodeHexagon {
3136  bits <2> Ii;
3137  let Inst{13-13} = Ii{1-1};
3138  let Inst{7-7} = Ii{0-0};
3139  bits <5> Rs32;
3140  let Inst{20-16} = Rs32{4-0};
3141  bits <5> Rt32;
3142  let Inst{12-8} = Rt32{4-0};
3143  bits <5> Rd32;
3144  let Inst{4-0} = Rd32{4-0};
3145}
3146class Enc_da8d43 : OpcodeHexagon {
3147  bits <6> Ii;
3148  let Inst{13-13} = Ii{5-5};
3149  let Inst{7-3} = Ii{4-0};
3150  bits <2> Pv4;
3151  let Inst{1-0} = Pv4{1-0};
3152  bits <5> Rs32;
3153  let Inst{20-16} = Rs32{4-0};
3154  bits <5> Rt32;
3155  let Inst{12-8} = Rt32{4-0};
3156}
3157class Enc_daea09 : OpcodeHexagon {
3158  bits <17> Ii;
3159  let Inst{23-22} = Ii{16-15};
3160  let Inst{20-16} = Ii{14-10};
3161  let Inst{13-13} = Ii{9-9};
3162  let Inst{7-1} = Ii{8-2};
3163  bits <2> Pu4;
3164  let Inst{9-8} = Pu4{1-0};
3165}
3166class Enc_db40cd : OpcodeHexagon {
3167  bits <6> Ii;
3168  let Inst{6-3} = Ii{5-2};
3169  bits <5> Rt32;
3170  let Inst{12-8} = Rt32{4-0};
3171  bits <5> Rx32;
3172  let Inst{20-16} = Rx32{4-0};
3173}
3174class Enc_dbd70c : OpcodeHexagon {
3175  bits <5> Rss32;
3176  let Inst{20-16} = Rss32{4-0};
3177  bits <5> Rtt32;
3178  let Inst{12-8} = Rtt32{4-0};
3179  bits <2> Pu4;
3180  let Inst{6-5} = Pu4{1-0};
3181  bits <5> Rdd32;
3182  let Inst{4-0} = Rdd32{4-0};
3183}
3184class Enc_dd766a : OpcodeHexagon {
3185  bits <5> Vu32;
3186  let Inst{12-8} = Vu32{4-0};
3187  bits <5> Vdd32;
3188  let Inst{4-0} = Vdd32{4-0};
3189}
3190class Enc_de0214 : OpcodeHexagon {
3191  bits <12> Ii;
3192  let Inst{26-25} = Ii{11-10};
3193  let Inst{13-5} = Ii{9-1};
3194  bits <5> Rs32;
3195  let Inst{20-16} = Rs32{4-0};
3196  bits <5> Rd32;
3197  let Inst{4-0} = Rd32{4-0};
3198}
3199class Enc_de5ea0 : OpcodeHexagon {
3200  bits <5> Vuu32;
3201  let Inst{12-8} = Vuu32{4-0};
3202  bits <5> Vv32;
3203  let Inst{20-16} = Vv32{4-0};
3204  bits <5> Vd32;
3205  let Inst{4-0} = Vd32{4-0};
3206}
3207class Enc_e07374 : OpcodeHexagon {
3208  bits <5> Rs32;
3209  let Inst{20-16} = Rs32{4-0};
3210  bits <5> Rtt32;
3211  let Inst{12-8} = Rtt32{4-0};
3212  bits <5> Rd32;
3213  let Inst{4-0} = Rd32{4-0};
3214}
3215class Enc_e0820b : OpcodeHexagon {
3216  bits <5> Vu32;
3217  let Inst{12-8} = Vu32{4-0};
3218  bits <5> Vv32;
3219  let Inst{20-16} = Vv32{4-0};
3220  bits <2> Qs4;
3221  let Inst{6-5} = Qs4{1-0};
3222  bits <5> Vd32;
3223  let Inst{4-0} = Vd32{4-0};
3224}
3225class Enc_e0a47a : OpcodeHexagon {
3226  bits <4> Ii;
3227  let Inst{8-5} = Ii{3-0};
3228  bits <1> Mu2;
3229  let Inst{13-13} = Mu2{0-0};
3230  bits <5> Rd32;
3231  let Inst{4-0} = Rd32{4-0};
3232  bits <5> Rx32;
3233  let Inst{20-16} = Rx32{4-0};
3234}
3235class Enc_e26546 : OpcodeHexagon {
3236  bits <5> Ii;
3237  let Inst{6-3} = Ii{4-1};
3238  bits <3> Nt8;
3239  let Inst{10-8} = Nt8{2-0};
3240  bits <5> Rx32;
3241  let Inst{20-16} = Rx32{4-0};
3242}
3243class Enc_e32517 : OpcodeHexagon {
3244  bits <7> Sss128;
3245  let Inst{22-16} = Sss128{6-0};
3246  bits <5> Rdd32;
3247  let Inst{4-0} = Rdd32{4-0};
3248}
3249class Enc_e38e1f : OpcodeHexagon {
3250  bits <8> Ii;
3251  let Inst{12-5} = Ii{7-0};
3252  bits <2> Pu4;
3253  let Inst{22-21} = Pu4{1-0};
3254  bits <5> Rs32;
3255  let Inst{20-16} = Rs32{4-0};
3256  bits <5> Rd32;
3257  let Inst{4-0} = Rd32{4-0};
3258}
3259class Enc_e39bb2 : OpcodeHexagon {
3260  bits <6> Ii;
3261  let Inst{9-4} = Ii{5-0};
3262  bits <4> Rd16;
3263  let Inst{3-0} = Rd16{3-0};
3264}
3265class Enc_e3b0c4 : OpcodeHexagon {
3266
3267}
3268class Enc_e66a97 : OpcodeHexagon {
3269  bits <7> Ii;
3270  let Inst{12-7} = Ii{6-1};
3271  bits <5> II;
3272  let Inst{4-0} = II{4-0};
3273  bits <5> Rs32;
3274  let Inst{20-16} = Rs32{4-0};
3275}
3276class Enc_e6abcf : OpcodeHexagon {
3277  bits <5> Rs32;
3278  let Inst{20-16} = Rs32{4-0};
3279  bits <5> Rtt32;
3280  let Inst{12-8} = Rtt32{4-0};
3281}
3282class Enc_e6c957 : OpcodeHexagon {
3283  bits <10> Ii;
3284  let Inst{21-21} = Ii{9-9};
3285  let Inst{13-5} = Ii{8-0};
3286  bits <5> Rdd32;
3287  let Inst{4-0} = Rdd32{4-0};
3288}
3289class Enc_e7581c : OpcodeHexagon {
3290  bits <5> Vu32;
3291  let Inst{12-8} = Vu32{4-0};
3292  bits <5> Vd32;
3293  let Inst{4-0} = Vd32{4-0};
3294}
3295class Enc_e83554 : OpcodeHexagon {
3296  bits <5> Ii;
3297  let Inst{8-5} = Ii{4-1};
3298  bits <1> Mu2;
3299  let Inst{13-13} = Mu2{0-0};
3300  bits <5> Rd32;
3301  let Inst{4-0} = Rd32{4-0};
3302  bits <5> Rx32;
3303  let Inst{20-16} = Rx32{4-0};
3304}
3305class Enc_e8c45e : OpcodeHexagon {
3306  bits <7> Ii;
3307  let Inst{13-13} = Ii{6-6};
3308  let Inst{7-3} = Ii{5-1};
3309  bits <2> Pv4;
3310  let Inst{1-0} = Pv4{1-0};
3311  bits <5> Rs32;
3312  let Inst{20-16} = Rs32{4-0};
3313  bits <5> Rt32;
3314  let Inst{12-8} = Rt32{4-0};
3315}
3316class Enc_e90a15 : OpcodeHexagon {
3317  bits <11> Ii;
3318  let Inst{21-20} = Ii{10-9};
3319  let Inst{7-1} = Ii{8-2};
3320  bits <3> Ns8;
3321  let Inst{18-16} = Ns8{2-0};
3322  bits <4> n1;
3323  let Inst{29-29} = n1{3-3};
3324  let Inst{26-25} = n1{2-1};
3325  let Inst{22-22} = n1{0-0};
3326}
3327class Enc_e957fb : OpcodeHexagon {
3328  bits <12> Ii;
3329  let Inst{26-25} = Ii{11-10};
3330  let Inst{13-13} = Ii{9-9};
3331  let Inst{7-0} = Ii{8-1};
3332  bits <5> Rs32;
3333  let Inst{20-16} = Rs32{4-0};
3334  bits <5> Rt32;
3335  let Inst{12-8} = Rt32{4-0};
3336}
3337class Enc_ea23e4 : OpcodeHexagon {
3338  bits <5> Rtt32;
3339  let Inst{12-8} = Rtt32{4-0};
3340  bits <5> Rss32;
3341  let Inst{20-16} = Rss32{4-0};
3342  bits <5> Rdd32;
3343  let Inst{4-0} = Rdd32{4-0};
3344}
3345class Enc_ea4c54 : OpcodeHexagon {
3346  bits <2> Pu4;
3347  let Inst{6-5} = Pu4{1-0};
3348  bits <5> Rs32;
3349  let Inst{20-16} = Rs32{4-0};
3350  bits <5> Rt32;
3351  let Inst{12-8} = Rt32{4-0};
3352  bits <5> Rd32;
3353  let Inst{4-0} = Rd32{4-0};
3354}
3355class Enc_eaa9f8 : OpcodeHexagon {
3356  bits <5> Vu32;
3357  let Inst{12-8} = Vu32{4-0};
3358  bits <5> Vv32;
3359  let Inst{20-16} = Vv32{4-0};
3360  bits <2> Qx4;
3361  let Inst{1-0} = Qx4{1-0};
3362}
3363class Enc_eafd18 : OpcodeHexagon {
3364  bits <5> II;
3365  let Inst{12-8} = II{4-0};
3366  bits <11> Ii;
3367  let Inst{21-20} = Ii{10-9};
3368  let Inst{7-1} = Ii{8-2};
3369  bits <3> Ns8;
3370  let Inst{18-16} = Ns8{2-0};
3371}
3372class Enc_eca7c8 : OpcodeHexagon {
3373  bits <2> Ii;
3374  let Inst{13-13} = Ii{1-1};
3375  let Inst{7-7} = Ii{0-0};
3376  bits <5> Rs32;
3377  let Inst{20-16} = Rs32{4-0};
3378  bits <5> Ru32;
3379  let Inst{12-8} = Ru32{4-0};
3380  bits <5> Rt32;
3381  let Inst{4-0} = Rt32{4-0};
3382}
3383class Enc_ecbcc8 : OpcodeHexagon {
3384  bits <5> Rs32;
3385  let Inst{20-16} = Rs32{4-0};
3386}
3387class Enc_ed48be : OpcodeHexagon {
3388  bits <2> Ii;
3389  let Inst{6-5} = Ii{1-0};
3390  bits <3> Rdd8;
3391  let Inst{2-0} = Rdd8{2-0};
3392}
3393class Enc_ed5027 : OpcodeHexagon {
3394  bits <5> Rss32;
3395  let Inst{20-16} = Rss32{4-0};
3396  bits <5> Gdd32;
3397  let Inst{4-0} = Gdd32{4-0};
3398}
3399class Enc_ee5ed0 : OpcodeHexagon {
3400  bits <4> Rs16;
3401  let Inst{7-4} = Rs16{3-0};
3402  bits <4> Rd16;
3403  let Inst{3-0} = Rd16{3-0};
3404  bits <2> n1;
3405  let Inst{9-8} = n1{1-0};
3406}
3407class Enc_ef601b : OpcodeHexagon {
3408  bits <4> Ii;
3409  let Inst{13-13} = Ii{3-3};
3410  let Inst{10-8} = Ii{2-0};
3411  bits <2> Pv4;
3412  let Inst{12-11} = Pv4{1-0};
3413  bits <5> Rt32;
3414  let Inst{20-16} = Rt32{4-0};
3415}
3416class Enc_efaed8 : OpcodeHexagon {
3417  bits <1> Ii;
3418  let Inst{8-8} = Ii{0-0};
3419}
3420class Enc_f0cca7 : OpcodeHexagon {
3421  bits <8> Ii;
3422  let Inst{12-5} = Ii{7-0};
3423  bits <6> II;
3424  let Inst{20-16} = II{5-1};
3425  let Inst{13-13} = II{0-0};
3426  bits <5> Rdd32;
3427  let Inst{4-0} = Rdd32{4-0};
3428}
3429class Enc_f20719 : OpcodeHexagon {
3430  bits <7> Ii;
3431  let Inst{12-7} = Ii{6-1};
3432  bits <6> II;
3433  let Inst{13-13} = II{5-5};
3434  let Inst{4-0} = II{4-0};
3435  bits <2> Pv4;
3436  let Inst{6-5} = Pv4{1-0};
3437  bits <5> Rs32;
3438  let Inst{20-16} = Rs32{4-0};
3439}
3440class Enc_f37377 : OpcodeHexagon {
3441  bits <8> Ii;
3442  let Inst{12-7} = Ii{7-2};
3443  bits <8> II;
3444  let Inst{13-13} = II{7-7};
3445  let Inst{6-0} = II{6-0};
3446  bits <5> Rs32;
3447  let Inst{20-16} = Rs32{4-0};
3448}
3449class Enc_f394d3 : OpcodeHexagon {
3450  bits <6> II;
3451  let Inst{11-8} = II{5-2};
3452  let Inst{6-5} = II{1-0};
3453  bits <5> Ryy32;
3454  let Inst{4-0} = Ryy32{4-0};
3455  bits <5> Re32;
3456  let Inst{20-16} = Re32{4-0};
3457}
3458class Enc_f3f408 : OpcodeHexagon {
3459  bits <4> Ii;
3460  let Inst{13-13} = Ii{3-3};
3461  let Inst{10-8} = Ii{2-0};
3462  bits <5> Rt32;
3463  let Inst{20-16} = Rt32{4-0};
3464  bits <5> Vd32;
3465  let Inst{4-0} = Vd32{4-0};
3466}
3467class Enc_f4413a : OpcodeHexagon {
3468  bits <4> Ii;
3469  let Inst{8-5} = Ii{3-0};
3470  bits <2> Pt4;
3471  let Inst{10-9} = Pt4{1-0};
3472  bits <5> Rd32;
3473  let Inst{4-0} = Rd32{4-0};
3474  bits <5> Rx32;
3475  let Inst{20-16} = Rx32{4-0};
3476}
3477class Enc_f44229 : OpcodeHexagon {
3478  bits <7> Ii;
3479  let Inst{13-13} = Ii{6-6};
3480  let Inst{7-3} = Ii{5-1};
3481  bits <2> Pv4;
3482  let Inst{1-0} = Pv4{1-0};
3483  bits <5> Rs32;
3484  let Inst{20-16} = Rs32{4-0};
3485  bits <3> Nt8;
3486  let Inst{10-8} = Nt8{2-0};
3487}
3488class Enc_f4f57b : OpcodeHexagon {
3489  bits <2> Ii;
3490  let Inst{6-5} = Ii{1-0};
3491  bits <5> Vuu32;
3492  let Inst{12-8} = Vuu32{4-0};
3493  bits <5> Vvv32;
3494  let Inst{20-16} = Vvv32{4-0};
3495  bits <5> Vxx32;
3496  let Inst{4-0} = Vxx32{4-0};
3497}
3498class Enc_f55a0c : OpcodeHexagon {
3499  bits <6> Ii;
3500  let Inst{11-8} = Ii{5-2};
3501  bits <4> Rs16;
3502  let Inst{7-4} = Rs16{3-0};
3503  bits <4> Rt16;
3504  let Inst{3-0} = Rt16{3-0};
3505}
3506class Enc_f5e933 : OpcodeHexagon {
3507  bits <2> Ps4;
3508  let Inst{17-16} = Ps4{1-0};
3509  bits <5> Rd32;
3510  let Inst{4-0} = Rd32{4-0};
3511}
3512class Enc_f6fe0b : OpcodeHexagon {
3513  bits <11> Ii;
3514  let Inst{21-20} = Ii{10-9};
3515  let Inst{7-1} = Ii{8-2};
3516  bits <4> Rs16;
3517  let Inst{19-16} = Rs16{3-0};
3518  bits <6> n1;
3519  let Inst{28-28} = n1{5-5};
3520  let Inst{24-22} = n1{4-2};
3521  let Inst{13-13} = n1{1-1};
3522  let Inst{8-8} = n1{0-0};
3523}
3524class Enc_f7430e : OpcodeHexagon {
3525  bits <4> Ii;
3526  let Inst{13-13} = Ii{3-3};
3527  let Inst{10-8} = Ii{2-0};
3528  bits <2> Pv4;
3529  let Inst{12-11} = Pv4{1-0};
3530  bits <5> Rt32;
3531  let Inst{20-16} = Rt32{4-0};
3532  bits <3> Os8;
3533  let Inst{2-0} = Os8{2-0};
3534}
3535class Enc_f77fbc : OpcodeHexagon {
3536  bits <4> Ii;
3537  let Inst{13-13} = Ii{3-3};
3538  let Inst{10-8} = Ii{2-0};
3539  bits <5> Rt32;
3540  let Inst{20-16} = Rt32{4-0};
3541  bits <3> Os8;
3542  let Inst{2-0} = Os8{2-0};
3543}
3544class Enc_f79415 : OpcodeHexagon {
3545  bits <2> Ii;
3546  let Inst{13-13} = Ii{1-1};
3547  let Inst{6-6} = Ii{0-0};
3548  bits <6> II;
3549  let Inst{5-0} = II{5-0};
3550  bits <5> Ru32;
3551  let Inst{20-16} = Ru32{4-0};
3552  bits <5> Rtt32;
3553  let Inst{12-8} = Rtt32{4-0};
3554}
3555class Enc_f7ea77 : OpcodeHexagon {
3556  bits <11> Ii;
3557  let Inst{21-20} = Ii{10-9};
3558  let Inst{7-1} = Ii{8-2};
3559  bits <3> Ns8;
3560  let Inst{18-16} = Ns8{2-0};
3561  bits <4> n1;
3562  let Inst{29-29} = n1{3-3};
3563  let Inst{26-25} = n1{2-1};
3564  let Inst{13-13} = n1{0-0};
3565}
3566class Enc_f82302 : OpcodeHexagon {
3567  bits <11> Ii;
3568  let Inst{21-20} = Ii{10-9};
3569  let Inst{7-1} = Ii{8-2};
3570  bits <3> Ns8;
3571  let Inst{18-16} = Ns8{2-0};
3572  bits <4> n1;
3573  let Inst{29-29} = n1{3-3};
3574  let Inst{26-25} = n1{2-1};
3575  let Inst{23-23} = n1{0-0};
3576}
3577class Enc_f82eaf : OpcodeHexagon {
3578  bits <8> Ii;
3579  let Inst{10-5} = Ii{7-2};
3580  bits <2> Pt4;
3581  let Inst{12-11} = Pt4{1-0};
3582  bits <5> Rs32;
3583  let Inst{20-16} = Rs32{4-0};
3584  bits <5> Rd32;
3585  let Inst{4-0} = Rd32{4-0};
3586}
3587class Enc_f8c1c4 : OpcodeHexagon {
3588  bits <2> Pv4;
3589  let Inst{12-11} = Pv4{1-0};
3590  bits <1> Mu2;
3591  let Inst{13-13} = Mu2{0-0};
3592  bits <5> Vd32;
3593  let Inst{4-0} = Vd32{4-0};
3594  bits <5> Rx32;
3595  let Inst{20-16} = Rx32{4-0};
3596}
3597class Enc_f8ecf9 : OpcodeHexagon {
3598  bits <5> Vuu32;
3599  let Inst{12-8} = Vuu32{4-0};
3600  bits <5> Vvv32;
3601  let Inst{20-16} = Vvv32{4-0};
3602  bits <5> Vdd32;
3603  let Inst{4-0} = Vdd32{4-0};
3604}
3605class Enc_fa3ba4 : OpcodeHexagon {
3606  bits <14> Ii;
3607  let Inst{26-25} = Ii{13-12};
3608  let Inst{13-5} = Ii{11-3};
3609  bits <5> Rs32;
3610  let Inst{20-16} = Rs32{4-0};
3611  bits <5> Rdd32;
3612  let Inst{4-0} = Rdd32{4-0};
3613}
3614class Enc_fb6577 : OpcodeHexagon {
3615  bits <2> Pu4;
3616  let Inst{9-8} = Pu4{1-0};
3617  bits <5> Rs32;
3618  let Inst{20-16} = Rs32{4-0};
3619  bits <5> Rd32;
3620  let Inst{4-0} = Rd32{4-0};
3621}
3622class Enc_fc4562 : OpcodeHexagon {
3623  bits <5> Rs32;
3624  let Inst{12-8} = Rs32{4-0};
3625  bits <5> Rtt32;
3626  let Inst{20-16} = Rtt32{4-0};
3627  bits <5> Rdd32;
3628  let Inst{4-0} = Rdd32{4-0};
3629}
3630class Enc_fcf7a7 : OpcodeHexagon {
3631  bits <5> Rss32;
3632  let Inst{20-16} = Rss32{4-0};
3633  bits <5> Rtt32;
3634  let Inst{12-8} = Rtt32{4-0};
3635  bits <2> Pd4;
3636  let Inst{1-0} = Pd4{1-0};
3637}
3638class Enc_fda92c : OpcodeHexagon {
3639  bits <17> Ii;
3640  let Inst{26-25} = Ii{16-15};
3641  let Inst{20-16} = Ii{14-10};
3642  let Inst{13-13} = Ii{9-9};
3643  let Inst{7-0} = Ii{8-1};
3644  bits <5> Rt32;
3645  let Inst{12-8} = Rt32{4-0};
3646}
3647class Enc_fef969 : OpcodeHexagon {
3648  bits <6> Ii;
3649  let Inst{20-16} = Ii{5-1};
3650  let Inst{5-5} = Ii{0-0};
3651  bits <5> Rt32;
3652  let Inst{12-8} = Rt32{4-0};
3653  bits <5> Rd32;
3654  let Inst{4-0} = Rd32{4-0};
3655}
3656class Enc_ff3442 : OpcodeHexagon {
3657  bits <4> Ii;
3658  let Inst{13-13} = Ii{3-3};
3659  let Inst{10-8} = Ii{2-0};
3660  bits <5> Rt32;
3661  let Inst{20-16} = Rt32{4-0};
3662}
3663