xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td (revision 43a5ec4eb41567cc92586503212743d89686d78f) 
1//===----------------------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Automatically generated file, do not edit!
9//===----------------------------------------------------------------------===//
10
11class Enc_01d3d0 : OpcodeHexagon {
12  bits <5> Vu32;
13  let Inst{12-8} = Vu32{4-0};
14  bits <5> Rt32;
15  let Inst{20-16} = Rt32{4-0};
16  bits <5> Vdd32;
17  let Inst{4-0} = Vdd32{4-0};
18}
19class Enc_02553a : OpcodeHexagon {
20  bits <7> Ii;
21  let Inst{11-5} = Ii{6-0};
22  bits <5> Rs32;
23  let Inst{20-16} = Rs32{4-0};
24  bits <2> Pd4;
25  let Inst{1-0} = Pd4{1-0};
26}
27class Enc_03833b : OpcodeHexagon {
28  bits <5> Rss32;
29  let Inst{20-16} = Rss32{4-0};
30  bits <5> Rt32;
31  let Inst{12-8} = Rt32{4-0};
32  bits <2> Pd4;
33  let Inst{1-0} = Pd4{1-0};
34}
35class Enc_041d7b : OpcodeHexagon {
36  bits <11> Ii;
37  let Inst{21-20} = Ii{10-9};
38  let Inst{7-1} = Ii{8-2};
39  bits <4> Rs16;
40  let Inst{19-16} = Rs16{3-0};
41  bits <5> n1;
42  let Inst{28-28} = n1{4-4};
43  let Inst{24-23} = n1{3-2};
44  let Inst{13-13} = n1{1-1};
45  let Inst{8-8} = n1{0-0};
46}
47class Enc_04c959 : OpcodeHexagon {
48  bits <2> Ii;
49  let Inst{13-13} = Ii{1-1};
50  let Inst{7-7} = Ii{0-0};
51  bits <6> II;
52  let Inst{11-8} = II{5-2};
53  let Inst{6-5} = II{1-0};
54  bits <5> Rt32;
55  let Inst{20-16} = Rt32{4-0};
56  bits <5> Ryy32;
57  let Inst{4-0} = Ryy32{4-0};
58}
59class Enc_0527db : OpcodeHexagon {
60  bits <4> Rs16;
61  let Inst{7-4} = Rs16{3-0};
62  bits <4> Rx16;
63  let Inst{3-0} = Rx16{3-0};
64}
65class Enc_052c7d : OpcodeHexagon {
66  bits <5> Ii;
67  let Inst{6-3} = Ii{4-1};
68  bits <5> Rt32;
69  let Inst{12-8} = Rt32{4-0};
70  bits <5> Rx32;
71  let Inst{20-16} = Rx32{4-0};
72}
73class Enc_08d755 : OpcodeHexagon {
74  bits <8> Ii;
75  let Inst{12-5} = Ii{7-0};
76  bits <5> Rs32;
77  let Inst{20-16} = Rs32{4-0};
78  bits <2> Pd4;
79  let Inst{1-0} = Pd4{1-0};
80}
81class Enc_0aa344 : OpcodeHexagon {
82  bits <5> Gss32;
83  let Inst{20-16} = Gss32{4-0};
84  bits <5> Rdd32;
85  let Inst{4-0} = Rdd32{4-0};
86}
87class Enc_0b2e5b : OpcodeHexagon {
88  bits <3> Ii;
89  let Inst{7-5} = Ii{2-0};
90  bits <5> Vu32;
91  let Inst{12-8} = Vu32{4-0};
92  bits <5> Vv32;
93  let Inst{20-16} = Vv32{4-0};
94  bits <5> Vd32;
95  let Inst{4-0} = Vd32{4-0};
96}
97class Enc_0b51ce : OpcodeHexagon {
98  bits <3> Ii;
99  let Inst{10-8} = Ii{2-0};
100  bits <2> Qv4;
101  let Inst{12-11} = Qv4{1-0};
102  bits <5> Vs32;
103  let Inst{4-0} = Vs32{4-0};
104  bits <5> Rx32;
105  let Inst{20-16} = Rx32{4-0};
106}
107class Enc_0cb018 : OpcodeHexagon {
108  bits <5> Cs32;
109  let Inst{20-16} = Cs32{4-0};
110  bits <5> Rd32;
111  let Inst{4-0} = Rd32{4-0};
112}
113class Enc_0d8870 : OpcodeHexagon {
114  bits <12> Ii;
115  let Inst{26-25} = Ii{11-10};
116  let Inst{13-13} = Ii{9-9};
117  let Inst{7-0} = Ii{8-1};
118  bits <5> Rs32;
119  let Inst{20-16} = Rs32{4-0};
120  bits <3> Nt8;
121  let Inst{10-8} = Nt8{2-0};
122}
123class Enc_0d8adb : OpcodeHexagon {
124  bits <8> Ii;
125  let Inst{12-5} = Ii{7-0};
126  bits <5> Rss32;
127  let Inst{20-16} = Rss32{4-0};
128  bits <2> Pd4;
129  let Inst{1-0} = Pd4{1-0};
130}
131class Enc_0e41fa : OpcodeHexagon {
132  bits <5> Vuu32;
133  let Inst{12-8} = Vuu32{4-0};
134  bits <5> Rt32;
135  let Inst{20-16} = Rt32{4-0};
136  bits <5> Vd32;
137  let Inst{4-0} = Vd32{4-0};
138}
139class Enc_0ed752 : OpcodeHexagon {
140  bits <5> Rss32;
141  let Inst{20-16} = Rss32{4-0};
142  bits <5> Cdd32;
143  let Inst{4-0} = Cdd32{4-0};
144}
145class Enc_0f8bab : OpcodeHexagon {
146  bits <5> Vu32;
147  let Inst{12-8} = Vu32{4-0};
148  bits <5> Rt32;
149  let Inst{20-16} = Rt32{4-0};
150  bits <2> Qd4;
151  let Inst{1-0} = Qd4{1-0};
152}
153class Enc_0fa531 : OpcodeHexagon {
154  bits <15> Ii;
155  let Inst{21-21} = Ii{14-14};
156  let Inst{13-13} = Ii{13-13};
157  let Inst{11-1} = Ii{12-2};
158  bits <5> Rs32;
159  let Inst{20-16} = Rs32{4-0};
160}
161class Enc_10bc21 : OpcodeHexagon {
162  bits <4> Ii;
163  let Inst{6-3} = Ii{3-0};
164  bits <5> Rt32;
165  let Inst{12-8} = Rt32{4-0};
166  bits <5> Rx32;
167  let Inst{20-16} = Rx32{4-0};
168}
169class Enc_1178da : OpcodeHexagon {
170  bits <3> Ii;
171  let Inst{7-5} = Ii{2-0};
172  bits <5> Vu32;
173  let Inst{12-8} = Vu32{4-0};
174  bits <5> Vv32;
175  let Inst{20-16} = Vv32{4-0};
176  bits <5> Vxx32;
177  let Inst{4-0} = Vxx32{4-0};
178}
179class Enc_11a146 : OpcodeHexagon {
180  bits <4> Ii;
181  let Inst{11-8} = Ii{3-0};
182  bits <5> Rss32;
183  let Inst{20-16} = Rss32{4-0};
184  bits <5> Rd32;
185  let Inst{4-0} = Rd32{4-0};
186}
187class Enc_12b6e9 : OpcodeHexagon {
188  bits <4> Ii;
189  let Inst{11-8} = Ii{3-0};
190  bits <5> Rss32;
191  let Inst{20-16} = Rss32{4-0};
192  bits <5> Rdd32;
193  let Inst{4-0} = Rdd32{4-0};
194}
195class Enc_134437 : OpcodeHexagon {
196  bits <2> Qs4;
197  let Inst{9-8} = Qs4{1-0};
198  bits <2> Qt4;
199  let Inst{23-22} = Qt4{1-0};
200  bits <2> Qd4;
201  let Inst{1-0} = Qd4{1-0};
202}
203class Enc_140c83 : OpcodeHexagon {
204  bits <10> Ii;
205  let Inst{21-21} = Ii{9-9};
206  let Inst{13-5} = Ii{8-0};
207  bits <5> Rs32;
208  let Inst{20-16} = Rs32{4-0};
209  bits <5> Rd32;
210  let Inst{4-0} = Rd32{4-0};
211}
212class Enc_143445 : OpcodeHexagon {
213  bits <13> Ii;
214  let Inst{26-25} = Ii{12-11};
215  let Inst{13-13} = Ii{10-10};
216  let Inst{7-0} = Ii{9-2};
217  bits <5> Rs32;
218  let Inst{20-16} = Rs32{4-0};
219  bits <5> Rt32;
220  let Inst{12-8} = Rt32{4-0};
221}
222class Enc_143a3c : OpcodeHexagon {
223  bits <6> Ii;
224  let Inst{13-8} = Ii{5-0};
225  bits <6> II;
226  let Inst{23-21} = II{5-3};
227  let Inst{7-5} = II{2-0};
228  bits <5> Rss32;
229  let Inst{20-16} = Rss32{4-0};
230  bits <5> Rxx32;
231  let Inst{4-0} = Rxx32{4-0};
232}
233class Enc_14640c : OpcodeHexagon {
234  bits <11> Ii;
235  let Inst{21-20} = Ii{10-9};
236  let Inst{7-1} = Ii{8-2};
237  bits <4> Rs16;
238  let Inst{19-16} = Rs16{3-0};
239  bits <5> n1;
240  let Inst{28-28} = n1{4-4};
241  let Inst{24-22} = n1{3-1};
242  let Inst{13-13} = n1{0-0};
243}
244class Enc_14d27a : OpcodeHexagon {
245  bits <5> II;
246  let Inst{12-8} = II{4-0};
247  bits <11> Ii;
248  let Inst{21-20} = Ii{10-9};
249  let Inst{7-1} = Ii{8-2};
250  bits <4> Rs16;
251  let Inst{19-16} = Rs16{3-0};
252}
253class Enc_152467 : OpcodeHexagon {
254  bits <5> Ii;
255  let Inst{8-5} = Ii{4-1};
256  bits <5> Rd32;
257  let Inst{4-0} = Rd32{4-0};
258  bits <5> Rx32;
259  let Inst{20-16} = Rx32{4-0};
260}
261class Enc_158beb : OpcodeHexagon {
262  bits <2> Qs4;
263  let Inst{6-5} = Qs4{1-0};
264  bits <5> Rt32;
265  let Inst{20-16} = Rt32{4-0};
266  bits <1> Mu2;
267  let Inst{13-13} = Mu2{0-0};
268  bits <5> Vv32;
269  let Inst{4-0} = Vv32{4-0};
270}
271class Enc_163a3c : OpcodeHexagon {
272  bits <7> Ii;
273  let Inst{12-7} = Ii{6-1};
274  bits <5> Rs32;
275  let Inst{20-16} = Rs32{4-0};
276  bits <5> Rt32;
277  let Inst{4-0} = Rt32{4-0};
278}
279class Enc_16c48b : OpcodeHexagon {
280  bits <5> Rt32;
281  let Inst{20-16} = Rt32{4-0};
282  bits <1> Mu2;
283  let Inst{13-13} = Mu2{0-0};
284  bits <5> Vv32;
285  let Inst{12-8} = Vv32{4-0};
286  bits <5> Vw32;
287  let Inst{4-0} = Vw32{4-0};
288}
289class Enc_178717 : OpcodeHexagon {
290  bits <11> Ii;
291  let Inst{21-20} = Ii{10-9};
292  let Inst{7-1} = Ii{8-2};
293  bits <4> Rs16;
294  let Inst{19-16} = Rs16{3-0};
295  bits <6> n1;
296  let Inst{28-28} = n1{5-5};
297  let Inst{25-23} = n1{4-2};
298  let Inst{13-13} = n1{1-1};
299  let Inst{8-8} = n1{0-0};
300}
301class Enc_179b35 : OpcodeHexagon {
302  bits <5> Rs32;
303  let Inst{20-16} = Rs32{4-0};
304  bits <5> Rtt32;
305  let Inst{12-8} = Rtt32{4-0};
306  bits <5> Rx32;
307  let Inst{4-0} = Rx32{4-0};
308}
309class Enc_18c338 : OpcodeHexagon {
310  bits <8> Ii;
311  let Inst{12-5} = Ii{7-0};
312  bits <8> II;
313  let Inst{22-16} = II{7-1};
314  let Inst{13-13} = II{0-0};
315  bits <5> Rdd32;
316  let Inst{4-0} = Rdd32{4-0};
317}
318class Enc_1a9974 : OpcodeHexagon {
319  bits <2> Ii;
320  let Inst{13-13} = Ii{1-1};
321  let Inst{7-7} = Ii{0-0};
322  bits <2> Pv4;
323  let Inst{6-5} = Pv4{1-0};
324  bits <5> Rs32;
325  let Inst{20-16} = Rs32{4-0};
326  bits <5> Ru32;
327  let Inst{12-8} = Ru32{4-0};
328  bits <5> Rtt32;
329  let Inst{4-0} = Rtt32{4-0};
330}
331class Enc_1aa186 : OpcodeHexagon {
332  bits <5> Rss32;
333  let Inst{20-16} = Rss32{4-0};
334  bits <5> Rt32;
335  let Inst{12-8} = Rt32{4-0};
336  bits <5> Rxx32;
337  let Inst{4-0} = Rxx32{4-0};
338}
339class Enc_1aaec1 : OpcodeHexagon {
340  bits <3> Ii;
341  let Inst{10-8} = Ii{2-0};
342  bits <3> Os8;
343  let Inst{2-0} = Os8{2-0};
344  bits <5> Rx32;
345  let Inst{20-16} = Rx32{4-0};
346}
347class Enc_1b64fb : OpcodeHexagon {
348  bits <16> Ii;
349  let Inst{26-25} = Ii{15-14};
350  let Inst{20-16} = Ii{13-9};
351  let Inst{13-13} = Ii{8-8};
352  let Inst{7-0} = Ii{7-0};
353  bits <5> Rt32;
354  let Inst{12-8} = Rt32{4-0};
355}
356class Enc_1bd127 : OpcodeHexagon {
357  bits <5> Vu32;
358  let Inst{12-8} = Vu32{4-0};
359  bits <3> Rt8;
360  let Inst{18-16} = Rt8{2-0};
361  bits <5> Vdddd32;
362  let Inst{4-0} = Vdddd32{4-0};
363}
364class Enc_1cf4ca : OpcodeHexagon {
365  bits <6> Ii;
366  let Inst{17-16} = Ii{5-4};
367  let Inst{6-3} = Ii{3-0};
368  bits <2> Pv4;
369  let Inst{1-0} = Pv4{1-0};
370  bits <5> Rt32;
371  let Inst{12-8} = Rt32{4-0};
372}
373class Enc_1de724 : OpcodeHexagon {
374  bits <11> Ii;
375  let Inst{21-20} = Ii{10-9};
376  let Inst{7-1} = Ii{8-2};
377  bits <4> Rs16;
378  let Inst{19-16} = Rs16{3-0};
379  bits <4> n1;
380  let Inst{28-28} = n1{3-3};
381  let Inst{24-22} = n1{2-0};
382}
383class Enc_1ef990 : OpcodeHexagon {
384  bits <2> Pv4;
385  let Inst{12-11} = Pv4{1-0};
386  bits <1> Mu2;
387  let Inst{13-13} = Mu2{0-0};
388  bits <5> Vs32;
389  let Inst{4-0} = Vs32{4-0};
390  bits <5> Rx32;
391  let Inst{20-16} = Rx32{4-0};
392}
393class Enc_1f19b5 : OpcodeHexagon {
394  bits <5> Ii;
395  let Inst{9-5} = Ii{4-0};
396  bits <5> Rss32;
397  let Inst{20-16} = Rss32{4-0};
398  bits <2> Pd4;
399  let Inst{1-0} = Pd4{1-0};
400}
401class Enc_1f5ba6 : OpcodeHexagon {
402  bits <4> Rd16;
403  let Inst{3-0} = Rd16{3-0};
404}
405class Enc_1f5d8f : OpcodeHexagon {
406  bits <1> Mu2;
407  let Inst{13-13} = Mu2{0-0};
408  bits <5> Ryy32;
409  let Inst{4-0} = Ryy32{4-0};
410  bits <5> Rx32;
411  let Inst{20-16} = Rx32{4-0};
412}
413class Enc_211aaa : OpcodeHexagon {
414  bits <11> Ii;
415  let Inst{26-25} = Ii{10-9};
416  let Inst{13-5} = Ii{8-0};
417  bits <5> Rs32;
418  let Inst{20-16} = Rs32{4-0};
419  bits <5> Rd32;
420  let Inst{4-0} = Rd32{4-0};
421}
422class Enc_217147 : OpcodeHexagon {
423  bits <2> Qv4;
424  let Inst{23-22} = Qv4{1-0};
425}
426class Enc_222336 : OpcodeHexagon {
427  bits <4> Ii;
428  let Inst{8-5} = Ii{3-0};
429  bits <5> Rd32;
430  let Inst{4-0} = Rd32{4-0};
431  bits <5> Rx32;
432  let Inst{20-16} = Rx32{4-0};
433}
434class Enc_223005 : OpcodeHexagon {
435  bits <6> Ii;
436  let Inst{6-3} = Ii{5-2};
437  bits <3> Nt8;
438  let Inst{10-8} = Nt8{2-0};
439  bits <5> Rx32;
440  let Inst{20-16} = Rx32{4-0};
441}
442class Enc_226535 : OpcodeHexagon {
443  bits <8> Ii;
444  let Inst{12-7} = Ii{7-2};
445  bits <5> Rs32;
446  let Inst{20-16} = Rs32{4-0};
447  bits <5> Rt32;
448  let Inst{4-0} = Rt32{4-0};
449}
450class Enc_22c845 : OpcodeHexagon {
451  bits <14> Ii;
452  let Inst{10-0} = Ii{13-3};
453  bits <5> Rx32;
454  let Inst{20-16} = Rx32{4-0};
455}
456class Enc_2301d6 : OpcodeHexagon {
457  bits <6> Ii;
458  let Inst{20-16} = Ii{5-1};
459  let Inst{8-8} = Ii{0-0};
460  bits <2> Pt4;
461  let Inst{10-9} = Pt4{1-0};
462  bits <5> Rd32;
463  let Inst{4-0} = Rd32{4-0};
464}
465class Enc_245865 : OpcodeHexagon {
466  bits <5> Vu32;
467  let Inst{12-8} = Vu32{4-0};
468  bits <5> Vv32;
469  let Inst{23-19} = Vv32{4-0};
470  bits <3> Rt8;
471  let Inst{18-16} = Rt8{2-0};
472  bits <5> Vx32;
473  let Inst{4-0} = Vx32{4-0};
474}
475class Enc_24a7dc : OpcodeHexagon {
476  bits <5> Vu32;
477  let Inst{12-8} = Vu32{4-0};
478  bits <5> Vv32;
479  let Inst{23-19} = Vv32{4-0};
480  bits <3> Rt8;
481  let Inst{18-16} = Rt8{2-0};
482  bits <5> Vdd32;
483  let Inst{4-0} = Vdd32{4-0};
484}
485class Enc_25bef0 : OpcodeHexagon {
486  bits <16> Ii;
487  let Inst{26-25} = Ii{15-14};
488  let Inst{20-16} = Ii{13-9};
489  let Inst{13-5} = Ii{8-0};
490  bits <5> Rd32;
491  let Inst{4-0} = Rd32{4-0};
492}
493class Enc_263841 : OpcodeHexagon {
494  bits <5> Vu32;
495  let Inst{12-8} = Vu32{4-0};
496  bits <5> Rtt32;
497  let Inst{20-16} = Rtt32{4-0};
498  bits <5> Vd32;
499  let Inst{4-0} = Vd32{4-0};
500}
501class Enc_277737 : OpcodeHexagon {
502  bits <8> Ii;
503  let Inst{22-21} = Ii{7-6};
504  let Inst{13-13} = Ii{5-5};
505  let Inst{7-5} = Ii{4-2};
506  bits <5> Ru32;
507  let Inst{4-0} = Ru32{4-0};
508  bits <5> Rs32;
509  let Inst{20-16} = Rs32{4-0};
510  bits <5> Rd32;
511  let Inst{12-8} = Rd32{4-0};
512}
513class Enc_27b757 : OpcodeHexagon {
514  bits <4> Ii;
515  let Inst{13-13} = Ii{3-3};
516  let Inst{10-8} = Ii{2-0};
517  bits <2> Pv4;
518  let Inst{12-11} = Pv4{1-0};
519  bits <5> Rt32;
520  let Inst{20-16} = Rt32{4-0};
521  bits <5> Vs32;
522  let Inst{4-0} = Vs32{4-0};
523}
524class Enc_27fd0e : OpcodeHexagon {
525  bits <6> Ii;
526  let Inst{8-5} = Ii{5-2};
527  bits <1> Mu2;
528  let Inst{13-13} = Mu2{0-0};
529  bits <5> Rd32;
530  let Inst{4-0} = Rd32{4-0};
531  bits <5> Rx32;
532  let Inst{20-16} = Rx32{4-0};
533}
534class Enc_284ebb : OpcodeHexagon {
535  bits <2> Ps4;
536  let Inst{17-16} = Ps4{1-0};
537  bits <2> Pt4;
538  let Inst{9-8} = Pt4{1-0};
539  bits <2> Pd4;
540  let Inst{1-0} = Pd4{1-0};
541}
542class Enc_28a2dc : OpcodeHexagon {
543  bits <5> Ii;
544  let Inst{12-8} = Ii{4-0};
545  bits <5> Rs32;
546  let Inst{20-16} = Rs32{4-0};
547  bits <5> Rx32;
548  let Inst{4-0} = Rx32{4-0};
549}
550class Enc_28dcbb : OpcodeHexagon {
551  bits <5> Rt32;
552  let Inst{20-16} = Rt32{4-0};
553  bits <1> Mu2;
554  let Inst{13-13} = Mu2{0-0};
555  bits <5> Vvv32;
556  let Inst{4-0} = Vvv32{4-0};
557}
558class Enc_2a3787 : OpcodeHexagon {
559  bits <13> Ii;
560  let Inst{26-25} = Ii{12-11};
561  let Inst{13-5} = Ii{10-2};
562  bits <5> Rs32;
563  let Inst{20-16} = Rs32{4-0};
564  bits <5> Rd32;
565  let Inst{4-0} = Rd32{4-0};
566}
567class Enc_2a7b91 : OpcodeHexagon {
568  bits <6> Ii;
569  let Inst{20-16} = Ii{5-1};
570  let Inst{8-8} = Ii{0-0};
571  bits <2> Pt4;
572  let Inst{10-9} = Pt4{1-0};
573  bits <5> Rdd32;
574  let Inst{4-0} = Rdd32{4-0};
575}
576class Enc_2ae154 : OpcodeHexagon {
577  bits <5> Rs32;
578  let Inst{20-16} = Rs32{4-0};
579  bits <5> Rt32;
580  let Inst{12-8} = Rt32{4-0};
581  bits <5> Rx32;
582  let Inst{4-0} = Rx32{4-0};
583}
584class Enc_2b3f60 : OpcodeHexagon {
585  bits <5> Rss32;
586  let Inst{20-16} = Rss32{4-0};
587  bits <5> Rtt32;
588  let Inst{12-8} = Rtt32{4-0};
589  bits <5> Rdd32;
590  let Inst{4-0} = Rdd32{4-0};
591  bits <2> Px4;
592  let Inst{6-5} = Px4{1-0};
593}
594class Enc_2b518f : OpcodeHexagon {
595  bits <32> Ii;
596  let Inst{27-16} = Ii{31-20};
597  let Inst{13-0} = Ii{19-6};
598}
599class Enc_2bae10 : OpcodeHexagon {
600  bits <4> Ii;
601  let Inst{10-8} = Ii{3-1};
602  bits <4> Rs16;
603  let Inst{7-4} = Rs16{3-0};
604  bits <4> Rd16;
605  let Inst{3-0} = Rd16{3-0};
606}
607class Enc_2d7491 : OpcodeHexagon {
608  bits <13> Ii;
609  let Inst{26-25} = Ii{12-11};
610  let Inst{13-5} = Ii{10-2};
611  bits <5> Rs32;
612  let Inst{20-16} = Rs32{4-0};
613  bits <5> Rdd32;
614  let Inst{4-0} = Rdd32{4-0};
615}
616class Enc_2d829e : OpcodeHexagon {
617  bits <14> Ii;
618  let Inst{10-0} = Ii{13-3};
619  bits <5> Rs32;
620  let Inst{20-16} = Rs32{4-0};
621}
622class Enc_2df31d : OpcodeHexagon {
623  bits <8> Ii;
624  let Inst{9-4} = Ii{7-2};
625  bits <4> Rd16;
626  let Inst{3-0} = Rd16{3-0};
627}
628class Enc_2e1979 : OpcodeHexagon {
629  bits <2> Ii;
630  let Inst{13-13} = Ii{1-1};
631  let Inst{7-7} = Ii{0-0};
632  bits <2> Pv4;
633  let Inst{6-5} = Pv4{1-0};
634  bits <5> Rs32;
635  let Inst{20-16} = Rs32{4-0};
636  bits <5> Rt32;
637  let Inst{12-8} = Rt32{4-0};
638  bits <5> Rd32;
639  let Inst{4-0} = Rd32{4-0};
640}
641class Enc_2ea740 : OpcodeHexagon {
642  bits <4> Ii;
643  let Inst{13-13} = Ii{3-3};
644  let Inst{10-8} = Ii{2-0};
645  bits <2> Qv4;
646  let Inst{12-11} = Qv4{1-0};
647  bits <5> Rt32;
648  let Inst{20-16} = Rt32{4-0};
649  bits <5> Vs32;
650  let Inst{4-0} = Vs32{4-0};
651}
652class Enc_2ebe3b : OpcodeHexagon {
653  bits <1> Mu2;
654  let Inst{13-13} = Mu2{0-0};
655  bits <5> Vd32;
656  let Inst{4-0} = Vd32{4-0};
657  bits <5> Rx32;
658  let Inst{20-16} = Rx32{4-0};
659}
660class Enc_2f2f04 : OpcodeHexagon {
661  bits <1> Ii;
662  let Inst{5-5} = Ii{0-0};
663  bits <5> Vuu32;
664  let Inst{12-8} = Vuu32{4-0};
665  bits <5> Rt32;
666  let Inst{20-16} = Rt32{4-0};
667  bits <5> Vdd32;
668  let Inst{4-0} = Vdd32{4-0};
669}
670class Enc_2fbf3c : OpcodeHexagon {
671  bits <3> Ii;
672  let Inst{10-8} = Ii{2-0};
673  bits <4> Rs16;
674  let Inst{7-4} = Rs16{3-0};
675  bits <4> Rd16;
676  let Inst{3-0} = Rd16{3-0};
677}
678class Enc_310ba1 : OpcodeHexagon {
679  bits <5> Vu32;
680  let Inst{12-8} = Vu32{4-0};
681  bits <5> Rtt32;
682  let Inst{20-16} = Rtt32{4-0};
683  bits <5> Vx32;
684  let Inst{4-0} = Vx32{4-0};
685}
686class Enc_311abd : OpcodeHexagon {
687  bits <5> Ii;
688  let Inst{12-8} = Ii{4-0};
689  bits <5> Rs32;
690  let Inst{20-16} = Rs32{4-0};
691  bits <5> Rdd32;
692  let Inst{4-0} = Rdd32{4-0};
693}
694class Enc_31aa6a : OpcodeHexagon {
695  bits <5> Ii;
696  let Inst{6-3} = Ii{4-1};
697  bits <2> Pv4;
698  let Inst{1-0} = Pv4{1-0};
699  bits <3> Nt8;
700  let Inst{10-8} = Nt8{2-0};
701  bits <5> Rx32;
702  let Inst{20-16} = Rx32{4-0};
703}
704class Enc_31db33 : OpcodeHexagon {
705  bits <2> Qt4;
706  let Inst{6-5} = Qt4{1-0};
707  bits <5> Vu32;
708  let Inst{12-8} = Vu32{4-0};
709  bits <5> Vv32;
710  let Inst{20-16} = Vv32{4-0};
711  bits <5> Vd32;
712  let Inst{4-0} = Vd32{4-0};
713}
714class Enc_322e1b : OpcodeHexagon {
715  bits <6> Ii;
716  let Inst{22-21} = Ii{5-4};
717  let Inst{13-13} = Ii{3-3};
718  let Inst{7-5} = Ii{2-0};
719  bits <6> II;
720  let Inst{23-23} = II{5-5};
721  let Inst{4-0} = II{4-0};
722  bits <5> Rs32;
723  let Inst{20-16} = Rs32{4-0};
724  bits <5> Rd32;
725  let Inst{12-8} = Rd32{4-0};
726}
727class Enc_323f2d : OpcodeHexagon {
728  bits <6> II;
729  let Inst{11-8} = II{5-2};
730  let Inst{6-5} = II{1-0};
731  bits <5> Rd32;
732  let Inst{4-0} = Rd32{4-0};
733  bits <5> Re32;
734  let Inst{20-16} = Re32{4-0};
735}
736class Enc_329361 : OpcodeHexagon {
737  bits <2> Pu4;
738  let Inst{6-5} = Pu4{1-0};
739  bits <5> Rss32;
740  let Inst{20-16} = Rss32{4-0};
741  bits <5> Rtt32;
742  let Inst{12-8} = Rtt32{4-0};
743  bits <5> Rdd32;
744  let Inst{4-0} = Rdd32{4-0};
745}
746class Enc_33f8ba : OpcodeHexagon {
747  bits <8> Ii;
748  let Inst{12-8} = Ii{7-3};
749  let Inst{4-2} = Ii{2-0};
750  bits <5> Rx32;
751  let Inst{20-16} = Rx32{4-0};
752}
753class Enc_3680c2 : OpcodeHexagon {
754  bits <7> Ii;
755  let Inst{11-5} = Ii{6-0};
756  bits <5> Rss32;
757  let Inst{20-16} = Rss32{4-0};
758  bits <2> Pd4;
759  let Inst{1-0} = Pd4{1-0};
760}
761class Enc_3694bd : OpcodeHexagon {
762  bits <11> Ii;
763  let Inst{21-20} = Ii{10-9};
764  let Inst{7-1} = Ii{8-2};
765  bits <3> Ns8;
766  let Inst{18-16} = Ns8{2-0};
767  bits <5> n1;
768  let Inst{29-29} = n1{4-4};
769  let Inst{26-25} = n1{3-2};
770  let Inst{23-22} = n1{1-0};
771}
772class Enc_372c9d : OpcodeHexagon {
773  bits <2> Pv4;
774  let Inst{12-11} = Pv4{1-0};
775  bits <1> Mu2;
776  let Inst{13-13} = Mu2{0-0};
777  bits <3> Os8;
778  let Inst{2-0} = Os8{2-0};
779  bits <5> Rx32;
780  let Inst{20-16} = Rx32{4-0};
781}
782class Enc_395cc4 : OpcodeHexagon {
783  bits <7> Ii;
784  let Inst{6-3} = Ii{6-3};
785  bits <1> Mu2;
786  let Inst{13-13} = Mu2{0-0};
787  bits <5> Rtt32;
788  let Inst{12-8} = Rtt32{4-0};
789  bits <5> Rx32;
790  let Inst{20-16} = Rx32{4-0};
791}
792class Enc_397f23 : OpcodeHexagon {
793  bits <8> Ii;
794  let Inst{13-13} = Ii{7-7};
795  let Inst{7-3} = Ii{6-2};
796  bits <2> Pv4;
797  let Inst{1-0} = Pv4{1-0};
798  bits <5> Rs32;
799  let Inst{20-16} = Rs32{4-0};
800  bits <5> Rt32;
801  let Inst{12-8} = Rt32{4-0};
802}
803class Enc_399e12 : OpcodeHexagon {
804  bits <4> Rs16;
805  let Inst{7-4} = Rs16{3-0};
806  bits <3> Rdd8;
807  let Inst{2-0} = Rdd8{2-0};
808}
809class Enc_3a2484 : OpcodeHexagon {
810  bits <11> Ii;
811  let Inst{21-20} = Ii{10-9};
812  let Inst{7-1} = Ii{8-2};
813  bits <4> Rs16;
814  let Inst{19-16} = Rs16{3-0};
815  bits <4> n1;
816  let Inst{28-28} = n1{3-3};
817  let Inst{24-23} = n1{2-1};
818  let Inst{13-13} = n1{0-0};
819}
820class Enc_3a3d62 : OpcodeHexagon {
821  bits <5> Rs32;
822  let Inst{20-16} = Rs32{4-0};
823  bits <5> Rdd32;
824  let Inst{4-0} = Rdd32{4-0};
825}
826class Enc_3b7631 : OpcodeHexagon {
827  bits <5> Vu32;
828  let Inst{12-8} = Vu32{4-0};
829  bits <5> Vdddd32;
830  let Inst{4-0} = Vdddd32{4-0};
831  bits <3> Rx8;
832  let Inst{18-16} = Rx8{2-0};
833}
834class Enc_3d5b28 : OpcodeHexagon {
835  bits <5> Rss32;
836  let Inst{20-16} = Rss32{4-0};
837  bits <5> Rt32;
838  let Inst{12-8} = Rt32{4-0};
839  bits <5> Rd32;
840  let Inst{4-0} = Rd32{4-0};
841}
842class Enc_3d6d37 : OpcodeHexagon {
843  bits <2> Qs4;
844  let Inst{6-5} = Qs4{1-0};
845  bits <5> Rt32;
846  let Inst{20-16} = Rt32{4-0};
847  bits <1> Mu2;
848  let Inst{13-13} = Mu2{0-0};
849  bits <5> Vvv32;
850  let Inst{12-8} = Vvv32{4-0};
851  bits <5> Vw32;
852  let Inst{4-0} = Vw32{4-0};
853}
854class Enc_3d920a : OpcodeHexagon {
855  bits <6> Ii;
856  let Inst{8-5} = Ii{5-2};
857  bits <5> Rd32;
858  let Inst{4-0} = Rd32{4-0};
859  bits <5> Rx32;
860  let Inst{20-16} = Rx32{4-0};
861}
862class Enc_3dac0b : OpcodeHexagon {
863  bits <2> Qt4;
864  let Inst{6-5} = Qt4{1-0};
865  bits <5> Vu32;
866  let Inst{12-8} = Vu32{4-0};
867  bits <5> Vv32;
868  let Inst{20-16} = Vv32{4-0};
869  bits <5> Vdd32;
870  let Inst{4-0} = Vdd32{4-0};
871}
872class Enc_3e3989 : OpcodeHexagon {
873  bits <11> Ii;
874  let Inst{21-20} = Ii{10-9};
875  let Inst{7-1} = Ii{8-2};
876  bits <4> Rs16;
877  let Inst{19-16} = Rs16{3-0};
878  bits <6> n1;
879  let Inst{28-28} = n1{5-5};
880  let Inst{25-22} = n1{4-1};
881  let Inst{8-8} = n1{0-0};
882}
883class Enc_3f97c8 : OpcodeHexagon {
884  bits <6> Ii;
885  let Inst{6-3} = Ii{5-2};
886  bits <1> Mu2;
887  let Inst{13-13} = Mu2{0-0};
888  bits <3> Nt8;
889  let Inst{10-8} = Nt8{2-0};
890  bits <5> Rx32;
891  let Inst{20-16} = Rx32{4-0};
892}
893class Enc_3fc427 : OpcodeHexagon {
894  bits <5> Vu32;
895  let Inst{12-8} = Vu32{4-0};
896  bits <5> Vv32;
897  let Inst{20-16} = Vv32{4-0};
898  bits <5> Vxx32;
899  let Inst{4-0} = Vxx32{4-0};
900}
901class Enc_405228 : OpcodeHexagon {
902  bits <11> Ii;
903  let Inst{21-20} = Ii{10-9};
904  let Inst{7-1} = Ii{8-2};
905  bits <4> Rs16;
906  let Inst{19-16} = Rs16{3-0};
907  bits <3> n1;
908  let Inst{28-28} = n1{2-2};
909  let Inst{24-23} = n1{1-0};
910}
911class Enc_412ff0 : OpcodeHexagon {
912  bits <5> Rss32;
913  let Inst{20-16} = Rss32{4-0};
914  bits <5> Ru32;
915  let Inst{4-0} = Ru32{4-0};
916  bits <5> Rxx32;
917  let Inst{12-8} = Rxx32{4-0};
918}
919class Enc_420cf3 : OpcodeHexagon {
920  bits <6> Ii;
921  let Inst{22-21} = Ii{5-4};
922  let Inst{13-13} = Ii{3-3};
923  let Inst{7-5} = Ii{2-0};
924  bits <5> Ru32;
925  let Inst{4-0} = Ru32{4-0};
926  bits <5> Rs32;
927  let Inst{20-16} = Rs32{4-0};
928  bits <5> Rd32;
929  let Inst{12-8} = Rd32{4-0};
930}
931class Enc_437f33 : OpcodeHexagon {
932  bits <5> Rs32;
933  let Inst{20-16} = Rs32{4-0};
934  bits <5> Rt32;
935  let Inst{12-8} = Rt32{4-0};
936  bits <2> Pu4;
937  let Inst{6-5} = Pu4{1-0};
938  bits <5> Rx32;
939  let Inst{4-0} = Rx32{4-0};
940}
941class Enc_44215c : OpcodeHexagon {
942  bits <6> Ii;
943  let Inst{17-16} = Ii{5-4};
944  let Inst{6-3} = Ii{3-0};
945  bits <2> Pv4;
946  let Inst{1-0} = Pv4{1-0};
947  bits <3> Nt8;
948  let Inst{10-8} = Nt8{2-0};
949}
950class Enc_44271f : OpcodeHexagon {
951  bits <5> Gs32;
952  let Inst{20-16} = Gs32{4-0};
953  bits <5> Rd32;
954  let Inst{4-0} = Rd32{4-0};
955}
956class Enc_44661f : OpcodeHexagon {
957  bits <1> Mu2;
958  let Inst{13-13} = Mu2{0-0};
959  bits <5> Rx32;
960  let Inst{20-16} = Rx32{4-0};
961}
962class Enc_448f7f : OpcodeHexagon {
963  bits <11> Ii;
964  let Inst{26-25} = Ii{10-9};
965  let Inst{13-13} = Ii{8-8};
966  let Inst{7-0} = Ii{7-0};
967  bits <5> Rs32;
968  let Inst{20-16} = Rs32{4-0};
969  bits <5> Rt32;
970  let Inst{12-8} = Rt32{4-0};
971}
972class Enc_45364e : OpcodeHexagon {
973  bits <5> Vu32;
974  let Inst{12-8} = Vu32{4-0};
975  bits <5> Vv32;
976  let Inst{20-16} = Vv32{4-0};
977  bits <5> Vd32;
978  let Inst{4-0} = Vd32{4-0};
979}
980class Enc_454a26 : OpcodeHexagon {
981  bits <2> Pt4;
982  let Inst{9-8} = Pt4{1-0};
983  bits <2> Ps4;
984  let Inst{17-16} = Ps4{1-0};
985  bits <2> Pd4;
986  let Inst{1-0} = Pd4{1-0};
987}
988class Enc_46c951 : OpcodeHexagon {
989  bits <6> Ii;
990  let Inst{12-7} = Ii{5-0};
991  bits <5> II;
992  let Inst{4-0} = II{4-0};
993  bits <5> Rs32;
994  let Inst{20-16} = Rs32{4-0};
995}
996class Enc_47ee5e : OpcodeHexagon {
997  bits <2> Ii;
998  let Inst{13-13} = Ii{1-1};
999  let Inst{7-7} = Ii{0-0};
1000  bits <2> Pv4;
1001  let Inst{6-5} = Pv4{1-0};
1002  bits <5> Rs32;
1003  let Inst{20-16} = Rs32{4-0};
1004  bits <5> Ru32;
1005  let Inst{12-8} = Ru32{4-0};
1006  bits <3> Nt8;
1007  let Inst{2-0} = Nt8{2-0};
1008}
1009class Enc_47ef61 : OpcodeHexagon {
1010  bits <3> Ii;
1011  let Inst{7-5} = Ii{2-0};
1012  bits <5> Rt32;
1013  let Inst{12-8} = Rt32{4-0};
1014  bits <5> Rs32;
1015  let Inst{20-16} = Rs32{4-0};
1016  bits <5> Rd32;
1017  let Inst{4-0} = Rd32{4-0};
1018}
1019class Enc_48b75f : OpcodeHexagon {
1020  bits <5> Rs32;
1021  let Inst{20-16} = Rs32{4-0};
1022  bits <2> Pd4;
1023  let Inst{1-0} = Pd4{1-0};
1024}
1025class Enc_4aca3a : OpcodeHexagon {
1026  bits <11> Ii;
1027  let Inst{21-20} = Ii{10-9};
1028  let Inst{7-1} = Ii{8-2};
1029  bits <3> Ns8;
1030  let Inst{18-16} = Ns8{2-0};
1031  bits <3> n1;
1032  let Inst{29-29} = n1{2-2};
1033  let Inst{26-25} = n1{1-0};
1034}
1035class Enc_4b39e4 : OpcodeHexagon {
1036  bits <3> Ii;
1037  let Inst{7-5} = Ii{2-0};
1038  bits <5> Vu32;
1039  let Inst{12-8} = Vu32{4-0};
1040  bits <5> Vv32;
1041  let Inst{20-16} = Vv32{4-0};
1042  bits <5> Vdd32;
1043  let Inst{4-0} = Vdd32{4-0};
1044}
1045class Enc_4dc228 : OpcodeHexagon {
1046  bits <9> Ii;
1047  let Inst{12-8} = Ii{8-4};
1048  let Inst{4-3} = Ii{3-2};
1049  bits <10> II;
1050  let Inst{20-16} = II{9-5};
1051  let Inst{7-5} = II{4-2};
1052  let Inst{1-0} = II{1-0};
1053}
1054class Enc_4df4e9 : OpcodeHexagon {
1055  bits <11> Ii;
1056  let Inst{26-25} = Ii{10-9};
1057  let Inst{13-13} = Ii{8-8};
1058  let Inst{7-0} = Ii{7-0};
1059  bits <5> Rs32;
1060  let Inst{20-16} = Rs32{4-0};
1061  bits <3> Nt8;
1062  let Inst{10-8} = Nt8{2-0};
1063}
1064class Enc_4dff07 : OpcodeHexagon {
1065  bits <2> Qv4;
1066  let Inst{12-11} = Qv4{1-0};
1067  bits <1> Mu2;
1068  let Inst{13-13} = Mu2{0-0};
1069  bits <5> Vs32;
1070  let Inst{4-0} = Vs32{4-0};
1071  bits <5> Rx32;
1072  let Inst{20-16} = Rx32{4-0};
1073}
1074class Enc_4e4a80 : OpcodeHexagon {
1075  bits <2> Qs4;
1076  let Inst{6-5} = Qs4{1-0};
1077  bits <5> Rt32;
1078  let Inst{20-16} = Rt32{4-0};
1079  bits <1> Mu2;
1080  let Inst{13-13} = Mu2{0-0};
1081  bits <5> Vvv32;
1082  let Inst{4-0} = Vvv32{4-0};
1083}
1084class Enc_4f4ed7 : OpcodeHexagon {
1085  bits <18> Ii;
1086  let Inst{26-25} = Ii{17-16};
1087  let Inst{20-16} = Ii{15-11};
1088  let Inst{13-5} = Ii{10-2};
1089  bits <5> Rd32;
1090  let Inst{4-0} = Rd32{4-0};
1091}
1092class Enc_4f677b : OpcodeHexagon {
1093  bits <2> Ii;
1094  let Inst{13-13} = Ii{1-1};
1095  let Inst{7-7} = Ii{0-0};
1096  bits <6> II;
1097  let Inst{11-8} = II{5-2};
1098  let Inst{6-5} = II{1-0};
1099  bits <5> Rt32;
1100  let Inst{20-16} = Rt32{4-0};
1101  bits <5> Rd32;
1102  let Inst{4-0} = Rd32{4-0};
1103}
1104class Enc_500cb0 : OpcodeHexagon {
1105  bits <5> Vu32;
1106  let Inst{12-8} = Vu32{4-0};
1107  bits <5> Vxx32;
1108  let Inst{4-0} = Vxx32{4-0};
1109}
1110class Enc_509701 : OpcodeHexagon {
1111  bits <19> Ii;
1112  let Inst{26-25} = Ii{18-17};
1113  let Inst{20-16} = Ii{16-12};
1114  let Inst{13-5} = Ii{11-3};
1115  bits <5> Rdd32;
1116  let Inst{4-0} = Rdd32{4-0};
1117}
1118class Enc_50b5ac : OpcodeHexagon {
1119  bits <6> Ii;
1120  let Inst{17-16} = Ii{5-4};
1121  let Inst{6-3} = Ii{3-0};
1122  bits <2> Pv4;
1123  let Inst{1-0} = Pv4{1-0};
1124  bits <5> Rtt32;
1125  let Inst{12-8} = Rtt32{4-0};
1126}
1127class Enc_50e578 : OpcodeHexagon {
1128  bits <5> Vu32;
1129  let Inst{12-8} = Vu32{4-0};
1130  bits <5> Rs32;
1131  let Inst{20-16} = Rs32{4-0};
1132  bits <5> Rd32;
1133  let Inst{4-0} = Rd32{4-0};
1134}
1135class Enc_5138b3 : OpcodeHexagon {
1136  bits <5> Vu32;
1137  let Inst{12-8} = Vu32{4-0};
1138  bits <5> Rt32;
1139  let Inst{20-16} = Rt32{4-0};
1140  bits <5> Vx32;
1141  let Inst{4-0} = Vx32{4-0};
1142}
1143class Enc_51436c : OpcodeHexagon {
1144  bits <16> Ii;
1145  let Inst{23-22} = Ii{15-14};
1146  let Inst{13-0} = Ii{13-0};
1147  bits <5> Rx32;
1148  let Inst{20-16} = Rx32{4-0};
1149}
1150class Enc_51635c : OpcodeHexagon {
1151  bits <7> Ii;
1152  let Inst{8-4} = Ii{6-2};
1153  bits <4> Rd16;
1154  let Inst{3-0} = Rd16{3-0};
1155}
1156class Enc_527412 : OpcodeHexagon {
1157  bits <2> Ps4;
1158  let Inst{17-16} = Ps4{1-0};
1159  bits <2> Pt4;
1160  let Inst{9-8} = Pt4{1-0};
1161  bits <5> Rd32;
1162  let Inst{4-0} = Rd32{4-0};
1163}
1164class Enc_52a5dd : OpcodeHexagon {
1165  bits <4> Ii;
1166  let Inst{6-3} = Ii{3-0};
1167  bits <2> Pv4;
1168  let Inst{1-0} = Pv4{1-0};
1169  bits <3> Nt8;
1170  let Inst{10-8} = Nt8{2-0};
1171  bits <5> Rx32;
1172  let Inst{20-16} = Rx32{4-0};
1173}
1174class Enc_53dca9 : OpcodeHexagon {
1175  bits <6> Ii;
1176  let Inst{11-8} = Ii{5-2};
1177  bits <4> Rs16;
1178  let Inst{7-4} = Rs16{3-0};
1179  bits <4> Rd16;
1180  let Inst{3-0} = Rd16{3-0};
1181}
1182class Enc_541f26 : OpcodeHexagon {
1183  bits <18> Ii;
1184  let Inst{26-25} = Ii{17-16};
1185  let Inst{20-16} = Ii{15-11};
1186  let Inst{13-13} = Ii{10-10};
1187  let Inst{7-0} = Ii{9-2};
1188  bits <5> Rt32;
1189  let Inst{12-8} = Rt32{4-0};
1190}
1191class Enc_55355c : OpcodeHexagon {
1192  bits <2> Ii;
1193  let Inst{13-13} = Ii{1-1};
1194  let Inst{7-7} = Ii{0-0};
1195  bits <5> Rs32;
1196  let Inst{20-16} = Rs32{4-0};
1197  bits <5> Ru32;
1198  let Inst{12-8} = Ru32{4-0};
1199  bits <5> Rtt32;
1200  let Inst{4-0} = Rtt32{4-0};
1201}
1202class Enc_569cfe : OpcodeHexagon {
1203  bits <5> Rt32;
1204  let Inst{20-16} = Rt32{4-0};
1205  bits <5> Vx32;
1206  let Inst{4-0} = Vx32{4-0};
1207}
1208class Enc_57a33e : OpcodeHexagon {
1209  bits <9> Ii;
1210  let Inst{13-13} = Ii{8-8};
1211  let Inst{7-3} = Ii{7-3};
1212  bits <2> Pv4;
1213  let Inst{1-0} = Pv4{1-0};
1214  bits <5> Rs32;
1215  let Inst{20-16} = Rs32{4-0};
1216  bits <5> Rtt32;
1217  let Inst{12-8} = Rtt32{4-0};
1218}
1219class Enc_585242 : OpcodeHexagon {
1220  bits <6> Ii;
1221  let Inst{13-13} = Ii{5-5};
1222  let Inst{7-3} = Ii{4-0};
1223  bits <2> Pv4;
1224  let Inst{1-0} = Pv4{1-0};
1225  bits <5> Rs32;
1226  let Inst{20-16} = Rs32{4-0};
1227  bits <3> Nt8;
1228  let Inst{10-8} = Nt8{2-0};
1229}
1230class Enc_58a8bf : OpcodeHexagon {
1231  bits <3> Ii;
1232  let Inst{10-8} = Ii{2-0};
1233  bits <2> Pv4;
1234  let Inst{12-11} = Pv4{1-0};
1235  bits <5> Vd32;
1236  let Inst{4-0} = Vd32{4-0};
1237  bits <5> Rx32;
1238  let Inst{20-16} = Rx32{4-0};
1239}
1240class Enc_5a18b3 : OpcodeHexagon {
1241  bits <11> Ii;
1242  let Inst{21-20} = Ii{10-9};
1243  let Inst{7-1} = Ii{8-2};
1244  bits <3> Ns8;
1245  let Inst{18-16} = Ns8{2-0};
1246  bits <5> n1;
1247  let Inst{29-29} = n1{4-4};
1248  let Inst{26-25} = n1{3-2};
1249  let Inst{22-22} = n1{1-1};
1250  let Inst{13-13} = n1{0-0};
1251}
1252class Enc_5ab2be : OpcodeHexagon {
1253  bits <5> Rs32;
1254  let Inst{20-16} = Rs32{4-0};
1255  bits <5> Rt32;
1256  let Inst{12-8} = Rt32{4-0};
1257  bits <5> Rd32;
1258  let Inst{4-0} = Rd32{4-0};
1259}
1260class Enc_5bdd42 : OpcodeHexagon {
1261  bits <7> Ii;
1262  let Inst{8-5} = Ii{6-3};
1263  bits <5> Rdd32;
1264  let Inst{4-0} = Rdd32{4-0};
1265  bits <5> Rx32;
1266  let Inst{20-16} = Rx32{4-0};
1267}
1268class Enc_5c124a : OpcodeHexagon {
1269  bits <19> Ii;
1270  let Inst{26-25} = Ii{18-17};
1271  let Inst{20-16} = Ii{16-12};
1272  let Inst{13-13} = Ii{11-11};
1273  let Inst{7-0} = Ii{10-3};
1274  bits <5> Rtt32;
1275  let Inst{12-8} = Rtt32{4-0};
1276}
1277class Enc_5ccba9 : OpcodeHexagon {
1278  bits <8> Ii;
1279  let Inst{12-7} = Ii{7-2};
1280  bits <6> II;
1281  let Inst{13-13} = II{5-5};
1282  let Inst{4-0} = II{4-0};
1283  bits <2> Pv4;
1284  let Inst{6-5} = Pv4{1-0};
1285  bits <5> Rs32;
1286  let Inst{20-16} = Rs32{4-0};
1287}
1288class Enc_5cd7e9 : OpcodeHexagon {
1289  bits <12> Ii;
1290  let Inst{26-25} = Ii{11-10};
1291  let Inst{13-5} = Ii{9-1};
1292  bits <5> Rs32;
1293  let Inst{20-16} = Rs32{4-0};
1294  bits <5> Ryy32;
1295  let Inst{4-0} = Ryy32{4-0};
1296}
1297class Enc_5d6c34 : OpcodeHexagon {
1298  bits <6> Ii;
1299  let Inst{13-8} = Ii{5-0};
1300  bits <5> Rs32;
1301  let Inst{20-16} = Rs32{4-0};
1302  bits <2> Pd4;
1303  let Inst{1-0} = Pd4{1-0};
1304}
1305class Enc_5de85f : OpcodeHexagon {
1306  bits <11> Ii;
1307  let Inst{21-20} = Ii{10-9};
1308  let Inst{7-1} = Ii{8-2};
1309  bits <5> Rt32;
1310  let Inst{12-8} = Rt32{4-0};
1311  bits <3> Ns8;
1312  let Inst{18-16} = Ns8{2-0};
1313}
1314class Enc_5e2823 : OpcodeHexagon {
1315  bits <5> Rs32;
1316  let Inst{20-16} = Rs32{4-0};
1317  bits <5> Rd32;
1318  let Inst{4-0} = Rd32{4-0};
1319}
1320class Enc_5e8512 : OpcodeHexagon {
1321  bits <5> Vu32;
1322  let Inst{12-8} = Vu32{4-0};
1323  bits <5> Rt32;
1324  let Inst{20-16} = Rt32{4-0};
1325  bits <5> Vxx32;
1326  let Inst{4-0} = Vxx32{4-0};
1327}
1328class Enc_5e87ce : OpcodeHexagon {
1329  bits <16> Ii;
1330  let Inst{23-22} = Ii{15-14};
1331  let Inst{20-16} = Ii{13-9};
1332  let Inst{13-5} = Ii{8-0};
1333  bits <5> Rd32;
1334  let Inst{4-0} = Rd32{4-0};
1335}
1336class Enc_5eac98 : OpcodeHexagon {
1337  bits <6> Ii;
1338  let Inst{13-8} = Ii{5-0};
1339  bits <5> Rss32;
1340  let Inst{20-16} = Rss32{4-0};
1341  bits <5> Rdd32;
1342  let Inst{4-0} = Rdd32{4-0};
1343}
1344class Enc_607661 : OpcodeHexagon {
1345  bits <6> Ii;
1346  let Inst{12-7} = Ii{5-0};
1347  bits <5> Rd32;
1348  let Inst{4-0} = Rd32{4-0};
1349}
1350class Enc_6185fe : OpcodeHexagon {
1351  bits <2> Ii;
1352  let Inst{13-13} = Ii{1-1};
1353  let Inst{7-7} = Ii{0-0};
1354  bits <6> II;
1355  let Inst{11-8} = II{5-2};
1356  let Inst{6-5} = II{1-0};
1357  bits <5> Rt32;
1358  let Inst{20-16} = Rt32{4-0};
1359  bits <5> Rdd32;
1360  let Inst{4-0} = Rdd32{4-0};
1361}
1362class Enc_61f0b0 : OpcodeHexagon {
1363  bits <5> Rs32;
1364  let Inst{20-16} = Rs32{4-0};
1365  bits <5> Rt32;
1366  let Inst{12-8} = Rt32{4-0};
1367  bits <5> Rxx32;
1368  let Inst{4-0} = Rxx32{4-0};
1369}
1370class Enc_621fba : OpcodeHexagon {
1371  bits <5> Rs32;
1372  let Inst{20-16} = Rs32{4-0};
1373  bits <5> Gd32;
1374  let Inst{4-0} = Gd32{4-0};
1375}
1376class Enc_625deb : OpcodeHexagon {
1377  bits <4> Ii;
1378  let Inst{10-8} = Ii{3-1};
1379  bits <4> Rs16;
1380  let Inst{7-4} = Rs16{3-0};
1381  bits <4> Rt16;
1382  let Inst{3-0} = Rt16{3-0};
1383}
1384class Enc_6339d5 : OpcodeHexagon {
1385  bits <2> Ii;
1386  let Inst{13-13} = Ii{1-1};
1387  let Inst{7-7} = Ii{0-0};
1388  bits <2> Pv4;
1389  let Inst{6-5} = Pv4{1-0};
1390  bits <5> Rs32;
1391  let Inst{20-16} = Rs32{4-0};
1392  bits <5> Ru32;
1393  let Inst{12-8} = Ru32{4-0};
1394  bits <5> Rt32;
1395  let Inst{4-0} = Rt32{4-0};
1396}
1397class Enc_63eaeb : OpcodeHexagon {
1398  bits <2> Ii;
1399  let Inst{1-0} = Ii{1-0};
1400  bits <4> Rs16;
1401  let Inst{7-4} = Rs16{3-0};
1402}
1403class Enc_6413b6 : OpcodeHexagon {
1404  bits <11> Ii;
1405  let Inst{21-20} = Ii{10-9};
1406  let Inst{7-1} = Ii{8-2};
1407  bits <3> Ns8;
1408  let Inst{18-16} = Ns8{2-0};
1409  bits <5> n1;
1410  let Inst{29-29} = n1{4-4};
1411  let Inst{26-25} = n1{3-2};
1412  let Inst{23-23} = n1{1-1};
1413  let Inst{13-13} = n1{0-0};
1414}
1415class Enc_645d54 : OpcodeHexagon {
1416  bits <2> Ii;
1417  let Inst{13-13} = Ii{1-1};
1418  let Inst{5-5} = Ii{0-0};
1419  bits <5> Rss32;
1420  let Inst{20-16} = Rss32{4-0};
1421  bits <5> Rt32;
1422  let Inst{12-8} = Rt32{4-0};
1423  bits <5> Rdd32;
1424  let Inst{4-0} = Rdd32{4-0};
1425}
1426class Enc_65d691 : OpcodeHexagon {
1427  bits <2> Ps4;
1428  let Inst{17-16} = Ps4{1-0};
1429  bits <2> Pd4;
1430  let Inst{1-0} = Pd4{1-0};
1431}
1432class Enc_65f095 : OpcodeHexagon {
1433  bits <6> Ii;
1434  let Inst{6-3} = Ii{5-2};
1435  bits <2> Pv4;
1436  let Inst{1-0} = Pv4{1-0};
1437  bits <3> Nt8;
1438  let Inst{10-8} = Nt8{2-0};
1439  bits <5> Rx32;
1440  let Inst{20-16} = Rx32{4-0};
1441}
1442class Enc_667b39 : OpcodeHexagon {
1443  bits <5> Css32;
1444  let Inst{20-16} = Css32{4-0};
1445  bits <5> Rdd32;
1446  let Inst{4-0} = Rdd32{4-0};
1447}
1448class Enc_668704 : OpcodeHexagon {
1449  bits <11> Ii;
1450  let Inst{21-20} = Ii{10-9};
1451  let Inst{7-1} = Ii{8-2};
1452  bits <4> Rs16;
1453  let Inst{19-16} = Rs16{3-0};
1454  bits <5> n1;
1455  let Inst{28-28} = n1{4-4};
1456  let Inst{25-22} = n1{3-0};
1457}
1458class Enc_66bce1 : OpcodeHexagon {
1459  bits <11> Ii;
1460  let Inst{21-20} = Ii{10-9};
1461  let Inst{7-1} = Ii{8-2};
1462  bits <4> Rs16;
1463  let Inst{19-16} = Rs16{3-0};
1464  bits <4> Rd16;
1465  let Inst{11-8} = Rd16{3-0};
1466}
1467class Enc_690862 : OpcodeHexagon {
1468  bits <13> Ii;
1469  let Inst{26-25} = Ii{12-11};
1470  let Inst{13-13} = Ii{10-10};
1471  let Inst{7-0} = Ii{9-2};
1472  bits <5> Rs32;
1473  let Inst{20-16} = Rs32{4-0};
1474  bits <3> Nt8;
1475  let Inst{10-8} = Nt8{2-0};
1476}
1477class Enc_691712 : OpcodeHexagon {
1478  bits <2> Pv4;
1479  let Inst{12-11} = Pv4{1-0};
1480  bits <1> Mu2;
1481  let Inst{13-13} = Mu2{0-0};
1482  bits <5> Rx32;
1483  let Inst{20-16} = Rx32{4-0};
1484}
1485class Enc_69d63b : OpcodeHexagon {
1486  bits <11> Ii;
1487  let Inst{21-20} = Ii{10-9};
1488  let Inst{7-1} = Ii{8-2};
1489  bits <3> Ns8;
1490  let Inst{18-16} = Ns8{2-0};
1491}
1492class Enc_6a5972 : OpcodeHexagon {
1493  bits <11> Ii;
1494  let Inst{21-20} = Ii{10-9};
1495  let Inst{7-1} = Ii{8-2};
1496  bits <4> Rs16;
1497  let Inst{19-16} = Rs16{3-0};
1498  bits <4> Rt16;
1499  let Inst{11-8} = Rt16{3-0};
1500}
1501class Enc_6b197f : OpcodeHexagon {
1502  bits <4> Ii;
1503  let Inst{8-5} = Ii{3-0};
1504  bits <5> Ryy32;
1505  let Inst{4-0} = Ryy32{4-0};
1506  bits <5> Rx32;
1507  let Inst{20-16} = Rx32{4-0};
1508}
1509class Enc_6baed4 : OpcodeHexagon {
1510  bits <3> Ii;
1511  let Inst{10-8} = Ii{2-0};
1512  bits <2> Pv4;
1513  let Inst{12-11} = Pv4{1-0};
1514  bits <5> Rx32;
1515  let Inst{20-16} = Rx32{4-0};
1516}
1517class Enc_6c9440 : OpcodeHexagon {
1518  bits <10> Ii;
1519  let Inst{21-21} = Ii{9-9};
1520  let Inst{13-5} = Ii{8-0};
1521  bits <5> Rd32;
1522  let Inst{4-0} = Rd32{4-0};
1523}
1524class Enc_6c9ee0 : OpcodeHexagon {
1525  bits <3> Ii;
1526  let Inst{10-8} = Ii{2-0};
1527  bits <5> Rx32;
1528  let Inst{20-16} = Rx32{4-0};
1529}
1530class Enc_6f70ca : OpcodeHexagon {
1531  bits <8> Ii;
1532  let Inst{8-4} = Ii{7-3};
1533}
1534class Enc_6f83e7 : OpcodeHexagon {
1535  bits <2> Qv4;
1536  let Inst{23-22} = Qv4{1-0};
1537  bits <5> Vd32;
1538  let Inst{4-0} = Vd32{4-0};
1539}
1540class Enc_70b24b : OpcodeHexagon {
1541  bits <6> Ii;
1542  let Inst{8-5} = Ii{5-2};
1543  bits <1> Mu2;
1544  let Inst{13-13} = Mu2{0-0};
1545  bits <5> Rdd32;
1546  let Inst{4-0} = Rdd32{4-0};
1547  bits <5> Rx32;
1548  let Inst{20-16} = Rx32{4-0};
1549}
1550class Enc_70fb07 : OpcodeHexagon {
1551  bits <6> Ii;
1552  let Inst{13-8} = Ii{5-0};
1553  bits <5> Rss32;
1554  let Inst{20-16} = Rss32{4-0};
1555  bits <5> Rxx32;
1556  let Inst{4-0} = Rxx32{4-0};
1557}
1558class Enc_71bb9b : OpcodeHexagon {
1559  bits <5> Vu32;
1560  let Inst{12-8} = Vu32{4-0};
1561  bits <5> Vv32;
1562  let Inst{20-16} = Vv32{4-0};
1563  bits <5> Vdd32;
1564  let Inst{4-0} = Vdd32{4-0};
1565}
1566class Enc_71f1b4 : OpcodeHexagon {
1567  bits <6> Ii;
1568  let Inst{8-5} = Ii{5-2};
1569  bits <5> Rdd32;
1570  let Inst{4-0} = Rdd32{4-0};
1571  bits <5> Rx32;
1572  let Inst{20-16} = Rx32{4-0};
1573}
1574class Enc_7222b7 : OpcodeHexagon {
1575  bits <5> Rt32;
1576  let Inst{20-16} = Rt32{4-0};
1577  bits <2> Qd4;
1578  let Inst{1-0} = Qd4{1-0};
1579}
1580class Enc_724154 : OpcodeHexagon {
1581  bits <6> II;
1582  let Inst{5-0} = II{5-0};
1583  bits <3> Nt8;
1584  let Inst{10-8} = Nt8{2-0};
1585  bits <5> Re32;
1586  let Inst{20-16} = Re32{4-0};
1587}
1588class Enc_729ff7 : OpcodeHexagon {
1589  bits <3> Ii;
1590  let Inst{7-5} = Ii{2-0};
1591  bits <5> Rtt32;
1592  let Inst{12-8} = Rtt32{4-0};
1593  bits <5> Rss32;
1594  let Inst{20-16} = Rss32{4-0};
1595  bits <5> Rdd32;
1596  let Inst{4-0} = Rdd32{4-0};
1597}
1598class Enc_733b27 : OpcodeHexagon {
1599  bits <5> Ii;
1600  let Inst{8-5} = Ii{4-1};
1601  bits <2> Pt4;
1602  let Inst{10-9} = Pt4{1-0};
1603  bits <5> Rd32;
1604  let Inst{4-0} = Rd32{4-0};
1605  bits <5> Rx32;
1606  let Inst{20-16} = Rx32{4-0};
1607}
1608class Enc_736575 : OpcodeHexagon {
1609  bits <11> Ii;
1610  let Inst{21-20} = Ii{10-9};
1611  let Inst{7-1} = Ii{8-2};
1612  bits <4> Rs16;
1613  let Inst{19-16} = Rs16{3-0};
1614  bits <4> n1;
1615  let Inst{28-28} = n1{3-3};
1616  let Inst{25-23} = n1{2-0};
1617}
1618class Enc_74aef2 : OpcodeHexagon {
1619  bits <4> Ii;
1620  let Inst{8-5} = Ii{3-0};
1621  bits <1> Mu2;
1622  let Inst{13-13} = Mu2{0-0};
1623  bits <5> Ryy32;
1624  let Inst{4-0} = Ryy32{4-0};
1625  bits <5> Rx32;
1626  let Inst{20-16} = Rx32{4-0};
1627}
1628class Enc_74d4e5 : OpcodeHexagon {
1629  bits <1> Mu2;
1630  let Inst{13-13} = Mu2{0-0};
1631  bits <5> Rd32;
1632  let Inst{4-0} = Rd32{4-0};
1633  bits <5> Rx32;
1634  let Inst{20-16} = Rx32{4-0};
1635}
1636class Enc_770858 : OpcodeHexagon {
1637  bits <2> Ps4;
1638  let Inst{6-5} = Ps4{1-0};
1639  bits <5> Vu32;
1640  let Inst{12-8} = Vu32{4-0};
1641  bits <5> Vd32;
1642  let Inst{4-0} = Vd32{4-0};
1643}
1644class Enc_784502 : OpcodeHexagon {
1645  bits <3> Ii;
1646  let Inst{10-8} = Ii{2-0};
1647  bits <2> Pv4;
1648  let Inst{12-11} = Pv4{1-0};
1649  bits <3> Os8;
1650  let Inst{2-0} = Os8{2-0};
1651  bits <5> Rx32;
1652  let Inst{20-16} = Rx32{4-0};
1653}
1654class Enc_78cbf0 : OpcodeHexagon {
1655  bits <18> Ii;
1656  let Inst{26-25} = Ii{17-16};
1657  let Inst{20-16} = Ii{15-11};
1658  let Inst{13-13} = Ii{10-10};
1659  let Inst{7-0} = Ii{9-2};
1660  bits <3> Nt8;
1661  let Inst{10-8} = Nt8{2-0};
1662}
1663class Enc_78e566 : OpcodeHexagon {
1664  bits <2> Pt4;
1665  let Inst{9-8} = Pt4{1-0};
1666  bits <5> Rdd32;
1667  let Inst{4-0} = Rdd32{4-0};
1668}
1669class Enc_79b8c8 : OpcodeHexagon {
1670  bits <6> Ii;
1671  let Inst{6-3} = Ii{5-2};
1672  bits <1> Mu2;
1673  let Inst{13-13} = Mu2{0-0};
1674  bits <5> Rt32;
1675  let Inst{12-8} = Rt32{4-0};
1676  bits <5> Rx32;
1677  let Inst{20-16} = Rx32{4-0};
1678}
1679class Enc_7a0ea6 : OpcodeHexagon {
1680  bits <4> Rd16;
1681  let Inst{3-0} = Rd16{3-0};
1682  bits <1> n1;
1683  let Inst{9-9} = n1{0-0};
1684}
1685class Enc_7b523d : OpcodeHexagon {
1686  bits <5> Vu32;
1687  let Inst{12-8} = Vu32{4-0};
1688  bits <5> Vv32;
1689  let Inst{23-19} = Vv32{4-0};
1690  bits <3> Rt8;
1691  let Inst{18-16} = Rt8{2-0};
1692  bits <5> Vxx32;
1693  let Inst{4-0} = Vxx32{4-0};
1694}
1695class Enc_7b7ba8 : OpcodeHexagon {
1696  bits <2> Qu4;
1697  let Inst{9-8} = Qu4{1-0};
1698  bits <5> Rt32;
1699  let Inst{20-16} = Rt32{4-0};
1700  bits <5> Vd32;
1701  let Inst{4-0} = Vd32{4-0};
1702}
1703class Enc_7e5a82 : OpcodeHexagon {
1704  bits <5> Ii;
1705  let Inst{12-8} = Ii{4-0};
1706  bits <5> Rss32;
1707  let Inst{20-16} = Rss32{4-0};
1708  bits <5> Rdd32;
1709  let Inst{4-0} = Rdd32{4-0};
1710}
1711class Enc_7eaeb6 : OpcodeHexagon {
1712  bits <6> Ii;
1713  let Inst{6-3} = Ii{5-2};
1714  bits <2> Pv4;
1715  let Inst{1-0} = Pv4{1-0};
1716  bits <5> Rt32;
1717  let Inst{12-8} = Rt32{4-0};
1718  bits <5> Rx32;
1719  let Inst{20-16} = Rx32{4-0};
1720}
1721class Enc_7eb485 : OpcodeHexagon {
1722  bits <2> Ii;
1723  let Inst{13-13} = Ii{1-1};
1724  let Inst{6-6} = Ii{0-0};
1725  bits <6> II;
1726  let Inst{5-0} = II{5-0};
1727  bits <5> Ru32;
1728  let Inst{20-16} = Ru32{4-0};
1729  bits <3> Nt8;
1730  let Inst{10-8} = Nt8{2-0};
1731}
1732class Enc_7eee72 : OpcodeHexagon {
1733  bits <1> Mu2;
1734  let Inst{13-13} = Mu2{0-0};
1735  bits <5> Rdd32;
1736  let Inst{4-0} = Rdd32{4-0};
1737  bits <5> Rx32;
1738  let Inst{20-16} = Rx32{4-0};
1739}
1740class Enc_7f1a05 : OpcodeHexagon {
1741  bits <5> Ru32;
1742  let Inst{4-0} = Ru32{4-0};
1743  bits <5> Rs32;
1744  let Inst{20-16} = Rs32{4-0};
1745  bits <5> Ry32;
1746  let Inst{12-8} = Ry32{4-0};
1747}
1748class Enc_7fa7f6 : OpcodeHexagon {
1749  bits <6> II;
1750  let Inst{11-8} = II{5-2};
1751  let Inst{6-5} = II{1-0};
1752  bits <5> Rdd32;
1753  let Inst{4-0} = Rdd32{4-0};
1754  bits <5> Re32;
1755  let Inst{20-16} = Re32{4-0};
1756}
1757class Enc_800e04 : OpcodeHexagon {
1758  bits <11> Ii;
1759  let Inst{21-20} = Ii{10-9};
1760  let Inst{7-1} = Ii{8-2};
1761  bits <4> Rs16;
1762  let Inst{19-16} = Rs16{3-0};
1763  bits <6> n1;
1764  let Inst{28-28} = n1{5-5};
1765  let Inst{25-22} = n1{4-1};
1766  let Inst{13-13} = n1{0-0};
1767}
1768class Enc_802dc0 : OpcodeHexagon {
1769  bits <1> Ii;
1770  let Inst{8-8} = Ii{0-0};
1771  bits <2> Qv4;
1772  let Inst{23-22} = Qv4{1-0};
1773}
1774class Enc_81ac1d : OpcodeHexagon {
1775  bits <24> Ii;
1776  let Inst{24-16} = Ii{23-15};
1777  let Inst{13-1} = Ii{14-2};
1778}
1779class Enc_8203bb : OpcodeHexagon {
1780  bits <6> Ii;
1781  let Inst{12-7} = Ii{5-0};
1782  bits <8> II;
1783  let Inst{13-13} = II{7-7};
1784  let Inst{6-0} = II{6-0};
1785  bits <5> Rs32;
1786  let Inst{20-16} = Rs32{4-0};
1787}
1788class Enc_830e5d : OpcodeHexagon {
1789  bits <8> Ii;
1790  let Inst{12-5} = Ii{7-0};
1791  bits <8> II;
1792  let Inst{22-16} = II{7-1};
1793  let Inst{13-13} = II{0-0};
1794  bits <2> Pu4;
1795  let Inst{24-23} = Pu4{1-0};
1796  bits <5> Rd32;
1797  let Inst{4-0} = Rd32{4-0};
1798}
1799class Enc_831a7d : OpcodeHexagon {
1800  bits <5> Rss32;
1801  let Inst{20-16} = Rss32{4-0};
1802  bits <5> Rtt32;
1803  let Inst{12-8} = Rtt32{4-0};
1804  bits <5> Rxx32;
1805  let Inst{4-0} = Rxx32{4-0};
1806  bits <2> Pe4;
1807  let Inst{6-5} = Pe4{1-0};
1808}
1809class Enc_83ee64 : OpcodeHexagon {
1810  bits <5> Ii;
1811  let Inst{12-8} = Ii{4-0};
1812  bits <5> Rs32;
1813  let Inst{20-16} = Rs32{4-0};
1814  bits <2> Pd4;
1815  let Inst{1-0} = Pd4{1-0};
1816}
1817class Enc_84b2cd : OpcodeHexagon {
1818  bits <8> Ii;
1819  let Inst{12-7} = Ii{7-2};
1820  bits <5> II;
1821  let Inst{4-0} = II{4-0};
1822  bits <5> Rs32;
1823  let Inst{20-16} = Rs32{4-0};
1824}
1825class Enc_84bff1 : OpcodeHexagon {
1826  bits <2> Ii;
1827  let Inst{13-13} = Ii{1-1};
1828  let Inst{7-7} = Ii{0-0};
1829  bits <5> Rs32;
1830  let Inst{20-16} = Rs32{4-0};
1831  bits <5> Rt32;
1832  let Inst{12-8} = Rt32{4-0};
1833  bits <5> Rdd32;
1834  let Inst{4-0} = Rdd32{4-0};
1835}
1836class Enc_84d359 : OpcodeHexagon {
1837  bits <4> Ii;
1838  let Inst{3-0} = Ii{3-0};
1839  bits <4> Rs16;
1840  let Inst{7-4} = Rs16{3-0};
1841}
1842class Enc_85bf58 : OpcodeHexagon {
1843  bits <7> Ii;
1844  let Inst{6-3} = Ii{6-3};
1845  bits <5> Rtt32;
1846  let Inst{12-8} = Rtt32{4-0};
1847  bits <5> Rx32;
1848  let Inst{20-16} = Rx32{4-0};
1849}
1850class Enc_864a5a : OpcodeHexagon {
1851  bits <9> Ii;
1852  let Inst{12-8} = Ii{8-4};
1853  let Inst{4-3} = Ii{3-2};
1854  bits <5> Rs32;
1855  let Inst{20-16} = Rs32{4-0};
1856}
1857class Enc_865390 : OpcodeHexagon {
1858  bits <3> Ii;
1859  let Inst{10-8} = Ii{2-0};
1860  bits <2> Pv4;
1861  let Inst{12-11} = Pv4{1-0};
1862  bits <5> Vs32;
1863  let Inst{4-0} = Vs32{4-0};
1864  bits <5> Rx32;
1865  let Inst{20-16} = Rx32{4-0};
1866}
1867class Enc_86a14b : OpcodeHexagon {
1868  bits <8> Ii;
1869  let Inst{7-3} = Ii{7-3};
1870  bits <3> Rdd8;
1871  let Inst{2-0} = Rdd8{2-0};
1872}
1873class Enc_87c142 : OpcodeHexagon {
1874  bits <7> Ii;
1875  let Inst{8-4} = Ii{6-2};
1876  bits <4> Rt16;
1877  let Inst{3-0} = Rt16{3-0};
1878}
1879class Enc_88c16c : OpcodeHexagon {
1880  bits <5> Rss32;
1881  let Inst{20-16} = Rss32{4-0};
1882  bits <5> Rtt32;
1883  let Inst{12-8} = Rtt32{4-0};
1884  bits <5> Rxx32;
1885  let Inst{4-0} = Rxx32{4-0};
1886}
1887class Enc_88d4d9 : OpcodeHexagon {
1888  bits <2> Pu4;
1889  let Inst{9-8} = Pu4{1-0};
1890  bits <5> Rs32;
1891  let Inst{20-16} = Rs32{4-0};
1892}
1893class Enc_890909 : OpcodeHexagon {
1894  bits <5> Rs32;
1895  let Inst{20-16} = Rs32{4-0};
1896  bits <5> Rd32;
1897  let Inst{4-0} = Rd32{4-0};
1898  bits <2> Pe4;
1899  let Inst{6-5} = Pe4{1-0};
1900}
1901class Enc_895bd9 : OpcodeHexagon {
1902  bits <2> Qu4;
1903  let Inst{9-8} = Qu4{1-0};
1904  bits <5> Rt32;
1905  let Inst{20-16} = Rt32{4-0};
1906  bits <5> Vx32;
1907  let Inst{4-0} = Vx32{4-0};
1908}
1909class Enc_8b8927 : OpcodeHexagon {
1910  bits <5> Rt32;
1911  let Inst{20-16} = Rt32{4-0};
1912  bits <1> Mu2;
1913  let Inst{13-13} = Mu2{0-0};
1914  bits <5> Vv32;
1915  let Inst{4-0} = Vv32{4-0};
1916}
1917class Enc_8b8d61 : OpcodeHexagon {
1918  bits <6> Ii;
1919  let Inst{22-21} = Ii{5-4};
1920  let Inst{13-13} = Ii{3-3};
1921  let Inst{7-5} = Ii{2-0};
1922  bits <5> Rs32;
1923  let Inst{20-16} = Rs32{4-0};
1924  bits <5> Ru32;
1925  let Inst{4-0} = Ru32{4-0};
1926  bits <5> Rd32;
1927  let Inst{12-8} = Rd32{4-0};
1928}
1929class Enc_8bcba4 : OpcodeHexagon {
1930  bits <6> II;
1931  let Inst{5-0} = II{5-0};
1932  bits <5> Rt32;
1933  let Inst{12-8} = Rt32{4-0};
1934  bits <5> Re32;
1935  let Inst{20-16} = Re32{4-0};
1936}
1937class Enc_8c2412 : OpcodeHexagon {
1938  bits <2> Ps4;
1939  let Inst{6-5} = Ps4{1-0};
1940  bits <5> Vu32;
1941  let Inst{12-8} = Vu32{4-0};
1942  bits <5> Vv32;
1943  let Inst{20-16} = Vv32{4-0};
1944  bits <5> Vdd32;
1945  let Inst{4-0} = Vdd32{4-0};
1946}
1947class Enc_8c6530 : OpcodeHexagon {
1948  bits <5> Rtt32;
1949  let Inst{12-8} = Rtt32{4-0};
1950  bits <5> Rss32;
1951  let Inst{20-16} = Rss32{4-0};
1952  bits <2> Pu4;
1953  let Inst{6-5} = Pu4{1-0};
1954  bits <5> Rdd32;
1955  let Inst{4-0} = Rdd32{4-0};
1956}
1957class Enc_8d8a30 : OpcodeHexagon {
1958  bits <4> Ii;
1959  let Inst{13-13} = Ii{3-3};
1960  let Inst{10-8} = Ii{2-0};
1961  bits <2> Pv4;
1962  let Inst{12-11} = Pv4{1-0};
1963  bits <5> Rt32;
1964  let Inst{20-16} = Rt32{4-0};
1965  bits <5> Vd32;
1966  let Inst{4-0} = Vd32{4-0};
1967}
1968class Enc_8dbdfe : OpcodeHexagon {
1969  bits <8> Ii;
1970  let Inst{13-13} = Ii{7-7};
1971  let Inst{7-3} = Ii{6-2};
1972  bits <2> Pv4;
1973  let Inst{1-0} = Pv4{1-0};
1974  bits <5> Rs32;
1975  let Inst{20-16} = Rs32{4-0};
1976  bits <3> Nt8;
1977  let Inst{10-8} = Nt8{2-0};
1978}
1979class Enc_8dbe85 : OpcodeHexagon {
1980  bits <1> Mu2;
1981  let Inst{13-13} = Mu2{0-0};
1982  bits <3> Nt8;
1983  let Inst{10-8} = Nt8{2-0};
1984  bits <5> Rx32;
1985  let Inst{20-16} = Rx32{4-0};
1986}
1987class Enc_8dec2e : OpcodeHexagon {
1988  bits <5> Ii;
1989  let Inst{12-8} = Ii{4-0};
1990  bits <5> Rss32;
1991  let Inst{20-16} = Rss32{4-0};
1992  bits <5> Rd32;
1993  let Inst{4-0} = Rd32{4-0};
1994}
1995class Enc_8df4be : OpcodeHexagon {
1996  bits <17> Ii;
1997  let Inst{26-25} = Ii{16-15};
1998  let Inst{20-16} = Ii{14-10};
1999  let Inst{13-5} = Ii{9-1};
2000  bits <5> Rd32;
2001  let Inst{4-0} = Rd32{4-0};
2002}
2003class Enc_8e583a : OpcodeHexagon {
2004  bits <11> Ii;
2005  let Inst{21-20} = Ii{10-9};
2006  let Inst{7-1} = Ii{8-2};
2007  bits <4> Rs16;
2008  let Inst{19-16} = Rs16{3-0};
2009  bits <5> n1;
2010  let Inst{28-28} = n1{4-4};
2011  let Inst{25-23} = n1{3-1};
2012  let Inst{13-13} = n1{0-0};
2013}
2014class Enc_90cd8b : OpcodeHexagon {
2015  bits <5> Rss32;
2016  let Inst{20-16} = Rss32{4-0};
2017  bits <5> Rd32;
2018  let Inst{4-0} = Rd32{4-0};
2019}
2020class Enc_91b9fe : OpcodeHexagon {
2021  bits <5> Ii;
2022  let Inst{6-3} = Ii{4-1};
2023  bits <1> Mu2;
2024  let Inst{13-13} = Mu2{0-0};
2025  bits <3> Nt8;
2026  let Inst{10-8} = Nt8{2-0};
2027  bits <5> Rx32;
2028  let Inst{20-16} = Rx32{4-0};
2029}
2030class Enc_927852 : OpcodeHexagon {
2031  bits <5> Rss32;
2032  let Inst{20-16} = Rss32{4-0};
2033  bits <5> Rt32;
2034  let Inst{12-8} = Rt32{4-0};
2035  bits <5> Rdd32;
2036  let Inst{4-0} = Rdd32{4-0};
2037}
2038class Enc_928ca1 : OpcodeHexagon {
2039  bits <1> Mu2;
2040  let Inst{13-13} = Mu2{0-0};
2041  bits <5> Rtt32;
2042  let Inst{12-8} = Rtt32{4-0};
2043  bits <5> Rx32;
2044  let Inst{20-16} = Rx32{4-0};
2045}
2046class Enc_935d9b : OpcodeHexagon {
2047  bits <5> Ii;
2048  let Inst{6-3} = Ii{4-1};
2049  bits <1> Mu2;
2050  let Inst{13-13} = Mu2{0-0};
2051  bits <5> Rt32;
2052  let Inst{12-8} = Rt32{4-0};
2053  bits <5> Rx32;
2054  let Inst{20-16} = Rx32{4-0};
2055}
2056class Enc_93af4c : OpcodeHexagon {
2057  bits <7> Ii;
2058  let Inst{10-4} = Ii{6-0};
2059  bits <4> Rx16;
2060  let Inst{3-0} = Rx16{3-0};
2061}
2062class Enc_95441f : OpcodeHexagon {
2063  bits <5> Vu32;
2064  let Inst{12-8} = Vu32{4-0};
2065  bits <5> Vv32;
2066  let Inst{20-16} = Vv32{4-0};
2067  bits <2> Qd4;
2068  let Inst{1-0} = Qd4{1-0};
2069}
2070class Enc_96ce4f : OpcodeHexagon {
2071  bits <4> Ii;
2072  let Inst{6-3} = Ii{3-0};
2073  bits <1> Mu2;
2074  let Inst{13-13} = Mu2{0-0};
2075  bits <3> Nt8;
2076  let Inst{10-8} = Nt8{2-0};
2077  bits <5> Rx32;
2078  let Inst{20-16} = Rx32{4-0};
2079}
2080class Enc_97d666 : OpcodeHexagon {
2081  bits <4> Rs16;
2082  let Inst{7-4} = Rs16{3-0};
2083  bits <4> Rd16;
2084  let Inst{3-0} = Rd16{3-0};
2085}
2086class Enc_989021 : OpcodeHexagon {
2087  bits <5> Rt32;
2088  let Inst{20-16} = Rt32{4-0};
2089  bits <5> Vy32;
2090  let Inst{12-8} = Vy32{4-0};
2091  bits <5> Vx32;
2092  let Inst{4-0} = Vx32{4-0};
2093}
2094class Enc_98c0b8 : OpcodeHexagon {
2095  bits <2> Ii;
2096  let Inst{13-13} = Ii{1-1};
2097  let Inst{7-7} = Ii{0-0};
2098  bits <2> Pv4;
2099  let Inst{6-5} = Pv4{1-0};
2100  bits <5> Rs32;
2101  let Inst{20-16} = Rs32{4-0};
2102  bits <5> Rt32;
2103  let Inst{12-8} = Rt32{4-0};
2104  bits <5> Rdd32;
2105  let Inst{4-0} = Rdd32{4-0};
2106}
2107class Enc_9a33d5 : OpcodeHexagon {
2108  bits <7> Ii;
2109  let Inst{6-3} = Ii{6-3};
2110  bits <2> Pv4;
2111  let Inst{1-0} = Pv4{1-0};
2112  bits <5> Rtt32;
2113  let Inst{12-8} = Rtt32{4-0};
2114  bits <5> Rx32;
2115  let Inst{20-16} = Rx32{4-0};
2116}
2117class Enc_9ac432 : OpcodeHexagon {
2118  bits <2> Ps4;
2119  let Inst{17-16} = Ps4{1-0};
2120  bits <2> Pt4;
2121  let Inst{9-8} = Pt4{1-0};
2122  bits <2> Pu4;
2123  let Inst{7-6} = Pu4{1-0};
2124  bits <2> Pd4;
2125  let Inst{1-0} = Pd4{1-0};
2126}
2127class Enc_9b0bc1 : OpcodeHexagon {
2128  bits <2> Pu4;
2129  let Inst{6-5} = Pu4{1-0};
2130  bits <5> Rt32;
2131  let Inst{12-8} = Rt32{4-0};
2132  bits <5> Rs32;
2133  let Inst{20-16} = Rs32{4-0};
2134  bits <5> Rd32;
2135  let Inst{4-0} = Rd32{4-0};
2136}
2137class Enc_9be1de : OpcodeHexagon {
2138  bits <2> Qs4;
2139  let Inst{6-5} = Qs4{1-0};
2140  bits <5> Rt32;
2141  let Inst{20-16} = Rt32{4-0};
2142  bits <1> Mu2;
2143  let Inst{13-13} = Mu2{0-0};
2144  bits <5> Vv32;
2145  let Inst{12-8} = Vv32{4-0};
2146  bits <5> Vw32;
2147  let Inst{4-0} = Vw32{4-0};
2148}
2149class Enc_9cdba7 : OpcodeHexagon {
2150  bits <8> Ii;
2151  let Inst{12-5} = Ii{7-0};
2152  bits <5> Rs32;
2153  let Inst{20-16} = Rs32{4-0};
2154  bits <5> Rdd32;
2155  let Inst{4-0} = Rdd32{4-0};
2156}
2157class Enc_9d1247 : OpcodeHexagon {
2158  bits <7> Ii;
2159  let Inst{8-5} = Ii{6-3};
2160  bits <2> Pt4;
2161  let Inst{10-9} = Pt4{1-0};
2162  bits <5> Rdd32;
2163  let Inst{4-0} = Rdd32{4-0};
2164  bits <5> Rx32;
2165  let Inst{20-16} = Rx32{4-0};
2166}
2167class Enc_9e2e1c : OpcodeHexagon {
2168  bits <5> Ii;
2169  let Inst{8-5} = Ii{4-1};
2170  bits <1> Mu2;
2171  let Inst{13-13} = Mu2{0-0};
2172  bits <5> Ryy32;
2173  let Inst{4-0} = Ryy32{4-0};
2174  bits <5> Rx32;
2175  let Inst{20-16} = Rx32{4-0};
2176}
2177class Enc_9e4c3f : OpcodeHexagon {
2178  bits <6> II;
2179  let Inst{13-8} = II{5-0};
2180  bits <11> Ii;
2181  let Inst{21-20} = Ii{10-9};
2182  let Inst{7-1} = Ii{8-2};
2183  bits <4> Rd16;
2184  let Inst{19-16} = Rd16{3-0};
2185}
2186class Enc_9ea4cf : OpcodeHexagon {
2187  bits <2> Ii;
2188  let Inst{13-13} = Ii{1-1};
2189  let Inst{6-6} = Ii{0-0};
2190  bits <6> II;
2191  let Inst{5-0} = II{5-0};
2192  bits <5> Ru32;
2193  let Inst{20-16} = Ru32{4-0};
2194  bits <5> Rt32;
2195  let Inst{12-8} = Rt32{4-0};
2196}
2197class Enc_9fae8a : OpcodeHexagon {
2198  bits <6> Ii;
2199  let Inst{13-8} = Ii{5-0};
2200  bits <5> Rs32;
2201  let Inst{20-16} = Rs32{4-0};
2202  bits <5> Rd32;
2203  let Inst{4-0} = Rd32{4-0};
2204}
2205class Enc_a05677 : OpcodeHexagon {
2206  bits <5> Ii;
2207  let Inst{12-8} = Ii{4-0};
2208  bits <5> Rs32;
2209  let Inst{20-16} = Rs32{4-0};
2210  bits <5> Rd32;
2211  let Inst{4-0} = Rd32{4-0};
2212}
2213class Enc_a1640c : OpcodeHexagon {
2214  bits <6> Ii;
2215  let Inst{13-8} = Ii{5-0};
2216  bits <5> Rss32;
2217  let Inst{20-16} = Rss32{4-0};
2218  bits <5> Rd32;
2219  let Inst{4-0} = Rd32{4-0};
2220}
2221class Enc_a198f6 : OpcodeHexagon {
2222  bits <7> Ii;
2223  let Inst{10-5} = Ii{6-1};
2224  bits <2> Pt4;
2225  let Inst{12-11} = Pt4{1-0};
2226  bits <5> Rs32;
2227  let Inst{20-16} = Rs32{4-0};
2228  bits <5> Rd32;
2229  let Inst{4-0} = Rd32{4-0};
2230}
2231class Enc_a1e29d : OpcodeHexagon {
2232  bits <5> Ii;
2233  let Inst{12-8} = Ii{4-0};
2234  bits <5> II;
2235  let Inst{22-21} = II{4-3};
2236  let Inst{7-5} = II{2-0};
2237  bits <5> Rs32;
2238  let Inst{20-16} = Rs32{4-0};
2239  bits <5> Rx32;
2240  let Inst{4-0} = Rx32{4-0};
2241}
2242class Enc_a21d47 : OpcodeHexagon {
2243  bits <6> Ii;
2244  let Inst{10-5} = Ii{5-0};
2245  bits <2> Pt4;
2246  let Inst{12-11} = Pt4{1-0};
2247  bits <5> Rs32;
2248  let Inst{20-16} = Rs32{4-0};
2249  bits <5> Rd32;
2250  let Inst{4-0} = Rd32{4-0};
2251}
2252class Enc_a255dc : OpcodeHexagon {
2253  bits <3> Ii;
2254  let Inst{10-8} = Ii{2-0};
2255  bits <5> Vd32;
2256  let Inst{4-0} = Vd32{4-0};
2257  bits <5> Rx32;
2258  let Inst{20-16} = Rx32{4-0};
2259}
2260class Enc_a27588 : OpcodeHexagon {
2261  bits <11> Ii;
2262  let Inst{26-25} = Ii{10-9};
2263  let Inst{13-5} = Ii{8-0};
2264  bits <5> Rs32;
2265  let Inst{20-16} = Rs32{4-0};
2266  bits <5> Ryy32;
2267  let Inst{4-0} = Ryy32{4-0};
2268}
2269class Enc_a30110 : OpcodeHexagon {
2270  bits <5> Vu32;
2271  let Inst{12-8} = Vu32{4-0};
2272  bits <5> Vv32;
2273  let Inst{23-19} = Vv32{4-0};
2274  bits <3> Rt8;
2275  let Inst{18-16} = Rt8{2-0};
2276  bits <5> Vd32;
2277  let Inst{4-0} = Vd32{4-0};
2278}
2279class Enc_a42857 : OpcodeHexagon {
2280  bits <11> Ii;
2281  let Inst{21-20} = Ii{10-9};
2282  let Inst{7-1} = Ii{8-2};
2283  bits <4> Rs16;
2284  let Inst{19-16} = Rs16{3-0};
2285  bits <5> n1;
2286  let Inst{28-28} = n1{4-4};
2287  let Inst{24-22} = n1{3-1};
2288  let Inst{8-8} = n1{0-0};
2289}
2290class Enc_a4ef14 : OpcodeHexagon {
2291  bits <5> Rd32;
2292  let Inst{4-0} = Rd32{4-0};
2293}
2294class Enc_a51a9a : OpcodeHexagon {
2295  bits <8> Ii;
2296  let Inst{12-8} = Ii{7-3};
2297  let Inst{4-2} = Ii{2-0};
2298}
2299class Enc_a56825 : OpcodeHexagon {
2300  bits <5> Rss32;
2301  let Inst{20-16} = Rss32{4-0};
2302  bits <5> Rtt32;
2303  let Inst{12-8} = Rtt32{4-0};
2304  bits <5> Rdd32;
2305  let Inst{4-0} = Rdd32{4-0};
2306}
2307class Enc_a568d4 : OpcodeHexagon {
2308  bits <5> Rt32;
2309  let Inst{12-8} = Rt32{4-0};
2310  bits <5> Rs32;
2311  let Inst{20-16} = Rs32{4-0};
2312  bits <5> Rx32;
2313  let Inst{4-0} = Rx32{4-0};
2314}
2315class Enc_a5ed8a : OpcodeHexagon {
2316  bits <5> Rt32;
2317  let Inst{20-16} = Rt32{4-0};
2318  bits <5> Vd32;
2319  let Inst{4-0} = Vd32{4-0};
2320}
2321class Enc_a641d0 : OpcodeHexagon {
2322  bits <5> Rt32;
2323  let Inst{20-16} = Rt32{4-0};
2324  bits <1> Mu2;
2325  let Inst{13-13} = Mu2{0-0};
2326  bits <5> Vvv32;
2327  let Inst{12-8} = Vvv32{4-0};
2328  bits <5> Vw32;
2329  let Inst{4-0} = Vw32{4-0};
2330}
2331class Enc_a6853f : OpcodeHexagon {
2332  bits <11> Ii;
2333  let Inst{21-20} = Ii{10-9};
2334  let Inst{7-1} = Ii{8-2};
2335  bits <3> Ns8;
2336  let Inst{18-16} = Ns8{2-0};
2337  bits <6> n1;
2338  let Inst{29-29} = n1{5-5};
2339  let Inst{26-25} = n1{4-3};
2340  let Inst{23-22} = n1{2-1};
2341  let Inst{13-13} = n1{0-0};
2342}
2343class Enc_a6ce9c : OpcodeHexagon {
2344  bits <6> Ii;
2345  let Inst{3-0} = Ii{5-2};
2346  bits <4> Rs16;
2347  let Inst{7-4} = Rs16{3-0};
2348}
2349class Enc_a7341a : OpcodeHexagon {
2350  bits <5> Vu32;
2351  let Inst{12-8} = Vu32{4-0};
2352  bits <5> Vv32;
2353  let Inst{20-16} = Vv32{4-0};
2354  bits <5> Vx32;
2355  let Inst{4-0} = Vx32{4-0};
2356}
2357class Enc_a75aa6 : OpcodeHexagon {
2358  bits <5> Rs32;
2359  let Inst{20-16} = Rs32{4-0};
2360  bits <5> Rt32;
2361  let Inst{12-8} = Rt32{4-0};
2362  bits <1> Mu2;
2363  let Inst{13-13} = Mu2{0-0};
2364}
2365class Enc_a7b8e8 : OpcodeHexagon {
2366  bits <6> Ii;
2367  let Inst{22-21} = Ii{5-4};
2368  let Inst{13-13} = Ii{3-3};
2369  let Inst{7-5} = Ii{2-0};
2370  bits <5> Rs32;
2371  let Inst{20-16} = Rs32{4-0};
2372  bits <5> Rt32;
2373  let Inst{12-8} = Rt32{4-0};
2374  bits <5> Rd32;
2375  let Inst{4-0} = Rd32{4-0};
2376}
2377class Enc_a803e0 : OpcodeHexagon {
2378  bits <7> Ii;
2379  let Inst{12-7} = Ii{6-1};
2380  bits <8> II;
2381  let Inst{13-13} = II{7-7};
2382  let Inst{6-0} = II{6-0};
2383  bits <5> Rs32;
2384  let Inst{20-16} = Rs32{4-0};
2385}
2386class Enc_a90628 : OpcodeHexagon {
2387  bits <2> Qv4;
2388  let Inst{23-22} = Qv4{1-0};
2389  bits <5> Vu32;
2390  let Inst{12-8} = Vu32{4-0};
2391  bits <5> Vx32;
2392  let Inst{4-0} = Vx32{4-0};
2393}
2394class Enc_a94f3b : OpcodeHexagon {
2395  bits <5> Rs32;
2396  let Inst{20-16} = Rs32{4-0};
2397  bits <5> Rt32;
2398  let Inst{12-8} = Rt32{4-0};
2399  bits <5> Rd32;
2400  let Inst{4-0} = Rd32{4-0};
2401  bits <2> Pe4;
2402  let Inst{6-5} = Pe4{1-0};
2403}
2404class Enc_aad80c : OpcodeHexagon {
2405  bits <5> Vuu32;
2406  let Inst{12-8} = Vuu32{4-0};
2407  bits <5> Rt32;
2408  let Inst{20-16} = Rt32{4-0};
2409  bits <5> Vdd32;
2410  let Inst{4-0} = Vdd32{4-0};
2411}
2412class Enc_acd6ed : OpcodeHexagon {
2413  bits <9> Ii;
2414  let Inst{10-5} = Ii{8-3};
2415  bits <2> Pt4;
2416  let Inst{12-11} = Pt4{1-0};
2417  bits <5> Rs32;
2418  let Inst{20-16} = Rs32{4-0};
2419  bits <5> Rdd32;
2420  let Inst{4-0} = Rdd32{4-0};
2421}
2422class Enc_ad1831 : OpcodeHexagon {
2423  bits <16> Ii;
2424  let Inst{26-25} = Ii{15-14};
2425  let Inst{20-16} = Ii{13-9};
2426  let Inst{13-13} = Ii{8-8};
2427  let Inst{7-0} = Ii{7-0};
2428  bits <3> Nt8;
2429  let Inst{10-8} = Nt8{2-0};
2430}
2431class Enc_ad1c74 : OpcodeHexagon {
2432  bits <11> Ii;
2433  let Inst{21-20} = Ii{10-9};
2434  let Inst{7-1} = Ii{8-2};
2435  bits <4> Rs16;
2436  let Inst{19-16} = Rs16{3-0};
2437}
2438class Enc_ad9bef : OpcodeHexagon {
2439  bits <5> Vu32;
2440  let Inst{12-8} = Vu32{4-0};
2441  bits <5> Rtt32;
2442  let Inst{20-16} = Rtt32{4-0};
2443  bits <5> Vxx32;
2444  let Inst{4-0} = Vxx32{4-0};
2445}
2446class Enc_adf111 : OpcodeHexagon {
2447  bits <5> Vu32;
2448  let Inst{12-8} = Vu32{4-0};
2449  bits <5> Rt32;
2450  let Inst{20-16} = Rt32{4-0};
2451  bits <2> Qx4;
2452  let Inst{1-0} = Qx4{1-0};
2453}
2454class Enc_b00112 : OpcodeHexagon {
2455  bits <5> Rss32;
2456  let Inst{20-16} = Rss32{4-0};
2457  bits <5> Rtt32;
2458  let Inst{12-8} = Rtt32{4-0};
2459}
2460class Enc_b05839 : OpcodeHexagon {
2461  bits <7> Ii;
2462  let Inst{8-5} = Ii{6-3};
2463  bits <1> Mu2;
2464  let Inst{13-13} = Mu2{0-0};
2465  bits <5> Rdd32;
2466  let Inst{4-0} = Rdd32{4-0};
2467  bits <5> Rx32;
2468  let Inst{20-16} = Rx32{4-0};
2469}
2470class Enc_b087ac : OpcodeHexagon {
2471  bits <5> Vu32;
2472  let Inst{12-8} = Vu32{4-0};
2473  bits <5> Rt32;
2474  let Inst{20-16} = Rt32{4-0};
2475  bits <5> Vd32;
2476  let Inst{4-0} = Vd32{4-0};
2477}
2478class Enc_b0e9d8 : OpcodeHexagon {
2479  bits <10> Ii;
2480  let Inst{21-21} = Ii{9-9};
2481  let Inst{13-5} = Ii{8-0};
2482  bits <5> Rs32;
2483  let Inst{20-16} = Rs32{4-0};
2484  bits <5> Rx32;
2485  let Inst{4-0} = Rx32{4-0};
2486}
2487class Enc_b15941 : OpcodeHexagon {
2488  bits <4> Ii;
2489  let Inst{6-3} = Ii{3-0};
2490  bits <1> Mu2;
2491  let Inst{13-13} = Mu2{0-0};
2492  bits <5> Rt32;
2493  let Inst{12-8} = Rt32{4-0};
2494  bits <5> Rx32;
2495  let Inst{20-16} = Rx32{4-0};
2496}
2497class Enc_b1e1fb : OpcodeHexagon {
2498  bits <11> Ii;
2499  let Inst{21-20} = Ii{10-9};
2500  let Inst{7-1} = Ii{8-2};
2501  bits <4> Rs16;
2502  let Inst{19-16} = Rs16{3-0};
2503  bits <5> n1;
2504  let Inst{28-28} = n1{4-4};
2505  let Inst{25-23} = n1{3-1};
2506  let Inst{8-8} = n1{0-0};
2507}
2508class Enc_b388cf : OpcodeHexagon {
2509  bits <5> Ii;
2510  let Inst{12-8} = Ii{4-0};
2511  bits <5> II;
2512  let Inst{22-21} = II{4-3};
2513  let Inst{7-5} = II{2-0};
2514  bits <5> Rs32;
2515  let Inst{20-16} = Rs32{4-0};
2516  bits <5> Rd32;
2517  let Inst{4-0} = Rd32{4-0};
2518}
2519class Enc_b38ffc : OpcodeHexagon {
2520  bits <4> Ii;
2521  let Inst{11-8} = Ii{3-0};
2522  bits <4> Rs16;
2523  let Inst{7-4} = Rs16{3-0};
2524  bits <4> Rt16;
2525  let Inst{3-0} = Rt16{3-0};
2526}
2527class Enc_b43b67 : OpcodeHexagon {
2528  bits <5> Vu32;
2529  let Inst{12-8} = Vu32{4-0};
2530  bits <5> Vv32;
2531  let Inst{20-16} = Vv32{4-0};
2532  bits <5> Vd32;
2533  let Inst{4-0} = Vd32{4-0};
2534  bits <2> Qx4;
2535  let Inst{6-5} = Qx4{1-0};
2536}
2537class Enc_b4e6cf : OpcodeHexagon {
2538  bits <10> Ii;
2539  let Inst{21-21} = Ii{9-9};
2540  let Inst{13-5} = Ii{8-0};
2541  bits <5> Ru32;
2542  let Inst{4-0} = Ru32{4-0};
2543  bits <5> Rx32;
2544  let Inst{20-16} = Rx32{4-0};
2545}
2546class Enc_b62ef7 : OpcodeHexagon {
2547  bits <3> Ii;
2548  let Inst{10-8} = Ii{2-0};
2549  bits <5> Vs32;
2550  let Inst{4-0} = Vs32{4-0};
2551  bits <5> Rx32;
2552  let Inst{20-16} = Rx32{4-0};
2553}
2554class Enc_b72622 : OpcodeHexagon {
2555  bits <2> Ii;
2556  let Inst{13-13} = Ii{1-1};
2557  let Inst{5-5} = Ii{0-0};
2558  bits <5> Rss32;
2559  let Inst{20-16} = Rss32{4-0};
2560  bits <5> Rt32;
2561  let Inst{12-8} = Rt32{4-0};
2562  bits <5> Rxx32;
2563  let Inst{4-0} = Rxx32{4-0};
2564}
2565class Enc_b78edd : OpcodeHexagon {
2566  bits <11> Ii;
2567  let Inst{21-20} = Ii{10-9};
2568  let Inst{7-1} = Ii{8-2};
2569  bits <4> Rs16;
2570  let Inst{19-16} = Rs16{3-0};
2571  bits <4> n1;
2572  let Inst{28-28} = n1{3-3};
2573  let Inst{24-23} = n1{2-1};
2574  let Inst{8-8} = n1{0-0};
2575}
2576class Enc_b7fad3 : OpcodeHexagon {
2577  bits <2> Pv4;
2578  let Inst{9-8} = Pv4{1-0};
2579  bits <5> Rs32;
2580  let Inst{20-16} = Rs32{4-0};
2581  bits <5> Rdd32;
2582  let Inst{4-0} = Rdd32{4-0};
2583}
2584class Enc_b8309d : OpcodeHexagon {
2585  bits <9> Ii;
2586  let Inst{8-3} = Ii{8-3};
2587  bits <3> Rtt8;
2588  let Inst{2-0} = Rtt8{2-0};
2589}
2590class Enc_b84c4c : OpcodeHexagon {
2591  bits <6> Ii;
2592  let Inst{13-8} = Ii{5-0};
2593  bits <6> II;
2594  let Inst{23-21} = II{5-3};
2595  let Inst{7-5} = II{2-0};
2596  bits <5> Rss32;
2597  let Inst{20-16} = Rss32{4-0};
2598  bits <5> Rdd32;
2599  let Inst{4-0} = Rdd32{4-0};
2600}
2601class Enc_b886fd : OpcodeHexagon {
2602  bits <5> Ii;
2603  let Inst{6-3} = Ii{4-1};
2604  bits <2> Pv4;
2605  let Inst{1-0} = Pv4{1-0};
2606  bits <5> Rt32;
2607  let Inst{12-8} = Rt32{4-0};
2608  bits <5> Rx32;
2609  let Inst{20-16} = Rx32{4-0};
2610}
2611class Enc_b8c967 : OpcodeHexagon {
2612  bits <8> Ii;
2613  let Inst{12-5} = Ii{7-0};
2614  bits <5> Rs32;
2615  let Inst{20-16} = Rs32{4-0};
2616  bits <5> Rd32;
2617  let Inst{4-0} = Rd32{4-0};
2618}
2619class Enc_b909d2 : OpcodeHexagon {
2620  bits <11> Ii;
2621  let Inst{21-20} = Ii{10-9};
2622  let Inst{7-1} = Ii{8-2};
2623  bits <4> Rs16;
2624  let Inst{19-16} = Rs16{3-0};
2625  bits <7> n1;
2626  let Inst{28-28} = n1{6-6};
2627  let Inst{25-22} = n1{5-2};
2628  let Inst{13-13} = n1{1-1};
2629  let Inst{8-8} = n1{0-0};
2630}
2631class Enc_b91167 : OpcodeHexagon {
2632  bits <2> Ii;
2633  let Inst{6-5} = Ii{1-0};
2634  bits <5> Vuu32;
2635  let Inst{12-8} = Vuu32{4-0};
2636  bits <5> Vvv32;
2637  let Inst{20-16} = Vvv32{4-0};
2638  bits <5> Vdd32;
2639  let Inst{4-0} = Vdd32{4-0};
2640}
2641class Enc_b97f71 : OpcodeHexagon {
2642  bits <6> Ii;
2643  let Inst{8-5} = Ii{5-2};
2644  bits <2> Pt4;
2645  let Inst{10-9} = Pt4{1-0};
2646  bits <5> Rd32;
2647  let Inst{4-0} = Rd32{4-0};
2648  bits <5> Rx32;
2649  let Inst{20-16} = Rx32{4-0};
2650}
2651class Enc_b9c5fb : OpcodeHexagon {
2652  bits <5> Rss32;
2653  let Inst{20-16} = Rss32{4-0};
2654  bits <5> Rdd32;
2655  let Inst{4-0} = Rdd32{4-0};
2656}
2657class Enc_bc03e5 : OpcodeHexagon {
2658  bits <17> Ii;
2659  let Inst{26-25} = Ii{16-15};
2660  let Inst{20-16} = Ii{14-10};
2661  let Inst{13-13} = Ii{9-9};
2662  let Inst{7-0} = Ii{8-1};
2663  bits <3> Nt8;
2664  let Inst{10-8} = Nt8{2-0};
2665}
2666class Enc_bd0b33 : OpcodeHexagon {
2667  bits <10> Ii;
2668  let Inst{21-21} = Ii{9-9};
2669  let Inst{13-5} = Ii{8-0};
2670  bits <5> Rs32;
2671  let Inst{20-16} = Rs32{4-0};
2672  bits <2> Pd4;
2673  let Inst{1-0} = Pd4{1-0};
2674}
2675class Enc_bd1cbc : OpcodeHexagon {
2676  bits <5> Ii;
2677  let Inst{8-5} = Ii{4-1};
2678  bits <5> Ryy32;
2679  let Inst{4-0} = Ryy32{4-0};
2680  bits <5> Rx32;
2681  let Inst{20-16} = Rx32{4-0};
2682}
2683class Enc_bd6011 : OpcodeHexagon {
2684  bits <5> Rt32;
2685  let Inst{12-8} = Rt32{4-0};
2686  bits <5> Rs32;
2687  let Inst{20-16} = Rs32{4-0};
2688  bits <5> Rd32;
2689  let Inst{4-0} = Rd32{4-0};
2690}
2691class Enc_bd811a : OpcodeHexagon {
2692  bits <5> Rs32;
2693  let Inst{20-16} = Rs32{4-0};
2694  bits <5> Cd32;
2695  let Inst{4-0} = Cd32{4-0};
2696}
2697class Enc_bddee3 : OpcodeHexagon {
2698  bits <5> Vu32;
2699  let Inst{12-8} = Vu32{4-0};
2700  bits <5> Vyyyy32;
2701  let Inst{4-0} = Vyyyy32{4-0};
2702  bits <3> Rx8;
2703  let Inst{18-16} = Rx8{2-0};
2704}
2705class Enc_be32a5 : OpcodeHexagon {
2706  bits <5> Rs32;
2707  let Inst{20-16} = Rs32{4-0};
2708  bits <5> Rt32;
2709  let Inst{12-8} = Rt32{4-0};
2710  bits <5> Rdd32;
2711  let Inst{4-0} = Rdd32{4-0};
2712}
2713class Enc_bfbf03 : OpcodeHexagon {
2714  bits <2> Qs4;
2715  let Inst{9-8} = Qs4{1-0};
2716  bits <2> Qd4;
2717  let Inst{1-0} = Qd4{1-0};
2718}
2719class Enc_c0cdde : OpcodeHexagon {
2720  bits <9> Ii;
2721  let Inst{13-5} = Ii{8-0};
2722  bits <5> Rs32;
2723  let Inst{20-16} = Rs32{4-0};
2724  bits <2> Pd4;
2725  let Inst{1-0} = Pd4{1-0};
2726}
2727class Enc_c175d0 : OpcodeHexagon {
2728  bits <4> Ii;
2729  let Inst{11-8} = Ii{3-0};
2730  bits <4> Rs16;
2731  let Inst{7-4} = Rs16{3-0};
2732  bits <4> Rd16;
2733  let Inst{3-0} = Rd16{3-0};
2734}
2735class Enc_c1d806 : OpcodeHexagon {
2736  bits <5> Vu32;
2737  let Inst{12-8} = Vu32{4-0};
2738  bits <5> Vv32;
2739  let Inst{20-16} = Vv32{4-0};
2740  bits <5> Vd32;
2741  let Inst{4-0} = Vd32{4-0};
2742  bits <2> Qe4;
2743  let Inst{6-5} = Qe4{1-0};
2744}
2745class Enc_c2b48e : OpcodeHexagon {
2746  bits <5> Rs32;
2747  let Inst{20-16} = Rs32{4-0};
2748  bits <5> Rt32;
2749  let Inst{12-8} = Rt32{4-0};
2750  bits <2> Pd4;
2751  let Inst{1-0} = Pd4{1-0};
2752}
2753class Enc_c31910 : OpcodeHexagon {
2754  bits <8> Ii;
2755  let Inst{23-21} = Ii{7-5};
2756  let Inst{13-13} = Ii{4-4};
2757  let Inst{7-5} = Ii{3-1};
2758  let Inst{3-3} = Ii{0-0};
2759  bits <5> II;
2760  let Inst{12-8} = II{4-0};
2761  bits <5> Rx32;
2762  let Inst{20-16} = Rx32{4-0};
2763}
2764class Enc_c4dc92 : OpcodeHexagon {
2765  bits <2> Qv4;
2766  let Inst{23-22} = Qv4{1-0};
2767  bits <5> Vu32;
2768  let Inst{12-8} = Vu32{4-0};
2769  bits <5> Vd32;
2770  let Inst{4-0} = Vd32{4-0};
2771}
2772class Enc_c6220b : OpcodeHexagon {
2773  bits <2> Ii;
2774  let Inst{13-13} = Ii{1-1};
2775  let Inst{7-7} = Ii{0-0};
2776  bits <5> Rs32;
2777  let Inst{20-16} = Rs32{4-0};
2778  bits <5> Ru32;
2779  let Inst{12-8} = Ru32{4-0};
2780  bits <3> Nt8;
2781  let Inst{2-0} = Nt8{2-0};
2782}
2783class Enc_c7a204 : OpcodeHexagon {
2784  bits <6> II;
2785  let Inst{5-0} = II{5-0};
2786  bits <5> Rtt32;
2787  let Inst{12-8} = Rtt32{4-0};
2788  bits <5> Re32;
2789  let Inst{20-16} = Re32{4-0};
2790}
2791class Enc_c7cd90 : OpcodeHexagon {
2792  bits <4> Ii;
2793  let Inst{6-3} = Ii{3-0};
2794  bits <3> Nt8;
2795  let Inst{10-8} = Nt8{2-0};
2796  bits <5> Rx32;
2797  let Inst{20-16} = Rx32{4-0};
2798}
2799class Enc_c85e2a : OpcodeHexagon {
2800  bits <5> Ii;
2801  let Inst{12-8} = Ii{4-0};
2802  bits <5> II;
2803  let Inst{22-21} = II{4-3};
2804  let Inst{7-5} = II{2-0};
2805  bits <5> Rd32;
2806  let Inst{4-0} = Rd32{4-0};
2807}
2808class Enc_c90aca : OpcodeHexagon {
2809  bits <8> Ii;
2810  let Inst{12-5} = Ii{7-0};
2811  bits <5> Rs32;
2812  let Inst{20-16} = Rs32{4-0};
2813  bits <5> Rx32;
2814  let Inst{4-0} = Rx32{4-0};
2815}
2816class Enc_c9a18e : OpcodeHexagon {
2817  bits <11> Ii;
2818  let Inst{21-20} = Ii{10-9};
2819  let Inst{7-1} = Ii{8-2};
2820  bits <3> Ns8;
2821  let Inst{18-16} = Ns8{2-0};
2822  bits <5> Rt32;
2823  let Inst{12-8} = Rt32{4-0};
2824}
2825class Enc_c9e3bc : OpcodeHexagon {
2826  bits <4> Ii;
2827  let Inst{13-13} = Ii{3-3};
2828  let Inst{10-8} = Ii{2-0};
2829  bits <5> Rt32;
2830  let Inst{20-16} = Rt32{4-0};
2831  bits <5> Vs32;
2832  let Inst{4-0} = Vs32{4-0};
2833}
2834class Enc_ca3887 : OpcodeHexagon {
2835  bits <5> Rs32;
2836  let Inst{20-16} = Rs32{4-0};
2837  bits <5> Rt32;
2838  let Inst{12-8} = Rt32{4-0};
2839}
2840class Enc_cb4b4e : OpcodeHexagon {
2841  bits <2> Pu4;
2842  let Inst{6-5} = Pu4{1-0};
2843  bits <5> Rs32;
2844  let Inst{20-16} = Rs32{4-0};
2845  bits <5> Rt32;
2846  let Inst{12-8} = Rt32{4-0};
2847  bits <5> Rdd32;
2848  let Inst{4-0} = Rdd32{4-0};
2849}
2850class Enc_cb785b : OpcodeHexagon {
2851  bits <5> Vu32;
2852  let Inst{12-8} = Vu32{4-0};
2853  bits <5> Rtt32;
2854  let Inst{20-16} = Rtt32{4-0};
2855  bits <5> Vdd32;
2856  let Inst{4-0} = Vdd32{4-0};
2857}
2858class Enc_cb9321 : OpcodeHexagon {
2859  bits <16> Ii;
2860  let Inst{27-21} = Ii{15-9};
2861  let Inst{13-5} = Ii{8-0};
2862  bits <5> Rs32;
2863  let Inst{20-16} = Rs32{4-0};
2864  bits <5> Rd32;
2865  let Inst{4-0} = Rd32{4-0};
2866}
2867class Enc_cc449f : OpcodeHexagon {
2868  bits <4> Ii;
2869  let Inst{6-3} = Ii{3-0};
2870  bits <2> Pv4;
2871  let Inst{1-0} = Pv4{1-0};
2872  bits <5> Rt32;
2873  let Inst{12-8} = Rt32{4-0};
2874  bits <5> Rx32;
2875  let Inst{20-16} = Rx32{4-0};
2876}
2877class Enc_cc857d : OpcodeHexagon {
2878  bits <5> Vuu32;
2879  let Inst{12-8} = Vuu32{4-0};
2880  bits <5> Rt32;
2881  let Inst{20-16} = Rt32{4-0};
2882  bits <5> Vx32;
2883  let Inst{4-0} = Vx32{4-0};
2884}
2885class Enc_cd4705 : OpcodeHexagon {
2886  bits <3> Ii;
2887  let Inst{7-5} = Ii{2-0};
2888  bits <5> Vu32;
2889  let Inst{12-8} = Vu32{4-0};
2890  bits <5> Vv32;
2891  let Inst{20-16} = Vv32{4-0};
2892  bits <5> Vx32;
2893  let Inst{4-0} = Vx32{4-0};
2894}
2895class Enc_cd82bc : OpcodeHexagon {
2896  bits <4> Ii;
2897  let Inst{21-21} = Ii{3-3};
2898  let Inst{7-5} = Ii{2-0};
2899  bits <6> II;
2900  let Inst{13-8} = II{5-0};
2901  bits <5> Rs32;
2902  let Inst{20-16} = Rs32{4-0};
2903  bits <5> Rx32;
2904  let Inst{4-0} = Rx32{4-0};
2905}
2906class Enc_cda00a : OpcodeHexagon {
2907  bits <12> Ii;
2908  let Inst{19-16} = Ii{11-8};
2909  let Inst{12-5} = Ii{7-0};
2910  bits <2> Pu4;
2911  let Inst{22-21} = Pu4{1-0};
2912  bits <5> Rd32;
2913  let Inst{4-0} = Rd32{4-0};
2914}
2915class Enc_ce6828 : OpcodeHexagon {
2916  bits <14> Ii;
2917  let Inst{26-25} = Ii{13-12};
2918  let Inst{13-13} = Ii{11-11};
2919  let Inst{7-0} = Ii{10-3};
2920  bits <5> Rs32;
2921  let Inst{20-16} = Rs32{4-0};
2922  bits <5> Rtt32;
2923  let Inst{12-8} = Rtt32{4-0};
2924}
2925class Enc_cf1927 : OpcodeHexagon {
2926  bits <1> Mu2;
2927  let Inst{13-13} = Mu2{0-0};
2928  bits <3> Os8;
2929  let Inst{2-0} = Os8{2-0};
2930  bits <5> Rx32;
2931  let Inst{20-16} = Rx32{4-0};
2932}
2933class Enc_d15d19 : OpcodeHexagon {
2934  bits <1> Mu2;
2935  let Inst{13-13} = Mu2{0-0};
2936  bits <5> Vs32;
2937  let Inst{4-0} = Vs32{4-0};
2938  bits <5> Rx32;
2939  let Inst{20-16} = Rx32{4-0};
2940}
2941class Enc_d2216a : OpcodeHexagon {
2942  bits <5> Rss32;
2943  let Inst{20-16} = Rss32{4-0};
2944  bits <5> Rtt32;
2945  let Inst{12-8} = Rtt32{4-0};
2946  bits <5> Rd32;
2947  let Inst{4-0} = Rd32{4-0};
2948}
2949class Enc_d2c7f1 : OpcodeHexagon {
2950  bits <5> Rtt32;
2951  let Inst{12-8} = Rtt32{4-0};
2952  bits <5> Rss32;
2953  let Inst{20-16} = Rss32{4-0};
2954  bits <5> Rdd32;
2955  let Inst{4-0} = Rdd32{4-0};
2956  bits <2> Pe4;
2957  let Inst{6-5} = Pe4{1-0};
2958}
2959class Enc_d44e31 : OpcodeHexagon {
2960  bits <6> Ii;
2961  let Inst{12-7} = Ii{5-0};
2962  bits <5> Rs32;
2963  let Inst{20-16} = Rs32{4-0};
2964  bits <5> Rt32;
2965  let Inst{4-0} = Rt32{4-0};
2966}
2967class Enc_d483b9 : OpcodeHexagon {
2968  bits <1> Ii;
2969  let Inst{5-5} = Ii{0-0};
2970  bits <5> Vuu32;
2971  let Inst{12-8} = Vuu32{4-0};
2972  bits <5> Rt32;
2973  let Inst{20-16} = Rt32{4-0};
2974  bits <5> Vxx32;
2975  let Inst{4-0} = Vxx32{4-0};
2976}
2977class Enc_d50cd3 : OpcodeHexagon {
2978  bits <3> Ii;
2979  let Inst{7-5} = Ii{2-0};
2980  bits <5> Rss32;
2981  let Inst{20-16} = Rss32{4-0};
2982  bits <5> Rtt32;
2983  let Inst{12-8} = Rtt32{4-0};
2984  bits <5> Rdd32;
2985  let Inst{4-0} = Rdd32{4-0};
2986}
2987class Enc_d5c73f : OpcodeHexagon {
2988  bits <1> Mu2;
2989  let Inst{13-13} = Mu2{0-0};
2990  bits <5> Rt32;
2991  let Inst{12-8} = Rt32{4-0};
2992  bits <5> Rx32;
2993  let Inst{20-16} = Rx32{4-0};
2994}
2995class Enc_d6990d : OpcodeHexagon {
2996  bits <5> Vuu32;
2997  let Inst{12-8} = Vuu32{4-0};
2998  bits <5> Rt32;
2999  let Inst{20-16} = Rt32{4-0};
3000  bits <5> Vxx32;
3001  let Inst{4-0} = Vxx32{4-0};
3002}
3003class Enc_d7a65e : OpcodeHexagon {
3004  bits <6> Ii;
3005  let Inst{12-7} = Ii{5-0};
3006  bits <6> II;
3007  let Inst{13-13} = II{5-5};
3008  let Inst{4-0} = II{4-0};
3009  bits <2> Pv4;
3010  let Inst{6-5} = Pv4{1-0};
3011  bits <5> Rs32;
3012  let Inst{20-16} = Rs32{4-0};
3013}
3014class Enc_d7bc34 : OpcodeHexagon {
3015  bits <5> Vu32;
3016  let Inst{12-8} = Vu32{4-0};
3017  bits <3> Rt8;
3018  let Inst{18-16} = Rt8{2-0};
3019  bits <5> Vyyyy32;
3020  let Inst{4-0} = Vyyyy32{4-0};
3021}
3022class Enc_d7dc10 : OpcodeHexagon {
3023  bits <5> Rs32;
3024  let Inst{20-16} = Rs32{4-0};
3025  bits <5> Rtt32;
3026  let Inst{12-8} = Rtt32{4-0};
3027  bits <2> Pd4;
3028  let Inst{1-0} = Pd4{1-0};
3029}
3030class Enc_da664b : OpcodeHexagon {
3031  bits <2> Ii;
3032  let Inst{13-13} = Ii{1-1};
3033  let Inst{7-7} = Ii{0-0};
3034  bits <5> Rs32;
3035  let Inst{20-16} = Rs32{4-0};
3036  bits <5> Rt32;
3037  let Inst{12-8} = Rt32{4-0};
3038  bits <5> Rd32;
3039  let Inst{4-0} = Rd32{4-0};
3040}
3041class Enc_da8d43 : OpcodeHexagon {
3042  bits <6> Ii;
3043  let Inst{13-13} = Ii{5-5};
3044  let Inst{7-3} = Ii{4-0};
3045  bits <2> Pv4;
3046  let Inst{1-0} = Pv4{1-0};
3047  bits <5> Rs32;
3048  let Inst{20-16} = Rs32{4-0};
3049  bits <5> Rt32;
3050  let Inst{12-8} = Rt32{4-0};
3051}
3052class Enc_daea09 : OpcodeHexagon {
3053  bits <17> Ii;
3054  let Inst{23-22} = Ii{16-15};
3055  let Inst{20-16} = Ii{14-10};
3056  let Inst{13-13} = Ii{9-9};
3057  let Inst{7-1} = Ii{8-2};
3058  bits <2> Pu4;
3059  let Inst{9-8} = Pu4{1-0};
3060}
3061class Enc_db40cd : OpcodeHexagon {
3062  bits <6> Ii;
3063  let Inst{6-3} = Ii{5-2};
3064  bits <5> Rt32;
3065  let Inst{12-8} = Rt32{4-0};
3066  bits <5> Rx32;
3067  let Inst{20-16} = Rx32{4-0};
3068}
3069class Enc_dbd70c : OpcodeHexagon {
3070  bits <5> Rss32;
3071  let Inst{20-16} = Rss32{4-0};
3072  bits <5> Rtt32;
3073  let Inst{12-8} = Rtt32{4-0};
3074  bits <2> Pu4;
3075  let Inst{6-5} = Pu4{1-0};
3076  bits <5> Rdd32;
3077  let Inst{4-0} = Rdd32{4-0};
3078}
3079class Enc_dd766a : OpcodeHexagon {
3080  bits <5> Vu32;
3081  let Inst{12-8} = Vu32{4-0};
3082  bits <5> Vdd32;
3083  let Inst{4-0} = Vdd32{4-0};
3084}
3085class Enc_de0214 : OpcodeHexagon {
3086  bits <12> Ii;
3087  let Inst{26-25} = Ii{11-10};
3088  let Inst{13-5} = Ii{9-1};
3089  bits <5> Rs32;
3090  let Inst{20-16} = Rs32{4-0};
3091  bits <5> Rd32;
3092  let Inst{4-0} = Rd32{4-0};
3093}
3094class Enc_e07374 : OpcodeHexagon {
3095  bits <5> Rs32;
3096  let Inst{20-16} = Rs32{4-0};
3097  bits <5> Rtt32;
3098  let Inst{12-8} = Rtt32{4-0};
3099  bits <5> Rd32;
3100  let Inst{4-0} = Rd32{4-0};
3101}
3102class Enc_e0820b : OpcodeHexagon {
3103  bits <5> Vu32;
3104  let Inst{12-8} = Vu32{4-0};
3105  bits <5> Vv32;
3106  let Inst{20-16} = Vv32{4-0};
3107  bits <2> Qs4;
3108  let Inst{6-5} = Qs4{1-0};
3109  bits <5> Vd32;
3110  let Inst{4-0} = Vd32{4-0};
3111}
3112class Enc_e0a47a : OpcodeHexagon {
3113  bits <4> Ii;
3114  let Inst{8-5} = Ii{3-0};
3115  bits <1> Mu2;
3116  let Inst{13-13} = Mu2{0-0};
3117  bits <5> Rd32;
3118  let Inst{4-0} = Rd32{4-0};
3119  bits <5> Rx32;
3120  let Inst{20-16} = Rx32{4-0};
3121}
3122class Enc_e26546 : OpcodeHexagon {
3123  bits <5> Ii;
3124  let Inst{6-3} = Ii{4-1};
3125  bits <3> Nt8;
3126  let Inst{10-8} = Nt8{2-0};
3127  bits <5> Rx32;
3128  let Inst{20-16} = Rx32{4-0};
3129}
3130class Enc_e38e1f : OpcodeHexagon {
3131  bits <8> Ii;
3132  let Inst{12-5} = Ii{7-0};
3133  bits <2> Pu4;
3134  let Inst{22-21} = Pu4{1-0};
3135  bits <5> Rs32;
3136  let Inst{20-16} = Rs32{4-0};
3137  bits <5> Rd32;
3138  let Inst{4-0} = Rd32{4-0};
3139}
3140class Enc_e39bb2 : OpcodeHexagon {
3141  bits <6> Ii;
3142  let Inst{9-4} = Ii{5-0};
3143  bits <4> Rd16;
3144  let Inst{3-0} = Rd16{3-0};
3145}
3146class Enc_e3b0c4 : OpcodeHexagon {
3147
3148}
3149class Enc_e66a97 : OpcodeHexagon {
3150  bits <7> Ii;
3151  let Inst{12-7} = Ii{6-1};
3152  bits <5> II;
3153  let Inst{4-0} = II{4-0};
3154  bits <5> Rs32;
3155  let Inst{20-16} = Rs32{4-0};
3156}
3157class Enc_e6abcf : OpcodeHexagon {
3158  bits <5> Rs32;
3159  let Inst{20-16} = Rs32{4-0};
3160  bits <5> Rtt32;
3161  let Inst{12-8} = Rtt32{4-0};
3162}
3163class Enc_e6c957 : OpcodeHexagon {
3164  bits <10> Ii;
3165  let Inst{21-21} = Ii{9-9};
3166  let Inst{13-5} = Ii{8-0};
3167  bits <5> Rdd32;
3168  let Inst{4-0} = Rdd32{4-0};
3169}
3170class Enc_e7581c : OpcodeHexagon {
3171  bits <5> Vu32;
3172  let Inst{12-8} = Vu32{4-0};
3173  bits <5> Vd32;
3174  let Inst{4-0} = Vd32{4-0};
3175}
3176class Enc_e83554 : OpcodeHexagon {
3177  bits <5> Ii;
3178  let Inst{8-5} = Ii{4-1};
3179  bits <1> Mu2;
3180  let Inst{13-13} = Mu2{0-0};
3181  bits <5> Rd32;
3182  let Inst{4-0} = Rd32{4-0};
3183  bits <5> Rx32;
3184  let Inst{20-16} = Rx32{4-0};
3185}
3186class Enc_e8c45e : OpcodeHexagon {
3187  bits <7> Ii;
3188  let Inst{13-13} = Ii{6-6};
3189  let Inst{7-3} = Ii{5-1};
3190  bits <2> Pv4;
3191  let Inst{1-0} = Pv4{1-0};
3192  bits <5> Rs32;
3193  let Inst{20-16} = Rs32{4-0};
3194  bits <5> Rt32;
3195  let Inst{12-8} = Rt32{4-0};
3196}
3197class Enc_e90a15 : OpcodeHexagon {
3198  bits <11> Ii;
3199  let Inst{21-20} = Ii{10-9};
3200  let Inst{7-1} = Ii{8-2};
3201  bits <3> Ns8;
3202  let Inst{18-16} = Ns8{2-0};
3203  bits <4> n1;
3204  let Inst{29-29} = n1{3-3};
3205  let Inst{26-25} = n1{2-1};
3206  let Inst{22-22} = n1{0-0};
3207}
3208class Enc_e957fb : OpcodeHexagon {
3209  bits <12> Ii;
3210  let Inst{26-25} = Ii{11-10};
3211  let Inst{13-13} = Ii{9-9};
3212  let Inst{7-0} = Ii{8-1};
3213  bits <5> Rs32;
3214  let Inst{20-16} = Rs32{4-0};
3215  bits <5> Rt32;
3216  let Inst{12-8} = Rt32{4-0};
3217}
3218class Enc_ea23e4 : OpcodeHexagon {
3219  bits <5> Rtt32;
3220  let Inst{12-8} = Rtt32{4-0};
3221  bits <5> Rss32;
3222  let Inst{20-16} = Rss32{4-0};
3223  bits <5> Rdd32;
3224  let Inst{4-0} = Rdd32{4-0};
3225}
3226class Enc_ea4c54 : OpcodeHexagon {
3227  bits <2> Pu4;
3228  let Inst{6-5} = Pu4{1-0};
3229  bits <5> Rs32;
3230  let Inst{20-16} = Rs32{4-0};
3231  bits <5> Rt32;
3232  let Inst{12-8} = Rt32{4-0};
3233  bits <5> Rd32;
3234  let Inst{4-0} = Rd32{4-0};
3235}
3236class Enc_eaa9f8 : OpcodeHexagon {
3237  bits <5> Vu32;
3238  let Inst{12-8} = Vu32{4-0};
3239  bits <5> Vv32;
3240  let Inst{20-16} = Vv32{4-0};
3241  bits <2> Qx4;
3242  let Inst{1-0} = Qx4{1-0};
3243}
3244class Enc_eafd18 : OpcodeHexagon {
3245  bits <5> II;
3246  let Inst{12-8} = II{4-0};
3247  bits <11> Ii;
3248  let Inst{21-20} = Ii{10-9};
3249  let Inst{7-1} = Ii{8-2};
3250  bits <3> Ns8;
3251  let Inst{18-16} = Ns8{2-0};
3252}
3253class Enc_eca7c8 : OpcodeHexagon {
3254  bits <2> Ii;
3255  let Inst{13-13} = Ii{1-1};
3256  let Inst{7-7} = Ii{0-0};
3257  bits <5> Rs32;
3258  let Inst{20-16} = Rs32{4-0};
3259  bits <5> Ru32;
3260  let Inst{12-8} = Ru32{4-0};
3261  bits <5> Rt32;
3262  let Inst{4-0} = Rt32{4-0};
3263}
3264class Enc_ecbcc8 : OpcodeHexagon {
3265  bits <5> Rs32;
3266  let Inst{20-16} = Rs32{4-0};
3267}
3268class Enc_ed48be : OpcodeHexagon {
3269  bits <2> Ii;
3270  let Inst{6-5} = Ii{1-0};
3271  bits <3> Rdd8;
3272  let Inst{2-0} = Rdd8{2-0};
3273}
3274class Enc_ed5027 : OpcodeHexagon {
3275  bits <5> Rss32;
3276  let Inst{20-16} = Rss32{4-0};
3277  bits <5> Gdd32;
3278  let Inst{4-0} = Gdd32{4-0};
3279}
3280class Enc_ee5ed0 : OpcodeHexagon {
3281  bits <4> Rs16;
3282  let Inst{7-4} = Rs16{3-0};
3283  bits <4> Rd16;
3284  let Inst{3-0} = Rd16{3-0};
3285  bits <2> n1;
3286  let Inst{9-8} = n1{1-0};
3287}
3288class Enc_ef601b : OpcodeHexagon {
3289  bits <4> Ii;
3290  let Inst{13-13} = Ii{3-3};
3291  let Inst{10-8} = Ii{2-0};
3292  bits <2> Pv4;
3293  let Inst{12-11} = Pv4{1-0};
3294  bits <5> Rt32;
3295  let Inst{20-16} = Rt32{4-0};
3296}
3297class Enc_efaed8 : OpcodeHexagon {
3298  bits <1> Ii;
3299  let Inst{8-8} = Ii{0-0};
3300}
3301class Enc_f0cca7 : OpcodeHexagon {
3302  bits <8> Ii;
3303  let Inst{12-5} = Ii{7-0};
3304  bits <6> II;
3305  let Inst{20-16} = II{5-1};
3306  let Inst{13-13} = II{0-0};
3307  bits <5> Rdd32;
3308  let Inst{4-0} = Rdd32{4-0};
3309}
3310class Enc_f20719 : OpcodeHexagon {
3311  bits <7> Ii;
3312  let Inst{12-7} = Ii{6-1};
3313  bits <6> II;
3314  let Inst{13-13} = II{5-5};
3315  let Inst{4-0} = II{4-0};
3316  bits <2> Pv4;
3317  let Inst{6-5} = Pv4{1-0};
3318  bits <5> Rs32;
3319  let Inst{20-16} = Rs32{4-0};
3320}
3321class Enc_f37377 : OpcodeHexagon {
3322  bits <8> Ii;
3323  let Inst{12-7} = Ii{7-2};
3324  bits <8> II;
3325  let Inst{13-13} = II{7-7};
3326  let Inst{6-0} = II{6-0};
3327  bits <5> Rs32;
3328  let Inst{20-16} = Rs32{4-0};
3329}
3330class Enc_f394d3 : OpcodeHexagon {
3331  bits <6> II;
3332  let Inst{11-8} = II{5-2};
3333  let Inst{6-5} = II{1-0};
3334  bits <5> Ryy32;
3335  let Inst{4-0} = Ryy32{4-0};
3336  bits <5> Re32;
3337  let Inst{20-16} = Re32{4-0};
3338}
3339class Enc_f3f408 : OpcodeHexagon {
3340  bits <4> Ii;
3341  let Inst{13-13} = Ii{3-3};
3342  let Inst{10-8} = Ii{2-0};
3343  bits <5> Rt32;
3344  let Inst{20-16} = Rt32{4-0};
3345  bits <5> Vd32;
3346  let Inst{4-0} = Vd32{4-0};
3347}
3348class Enc_f4413a : OpcodeHexagon {
3349  bits <4> Ii;
3350  let Inst{8-5} = Ii{3-0};
3351  bits <2> Pt4;
3352  let Inst{10-9} = Pt4{1-0};
3353  bits <5> Rd32;
3354  let Inst{4-0} = Rd32{4-0};
3355  bits <5> Rx32;
3356  let Inst{20-16} = Rx32{4-0};
3357}
3358class Enc_f44229 : OpcodeHexagon {
3359  bits <7> Ii;
3360  let Inst{13-13} = Ii{6-6};
3361  let Inst{7-3} = Ii{5-1};
3362  bits <2> Pv4;
3363  let Inst{1-0} = Pv4{1-0};
3364  bits <5> Rs32;
3365  let Inst{20-16} = Rs32{4-0};
3366  bits <3> Nt8;
3367  let Inst{10-8} = Nt8{2-0};
3368}
3369class Enc_f4f57b : OpcodeHexagon {
3370  bits <2> Ii;
3371  let Inst{6-5} = Ii{1-0};
3372  bits <5> Vuu32;
3373  let Inst{12-8} = Vuu32{4-0};
3374  bits <5> Vvv32;
3375  let Inst{20-16} = Vvv32{4-0};
3376  bits <5> Vxx32;
3377  let Inst{4-0} = Vxx32{4-0};
3378}
3379class Enc_f55a0c : OpcodeHexagon {
3380  bits <6> Ii;
3381  let Inst{11-8} = Ii{5-2};
3382  bits <4> Rs16;
3383  let Inst{7-4} = Rs16{3-0};
3384  bits <4> Rt16;
3385  let Inst{3-0} = Rt16{3-0};
3386}
3387class Enc_f5e933 : OpcodeHexagon {
3388  bits <2> Ps4;
3389  let Inst{17-16} = Ps4{1-0};
3390  bits <5> Rd32;
3391  let Inst{4-0} = Rd32{4-0};
3392}
3393class Enc_f6fe0b : OpcodeHexagon {
3394  bits <11> Ii;
3395  let Inst{21-20} = Ii{10-9};
3396  let Inst{7-1} = Ii{8-2};
3397  bits <4> Rs16;
3398  let Inst{19-16} = Rs16{3-0};
3399  bits <6> n1;
3400  let Inst{28-28} = n1{5-5};
3401  let Inst{24-22} = n1{4-2};
3402  let Inst{13-13} = n1{1-1};
3403  let Inst{8-8} = n1{0-0};
3404}
3405class Enc_f7430e : OpcodeHexagon {
3406  bits <4> Ii;
3407  let Inst{13-13} = Ii{3-3};
3408  let Inst{10-8} = Ii{2-0};
3409  bits <2> Pv4;
3410  let Inst{12-11} = Pv4{1-0};
3411  bits <5> Rt32;
3412  let Inst{20-16} = Rt32{4-0};
3413  bits <3> Os8;
3414  let Inst{2-0} = Os8{2-0};
3415}
3416class Enc_f77fbc : OpcodeHexagon {
3417  bits <4> Ii;
3418  let Inst{13-13} = Ii{3-3};
3419  let Inst{10-8} = Ii{2-0};
3420  bits <5> Rt32;
3421  let Inst{20-16} = Rt32{4-0};
3422  bits <3> Os8;
3423  let Inst{2-0} = Os8{2-0};
3424}
3425class Enc_f79415 : OpcodeHexagon {
3426  bits <2> Ii;
3427  let Inst{13-13} = Ii{1-1};
3428  let Inst{6-6} = Ii{0-0};
3429  bits <6> II;
3430  let Inst{5-0} = II{5-0};
3431  bits <5> Ru32;
3432  let Inst{20-16} = Ru32{4-0};
3433  bits <5> Rtt32;
3434  let Inst{12-8} = Rtt32{4-0};
3435}
3436class Enc_f7ea77 : OpcodeHexagon {
3437  bits <11> Ii;
3438  let Inst{21-20} = Ii{10-9};
3439  let Inst{7-1} = Ii{8-2};
3440  bits <3> Ns8;
3441  let Inst{18-16} = Ns8{2-0};
3442  bits <4> n1;
3443  let Inst{29-29} = n1{3-3};
3444  let Inst{26-25} = n1{2-1};
3445  let Inst{13-13} = n1{0-0};
3446}
3447class Enc_f82302 : OpcodeHexagon {
3448  bits <11> Ii;
3449  let Inst{21-20} = Ii{10-9};
3450  let Inst{7-1} = Ii{8-2};
3451  bits <3> Ns8;
3452  let Inst{18-16} = Ns8{2-0};
3453  bits <4> n1;
3454  let Inst{29-29} = n1{3-3};
3455  let Inst{26-25} = n1{2-1};
3456  let Inst{23-23} = n1{0-0};
3457}
3458class Enc_f82eaf : OpcodeHexagon {
3459  bits <8> Ii;
3460  let Inst{10-5} = Ii{7-2};
3461  bits <2> Pt4;
3462  let Inst{12-11} = Pt4{1-0};
3463  bits <5> Rs32;
3464  let Inst{20-16} = Rs32{4-0};
3465  bits <5> Rd32;
3466  let Inst{4-0} = Rd32{4-0};
3467}
3468class Enc_f8c1c4 : OpcodeHexagon {
3469  bits <2> Pv4;
3470  let Inst{12-11} = Pv4{1-0};
3471  bits <1> Mu2;
3472  let Inst{13-13} = Mu2{0-0};
3473  bits <5> Vd32;
3474  let Inst{4-0} = Vd32{4-0};
3475  bits <5> Rx32;
3476  let Inst{20-16} = Rx32{4-0};
3477}
3478class Enc_f8ecf9 : OpcodeHexagon {
3479  bits <5> Vuu32;
3480  let Inst{12-8} = Vuu32{4-0};
3481  bits <5> Vvv32;
3482  let Inst{20-16} = Vvv32{4-0};
3483  bits <5> Vdd32;
3484  let Inst{4-0} = Vdd32{4-0};
3485}
3486class Enc_fa3ba4 : OpcodeHexagon {
3487  bits <14> Ii;
3488  let Inst{26-25} = Ii{13-12};
3489  let Inst{13-5} = Ii{11-3};
3490  bits <5> Rs32;
3491  let Inst{20-16} = Rs32{4-0};
3492  bits <5> Rdd32;
3493  let Inst{4-0} = Rdd32{4-0};
3494}
3495class Enc_fb6577 : OpcodeHexagon {
3496  bits <2> Pu4;
3497  let Inst{9-8} = Pu4{1-0};
3498  bits <5> Rs32;
3499  let Inst{20-16} = Rs32{4-0};
3500  bits <5> Rd32;
3501  let Inst{4-0} = Rd32{4-0};
3502}
3503class Enc_fcf7a7 : OpcodeHexagon {
3504  bits <5> Rss32;
3505  let Inst{20-16} = Rss32{4-0};
3506  bits <5> Rtt32;
3507  let Inst{12-8} = Rtt32{4-0};
3508  bits <2> Pd4;
3509  let Inst{1-0} = Pd4{1-0};
3510}
3511class Enc_fda92c : OpcodeHexagon {
3512  bits <17> Ii;
3513  let Inst{26-25} = Ii{16-15};
3514  let Inst{20-16} = Ii{14-10};
3515  let Inst{13-13} = Ii{9-9};
3516  let Inst{7-0} = Ii{8-1};
3517  bits <5> Rt32;
3518  let Inst{12-8} = Rt32{4-0};
3519}
3520class Enc_fef969 : OpcodeHexagon {
3521  bits <6> Ii;
3522  let Inst{20-16} = Ii{5-1};
3523  let Inst{5-5} = Ii{0-0};
3524  bits <5> Rt32;
3525  let Inst{12-8} = Rt32{4-0};
3526  bits <5> Rd32;
3527  let Inst{4-0} = Rd32{4-0};
3528}
3529class Enc_ff3442 : OpcodeHexagon {
3530  bits <4> Ii;
3531  let Inst{13-13} = Ii{3-3};
3532  let Inst{10-8} = Ii{2-0};
3533  bits <5> Rt32;
3534  let Inst{20-16} = Rt32{4-0};
3535}
3536