1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the Hexagon target. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// Hexagon Subtarget features. 21//===----------------------------------------------------------------------===// 22 23// Hexagon Architectures 24include "HexagonDepArch.td" 25 26def ProcTinyCore: SubtargetFeature<"tinycore", "HexagonProcFamily", 27 "TinyCore", "Hexagon Tiny Core">; 28 29// Hexagon ISA Extensions 30def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true", 31 "Hexagon ZReg extension instructions">; 32def ExtensionHVXQFloat: SubtargetFeature<"hvx-qfloat", "UseHVXQFloatOps", 33 "true", "Hexagon HVX QFloating point instructions">; 34 35def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", 36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; 37def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", 38 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions", 39 [ExtensionHVX]>; 40def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", 41 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", 42 [ExtensionHVX, ExtensionHVXV60]>; 43def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion", 44 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions", 45 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>; 46def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion", 47 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions", 48 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, 49 ExtensionZReg]>; 50def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion", 51 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions", 52 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>; 53def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion", 54 "Hexagon::ArchEnum::V68", "Hexagon HVX instructions", 55 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66, 56 ExtensionHVXV67]>; 57def ExtensionHVXV69: SubtargetFeature<"hvxv69", "HexagonHVXVersion", 58 "Hexagon::ArchEnum::V69", "Hexagon HVX instructions", 59 [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66, 60 ExtensionHVXV67, ExtensionHVXV68]>; 61 62def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", 63 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>; 64def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", 65 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>; 66 67def ExtensionAudio: SubtargetFeature<"audio", "UseAudioOps", "true", 68 "Hexagon Audio extension instructions">; 69 70def ExtensionHVXIEEEFP: SubtargetFeature<"hvx-ieee-fp", "UseHVXIEEEFPOps", 71 "true", "Hexagon HVX IEEE floating point instructions">; 72 73def FeatureCompound: SubtargetFeature<"compound", "UseCompound", "true", 74 "Use compound instructions">; 75def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true", 76 "Support for instruction packets">; 77def FeaturePreV65: SubtargetFeature<"prev65", "HasPreV65", "true", 78 "Support features deprecated in v65">; 79def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", 80 "Use constant-extended calls">; 81def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", 82 "Supports mem_noshuf feature">; 83def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true", 84 "Use memop instructions">; 85def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true", 86 "Support for new-value jumps", [FeaturePackets]>; 87def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true", 88 "Support for new-value stores", [FeaturePackets]>; 89def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true", 90 "Allow GP-relative addressing of global variables">; 91def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", 92 "Enable generation of duplex instruction">; 93def FeatureUnsafeFP: SubtargetFeature<"unsafe-fp", "UseUnsafeMath", "true", 94 "Use unsafe FP math">; 95def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", 96 "true", "Reserve register R19">; 97def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim", 98 "NoreturnStackElim", "true", 99 "Eliminate stack allocation in a noreturn function when possible">; 100def FeatureCabac: SubtargetFeature<"cabac", "UseCabac", "false", 101 "Emit the CABAC instruction">; 102 103//===----------------------------------------------------------------------===// 104// Hexagon Instruction Predicate Definitions. 105//===----------------------------------------------------------------------===// 106 107def UseMEMOPS : Predicate<"HST->useMemops()">; 108def UseHVX64B : Predicate<"HST->useHVX64BOps()">, 109 AssemblerPredicate<(all_of ExtensionHVX64B)>; 110def UseHVX128B : Predicate<"HST->useHVX128BOps()">, 111 AssemblerPredicate<(all_of ExtensionHVX128B)>; 112def UseHVX : Predicate<"HST->useHVXOps()">, 113 AssemblerPredicate<(all_of ExtensionHVXV60)>; 114def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">, 115 AssemblerPredicate<(all_of ExtensionHVXV60)>; 116def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">, 117 AssemblerPredicate<(all_of ExtensionHVXV62)>; 118def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">, 119 AssemblerPredicate<(all_of ExtensionHVXV65)>; 120def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">, 121 AssemblerPredicate<(all_of ExtensionHVXV66)>; 122def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">, 123 AssemblerPredicate<(all_of ExtensionHVXV67)>; 124def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">, 125 AssemblerPredicate<(all_of ExtensionHVXV68)>; 126def UseHVXV69 : Predicate<"HST->useHVXV69Ops()">, 127 AssemblerPredicate<(all_of ExtensionHVXV69)>; 128def UseAudio : Predicate<"HST->useAudioOps()">, 129 AssemblerPredicate<(all_of ExtensionAudio)>; 130def UseZReg : Predicate<"HST->useZRegOps()">, 131 AssemblerPredicate<(all_of ExtensionZReg)>; 132def UseCompound : Predicate<"HST->useCompound()">; 133def HasPreV65 : Predicate<"HST->hasPreV65()">, 134 AssemblerPredicate<(all_of FeaturePreV65)>; 135def UseHVXIEEEFP : Predicate<"HST->useHVXIEEEFPOps()">, 136 AssemblerPredicate<(all_of ExtensionHVXIEEEFP)>; 137def UseHVXQFloat : Predicate<"HST->useHVXQFloatOps()">, 138 AssemblerPredicate<(all_of ExtensionHVXQFloat)>; 139def UseHVXFloatingPoint: Predicate<"HST->useHVXFloatingPoint()">; 140def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">, 141 AssemblerPredicate<(all_of FeatureMemNoShuf)>; 142def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">; 143def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||" 144 "MF->getFunction().hasOptSize()"> { 145 let RecomputePerFunction = 1; 146} 147def UseSmallData : Predicate<"HST->useSmallData()">; 148def UseCabac : Predicate<"HST->useCabac()">, 149 AssemblerPredicate<(any_of FeatureCabac)>; 150 151def Hvx64: HwMode<"+hvx-length64b">; 152def Hvx128: HwMode<"+hvx-length128b">; 153 154//===----------------------------------------------------------------------===// 155// Classes used for relation maps. 156//===----------------------------------------------------------------------===// 157 158// The classes below should remain in hierarchical order... 159class ImmRegShl; 160// ImmRegRel - Filter class used to relate instructions having reg-reg form 161// with their reg-imm counterparts. 162class ImmRegRel; 163// PredRel - Filter class used to relate non-predicated instructions with their 164// predicated forms. 165class PredRel; 166class PredNewRel: PredRel; 167// NewValueRel - Filter class used to relate regular store instructions with 168// their new-value store form. 169class NewValueRel: PredNewRel; 170class AddrModeRel: NewValueRel; 171class PostInc_BaseImm; 172class IntrinsicsRel; 173// ... through here. 174 175//===----------------------------------------------------------------------===// 176// Generate mapping table to relate non-predicate instructions with their 177// predicated formats - true and false. 178// 179 180def getPredOpcode : InstrMapping { 181 let FilterClass = "PredRel"; 182 // Instructions with the same BaseOpcode and isNVStore values form a row. 183 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; 184 // Instructions with the same predicate sense form a column. 185 let ColFields = ["PredSense"]; 186 // The key column is the unpredicated instructions. 187 let KeyCol = [""]; 188 // Value columns are PredSense=true and PredSense=false 189 let ValueCols = [["true"], ["false"]]; 190} 191 192//===----------------------------------------------------------------------===// 193// Generate mapping table to relate predicate-true instructions with their 194// predicate-false forms 195// 196def getFalsePredOpcode : InstrMapping { 197 let FilterClass = "PredRel"; 198 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 199 let ColFields = ["PredSense"]; 200 let KeyCol = ["true"]; 201 let ValueCols = [["false"]]; 202} 203 204//===----------------------------------------------------------------------===// 205// Generate mapping table to relate predicate-false instructions with their 206// predicate-true forms 207// 208def getTruePredOpcode : InstrMapping { 209 let FilterClass = "PredRel"; 210 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 211 let ColFields = ["PredSense"]; 212 let KeyCol = ["false"]; 213 let ValueCols = [["true"]]; 214} 215 216//===----------------------------------------------------------------------===// 217// Generate mapping table to relate predicated instructions with their .new 218// format. 219// 220def getPredNewOpcode : InstrMapping { 221 let FilterClass = "PredNewRel"; 222 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 223 let ColFields = ["PNewValue"]; 224 let KeyCol = [""]; 225 let ValueCols = [["new"]]; 226} 227 228//===----------------------------------------------------------------------===// 229// Generate mapping table to relate .new predicated instructions with their old 230// format. 231// 232def getPredOldOpcode : InstrMapping { 233 let FilterClass = "PredNewRel"; 234 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 235 let ColFields = ["PNewValue"]; 236 let KeyCol = ["new"]; 237 let ValueCols = [[""]]; 238} 239 240//===----------------------------------------------------------------------===// 241// Generate mapping table to relate store instructions with their new-value 242// format. 243// 244def getNewValueOpcode : InstrMapping { 245 let FilterClass = "NewValueRel"; 246 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 247 let ColFields = ["NValueST"]; 248 let KeyCol = ["false"]; 249 let ValueCols = [["true"]]; 250} 251 252//===----------------------------------------------------------------------===// 253// Generate mapping table to relate new-value store instructions with their old 254// format. 255// 256def getNonNVStore : InstrMapping { 257 let FilterClass = "NewValueRel"; 258 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 259 let ColFields = ["NValueST"]; 260 let KeyCol = ["true"]; 261 let ValueCols = [["false"]]; 262} 263 264def changeAddrMode_abs_io: InstrMapping { 265 let FilterClass = "AddrModeRel"; 266 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 267 "isFloat"]; 268 let ColFields = ["addrMode"]; 269 let KeyCol = ["Absolute"]; 270 let ValueCols = [["BaseImmOffset"]]; 271} 272 273def changeAddrMode_io_abs: InstrMapping { 274 let FilterClass = "AddrModeRel"; 275 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 276 "isFloat"]; 277 let ColFields = ["addrMode"]; 278 let KeyCol = ["BaseImmOffset"]; 279 let ValueCols = [["Absolute"]]; 280} 281 282def changeAddrMode_io_rr: InstrMapping { 283 let FilterClass = "AddrModeRel"; 284 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 285 let ColFields = ["addrMode"]; 286 let KeyCol = ["BaseImmOffset"]; 287 let ValueCols = [["BaseRegOffset"]]; 288} 289 290def changeAddrMode_rr_io: InstrMapping { 291 let FilterClass = "AddrModeRel"; 292 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 293 let ColFields = ["addrMode"]; 294 let KeyCol = ["BaseRegOffset"]; 295 let ValueCols = [["BaseImmOffset"]]; 296} 297 298def changeAddrMode_pi_io: InstrMapping { 299 let FilterClass = "PostInc_BaseImm"; 300 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 301 let ColFields = ["addrMode"]; 302 let KeyCol = ["PostInc"]; 303 let ValueCols = [["BaseImmOffset"]]; 304} 305 306def changeAddrMode_io_pi: InstrMapping { 307 let FilterClass = "PostInc_BaseImm"; 308 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 309 let ColFields = ["addrMode"]; 310 let KeyCol = ["BaseImmOffset"]; 311 let ValueCols = [["PostInc"]]; 312} 313 314def changeAddrMode_rr_ur: InstrMapping { 315 let FilterClass = "ImmRegShl"; 316 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 317 let ColFields = ["addrMode"]; 318 let KeyCol = ["BaseRegOffset"]; 319 let ValueCols = [["BaseLongOffset"]]; 320} 321 322def changeAddrMode_ur_rr: InstrMapping { 323 let FilterClass = "ImmRegShl"; 324 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 325 let ColFields = ["addrMode"]; 326 let KeyCol = ["BaseLongOffset"]; 327 let ValueCols = [["BaseRegOffset"]]; 328} 329 330def getRegForm : InstrMapping { 331 let FilterClass = "ImmRegRel"; 332 let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 333 let ColFields = ["InputType"]; 334 let KeyCol = ["imm"]; 335 let ValueCols = [["reg"]]; 336} 337 338def notTakenBranchPrediction : InstrMapping { 339 let FilterClass = "PredRel"; 340 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 341 let ColFields = ["isBrTaken"]; 342 let KeyCol = ["true"]; 343 let ValueCols = [["false"]]; 344} 345 346def takenBranchPrediction : InstrMapping { 347 let FilterClass = "PredRel"; 348 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 349 let ColFields = ["isBrTaken"]; 350 let KeyCol = ["false"]; 351 let ValueCols = [["true"]]; 352} 353 354def getRealHWInstr : InstrMapping { 355 let FilterClass = "IntrinsicsRel"; 356 let RowFields = ["BaseOpcode"]; 357 let ColFields = ["InstrType"]; 358 let KeyCol = ["Pseudo"]; 359 let ValueCols = [["Pseudo"], ["Real"]]; 360} 361//===----------------------------------------------------------------------===// 362// Register File, Instruction Descriptions 363//===----------------------------------------------------------------------===// 364include "HexagonSchedule.td" 365include "HexagonRegisterInfo.td" 366include "HexagonOperands.td" 367include "HexagonDepOperands.td" 368include "HexagonDepITypes.td" 369include "HexagonInstrFormats.td" 370include "HexagonDepInstrFormats.td" 371include "HexagonDepInstrInfo.td" 372include "HexagonCallingConv.td" 373include "HexagonPseudo.td" 374include "HexagonPatterns.td" 375include "HexagonPatternsHVX.td" 376include "HexagonPatternsV65.td" 377include "HexagonDepMappings.td" 378include "HexagonIntrinsics.td" 379 380def HexagonInstrInfo : InstrInfo; 381 382//===----------------------------------------------------------------------===// 383// Hexagon processors supported. 384//===----------------------------------------------------------------------===// 385 386class Proc<string Name, SchedMachineModel Model, 387 list<SubtargetFeature> Features> 388 : ProcessorModel<Name, Model, Features>; 389 390def : Proc<"generic", HexagonModelV60, 391 [ArchV5, ArchV55, ArchV60, 392 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 393 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 394 FeatureCabac]>; 395def : Proc<"hexagonv5", HexagonModelV5, 396 [ArchV5, 397 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 398 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 399 FeatureCabac]>; 400def : Proc<"hexagonv55", HexagonModelV55, 401 [ArchV5, ArchV55, 402 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 403 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 404 FeatureCabac]>; 405def : Proc<"hexagonv60", HexagonModelV60, 406 [ArchV5, ArchV55, ArchV60, 407 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 408 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 409 FeatureCabac]>; 410def : Proc<"hexagonv62", HexagonModelV62, 411 [ArchV5, ArchV55, ArchV60, ArchV62, 412 FeatureCompound, FeatureDuplex, FeaturePreV65, FeatureMemops, 413 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 414 FeatureCabac]>; 415def : Proc<"hexagonv65", HexagonModelV65, 416 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, 417 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 418 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 419 FeatureCabac]>; 420def : Proc<"hexagonv66", HexagonModelV66, 421 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, 422 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 423 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 424 FeatureCabac]>; 425def : Proc<"hexagonv67", HexagonModelV67, 426 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 427 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 428 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 429 FeatureCabac]>; 430def : Proc<"hexagonv68", HexagonModelV68, 431 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 432 ArchV68, 433 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 434 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 435 FeatureCabac]>; 436def : Proc<"hexagonv69", HexagonModelV69, 437 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 438 ArchV68, ArchV69, 439 FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, 440 FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData, 441 FeatureCabac]>; 442// Need to update the correct features for tiny core. 443// Disable NewValueJumps since the packetizer is unable to handle a packet with 444// a new value jump and another SLOT0 instruction. 445def : Proc<"hexagonv67t", HexagonModelV67T, 446 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, 447 ProcTinyCore, ExtensionAudio, 448 FeatureCompound, FeatureMemNoShuf, FeatureMemops, 449 FeatureNVS, FeaturePackets, FeatureSmallData]>; 450 451//===----------------------------------------------------------------------===// 452// Declare the target which we are implementing 453//===----------------------------------------------------------------------===// 454 455def HexagonAsmParser : AsmParser { 456 let ShouldEmitMatchRegisterAltName = 1; 457 bit HasMnemonicFirst = 0; 458} 459 460def HexagonAsmParserVariant : AsmParserVariant { 461 int Variant = 0; 462 string TokenizingCharacters = "#()=:.<>!+*-|^&"; 463 string BreakCharacters = ""; 464} 465 466def HexagonAsmWriter : AsmWriter { 467 string AsmWriterClassName = "InstPrinter"; 468 bit isMCAsmWriter = 1; 469} 470 471def Hexagon : Target { 472 let InstructionSet = HexagonInstrInfo; 473 let AssemblyParsers = [HexagonAsmParser]; 474 let AssemblyParserVariants = [HexagonAsmParserVariant]; 475 let AssemblyWriters = [HexagonAsmWriter]; 476 let AllowRegisterRenaming = 1; 477} 478