1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the Hexagon target. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// Hexagon Subtarget features. 21//===----------------------------------------------------------------------===// 22 23// Hexagon Architectures 24include "HexagonDepArch.td" 25 26// Hexagon ISA Extensions 27def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true", 28 "Hexagon ZReg extension instructions">; 29 30def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", 31 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; 32def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", 33 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions", 34 [ExtensionHVX]>; 35def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", 36 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", 37 [ExtensionHVX, ExtensionHVXV60]>; 38def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion", 39 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions", 40 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>; 41def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion", 42 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions", 43 [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, 44 ExtensionZReg]>; 45 46def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", 47 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>; 48def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps", 49 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>; 50 51def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true", 52 "Support for instruction packets">; 53def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", 54 "Use constant-extended calls">; 55def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", 56 "Supports mem_noshuf feature">; 57def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true", 58 "Use memop instructions">; 59def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true", 60 "Support for new-value jumps", [FeaturePackets]>; 61def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true", 62 "Support for new-value stores", [FeaturePackets]>; 63def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true", 64 "Allow GP-relative addressing of global variables">; 65def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", 66 "Enable generation of duplex instruction">; 67def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", 68 "true", "Reserve register R19">; 69def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim", 70 "NoreturnStackElim", "true", 71 "Eliminate stack allocation in a noreturn function when possible">; 72 73//===----------------------------------------------------------------------===// 74// Hexagon Instruction Predicate Definitions. 75//===----------------------------------------------------------------------===// 76 77def UseMEMOPS : Predicate<"HST->useMemops()">; 78def UseHVX64B : Predicate<"HST->useHVX64BOps()">, 79 AssemblerPredicate<"ExtensionHVX64B">; 80def UseHVX128B : Predicate<"HST->useHVX128BOps()">, 81 AssemblerPredicate<"ExtensionHVX128B">; 82def UseHVX : Predicate<"HST->useHVXOps()">, 83 AssemblerPredicate<"ExtensionHVXV60">; 84def UseHVXV60 : Predicate<"HST->useHVXOps()">, 85 AssemblerPredicate<"ExtensionHVXV60">; 86def UseHVXV62 : Predicate<"HST->useHVXOps()">, 87 AssemblerPredicate<"ExtensionHVXV62">; 88def UseHVXV65 : Predicate<"HST->useHVXOps()">, 89 AssemblerPredicate<"ExtensionHVXV65">; 90def UseHVXV66 : Predicate<"HST->useHVXOps()">, 91 AssemblerPredicate<"ExtensionHVXV66">; 92def UseZReg : Predicate<"HST->useZRegOps()">, 93 AssemblerPredicate<"ExtensionZReg">; 94 95def Hvx64: HwMode<"+hvx-length64b">; 96def Hvx128: HwMode<"+hvx-length128b">; 97 98//===----------------------------------------------------------------------===// 99// Classes used for relation maps. 100//===----------------------------------------------------------------------===// 101 102class ImmRegShl; 103// ImmRegRel - Filter class used to relate instructions having reg-reg form 104// with their reg-imm counterparts. 105class ImmRegRel; 106// PredRel - Filter class used to relate non-predicated instructions with their 107// predicated forms. 108class PredRel; 109// PredNewRel - Filter class used to relate predicated instructions with their 110// predicate-new forms. 111class PredNewRel: PredRel; 112// NewValueRel - Filter class used to relate regular store instructions with 113// their new-value store form. 114class NewValueRel: PredNewRel; 115// NewValueRel - Filter class used to relate load/store instructions having 116// different addressing modes with each other. 117class AddrModeRel: NewValueRel; 118class PostInc_BaseImm; 119class IntrinsicsRel; 120 121//===----------------------------------------------------------------------===// 122// Generate mapping table to relate non-predicate instructions with their 123// predicated formats - true and false. 124// 125 126def getPredOpcode : InstrMapping { 127 let FilterClass = "PredRel"; 128 // Instructions with the same BaseOpcode and isNVStore values form a row. 129 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; 130 // Instructions with the same predicate sense form a column. 131 let ColFields = ["PredSense"]; 132 // The key column is the unpredicated instructions. 133 let KeyCol = [""]; 134 // Value columns are PredSense=true and PredSense=false 135 let ValueCols = [["true"], ["false"]]; 136} 137 138//===----------------------------------------------------------------------===// 139// Generate mapping table to relate predicate-true instructions with their 140// predicate-false forms 141// 142def getFalsePredOpcode : InstrMapping { 143 let FilterClass = "PredRel"; 144 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 145 let ColFields = ["PredSense"]; 146 let KeyCol = ["true"]; 147 let ValueCols = [["false"]]; 148} 149 150//===----------------------------------------------------------------------===// 151// Generate mapping table to relate predicate-false instructions with their 152// predicate-true forms 153// 154def getTruePredOpcode : InstrMapping { 155 let FilterClass = "PredRel"; 156 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"]; 157 let ColFields = ["PredSense"]; 158 let KeyCol = ["false"]; 159 let ValueCols = [["true"]]; 160} 161 162//===----------------------------------------------------------------------===// 163// Generate mapping table to relate predicated instructions with their .new 164// format. 165// 166def getPredNewOpcode : InstrMapping { 167 let FilterClass = "PredNewRel"; 168 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 169 let ColFields = ["PNewValue"]; 170 let KeyCol = [""]; 171 let ValueCols = [["new"]]; 172} 173 174//===----------------------------------------------------------------------===// 175// Generate mapping table to relate .new predicated instructions with their old 176// format. 177// 178def getPredOldOpcode : InstrMapping { 179 let FilterClass = "PredNewRel"; 180 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; 181 let ColFields = ["PNewValue"]; 182 let KeyCol = ["new"]; 183 let ValueCols = [[""]]; 184} 185 186//===----------------------------------------------------------------------===// 187// Generate mapping table to relate store instructions with their new-value 188// format. 189// 190def getNewValueOpcode : InstrMapping { 191 let FilterClass = "NewValueRel"; 192 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 193 let ColFields = ["NValueST"]; 194 let KeyCol = ["false"]; 195 let ValueCols = [["true"]]; 196} 197 198//===----------------------------------------------------------------------===// 199// Generate mapping table to relate new-value store instructions with their old 200// format. 201// 202def getNonNVStore : InstrMapping { 203 let FilterClass = "NewValueRel"; 204 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"]; 205 let ColFields = ["NValueST"]; 206 let KeyCol = ["true"]; 207 let ValueCols = [["false"]]; 208} 209 210def changeAddrMode_abs_io: InstrMapping { 211 let FilterClass = "AddrModeRel"; 212 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 213 "isFloat"]; 214 let ColFields = ["addrMode"]; 215 let KeyCol = ["Absolute"]; 216 let ValueCols = [["BaseImmOffset"]]; 217} 218 219def changeAddrMode_io_abs: InstrMapping { 220 let FilterClass = "AddrModeRel"; 221 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore", 222 "isFloat"]; 223 let ColFields = ["addrMode"]; 224 let KeyCol = ["BaseImmOffset"]; 225 let ValueCols = [["Absolute"]]; 226} 227 228def changeAddrMode_io_rr: InstrMapping { 229 let FilterClass = "AddrModeRel"; 230 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 231 let ColFields = ["addrMode"]; 232 let KeyCol = ["BaseImmOffset"]; 233 let ValueCols = [["BaseRegOffset"]]; 234} 235 236def changeAddrMode_rr_io: InstrMapping { 237 let FilterClass = "AddrModeRel"; 238 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 239 let ColFields = ["addrMode"]; 240 let KeyCol = ["BaseRegOffset"]; 241 let ValueCols = [["BaseImmOffset"]]; 242} 243 244def changeAddrMode_pi_io: InstrMapping { 245 let FilterClass = "PostInc_BaseImm"; 246 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 247 let ColFields = ["addrMode"]; 248 let KeyCol = ["PostInc"]; 249 let ValueCols = [["BaseImmOffset"]]; 250} 251 252def changeAddrMode_io_pi: InstrMapping { 253 let FilterClass = "PostInc_BaseImm"; 254 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 255 let ColFields = ["addrMode"]; 256 let KeyCol = ["BaseImmOffset"]; 257 let ValueCols = [["PostInc"]]; 258} 259 260def changeAddrMode_rr_ur: InstrMapping { 261 let FilterClass = "ImmRegShl"; 262 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 263 let ColFields = ["addrMode"]; 264 let KeyCol = ["BaseRegOffset"]; 265 let ValueCols = [["BaseLongOffset"]]; 266} 267 268def changeAddrMode_ur_rr : InstrMapping { 269 let FilterClass = "ImmRegShl"; 270 let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; 271 let ColFields = ["addrMode"]; 272 let KeyCol = ["BaseLongOffset"]; 273 let ValueCols = [["BaseRegOffset"]]; 274} 275 276def getRegForm : InstrMapping { 277 let FilterClass = "ImmRegRel"; 278 let RowFields = ["CextOpcode", "PredSense", "PNewValue"]; 279 let ColFields = ["InputType"]; 280 let KeyCol = ["imm"]; 281 let ValueCols = [["reg"]]; 282} 283 284def notTakenBranchPrediction : InstrMapping { 285 let FilterClass = "PredRel"; 286 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 287 let ColFields = ["isBrTaken"]; 288 let KeyCol = ["true"]; 289 let ValueCols = [["false"]]; 290} 291 292def takenBranchPrediction : InstrMapping { 293 let FilterClass = "PredRel"; 294 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"]; 295 let ColFields = ["isBrTaken"]; 296 let KeyCol = ["false"]; 297 let ValueCols = [["true"]]; 298} 299 300def getRealHWInstr : InstrMapping { 301 let FilterClass = "IntrinsicsRel"; 302 let RowFields = ["BaseOpcode"]; 303 let ColFields = ["InstrType"]; 304 let KeyCol = ["Pseudo"]; 305 let ValueCols = [["Pseudo"], ["Real"]]; 306} 307//===----------------------------------------------------------------------===// 308// Register File, Instruction Descriptions 309//===----------------------------------------------------------------------===// 310include "HexagonSchedule.td" 311include "HexagonRegisterInfo.td" 312include "HexagonOperands.td" 313include "HexagonDepOperands.td" 314include "HexagonDepITypes.td" 315include "HexagonInstrFormats.td" 316include "HexagonDepInstrFormats.td" 317include "HexagonDepInstrInfo.td" 318include "HexagonCallingConv.td" 319include "HexagonPseudo.td" 320include "HexagonPatterns.td" 321include "HexagonPatternsHVX.td" 322include "HexagonPatternsV65.td" 323include "HexagonDepMappings.td" 324include "HexagonIntrinsics.td" 325 326def HexagonInstrInfo : InstrInfo; 327 328//===----------------------------------------------------------------------===// 329// Hexagon processors supported. 330//===----------------------------------------------------------------------===// 331 332class Proc<string Name, SchedMachineModel Model, 333 list<SubtargetFeature> Features> 334 : ProcessorModel<Name, Model, Features>; 335 336def : Proc<"generic", HexagonModelV60, 337 [ArchV5, ArchV55, ArchV60, 338 FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, 339 FeaturePackets, FeatureSmallData]>; 340def : Proc<"hexagonv5", HexagonModelV5, 341 [ArchV5, 342 FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, 343 FeaturePackets, FeatureSmallData]>; 344def : Proc<"hexagonv55", HexagonModelV55, 345 [ArchV5, ArchV55, 346 FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, 347 FeaturePackets, FeatureSmallData]>; 348def : Proc<"hexagonv60", HexagonModelV60, 349 [ArchV5, ArchV55, ArchV60, 350 FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, 351 FeaturePackets, FeatureSmallData]>; 352def : Proc<"hexagonv62", HexagonModelV62, 353 [ArchV5, ArchV55, ArchV60, ArchV62, 354 FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, 355 FeaturePackets, FeatureSmallData]>; 356def : Proc<"hexagonv65", HexagonModelV65, 357 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, 358 FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, 359 FeatureNVS, FeaturePackets, FeatureSmallData]>; 360def : Proc<"hexagonv66", HexagonModelV66, 361 [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, 362 FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, 363 FeatureNVS, FeaturePackets, FeatureSmallData]>; 364 365//===----------------------------------------------------------------------===// 366// Declare the target which we are implementing 367//===----------------------------------------------------------------------===// 368 369def HexagonAsmParser : AsmParser { 370 let ShouldEmitMatchRegisterAltName = 1; 371 bit HasMnemonicFirst = 0; 372} 373 374def HexagonAsmParserVariant : AsmParserVariant { 375 int Variant = 0; 376 string TokenizingCharacters = "#()=:.<>!+*-|^&"; 377 string BreakCharacters = ""; 378} 379 380def HexagonAsmWriter : AsmWriter { 381 string AsmWriterClassName = "InstPrinter"; 382 bit isMCAsmWriter = 1; 383} 384 385def Hexagon : Target { 386 let InstructionSet = HexagonInstrInfo; 387 let AssemblyParsers = [HexagonAsmParser]; 388 let AssemblyParserVariants = [HexagonAsmParserVariant]; 389 let AssemblyWriters = [HexagonAsmWriter]; 390 let AllowRegisterRenaming = 1; 391} 392