1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/HexagonBaseInfo.h" 10 #include "MCTargetDesc/HexagonMCChecker.h" 11 #include "MCTargetDesc/HexagonMCInstrInfo.h" 12 #include "MCTargetDesc/HexagonMCTargetDesc.h" 13 #include "TargetInfo/HexagonTargetInfo.h" 14 #include "llvm/ADT/ArrayRef.h" 15 #include "llvm/ADT/STLExtras.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCFixedLenDisassembler.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCInstrInfo.h" 22 #include "llvm/MC/MCRegisterInfo.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/MC/TargetRegistry.h" 25 #include "llvm/Support/Endian.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <cassert> 29 #include <cstddef> 30 #include <cstdint> 31 #include <memory> 32 33 #define DEBUG_TYPE "hexagon-disassembler" 34 35 using namespace llvm; 36 using namespace Hexagon; 37 38 using DecodeStatus = MCDisassembler::DecodeStatus; 39 40 namespace { 41 42 /// Hexagon disassembler for all Hexagon platforms. 43 class HexagonDisassembler : public MCDisassembler { 44 public: 45 std::unique_ptr<MCInstrInfo const> const MCII; 46 std::unique_ptr<MCInst *> CurrentBundle; 47 mutable MCInst const *CurrentExtender; 48 49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 50 MCInstrInfo const *MCII) 51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), 52 CurrentExtender(nullptr) {} 53 54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, 55 ArrayRef<uint8_t> Bytes, uint64_t Address, 56 raw_ostream &CStream, bool &Complete) const; 57 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 58 ArrayRef<uint8_t> Bytes, uint64_t Address, 59 raw_ostream &CStream) const override; 60 void remapInstruction(MCInst &Instr) const; 61 }; 62 63 static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, 64 int64_t Value) { 65 MCInstrInfo MCII = *Disassembler.MCII; 66 if (!Disassembler.CurrentExtender || 67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) 68 return Value; 69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 70 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; 71 int64_t Bits; 72 bool Success = 73 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( 74 Bits); 75 assert(Success); 76 (void)Success; 77 uint64_t Upper26 = static_cast<uint64_t>(Bits); 78 uint64_t Operand = Upper26 | Lower6; 79 return Operand; 80 } 81 static HexagonDisassembler const &disassembler(void const *Decoder) { 82 return *static_cast<HexagonDisassembler const *>(Decoder); 83 } 84 template <size_t T> 85 static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { 86 HexagonDisassembler const &Disassembler = disassembler(Decoder); 87 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); 88 int64_t Extended = SignExtend64<32>(FullValue); 89 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 90 } 91 } 92 93 // Forward declare these because the auto-generated code will reference them. 94 // Definitions are further down. 95 96 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 97 uint64_t Address, 98 const void *Decoder); 99 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 100 unsigned RegNo, 101 uint64_t Address, 102 const void *Decoder); 103 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 104 uint64_t Address, 105 const void *Decoder); 106 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 107 uint64_t Address, 108 const void *Decoder); 109 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus 113 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, 114 uint64_t Address, const void *Decoder); 115 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, 119 unsigned RegNo, 120 uint64_t Address, 121 const void *Decoder); 122 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 123 uint64_t Address, 124 const void *Decoder); 125 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 126 uint64_t Address, 127 const void *Decoder); 128 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 129 uint64_t Address, 130 const void *Decoder); 131 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 132 uint64_t Address, 133 const void *Decoder); 134 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, 135 uint64_t Address, 136 const void *Decoder); 137 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 138 uint64_t Address, 139 const void *Decoder); 140 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 141 uint64_t Address, 142 const void *Decoder); 143 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 147 uint64_t Address, 148 const void *Decoder); 149 150 151 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 154 uint64_t /*Address*/, const void *Decoder); 155 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 156 const void *Decoder); 157 #include "HexagonDepDecoders.inc" 158 #include "HexagonGenDisassemblerTables.inc" 159 160 static MCDisassembler *createHexagonDisassembler(const Target &T, 161 const MCSubtargetInfo &STI, 162 MCContext &Ctx) { 163 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo()); 164 } 165 166 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() { 167 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(), 168 createHexagonDisassembler); 169 } 170 171 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 172 ArrayRef<uint8_t> Bytes, 173 uint64_t Address, 174 raw_ostream &cs) const { 175 DecodeStatus Result = DecodeStatus::Success; 176 bool Complete = false; 177 Size = 0; 178 179 *CurrentBundle = &MI; 180 MI.setOpcode(Hexagon::BUNDLE); 181 MI.addOperand(MCOperand::createImm(0)); 182 while (Result == Success && !Complete) { 183 if (Bytes.size() < HEXAGON_INSTR_SIZE) 184 return MCDisassembler::Fail; 185 MCInst *Inst = getContext().createMCInst(); 186 Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete); 187 MI.addOperand(MCOperand::createInst(Inst)); 188 Size += HEXAGON_INSTR_SIZE; 189 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); 190 } 191 if (Result == MCDisassembler::Fail) 192 return Result; 193 if (Size > HEXAGON_MAX_PACKET_SIZE) 194 return MCDisassembler::Fail; 195 196 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI); 197 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI; 198 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, 199 *getContext().getRegisterInfo(), false); 200 if (!Checker.check()) 201 return MCDisassembler::Fail; 202 remapInstruction(MI); 203 return MCDisassembler::Success; 204 } 205 206 void HexagonDisassembler::remapInstruction(MCInst &Instr) const { 207 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { 208 auto &MI = const_cast<MCInst &>(*I.getInst()); 209 switch (MI.getOpcode()) { 210 case Hexagon::S2_allocframe: 211 if (MI.getOperand(0).getReg() == Hexagon::R29) { 212 MI.setOpcode(Hexagon::S6_allocframe_to_raw); 213 MI.erase(MI.begin () + 1); 214 MI.erase(MI.begin ()); 215 } 216 break; 217 case Hexagon::L2_deallocframe: 218 if (MI.getOperand(0).getReg() == Hexagon::D15 && 219 MI.getOperand(1).getReg() == Hexagon::R30) { 220 MI.setOpcode(L6_deallocframe_map_to_raw); 221 MI.erase(MI.begin () + 1); 222 MI.erase(MI.begin ()); 223 } 224 break; 225 case Hexagon::L4_return: 226 if (MI.getOperand(0).getReg() == Hexagon::D15 && 227 MI.getOperand(1).getReg() == Hexagon::R30) { 228 MI.setOpcode(L6_return_map_to_raw); 229 MI.erase(MI.begin () + 1); 230 MI.erase(MI.begin ()); 231 } 232 break; 233 case Hexagon::L4_return_t: 234 if (MI.getOperand(0).getReg() == Hexagon::D15 && 235 MI.getOperand(2).getReg() == Hexagon::R30) { 236 MI.setOpcode(L4_return_map_to_raw_t); 237 MI.erase(MI.begin () + 2); 238 MI.erase(MI.begin ()); 239 } 240 break; 241 case Hexagon::L4_return_f: 242 if (MI.getOperand(0).getReg() == Hexagon::D15 && 243 MI.getOperand(2).getReg() == Hexagon::R30) { 244 MI.setOpcode(L4_return_map_to_raw_f); 245 MI.erase(MI.begin () + 2); 246 MI.erase(MI.begin ()); 247 } 248 break; 249 case Hexagon::L4_return_tnew_pt: 250 if (MI.getOperand(0).getReg() == Hexagon::D15 && 251 MI.getOperand(2).getReg() == Hexagon::R30) { 252 MI.setOpcode(L4_return_map_to_raw_tnew_pt); 253 MI.erase(MI.begin () + 2); 254 MI.erase(MI.begin ()); 255 } 256 break; 257 case Hexagon::L4_return_fnew_pt: 258 if (MI.getOperand(0).getReg() == Hexagon::D15 && 259 MI.getOperand(2).getReg() == Hexagon::R30) { 260 MI.setOpcode(L4_return_map_to_raw_fnew_pt); 261 MI.erase(MI.begin () + 2); 262 MI.erase(MI.begin ()); 263 } 264 break; 265 case Hexagon::L4_return_tnew_pnt: 266 if (MI.getOperand(0).getReg() == Hexagon::D15 && 267 MI.getOperand(2).getReg() == Hexagon::R30) { 268 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); 269 MI.erase(MI.begin () + 2); 270 MI.erase(MI.begin ()); 271 } 272 break; 273 case Hexagon::L4_return_fnew_pnt: 274 if (MI.getOperand(0).getReg() == Hexagon::D15 && 275 MI.getOperand(2).getReg() == Hexagon::R30) { 276 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); 277 MI.erase(MI.begin () + 2); 278 MI.erase(MI.begin ()); 279 } 280 break; 281 } 282 } 283 } 284 285 static void adjustDuplex(MCInst &MI, MCContext &Context) { 286 switch (MI.getOpcode()) { 287 case Hexagon::SA1_setin1: 288 MI.insert(MI.begin() + 1, 289 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 290 break; 291 case Hexagon::SA1_dec: 292 MI.insert(MI.begin() + 2, 293 MCOperand::createExpr(MCConstantExpr::create(-1, Context))); 294 break; 295 default: 296 break; 297 } 298 } 299 300 DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, 301 ArrayRef<uint8_t> Bytes, 302 uint64_t Address, 303 raw_ostream &cs, 304 bool &Complete) const { 305 assert(Bytes.size() >= HEXAGON_INSTR_SIZE); 306 307 uint32_t Instruction = support::endian::read32le(Bytes.data()); 308 309 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); 310 if ((Instruction & HexagonII::INST_PARSE_MASK) == 311 HexagonII::INST_PARSE_LOOP_END) { 312 if (BundleSize == 0) 313 HexagonMCInstrInfo::setInnerLoop(MCB); 314 else if (BundleSize == 1) 315 HexagonMCInstrInfo::setOuterLoop(MCB); 316 else 317 return DecodeStatus::Fail; 318 } 319 320 CurrentExtender = HexagonMCInstrInfo::extenderForIndex( 321 MCB, HexagonMCInstrInfo::bundleSize(MCB)); 322 323 DecodeStatus Result = DecodeStatus::Fail; 324 if ((Instruction & HexagonII::INST_PARSE_MASK) == 325 HexagonII::INST_PARSE_DUPLEX) { 326 unsigned duplexIClass; 327 uint8_t const *DecodeLow, *DecodeHigh; 328 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); 329 switch (duplexIClass) { 330 default: 331 return MCDisassembler::Fail; 332 case 0: 333 DecodeLow = DecoderTableSUBINSN_L132; 334 DecodeHigh = DecoderTableSUBINSN_L132; 335 break; 336 case 1: 337 DecodeLow = DecoderTableSUBINSN_L232; 338 DecodeHigh = DecoderTableSUBINSN_L132; 339 break; 340 case 2: 341 DecodeLow = DecoderTableSUBINSN_L232; 342 DecodeHigh = DecoderTableSUBINSN_L232; 343 break; 344 case 3: 345 DecodeLow = DecoderTableSUBINSN_A32; 346 DecodeHigh = DecoderTableSUBINSN_A32; 347 break; 348 case 4: 349 DecodeLow = DecoderTableSUBINSN_L132; 350 DecodeHigh = DecoderTableSUBINSN_A32; 351 break; 352 case 5: 353 DecodeLow = DecoderTableSUBINSN_L232; 354 DecodeHigh = DecoderTableSUBINSN_A32; 355 break; 356 case 6: 357 DecodeLow = DecoderTableSUBINSN_S132; 358 DecodeHigh = DecoderTableSUBINSN_A32; 359 break; 360 case 7: 361 DecodeLow = DecoderTableSUBINSN_S232; 362 DecodeHigh = DecoderTableSUBINSN_A32; 363 break; 364 case 8: 365 DecodeLow = DecoderTableSUBINSN_S132; 366 DecodeHigh = DecoderTableSUBINSN_L132; 367 break; 368 case 9: 369 DecodeLow = DecoderTableSUBINSN_S132; 370 DecodeHigh = DecoderTableSUBINSN_L232; 371 break; 372 case 10: 373 DecodeLow = DecoderTableSUBINSN_S132; 374 DecodeHigh = DecoderTableSUBINSN_S132; 375 break; 376 case 11: 377 DecodeLow = DecoderTableSUBINSN_S232; 378 DecodeHigh = DecoderTableSUBINSN_S132; 379 break; 380 case 12: 381 DecodeLow = DecoderTableSUBINSN_S232; 382 DecodeHigh = DecoderTableSUBINSN_L132; 383 break; 384 case 13: 385 DecodeLow = DecoderTableSUBINSN_S232; 386 DecodeHigh = DecoderTableSUBINSN_L232; 387 break; 388 case 14: 389 DecodeLow = DecoderTableSUBINSN_S232; 390 DecodeHigh = DecoderTableSUBINSN_S232; 391 break; 392 } 393 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); 394 MCInst *MILow = getContext().createMCInst(); 395 MCInst *MIHigh = getContext().createMCInst(); 396 auto TmpExtender = CurrentExtender; 397 CurrentExtender = 398 nullptr; // constant extenders in duplex must always be in slot 1 399 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, 400 this, STI); 401 CurrentExtender = TmpExtender; 402 if (Result != DecodeStatus::Success) 403 return DecodeStatus::Fail; 404 adjustDuplex(*MILow, getContext()); 405 Result = decodeInstruction( 406 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); 407 if (Result != DecodeStatus::Success) 408 return DecodeStatus::Fail; 409 adjustDuplex(*MIHigh, getContext()); 410 MCOperand OPLow = MCOperand::createInst(MILow); 411 MCOperand OPHigh = MCOperand::createInst(MIHigh); 412 MI.addOperand(OPLow); 413 MI.addOperand(OPHigh); 414 Complete = true; 415 } else { 416 if ((Instruction & HexagonII::INST_PARSE_MASK) == 417 HexagonII::INST_PARSE_PACKET_END) 418 Complete = true; 419 420 if (CurrentExtender != nullptr) 421 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, 422 Address, this, STI); 423 424 if (Result != MCDisassembler::Success) 425 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, 426 STI); 427 428 if (Result != MCDisassembler::Success && 429 STI.getFeatureBits()[Hexagon::ExtensionHVX]) 430 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, 431 Address, this, STI); 432 433 } 434 435 switch (MI.getOpcode()) { 436 case Hexagon::J4_cmpeqn1_f_jumpnv_nt: 437 case Hexagon::J4_cmpeqn1_f_jumpnv_t: 438 case Hexagon::J4_cmpeqn1_fp0_jump_nt: 439 case Hexagon::J4_cmpeqn1_fp0_jump_t: 440 case Hexagon::J4_cmpeqn1_fp1_jump_nt: 441 case Hexagon::J4_cmpeqn1_fp1_jump_t: 442 case Hexagon::J4_cmpeqn1_t_jumpnv_nt: 443 case Hexagon::J4_cmpeqn1_t_jumpnv_t: 444 case Hexagon::J4_cmpeqn1_tp0_jump_nt: 445 case Hexagon::J4_cmpeqn1_tp0_jump_t: 446 case Hexagon::J4_cmpeqn1_tp1_jump_nt: 447 case Hexagon::J4_cmpeqn1_tp1_jump_t: 448 case Hexagon::J4_cmpgtn1_f_jumpnv_nt: 449 case Hexagon::J4_cmpgtn1_f_jumpnv_t: 450 case Hexagon::J4_cmpgtn1_fp0_jump_nt: 451 case Hexagon::J4_cmpgtn1_fp0_jump_t: 452 case Hexagon::J4_cmpgtn1_fp1_jump_nt: 453 case Hexagon::J4_cmpgtn1_fp1_jump_t: 454 case Hexagon::J4_cmpgtn1_t_jumpnv_nt: 455 case Hexagon::J4_cmpgtn1_t_jumpnv_t: 456 case Hexagon::J4_cmpgtn1_tp0_jump_nt: 457 case Hexagon::J4_cmpgtn1_tp0_jump_t: 458 case Hexagon::J4_cmpgtn1_tp1_jump_nt: 459 case Hexagon::J4_cmpgtn1_tp1_jump_t: 460 MI.insert(MI.begin() + 1, 461 MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); 462 break; 463 default: 464 break; 465 } 466 467 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { 468 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); 469 MCOperand &MCO = MI.getOperand(OpIndex); 470 assert(MCO.isReg() && "New value consumers must be registers"); 471 unsigned Register = 472 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg()); 473 if ((Register & 0x6) == 0) 474 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved 475 return MCDisassembler::Fail; 476 unsigned Lookback = (Register & 0x6) >> 1; 477 unsigned Offset = 1; 478 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); 479 bool PrevVector = false; 480 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); 481 auto i = Instructions.end() - 1; 482 for (auto n = Instructions.begin() - 1;; --i, ++Offset) { 483 if (i == n) 484 // Couldn't find producer 485 return MCDisassembler::Fail; 486 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); 487 if (Vector && !CurrentVector) 488 // Skip scalars when calculating distances for vectors 489 ++Lookback; 490 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) 491 ++Lookback; 492 PrevVector = CurrentVector; 493 if (Offset == Lookback) 494 break; 495 } 496 auto const &Inst = *i->getInst(); 497 bool SubregBit = (Register & 0x1) != 0; 498 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { 499 // If subreg bit is set we're selecting the second produced newvalue 500 unsigned Producer = SubregBit ? 501 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : 502 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); 503 assert(Producer != Hexagon::NoRegister); 504 MCO.setReg(Producer); 505 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) { 506 unsigned Producer = 507 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg(); 508 509 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) { 510 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); 511 const unsigned ProdPairIndex = 512 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0; 513 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0; 514 } else if (SubregBit) 515 // Hexagon PRM 10.11 New-value operands 516 // Nt[0] is reserved and should always be encoded as zero. 517 return MCDisassembler::Fail; 518 assert(Producer != Hexagon::NoRegister); 519 MCO.setReg(Producer); 520 } else 521 return MCDisassembler::Fail; 522 } 523 524 if (CurrentExtender != nullptr) { 525 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) 526 ? *MI.getOperand(1).getInst() 527 : MI; 528 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && 529 !HexagonMCInstrInfo::isExtended(*MCII, Inst)) 530 return MCDisassembler::Fail; 531 } 532 return Result; 533 } 534 535 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 536 ArrayRef<MCPhysReg> Table) { 537 if (RegNo < Table.size()) { 538 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 539 return MCDisassembler::Success; 540 } 541 542 return MCDisassembler::Fail; 543 } 544 545 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 546 uint64_t Address, 547 const void *Decoder) { 548 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); 549 } 550 551 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 552 uint64_t Address, 553 const void *Decoder) { 554 static const MCPhysReg IntRegDecoderTable[] = { 555 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 556 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 557 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 558 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 559 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 560 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 561 Hexagon::R30, Hexagon::R31}; 562 563 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); 564 } 565 566 static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, 567 unsigned RegNo, 568 uint64_t Address, 569 const void *Decoder) { 570 static const MCPhysReg GeneralSubRegDecoderTable[] = { 571 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, 572 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, 573 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 574 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, 575 }; 576 577 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); 578 } 579 580 static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, 581 uint64_t /*Address*/, 582 const void *Decoder) { 583 static const MCPhysReg HvxVRDecoderTable[] = { 584 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, 585 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, 586 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14, 587 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, 588 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24, 589 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29, 590 Hexagon::V30, Hexagon::V31}; 591 592 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); 593 } 594 595 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 596 uint64_t /*Address*/, 597 const void *Decoder) { 598 static const MCPhysReg DoubleRegDecoderTable[] = { 599 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 600 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 601 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 602 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15}; 603 604 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); 605 } 606 607 static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( 608 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { 609 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { 610 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 611 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; 612 613 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); 614 } 615 616 static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, 617 uint64_t /*Address*/, 618 const void *Decoder) { 619 static const MCPhysReg HvxWRDecoderTable[] = { 620 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, 621 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, 622 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7, 623 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9, 624 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12, 625 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14, 626 Hexagon::W15, Hexagon::WR15, 627 }; 628 629 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); 630 } 631 632 LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. 633 static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, 634 unsigned RegNo, 635 uint64_t /*Address*/, 636 const void *Decoder) { 637 static const MCPhysReg HvxVQRDecoderTable[] = { 638 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, 639 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; 640 641 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable); 642 } 643 644 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 645 uint64_t /*Address*/, 646 const void *Decoder) { 647 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, 648 Hexagon::P2, Hexagon::P3}; 649 650 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable); 651 } 652 653 static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, 654 uint64_t /*Address*/, 655 const void *Decoder) { 656 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, 657 Hexagon::Q2, Hexagon::Q3}; 658 659 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable); 660 } 661 662 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 663 uint64_t /*Address*/, 664 const void *Decoder) { 665 using namespace Hexagon; 666 667 static const MCPhysReg CtrlRegDecoderTable[] = { 668 /* 0 */ SA0, LC0, SA1, LC1, 669 /* 4 */ P3_0, C5, M0, M1, 670 /* 8 */ USR, PC, UGP, GP, 671 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, 672 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, 673 /* 20 */ 0, 0, 0, 0, 674 /* 24 */ 0, 0, 0, 0, 675 /* 28 */ 0, 0, UTIMERLO, UTIMERHI 676 }; 677 678 if (RegNo >= array_lengthof(CtrlRegDecoderTable)) 679 return MCDisassembler::Fail; 680 681 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 682 if (CtrlRegDecoderTable[RegNo] == NoRegister) 683 return MCDisassembler::Fail; 684 685 unsigned Register = CtrlRegDecoderTable[RegNo]; 686 Inst.addOperand(MCOperand::createReg(Register)); 687 return MCDisassembler::Success; 688 } 689 690 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 691 uint64_t /*Address*/, 692 const void *Decoder) { 693 using namespace Hexagon; 694 695 static const MCPhysReg CtrlReg64DecoderTable[] = { 696 /* 0 */ C1_0, 0, C3_2, 0, 697 /* 4 */ C5_4, 0, C7_6, 0, 698 /* 8 */ C9_8, 0, C11_10, 0, 699 /* 12 */ CS, 0, UPCYCLE, 0, 700 /* 16 */ C17_16, 0, PKTCOUNT, 0, 701 /* 20 */ 0, 0, 0, 0, 702 /* 24 */ 0, 0, 0, 0, 703 /* 28 */ 0, 0, UTIMER, 0 704 }; 705 706 if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) 707 return MCDisassembler::Fail; 708 709 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); 710 if (CtrlReg64DecoderTable[RegNo] == NoRegister) 711 return MCDisassembler::Fail; 712 713 unsigned Register = CtrlReg64DecoderTable[RegNo]; 714 Inst.addOperand(MCOperand::createReg(Register)); 715 return MCDisassembler::Success; 716 } 717 718 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 719 uint64_t /*Address*/, 720 const void *Decoder) { 721 unsigned Register = 0; 722 switch (RegNo) { 723 case 0: 724 Register = Hexagon::M0; 725 break; 726 case 1: 727 Register = Hexagon::M1; 728 break; 729 default: 730 return MCDisassembler::Fail; 731 } 732 Inst.addOperand(MCOperand::createReg(Register)); 733 return MCDisassembler::Success; 734 } 735 736 static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, 737 uint64_t /*Address*/, 738 const void *Decoder) { 739 HexagonDisassembler const &Disassembler = disassembler(Decoder); 740 int64_t FullValue = fullValue(Disassembler, MI, tmp); 741 assert(FullValue >= 0 && "Negative in unsigned decoder"); 742 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); 743 return MCDisassembler::Success; 744 } 745 746 static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, 747 uint64_t /*Address*/, const void *Decoder) { 748 HexagonDisassembler const &Disassembler = disassembler(Decoder); 749 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 750 tmp = SignExtend64(tmp, Bits); 751 signedDecoder<32>(MI, tmp, Decoder); 752 return MCDisassembler::Success; 753 } 754 755 // custom decoder for various jump/call immediates 756 static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, 757 const void *Decoder) { 758 HexagonDisassembler const &Disassembler = disassembler(Decoder); 759 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); 760 // r13_2 is not extendable, so if there are no extent bits, it's r13_2 761 if (Bits == 0) 762 Bits = 15; 763 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); 764 uint32_t Extended = FullValue + Address; 765 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) 766 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); 767 return MCDisassembler::Success; 768 } 769 770 static const uint16_t SysRegDecoderTable[] = { 771 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID, 772 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1, 773 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID, 774 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11, 775 Hexagon::S12, Hexagon::S13, Hexagon::S14, 776 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL, 777 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20, 778 Hexagon::VID, Hexagon::S22, Hexagon::S23, 779 Hexagon::S24, Hexagon::S25, Hexagon::S26, 780 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV, 781 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST, 782 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35, 783 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1, 784 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT, 785 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44, 786 Hexagon::S45, Hexagon::S46, Hexagon::S47, 787 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2, 788 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG, 789 Hexagon::S54, Hexagon::S55, Hexagon::S56, 790 Hexagon::S57, Hexagon::S58, Hexagon::S59, 791 Hexagon::S60, Hexagon::S61, Hexagon::S62, 792 Hexagon::S63, Hexagon::S64, Hexagon::S65, 793 Hexagon::S66, Hexagon::S67, Hexagon::S68, 794 Hexagon::S69, Hexagon::S70, Hexagon::S71, 795 Hexagon::S72, Hexagon::S73, Hexagon::S74, 796 Hexagon::S75, Hexagon::S76, Hexagon::S77, 797 Hexagon::S78, Hexagon::S79, Hexagon::S80, 798 }; 799 800 static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, 801 uint64_t /*Address*/, 802 const void *Decoder) { 803 if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) 804 return MCDisassembler::Fail; 805 806 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister) 807 return MCDisassembler::Fail; 808 809 unsigned Register = SysRegDecoderTable[RegNo]; 810 Inst.addOperand(MCOperand::createReg(Register)); 811 return MCDisassembler::Success; 812 } 813 814 static const uint16_t SysReg64DecoderTable[] = { 815 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6, 816 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14, 817 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22, 818 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30, 819 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38, 820 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46, 821 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54, 822 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62, 823 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70, 824 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, 825 }; 826 827 static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 828 uint64_t /*Address*/, 829 const void *Decoder) { 830 RegNo = RegNo >> 1; 831 if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0])) 832 return MCDisassembler::Fail; 833 834 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister) 835 return MCDisassembler::Fail; 836 837 unsigned Register = SysReg64DecoderTable[RegNo]; 838 Inst.addOperand(MCOperand::createReg(Register)); 839 return MCDisassembler::Success; 840 } 841 842 static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, 843 uint64_t /*Address*/, 844 const void *Decoder) { 845 using namespace Hexagon; 846 847 static const MCPhysReg GuestRegDecoderTable[] = { 848 /* 0 */ GELR, GSR, GOSP, G3, 849 /* 4 */ G4, G5, G6, G7, 850 /* 8 */ G8, G9, G10, G11, 851 /* 12 */ G12, G13, G14, G15, 852 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 853 /* 20 */ G20, G21, G22, G23, 854 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 855 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31 856 }; 857 858 if (RegNo >= array_lengthof(GuestRegDecoderTable)) 859 return MCDisassembler::Fail; 860 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) 861 return MCDisassembler::Fail; 862 863 unsigned Register = GuestRegDecoderTable[RegNo]; 864 Inst.addOperand(MCOperand::createReg(Register)); 865 return MCDisassembler::Success; 866 } 867 868 static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 869 uint64_t /*Address*/, 870 const void *Decoder) { 871 using namespace Hexagon; 872 873 static const MCPhysReg GuestReg64DecoderTable[] = { 874 /* 0 */ G1_0, 0, G3_2, 0, 875 /* 4 */ G5_4, 0, G7_6, 0, 876 /* 8 */ G9_8, 0, G11_10, 0, 877 /* 12 */ G13_12, 0, G15_14, 0, 878 /* 16 */ G17_16, 0, G19_18, 0, 879 /* 20 */ G21_20, 0, G23_22, 0, 880 /* 24 */ G25_24, 0, G27_26, 0, 881 /* 28 */ G29_28, 0, G31_30, 0 882 }; 883 884 if (RegNo >= array_lengthof(GuestReg64DecoderTable)) 885 return MCDisassembler::Fail; 886 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) 887 return MCDisassembler::Fail; 888 889 unsigned Register = GuestReg64DecoderTable[RegNo]; 890 Inst.addOperand(MCOperand::createReg(Register)); 891 return MCDisassembler::Success; 892 } 893