1*81ad6265SDimitry Andric//- DirectX.td - Describe the DirectX Target Machine ----------*- tablegen -*-// 2*81ad6265SDimitry Andric// 3*81ad6265SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*81ad6265SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*81ad6265SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*81ad6265SDimitry Andric// 7*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 8*81ad6265SDimitry Andric/// 9*81ad6265SDimitry Andric/// \file 10*81ad6265SDimitry Andric/// This is a target description file for the DirectX target 11*81ad6265SDimitry Andric/// 12*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 13*81ad6265SDimitry Andric 14*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 15*81ad6265SDimitry Andric// Target-independent interfaces which we are implementing 16*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 17*81ad6265SDimitry Andric 18*81ad6265SDimitry Andricinclude "llvm/Target/Target.td" 19*81ad6265SDimitry Andricinclude "DXILStubs.td" 20*81ad6265SDimitry Andric 21*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 22*81ad6265SDimitry Andric// DirectX Subtarget features. 23*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 24*81ad6265SDimitry Andric 25*81ad6265SDimitry Andricdef DirectXInstrInfo : InstrInfo; 26*81ad6265SDimitry Andric 27*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 28*81ad6265SDimitry Andric// DirectX Processors supported. 29*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 30*81ad6265SDimitry Andric 31*81ad6265SDimitry Andricdef : ProcessorModel<"generic", NoSchedModel, []>; 32*81ad6265SDimitry Andric 33*81ad6265SDimitry Andric 34*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 35*81ad6265SDimitry Andric// Target Declaration 36*81ad6265SDimitry Andric//===----------------------------------------------------------------------===// 37*81ad6265SDimitry Andric 38*81ad6265SDimitry Andricdef DirectXAsmParser : AsmParser { 39*81ad6265SDimitry Andric // The physical register names are not in the binary format or asm text 40*81ad6265SDimitry Andric let ShouldEmitMatchRegisterName = 0; 41*81ad6265SDimitry Andric} 42*81ad6265SDimitry Andric 43*81ad6265SDimitry Andricdef DirectXAsmWriter : AsmWriter { 44*81ad6265SDimitry Andric string AsmWriterClassName = "InstPrinter"; 45*81ad6265SDimitry Andric int PassSubtarget = 0; 46*81ad6265SDimitry Andric int Variant = 0; 47*81ad6265SDimitry Andric bit isMCAsmWriter = 1; 48*81ad6265SDimitry Andric} 49*81ad6265SDimitry Andric 50*81ad6265SDimitry Andricdef DirectX : Target { 51*81ad6265SDimitry Andric let InstructionSet = DirectXInstrInfo; 52*81ad6265SDimitry Andric let AssemblyParsers = [DirectXAsmParser]; 53*81ad6265SDimitry Andric let AssemblyWriters = [DirectXAsmWriter]; 54*81ad6265SDimitry Andric} 55