xref: /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/CSKYInstrInfo.td (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873)
1//===-- CSKYInstrInfo.td - Target Description for CSKY -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the CSKY instructions in TableGen format.
10//
11//===----------------------------------------------------------------------===//
12
13
14//===----------------------------------------------------------------------===//
15// CSKY specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18// Target-independent type requirements, but with target-specific formats.
19def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
20                                       SDTCisVT<1, i32>]>;
21
22def SDT_CallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,
23                                     SDTCisVT<1, i32>]>;
24
25def SDT_CSKYCall : SDTypeProfile<0, 2, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
26
27def SDT_CSKYCallReg : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
28
29def SDT_CSKY_LOADADDR : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
30                        SDTCisVT<1, iPTR>, SDTCisVT<2, iPTR>]>;
31
32def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
33                           [SDNPHasChain, SDNPOutGlue]>;
34def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
35                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
36
37def CSKY_RET : SDNode<"CSKYISD::RET", SDTNone,
38    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
39
40def CSKY_CALL : SDNode<"CSKYISD::CALL", SDT_CSKYCall,
41  [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
42
43def CSKY_CALLReg : SDNode<"CSKYISD::CALLReg", SDT_CSKYCallReg,
44  [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
45
46def CSKY_TAIL : SDNode<"CSKYISD::TAIL", SDT_CSKYCall,
47  [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
48
49def CSKY_TAILReg : SDNode<"CSKYISD::TAILReg", SDT_CSKYCallReg,
50  [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>;
51
52def CSKY_LOAD_ADDR : SDNode<"CSKYISD::LOAD_ADDR", SDT_CSKY_LOADADDR>;
53
54//===----------------------------------------------------------------------===//
55// Operand and SDNode transformation definitions.
56//===----------------------------------------------------------------------===//
57class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
58  let Name = prefix # "Imm" # width # suffix;
59  let RenderMethod = "addImmOperands";
60  let DiagnosticType = !strconcat("Invalid", Name);
61}
62
63class SImmAsmOperand<int width, string suffix = "">
64    : ImmAsmOperand<"S", width, suffix> {
65}
66
67class UImmAsmOperand<int width, string suffix = "">
68    : ImmAsmOperand<"U", width, suffix> {
69}
70
71class OImmAsmOperand<int width, string suffix = "">
72    : ImmAsmOperand<"O", width, suffix> {
73}
74
75def to_tframeindex : SDNodeXForm<frameindex, [{
76  auto FI = cast<FrameIndexSDNode>(N);
77  return CurDAG->getTargetFrameIndex(FI->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));
78}]>;
79
80def to_tconstpool : SDNodeXForm<constpool, [{
81  auto CP = cast<ConstantPoolSDNode>(N);
82  return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),
83                    CP->getAlign(), CP->getOffset(), CSKYII::MO_None);
84}]>;
85
86def to_tconstpool_hi16 : SDNodeXForm<constpool, [{
87  auto CP = cast<ConstantPoolSDNode>(N);
88  return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),
89                    CP->getAlign(), CP->getOffset(), CSKYII::MO_ADDR_HI16);
90}]>;
91
92def to_tconstpool_lo16 : SDNodeXForm<constpool, [{
93  auto CP = cast<ConstantPoolSDNode>(N);
94  return CurDAG->getTargetConstantPool(CP->getConstVal(), TLI->getPointerTy(CurDAG->getDataLayout()),
95                    CP->getAlign(), CP->getOffset(), CSKYII::MO_ADDR_LO16);
96}]>;
97
98class oimm<int num> : Operand<i32>,
99  ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {
100  let EncoderMethod = "getOImmOpValue";
101  let ParserMatchClass = OImmAsmOperand<num>;
102  let DecoderMethod = "decodeOImmOperand<"#num#">";
103}
104
105class uimm<int num, int shift = 0> : Operand<i32>,
106  ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
107  let EncoderMethod = "getImmOpValue<"#shift#">";
108  let ParserMatchClass =
109    !if(!ne(shift, 0),
110        UImmAsmOperand<num, "Shift"#shift>,
111        UImmAsmOperand<num>);
112  let DecoderMethod = "decodeUImmOperand<"#num#", "#shift#">";
113}
114
115class simm<int num, int shift = 0> : Operand<i32>,
116  ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
117  let EncoderMethod = "getImmOpValue<"#shift#">";
118  let ParserMatchClass = SImmAsmOperand<num>;
119  let DecoderMethod = "decodeSImmOperand<"#num#", "#shift#">";
120}
121
122def nimm_XFORM : SDNodeXForm<imm, [{
123  return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N), MVT::i32);
124}]>;
125class nimm<int num> : Operand<i32>,
126  ImmLeaf<i32, "return isUInt<"#num#">(~Imm);", nimm_XFORM> {
127  let ParserMatchClass = UImmAsmOperand<num>;
128}
129
130def uimm32_hi16 : SDNodeXForm<imm, [{
131  return CurDAG->getTargetConstant((N->getZExtValue() >> 16) & 0xFFFF,
132    SDLoc(N), MVT::i32);
133}]>;
134def uimm32_lo16 : SDNodeXForm<imm, [{
135  return CurDAG->getTargetConstant(N->getZExtValue()& 0xFFFF, SDLoc(N), MVT::i32);
136}]>;
137def uimm16_16_xform : Operand<i32>,
138  ImmLeaf<i32, "return isShiftedUInt<16, 16>(Imm);", uimm32_hi16> {
139  let ParserMatchClass = UImmAsmOperand<16>;
140  let EncoderMethod = "getImmOpValue";
141}
142
143def uimm_shift : Operand<i32>, ImmLeaf<i32, "return isUInt<2>(Imm);"> {
144  let EncoderMethod = "getImmShiftOpValue";
145  let ParserMatchClass = UImmAsmOperand<2>;
146  let DecoderMethod = "decodeImmShiftOpValue";
147}
148
149def CSKYSymbol : AsmOperandClass {
150  let Name = "CSKYSymbol";
151  let RenderMethod = "addImmOperands";
152  let DiagnosticType = "InvalidCSKYSymbol";
153  let ParserMethod = "parseCSKYSymbol";
154}
155
156def br_symbol : Operand<OtherVT> {
157  let EncoderMethod =
158    "getBranchSymbolOpValue<CSKY::fixup_csky_pcrel_imm16_scale2>";
159  let ParserMatchClass = CSKYSymbol;
160  let DecoderMethod = "decodeSImmOperand<16, 1>";
161  let PrintMethod = "printCSKYSymbolOperand";
162  let OperandType = "OPERAND_PCREL";
163}
164
165def call_symbol : Operand<iPTR> {
166  let ParserMatchClass = CSKYSymbol;
167  let EncoderMethod = "getCallSymbolOpValue";
168  let DecoderMethod = "decodeSImmOperand<26, 1>";
169  let PrintMethod = "printCSKYSymbolOperand";
170  let OperandType = "OPERAND_PCREL";
171}
172
173def Constpool : AsmOperandClass {
174  let Name = "Constpool";
175  let RenderMethod = "addConstpoolOperands";
176  let DiagnosticType = "InvalidConstpool";
177  let ParserMethod = "parseConstpoolSymbol";
178}
179
180def constpool_symbol : Operand<iPTR> {
181  let ParserMatchClass = Constpool;
182  let EncoderMethod =
183    "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm16_scale4>";
184  let DecoderMethod = "decodeUImmOperand<16, 2>";
185  let PrintMethod = "printConstpool";
186  let OperandType = "OPERAND_PCREL";
187}
188
189def DataAsmClass : AsmOperandClass {
190  let Name = "DataSymbol";
191  let RenderMethod = "addConstpoolOperands";
192  let DiagnosticType = "InvalidConstpool";
193  let ParserMethod = "parseDataSymbol";
194}
195
196class data_symbol<string reloc, int shift> : Operand<iPTR> {
197  let ParserMatchClass = Constpool;
198  let EncoderMethod =
199    "getDataSymbolOpValue<"#reloc#">";
200  let DecoderMethod = "decodeUImmOperand<18, "#shift#">";
201  let PrintMethod = "printDataSymbol";
202}
203
204def bare_symbol : Operand<iPTR> {
205  let ParserMatchClass = CSKYSymbol;
206  let EncoderMethod = "getBareSymbolOpValue";
207  let PrintMethod = "printCSKYSymbolOperand";
208  let DecoderMethod = "decodeSImmOperand<18, 1>";
209  let OperandType = "OPERAND_PCREL";
210}
211
212def oimm3 : oimm<3> {
213  let MCOperandPredicate = [{
214    int64_t Imm;
215    if (MCOp.evaluateAsConstantImm(Imm))
216      return isUInt<3>(Imm - 1);
217    return MCOp.isBareSymbolRef();
218  }];
219}
220def oimm4 : oimm<4>;
221def oimm5 : oimm<5> {
222  let MCOperandPredicate = [{
223    int64_t Imm;
224    if (MCOp.evaluateAsConstantImm(Imm))
225      return isUInt<5>(Imm - 1);
226    return MCOp.isBareSymbolRef();
227  }];
228}
229def oimm6 : oimm<6>;
230
231def imm5_idly : Operand<i32>, ImmLeaf<i32,
232  "return Imm <= 32 && Imm >= 0;"> {
233  let EncoderMethod = "getImmOpValueIDLY";
234  let DecoderMethod = "decodeOImmOperand<5>";
235}
236
237def oimm8 : oimm<8> {
238  let MCOperandPredicate = [{
239    int64_t Imm;
240    if (MCOp.evaluateAsConstantImm(Imm))
241      return isUInt<8>(Imm - 1);
242    return MCOp.isBareSymbolRef();
243  }];
244}
245def oimm12 : oimm<12> {
246  let MCOperandPredicate = [{
247    int64_t Imm;
248    if (MCOp.evaluateAsConstantImm(Imm))
249      return isUInt<12>(Imm - 1);
250    return MCOp.isBareSymbolRef();
251  }];
252}
253def oimm16 : oimm<16> {
254  let MCOperandPredicate = [{
255    int64_t Imm;
256    if (MCOp.evaluateAsConstantImm(Imm))
257      return isUInt<16>(Imm - 1);
258    return MCOp.isBareSymbolRef();
259  }];
260}
261
262def nimm12 : nimm<12>;
263
264def uimm1 : uimm<1>;
265def uimm2 : uimm<2>;
266
267
268def uimm2_jmpix : Operand<i32>,
269  ImmLeaf<i32, "return Imm == 16 || Imm == 24 || Imm == 32 || Imm == 40;"> {
270  let EncoderMethod = "getImmJMPIX";
271  let DecoderMethod = "decodeJMPIXImmOperand";
272}
273
274def uimm3 : uimm<3>;
275def uimm4 : uimm<4>;
276def uimm5 : uimm<5> {
277  let MCOperandPredicate = [{
278    int64_t Imm;
279    if (MCOp.evaluateAsConstantImm(Imm))
280      return isShiftedUInt<5, 0>(Imm);
281    return MCOp.isBareSymbolRef();
282  }];
283}
284def uimm5_msb_size : uimm<5> {
285  let EncoderMethod = "getImmOpValueMSBSize";
286}
287
288def uimm5_1 : uimm<5, 1> {
289  let MCOperandPredicate = [{
290    int64_t Imm;
291    if (MCOp.evaluateAsConstantImm(Imm))
292      return isShiftedUInt<5, 1>(Imm);
293    return MCOp.isBareSymbolRef();
294  }];
295}
296def uimm5_2 : uimm<5, 2> {
297  let MCOperandPredicate = [{
298    int64_t Imm;
299    if (MCOp.evaluateAsConstantImm(Imm))
300      return isShiftedUInt<5, 2>(Imm);
301    return MCOp.isBareSymbolRef();
302  }];
303}
304def uimm6 : uimm<6>;
305def uimm7 : uimm<7>;
306def uimm7_1 : uimm<7, 1>;
307def uimm7_2 : uimm<7, 2>{
308  let MCOperandPredicate = [{
309    int64_t Imm;
310    if (MCOp.evaluateAsConstantImm(Imm))
311      return isShiftedUInt<7, 2>(Imm);
312    return MCOp.isBareSymbolRef();
313  }];
314}
315def uimm7_3 : uimm<7, 3>;
316def uimm8 : uimm<8> {
317  let MCOperandPredicate = [{
318    int64_t Imm;
319    if (MCOp.evaluateAsConstantImm(Imm))
320      return isShiftedUInt<8, 0>(Imm);
321    return MCOp.isBareSymbolRef();
322  }];
323}
324def uimm8_2 : uimm<8, 2> {
325  let MCOperandPredicate = [{
326    int64_t Imm;
327    if (MCOp.evaluateAsConstantImm(Imm))
328      return isShiftedUInt<8, 2>(Imm);
329    return MCOp.isBareSymbolRef();
330  }];
331}
332def uimm8_3 : uimm<8, 3>;
333def uimm8_8 : uimm<8, 8>;
334def uimm8_16 : uimm<8, 16>;
335def uimm8_24 : uimm<8, 24>;
336def uimm12 : uimm<12>  {
337  let MCOperandPredicate = [{
338    int64_t Imm;
339    if (MCOp.evaluateAsConstantImm(Imm))
340      return isShiftedUInt<12, 0>(Imm);
341    return MCOp.isBareSymbolRef();
342  }];
343}
344def uimm12_1 : uimm<12, 1> {
345  let MCOperandPredicate = [{
346    int64_t Imm;
347    if (MCOp.evaluateAsConstantImm(Imm))
348      return isShiftedUInt<12, 1>(Imm);
349    return MCOp.isBareSymbolRef();
350  }];
351}
352def uimm12_2 : uimm<12, 2> {
353  let MCOperandPredicate = [{
354    int64_t Imm;
355    if (MCOp.evaluateAsConstantImm(Imm))
356      return isShiftedUInt<12, 2>(Imm);
357    return MCOp.isBareSymbolRef();
358  }];
359}
360def uimm16 : uimm<16> {
361  let MCOperandPredicate = [{
362    int64_t Imm;
363    if (MCOp.evaluateAsConstantImm(Imm))
364      return isShiftedUInt<16, 0>(Imm);
365    return MCOp.isBareSymbolRef();
366  }];
367}
368def uimm16_8 : uimm<16, 8>;
369def uimm16_16 : uimm<16, 16>;
370def uimm20 : uimm<20>;
371def uimm24 : uimm<24>;
372def uimm24_8 : uimm<24, 8>;
373
374def simm8_2 : simm<8, 2>;
375
376class RegSeqAsmOperand<string Suffix = ""> : AsmOperandClass {
377  let Name = "RegSeq"#Suffix;
378  let RenderMethod = "addRegSeqOperands";
379  let DiagnosticType = "InvalidRegSeq";
380  let ParserMethod = "parseRegSeq";
381}
382
383def regseq : Operand<iPTR> {
384  let EncoderMethod = "getRegisterSeqOpValue";
385  let ParserMatchClass = RegSeqAsmOperand<"">;
386  let PrintMethod = "printRegisterSeq";
387  let DecoderMethod = "DecodeRegSeqOperand";
388  let MIOperandInfo = (ops GPR, uimm5);
389}
390
391def RegListAsmOperand : AsmOperandClass {
392  let Name = "RegList";
393  let RenderMethod = "addRegListOperands";
394  let DiagnosticType = "InvalidRegList";
395  let ParserMethod = "parseRegList";
396}
397
398def reglist : Operand<iPTR> {
399  let ParserMatchClass = RegListAsmOperand;
400  let PrintMethod = "printRegisterList";
401}
402
403def PSRFlag : AsmOperandClass {
404  let Name = "PSRFlag";
405  let RenderMethod = "addImmOperands";
406  let DiagnosticType = "InvalidPSRFlag";
407  let ParserMethod = "parsePSRFlag";
408}
409
410def psrflag : Operand<i32>, ImmLeaf<i32, "return isShiftedUInt<5, 0>(Imm);"> {
411  let EncoderMethod = "getImmOpValue";
412  let ParserMatchClass = PSRFlag;
413  let PrintMethod = "printPSRFlag";
414}
415
416multiclass uimm8SRLXForm<SDNode opc> {
417  def _0: SDNodeXForm<opc,
418    [{return CurDAG->getTargetConstant((N->getZExtValue() >> 0) & 0xFF, SDLoc(N), MVT::i32);}]>;
419  def _8: SDNodeXForm<opc,
420    [{return CurDAG->getTargetConstant((N->getZExtValue() >> 8) & 0xFF, SDLoc(N), MVT::i32);}]>;
421  def _16: SDNodeXForm<opc,
422    [{return CurDAG->getTargetConstant((N->getZExtValue() >> 16) & 0xFF, SDLoc(N), MVT::i32);}]>;
423  def _24: SDNodeXForm<opc,
424    [{return CurDAG->getTargetConstant((N->getZExtValue() >> 24) & 0xFF, SDLoc(N), MVT::i32);}]>;
425}
426
427defm uimm8SRL : uimm8SRLXForm<imm>;
428
429//===----------------------------------------------------------------------===//
430// Instruction Formats
431//===----------------------------------------------------------------------===//
432
433include "CSKYInstrFormats.td"
434
435//===----------------------------------------------------------------------===//
436// Instruction definitions.
437//===----------------------------------------------------------------------===//
438
439class TriOpFrag<dag res> : PatFrag<(ops node: $LHS, node:$MHS, node:$RHS), res>;
440class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
441class UnOpFrag<dag res> : PatFrag<(ops node:$Src), res>;
442
443def eqToAdd : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs), [{
444  return isOrEquivalentToAdd(N);
445}]>;
446
447def BaseAddr : ComplexPattern<iPTR, 1, "SelectBaseAddr">;
448
449
450//===----------------------------------------------------------------------===//
451// CSKYPseudo
452//===----------------------------------------------------------------------===//
453
454// Pessimistically assume the stack pointer will be clobbered
455let Defs = [R14], Uses = [R14] in {
456def ADJCALLSTACKDOWN : CSKYPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
457  "!ADJCALLSTACKDOWN $amt1, $amt2", [(callseq_start timm:$amt1, timm:$amt2)]>;
458def ADJCALLSTACKUP   : CSKYPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
459  "!ADJCALLSTACKUP $amt1, $amt2", [(callseq_end timm:$amt1, timm:$amt2)]>;
460} // Defs = [R14], Uses = [R14]
461
462
463//===----------------------------------------------------------------------===//
464// Basic ALU instructions.
465//===----------------------------------------------------------------------===//
466
467let Predicates = [iHasE2] in {
468  let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
469  let isAdd = 1 in
470  def ADDI32 : I_12<0x0, "addi32", add, oimm12>;
471  def SUBI32 : I_12<0x1, "subi32", sub, oimm12>;
472  def ORI32 : I_16_ZX<"ori32", uimm16,
473  [(set GPR:$rz, (or GPR:$rx, uimm16:$imm16))]>;
474  def XORI32 : I_12<0x4, "xori32", xor, uimm12>;
475  def ANDI32 : I_12<0x2, "andi32", and, uimm12>;
476  def ANDNI32 : I_12<0x3, "andni32", and, nimm12>;
477  def LSLI32 : I_5_XZ<0x12, 0x1, "lsli32",
478    (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
479    [(set GPR:$rz, (shl GPR:$rx, uimm5:$imm5))]>;
480  def LSRI32 : I_5_XZ<0x12, 0x2, "lsri32",
481    (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
482    [(set GPR:$rz, (srl GPR:$rx, uimm5:$imm5))]>;
483  def ASRI32 : I_5_XZ<0x12, 0x4, "asri32",
484    (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
485    [(set GPR:$rz, (sra GPR:$rx, uimm5:$imm5))]>;
486  def ROTLI32 : I_5_XZ<0x12, 0x8, "rotli32",
487    (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5),
488    [(set GPR:$rz, (rotl GPR:$rx, uimm5:$imm5))]>;
489
490  def ROTRI32 : CSKYPseudo<(outs GPR:$rz), (ins GPR:$rx, oimm5:$imm5),
491                            "rotri32 $rz, $rx, $imm5", []>;
492  }
493  let isAdd = 1 in
494  def ADDU32 : R_YXZ_SP_F1<0x0, 0x1,
495    BinOpFrag<(add node:$LHS, node:$RHS)>, "addu32", 1>;
496  def SUBU32 : R_YXZ_SP_F1<0x0, 0x4,
497    BinOpFrag<(sub node:$LHS, node:$RHS)>, "subu32">;
498
499  def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
500    BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
501  def AND32 : R_YXZ_SP_F1<0x8, 0x1,
502    BinOpFrag<(and node:$LHS, node:$RHS)>, "and32", 1>;
503  def ANDN32 : R_YXZ_SP_F1<0x8, 0x2,
504    BinOpFrag<(and node:$LHS, (not node:$RHS))>, "andn32">;
505  def OR32: R_YXZ_SP_F1<0x9, 0x1,
506    BinOpFrag<(or node:$LHS, node:$RHS)>, "or32", 1>;
507  def XOR32 : R_YXZ_SP_F1<0x9, 0x2,
508    BinOpFrag<(xor node:$LHS, node:$RHS)>, "xor32", 1>;
509  def NOR32 : R_YXZ_SP_F1<0x9, 0x4,
510    BinOpFrag<(not (or node:$LHS, node:$RHS))>, "nor32", 1>;
511  let isCodeGenOnly = 1 in
512  def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
513    "not32", [(set GPR:$rz, (not GPR:$rx))]>;
514
515  let Size = 8 in
516  def NEG32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx), "neg32 $rd, $rx", []>;
517
518  let Size = 8 in
519  def RSUBI32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx, uimm12:$imm12), "rsubi32 $rd, $rx, $imm12", []>;
520
521  def LSL32 : R_YXZ_SP_F1<0x10, 0x1,
522    BinOpFrag<(shl node:$LHS, node:$RHS)>, "lsl32">;
523  def LSR32 : R_YXZ_SP_F1<0x10, 0x2,
524    BinOpFrag<(srl node:$LHS, node:$RHS)>, "lsr32">;
525  def ASR32 : R_YXZ_SP_F1<0x10, 0x4,
526    BinOpFrag<(sra node:$LHS, node:$RHS)>, "asr32">;
527  def ROTL32 : R_YXZ_SP_F1<0x10, 0x8,
528    BinOpFrag<(rotl node:$LHS, (and node:$RHS, 0x1f))>, "rotl32">;
529
530  def BMASKI32 : I_5_Z<0b010100, 0x1, "bmaski32", oimm5, []>;
531  def LSLC32 : I_5_XZ<0x13, 0x1, "lslc32",
532    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
533  def LSRC32 : I_5_XZ<0x13, 0x2, "lsrc32",
534    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
535  def ASRC32 : I_5_XZ<0x13, 0x4, "asrc32",
536    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5), []>;
537  def XSR32 : I_5_XZ<0x13, 0x8, "xsr32",
538    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, oimm5:$imm5, CARRY:$cin), []>;
539
540  def IXH32 : R_YXZ_SP_F1<0x2, 0x1,
541    BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 1)))>, "ixh32">;
542  def IXW32 : R_YXZ_SP_F1<0x2, 0x2,
543    BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 2)))>, "ixw32">;
544  let Predicates = [iHas2E3] in
545  def IXD32 : R_YXZ_SP_F1<0x2, 0x4,
546    BinOpFrag<(add node:$LHS, (shl node:$RHS, (i32 3)))>, "ixd32">;
547
548  let isCommutable = 1, isAdd = 1 in
549  def ADDC32 : R_YXZ<0x31, 0x0, 0x2, (outs GPR:$rz, CARRY:$cout),
550    (ins GPR:$rx, GPR:$ry, CARRY:$cin), "addc32", []>;
551  def SUBC32 : R_YXZ<0x31, 0x0, 0x8, (outs GPR:$rz, CARRY:$cout),
552    (ins GPR:$rx, GPR:$ry, CARRY:$cin), "subc32", []>;
553
554  def INCF32 : I_5_ZX<0x3, 0x1, "incf32", uimm5, []>;
555  def INCT32 : I_5_ZX<0x3, 0x2, "inct32", uimm5, []>;
556  def DECF32 : I_5_ZX<0x3, 0x4, "decf32", uimm5, []>;
557  def DECT32 : I_5_ZX<0x3, 0x8, "dect32", uimm5, []>;
558}
559
560let Predicates = [iHas2E3] in {
561  def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
562    BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
563  def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
564    BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
565
566  def DECGT32 : I_5_XZ<0x4, 0x1, "decgt32",
567    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
568  def DECLT32 : I_5_XZ<0x4, 0x2, "declt32",
569    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
570  def DECNE32 : I_5_XZ<0x4, 0x4, "decne32",
571    (outs GPR:$rz, CARRY:$cout), (ins GPR:$rx, uimm5:$imm5), []>;
572
573  def SEXT32 : I_5_XZ_U<0x16, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "sext32", []>;
574  let isCodeGenOnly = 1 in {
575  def SEXTB32 : I_5_XZ_US<0x16, 0, 7, "sextb32", sext_inreg, i8>;
576  def SEXTH32 : I_5_XZ_US<0x16, 0, 15, "sexth32", sext_inreg, i16>;
577  def ZEXTB32 : I_5_XZ_UZ<0x15, 0, 7, "zextb32", 255>;
578  def ZEXTH32 : I_5_XZ_UZ<0x15, 0, 15, "zexth32", 65535>;
579  }
580  def ZEXT32 : I_5_XZ_U<0x15, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), "zext32",[]>;
581
582  let Constraints = "$rZ = $rz" in
583  def INS32 : I_5_XZ_INS<0b010111, (outs GPR:$rz), (ins GPR:$rZ, GPR:$rx, uimm5_msb_size:$msb, uimm5:$lsb), "ins32", []>;
584}
585
586let Predicates = [iHas3E3r1] in {
587def MULTS32 : R_YXZ<0x3e, 0x20, 0x10, (outs GPRPair:$rz),
588    (ins GPR:$rx, GPR:$ry), "mul.s32", []>;
589def MULTU32 : R_YXZ<0x3e, 0x20, 0x00, (outs GPRPair:$rz),
590    (ins GPR:$rx, GPR:$ry), "mul.u32", []>;
591
592let Constraints = "$rZ = $rz" in {
593def MULATS32 : R_YXZ<0x3e, 0x20, 0x14, (outs GPRPair:$rZ),
594    (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.s32", []>;
595def MULATU32 : R_YXZ<0x3e, 0x20, 0x04, (outs GPRPair:$rZ),
596    (ins GPRPair:$rz, GPR:$rx, GPR:$ry), "mula.u32", []>;
597}
598}
599
600def MULSH32 : R_YXZ<0x31, 0b100100, 0b00001, (outs GPR:$rz),
601    (ins GPR:$rx, GPR:$ry), "mulsh32", []>;
602
603//===----------------------------------------------------------------------===//
604// Load & Store instructions.
605//===----------------------------------------------------------------------===//
606
607def LD32B : I_LD<AddrMode32B, 0x0, "ld32.b", uimm12>;
608def LD32H : I_LD<AddrMode32H, 0x1, "ld32.h", uimm12_1>;
609def LD32W : I_LD<AddrMode32WD, 0x2, "ld32.w", uimm12_2>;
610
611let OutOperandList = (outs GPRPair:$rz) in
612def LD32D : I_LD<AddrMode32WD, 0x3, "ld32.d", uimm12_2>;
613
614let Predicates = [iHasE2] in {
615  def LD32BS : I_LD<AddrMode32B, 0x4, "ld32.bs", uimm12>;
616  def LD32HS : I_LD<AddrMode32H, 0x5, "ld32.hs", uimm12_1>;
617
618  def LDM32 : I_5_YX<0b110100, 0b000111,
619    (outs), (ins GPR:$rx, regseq:$regs, variable_ops), "ldm32\t$regs, (${rx})", []>;
620  def STM32 : I_5_YX<0b110101, 0b000111,
621    (outs), (ins GPR:$rx, regseq:$regs, variable_ops), "stm32\t$regs, (${rx})", []>;
622
623  let Size = 4, isCodeGenOnly = 0 in {
624  def LDQ32 : CSKYPseudo<(outs), (ins GPR:$rx, regseq:$regs, variable_ops),
625                             "ldq32\t$regs, (${rx})", []>;
626  def STQ32 : CSKYPseudo<(outs), (ins GPR:$rx, regseq:$regs, variable_ops),
627                             "stq32\t$regs, (${rx})", []>;
628  }
629
630}
631
632def ST32B : I_ST<AddrMode32B, 0x0, "st32.b", uimm12>;
633def ST32H : I_ST<AddrMode32H, 0x1, "st32.h", uimm12_1>;
634def ST32W : I_ST<AddrMode32WD, 0x2, "st32.w", uimm12_2>;
635
636let InOperandList = (ins GPRPair:$rz, GPR:$rx, uimm12_2:$imm12 ) in
637def ST32D : I_ST<AddrMode32WD, 0x3, "st32.d", uimm12_2>;
638
639let Predicates = [iHas2E3] in {
640  def LDR32B :  I_LDR<0x0, "ldr32.b">;
641  def LDR32BS :  I_LDR<0x4, "ldr32.bs">;
642  def LDR32H :  I_LDR<0x1, "ldr32.h">;
643  def LDR32HS :  I_LDR<0x5, "ldr32.hs">;
644  def LDR32W :  I_LDR<0x2, "ldr32.w">;
645  def STR32B :  I_STR<0x0, "str32.b">;
646  def STR32H :  I_STR<0x1, "str32.h">;
647  def STR32W :  I_STR<0x2, "str32.w">;
648}
649
650// Indicate that we're dumping the CR register, so we'll need to
651// scavenge a register for it.
652let mayStore = 1 in {
653def SPILL_CARRY : CSKYPseudo<(outs), (ins CARRY:$cond, GPR:$rx, uimm12_2:$imm),
654                             "!SPILL_CARRY $cond, $rx, $imm", []>;
655}
656
657// Indicate that we're restoring the CR register (previously
658// spilled), so we'll need to scavenge a register for it.
659let mayLoad = 1 in {
660def RESTORE_CARRY : CSKYPseudo<(outs CARRY:$cond), (ins GPR:$rx, uimm12_2:$imm),
661                                "!RESTORE_CARRY $cond, $rx, $imm", []>;
662}
663
664let mayLoad = 1 in {
665def STORE_PAIR : CSKYPseudo<(outs), (ins GPRPair:$rz, GPR:$rx, uimm12_2:$imm),
666                            "!STORE_PAIR $rz, $rx, $imm", []>;
667}
668
669let mayLoad = 1 in {
670def LOAD_PAIR : CSKYPseudo<(outs GPRPair:$rz), (ins GPR:$rx, uimm12_2:$imm),
671                            "!LOAD_PAIR $rz, $rx, $imm", []>;
672}
673
674//===----------------------------------------------------------------------===//
675// Compare instructions.
676//===----------------------------------------------------------------------===//
677let Predicates = [iHasE2] in {
678  def CMPNEI32 : I_16_X<0x1A, "cmpnei32", uimm16>;
679  def CMPHSI32 : I_16_X<0x18, "cmphsi32", oimm16>;
680  def CMPLTI32 : I_16_X<0x19, "cmplti32", oimm16>;
681  def CMPLEI32 : CSKYPseudo<(outs CARRY:$ca), (ins GPR:$rx, uimm16:$imm16),
682    "cmplei32\t$rx, $imm16", []>;
683}
684let Predicates = [iHas2E3] in {
685  def CMPNE32 : R_YX<0x1, 0x4, "cmpne32">;
686  def CMPHS32 : R_YX<0x1, 0x1, "cmphs32">;
687  def CMPLT32 : R_YX<0x1, 0x2, "cmplt32">;
688
689  def SETC32 : CSKY32Inst<AddrModeNone, 0x31,
690    (outs CARRY:$ca), (ins), "setc32", []> {
691    let Inst{25 - 21} = 0; //rx
692    let Inst{20 - 16} = 0; //ry
693    let Inst{15 - 10} = 0x1;
694    let Inst{9 - 5} = 0x1;
695    let Inst{4 - 0} = 0;
696    let isCompare = 1;
697  }
698  def CLRC32 : CSKY32Inst<AddrModeNone, 0x31,
699    (outs CARRY:$ca), (ins), "clrc32", []> {
700    let Inst{25 - 21} = 0; //rx
701    let Inst{20 - 16} = 0; //ry
702    let Inst{15 - 10} = 0x1;
703    let Inst{9 - 5} = 0x4;
704    let Inst{4 - 0} = 0;
705    let isCompare = 1;
706  }
707
708  def TST32 : R_YX<0x8, 0x4, "tst32">;
709  def TSTNBZ32 : R_X<0x8, 0x8,
710    (outs CARRY:$ca), (ins GPR:$rx), "tstnbz32", []>;
711}
712
713//===----------------------------------------------------------------------===//
714// Data move instructions.
715//===----------------------------------------------------------------------===//
716
717let Predicates= [iHasE2] in {
718  let isCodeGenOnly = 1 in {
719  def MOVT32 : R_ZX<0x3, 0x2, "movt32", []>;
720  def MOVF32 : R_ZX<0x3, 0x1, "movf32", []>;
721  }
722  def MOVI32 : I_16_MOV<0x10, "movi32", uimm16>;
723  let Size = 4, isCodeGenOnly = 0 in
724  def BGENI : CSKYPseudo<(outs GPR:$dst), (ins uimm5:$imm), "bgeni\t$dst, $imm", []>;
725  def MOVIH32 : I_16_MOV<0x11, "movih32", uimm16_16_xform>;
726  def MVC32 : R_Z_1<0x1, 0x8, "mvc32">;
727  let isCodeGenOnly = 1 in
728  def MOV32 : R_XZ<0x12, 0x1, "mov32">;
729
730  let usesCustomInserter = 1 in
731  def ISEL32 : CSKYPseudo<(outs GPR:$dst), (ins CARRY:$cond, GPR:$src1, GPR:$src2),
732    "!isel32\t$dst, $src1, src2", [(set GPR:$dst, (select CARRY:$cond, GPR:$src1, GPR:$src2))]>;
733}
734
735let Predicates = [iHas2E3] in {
736  def MVCV32 : R_Z_1<0x1, 0x10, "mvcv32">;
737  def CLRF32 : R_Z_2<0xB, 0x1, "clrf32">;
738  def CLRT32 : R_Z_2<0xB, 0x2, "clrt32">;
739}
740
741//===----------------------------------------------------------------------===//
742// Branch and call instructions.
743//===----------------------------------------------------------------------===//
744
745let isBranch = 1, isTerminator = 1 in {
746  let isBarrier = 1, isPredicable = 1 in
747    def BR32 : I_16_L<0x0, (outs), (ins br_symbol:$imm16), "br32\t$imm16",
748                     [(br bb:$imm16)]>;
749
750  def BT32 : I_16_L<0x3, (outs), (ins CARRY:$ca, br_symbol:$imm16),
751    "bt32\t$imm16", [(brcond CARRY:$ca, bb:$imm16)]>, Requires<[iHasE2]>;
752  def BF32 : I_16_L<0x2, (outs), (ins CARRY:$ca, br_symbol:$imm16),
753    "bf32\t$imm16", []>, Requires<[iHasE2]>;
754}
755
756let Predicates = [iHas2E3] in {
757  def BEZ32 : I_16_X_L<0x8, "bez32", br_symbol>;
758  def BNEZ32 : I_16_X_L<0x9, "bnez32", br_symbol>;
759  def BHZ32 : I_16_X_L<0xA, "bhz32", br_symbol>;
760  def BLSZ32 : I_16_X_L<0xB, "blsz32", br_symbol>;
761  def BLZ32 : I_16_X_L<0xC, "blz32", br_symbol>;
762  def BHSZ32 : I_16_X_L<0xD, "bhsz32", br_symbol>;
763
764  let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
765    def JMP32 : I_16_JX<0x6, "jmp32", [(brind GPR:$rx)]>; // jmp to register
766    def JMPI32 : I_16_L<0x16, (outs), (ins constpool_symbol:$imm16),
767                   "jmpi32\t$imm16", []>;
768  }
769
770  let isCall = 1, Defs = [ R15 ] in
771    def JSR32 : I_16_JX<0x7, "jsr32", []>;
772
773  let isCall = 1, Defs = [ R15 ] , mayLoad = 1 in
774    def JSRI32: I_16_L<0x17, (outs),
775      (ins constpool_symbol:$imm16), "jsri32\t$imm16", []>;
776}
777
778def BNEZAD32 : CSKY32Inst<AddrModeNone, 0x3a,
779  (outs GPR:$rx_u), (ins GPR:$rx, br_symbol:$imm16), "bnezad32\t$rx, $imm16", []> {
780  bits<5> rx;
781  bits<16> imm16;
782  let Inst{25 - 21} = 0x1;
783  let Inst{20 - 16} = rx;
784  let Inst{15 - 0} = imm16;
785  let isBranch = 1;
786  let isTerminator = 1;
787  let Constraints = "$rx_u = $rx";
788  let Predicates = [iHas2E3, iHas10E60];
789}
790
791def BSR32 : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>;
792
793def BSR32_BR : J<0x38, (outs), (ins call_symbol:$offset), "bsr32", []>{
794  let isCodeGenOnly = 1;
795  let isBranch = 1;
796  let isTerminator = 1;
797  let isBarrier = 1;
798  let isPredicable = 1;
799  let Defs = [ R15 ];
800}
801
802//===----------------------------------------------------------------------===//
803// Symbol address instructions.
804//===----------------------------------------------------------------------===//
805
806def data_symbol_b : data_symbol<"CSKY::fixup_csky_doffset_imm18", 0>;
807def data_symbol_h : data_symbol<"CSKY::fixup_csky_doffset_imm18_scale2", 1>;
808def data_symbol_w : data_symbol<"CSKY::fixup_csky_doffset_imm18_scale4", 2> {
809  let ParserMatchClass = DataAsmClass;
810}
811
812let Predicates = [iHas2E3] in {
813
814def GRS32 : I_18_Z_L<0x3, "grs32\t$rz, $offset",
815                    (outs GPR:$rz), (ins bare_symbol:$offset), []>;
816
817let Uses = [R28] in {
818def LRS32B : I_18_Z_L<0x0, "lrs32.b\t$rz, $offset",
819                    (outs GPR:$rz), (ins data_symbol_b:$offset), []>;
820def LRS32H : I_18_Z_L<0x1, "lrs32.h\t$rz, $offset",
821                    (outs GPR:$rz), (ins data_symbol_h:$offset), []>;
822def LRS32W : I_18_Z_L<0x2, "lrs32.w\t$rz, $offset",
823                    (outs GPR:$rz), (ins data_symbol_w:$offset), []>;
824def SRS32B : I_18_Z_L<0x4, "srs32.b\t$rz, $offset",
825                    (outs), (ins GPR:$rz, data_symbol_b:$offset), []>;
826def SRS32H : I_18_Z_L<0x5, "srs32.h\t$rz, $offset",
827                    (outs), (ins GPR:$rz, data_symbol_h:$offset), []>;
828def SRS32W : I_18_Z_L<0x6, "srs32.w\t$rz, $offset",
829                    (outs), (ins GPR:$rz, data_symbol_w:$offset), []>;
830}
831
832def PUSH32 : I_12_PP<0b11111, 0b00000, (outs), (ins reglist:$regs, variable_ops), "push32 $regs">;
833
834let Uses = [R14, R15], isReturn = 1, isTerminator = 1, isBarrier = 1 in
835def POP32 : I_12_PP<0b11110, 0b00000, (outs), (ins reglist:$regs, variable_ops), "pop32 $regs">;
836
837}
838
839let mayLoad = 1, mayStore = 0 in {
840def LRW32 : I_16_Z_L<0x14, "lrw32", (ins constpool_symbol:$imm16), []>;
841let isCodeGenOnly = 1 in
842def LRW32_Gen : I_16_Z_L<0x14, "lrw32", (ins bare_symbol:$src1, constpool_symbol:$imm16), []>;
843}
844
845//===----------------------------------------------------------------------===//
846// Atomic and fence instructions.
847//===----------------------------------------------------------------------===//
848
849let Predicates = [iHasMP1E2] in {
850  def BRWARW : BAR<0b01111, "bar.brwarw", 0>;
851  def BRWARWS : BAR<0b01111, "bar.brwarws", 1>;
852  def BRARW : BAR<0b00111, "bar.brarw", 0>;
853  def BRARWS : BAR<0b00111, "bar.brarws", 1>;
854  def BRWAW : BAR<0b01110, "bar.brwaw", 0>;
855  def BRWAWS : BAR<0b01110, "bar.brwaws", 1>;
856  def BRAR : BAR<0b00101, "bar.brar", 0>;
857  def BRARS : BAR<0b00101, "bar.brars", 1>;
858  def BWAW : BAR<0b01010, "bar.bwaw", 0>;
859  def BWAWS : BAR<0b01010, "bar.bwaws", 1>;
860
861  def LDEX32W : I_LD<AddrMode32WD, 0x7, "ldex32.w", uimm12_2>;
862  let Constraints = "$rd = $rz" in
863    def STEX32W : I_LDST<AddrMode32WD, 0x37, 7,
864      (outs GPR:$rd), (ins GPR:$rz, GPR:$rx, uimm12_2:$imm12), "stex32.w", []>;
865}
866
867//===----------------------------------------------------------------------===//
868// Other operation instructions.
869//===----------------------------------------------------------------------===//
870
871let Predicates = [iHas2E3] in {
872  def BREV32 : R_XZ<0x18, 0x10, "brev32">;
873  def ABS32 : R_XZ<0x0, 0x10, "abs32">;
874  def BGENR32 : R_XZ<0x14, 0x2, "bgenr32">;
875}
876
877let Predicates = [iHasE2] in {
878  def REVB32 : R_XZ<0x18, 0x4, "revb32">;
879  def REVH32 : R_XZ<0x18, 0x8, "revh32">;
880  def FF0 : R_XZ<0x1F, 0x1, "ff0.32">;
881  def FF1 : R_XZ<0x1F, 0x2, "ff1.32">;
882  def XTRB0 : R_XZ<0x1C, 0x1, "xtrb0.32">;
883  def XTRB1 : R_XZ<0x1C, 0x2, "xtrb1.32">;
884  def XTRB2 : R_XZ<0x1C, 0x4, "xtrb2.32">;
885  def XTRB3 : R_XZ<0x1C, 0x8, "xtrb3.32">;
886  def BTSTI32 : I_5_X<0x0A, 0x4, "btsti32", uimm5, []>;
887  def BCLRI32 : I_5_XZ<0xA, 0x1, "bclri32",
888  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;
889  def BSETI32 : I_5_XZ<0xA, 0x2, "bseti32",
890  (outs GPR:$rz), (ins GPR:$rx, uimm5:$imm5), []>;
891}
892
893//===----------------------------------------------------------------------===//
894// Special instructions.
895//===----------------------------------------------------------------------===//
896
897def MFFCR : CSKY32Inst<AddrModeNone, 0x30,
898  (outs GPR:$rx), (ins), "mfcr\t$rx, fcr", []> {
899  bits<5> rx;
900
901  let Inst{25 - 21} = 0b00010;
902  let Inst{20 - 16} = 0b00001;
903  let Inst{15 - 10} = 0b011000;
904  let Inst{9 - 5} = 0b00001;
905  let Inst{4 - 0} = rx;
906  let hasSideEffects = 1;
907  let isCodeGenOnly = 1;
908}
909
910def MTFCR : CSKY32Inst<AddrModeNone, 0x30,
911  (outs), (ins GPR:$rx), "mtcr\t$rx, fcr", []> {
912  bits<5> rx;
913
914  let Inst{25 - 21} = 0b00010;
915  let Inst{20 - 16} = rx;
916  let Inst{15 - 10} = 0b011001;
917  let Inst{9 - 5} = 0b00001;
918  let Inst{4 - 0} = 0b00001;
919  let hasSideEffects = 1;
920  let isCodeGenOnly = 1;
921}
922
923def SYNC32 : I_5_IMM5<0x30, 0b000001, 0b00001, "sync32", uimm5, []>;
924
925def SYNC0_32 : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),
926                 "sync32", []> {
927  let Inst{25 - 21} = 0;
928  let Inst{20 - 16} = 0;
929  let Inst{15 - 10} = 0b000001;
930  let Inst{9 - 5} = 0b00001;
931  let Inst{4 - 0} = 0;
932}
933
934def SYNC_32_I : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),
935                 "sync32.i", []> {
936  let Inst{25 - 21} = 1;
937  let Inst{20 - 16} = 0;
938  let Inst{15 - 10} = 0b000001;
939  let Inst{9 - 5} = 0b00001;
940  let Inst{4 - 0} = 0;
941}
942
943def SYNC_32_S : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),
944                 "sync32.s", []> {
945  let Inst{25 - 21} = 0b10000;
946  let Inst{20 - 16} = 0;
947  let Inst{15 - 10} = 0b000001;
948  let Inst{9 - 5} = 0b00001;
949  let Inst{4 - 0} = 0;
950}
951
952def SYNC_32_IS : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins),
953                 "sync32.is", []> {
954  let Inst{25 - 21} = 0b10001;
955  let Inst{20 - 16} = 0;
956  let Inst{15 - 10} = 0b000001;
957  let Inst{9 - 5} = 0b00001;
958  let Inst{4 - 0} = 0;
959}
960
961let Predicates = [iHas2E3] in {
962  def RFI32 : I_5_XZ_PRIVI<0x11, 0x1, "rfi32">;
963  def SCE32 : I_5_IMM5<0x30, 0b000110, 0b00001, "sce32", uimm4, []>;
964}
965let Predicates = [HasExtendLrw] in
966def IDLY32 : I_5_IMM5<0x30, 0b000111, 0b00001, "idly32", imm5_idly, []>;
967def STOP32 : I_5_XZ_PRIVI<0x12, 0x1, "stop32">;
968def WAIT32 : I_5_XZ_PRIVI<0x13, 0x1, "wait32">;
969def DOZE32 : I_5_XZ_PRIVI<0x14, 0x1, "doze32">;
970def WE32 : I_5_XZ_PRIVI<0b010101, 0x1, "we32">;
971def SE32 : I_5_XZ_PRIVI<0b010110, 0x1, "se32">;
972def WSC32 : I_5_XZ_PRIVI<0b001111, 0x1, "wsc32">;
973
974def CPOP32 : I_CPOP<(outs), (ins uimm5:$cpid, uimm20:$usdef), "cpop32 <$cpid, ${usdef}>">;
975def CPRC32 : I_CP<0b0100, (outs CARRY:$ca), (ins uimm5:$cpid, uimm12:$usdef), "cprc32 <$cpid, ${usdef}>">;
976def CPRCR32 : I_CP_Z<0b0010, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprcr32 $rz, <$cpid, ${usdef}>">;
977def CPRGR32 : I_CP_Z<0b0000, (outs GPR:$rz), (ins uimm5:$cpid, uimm12:$usdef), "cprgr32 $rz, <$cpid, ${usdef}>">;
978def CPWCR32 : I_CP_Z<0b0011, (outs), (ins GPR:$rz, uimm5:$cpid, uimm12:$usdef), "cpwcr32 $rz, <$cpid, ${usdef}>">;
979def CPWGR32 : I_CP_Z<0b0001, (outs), (ins GPR:$rz, uimm5:$cpid, uimm12:$usdef), "cpwgr32 $rz, <$cpid, ${usdef}>">;
980
981let Predicates = [iHas3r2E3r3] in {
982def DCACHE_IALL32 : I_5_CACHE<0b100101, 0b01000, "dcache32.iall">;
983def DCACHE_CALL32 : I_5_CACHE<0b100101, 0b00100, "dcache32.call">;
984def DCACHE_CIALL32 : I_5_CACHE<0b100101, 0b01100, "dcache32.ciall">;
985def DCACHE_IVA32 : I_5_X_CACHE<0b100101, 0b01011, "dcache32.iva">;
986def DCACHE_ISW32: I_5_X_CACHE<0b100101, 0b01010, "dcache32.isw">;
987def DCACHE_CVA32 : I_5_X_CACHE<0b100101, 0b00111, "dcache32.cva">;
988def DCACHE_CVAL32 : I_5_X_CACHE<0b100101, 0b10111, "dcache32.cval1">;
989def DCACHE_CSW32 : I_5_X_CACHE<0b100101, 0b00110, "dcache32.csw">;
990def DCACHE_CIVA32 : I_5_X_CACHE<0b100101, 0b01111, "dcache32.civa">;
991def DCACHE_CISW32 : I_5_X_CACHE<0b100101, 0b01110, "dcache32.cisw">;
992
993def ICACHE_IALL32 : I_5_CACHE<0b100100, 0b01000, "icache32.iall">;
994def ICACHE_IALLS32 : I_5_CACHE<0b100100, 0b11000, "icache32.ialls">;
995def ICACHE_IVA32 : I_5_X_CACHE<0b100100, 0b01011, "icache32.iva">;
996
997def TLBI_VAA32 : I_5_X_CACHE<0b100010, 0b00010, "tlbi32.vaa">;
998def TLBI_VAAS32 : I_5_X_CACHE<0b100010, 0b10010, "tlbi32.vaas">;
999def TLBI_ASID32 : I_5_X_CACHE<0b100010, 0b00001, "tlbi32.asid">;
1000def TLBI_ASIDS32 : I_5_X_CACHE<0b100010, 0b10001, "tlbi32.asids">;
1001def TLBI_VA32 : I_5_X_CACHE<0b100010, 0b00011, "tlbi32.va">;
1002def TLBI_VAS32 : I_5_X_CACHE<0b100010, 0b10011, "tlbi32.vas">;
1003def TLBI_ALL32 : I_5_CACHE<0b100010, 0b00000, "tlbi32.all">;
1004def TLBI_ALLS32 : I_5_CACHE<0b100010, 0b10000, "tlbi32.alls">;
1005
1006def L2CACHE_IALL : I_5_CACHE<0b100110, 0b01000, "l2cache.iall">;
1007def L2CACHE_CALL : I_5_CACHE<0b100110, 0b00100, "l2cache.call">;
1008def L2CACHE_CIALL : I_5_CACHE<0b100110, 0b01100, "l2cache.ciall">;
1009}
1010
1011def PLDR32 :I_PLDR<AddrMode32WD, 0x36, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldr32", []>;
1012def PLDW32 :I_PLDR<AddrMode32WD, 0x37, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldw32", []>;
1013
1014def TRAP32 : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins uimm2:$imm2), "trap32 ${imm2}", []> {
1015  bits<2> imm2;
1016
1017  let Inst{25 - 21} = 0;
1018  let Inst{20 - 16} = 0;
1019  let Inst{15 - 12} = 0b0010;
1020  let Inst{11 - 10} = imm2;
1021  let Inst{9 - 5} = 0b00001;
1022  let Inst{4 - 0} = 0;
1023
1024}
1025
1026//===----------------------------------------------------------------------===//
1027// Instruction Patterns.
1028//===----------------------------------------------------------------------===//
1029
1030// Load & Store Patterns
1031multiclass LdPat<PatFrag LoadOp, ImmLeaf imm_type, Instruction Inst, ValueType Type> {
1032  def : Pat<(Type (LoadOp GPR:$rs1)), (Inst GPR:$rs1, 0)>;
1033  def : Pat<(Type (LoadOp (i32 frameindex:$rs1))), (Inst (i32 (to_tframeindex tframeindex:$rs1)), 0)>;
1034  def : Pat<(Type (LoadOp (add GPR:$rs1, imm_type:$uimm))),
1035            (Inst GPR:$rs1, imm_type:$uimm)>;
1036  def : Pat<(Type (LoadOp (add frameindex:$rs1, imm_type:$uimm))),
1037            (Inst (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm)>;
1038  def : Pat<(Type (LoadOp (eqToAdd frameindex:$rs1, imm_type:$uimm))),
1039            (Inst (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm)>;
1040  def : Pat<(Type (LoadOp (add GPR:$rs1, tglobaladdr:$gd))),
1041            (Inst GPR:$rs1, tglobaladdr:$gd)>;
1042}
1043
1044defm : LdPat<extloadi8, uimm12, LD32B, i32>;
1045defm : LdPat<zextloadi8, uimm12, LD32B, i32>;
1046let Predicates = [iHasE2] in {
1047  defm : LdPat<sextloadi8, uimm12, LD32BS, i32>;
1048}
1049defm : LdPat<extloadi16, uimm12_1, LD32H, i32>;
1050defm : LdPat<zextloadi16, uimm12_1, LD32H, i32>;
1051let Predicates = [iHasE2] in {
1052defm : LdPat<sextloadi16, uimm12_1, LD32HS, i32>;
1053}
1054defm : LdPat<load, uimm12_2, LD32W, i32>;
1055
1056multiclass LdrPat<PatFrag LoadOp, Instruction Inst, ValueType Type> {
1057  def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;
1058  def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>;
1059  def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>;
1060  def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>;
1061}
1062
1063let Predicates = [iHas2E3] in {
1064  defm : LdrPat<zextloadi8, LDR32B, i32>;
1065  defm : LdrPat<sextloadi8, LDR32BS, i32>;
1066  defm : LdrPat<extloadi8, LDR32BS, i32>;
1067  defm : LdrPat<zextloadi16, LDR32H, i32>;
1068  defm : LdrPat<sextloadi16, LDR32HS, i32>;
1069  defm : LdrPat<extloadi16, LDR32HS, i32>;
1070  defm : LdrPat<load, LDR32W, i32>;
1071}
1072
1073multiclass StPat<PatFrag StoreOp, ValueType Type, ImmLeaf imm_type, Instruction Inst> {
1074  def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GPR:$rs1, 0)>;
1075  def : Pat<(StoreOp Type:$rs2, frameindex:$rs1), (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), 0)>;
1076  def : Pat<(StoreOp Type:$rs2, (add GPR:$rs1, imm_type:$uimm12)),
1077            (Inst Type:$rs2, GPR:$rs1, imm_type:$uimm12)>;
1078  def : Pat<(StoreOp Type:$rs2, (add frameindex:$rs1, imm_type:$uimm12)),
1079            (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm12)>;
1080  def : Pat<(StoreOp Type:$rs2, (eqToAdd frameindex:$rs1, imm_type:$uimm12)),
1081            (Inst Type:$rs2, (i32 (to_tframeindex tframeindex:$rs1)), imm_type:$uimm12)>;
1082}
1083
1084defm : StPat<truncstorei8, i32, uimm12, ST32B>;
1085defm : StPat<truncstorei16, i32, uimm12_1, ST32H>;
1086defm : StPat<store, i32, uimm12_2, ST32W>;
1087
1088multiclass StrPat<PatFrag StoreOp, ValueType Type, Instruction Inst> {
1089  def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, GPR:$rs2)), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 0)>;
1090  def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 1)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 1)>;
1091  def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 2)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 2)>;
1092  def : Pat<(StoreOp Type:$rz, (add GPR:$rs1, (shl GPR:$rs2, (i32 3)))), (Inst Type:$rz, GPR:$rs1, GPR:$rs2, 3)>;
1093}
1094
1095let Predicates = [iHas2E3] in {
1096  defm : StrPat<truncstorei8, i32, STR32B>;
1097  defm : StrPat<truncstorei16, i32, STR32H>;
1098  defm : StrPat<store, i32, STR32W>;
1099
1100  // Sext & Zext Patterns
1101  def : Pat<(sext_inreg GPR:$src, i1), (SEXT32 GPR:$src, 0, 0)>;
1102  def : Pat<(and GPR:$src, 255), (ZEXT32 GPR:$src, 7, 0)>;
1103  def : Pat<(and GPR:$src, 65535), (ZEXT32 GPR:$src, 15, 0)>;
1104
1105   // Call Patterns
1106  def : Pat<(CSKY_CALL tglobaladdr, tconstpool:$src2), (JSRI32 tconstpool:$src2)>;
1107  def : Pat<(CSKY_CALL texternalsym, tconstpool:$src2), (JSRI32 tconstpool:$src2)>;
1108  def : Pat<(CSKY_TAIL tglobaladdr, tconstpool:$src2), (JMPI32 tconstpool:$src2)>;
1109  def : Pat<(CSKY_TAIL texternalsym, tconstpool:$src2), (JMPI32 tconstpool:$src2)>;
1110
1111  def : Pat<(CSKY_CALLReg GPR:$src), (JSR32 GPR:$src)>;
1112  def : Pat<(CSKY_TAILReg GPR:$src), (JMP32 GPR:$src)>;
1113}
1114
1115// Symbol address Patterns
1116def : Pat<(CSKY_LOAD_ADDR tglobaladdr, tconstpool:$src2), (LRW32 tconstpool:$src2)>;
1117def : Pat<(CSKY_LOAD_ADDR tblockaddress, tconstpool:$src2), (LRW32 tconstpool:$src2)>;
1118def : Pat<(CSKY_LOAD_ADDR tjumptable:$src1, tconstpool:$src2), (LRW32_Gen tjumptable:$src1, tconstpool:$src2)>;
1119def : Pat<(CSKY_LOAD_ADDR texternalsym, tconstpool:$src2), (LRW32 tconstpool:$src2)>;
1120
1121let Predicates = [iHas2E3] in
1122  def : Pat<(i32 constpool:$src), (GRS32 (to_tconstpool tconstpool:$src))>;
1123
1124let Predicates = [iHasE2] in
1125  def : Pat<(i32 constpool:$src),
1126    (ORI32 (MOVIH32 (to_tconstpool_hi16 tconstpool:$src)),
1127           (to_tconstpool_lo16 tconstpool:$src))>;
1128
1129def : Pat<(i32 (load constpool:$src)), (LRW32 (to_tconstpool tconstpool:$src))>;
1130
1131// Branch Patterns.
1132let Predicates = [iHasE2] in {
1133  def : Pat<(brcond CARRY:$ca, bb:$imm16),
1134          (BT32 CARRY:$ca, bb:$imm16)>;
1135
1136  def : Pat<(brcond (i32 (setne GPR:$rs1, uimm16:$rs2)), bb:$imm16),
1137          (BT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), bb:$imm16)>;
1138  def : Pat<(brcond (i32 (seteq GPR:$rs1, uimm16:$rs2)), bb:$imm16),
1139          (BF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), bb:$imm16)>;
1140  def : Pat<(brcond (i32 (setuge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
1141          (BT32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
1142  def : Pat<(brcond (i32 (setult GPR:$rs1, oimm16:$rs2)), bb:$imm16),
1143          (BF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
1144  def : Pat<(brcond (i32 (setlt GPR:$rs1, oimm16:$rs2)), bb:$imm16),
1145          (BT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
1146  def : Pat<(brcond (i32 (setge GPR:$rs1, oimm16:$rs2)), bb:$imm16),
1147          (BF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), bb:$imm16)>;
1148
1149}
1150
1151let Predicates = [iHas2E3] in {
1152
1153def : Pat<(brcond (i32 (setne GPR:$rs1, GPR:$rs2)), bb:$imm16),
1154          (BT32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1155def : Pat<(brcond (i32 (seteq GPR:$rs1, GPR:$rs2)), bb:$imm16),
1156          (BF32 (CMPNE32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1157def : Pat<(brcond (i32 (setuge GPR:$rs1, GPR:$rs2)), bb:$imm16),
1158          (BT32 (CMPHS32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1159def : Pat<(brcond (i32 (setule GPR:$rs1, GPR:$rs2)), bb:$imm16),
1160          (BT32 (CMPHS32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
1161def : Pat<(brcond (i32 (setult GPR:$rs1, GPR:$rs2)), bb:$imm16),
1162          (BF32 (CMPHS32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1163def : Pat<(brcond (i32 (setugt GPR:$rs1, GPR:$rs2)), bb:$imm16),
1164          (BF32 (CMPHS32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
1165def : Pat<(brcond (i32 (setlt GPR:$rs1, GPR:$rs2)), bb:$imm16),
1166          (BT32 (CMPLT32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1167def : Pat<(brcond (i32 (setgt GPR:$rs1, GPR:$rs2)), bb:$imm16),
1168          (BT32 (CMPLT32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
1169def : Pat<(brcond (i32 (setge GPR:$rs1, GPR:$rs2)), bb:$imm16),
1170          (BF32 (CMPLT32 GPR:$rs1, GPR:$rs2), bb:$imm16)>;
1171def : Pat<(brcond (i32 (setle GPR:$rs1, GPR:$rs2)), bb:$imm16),
1172          (BF32 (CMPLT32 GPR:$rs2, GPR:$rs1), bb:$imm16)>;
1173
1174def : Pat<(brcond (i32 (seteq GPR:$rs1, (i32 0))), bb:$imm16),
1175          (BEZ32 GPR:$rs1, bb:$imm16)>;
1176def : Pat<(brcond (i32 (setne GPR:$rs1, (i32 0))), bb:$imm16),
1177          (BNEZ32 GPR:$rs1, bb:$imm16)>;
1178def : Pat<(brcond (i32 (setlt GPR:$rs1, (i32 0))), bb:$imm16),
1179          (BLZ32 GPR:$rs1, bb:$imm16)>;
1180def : Pat<(brcond (i32 (setge GPR:$rs1, (i32 0))), bb:$imm16),
1181          (BHSZ32 GPR:$rs1, bb:$imm16)>;
1182def : Pat<(brcond (i32 (setgt GPR:$rs1, (i32 0))), bb:$imm16),
1183          (BHZ32 GPR:$rs1, bb:$imm16)>;
1184def : Pat<(brcond (i32 (setle GPR:$rs1, (i32 0))), bb:$imm16),
1185          (BLSZ32 GPR:$rs1, bb:$imm16)>;
1186}
1187
1188// Compare Patterns.
1189let Predicates = [iHas2E3] in {
1190  def : Pat<(setne GPR:$rs1, GPR:$rs2),
1191            (CMPNE32 GPR:$rs1, GPR:$rs2)>;
1192  def : Pat<(i32 (seteq GPR:$rs1, GPR:$rs2)),
1193            (MVCV32 (CMPNE32 GPR:$rs1, GPR:$rs2))>;
1194  def : Pat<(setuge GPR:$rs1, GPR:$rs2),
1195            (CMPHS32 GPR:$rs1, GPR:$rs2)>;
1196  def : Pat<(setule GPR:$rs1, GPR:$rs2),
1197            (CMPHS32 GPR:$rs2, GPR:$rs1)>;
1198  def : Pat<(i32 (setult GPR:$rs1, GPR:$rs2)),
1199            (MVCV32 (CMPHS32 GPR:$rs1, GPR:$rs2))>;
1200  def : Pat<(i32 (setugt GPR:$rs1, GPR:$rs2)),
1201            (MVCV32 (CMPHS32 GPR:$rs2, GPR:$rs1))>;
1202  def : Pat<(setlt GPR:$rs1, GPR:$rs2),
1203            (CMPLT32 GPR:$rs1, GPR:$rs2)>;
1204  def : Pat<(setgt GPR:$rs1, GPR:$rs2),
1205            (CMPLT32 GPR:$rs2, GPR:$rs1)>;
1206  def : Pat<(i32 (setge GPR:$rs1, GPR:$rs2)),
1207            (MVCV32 (CMPLT32 GPR:$rs1, GPR:$rs2))>;
1208  def : Pat<(i32 (setle GPR:$rs1, GPR:$rs2)),
1209            (MVCV32 (CMPLT32 GPR:$rs2, GPR:$rs1))>;
1210}
1211
1212let Predicates = [iHasE2] in {
1213  def : Pat<(setne GPR:$rs1, uimm16:$rs2),
1214            (CMPNEI32 GPR:$rs1, uimm16:$rs2)>;
1215  let Predicates = [iHas2E3] in
1216  def : Pat<(i32 (seteq GPR:$rs1, uimm16:$rs2)),
1217            (MVCV32 (CMPNEI32 GPR:$rs1, uimm16:$rs2))>;
1218  def : Pat<(setuge GPR:$rs1, oimm16:$rs2),
1219            (CMPHSI32 GPR:$rs1, oimm16:$rs2)>;
1220  let Predicates = [iHas2E3] in
1221  def : Pat<(i32 (setult GPR:$rs1, oimm16:$rs2)),
1222            (MVCV32 (CMPHSI32 GPR:$rs1, oimm16:$rs2))>;
1223  def : Pat<(setlt GPR:$rs1, oimm16:$rs2),
1224            (CMPLTI32 GPR:$rs1, oimm16:$rs2)>;
1225  let Predicates = [iHas2E3] in
1226  def : Pat<(i32 (setge GPR:$rs1, oimm16:$rs2)),
1227            (MVCV32 (CMPLTI32 GPR:$rs1, oimm16:$rs2))>;
1228}
1229
1230// Select Patterns.
1231let Predicates = [iHasE2] in {
1232def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
1233          (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
1234def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
1235          (MOVT32 CARRY:$ca, GPR:$rx, GPR:$false)>;
1236
1237def : Pat<(select (i32 (setne GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1238          (MOVT32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1239def : Pat<(select (i32 (setne GPR:$rs1, uimm16:$rs2)), GPR:$rx, GPR:$false),
1240          (MOVT32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$rx, GPR:$false)>;
1241def : Pat<(select (i32 (seteq GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1242          (MOVF32 (CMPNE32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1243def : Pat<(select (i32 (seteq GPR:$rs1, uimm16:$rs2)), GPR:$rx, GPR:$false),
1244          (MOVF32 (CMPNEI32 GPR:$rs1, uimm16:$rs2), GPR:$rx, GPR:$false)>;
1245
1246def : Pat<(select (i32 (setuge GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1247          (MOVT32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1248def : Pat<(select (i32 (setuge GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
1249          (MOVT32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
1250def : Pat<(select (i32 (setule GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1251          (MOVT32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1252def : Pat<(select (i32 (setult GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1253          (MOVF32 (CMPHS32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1254def : Pat<(select (i32 (setult GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
1255          (MOVF32 (CMPHSI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
1256def : Pat<(select (i32 (setugt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1257          (MOVF32 (CMPHS32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1258
1259def : Pat<(select (i32 (setlt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1260          (MOVT32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1261def : Pat<(select (i32 (setlt GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
1262          (MOVT32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
1263def : Pat<(select (i32 (setgt GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1264          (MOVT32 (CMPLT32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1265def : Pat<(select (i32 (setge GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1266          (MOVF32 (CMPLT32 GPR:$rs1, GPR:$rs2), GPR:$rx, GPR:$false)>;
1267def : Pat<(select (i32 (setge GPR:$rs1, oimm16:$rs2)), GPR:$rx, GPR:$false),
1268          (MOVF32 (CMPLTI32 GPR:$rs1, oimm16:$rs2), GPR:$rx, GPR:$false)>;
1269def : Pat<(select (i32 (setle GPR:$rs1, GPR:$rs2)), GPR:$rx, GPR:$false),
1270          (MOVF32 (CMPLT32 GPR:$rs2, GPR:$rs1), GPR:$rx, GPR:$false)>;
1271
1272def : Pat<(select CARRY:$ca, GPR:$rx, GPR:$false),
1273          (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
1274def : Pat<(select (and CARRY:$ca, 1), GPR:$rx, GPR:$false),
1275          (ISEL32 CARRY:$ca, GPR:$rx, GPR:$false)>;
1276}
1277
1278// Constant materialize patterns.
1279let Predicates = [iHasE2] in
1280  def : Pat<(i32 imm:$imm),
1281            (ORI32 (MOVIH32 (uimm32_hi16 imm:$imm)), (uimm32_lo16 imm:$imm))>;
1282
1283
1284// Other operations.
1285let Predicates = [iHasE2] in {
1286  def : Pat<(rotl GPR:$rs1, GPR:$rs2),
1287            (ROTL32 GPR:$rs1, (ANDI32 GPR:$rs2, 0x1f))>;
1288  let Predicates = [iHas2E3] in {
1289    def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;
1290    def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;
1291  }
1292  def : Pat<(i32 (ctlz GPR:$rx)), (FF1 GPR:$rx)>;
1293}
1294
1295//===----------------------------------------------------------------------===//
1296// Pseudo for assembly
1297//===----------------------------------------------------------------------===//
1298
1299let isCall = 1, Defs = [ R15 ], mayLoad = 1, Size = 4, isCodeGenOnly = 0 in
1300def JBSR32 : CSKYPseudo<(outs), (ins call_symbol:$src1), "jbsr32\t$src1", []>;
1301
1302def JBR32 : CSKYPseudo<(outs), (ins br_symbol:$src1), "jbr32\t$src1", []> {
1303  let isBranch = 1;
1304  let isTerminator = 1;
1305  let isBarrier = 1;
1306  let isIndirectBranch = 1;
1307  let mayLoad = 1;
1308  let Size = 4;
1309}
1310
1311def JBT32 : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "jbt32\t$src1", []> {
1312  let isBranch = 1;
1313  let isTerminator = 1;
1314  let isIndirectBranch = 1;
1315  let mayLoad = 1;
1316  let Size = 4;
1317}
1318
1319def JBF32 : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "jbf32\t$src1", []> {
1320  let isBranch = 1;
1321  let isTerminator = 1;
1322  let isIndirectBranch = 1;
1323  let mayLoad = 1;
1324  let Size = 4;
1325}
1326
1327def JBT_E : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "!jbt_e\t$src1", []> {
1328  let isBranch = 1;
1329  let isTerminator = 1;
1330  let isIndirectBranch = 1;
1331  let mayLoad = 1;
1332  let Size = 6;
1333}
1334
1335def JBF_E : CSKYPseudo<(outs), (ins CARRY:$ca, br_symbol:$src1), "!jbf_e\t$src1", []> {
1336  let isBranch = 1;
1337  let isTerminator = 1;
1338  let isIndirectBranch = 1;
1339  let mayLoad = 1;
1340  let Size = 6;
1341}
1342
1343let mayLoad = 1, Size = 2, isCodeGenOnly = 0 in
1344def PseudoLRW32 : CSKYPseudo<(outs GPR:$rz), (ins bare_symbol:$src), "lrw32 $rz, $src", []>;
1345
1346
1347
1348
1349let mayLoad = 1, Size = 4, isCodeGenOnly = 0 in
1350def PseudoJSRI32 : CSKYPseudo<(outs), (ins call_symbol:$src), "jsri32 $src", []>;
1351
1352let mayLoad = 1, Size = 4, isCodeGenOnly = 0 in
1353def PseudoJMPI32 : CSKYPseudo<(outs), (ins br_symbol:$src), "jmpi32 $src", []>;
1354
1355let isNotDuplicable = 1, mayLoad = 1, mayStore = 0, Size = 8 in
1356def PseudoTLSLA32 : CSKYPseudo<(outs GPR:$dst1, GPR:$dst2),
1357  (ins constpool_symbol:$src, i32imm:$label), "!tlslrw32\t$dst1, $dst2, $src, $label", []>;
1358
1359let hasSideEffects = 0, isNotDuplicable = 1 in
1360def CONSTPOOL_ENTRY : CSKYPseudo<(outs),
1361  (ins i32imm:$instid, i32imm:$cpidx, i32imm:$size), "", []>;
1362
1363include "CSKYInstrInfo16Instr.td"
1364include "CSKYInstrInfoF1.td"
1365include "CSKYInstrInfoF2.td"
1366include "CSKYInstrAlias.td"
1367