xref: /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/CSKYInstrFormats16Instr.td (revision af23369a6deaaeb612ab266eb88b8bb8d560c322) 
1//===- CSKYInstrFormats16Instr.td - 16-bit Instr. Formats -*- tablegen --*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class J16<bits<5> sop, string opstr, dag ins>
10  : CSKY16Inst<AddrModeNone, (outs), ins,
11    !strconcat(opstr, "\t$offset"), []> {
12  bits<10> offset;
13  let Inst{15} = 0;
14  let Inst{14 - 10} = sop;
15  let Inst{9 - 0} = offset;
16}
17
18class J16_B<bits<5> sop, string opstr>
19  : CSKY16Inst<AddrModeNone, (outs), (ins CARRY:$ca, br_symbol_16bit:$offset),
20    !strconcat(opstr, "\t$offset"), []> {
21  bits<10> offset;
22  let Inst{15} = 0;
23  let Inst{14 - 10} = sop;
24  let Inst{9 - 0} = offset;
25}
26
27class R16_XYZ<bits<2> sop, string opstr, SDNode opnode> : CSKY16Inst<AddrModeNone,
28  (outs mGPR:$rz), (ins mGPR:$rx, mGPR:$ry), !strconcat(opstr, "\t$rz, $rx, $ry"),
29  [(set mGPR:$rz, (opnode mGPR:$rx, mGPR:$ry)) ]> {
30  bits<3> rz;
31  bits<3> rx;
32  bits<3> ry;
33  let Inst{15 - 11} = 0b01011;
34  let Inst{10 - 8} = rx;
35  let Inst{7 - 5} = rz;
36  let Inst{4 - 2} = ry;
37  let Inst{1, 0} = sop;
38}
39
40class R16_XZ_BINOP<bits<4> op, bits<2> sop, string opstr, PatFrag opnode> : CSKY16Inst<
41  AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
42  [(set sGPR:$rz, (opnode sGPR:$rZ, sGPR:$rx))]> {
43  bits<4> rz;
44  bits<4> rx;
45  let Inst{15, 14} = 0b01;
46  let Inst{13 - 10} = op;
47  let Inst{9 - 6} = rz;
48  let Inst{5 - 2} = rx;
49  let Inst{1, 0} = sop;
50  let Constraints = "$rz = $rZ";
51}
52
53class R16_XZ_BINOP_NOPat<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
54  AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
55  []> {
56  bits<4> rz;
57  bits<4> rx;
58  let Inst{15, 14} = 0b01;
59  let Inst{13 - 10} = op;
60  let Inst{9 - 6} = rz;
61  let Inst{5 - 2} = rx;
62  let Inst{1, 0} = sop;
63  let Constraints = "$rz = $rZ";
64}
65
66class R16_XZ_BINOP_C<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
67  AddrModeNone, (outs sGPR:$rz, CARRY:$cout),
68  (ins sGPR:$rZ, sGPR:$rx, CARRY:$cin), !strconcat(opstr, "\t$rz, $rx"), []> {
69  bits<4> rz;
70  bits<4> rx;
71  let Inst{15, 14} = 0b01;
72  let Inst{13 - 10} = op;
73  let Inst{9 - 6} = rz;
74  let Inst{5 - 2} = rx;
75  let Inst{1, 0} = sop;
76  let Constraints = "$rz = $rZ";
77}
78
79class R16_XZ_UNOP<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
80  AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
81  []> {
82  bits<4> rz;
83  bits<4> rx;
84  let Inst{15, 14} = 0b01;
85  let Inst{13 - 10} = op;
86  let Inst{9 - 6} = rz;
87  let Inst{5 - 2} = rx;
88  let Inst{1, 0} = sop;
89}
90
91class R16_Z_UNOP<bits<4> op, bits<2> sop, string opstr> : CSKY16Inst<
92  AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx), !strconcat(opstr, "\t$rz"),
93  []> {
94  bits<4> rz;
95  bits<4> rx;
96  let Inst{15, 14} = 0b01;
97  let Inst{13 - 10} = op;
98  let Inst{9 - 6} = rz;
99  let Inst{5 - 2} = rx;
100  let Inst{1, 0} = sop;
101  let Constraints = "$rz = $rx";
102}
103
104class R16_XY_CMP<bits<2> sop, string opstr> : CSKY16Inst<
105  AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry), !strconcat(opstr, "\t$rx, $ry"),
106  []> {
107  bits<4> ry;
108  bits<4> rx;
109  let Inst{15, 14} = 0b01;
110  let Inst{13 - 10} = 0b1001;
111  let Inst{9 - 6} = ry;
112  let Inst{5 - 2} = rx;
113  let Inst{1, 0} = sop;
114  let isCompare = 1;
115}
116
117class R16_X_J<bits<8> op_rz, bits<2> sop, string opstr> : CSKY16Inst<
118  AddrModeNone, (outs), (ins sGPR:$rx), !strconcat(opstr, "\t$rx"), []> {
119  bits<4> rx;
120  let Inst{15, 14} = 0b01;
121  let Inst{13 - 6} = op_rz;
122  let Inst{5 - 2} = rx;
123  let Inst{1, 0} = sop;
124}
125
126class I16_Z_8<bits<3> op, dag ins, string asmstr>
127  : CSKY16Inst<AddrModeNone, (outs mGPR:$rz), ins, asmstr, []> {
128  bits<3> rz;
129  bits<8> imm8;
130  let Inst{15, 14} = 0b00;
131  let Inst{13 - 11} = op;
132  let Inst{10 - 8} = rz;
133  let Inst{7 - 0} = imm8;
134}
135
136class I16_Z_5<bits<3> sop, dag outs, dag ins,string opstr>
137  : CSKY16Inst<AddrModeNone, outs, ins,
138  !strconcat(opstr, "\t$rz, $imm5"), []> {
139  bits<3> rz;
140  bits<5> imm5;
141  let Inst{15, 14} = 0b00;
142  let Inst{13 - 11} = 0b111;
143  let Inst{10 - 8} = rz;
144  let Inst{7 - 5} = sop;
145  let Inst{4 - 0} = imm5;
146}
147
148class I16_X_CMP<bits<3> sop, string opstr, Operand Immoperand> : CSKY16Inst<
149  AddrModeNone, (outs CARRY:$ca), (ins mGPR:$rx, Immoperand:$imm5),
150  !strconcat(opstr, "\t$rx, $imm5"), []> {
151  bits<3> rx;
152  bits<5> imm5;
153  let Inst{15, 14} = 0b00;
154  let Inst{13 - 11} = 0b111;
155  let Inst{10 - 8} = rx;
156  let Inst{7 - 5} = sop;
157  let Inst{4 - 0} = imm5;
158  let isCompare = 1;
159}
160
161class I16_SP_IMM7<bits<3> sop, string opstr> : CSKY16Inst<
162  AddrModeNone, (outs GPRSP:$sp2), (ins GPRSP:$sp1, uimm7_2:$imm7),
163  !strconcat(opstr, "\t$sp2, $sp1, $imm7"), []> {
164  bits<7> imm7;
165  let Inst{15, 14} = 0b00;
166  let Inst{13 - 10} = 0b0101;
167  let Inst{9, 8} = imm7{6,5};
168  let Inst{7 - 5} = sop;
169  let Inst{4 - 0} = imm7{4 - 0};
170}
171
172class I16_XZ_IMM5<bits<3> sop, string opstr, SDNode opnode> : CSKY16Inst<
173  AddrModeNone, (outs mGPR:$rz), (ins mGPR:$rx, uimm5:$imm5),
174  !strconcat(opstr, "\t$rz, $rx, $imm5"), [(set mGPR:$rz, (opnode mGPR:$rx, uimm5:$imm5))]> {
175  bits<3> rx;
176  bits<3> rz;
177  bits<5> imm5;
178  let Inst{15, 14} = 0b01;
179  let Inst{13 - 11} = sop;
180  let Inst{10 - 8} = rx;
181  let Inst{7 - 5} = rz;
182  let Inst{4 - 0} = imm5;
183}
184
185class I16_XZ_LDST<AddrMode am, bits<3> sop, string opstr, dag outs, dag ins>
186  : CSKY16Inst<am, outs, ins, !strconcat(opstr, "\t$rz, ($rx, ${imm})"),
187  []> {
188  bits<3> rx;
189  bits<3> rz;
190  bits<5> imm;
191  let Inst{15, 14} = 0b10;
192  let Inst{13 - 11} = sop;
193  let Inst{10 - 8} = rx;
194  let Inst{7 - 5} = rz;
195  let Inst{4 - 0} = imm;
196}
197
198class I16_ZSP_LDST<AddrMode am, bits<3> sop, string opstr, dag outs, dag ins> : CSKY16Inst<
199  am,  outs, ins, !strconcat(opstr, "\t$rz, ($sp, ${addr})"),
200  []> {
201  bits<3> rz;
202  bits<8> addr;
203  let Inst{15, 14} = 0b10;
204  let Inst{13 - 11} = sop;
205  let Inst{10 - 8} = addr{7 - 5};
206  let Inst{7 - 5} = rz;
207  let Inst{4 - 0} = addr{4 - 0};
208}
209
210class I16_XZ_IMM3<bits<2> sop, string opstr, SDNode opnode> : CSKY16Inst<
211  AddrModeNone, (outs mGPR:$rz), (ins mGPR:$rx, oimm3:$oimm3),
212  !strconcat(opstr, "\t$rz, $rx, $oimm3"), [(set mGPR:$rz, (opnode mGPR:$rx, oimm3:$oimm3))]> {
213  bits<3> rx;
214  bits<3> rz;
215  bits<3> oimm3;
216  let Inst{15, 14} = 0b01;
217  let Inst{13 - 11} = 0b011;
218  let Inst{10 - 8} = rx;
219  let Inst{7 - 5} = rz;
220  let Inst{4 - 2} = oimm3;
221  let Inst{1, 0} = sop;
222}
223
224class I16_BPushPop<bits<11> op, bits<2> uop, dag out, dag ins, string opstr> :
225  CSKY16Inst<AddrModeNone, out, ins, opstr, []>{
226  bits<3> rz;
227  let Inst{15- 5} = op;
228  let Inst{4 -2} = rz;
229  let Inst{1,0} = uop;
230  let Predicates = [HasJAVA];
231  let hasSideEffects = 1;
232}
233