xref: /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/CSKYInstrFormats.td (revision 963f5dc7a30624e95d72fb7f87b8892651164e46) 
1//===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class AddrMode<bits<5> val> {
10  bits<5> Value = val;
11}
12
13def AddrModeNone : AddrMode<0>;
14def AddrMode32B : AddrMode<1>;   // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
15def AddrMode32H : AddrMode<2>;   // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
16def AddrMode32WD : AddrMode<3>;  // ld32.w, st32.w, ld32.d, st32.d, +16kb
17def AddrMode16B : AddrMode<4>;   // ld16.b, +32b
18def AddrMode16H : AddrMode<5>;   // ld16.h, +64b
19def AddrMode16W : AddrMode<6>;   // ld16.w, +128b or +1kb
20def AddrMode32SDF : AddrMode<7>; // flds, fldd, +1kb
21
22class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
23               list<dag> pattern> : Instruction {
24  let Namespace = "CSKY";
25  int Size = sz;
26  AddrMode AM = am;
27
28  let OutOperandList = outs;
29  let InOperandList = ins;
30  let AsmString = asmstr;
31  let Pattern = pattern;
32  let Itinerary = NoItinerary;
33  let TSFlags{4 - 0} = AM.Value;
34}
35
36class CSKYPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
37    : CSKYInst<AddrModeNone, 0, outs, ins, asmstr, pattern> {
38  let isCodeGenOnly = 1;
39  let isPseudo = 1;
40}
41
42class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
43                 list<dag> pattern>
44    : CSKYInst<am, 4, outs, ins, asmstr, pattern> {
45  field bits<32> Inst;
46  let Inst{31 - 26} = opcode;
47}
48
49// CSKY 32-bit instruction
50// Format< OP[6] | Offset[26] >
51// Instruction(1): bsr32
52class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
53    : CSKY32Inst<AddrModeNone, opcode, outs, ins, !strconcat(op, "\t$offset"),
54                 pattern> {
55  bits<26> offset;
56  let Inst{25 - 0} = offset;
57  let isCall = 1;
58  let Defs = [ R15 ];
59}
60
61// Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
62// Instructions(7): grs, lrs32.b, lrs32.h, lrs32.w, srs32.b, srs32.h, srs32.w
63class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
64    : CSKY32Inst<AddrModeNone, 0x33, outs, ins, asm, pattern> {
65  bits<5> rz;
66  bits<18> offset;
67  let Inst{25 - 21} = rz;
68  let Inst{20 - 18} = sop;
69  let Inst{17 - 0} = offset;
70}
71
72// Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
73// Instructions(1): ori32
74class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
75    : CSKY32Inst<AddrModeNone, 0x3b,
76                 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
77                 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
78  bits<5> rz;
79  bits<5> rx;
80  bits<16> imm16;
81  let Inst{25 - 21} = rz;
82  let Inst{20 - 16} = rx;
83  let Inst{15 - 0} = imm16;
84}
85
86// Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
87// Instructions(3): movi32, movih32, (bgeni32)
88class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
89    : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
90                 !strconcat(op, "\t$rz, $imm16"),
91                 [(set GPR:$rz, ImmType:$imm16)]> {
92  bits<5> rz;
93  bits<16> imm16;
94  let Inst{25 - 21} = sop;
95  let Inst{20 - 16} = rz;
96  let Inst{15 - 0} = imm16;
97  let isReMaterializable = 1;
98  let isAsCheapAsAMove = 1;
99  let isMoveImm = 1;
100}
101
102// Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
103// Instructions(1): lrw32
104class I_16_Z_L<bits<5> sop, string op, dag ins, list<dag> pattern>
105  : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
106  !strconcat(op, "\t$rz, $imm16"), pattern> {
107  bits<5> rz;
108  bits<16> imm16;
109  let Inst{25 - 21} = sop;
110  let Inst{20 - 16} = rz;
111  let Inst{15 - 0} = imm16;
112}
113
114// Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
115// Instructions(5): bt32, bf32, br32, jmpi32, jsri32
116class I_16_L<bits<5> sop, dag outs, dag ins, string asm, list<dag> pattern>
117    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, asm, pattern> {
118  bits<16> imm16;
119  let Inst{25 - 21} = sop;
120  let Inst{20 - 16} = 0;
121  let Inst{15 - 0} = imm16;
122}
123
124// Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
125// Instructions(2): jmp32, jsr32
126class I_16_JX<bits<5> sop, string op, list<dag> pattern>
127    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
128                 !strconcat(op, "\t$rx"), pattern> {
129  bits<5> rx;
130  bits<16> imm16;
131  let Inst{25 - 21} = sop;
132  let Inst{20 - 16} = rx;
133  let Inst{15 - 0} = 0;
134}
135
136// Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
137// Instructions(1): jmpix32
138class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
139    : CSKY32Inst<AddrModeNone, 0x3a, (outs),
140                 (ins GPR:$rx, operand:$imm2),
141                 !strconcat(op, "\t$rx, $imm2"), pattern> {
142  bits<5> rx;
143  bits<2> imm2;
144  let Inst{25 - 21} = sop;
145  let Inst{20 - 16} = rx;
146  let Inst{15 - 2} = 0;
147  let Inst{1 - 0} = imm2;
148}
149
150// Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
151// Instructions(1): rts32
152class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
153    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins), op, pattern> {
154  let Inst{25 - 21} = sop;
155  let Inst{20 - 16} = pcode;
156  let Inst{15 - 0} = 0;
157  let isTerminator = 1;
158  let isReturn = 1;
159  let isBarrier = 1;
160}
161
162// Instructions(1): rte32
163class I_16_RET_I<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
164    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), op, pattern> {
165  let Inst{25 - 21} = sop;
166  let Inst{20 - 16} = pcode;
167  let Inst{15 - 10} = 0x10;
168  let Inst{9 - 5} = 1;
169  let Inst{4 - 0} = 0;
170  let isTerminator = 1;
171  let isReturn = 1;
172  let isBarrier = 1;
173}
174
175// Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
176// Instructions(3): cmpnei32, cmphsi32, cmplti32
177class I_16_X<bits<5> sop, string op, Operand operand>
178    : CSKY32Inst<AddrModeNone, 0x3a, (outs CARRY:$ca),
179    (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
180  bits<16> imm16;
181  bits<5> rx;
182  let Inst{25 - 21} = sop;
183  let Inst{20 - 16} = rx;
184  let Inst{15 - 0} = imm16;
185  let isCompare = 1;
186}
187
188// Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
189// Instructions(7): bez32, bnez32, bnezad32, bhz32, blsz32, blz32, bhsz32
190class I_16_X_L<bits<5> sop, string op, Operand operand>
191    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
192                 !strconcat(op, "\t$rx, $imm16"), []> {
193  bits<5> rx;
194  bits<16> imm16;
195  let Inst{25 - 21} = sop;
196  let Inst{20 - 16} = rx;
197  let Inst{15 - 0} = imm16;
198  let isBranch = 1;
199  let isTerminator = 1;
200}
201
202// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
203// Instructions(5): addi32, subi32, andi32, andni32, xori32
204class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
205    : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
206    (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
207    [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
208  bits<5> rz;
209  bits<5> rx;
210  bits<12> imm12;
211  let Inst{25 - 21} = rz;
212  let Inst{20 - 16} = rx;
213  let Inst{15 - 12} = sop;
214  let Inst{11 - 0} = imm12;
215}
216
217class I_LDST<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
218             string op, list<dag> pattern>
219    : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, ${imm12})"),
220                 pattern> {
221  bits<5> rx;
222  bits<5> rz;
223  bits<12> imm12;
224  let Inst{25 - 21} = rz;
225  let Inst{20 - 16} = rx;
226  let Inst{15 - 12} = sop;
227  let Inst{11 - 0} = imm12;
228}
229
230// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
231// Instructions(6): ld32.b, ld32.bs, ld32.h, ld32.hs, ld32.w, ld32.d
232class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
233    : I_LDST<am, 0x36, sop,
234    (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
235
236// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
237// Instructions(4): st32.b, st32.h, st32.w, st32.d
238class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
239    : I_LDST<am, 0x37, sop, (outs),
240    (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
241
242// Format< OP[6] | SOP[5] | PCODE[5] | 0000[4] | 000 | R28 | LIST2[3] | R15 |
243// LIST1[4] >
244// Instructions(2): push32, pop32
245class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
246    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$regs"), []> {
247  bits<12> regs;
248  let Inst{25 - 21} = sop;
249  let Inst{20 - 16} = pcode;
250  let Inst{15 - 12} = 0;
251  let Inst{11 - 0} = regs;
252}
253
254// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
255// Instructions(4): incf32, inct32, decf32, dect32
256class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
257             list<dag> pattern>
258    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
259    (ins GPR:$false, GPR:$rx, ImmType:$imm5),
260    !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
261  bits<5> rz;
262  bits<5> rx;
263  bits<5> imm5;
264  let Inst{25 - 21} = rz;
265  let Inst{20 - 16} = rx;
266  let Inst{15 - 10} = sop;
267  let Inst{9 - 5} = pcode;
268  let Inst{4 - 0} = imm5;
269  let Constraints = "$rz = $false";
270}
271
272// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
273// Instructions(13): decgt32, declt32, decne32, lsli32, lslc32, lsri32
274//                   lsrc32, asri32, asrc32, rotli32, xsr32, bclri32, bseti32
275class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag ins, dag outs,
276             list<dag> pattern>
277    : CSKY32Inst<AddrModeNone, 0x31, ins, outs,
278                 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
279  bits<5> imm5;
280  bits<5> rx;
281  bits<5> rz;
282  let Inst{25 - 21} = imm5;
283  let Inst{20 - 16} = rx;
284  let Inst{15 - 10} = sop;
285  let Inst{9 - 5} = pcode;
286  let Inst{4 - 0} = rz;
287}
288
289// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
290// Instructions(2): ldm32, (ldq32), stm32, (stq32)
291class I_5_YX<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern,
292             bits<5> imm5>
293    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
294                 op #"\t${ry}, (${rx}), " #!cast<int>(imm5), pattern> {
295  bits<5> rx;
296  bits<5> ry;
297  let Inst{25 - 21} = ry; // ry
298  let Inst{20 - 16} = rx;
299  let Inst{15 - 10} = 0b000111;
300  let Inst{9 - 5} = 0b00001;
301  let Inst{4 - 0} = imm5{4 - 0}; // imm5
302}
303
304// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
305// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
306class I_5_XZ_U<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
307    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
308                 pattern> {
309  bits<5> rx;
310  bits<5> rz;
311  bits<5> msb;
312  bits<5> lsb;
313  let Inst{25 - 21} = lsb; // lsb
314  let Inst{20 - 16} = rx;
315  let Inst{15 - 10} = sop;
316  let Inst{9 - 5} = msb; // msb
317  let Inst{4 - 0} = rz;
318}
319
320// sextb, sexth
321class I_5_XZ_US<bits<6> sop, string op, SDNode opnode,
322  ValueType type> : I_5_XZ_U<sop, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), op,
323    [(set GPR:$rz, (opnode GPR:$rx, type))]>;
324
325class I_5_XZ_UZ<bits<6> sop, string op, int v>
326    : I_5_XZ_U<sop, (outs GPR:$rz), (ins GPR:$rx, uimm5:$msb, uimm5:$lsb), op,
327    [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
328
329// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]>
330// Instructions(1): ins32
331class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
332    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins operand:$size_lsb),
333                 !strconcat(op, "\t$rz, operand:$size_lsb"), pattern> {
334  bits<10> size_lsb;
335  bits<5> rz;
336  bits<5> rx;
337  let Inst{25 - 21} = rz;
338  let Inst{20 - 16} = rx;
339  let Inst{15 - 10} = sop;
340  let Inst{9 - 5} = size_lsb{9 - 5}; // size
341  let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
342}
343
344// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
345// Instructions(1): btsti32
346class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
347            list<dag> pattern>
348    : CSKY32Inst<AddrModeNone, 0x31,
349    (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
350    !strconcat(op, "\t$rx, $imm5"), pattern> {
351  bits<5> imm5;
352  bits<5> rx;
353  let Inst{25 - 21} = imm5;
354  let Inst{20 - 16} = rx;
355  let Inst{15 - 10} = sop;
356  let Inst{9 - 5} = pcode;
357  let Inst{4 - 0} = 0;
358  let isCompare = 1;
359}
360
361// Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
362// Instructions(1): bmaski32
363class I_5_Z<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
364            list<dag> pattern>
365    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins ImmType:$imm5),
366                 !strconcat(op, "\t$rz, $imm5"), pattern> {
367  bits<5> imm5;
368  bits<5> rz;
369  let Inst{25 - 21} = imm5;
370  let Inst{20 - 16} = 0;
371  let Inst{15 - 10} = sop;
372  let Inst{9 - 5} = pcode;
373  let Inst{4 - 0} = rz;
374}
375
376// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
377// Instructions(24): addu32, addc32, subu32, subc32, (rsub32), ixh32, ixw32,
378// ixd32, and32, andn32, or32, xor32, nor32, lsl32, lsr32, asr32, rotl32
379// mult32, divu32, divs32, mul.(u/s)32, mula.32.l, mula.u32, mulall.s16.s
380class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
381            string op, list<dag> pattern>
382    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
383                 !strconcat(op, "\t$rz, $rx, $ry"), pattern> {
384  bits<5> ry;
385  bits<5> rx;
386  bits<5> rz;
387  let Inst{25 - 21} = ry;
388  let Inst{20 - 16} = rx;
389  let Inst{15 - 10} = sop;
390  let Inst{9 - 5} = pcode;
391  let Inst{4 - 0} = rz;
392}
393
394// R_YXZ instructions with simple pattern
395// Output: GPR:rz
396// Input: GPR:rx, GPR:ry
397// Asm string: op rz, rx, ry
398// Instructions: addu32, subu32, ixh32, ixw32, ixd32, and32, andn32, or32,
399// xor32, nor32, lsl32, lsr32, asr32, mult32, divu32, divs32
400class R_YXZ_SP_F1<bits<6> sop, bits<5> pcode, PatFrag opnode, string op,
401  bit Commutable = 0> : R_YXZ<0x31, sop, pcode, (outs GPR:$rz),
402  (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
403  let isCommutable = Commutable;
404}
405
406// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
407// Instructions:(8) ldr32.b, ldr32.h, ldr32.bs, ldr32.hs, ldr32.w,
408//                  str32.b, str32.h, str32.w
409class R_YXZ_LDST<bits<6> opcode, bits<6> sop, dag outs,
410                 dag ins, string op, list<dag> pattern>
411    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
412                 op # "\t$rz, ($rx, $ry << ${imm})", pattern> {
413  bits<5> rx;
414  bits<5> ry;
415  bits<5> rz;
416  bits<5> imm;
417  let Inst{25 - 21} = ry; // ry;
418  let Inst{20 - 16} = rx; // rx;
419  let Inst{15 - 10} = sop;
420  let Inst{9 - 5} = imm;  // pcode;
421  let Inst{4 - 0} = rz;
422}
423
424class I_LDR<bits<6> sop, string op> : R_YXZ_LDST<0x34, sop,
425  (outs GPR:$rz), (ins GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
426
427class I_STR<bits<6> sop, string op> : R_YXZ_LDST<0x35, sop,
428  (outs), (ins GPR:$rz, GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
429
430// Format< OP[6] | RX[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
431// Instructions:(1) not32
432class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
433            list<dag> pattern>
434    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"),
435                 pattern> {
436  bits<5> rx;
437  bits<5> rz;
438  let Inst{25 - 21} = rx;
439  let Inst{20 - 16} = rx;
440  let Inst{15 - 10} = sop;
441  let Inst{9 - 5} = pcode;
442  let Inst{4 - 0} = rz;
443}
444
445// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
446// Instructions:(4) cmpne32, cmphs32, cmplt32, tst32
447class R_YX<bits<6> sop, bits<5> pcode, string op>
448    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
449                 (ins GPR:$rx, GPR:$ry),
450                 !strconcat(op, "\t$rx, $ry"), []> {
451  bits<5> ry;
452  bits<5> rx;
453  let Inst{25 - 21} = ry;
454  let Inst{20 - 16} = rx;
455  let Inst{15 - 10} = sop;
456  let Inst{9 - 5} = pcode;
457  let Inst{4 - 0} = 0;
458  let isCompare = 1;
459}
460
461// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
462// Instructions:(12)
463//   mov32, xtrb0.32, xtrb1.32, xtrb2.32, xtrb3.32, brev32, revb32
464//   revh32, abs32, ff0.32, ff1.32, bgenr32
465class R_XZ<bits<6> sop, bits<5> pcode, string op>
466    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins GPR:$rx),
467                 !strconcat(op, "\t$rz, $rx"), []> {
468  bits<5> rx;
469  bits<5> rz;
470  let Inst{25 - 21} = 0;
471  let Inst{20 - 16} = rx;
472  let Inst{15 - 10} = sop;
473  let Inst{9 - 5} = pcode;
474  let Inst{4 - 0} = rz;
475}
476
477// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
478// Instructions:(2) movf32, movt32
479class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
480    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
481                 (ins CARRY:$ca, GPR:$rx, GPR:$false),
482                 !strconcat(op, "\t$rz, $rx"), pattern> {
483  bits<5> rz;
484  bits<5> rx;
485  let Inst{25 - 21} = rz;
486  let Inst{20 - 16} = rx;
487  let Inst{15 - 10} = sop;
488  let Inst{9 - 5} = pcode;
489  let Inst{4 - 0} = 0;
490  let Constraints = "$rz = $false";
491  let isSelect = 1;
492}
493
494// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
495// Instructions:(1) tstnbz32
496class R_X<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
497    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),(ins GPR:$rx),
498                 !strconcat(op, "\t$rx"), pattern> {
499  bits<5> rx;
500  let Inst{25 - 21} = 0;
501  let Inst{20 - 16} = rx;
502  let Inst{15 - 10} = sop;
503  let Inst{9 - 5} = pcode;
504  let Inst{4 - 0} = 0;
505}
506
507// Format< OP[6] | 00000[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5] >
508// Instructions:(2) mvc32, mvcv32
509class R_Z_1<bits<6> sop, bits<5> pcode, string op>
510    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
511                 (ins CARRY:$ca), !strconcat(op, "\t$rz"), []> {
512  bits<5> rz;
513  let Inst{25 - 21} = 0;
514  let Inst{20 - 16} = 0;
515  let Inst{15 - 10} = sop;
516  let Inst{9 - 5} = pcode;
517  let Inst{4 - 0} = rz;
518}
519
520// Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
521// Instructions:(2) clrf32, clrt32
522class R_Z_2<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
523    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
524    (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
525  bits<5> rz;
526  let Inst{25 - 21} = rz;
527  let Inst{20 - 16} = 0;
528  let Inst{15 - 10} = sop;
529  let Inst{9 - 5} = pcode;
530  let Inst{4 - 0} = 0;
531  let Constraints = "$rz = $false";
532}
533