xref: /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/CSKYInstrFormats.td (revision 06c3fb2749bda94cb5201f81ffdb8fa6c3161b2e) 
1//===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class AddrMode<bits<5> val> {
10  bits<5> Value = val;
11}
12
13def AddrModeNone : AddrMode<0>;
14def AddrMode32B : AddrMode<1>;   // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
15def AddrMode32H : AddrMode<2>;   // ld32.h, ld32.hs, st32.h, st32.hs, +8kb
16def AddrMode32WD : AddrMode<3>;  // ld32.w, st32.w, ld32.d, st32.d, +16kb
17def AddrMode16B : AddrMode<4>;   // ld16.b, +32b
18def AddrMode16H : AddrMode<5>;   // ld16.h, +64b
19def AddrMode16W : AddrMode<6>;   // ld16.w, +128b or +1kb
20def AddrMode32SDF : AddrMode<7>; // flds, fldd, +1kb
21
22class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
23               list<dag> pattern> : Instruction {
24  let Namespace = "CSKY";
25  int Size = sz;
26  AddrMode AM = am;
27  field bits<32> SoftFail = 0;
28  let OutOperandList = outs;
29  let InOperandList = ins;
30  let AsmString = asmstr;
31  let Pattern = pattern;
32  let Itinerary = NoItinerary;
33  let TSFlags{4 - 0} = AM.Value;
34}
35
36class CSKYPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
37    : CSKYInst<AddrModeNone, 0, outs, ins, asmstr, pattern> {
38  let isCodeGenOnly = 1;
39  let isPseudo = 1;
40}
41
42class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
43                 list<dag> pattern>
44    : CSKYInst<am, 4, outs, ins, asmstr, pattern> {
45  field bits<32> Inst;
46  let Inst{31 - 26} = opcode;
47}
48
49class CSKY16Inst<AddrMode am, dag outs, dag ins, string asmstr, list<dag> pattern>
50  : CSKYInst<am, 2, outs, ins, asmstr, pattern> {
51  field bits<16> Inst;
52}
53
54// CSKY 32-bit instruction
55// Format< OP[6] | Offset[26] >
56// Instruction(1): bsr32
57class J<bits<6> opcode, dag outs, dag ins, string op, list<dag> pattern>
58    : CSKY32Inst<AddrModeNone, opcode, outs, ins, !strconcat(op, "\t$offset"),
59                 pattern> {
60  bits<26> offset;
61  let Inst{25 - 0} = offset;
62  let isCall = 1;
63  let Defs = [ R15 ];
64}
65
66// Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
67// Instructions(7): grs, lrs32.b, lrs32.h, lrs32.w, srs32.b, srs32.h, srs32.w
68class I_18_Z_L<bits<3> sop, string asm, dag outs, dag ins, list<dag> pattern>
69    : CSKY32Inst<AddrModeNone, 0x33, outs, ins, asm, pattern> {
70  bits<5> rz;
71  bits<18> offset;
72  let Inst{25 - 21} = rz;
73  let Inst{20 - 18} = sop;
74  let Inst{17 - 0} = offset;
75}
76
77// Format< OP[6] | RZ[5] | RX[5] | IMM[16] >
78// Instructions(1): ori32
79class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
80    : CSKY32Inst<AddrModeNone, 0x3b,
81                 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
82                 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
83  bits<5> rz;
84  bits<5> rx;
85  bits<16> imm16;
86  let Inst{25 - 21} = rz;
87  let Inst{20 - 16} = rx;
88  let Inst{15 - 0} = imm16;
89}
90
91// Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
92// Instructions(3): movi32, movih32, (bgeni32)
93class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
94    : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
95                 !strconcat(op, "\t$rz, $imm16"),
96                 [(set GPR:$rz, ImmType:$imm16)]> {
97  bits<5> rz;
98  bits<16> imm16;
99  let Inst{25 - 21} = sop;
100  let Inst{20 - 16} = rz;
101  let Inst{15 - 0} = imm16;
102  let isReMaterializable = 1;
103  let isAsCheapAsAMove = 1;
104  let isMoveImm = 1;
105}
106
107// Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
108// Instructions(1): lrw32
109class I_16_Z_L<bits<5> sop, string op, dag ins, list<dag> pattern>
110  : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), ins,
111  !strconcat(op, "\t$rz, $imm16"), pattern> {
112  bits<5> rz;
113  bits<16> imm16;
114  let Inst{25 - 21} = sop;
115  let Inst{20 - 16} = rz;
116  let Inst{15 - 0} = imm16;
117}
118
119// Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
120// Instructions(5): bt32, bf32, br32, jmpi32, jsri32
121class I_16_L<bits<5> sop, dag outs, dag ins, string asm, list<dag> pattern>
122    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, asm, pattern> {
123  bits<16> imm16;
124  let Inst{25 - 21} = sop;
125  let Inst{20 - 16} = 0;
126  let Inst{15 - 0} = imm16;
127}
128
129// Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
130// Instructions(2): jmp32, jsr32
131class I_16_JX<bits<5> sop, string op, list<dag> pattern>
132    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
133                 !strconcat(op, "\t$rx"), pattern> {
134  bits<5> rx;
135  bits<16> imm16;
136  let Inst{25 - 21} = sop;
137  let Inst{20 - 16} = rx;
138  let Inst{15 - 0} = 0;
139}
140
141// Format< OP[6] | SOP[5] | RX[5] | 00000000000000[14] | IMM[2] >
142// Instructions(1): jmpix32
143class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
144    : CSKY32Inst<AddrModeNone, 0x3a, (outs),
145                 (ins GPR:$rx, operand:$imm2),
146                 !strconcat(op, "\t$rx, $imm2"), pattern> {
147  bits<5> rx;
148  bits<2> imm2;
149  let Inst{25 - 21} = sop;
150  let Inst{20 - 16} = rx;
151  let Inst{15 - 2} = 0;
152  let Inst{1 - 0} = imm2;
153}
154
155// Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
156// Instructions(1): rts32
157class I_16_RET<bits<5> sop, bits<5> pcode, string op, list<dag> pattern>
158    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins), op, pattern> {
159  let Inst{25 - 21} = sop;
160  let Inst{20 - 16} = pcode;
161  let Inst{15 - 0} = 0;
162  let isTerminator = 1;
163  let isReturn = 1;
164  let isBarrier = 1;
165  let Uses = [ R15 ];
166}
167
168// Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
169// Instructions(3): cmpnei32, cmphsi32, cmplti32
170class I_16_X<bits<5> sop, string op, Operand operand>
171    : CSKY32Inst<AddrModeNone, 0x3a, (outs CARRY:$ca),
172    (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
173  bits<16> imm16;
174  bits<5> rx;
175  let Inst{25 - 21} = sop;
176  let Inst{20 - 16} = rx;
177  let Inst{15 - 0} = imm16;
178  let isCompare = 1;
179}
180
181// Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
182// Instructions(7): bez32, bnez32, bnezad32, bhz32, blsz32, blz32, bhsz32
183class I_16_X_L<bits<5> sop, string op, Operand operand>
184    : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
185                 !strconcat(op, "\t$rx, $imm16"), []> {
186  bits<5> rx;
187  bits<16> imm16;
188  let Inst{25 - 21} = sop;
189  let Inst{20 - 16} = rx;
190  let Inst{15 - 0} = imm16;
191  let isBranch = 1;
192  let isTerminator = 1;
193}
194
195// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
196// Instructions(5): addi32, subi32, andi32, andni32, xori32
197class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
198    : CSKY32Inst<AddrModeNone, 0x39, (outs GPR:$rz),
199    (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
200    [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
201  bits<5> rz;
202  bits<5> rx;
203  bits<12> imm12;
204  let Inst{25 - 21} = rz;
205  let Inst{20 - 16} = rx;
206  let Inst{15 - 12} = sop;
207  let Inst{11 - 0} = imm12;
208}
209
210class I_LDST<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
211             string op, list<dag> pattern>
212    : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, ${imm12})"),
213                 pattern> {
214  bits<5> rx;
215  bits<5> rz;
216  bits<12> imm12;
217  let Inst{25 - 21} = rz;
218  let Inst{20 - 16} = rx;
219  let Inst{15 - 12} = sop;
220  let Inst{11 - 0} = imm12;
221}
222
223class I_PLDR<AddrMode am, bits<6> opcode, bits<4> sop, dag outs, dag ins,
224             string op, list<dag> pattern>
225    : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t($rx, ${imm12})"),
226                 pattern> {
227  bits<5> rx;
228  bits<12> imm12;
229  let Inst{25 - 21} = 0;
230  let Inst{20 - 16} = rx;
231  let Inst{15 - 12} = sop;
232  let Inst{11 - 0} = imm12;
233}
234
235
236// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
237// Instructions(6): ld32.b, ld32.bs, ld32.h, ld32.hs, ld32.w
238class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
239    : I_LDST<am, 0x36, sop,
240    (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
241
242// Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
243// Instructions(4): st32.b, st32.h, st32.w
244class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
245    : I_LDST<am, 0x37, sop, (outs),
246    (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
247
248// Format< OP[6] | SOP[5] | PCODE[5] | 0000[4] | 000 | R28 | LIST2[3] | R15 |
249// LIST1[4] >
250// Instructions(2): push32, pop32
251class I_12_PP<bits<5> sop, bits<5> pcode, dag outs, dag ins, string op>
252    : CSKY32Inst<AddrModeNone, 0x3a, outs, ins, !strconcat(op, "\t$regs"), []> {
253  bits<12> regs;
254  let Inst{25 - 21} = sop;
255  let Inst{20 - 16} = pcode;
256  let Inst{15 - 12} = 0;
257  let Inst{11 - 0} = regs;
258  let Uses = [R14];
259  let Defs = [R14];
260}
261
262// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
263// Instructions(4): incf32, inct32, decf32, dect32
264class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
265             list<dag> pattern>
266    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
267    (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
268    !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
269  bits<5> rz;
270  bits<5> rx;
271  bits<5> imm5;
272  let Inst{25 - 21} = rz;
273  let Inst{20 - 16} = rx;
274  let Inst{15 - 10} = sop;
275  let Inst{9 - 5} = pcode;
276  let Inst{4 - 0} = imm5;
277  let Constraints = "$rz = $false";
278}
279
280// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5]>
281// Instructions(13): decgt32, declt32, decne32, lsli32, lslc32, lsri32
282//                   lsrc32, asri32, asrc32, rotli32, xsr32, bclri32, bseti32
283class I_5_XZ<bits<6> sop, bits<5> pcode, string op, dag outs, dag ins,
284             list<dag> pattern>
285    : CSKY32Inst<AddrModeNone, 0x31, outs, ins,
286                 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
287  bits<5> imm5;
288  bits<5> rx;
289  bits<5> rz;
290  let Inst{25 - 21} = imm5;
291  let Inst{20 - 16} = rx;
292  let Inst{15 - 10} = sop;
293  let Inst{9 - 5} = pcode;
294  let Inst{4 - 0} = rz;
295}
296
297// mtcr32, mfcr32
298class I_5_XZ_CR<bits<6> sop, bits<5> pcode, string opStr, dag outs, dag ins,
299             list<dag> pattern>
300    : CSKY32Inst<AddrModeNone, 0x30, outs, ins, opStr, pattern> {
301  bits<5> sel;
302  bits<5> rx;
303  bits<5> cr;
304  let Inst{25 - 21} = sel;
305  let Inst{20 - 16} = rx;
306  let Inst{15 - 10} = sop;
307  let Inst{9 - 5} = pcode;
308  let Inst{4 - 0} = cr;
309}
310
311// sync
312class I_5_XZ_SYNC<bits<6> sop, bits<5> pcode, string opStr, bits<1> S, bits<1> I>
313    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), opStr, []> {
314  let Inst{25 - 21} = 0;
315  let Inst{20 - 16} = 0;
316  let Inst{15 - 10} = sop;
317  let Inst{9 - 5} = pcode;
318  let Inst{4 - 0} = 0;
319  let Inst{25} = S;
320  let Inst{21} = I;
321
322}
323
324// Priviledged Instructions
325class I_5_XZ_PRIVI<bits<6> sop, bits<5> pcode, string opStr>
326    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), opStr, []> {
327  let Inst{25 - 21} = 0;
328  let Inst{20 - 16} = 0;
329  let Inst{15 - 10} = sop;
330  let Inst{9 - 5} = pcode;
331  let Inst{4 - 0} = 0;
332}
333
334class I_CP<bits<4> sop, dag outs, dag ins, string opStr>
335    : CSKY32Inst<AddrModeNone, 0x3f, outs, ins, opStr, []> {
336  bits<5> cpid;
337  bits<12> usdef;
338  let Inst{25 - 21} = cpid;
339  let Inst{20 - 16} = 0;
340  let Inst{15 - 12} = sop;
341  let Inst{11 - 0} = usdef;
342}
343
344class I_CPOP<dag outs, dag ins, string opStr>
345    : CSKY32Inst<AddrModeNone, 0x3f, outs, ins, opStr, []> {
346  bits<5> cpid;
347  bits<20> usdef;
348  let Inst{25 - 21} = cpid;
349  let Inst{20 - 16} = usdef{19-15};
350  let Inst{15} = 1;
351  let Inst{14 - 0} = usdef{14-0};
352}
353
354class I_CP_Z<bits<4> sop, dag outs, dag ins, string opStr>
355    : CSKY32Inst<AddrModeNone, 0x3f, outs, ins, opStr, []> {
356  bits<5> cpid;
357  bits<12> usdef;
358  bits<5> rz;
359
360  let Inst{25 - 21} = cpid;
361  let Inst{20 - 16} = rz;
362  let Inst{15 - 12} = sop;
363  let Inst{11 - 0} = usdef;
364}
365
366class I_5_CACHE<bits<6> sop, bits<5> pcode, string opStr>
367    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), opStr, []> {
368  let Inst{25 - 21} = pcode;
369  let Inst{20 - 16} = 0;
370  let Inst{15 - 10} = sop;
371  let Inst{9 - 5} = 0b00001;
372  let Inst{4 - 0} = 0;
373}
374
375class I_5_X_CACHE<bits<6> sop, bits<5> pcode, string opStr>
376    : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins GPR:$rx), opStr #"\t$rx", []> {
377  bits<5> rx;
378
379  let Inst{25 - 21} = pcode;
380  let Inst{20 - 16} = rx;
381  let Inst{15 - 10} = sop;
382  let Inst{9 - 5} = 0b00001;
383  let Inst{4 - 0} = 0;
384}
385
386// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | IMM[5]>
387// Instructions(2): ldm32, (ldq32), stm32, (stq32)
388class I_5_YX<bits<6> opcode, bits<6> sop, dag outs, dag ins, string opStr, list<dag> pattern>
389    : CSKY32Inst<AddrModeNone, opcode, outs, ins, opStr, pattern> {
390  bits<10> regs;
391  bits<5> rx;
392
393  let Inst{25 - 21} = regs{9 - 5}; // ry
394  let Inst{20 - 16} = rx;
395  let Inst{15 - 10} = sop;
396  let Inst{9 - 5} = 0b00001;
397  let Inst{4 - 0} = regs{4 - 0}; // imm5
398}
399
400// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
401// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
402class I_5_XZ_U<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
403    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
404                 pattern> {
405  bits<5> rx;
406  bits<5> rz;
407  bits<5> msb;
408  bits<5> lsb;
409  let Inst{25 - 21} = lsb; // lsb
410  let Inst{20 - 16} = rx;
411  let Inst{15 - 10} = sop;
412  let Inst{9 - 5} = msb; // msb
413  let Inst{4 - 0} = rz;
414}
415
416class I_5_XZ_INS<bits<6> sop, dag outs, dag ins, string op, list<dag> pattern>
417    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
418                 pattern> {
419  bits<5> rx;
420  bits<5> rz;
421  bits<5> msb;
422  bits<5> lsb;
423  let Inst{25 - 21} = rz;
424  let Inst{20 - 16} = rx;
425  let Inst{15 - 10} = sop;
426  let Inst{9 - 5} = msb;
427  let Inst{4 - 0} = lsb;
428}
429
430// Format< OP[6] | LSB[5] | RX[5] | SOP[6] | MSB[5] | RZ[5]>
431// Instructions(6): zext32, zextb32, zexth32, sext32, sextb32, sexth32
432class I_5_XZ_U2<bits<6> sop, bits<5> lsb, bits<5> msb, dag outs, dag ins,
433  string op, list<dag> pattern>
434  : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"), pattern> {
435  bits<5> rx;
436  bits<5> rz;
437  let Inst{25 - 21} = lsb;     // lsb
438  let Inst{20 - 16} = rx;
439  let Inst{15 - 10} = sop;
440  let Inst{9 - 5} = msb;       // msb
441  let Inst{4 - 0} = rz;
442}
443
444// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | SIZE[5] | LSB[5]>
445// Instructions(1): ins32
446class I_5_ZX_U<bits<6> sop, string op, Operand operand, list<dag> pattern>
447    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins operand:$size_lsb),
448                 !strconcat(op, "\t$rz, operand:$size_lsb"), pattern> {
449  bits<10> size_lsb;
450  bits<5> rz;
451  bits<5> rx;
452  let Inst{25 - 21} = rz;
453  let Inst{20 - 16} = rx;
454  let Inst{15 - 10} = sop;
455  let Inst{9 - 5} = size_lsb{9 - 5}; // size
456  let Inst{4 - 0} = size_lsb{4 - 0}; // lsb
457}
458
459// sextb, sexth
460class I_5_XZ_US<bits<6> sop, bits<5> lsb, bits<5> msb, string op,
461  SDNode opnode, ValueType type>
462  : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
463  [(set GPR:$rz, (opnode GPR:$rx, type))]>;
464
465class I_5_XZ_UZ<bits<6> sop, bits<5> lsb, bits<5> msb, string op, int v>
466  : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
467  [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
468
469// Format< OP[6] | IMM[5] | RX[5] | SOP[6] | PCODE[5] | 00000 >
470// Instructions(1): btsti32
471class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
472            list<dag> pattern>
473    : CSKY32Inst<AddrModeNone, 0x31,
474    (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
475    !strconcat(op, "\t$rx, $imm5"), pattern> {
476  bits<5> imm5;
477  bits<5> rx;
478  let Inst{25 - 21} = imm5;
479  let Inst{20 - 16} = rx;
480  let Inst{15 - 10} = sop;
481  let Inst{9 - 5} = pcode;
482  let Inst{4 - 0} = 0;
483  let isCompare = 1;
484}
485
486// Format< OP[6] | IMM[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5]>
487// Instructions(1): bmaski32
488class I_5_Z<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
489            list<dag> pattern>
490    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins ImmType:$imm5),
491                 !strconcat(op, "\t$rz, $imm5"), pattern> {
492  bits<5> imm5;
493  bits<5> rz;
494  let Inst{25 - 21} = imm5;
495  let Inst{20 - 16} = 0;
496  let Inst{15 - 10} = sop;
497  let Inst{9 - 5} = pcode;
498  let Inst{4 - 0} = rz;
499}
500
501class I_5_IMM5<bits<6> opcode, bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
502            list<dag> pattern>
503    : CSKY32Inst<AddrModeNone, opcode, (outs), (ins ImmType:$imm5),
504                 !strconcat(op, "\t$imm5"), pattern> {
505  bits<5> imm5;
506  let Inst{25 - 21} = imm5;
507  let Inst{20 - 16} = 0;
508  let Inst{15 - 10} = sop;
509  let Inst{9 - 5} = pcode;
510  let Inst{4 - 0} = 0;
511}
512
513// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
514// Instructions(24): addu32, addc32, subu32, subc32, (rsub32), ixh32, ixw32,
515// ixd32, and32, andn32, or32, xor32, nor32, lsl32, lsr32, asr32, rotl32
516// mult32, divu32, divs32, mul.(u/s)32, mula.32.l, mula.u32, mulall.s16.s
517class R_YXZ<bits<6> opcode, bits<6> sop, bits<5> pcode, dag outs, dag ins,
518            string op, list<dag> pattern>
519    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
520                 !strconcat(op, "\t$rz, $rx, $ry"), pattern> {
521  bits<5> ry;
522  bits<5> rx;
523  bits<5> rz;
524  let Inst{25 - 21} = ry;
525  let Inst{20 - 16} = rx;
526  let Inst{15 - 10} = sop;
527  let Inst{9 - 5} = pcode;
528  let Inst{4 - 0} = rz;
529}
530
531// R_YXZ instructions with simple pattern
532// Output: GPR:rz
533// Input: GPR:rx, GPR:ry
534// Asm string: op rz, rx, ry
535// Instructions: addu32, subu32, ixh32, ixw32, ixd32, and32, andn32, or32,
536// xor32, nor32, lsl32, lsr32, asr32, mult32, divu32, divs32
537class R_YXZ_SP_F1<bits<6> sop, bits<5> pcode, PatFrag opnode, string op,
538  bit Commutable = 0> : R_YXZ<0x31, sop, pcode, (outs GPR:$rz),
539  (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
540  let isCommutable = Commutable;
541}
542
543// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
544// Instructions:(8) ldr32.b, ldr32.h, ldr32.bs, ldr32.hs, ldr32.w,
545//                  str32.b, str32.h, str32.w
546class R_YXZ_LDST<bits<6> opcode, bits<6> sop, dag outs,
547                 dag ins, string op, list<dag> pattern>
548    : CSKY32Inst<AddrModeNone, opcode, outs, ins,
549                 op # "\t$rz, ($rx, $ry << ${imm})", pattern> {
550  bits<5> rx;
551  bits<5> ry;
552  bits<5> rz;
553  bits<5> imm;
554  let Inst{25 - 21} = ry; // ry;
555  let Inst{20 - 16} = rx; // rx;
556  let Inst{15 - 10} = sop;
557  let Inst{9 - 5} = imm;  // pcode;
558  let Inst{4 - 0} = rz;
559}
560
561class I_LDR<bits<6> sop, string op> : R_YXZ_LDST<0x34, sop,
562  (outs GPR:$rz), (ins GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
563
564class I_STR<bits<6> sop, string op> : R_YXZ_LDST<0x35, sop,
565  (outs), (ins GPR:$rz, GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
566
567// Format< OP[6] | RX[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
568// Instructions:(1) not32
569class R_XXZ<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op,
570            list<dag> pattern>
571    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"),
572                 pattern> {
573  bits<5> rx;
574  bits<5> rz;
575  let Inst{25 - 21} = rx;
576  let Inst{20 - 16} = rx;
577  let Inst{15 - 10} = sop;
578  let Inst{9 - 5} = pcode;
579  let Inst{4 - 0} = rz;
580}
581
582// Format< OP[6] | RY[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
583// Instructions:(4) cmpne32, cmphs32, cmplt32, tst32
584class R_YX<bits<6> sop, bits<5> pcode, string op>
585    : CSKY32Inst<AddrModeNone, 0x31, (outs CARRY:$ca),
586                 (ins GPR:$rx, GPR:$ry),
587                 !strconcat(op, "\t$rx, $ry"), []> {
588  bits<5> ry;
589  bits<5> rx;
590  let Inst{25 - 21} = ry;
591  let Inst{20 - 16} = rx;
592  let Inst{15 - 10} = sop;
593  let Inst{9 - 5} = pcode;
594  let Inst{4 - 0} = 0;
595  let isCompare = 1;
596}
597
598// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | RZ[5] >
599// Instructions:(12)
600//   mov32, xtrb0.32, xtrb1.32, xtrb2.32, xtrb3.32, brev32, revb32
601//   revh32, abs32, ff0.32, ff1.32, bgenr32
602class R_XZ<bits<6> sop, bits<5> pcode, string op>
603    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins GPR:$rx),
604                 !strconcat(op, "\t$rz, $rx"), []> {
605  bits<5> rx;
606  bits<5> rz;
607  let Inst{25 - 21} = 0;
608  let Inst{20 - 16} = rx;
609  let Inst{15 - 10} = sop;
610  let Inst{9 - 5} = pcode;
611  let Inst{4 - 0} = rz;
612}
613
614// Format< OP[6] | RZ[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
615// Instructions:(2) movf32, movt32
616class R_ZX<bits<6> sop, bits<5> pcode, string op, list<dag> pattern>
617    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
618                 (ins CARRY:$ca, GPR:$rx, GPR:$false),
619                 !strconcat(op, "\t$rz, $rx"), pattern> {
620  bits<5> rz;
621  bits<5> rx;
622  let Inst{25 - 21} = rz;
623  let Inst{20 - 16} = rx;
624  let Inst{15 - 10} = sop;
625  let Inst{9 - 5} = pcode;
626  let Inst{4 - 0} = 0;
627  let Constraints = "$rz = $false";
628  let isSelect = 1;
629}
630
631// Format< OP[6] | 00000[5] | RX[5] | SOP[6] | PCODE[5] | 00000[5] >
632// Instructions:(1) tstnbz32
633class R_X<bits<6> sop, bits<5> pcode, dag outs, dag ins, string op, list<dag> pattern>
634    : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rx"), pattern> {
635  bits<5> rx;
636  let Inst{25 - 21} = 0;
637  let Inst{20 - 16} = rx;
638  let Inst{15 - 10} = sop;
639  let Inst{9 - 5} = pcode;
640  let Inst{4 - 0} = 0;
641}
642
643// Format< OP[6] | 00000[5] | 00000[5] | SOP[6] | PCODE[5] | RZ[5] >
644// Instructions:(2) mvc32, mvcv32
645class R_Z_1<bits<6> sop, bits<5> pcode, string op>
646    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
647                 (ins CARRY:$ca), !strconcat(op, "\t$rz"), []> {
648  bits<5> rz;
649  let Inst{25 - 21} = 0;
650  let Inst{20 - 16} = 0;
651  let Inst{15 - 10} = sop;
652  let Inst{9 - 5} = pcode;
653  let Inst{4 - 0} = rz;
654}
655
656// Format< OP[6] | RZ[5] | 00000[5] | SOP[6] | PCODE[5] | 00000[5] >
657// Instructions:(2) clrf32, clrt32
658class R_Z_2<bits<6> sop, bits<5> pcode, string op>
659    : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz),
660    (ins CARRY:$ca, GPR:$false), !strconcat(op, "\t$rz"), []> {
661  bits<5> rz;
662  let Inst{25 - 21} = rz;
663  let Inst{20 - 16} = 0;
664  let Inst{15 - 10} = sop;
665  let Inst{9 - 5} = pcode;
666  let Inst{4 - 0} = 0;
667  let Constraints = "$rz = $false";
668}
669
670class BAR<bits<5> sop, string op, bits<1> signed>
671  : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins), op, []> {
672  let Inst{25} = signed;
673  let Inst{24 - 16} = 0;
674  let Inst{15 - 5} = 0x421;
675  let Inst{4 - 0} = sop;
676  let hasSideEffects = 1;
677  let mayLoad = 0;
678  let mayStore = 0;
679}
680