1 //===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that CSKY uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "CSKYISelLowering.h" 15 #include "CSKYCallingConv.h" 16 #include "CSKYConstantPoolValue.h" 17 #include "CSKYMachineFunctionInfo.h" 18 #include "CSKYRegisterInfo.h" 19 #include "CSKYSubtarget.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/MachineFrameInfo.h" 23 #include "llvm/CodeGen/MachineJumpTableInfo.h" 24 #include "llvm/Support/Debug.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "csky-isel-lowering" 29 30 STATISTIC(NumTailCalls, "Number of tail calls"); 31 32 #include "CSKYGenCallingConv.inc" 33 34 static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3}; 35 36 CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM, 37 const CSKYSubtarget &STI) 38 : TargetLowering(TM), Subtarget(STI) { 39 // Register Class 40 addRegisterClass(MVT::i32, &CSKY::GPRRegClass); 41 42 if (STI.useHardFloat()) { 43 if (STI.hasFPUv2SingleFloat()) 44 addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass); 45 else if (STI.hasFPUv3SingleFloat()) 46 addRegisterClass(MVT::f32, &CSKY::FPR32RegClass); 47 48 if (STI.hasFPUv2DoubleFloat()) 49 addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass); 50 else if (STI.hasFPUv3DoubleFloat()) 51 addRegisterClass(MVT::f64, &CSKY::FPR64RegClass); 52 } 53 54 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); 55 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal); 56 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); 57 58 setOperationAction(ISD::SREM, MVT::i32, Expand); 59 setOperationAction(ISD::UREM, MVT::i32, Expand); 60 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 61 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 62 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 63 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 64 setOperationAction(ISD::ROTR, MVT::i32, Expand); 65 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 66 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 67 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 68 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 69 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 70 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 71 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 72 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 73 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 74 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 75 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 76 setOperationAction(ISD::MULHS, MVT::i32, Expand); 77 setOperationAction(ISD::MULHU, MVT::i32, Expand); 78 setOperationAction(ISD::VAARG, MVT::Other, Expand); 79 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 80 setOperationAction(ISD::VAEND, MVT::Other, Expand); 81 82 setLoadExtAction(ISD::EXTLOAD, MVT::i32, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i1, Promote); 84 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, MVT::i1, Promote); 85 86 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 87 setOperationAction(ISD::ExternalSymbol, MVT::i32, Custom); 88 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 89 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 90 if (!Subtarget.hasE2()) { 91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 92 } 93 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 94 setOperationAction(ISD::VASTART, MVT::Other, Custom); 95 96 if (!Subtarget.hasE2()) { 97 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i8, Expand); 98 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, MVT::i16, Expand); 99 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 100 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 101 } 102 103 if (!Subtarget.has2E3()) { 104 setOperationAction(ISD::ABS, MVT::i32, Expand); 105 setOperationAction(ISD::BITREVERSE, MVT::i32, Expand); 106 setOperationAction(ISD::SDIV, MVT::i32, Expand); 107 setOperationAction(ISD::UDIV, MVT::i32, Expand); 108 } 109 110 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 111 112 // Float 113 114 ISD::CondCode FPCCToExtend[] = { 115 ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, 116 ISD::SETUGE, ISD::SETULT, ISD::SETULE, 117 }; 118 119 ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, 120 ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN}; 121 122 if (STI.useHardFloat()) { 123 124 MVT AllVTy[] = {MVT::f32, MVT::f64}; 125 126 for (auto VT : AllVTy) { 127 setOperationAction(ISD::FREM, VT, Expand); 128 setOperationAction(ISD::SELECT_CC, VT, Expand); 129 setOperationAction(ISD::BR_CC, VT, Expand); 130 131 for (auto CC : FPCCToExtend) 132 setCondCodeAction(CC, VT, Expand); 133 for (auto Op : FPOpToExpand) 134 setOperationAction(Op, VT, Expand); 135 } 136 137 if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) { 138 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 139 } 140 if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) { 141 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); 142 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 143 } 144 } 145 146 // Compute derived properties from the register classes. 147 computeRegisterProperties(STI.getRegisterInfo()); 148 149 setBooleanContents(UndefinedBooleanContent); 150 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 151 152 // TODO: Add atomic support fully. 153 setMaxAtomicSizeInBitsSupported(0); 154 155 setStackPointerRegisterToSaveRestore(CSKY::R14); 156 const Align FunctionAlignment(2); 157 setMinFunctionAlignment(FunctionAlignment); 158 setSchedulingPreference(Sched::Source); 159 } 160 161 SDValue CSKYTargetLowering::LowerOperation(SDValue Op, 162 SelectionDAG &DAG) const { 163 switch (Op.getOpcode()) { 164 default: 165 llvm_unreachable("unimplemented op"); 166 case ISD::GlobalAddress: 167 return LowerGlobalAddress(Op, DAG); 168 case ISD::ExternalSymbol: 169 return LowerExternalSymbol(Op, DAG); 170 case ISD::GlobalTLSAddress: 171 return LowerGlobalTLSAddress(Op, DAG); 172 case ISD::JumpTable: 173 return LowerJumpTable(Op, DAG); 174 case ISD::BlockAddress: 175 return LowerBlockAddress(Op, DAG); 176 case ISD::ConstantPool: 177 return LowerConstantPool(Op, DAG); 178 case ISD::VASTART: 179 return LowerVASTART(Op, DAG); 180 case ISD::FRAMEADDR: 181 return LowerFRAMEADDR(Op, DAG); 182 case ISD::RETURNADDR: 183 return LowerRETURNADDR(Op, DAG); 184 } 185 } 186 187 EVT CSKYTargetLowering::getSetCCResultType(const DataLayout &DL, 188 LLVMContext &Context, EVT VT) const { 189 if (!VT.isVector()) 190 return MVT::i32; 191 192 return VT.changeVectorElementTypeToInteger(); 193 } 194 195 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, 196 const CCValAssign &VA, const SDLoc &DL) { 197 EVT LocVT = VA.getLocVT(); 198 199 switch (VA.getLocInfo()) { 200 default: 201 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 202 case CCValAssign::Full: 203 break; 204 case CCValAssign::BCvt: 205 Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val); 206 break; 207 } 208 return Val; 209 } 210 211 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, 212 const CCValAssign &VA, const SDLoc &DL) { 213 switch (VA.getLocInfo()) { 214 default: 215 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 216 case CCValAssign::Full: 217 break; 218 case CCValAssign::BCvt: 219 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); 220 break; 221 } 222 return Val; 223 } 224 225 static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, 226 SelectionDAG &DAG, SDValue Chain, 227 const CCValAssign &VA, const SDLoc &DL) { 228 MachineFunction &MF = DAG.getMachineFunction(); 229 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 230 EVT LocVT = VA.getLocVT(); 231 SDValue Val; 232 const TargetRegisterClass *RC; 233 234 switch (LocVT.getSimpleVT().SimpleTy) { 235 default: 236 llvm_unreachable("Unexpected register type"); 237 case MVT::i32: 238 RC = &CSKY::GPRRegClass; 239 break; 240 case MVT::f32: 241 RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass 242 : &CSKY::FPR32RegClass; 243 break; 244 case MVT::f64: 245 RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass 246 : &CSKY::FPR64RegClass; 247 break; 248 } 249 250 Register VReg = RegInfo.createVirtualRegister(RC); 251 RegInfo.addLiveIn(VA.getLocReg(), VReg); 252 Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT); 253 254 return convertLocVTToValVT(DAG, Val, VA, DL); 255 } 256 257 static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, 258 const CCValAssign &VA, const SDLoc &DL) { 259 MachineFunction &MF = DAG.getMachineFunction(); 260 MachineFrameInfo &MFI = MF.getFrameInfo(); 261 EVT LocVT = VA.getLocVT(); 262 EVT ValVT = VA.getValVT(); 263 EVT PtrVT = MVT::getIntegerVT(DAG.getDataLayout().getPointerSizeInBits(0)); 264 int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, 265 VA.getLocMemOffset(), /*Immutable=*/true); 266 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 267 SDValue Val; 268 269 ISD::LoadExtType ExtType; 270 switch (VA.getLocInfo()) { 271 default: 272 llvm_unreachable("Unexpected CCValAssign::LocInfo"); 273 case CCValAssign::Full: 274 case CCValAssign::BCvt: 275 ExtType = ISD::NON_EXTLOAD; 276 break; 277 } 278 Val = DAG.getExtLoad( 279 ExtType, DL, LocVT, Chain, FIN, 280 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), ValVT); 281 return Val; 282 } 283 284 static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, 285 const SDLoc &DL) { 286 assert(VA.getLocVT() == MVT::i32 && 287 (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) && 288 "Unexpected VA"); 289 MachineFunction &MF = DAG.getMachineFunction(); 290 MachineFrameInfo &MFI = MF.getFrameInfo(); 291 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 292 293 if (VA.isMemLoc()) { 294 // f64/i64 is passed on the stack. 295 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true); 296 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 297 return DAG.getLoad(VA.getValVT(), DL, Chain, FIN, 298 MachinePointerInfo::getFixedStack(MF, FI)); 299 } 300 301 assert(VA.isRegLoc() && "Expected register VA assignment"); 302 303 Register LoVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass); 304 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); 305 SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32); 306 SDValue Hi; 307 if (VA.getLocReg() == CSKY::R3) { 308 // Second half of f64/i64 is passed on the stack. 309 int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true); 310 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 311 Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN, 312 MachinePointerInfo::getFixedStack(MF, FI)); 313 } else { 314 // Second half of f64/i64 is passed in another GPR. 315 Register HiVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass); 316 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); 317 Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32); 318 } 319 return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), Lo, Hi); 320 } 321 322 // Transform physical registers into virtual registers. 323 SDValue CSKYTargetLowering::LowerFormalArguments( 324 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 325 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 326 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 327 328 switch (CallConv) { 329 default: 330 report_fatal_error("Unsupported calling convention"); 331 case CallingConv::C: 332 case CallingConv::Fast: 333 break; 334 } 335 336 MachineFunction &MF = DAG.getMachineFunction(); 337 338 // Used with vargs to acumulate store chains. 339 std::vector<SDValue> OutChains; 340 341 // Assign locations to all of the incoming arguments. 342 SmallVector<CCValAssign, 16> ArgLocs; 343 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 344 345 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg)); 346 347 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 348 CCValAssign &VA = ArgLocs[i]; 349 SDValue ArgValue; 350 351 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; 352 353 if (IsF64OnCSKY) 354 ArgValue = unpack64(DAG, Chain, VA, DL); 355 else if (VA.isRegLoc()) 356 ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL); 357 else 358 ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL); 359 360 InVals.push_back(ArgValue); 361 } 362 363 if (IsVarArg) { 364 const unsigned XLenInBytes = 4; 365 const MVT XLenVT = MVT::i32; 366 367 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(GPRArgRegs); 368 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); 369 const TargetRegisterClass *RC = &CSKY::GPRRegClass; 370 MachineFrameInfo &MFI = MF.getFrameInfo(); 371 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 372 CSKYMachineFunctionInfo *CSKYFI = MF.getInfo<CSKYMachineFunctionInfo>(); 373 374 // Offset of the first variable argument from stack pointer, and size of 375 // the vararg save area. For now, the varargs save area is either zero or 376 // large enough to hold a0-a4. 377 int VaArgOffset, VarArgsSaveSize; 378 379 // If all registers are allocated, then all varargs must be passed on the 380 // stack and we don't need to save any argregs. 381 if (ArgRegs.size() == Idx) { 382 VaArgOffset = CCInfo.getNextStackOffset(); 383 VarArgsSaveSize = 0; 384 } else { 385 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); 386 VaArgOffset = -VarArgsSaveSize; 387 } 388 389 // Record the frame index of the first variable argument 390 // which is a value necessary to VASTART. 391 int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); 392 CSKYFI->setVarArgsFrameIndex(FI); 393 394 // Copy the integer registers that may have been used for passing varargs 395 // to the vararg save area. 396 for (unsigned I = Idx; I < ArgRegs.size(); 397 ++I, VaArgOffset += XLenInBytes) { 398 const Register Reg = RegInfo.createVirtualRegister(RC); 399 RegInfo.addLiveIn(ArgRegs[I], Reg); 400 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT); 401 FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true); 402 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 403 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 404 MachinePointerInfo::getFixedStack(MF, FI)); 405 cast<StoreSDNode>(Store.getNode()) 406 ->getMemOperand() 407 ->setValue((Value *)nullptr); 408 OutChains.push_back(Store); 409 } 410 CSKYFI->setVarArgsSaveSize(VarArgsSaveSize); 411 } 412 413 // All stores are grouped in one node to allow the matching between 414 // the size of Ins and InVals. This only happens for vararg functions. 415 if (!OutChains.empty()) { 416 OutChains.push_back(Chain); 417 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); 418 } 419 420 return Chain; 421 } 422 423 bool CSKYTargetLowering::CanLowerReturn( 424 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, 425 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 426 SmallVector<CCValAssign, 16> CSKYLocs; 427 CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context); 428 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)); 429 } 430 431 SDValue 432 CSKYTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 433 bool IsVarArg, 434 const SmallVectorImpl<ISD::OutputArg> &Outs, 435 const SmallVectorImpl<SDValue> &OutVals, 436 const SDLoc &DL, SelectionDAG &DAG) const { 437 // Stores the assignment of the return value to a location. 438 SmallVector<CCValAssign, 16> CSKYLocs; 439 440 // Info about the registers and stack slot. 441 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CSKYLocs, 442 *DAG.getContext()); 443 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg)); 444 445 SDValue Glue; 446 SmallVector<SDValue, 4> RetOps(1, Chain); 447 448 // Copy the result values into the output registers. 449 for (unsigned i = 0, e = CSKYLocs.size(); i < e; ++i) { 450 SDValue Val = OutVals[i]; 451 CCValAssign &VA = CSKYLocs[i]; 452 assert(VA.isRegLoc() && "Can only return in registers!"); 453 454 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; 455 456 if (IsF64OnCSKY) { 457 458 assert(VA.isRegLoc() && "Expected return via registers"); 459 SDValue Split64 = DAG.getNode(CSKYISD::BITCAST_TO_LOHI, DL, 460 DAG.getVTList(MVT::i32, MVT::i32), Val); 461 SDValue Lo = Split64.getValue(0); 462 SDValue Hi = Split64.getValue(1); 463 464 Register RegLo = VA.getLocReg(); 465 assert(RegLo < CSKY::R31 && "Invalid register pair"); 466 Register RegHi = RegLo + 1; 467 468 Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue); 469 Glue = Chain.getValue(1); 470 RetOps.push_back(DAG.getRegister(RegLo, MVT::i32)); 471 Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue); 472 Glue = Chain.getValue(1); 473 RetOps.push_back(DAG.getRegister(RegHi, MVT::i32)); 474 } else { 475 // Handle a 'normal' return. 476 Val = convertValVTToLocVT(DAG, Val, VA, DL); 477 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); 478 479 // Guarantee that all emitted copies are stuck together. 480 Glue = Chain.getValue(1); 481 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 482 } 483 } 484 485 RetOps[0] = Chain; // Update chain. 486 487 // Add the glue node if we have it. 488 if (Glue.getNode()) { 489 RetOps.push_back(Glue); 490 } 491 492 // Interrupt service routines use different return instructions. 493 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt")) 494 return DAG.getNode(CSKYISD::NIR, DL, MVT::Other, RetOps); 495 496 return DAG.getNode(CSKYISD::RET, DL, MVT::Other, RetOps); 497 } 498 499 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input 500 // and output parameter nodes. 501 SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI, 502 SmallVectorImpl<SDValue> &InVals) const { 503 SelectionDAG &DAG = CLI.DAG; 504 SDLoc &DL = CLI.DL; 505 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 506 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 507 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 508 SDValue Chain = CLI.Chain; 509 SDValue Callee = CLI.Callee; 510 bool &IsTailCall = CLI.IsTailCall; 511 CallingConv::ID CallConv = CLI.CallConv; 512 bool IsVarArg = CLI.IsVarArg; 513 EVT PtrVT = getPointerTy(DAG.getDataLayout()); 514 MVT XLenVT = MVT::i32; 515 516 MachineFunction &MF = DAG.getMachineFunction(); 517 518 // Analyze the operands of the call, assigning locations to each operand. 519 SmallVector<CCValAssign, 16> ArgLocs; 520 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 521 522 ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg)); 523 524 // Check if it's really possible to do a tail call. 525 if (IsTailCall) 526 IsTailCall = false; // TODO: TailCallOptimization; 527 528 if (IsTailCall) 529 ++NumTailCalls; 530 else if (CLI.CB && CLI.CB->isMustTailCall()) 531 report_fatal_error("failed to perform tail call elimination on a call " 532 "site marked musttail"); 533 534 // Get a count of how many bytes are to be pushed on the stack. 535 unsigned NumBytes = ArgCCInfo.getNextStackOffset(); 536 537 // Create local copies for byval args 538 SmallVector<SDValue, 8> ByValArgs; 539 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 540 ISD::ArgFlagsTy Flags = Outs[i].Flags; 541 if (!Flags.isByVal()) 542 continue; 543 544 SDValue Arg = OutVals[i]; 545 unsigned Size = Flags.getByValSize(); 546 Align Alignment = Flags.getNonZeroByValAlign(); 547 548 int FI = 549 MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false); 550 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); 551 SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); 552 553 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, 554 /*IsVolatile=*/false, 555 /*AlwaysInline=*/false, IsTailCall, 556 MachinePointerInfo(), MachinePointerInfo()); 557 ByValArgs.push_back(FIPtr); 558 } 559 560 if (!IsTailCall) 561 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 562 563 // Copy argument values to their designated locations. 564 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass; 565 SmallVector<SDValue, 8> MemOpChains; 566 SDValue StackPtr; 567 for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) { 568 CCValAssign &VA = ArgLocs[i]; 569 SDValue ArgValue = OutVals[i]; 570 ISD::ArgFlagsTy Flags = Outs[i].Flags; 571 572 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; 573 574 if (IsF64OnCSKY && VA.isRegLoc()) { 575 SDValue Split64 = 576 DAG.getNode(CSKYISD::BITCAST_TO_LOHI, DL, 577 DAG.getVTList(MVT::i32, MVT::i32), ArgValue); 578 SDValue Lo = Split64.getValue(0); 579 SDValue Hi = Split64.getValue(1); 580 581 Register RegLo = VA.getLocReg(); 582 RegsToPass.push_back(std::make_pair(RegLo, Lo)); 583 584 if (RegLo == CSKY::R3) { 585 // Second half of f64/i64 is passed on the stack. 586 // Work out the address of the stack slot. 587 if (!StackPtr.getNode()) 588 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); 589 // Emit the store. 590 MemOpChains.push_back( 591 DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo())); 592 } else { 593 // Second half of f64/i64 is passed in another GPR. 594 assert(RegLo < CSKY::R31 && "Invalid register pair"); 595 Register RegHigh = RegLo + 1; 596 RegsToPass.push_back(std::make_pair(RegHigh, Hi)); 597 } 598 continue; 599 } 600 601 ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL); 602 603 // Use local copy if it is a byval arg. 604 if (Flags.isByVal()) 605 ArgValue = ByValArgs[j++]; 606 607 if (VA.isRegLoc()) { 608 // Queue up the argument copies and emit them at the end. 609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); 610 } else { 611 assert(VA.isMemLoc() && "Argument not register or memory"); 612 assert(!IsTailCall && "Tail call not allowed if stack is used " 613 "for passing parameters"); 614 615 // Work out the address of the stack slot. 616 if (!StackPtr.getNode()) 617 StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT); 618 SDValue Address = 619 DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, 620 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); 621 622 // Emit the store. 623 MemOpChains.push_back( 624 DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); 625 } 626 } 627 628 // Join the stores, which are independent of one another. 629 if (!MemOpChains.empty()) 630 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 631 632 SDValue Glue; 633 634 // Build a sequence of copy-to-reg nodes, chained and glued together. 635 for (auto &Reg : RegsToPass) { 636 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue); 637 Glue = Chain.getValue(1); 638 } 639 640 SmallVector<SDValue, 8> Ops; 641 EVT Ty = getPointerTy(DAG.getDataLayout()); 642 bool IsRegCall = false; 643 644 Ops.push_back(Chain); 645 646 if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) { 647 const GlobalValue *GV = S->getGlobal(); 648 bool IsLocal = 649 getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV); 650 651 if (isPositionIndependent() || !Subtarget.has2E3()) { 652 IsRegCall = true; 653 Ops.push_back(getAddr<GlobalAddressSDNode, true>(S, DAG, IsLocal)); 654 } else { 655 Ops.push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee), DL, Ty, 656 DAG, CSKYII::MO_None)); 657 Ops.push_back(getTargetConstantPoolValue( 658 cast<GlobalAddressSDNode>(Callee), Ty, DAG, CSKYII::MO_None)); 659 } 660 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 661 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal( 662 *MF.getFunction().getParent(), nullptr); 663 664 if (isPositionIndependent() || !Subtarget.has2E3()) { 665 IsRegCall = true; 666 Ops.push_back(getAddr<ExternalSymbolSDNode, true>(S, DAG, IsLocal)); 667 } else { 668 Ops.push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee), DL, Ty, 669 DAG, CSKYII::MO_None)); 670 Ops.push_back(getTargetConstantPoolValue( 671 cast<ExternalSymbolSDNode>(Callee), Ty, DAG, CSKYII::MO_None)); 672 } 673 } else { 674 IsRegCall = true; 675 Ops.push_back(Callee); 676 } 677 678 // Add argument registers to the end of the list so that they are 679 // known live into the call. 680 for (auto &Reg : RegsToPass) 681 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 682 683 if (!IsTailCall) { 684 // Add a register mask operand representing the call-preserved registers. 685 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 686 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); 687 assert(Mask && "Missing call preserved mask for calling convention"); 688 Ops.push_back(DAG.getRegisterMask(Mask)); 689 } 690 691 // Glue the call to the argument copies, if any. 692 if (Glue.getNode()) 693 Ops.push_back(Glue); 694 695 // Emit the call. 696 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 697 698 if (IsTailCall) { 699 MF.getFrameInfo().setHasTailCall(); 700 return DAG.getNode(IsRegCall ? CSKYISD::TAILReg : CSKYISD::TAIL, DL, 701 NodeTys, Ops); 702 } 703 704 Chain = DAG.getNode(IsRegCall ? CSKYISD::CALLReg : CSKYISD::CALL, DL, NodeTys, 705 Ops); 706 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); 707 Glue = Chain.getValue(1); 708 709 // Mark the end of the call, which is glued to the call itself. 710 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL); 711 Glue = Chain.getValue(1); 712 713 // Assign locations to each value returned by this call. 714 SmallVector<CCValAssign, 16> CSKYLocs; 715 CCState RetCCInfo(CallConv, IsVarArg, MF, CSKYLocs, *DAG.getContext()); 716 RetCCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, IsVarArg)); 717 718 // Copy all of the result registers out of their specified physreg. 719 for (auto &VA : CSKYLocs) { 720 // Copy the value out 721 SDValue RetValue = 722 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); 723 // Glue the RetValue to the end of the call sequence 724 Chain = RetValue.getValue(1); 725 Glue = RetValue.getValue(2); 726 727 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; 728 729 if (IsF64OnCSKY) { 730 assert(VA.getLocReg() == GPRArgRegs[0] && "Unexpected reg assignment"); 731 SDValue RetValue2 = 732 DAG.getCopyFromReg(Chain, DL, GPRArgRegs[1], MVT::i32, Glue); 733 Chain = RetValue2.getValue(1); 734 Glue = RetValue2.getValue(2); 735 RetValue = DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), 736 RetValue, RetValue2); 737 } 738 739 RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL); 740 741 InVals.push_back(RetValue); 742 } 743 744 return Chain; 745 } 746 747 CCAssignFn *CSKYTargetLowering::CCAssignFnForReturn(CallingConv::ID CC, 748 bool IsVarArg) const { 749 if (IsVarArg || !Subtarget.useHardFloatABI()) 750 return RetCC_CSKY_ABIV2_SOFT; 751 else 752 return RetCC_CSKY_ABIV2_FP; 753 } 754 755 CCAssignFn *CSKYTargetLowering::CCAssignFnForCall(CallingConv::ID CC, 756 bool IsVarArg) const { 757 if (IsVarArg || !Subtarget.useHardFloatABI()) 758 return CC_CSKY_ABIV2_SOFT; 759 else 760 return CC_CSKY_ABIV2_FP; 761 } 762 763 static CSKYCP::CSKYCPModifier getModifier(unsigned Flags) { 764 765 if (Flags == CSKYII::MO_ADDR32) 766 return CSKYCP::ADDR; 767 else if (Flags == CSKYII::MO_GOT32) 768 return CSKYCP::GOT; 769 else if (Flags == CSKYII::MO_GOTOFF) 770 return CSKYCP::GOTOFF; 771 else if (Flags == CSKYII::MO_PLT32) 772 return CSKYCP::PLT; 773 else if (Flags == CSKYII::MO_None) 774 return CSKYCP::NO_MOD; 775 else 776 assert(0 && "unknown CSKYII Modifier"); 777 return CSKYCP::NO_MOD; 778 } 779 780 SDValue CSKYTargetLowering::getTargetConstantPoolValue(GlobalAddressSDNode *N, 781 EVT Ty, 782 SelectionDAG &DAG, 783 unsigned Flags) const { 784 CSKYConstantPoolValue *CPV = CSKYConstantPoolConstant::Create( 785 N->getGlobal(), CSKYCP::CPValue, 0, getModifier(Flags), false); 786 787 return DAG.getTargetConstantPool(CPV, Ty); 788 } 789 790 CSKYTargetLowering::ConstraintType 791 CSKYTargetLowering::getConstraintType(StringRef Constraint) const { 792 if (Constraint.size() == 1) { 793 switch (Constraint[0]) { 794 default: 795 break; 796 case 'a': 797 case 'b': 798 case 'v': 799 case 'w': 800 case 'y': 801 return C_RegisterClass; 802 case 'c': 803 case 'l': 804 case 'h': 805 case 'z': 806 return C_Register; 807 } 808 } 809 return TargetLowering::getConstraintType(Constraint); 810 } 811 812 std::pair<unsigned, const TargetRegisterClass *> 813 CSKYTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 814 StringRef Constraint, 815 MVT VT) const { 816 if (Constraint.size() == 1) { 817 switch (Constraint[0]) { 818 case 'r': 819 return std::make_pair(0U, &CSKY::GPRRegClass); 820 case 'a': 821 return std::make_pair(0U, &CSKY::mGPRRegClass); 822 case 'b': 823 return std::make_pair(0U, &CSKY::sGPRRegClass); 824 case 'z': 825 return std::make_pair(CSKY::R14, &CSKY::GPRRegClass); 826 case 'c': 827 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass); 828 case 'w': 829 if ((Subtarget.hasFPUv2SingleFloat() || 830 Subtarget.hasFPUv3SingleFloat()) && 831 VT == MVT::f32) 832 return std::make_pair(0U, &CSKY::sFPR32RegClass); 833 if ((Subtarget.hasFPUv2DoubleFloat() || 834 Subtarget.hasFPUv3DoubleFloat()) && 835 VT == MVT::f64) 836 return std::make_pair(0U, &CSKY::sFPR64RegClass); 837 break; 838 case 'v': 839 if (Subtarget.hasFPUv2SingleFloat() && VT == MVT::f32) 840 return std::make_pair(0U, &CSKY::sFPR32RegClass); 841 if (Subtarget.hasFPUv3SingleFloat() && VT == MVT::f32) 842 return std::make_pair(0U, &CSKY::FPR32RegClass); 843 if (Subtarget.hasFPUv2DoubleFloat() && VT == MVT::f64) 844 return std::make_pair(0U, &CSKY::sFPR64RegClass); 845 if (Subtarget.hasFPUv3DoubleFloat() && VT == MVT::f64) 846 return std::make_pair(0U, &CSKY::FPR64RegClass); 847 break; 848 default: 849 break; 850 } 851 } 852 853 if (Constraint == "{c}") 854 return std::make_pair(CSKY::C, &CSKY::CARRYRegClass); 855 856 // Clang will correctly decode the usage of register name aliases into their 857 // official names. However, other frontends like `rustc` do not. This allows 858 // users of these frontends to use the ABI names for registers in LLVM-style 859 // register constraints. 860 unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower()) 861 .Case("{a0}", CSKY::R0) 862 .Case("{a1}", CSKY::R1) 863 .Case("{a2}", CSKY::R2) 864 .Case("{a3}", CSKY::R3) 865 .Case("{l0}", CSKY::R4) 866 .Case("{l1}", CSKY::R5) 867 .Case("{l2}", CSKY::R6) 868 .Case("{l3}", CSKY::R7) 869 .Case("{l4}", CSKY::R8) 870 .Case("{l5}", CSKY::R9) 871 .Case("{l6}", CSKY::R10) 872 .Case("{l7}", CSKY::R11) 873 .Case("{t0}", CSKY::R12) 874 .Case("{t1}", CSKY::R13) 875 .Case("{sp}", CSKY::R14) 876 .Case("{lr}", CSKY::R15) 877 .Case("{l8}", CSKY::R16) 878 .Case("{l9}", CSKY::R17) 879 .Case("{t2}", CSKY::R18) 880 .Case("{t3}", CSKY::R19) 881 .Case("{t4}", CSKY::R20) 882 .Case("{t5}", CSKY::R21) 883 .Case("{t6}", CSKY::R22) 884 .Cases("{t7}", "{fp}", CSKY::R23) 885 .Cases("{t8}", "{top}", CSKY::R24) 886 .Cases("{t9}", "{bsp}", CSKY::R25) 887 .Case("{r26}", CSKY::R26) 888 .Case("{r27}", CSKY::R27) 889 .Cases("{gb}", "{rgb}", "{rdb}", CSKY::R28) 890 .Cases("{tb}", "{rtb}", CSKY::R29) 891 .Case("{svbr}", CSKY::R30) 892 .Case("{tls}", CSKY::R31) 893 .Default(CSKY::NoRegister); 894 895 if (XRegFromAlias != CSKY::NoRegister) 896 return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass); 897 898 // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the 899 // TableGen record rather than the AsmName to choose registers for InlineAsm 900 // constraints, plus we want to match those names to the widest floating point 901 // register type available, manually select floating point registers here. 902 // 903 // The second case is the ABI name of the register, so that frontends can also 904 // use the ABI names in register constraint lists. 905 if (Subtarget.useHardFloat()) { 906 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) 907 .Cases("{fr0}", "{vr0}", CSKY::F0_32) 908 .Cases("{fr1}", "{vr1}", CSKY::F1_32) 909 .Cases("{fr2}", "{vr2}", CSKY::F2_32) 910 .Cases("{fr3}", "{vr3}", CSKY::F3_32) 911 .Cases("{fr4}", "{vr4}", CSKY::F4_32) 912 .Cases("{fr5}", "{vr5}", CSKY::F5_32) 913 .Cases("{fr6}", "{vr6}", CSKY::F6_32) 914 .Cases("{fr7}", "{vr7}", CSKY::F7_32) 915 .Cases("{fr8}", "{vr8}", CSKY::F8_32) 916 .Cases("{fr9}", "{vr9}", CSKY::F9_32) 917 .Cases("{fr10}", "{vr10}", CSKY::F10_32) 918 .Cases("{fr11}", "{vr11}", CSKY::F11_32) 919 .Cases("{fr12}", "{vr12}", CSKY::F12_32) 920 .Cases("{fr13}", "{vr13}", CSKY::F13_32) 921 .Cases("{fr14}", "{vr14}", CSKY::F14_32) 922 .Cases("{fr15}", "{vr15}", CSKY::F15_32) 923 .Cases("{fr16}", "{vr16}", CSKY::F16_32) 924 .Cases("{fr17}", "{vr17}", CSKY::F17_32) 925 .Cases("{fr18}", "{vr18}", CSKY::F18_32) 926 .Cases("{fr19}", "{vr19}", CSKY::F19_32) 927 .Cases("{fr20}", "{vr20}", CSKY::F20_32) 928 .Cases("{fr21}", "{vr21}", CSKY::F21_32) 929 .Cases("{fr22}", "{vr22}", CSKY::F22_32) 930 .Cases("{fr23}", "{vr23}", CSKY::F23_32) 931 .Cases("{fr24}", "{vr24}", CSKY::F24_32) 932 .Cases("{fr25}", "{vr25}", CSKY::F25_32) 933 .Cases("{fr26}", "{vr26}", CSKY::F26_32) 934 .Cases("{fr27}", "{vr27}", CSKY::F27_32) 935 .Cases("{fr28}", "{vr28}", CSKY::F28_32) 936 .Cases("{fr29}", "{vr29}", CSKY::F29_32) 937 .Cases("{fr30}", "{vr30}", CSKY::F30_32) 938 .Cases("{fr31}", "{vr31}", CSKY::F31_32) 939 .Default(CSKY::NoRegister); 940 if (FReg != CSKY::NoRegister) { 941 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg"); 942 unsigned RegNo = FReg - CSKY::F0_32; 943 unsigned DReg = CSKY::F0_64 + RegNo; 944 945 if (Subtarget.hasFPUv2DoubleFloat()) 946 return std::make_pair(DReg, &CSKY::sFPR64RegClass); 947 else if (Subtarget.hasFPUv3DoubleFloat()) 948 return std::make_pair(DReg, &CSKY::FPR64RegClass); 949 else if (Subtarget.hasFPUv2SingleFloat()) 950 return std::make_pair(FReg, &CSKY::sFPR32RegClass); 951 else if (Subtarget.hasFPUv3SingleFloat()) 952 return std::make_pair(FReg, &CSKY::FPR32RegClass); 953 } 954 } 955 956 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 957 } 958 959 static MachineBasicBlock * 960 emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode) { 961 962 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 963 DebugLoc DL = MI.getDebugLoc(); 964 965 // To "insert" a SELECT instruction, we actually have to insert the 966 // diamond control-flow pattern. The incoming instruction knows the 967 // destination vreg to set, the condition code register to branch on, the 968 // true/false values to select between, and a branch opcode to use. 969 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 970 MachineFunction::iterator It = ++BB->getIterator(); 971 972 // thisMBB: 973 // ... 974 // TrueVal = ... 975 // bt32 c, sinkMBB 976 // fallthrough --> copyMBB 977 MachineBasicBlock *thisMBB = BB; 978 MachineFunction *F = BB->getParent(); 979 MachineBasicBlock *copyMBB = F->CreateMachineBasicBlock(LLVM_BB); 980 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 981 F->insert(It, copyMBB); 982 F->insert(It, sinkMBB); 983 984 // Transfer the remainder of BB and its successor edges to sinkMBB. 985 sinkMBB->splice(sinkMBB->begin(), BB, 986 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 987 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 988 989 // Next, add the true and fallthrough blocks as its successors. 990 BB->addSuccessor(copyMBB); 991 BB->addSuccessor(sinkMBB); 992 993 // bt32 condition, sinkMBB 994 BuildMI(BB, DL, TII.get(Opcode)) 995 .addReg(MI.getOperand(1).getReg()) 996 .addMBB(sinkMBB); 997 998 // copyMBB: 999 // %FalseValue = ... 1000 // # fallthrough to sinkMBB 1001 BB = copyMBB; 1002 1003 // Update machine-CFG edges 1004 BB->addSuccessor(sinkMBB); 1005 1006 // sinkMBB: 1007 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copyMBB ] 1008 // ... 1009 BB = sinkMBB; 1010 1011 BuildMI(*BB, BB->begin(), DL, TII.get(CSKY::PHI), MI.getOperand(0).getReg()) 1012 .addReg(MI.getOperand(2).getReg()) 1013 .addMBB(thisMBB) 1014 .addReg(MI.getOperand(3).getReg()) 1015 .addMBB(copyMBB); 1016 1017 MI.eraseFromParent(); // The pseudo instruction is gone now. 1018 1019 return BB; 1020 } 1021 1022 MachineBasicBlock * 1023 CSKYTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1024 MachineBasicBlock *BB) const { 1025 switch (MI.getOpcode()) { 1026 default: 1027 llvm_unreachable("Unexpected instr type to insert"); 1028 case CSKY::FSELS: 1029 case CSKY::FSELD: 1030 if (Subtarget.hasE2()) 1031 return emitSelectPseudo(MI, BB, CSKY::BT32); 1032 else 1033 return emitSelectPseudo(MI, BB, CSKY::BT16); 1034 case CSKY::ISEL32: 1035 return emitSelectPseudo(MI, BB, CSKY::BT32); 1036 case CSKY::ISEL16: 1037 return emitSelectPseudo(MI, BB, CSKY::BT16); 1038 } 1039 } 1040 1041 SDValue CSKYTargetLowering::getTargetConstantPoolValue(ExternalSymbolSDNode *N, 1042 EVT Ty, 1043 SelectionDAG &DAG, 1044 unsigned Flags) const { 1045 CSKYConstantPoolValue *CPV = 1046 CSKYConstantPoolSymbol::Create(Type::getInt32Ty(*DAG.getContext()), 1047 N->getSymbol(), 0, getModifier(Flags)); 1048 1049 return DAG.getTargetConstantPool(CPV, Ty); 1050 } 1051 1052 SDValue CSKYTargetLowering::getTargetConstantPoolValue(JumpTableSDNode *N, 1053 EVT Ty, 1054 SelectionDAG &DAG, 1055 unsigned Flags) const { 1056 CSKYConstantPoolValue *CPV = 1057 CSKYConstantPoolJT::Create(Type::getInt32Ty(*DAG.getContext()), 1058 N->getIndex(), 0, getModifier(Flags)); 1059 return DAG.getTargetConstantPool(CPV, Ty); 1060 } 1061 1062 SDValue CSKYTargetLowering::getTargetConstantPoolValue(BlockAddressSDNode *N, 1063 EVT Ty, 1064 SelectionDAG &DAG, 1065 unsigned Flags) const { 1066 assert(N->getOffset() == 0); 1067 CSKYConstantPoolValue *CPV = CSKYConstantPoolConstant::Create( 1068 N->getBlockAddress(), CSKYCP::CPBlockAddress, 0, getModifier(Flags), 1069 false); 1070 return DAG.getTargetConstantPool(CPV, Ty); 1071 } 1072 1073 SDValue CSKYTargetLowering::getTargetConstantPoolValue(ConstantPoolSDNode *N, 1074 EVT Ty, 1075 SelectionDAG &DAG, 1076 unsigned Flags) const { 1077 assert(N->getOffset() == 0); 1078 CSKYConstantPoolValue *CPV = CSKYConstantPoolConstant::Create( 1079 N->getConstVal(), Type::getInt32Ty(*DAG.getContext()), 1080 CSKYCP::CPConstPool, 0, getModifier(Flags), false); 1081 return DAG.getTargetConstantPool(CPV, Ty); 1082 } 1083 1084 SDValue CSKYTargetLowering::getTargetNode(GlobalAddressSDNode *N, SDLoc DL, 1085 EVT Ty, SelectionDAG &DAG, 1086 unsigned Flags) const { 1087 return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags); 1088 } 1089 1090 SDValue CSKYTargetLowering::getTargetNode(ExternalSymbolSDNode *N, SDLoc DL, 1091 EVT Ty, SelectionDAG &DAG, 1092 unsigned Flags) const { 1093 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flags); 1094 } 1095 1096 SDValue CSKYTargetLowering::getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty, 1097 SelectionDAG &DAG, 1098 unsigned Flags) const { 1099 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags); 1100 } 1101 1102 SDValue CSKYTargetLowering::getTargetNode(BlockAddressSDNode *N, SDLoc DL, 1103 EVT Ty, SelectionDAG &DAG, 1104 unsigned Flags) const { 1105 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(), 1106 Flags); 1107 } 1108 1109 SDValue CSKYTargetLowering::getTargetNode(ConstantPoolSDNode *N, SDLoc DL, 1110 EVT Ty, SelectionDAG &DAG, 1111 unsigned Flags) const { 1112 1113 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), 1114 N->getOffset(), Flags); 1115 } 1116 1117 const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const { 1118 switch (Opcode) { 1119 default: 1120 llvm_unreachable("unknown CSKYISD node"); 1121 case CSKYISD::NIE: 1122 return "CSKYISD::NIE"; 1123 case CSKYISD::NIR: 1124 return "CSKYISD::NIR"; 1125 case CSKYISD::RET: 1126 return "CSKYISD::RET"; 1127 case CSKYISD::CALL: 1128 return "CSKYISD::CALL"; 1129 case CSKYISD::CALLReg: 1130 return "CSKYISD::CALLReg"; 1131 case CSKYISD::TAIL: 1132 return "CSKYISD::TAIL"; 1133 case CSKYISD::TAILReg: 1134 return "CSKYISD::TAILReg"; 1135 case CSKYISD::LOAD_ADDR: 1136 return "CSKYISD::LOAD_ADDR"; 1137 case CSKYISD::BITCAST_TO_LOHI: 1138 return "CSKYISD::BITCAST_TO_LOHI"; 1139 case CSKYISD::BITCAST_FROM_LOHI: 1140 return "CSKYISD::BITCAST_FROM_LOHI"; 1141 } 1142 } 1143 1144 SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op, 1145 SelectionDAG &DAG) const { 1146 SDLoc DL(Op); 1147 EVT Ty = Op.getValueType(); 1148 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1149 int64_t Offset = N->getOffset(); 1150 1151 const GlobalValue *GV = N->getGlobal(); 1152 bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV); 1153 SDValue Addr = getAddr<GlobalAddressSDNode, false>(N, DAG, IsLocal); 1154 1155 // In order to maximise the opportunity for common subexpression elimination, 1156 // emit a separate ADD node for the global address offset instead of folding 1157 // it in the global address node. Later peephole optimisations may choose to 1158 // fold it back in when profitable. 1159 if (Offset != 0) 1160 return DAG.getNode(ISD::ADD, DL, Ty, Addr, 1161 DAG.getConstant(Offset, DL, MVT::i32)); 1162 return Addr; 1163 } 1164 1165 SDValue CSKYTargetLowering::LowerExternalSymbol(SDValue Op, 1166 SelectionDAG &DAG) const { 1167 ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op); 1168 1169 return getAddr(N, DAG, false); 1170 } 1171 1172 SDValue CSKYTargetLowering::LowerJumpTable(SDValue Op, 1173 SelectionDAG &DAG) const { 1174 JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1175 1176 return getAddr<JumpTableSDNode, false>(N, DAG); 1177 } 1178 1179 SDValue CSKYTargetLowering::LowerBlockAddress(SDValue Op, 1180 SelectionDAG &DAG) const { 1181 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1182 1183 return getAddr(N, DAG); 1184 } 1185 1186 SDValue CSKYTargetLowering::LowerConstantPool(SDValue Op, 1187 SelectionDAG &DAG) const { 1188 assert(!Subtarget.hasE2()); 1189 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1190 1191 return getAddr(N, DAG); 1192 } 1193 1194 SDValue CSKYTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1195 MachineFunction &MF = DAG.getMachineFunction(); 1196 CSKYMachineFunctionInfo *FuncInfo = MF.getInfo<CSKYMachineFunctionInfo>(); 1197 1198 SDLoc DL(Op); 1199 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1200 getPointerTy(MF.getDataLayout())); 1201 1202 // vastart just stores the address of the VarArgsFrameIndex slot into the 1203 // memory location argument. 1204 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1205 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1206 MachinePointerInfo(SV)); 1207 } 1208 1209 SDValue CSKYTargetLowering::LowerFRAMEADDR(SDValue Op, 1210 SelectionDAG &DAG) const { 1211 const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo(); 1212 MachineFunction &MF = DAG.getMachineFunction(); 1213 MachineFrameInfo &MFI = MF.getFrameInfo(); 1214 MFI.setFrameAddressIsTaken(true); 1215 1216 EVT VT = Op.getValueType(); 1217 SDLoc dl(Op); 1218 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1219 Register FrameReg = RI.getFrameRegister(MF); 1220 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1221 while (Depth--) 1222 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 1223 MachinePointerInfo()); 1224 return FrameAddr; 1225 } 1226 1227 SDValue CSKYTargetLowering::LowerRETURNADDR(SDValue Op, 1228 SelectionDAG &DAG) const { 1229 const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo(); 1230 MachineFunction &MF = DAG.getMachineFunction(); 1231 MachineFrameInfo &MFI = MF.getFrameInfo(); 1232 MFI.setReturnAddressIsTaken(true); 1233 1234 if (verifyReturnAddressArgumentIsConstant(Op, DAG)) 1235 return SDValue(); 1236 1237 EVT VT = Op.getValueType(); 1238 SDLoc dl(Op); 1239 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1240 if (Depth) { 1241 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 1242 SDValue Offset = DAG.getConstant(4, dl, MVT::i32); 1243 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 1244 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 1245 MachinePointerInfo()); 1246 } 1247 // Return the value of the return address register, marking it an implicit 1248 // live-in. 1249 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32)); 1250 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 1251 } 1252 1253 Register CSKYTargetLowering::getExceptionPointerRegister( 1254 const Constant *PersonalityFn) const { 1255 return CSKY::R0; 1256 } 1257 1258 Register CSKYTargetLowering::getExceptionSelectorRegister( 1259 const Constant *PersonalityFn) const { 1260 return CSKY::R1; 1261 } 1262 1263 SDValue CSKYTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1264 SelectionDAG &DAG) const { 1265 SDLoc DL(Op); 1266 EVT Ty = Op.getValueType(); 1267 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1268 int64_t Offset = N->getOffset(); 1269 MVT XLenVT = MVT::i32; 1270 1271 TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); 1272 SDValue Addr; 1273 switch (Model) { 1274 case TLSModel::LocalExec: 1275 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false); 1276 break; 1277 case TLSModel::InitialExec: 1278 Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true); 1279 break; 1280 case TLSModel::LocalDynamic: 1281 case TLSModel::GeneralDynamic: 1282 Addr = getDynamicTLSAddr(N, DAG); 1283 break; 1284 } 1285 1286 // In order to maximise the opportunity for common subexpression elimination, 1287 // emit a separate ADD node for the global address offset instead of folding 1288 // it in the global address node. Later peephole optimisations may choose to 1289 // fold it back in when profitable. 1290 if (Offset != 0) 1291 return DAG.getNode(ISD::ADD, DL, Ty, Addr, 1292 DAG.getConstant(Offset, DL, XLenVT)); 1293 return Addr; 1294 } 1295 1296 SDValue CSKYTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N, 1297 SelectionDAG &DAG, 1298 bool UseGOT) const { 1299 MachineFunction &MF = DAG.getMachineFunction(); 1300 CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>(); 1301 1302 unsigned CSKYPCLabelIndex = CFI->createPICLabelUId(); 1303 1304 SDLoc DL(N); 1305 EVT Ty = getPointerTy(DAG.getDataLayout()); 1306 1307 CSKYCP::CSKYCPModifier Flag = UseGOT ? CSKYCP::TLSIE : CSKYCP::TLSLE; 1308 bool AddCurrentAddr = UseGOT ? true : false; 1309 unsigned char PCAjust = UseGOT ? 4 : 0; 1310 1311 CSKYConstantPoolValue *CPV = 1312 CSKYConstantPoolConstant::Create(N->getGlobal(), CSKYCP::CPValue, PCAjust, 1313 Flag, AddCurrentAddr, CSKYPCLabelIndex); 1314 SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty); 1315 1316 SDValue Load; 1317 if (UseGOT) { 1318 SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32); 1319 auto *LRWGRS = DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, 1320 {CAddr, PICLabel}); 1321 auto LRWADDGRS = 1322 DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1)); 1323 Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS, 1324 MachinePointerInfo(N->getGlobal())); 1325 } else { 1326 Load = SDValue(DAG.getMachineNode(CSKY::LRW32, DL, Ty, CAddr), 0); 1327 } 1328 1329 // Add the thread pointer. 1330 SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32); 1331 return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg); 1332 } 1333 1334 SDValue CSKYTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N, 1335 SelectionDAG &DAG) const { 1336 MachineFunction &MF = DAG.getMachineFunction(); 1337 CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>(); 1338 1339 unsigned CSKYPCLabelIndex = CFI->createPICLabelUId(); 1340 1341 SDLoc DL(N); 1342 EVT Ty = getPointerTy(DAG.getDataLayout()); 1343 IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits()); 1344 1345 CSKYConstantPoolValue *CPV = 1346 CSKYConstantPoolConstant::Create(N->getGlobal(), CSKYCP::CPValue, 4, 1347 CSKYCP::TLSGD, true, CSKYPCLabelIndex); 1348 SDValue Addr = DAG.getTargetConstantPool(CPV, Ty); 1349 SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32); 1350 1351 auto *LRWGRS = 1352 DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, {Addr, PICLabel}); 1353 1354 auto Load = 1355 DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1)); 1356 1357 // Prepare argument list to generate call. 1358 ArgListTy Args; 1359 ArgListEntry Entry; 1360 Entry.Node = Load; 1361 Entry.Ty = CallTy; 1362 Args.push_back(Entry); 1363 1364 // Setup call to __tls_get_addr. 1365 TargetLowering::CallLoweringInfo CLI(DAG); 1366 CLI.setDebugLoc(DL) 1367 .setChain(DAG.getEntryNode()) 1368 .setLibCallee(CallingConv::C, CallTy, 1369 DAG.getExternalSymbol("__tls_get_addr", Ty), 1370 std::move(Args)); 1371 SDValue V = LowerCallTo(CLI).first; 1372 1373 return V; 1374 } 1375