1//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the BPF instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "BPFInstrFormats.td" 14 15// Instruction Operands and Patterns 16 17// These are target-independent nodes, but have target-specific formats. 18def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, 19 SDTCisVT<1, iPTR>]>; 20def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 21def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; 23def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, 24 SDTCisSameAs<0, 4>, 25 SDTCisSameAs<4, 5>]>; 26def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>, 27 SDTCisVT<3, OtherVT>]>; 28def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29 SDTCisPtrTy<0>]>; 30def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>, 31 SDTCisVT<1, i64>, 32 SDTCisVT<2, i64>, 33 SDTCisVT<3, i64>]>; 34 35def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall, 36 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 37 SDNPVariadic]>; 38def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone, 39 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 40def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart, 41 [SDNPHasChain, SDNPOutGlue]>; 42def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd, 43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 44def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC, 45 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>; 46 47def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>; 48def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>; 49def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY, 50 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 51 SDNPMayStore, SDNPMayLoad]>; 52def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">; 53def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">; 54def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">; 55def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">; 56 57def brtarget : Operand<OtherVT> { 58 let PrintMethod = "printBrTargetOperand"; 59} 60def calltarget : Operand<i64>; 61 62def u64imm : Operand<i64> { 63 let PrintMethod = "printImm64Operand"; 64} 65 66def i64immSExt32 : PatLeaf<(i64 imm), 67 [{return isInt<32>(N->getSExtValue()); }]>; 68def i32immSExt32 : PatLeaf<(i32 imm), 69 [{return isInt<32>(N->getSExtValue()); }]>; 70 71// Addressing modes. 72def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>; 73def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>; 74 75// Address operands 76def MEMri : Operand<i64> { 77 let PrintMethod = "printMemOperand"; 78 let EncoderMethod = "getMemoryOpValue"; 79 let DecoderMethod = "decodeMemoryOpValue"; 80 let MIOperandInfo = (ops GPR, i16imm); 81} 82 83// Conditional code predicates - used for pattern matching for jump instructions 84def BPF_CC_EQ : PatLeaf<(i64 imm), 85 [{return (N->getZExtValue() == ISD::SETEQ);}]>; 86def BPF_CC_NE : PatLeaf<(i64 imm), 87 [{return (N->getZExtValue() == ISD::SETNE);}]>; 88def BPF_CC_GE : PatLeaf<(i64 imm), 89 [{return (N->getZExtValue() == ISD::SETGE);}]>; 90def BPF_CC_GT : PatLeaf<(i64 imm), 91 [{return (N->getZExtValue() == ISD::SETGT);}]>; 92def BPF_CC_GTU : PatLeaf<(i64 imm), 93 [{return (N->getZExtValue() == ISD::SETUGT);}]>; 94def BPF_CC_GEU : PatLeaf<(i64 imm), 95 [{return (N->getZExtValue() == ISD::SETUGE);}]>; 96def BPF_CC_LE : PatLeaf<(i64 imm), 97 [{return (N->getZExtValue() == ISD::SETLE);}]>; 98def BPF_CC_LT : PatLeaf<(i64 imm), 99 [{return (N->getZExtValue() == ISD::SETLT);}]>; 100def BPF_CC_LTU : PatLeaf<(i64 imm), 101 [{return (N->getZExtValue() == ISD::SETULT);}]>; 102def BPF_CC_LEU : PatLeaf<(i64 imm), 103 [{return (N->getZExtValue() == ISD::SETULE);}]>; 104def BPF_CC_EQ_32 : PatLeaf<(i32 imm), 105 [{return (N->getZExtValue() == ISD::SETEQ);}]>; 106def BPF_CC_NE_32 : PatLeaf<(i32 imm), 107 [{return (N->getZExtValue() == ISD::SETNE);}]>; 108def BPF_CC_GE_32 : PatLeaf<(i32 imm), 109 [{return (N->getZExtValue() == ISD::SETGE);}]>; 110def BPF_CC_GT_32 : PatLeaf<(i32 imm), 111 [{return (N->getZExtValue() == ISD::SETGT);}]>; 112def BPF_CC_GTU_32 : PatLeaf<(i32 imm), 113 [{return (N->getZExtValue() == ISD::SETUGT);}]>; 114def BPF_CC_GEU_32 : PatLeaf<(i32 imm), 115 [{return (N->getZExtValue() == ISD::SETUGE);}]>; 116def BPF_CC_LE_32 : PatLeaf<(i32 imm), 117 [{return (N->getZExtValue() == ISD::SETLE);}]>; 118def BPF_CC_LT_32 : PatLeaf<(i32 imm), 119 [{return (N->getZExtValue() == ISD::SETLT);}]>; 120def BPF_CC_LTU_32 : PatLeaf<(i32 imm), 121 [{return (N->getZExtValue() == ISD::SETULT);}]>; 122def BPF_CC_LEU_32 : PatLeaf<(i32 imm), 123 [{return (N->getZExtValue() == ISD::SETULE);}]>; 124 125// For arithmetic and jump instructions the 8-bit 'code' 126// field is divided into three parts: 127// 128// +----------------+--------+--------------------+ 129// | 4 bits | 1 bit | 3 bits | 130// | operation code | source | instruction class | 131// +----------------+--------+--------------------+ 132// (MSB) (LSB) 133class TYPE_ALU_JMP<bits<4> op, bits<1> srctype, 134 dag outs, dag ins, string asmstr, list<dag> pattern> 135 : InstBPF<outs, ins, asmstr, pattern> { 136 137 let Inst{63-60} = op; 138 let Inst{59} = srctype; 139} 140 141//For load and store instructions the 8-bit 'code' field is divided as: 142// 143// +--------+--------+-------------------+ 144// | 3 bits | 2 bits | 3 bits | 145// | mode | size | instruction class | 146// +--------+--------+-------------------+ 147// (MSB) (LSB) 148class TYPE_LD_ST<bits<3> mode, bits<2> size, 149 dag outs, dag ins, string asmstr, list<dag> pattern> 150 : InstBPF<outs, ins, asmstr, pattern> { 151 152 let Inst{63-61} = mode; 153 let Inst{60-59} = size; 154} 155 156// jump instructions 157class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 158 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, 159 (outs), 160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst), 161 "if $dst "#OpcodeStr#" $src goto $BrDst", 162 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> { 163 bits<4> dst; 164 bits<4> src; 165 bits<16> BrDst; 166 167 let Inst{55-52} = src; 168 let Inst{51-48} = dst; 169 let Inst{47-32} = BrDst; 170 let BPFClass = BPF_JMP; 171} 172 173class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 174 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 175 (outs), 176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst), 177 "if $dst "#OpcodeStr#" $imm goto $BrDst", 178 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> { 179 bits<4> dst; 180 bits<16> BrDst; 181 bits<32> imm; 182 183 let Inst{51-48} = dst; 184 let Inst{47-32} = BrDst; 185 let Inst{31-0} = imm; 186 let BPFClass = BPF_JMP; 187} 188 189class JMP_RR_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 190 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, 191 (outs), 192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst), 193 "if $dst "#OpcodeStr#" $src goto $BrDst", 194 [(BPFbrcc i32:$dst, i32:$src, Cond, bb:$BrDst)]> { 195 bits<4> dst; 196 bits<4> src; 197 bits<16> BrDst; 198 199 let Inst{55-52} = src; 200 let Inst{51-48} = dst; 201 let Inst{47-32} = BrDst; 202 let BPFClass = BPF_JMP32; 203} 204 205class JMP_RI_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 206 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 207 (outs), 208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst), 209 "if $dst "#OpcodeStr#" $imm goto $BrDst", 210 [(BPFbrcc i32:$dst, i32immSExt32:$imm, Cond, bb:$BrDst)]> { 211 bits<4> dst; 212 bits<16> BrDst; 213 bits<32> imm; 214 215 let Inst{51-48} = dst; 216 let Inst{47-32} = BrDst; 217 let Inst{31-0} = imm; 218 let BPFClass = BPF_JMP32; 219} 220 221multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond, PatLeaf Cond32> { 222 def _rr : JMP_RR<Opc, OpcodeStr, Cond>; 223 def _ri : JMP_RI<Opc, OpcodeStr, Cond>; 224 def _rr_32 : JMP_RR_32<Opc, OpcodeStr, Cond32>; 225 def _ri_32 : JMP_RI_32<Opc, OpcodeStr, Cond32>; 226} 227 228let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in { 229// cmp+goto instructions 230defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ, BPF_CC_EQ_32>; 231defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU, BPF_CC_GTU_32>; 232defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU, BPF_CC_GEU_32>; 233defm JNE : J<BPF_JNE, "!=", BPF_CC_NE, BPF_CC_NE_32>; 234defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT, BPF_CC_GT_32>; 235defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE, BPF_CC_GE_32>; 236defm JULT : J<BPF_JLT, "<", BPF_CC_LTU, BPF_CC_LTU_32>; 237defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU, BPF_CC_LEU_32>; 238defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT, BPF_CC_LT_32>; 239defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE, BPF_CC_LE_32>; 240} 241 242// ALU instructions 243class ALU_RI<BPFOpClass Class, BPFArithOp Opc, 244 dag outs, dag ins, string asmstr, list<dag> pattern> 245 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> { 246 bits<4> dst; 247 bits<32> imm; 248 249 let Inst{51-48} = dst; 250 let Inst{31-0} = imm; 251 let BPFClass = Class; 252} 253 254class ALU_RR<BPFOpClass Class, BPFArithOp Opc, 255 dag outs, dag ins, string asmstr, list<dag> pattern> 256 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> { 257 bits<4> dst; 258 bits<4> src; 259 260 let Inst{55-52} = src; 261 let Inst{51-48} = dst; 262 let BPFClass = Class; 263} 264 265multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> { 266 def _rr : ALU_RR<BPF_ALU64, Opc, 267 (outs GPR:$dst), 268 (ins GPR:$src2, GPR:$src), 269 "$dst "#OpcodeStr#" $src", 270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>; 271 def _ri : ALU_RI<BPF_ALU64, Opc, 272 (outs GPR:$dst), 273 (ins GPR:$src2, i64imm:$imm), 274 "$dst "#OpcodeStr#" $imm", 275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>; 276 def _rr_32 : ALU_RR<BPF_ALU, Opc, 277 (outs GPR32:$dst), 278 (ins GPR32:$src2, GPR32:$src), 279 "$dst "#OpcodeStr#" $src", 280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>; 281 def _ri_32 : ALU_RI<BPF_ALU, Opc, 282 (outs GPR32:$dst), 283 (ins GPR32:$src2, i32imm:$imm), 284 "$dst "#OpcodeStr#" $imm", 285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>; 286} 287 288let Constraints = "$dst = $src2" in { 289let isAsCheapAsAMove = 1 in { 290 defm ADD : ALU<BPF_ADD, "+=", add>; 291 defm SUB : ALU<BPF_SUB, "-=", sub>; 292 defm OR : ALU<BPF_OR, "|=", or>; 293 defm AND : ALU<BPF_AND, "&=", and>; 294 defm SLL : ALU<BPF_LSH, "<<=", shl>; 295 defm SRL : ALU<BPF_RSH, ">>=", srl>; 296 defm XOR : ALU<BPF_XOR, "^=", xor>; 297 defm SRA : ALU<BPF_ARSH, "s>>=", sra>; 298} 299 defm MUL : ALU<BPF_MUL, "*=", mul>; 300 defm DIV : ALU<BPF_DIV, "/=", udiv>; 301 defm MOD : ALU<BPF_MOD, "%=", urem>; 302} 303 304class NEG_RR<BPFOpClass Class, BPFArithOp Opc, 305 dag outs, dag ins, string asmstr, list<dag> pattern> 306 : TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> { 307 bits<4> dst; 308 309 let Inst{51-48} = dst; 310 let BPFClass = Class; 311} 312 313let Constraints = "$dst = $src", isAsCheapAsAMove = 1 in { 314 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src), 315 "$dst = -$src", 316 [(set GPR:$dst, (ineg i64:$src))]>; 317 def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src), 318 "$dst = -$src", 319 [(set GPR32:$dst, (ineg i32:$src))]>; 320} 321 322class LD_IMM64<bits<4> Pseudo, string OpcodeStr> 323 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 324 (outs GPR:$dst), 325 (ins u64imm:$imm), 326 "$dst "#OpcodeStr#" ${imm} ll", 327 [(set GPR:$dst, (i64 imm:$imm))]> { 328 329 bits<4> dst; 330 bits<64> imm; 331 332 let Inst{51-48} = dst; 333 let Inst{55-52} = Pseudo; 334 let Inst{47-32} = 0; 335 let Inst{31-0} = imm{31-0}; 336 let BPFClass = BPF_LD; 337} 338 339let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 340def LD_imm64 : LD_IMM64<0, "=">; 341def MOV_rr : ALU_RR<BPF_ALU64, BPF_MOV, 342 (outs GPR:$dst), 343 (ins GPR:$src), 344 "$dst = $src", 345 []>; 346def MOV_ri : ALU_RI<BPF_ALU64, BPF_MOV, 347 (outs GPR:$dst), 348 (ins i64imm:$imm), 349 "$dst = $imm", 350 [(set GPR:$dst, (i64 i64immSExt32:$imm))]>; 351def MOV_rr_32 : ALU_RR<BPF_ALU, BPF_MOV, 352 (outs GPR32:$dst), 353 (ins GPR32:$src), 354 "$dst = $src", 355 []>; 356def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV, 357 (outs GPR32:$dst), 358 (ins i32imm:$imm), 359 "$dst = $imm", 360 [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>; 361} 362 363def FI_ri 364 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 365 (outs GPR:$dst), 366 (ins MEMri:$addr), 367 "lea\t$dst, $addr", 368 [(set i64:$dst, FIri:$addr)]> { 369 // This is a tentative instruction, and will be replaced 370 // with MOV_rr and ADD_ri in PEI phase 371 let Inst{51-48} = 0; 372 let Inst{55-52} = 2; 373 let Inst{47-32} = 0; 374 let Inst{31-0} = 0; 375 let BPFClass = BPF_LD; 376 bit isPseudo = true; 377} 378 379def LD_pseudo 380 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 381 (outs GPR:$dst), 382 (ins i64imm:$pseudo, u64imm:$imm), 383 "ld_pseudo\t$dst, $pseudo, $imm", 384 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> { 385 386 bits<4> dst; 387 bits<64> imm; 388 bits<4> pseudo; 389 390 let Inst{51-48} = dst; 391 let Inst{55-52} = pseudo; 392 let Inst{47-32} = 0; 393 let Inst{31-0} = imm{31-0}; 394 let BPFClass = BPF_LD; 395} 396 397// STORE instructions 398class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 399 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 400 (outs), 401 (ins GPR:$src, MEMri:$addr), 402 "*("#OpcodeStr#" *)($addr) = $src", 403 Pattern> { 404 bits<4> src; 405 bits<20> addr; 406 407 let Inst{51-48} = addr{19-16}; // base reg 408 let Inst{55-52} = src; 409 let Inst{47-32} = addr{15-0}; // offset 410 let BPFClass = BPF_STX; 411} 412 413class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> 414 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>; 415 416let Predicates = [BPFNoALU32] in { 417 def STW : STOREi64<BPF_W, "u32", truncstorei32>; 418 def STH : STOREi64<BPF_H, "u16", truncstorei16>; 419 def STB : STOREi64<BPF_B, "u8", truncstorei8>; 420} 421def STD : STOREi64<BPF_DW, "u64", store>; 422 423// LOAD instructions 424class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 425 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 426 (outs GPR:$dst), 427 (ins MEMri:$addr), 428 "$dst = *("#OpcodeStr#" *)($addr)", 429 Pattern> { 430 bits<4> dst; 431 bits<20> addr; 432 433 let Inst{51-48} = dst; 434 let Inst{55-52} = addr{19-16}; 435 let Inst{47-32} = addr{15-0}; 436 let BPFClass = BPF_LDX; 437} 438 439class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 440 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>; 441 442let isCodeGenOnly = 1 in { 443 def CORE_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value, 444 (outs GPR:$dst), 445 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 446 "$dst = core_mem($opcode, $src, $offset)", 447 []>; 448 def CORE_ALU32_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value, 449 (outs GPR32:$dst), 450 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 451 "$dst = core_alu32_mem($opcode, $src, $offset)", 452 []>; 453 let Constraints = "$dst = $src" in { 454 def CORE_SHIFT : ALU_RR<BPF_ALU64, BPF_LSH, 455 (outs GPR:$dst), 456 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 457 "$dst = core_shift($opcode, $src, $offset)", 458 []>; 459 } 460} 461 462let Predicates = [BPFNoALU32] in { 463 def LDW : LOADi64<BPF_W, "u32", zextloadi32>; 464 def LDH : LOADi64<BPF_H, "u16", zextloadi16>; 465 def LDB : LOADi64<BPF_B, "u8", zextloadi8>; 466} 467 468def LDD : LOADi64<BPF_DW, "u64", load>; 469 470class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern> 471 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 472 (outs), 473 (ins brtarget:$BrDst), 474 !strconcat(OpcodeStr, " $BrDst"), 475 Pattern> { 476 bits<16> BrDst; 477 478 let Inst{47-32} = BrDst; 479 let BPFClass = BPF_JMP; 480} 481 482class CALL<string OpcodeStr> 483 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_K.Value, 484 (outs), 485 (ins calltarget:$BrDst), 486 !strconcat(OpcodeStr, " $BrDst"), 487 []> { 488 bits<32> BrDst; 489 490 let Inst{31-0} = BrDst; 491 let BPFClass = BPF_JMP; 492} 493 494class CALLX<string OpcodeStr> 495 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_X.Value, 496 (outs), 497 (ins GPR:$BrDst), 498 !strconcat(OpcodeStr, " $BrDst"), 499 []> { 500 bits<32> BrDst; 501 502 let Inst{31-0} = BrDst; 503 let BPFClass = BPF_JMP; 504} 505 506// Jump always 507let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { 508 def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>; 509} 510 511// Jump and link 512let isCall=1, hasDelaySlot=0, Uses = [R11], 513 // Potentially clobbered registers 514 Defs = [R0, R1, R2, R3, R4, R5] in { 515 def JAL : CALL<"call">; 516 def JALX : CALLX<"callx">; 517} 518 519class NOP_I<string OpcodeStr> 520 : TYPE_ALU_JMP<BPF_MOV.Value, BPF_X.Value, 521 (outs), 522 (ins i32imm:$imm), 523 !strconcat(OpcodeStr, "\t$imm"), 524 []> { 525 // mov r0, r0 == nop 526 let Inst{55-52} = 0; 527 let Inst{51-48} = 0; 528 let BPFClass = BPF_ALU64; 529} 530 531let hasSideEffects = 0, isCodeGenOnly = 1 in 532 def NOP : NOP_I<"nop">; 533 534class RET<string OpcodeStr> 535 : TYPE_ALU_JMP<BPF_EXIT.Value, BPF_K.Value, 536 (outs), 537 (ins), 538 !strconcat(OpcodeStr, ""), 539 [(BPFretflag)]> { 540 let Inst{31-0} = 0; 541 let BPFClass = BPF_JMP; 542} 543 544let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, 545 isNotDuplicable = 1 in { 546 def RET : RET<"exit">; 547} 548 549// ADJCALLSTACKDOWN/UP pseudo insns 550let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in { 551def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 552 "#ADJCALLSTACKDOWN $amt1 $amt2", 553 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>; 554def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 555 "#ADJCALLSTACKUP $amt1 $amt2", 556 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>; 557} 558 559let usesCustomInserter = 1, isCodeGenOnly = 1 in { 560 def Select : Pseudo<(outs GPR:$dst), 561 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), 562 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 563 [(set i64:$dst, 564 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>; 565 def Select_Ri : Pseudo<(outs GPR:$dst), 566 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), 567 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 568 [(set i64:$dst, 569 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>; 570 def Select_64_32 : Pseudo<(outs GPR32:$dst), 571 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), 572 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 573 [(set i32:$dst, 574 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i32:$src, i32:$src2))]>; 575 def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst), 576 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), 577 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 578 [(set i32:$dst, 579 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i32:$src, i32:$src2))]>; 580 def Select_32 : Pseudo<(outs GPR32:$dst), 581 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), 582 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 583 [(set i32:$dst, 584 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i32:$src, i32:$src2))]>; 585 def Select_Ri_32 : Pseudo<(outs GPR32:$dst), 586 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), 587 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 588 [(set i32:$dst, 589 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i32:$src, i32:$src2))]>; 590 def Select_32_64 : Pseudo<(outs GPR:$dst), 591 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), 592 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 593 [(set i64:$dst, 594 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i64:$src, i64:$src2))]>; 595 def Select_Ri_32_64 : Pseudo<(outs GPR:$dst), 596 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), 597 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 598 [(set i64:$dst, 599 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>; 600} 601 602// load 64-bit global addr into register 603def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>; 604 605// 0xffffFFFF doesn't fit into simm32, optimize common case 606def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)), 607 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>; 608 609// Calls 610def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>; 611def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>; 612def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>; 613def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>; 614 615// Loads 616let Predicates = [BPFNoALU32] in { 617 def : Pat<(i64 (extloadi8 ADDRri:$src)), (i64 (LDB ADDRri:$src))>; 618 def : Pat<(i64 (extloadi16 ADDRri:$src)), (i64 (LDH ADDRri:$src))>; 619 def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>; 620} 621 622// Atomic XADD for BPFNoALU32 623class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 624 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 625 (outs GPR:$dst), 626 (ins MEMri:$addr, GPR:$val), 627 "lock *("#OpcodeStr#" *)($addr) += $val", 628 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { 629 bits<4> dst; 630 bits<20> addr; 631 632 let Inst{51-48} = addr{19-16}; // base reg 633 let Inst{55-52} = dst; 634 let Inst{47-32} = addr{15-0}; // offset 635 let Inst{7-4} = BPF_ADD.Value; 636 let BPFClass = BPF_STX; 637} 638 639let Constraints = "$dst = $val" in { 640 let Predicates = [BPFNoALU32] in { 641 def XADDW : XADD<BPF_W, "u32", atomic_load_add_32>; 642 } 643} 644 645// Atomic add, and, or, xor 646class ATOMIC_NOFETCH<BPFArithOp Opc, string Opstr> 647 : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_DW.Value, 648 (outs GPR:$dst), 649 (ins MEMri:$addr, GPR:$val), 650 "lock *(u64 *)($addr) " #Opstr# "= $val", 651 []> { 652 bits<4> dst; 653 bits<20> addr; 654 655 let Inst{51-48} = addr{19-16}; // base reg 656 let Inst{55-52} = dst; 657 let Inst{47-32} = addr{15-0}; // offset 658 let Inst{7-4} = Opc.Value; 659 let BPFClass = BPF_STX; 660} 661 662class ATOMIC32_NOFETCH<BPFArithOp Opc, string Opstr> 663 : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_W.Value, 664 (outs GPR32:$dst), 665 (ins MEMri:$addr, GPR32:$val), 666 "lock *(u32 *)($addr) " #Opstr# "= $val", 667 []> { 668 bits<4> dst; 669 bits<20> addr; 670 671 let Inst{51-48} = addr{19-16}; // base reg 672 let Inst{55-52} = dst; 673 let Inst{47-32} = addr{15-0}; // offset 674 let Inst{7-4} = Opc.Value; 675 let BPFClass = BPF_STX; 676} 677 678let Constraints = "$dst = $val" in { 679 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 680 def XADDW32 : ATOMIC32_NOFETCH<BPF_ADD, "+">; 681 def XANDW32 : ATOMIC32_NOFETCH<BPF_AND, "&">; 682 def XORW32 : ATOMIC32_NOFETCH<BPF_OR, "|">; 683 def XXORW32 : ATOMIC32_NOFETCH<BPF_XOR, "^">; 684 } 685 686 def XADDD : ATOMIC_NOFETCH<BPF_ADD, "+">; 687 def XANDD : ATOMIC_NOFETCH<BPF_AND, "&">; 688 def XORD : ATOMIC_NOFETCH<BPF_OR, "|">; 689 def XXORD : ATOMIC_NOFETCH<BPF_XOR, "^">; 690} 691 692// Atomic Fetch-and-<add, and, or, xor> operations 693class XFALU64<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, 694 string OpcStr, PatFrag OpNode> 695 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 696 (outs GPR:$dst), 697 (ins MEMri:$addr, GPR:$val), 698 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", 699 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { 700 bits<4> dst; 701 bits<20> addr; 702 703 let Inst{51-48} = addr{19-16}; // base reg 704 let Inst{55-52} = dst; 705 let Inst{47-32} = addr{15-0}; // offset 706 let Inst{7-4} = Opc.Value; 707 let Inst{3-0} = BPF_FETCH.Value; 708 let BPFClass = BPF_STX; 709} 710 711class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, 712 string OpcStr, PatFrag OpNode> 713 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 714 (outs GPR32:$dst), 715 (ins MEMri:$addr, GPR32:$val), 716 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", 717 [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$val))]> { 718 bits<4> dst; 719 bits<20> addr; 720 721 let Inst{51-48} = addr{19-16}; // base reg 722 let Inst{55-52} = dst; 723 let Inst{47-32} = addr{15-0}; // offset 724 let Inst{7-4} = Opc.Value; 725 let Inst{3-0} = BPF_FETCH.Value; 726 let BPFClass = BPF_STX; 727} 728 729let Constraints = "$dst = $val" in { 730 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 731 def XFADDW32 : XFALU32<BPF_W, BPF_ADD, "u32", "add", atomic_load_add_32>; 732 def XFANDW32 : XFALU32<BPF_W, BPF_AND, "u32", "and", atomic_load_and_32>; 733 def XFORW32 : XFALU32<BPF_W, BPF_OR, "u32", "or", atomic_load_or_32>; 734 def XFXORW32 : XFALU32<BPF_W, BPF_XOR, "u32", "xor", atomic_load_xor_32>; 735 } 736 737 def XFADDD : XFALU64<BPF_DW, BPF_ADD, "u64", "add", atomic_load_add_64>; 738 def XFANDD : XFALU64<BPF_DW, BPF_AND, "u64", "and", atomic_load_and_64>; 739 def XFORD : XFALU64<BPF_DW, BPF_OR, "u64", "or", atomic_load_or_64>; 740 def XFXORD : XFALU64<BPF_DW, BPF_XOR, "u64", "xor", atomic_load_xor_64>; 741} 742 743// atomic_load_sub can be represented as a neg followed 744// by an atomic_load_add. 745def : Pat<(atomic_load_sub_32 ADDRri:$addr, GPR32:$val), 746 (XFADDW32 ADDRri:$addr, (NEG_32 GPR32:$val))>; 747def : Pat<(atomic_load_sub_64 ADDRri:$addr, GPR:$val), 748 (XFADDD ADDRri:$addr, (NEG_64 GPR:$val))>; 749 750// Atomic Exchange 751class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 752 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 753 (outs GPR:$dst), 754 (ins MEMri:$addr, GPR:$val), 755 "$dst = xchg_"#OpcodeStr#"($addr, $val)", 756 [(set GPR:$dst, (OpNode ADDRri:$addr,GPR:$val))]> { 757 bits<4> dst; 758 bits<20> addr; 759 760 let Inst{51-48} = addr{19-16}; // base reg 761 let Inst{55-52} = dst; 762 let Inst{47-32} = addr{15-0}; // offset 763 let Inst{7-4} = BPF_XCHG.Value; 764 let Inst{3-0} = BPF_FETCH.Value; 765 let BPFClass = BPF_STX; 766} 767 768class XCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 769 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 770 (outs GPR32:$dst), 771 (ins MEMri:$addr, GPR32:$val), 772 "$dst = xchg32_"#OpcodeStr#"($addr, $val)", 773 [(set GPR32:$dst, (OpNode ADDRri:$addr,GPR32:$val))]> { 774 bits<4> dst; 775 bits<20> addr; 776 777 let Inst{51-48} = addr{19-16}; // base reg 778 let Inst{55-52} = dst; 779 let Inst{47-32} = addr{15-0}; // offset 780 let Inst{7-4} = BPF_XCHG.Value; 781 let Inst{3-0} = BPF_FETCH.Value; 782 let BPFClass = BPF_STX; 783} 784 785let Constraints = "$dst = $val" in { 786 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 787 def XCHGW32 : XCHG32<BPF_W, "32", atomic_swap_32>; 788 } 789 790 def XCHGD : XCHG<BPF_DW, "64", atomic_swap_64>; 791} 792 793// Compare-And-Exchange 794class CMPXCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 795 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 796 (outs), 797 (ins MEMri:$addr, GPR:$new), 798 "r0 = cmpxchg_"#OpcodeStr#"($addr, r0, $new)", 799 [(set R0, (OpNode ADDRri:$addr, R0, GPR:$new))]> { 800 bits<4> new; 801 bits<20> addr; 802 803 let Inst{51-48} = addr{19-16}; // base reg 804 let Inst{55-52} = new; 805 let Inst{47-32} = addr{15-0}; // offset 806 let Inst{7-4} = BPF_CMPXCHG.Value; 807 let Inst{3-0} = BPF_FETCH.Value; 808 let BPFClass = BPF_STX; 809} 810 811class CMPXCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 812 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 813 (outs), 814 (ins MEMri:$addr, GPR32:$new), 815 "w0 = cmpxchg32_"#OpcodeStr#"($addr, w0, $new)", 816 [(set W0, (OpNode ADDRri:$addr, W0, GPR32:$new))]> { 817 bits<4> new; 818 bits<20> addr; 819 820 let Inst{51-48} = addr{19-16}; // base reg 821 let Inst{55-52} = new; 822 let Inst{47-32} = addr{15-0}; // offset 823 let Inst{7-4} = BPF_CMPXCHG.Value; 824 let Inst{3-0} = BPF_FETCH.Value; 825 let BPFClass = BPF_STX; 826} 827 828let Predicates = [BPFHasALU32], Defs = [W0], Uses = [W0], 829 DecoderNamespace = "BPFALU32" in { 830 def CMPXCHGW32 : CMPXCHG32<BPF_W, "32", atomic_cmp_swap_32>; 831} 832 833let Defs = [R0], Uses = [R0] in { 834 def CMPXCHGD : CMPXCHG<BPF_DW, "64", atomic_cmp_swap_64>; 835} 836 837// bswap16, bswap32, bswap64 838class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern> 839 : TYPE_ALU_JMP<BPF_END.Value, SrcType.Value, 840 (outs GPR:$dst), 841 (ins GPR:$src), 842 "$dst = "#OpcodeStr#" $src", 843 Pattern> { 844 bits<4> dst; 845 846 let Inst{51-48} = dst; 847 let Inst{31-0} = SizeOp; 848 let BPFClass = BPF_ALU; 849} 850 851 852let Constraints = "$dst = $src" in { 853 let Predicates = [BPFIsLittleEndian] in { 854 def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; 855 def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; 856 def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>; 857 } 858 let Predicates = [BPFIsBigEndian] in { 859 def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; 860 def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; 861 def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>; 862 } 863} 864 865let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1, 866 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in { 867class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode> 868 : TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value, 869 (outs), 870 (ins GPR:$skb, i64imm:$imm), 871 "r0 = *("#OpcodeStr#" *)skb[$imm]", 872 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> { 873 bits<32> imm; 874 875 let Inst{31-0} = imm; 876 let BPFClass = BPF_LD; 877} 878 879class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode> 880 : TYPE_LD_ST<BPF_IND.Value, SizeOp.Value, 881 (outs), 882 (ins GPR:$skb, GPR:$val), 883 "r0 = *("#OpcodeStr#" *)skb[$val]", 884 [(set R0, (OpNode GPR:$skb, GPR:$val))]> { 885 bits<4> val; 886 887 let Inst{55-52} = val; 888 let BPFClass = BPF_LD; 889} 890} 891 892def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>; 893def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>; 894def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>; 895 896def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>; 897def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>; 898def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>; 899 900let isCodeGenOnly = 1 in { 901 def MOV_32_64 : ALU_RR<BPF_ALU, BPF_MOV, 902 (outs GPR:$dst), (ins GPR32:$src), 903 "$dst = $src", []>; 904} 905 906def : Pat<(i64 (sext GPR32:$src)), 907 (SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>; 908 909def : Pat<(i64 (zext GPR32:$src)), (MOV_32_64 GPR32:$src)>; 910 911// For i64 -> i32 truncation, use the 32-bit subregister directly. 912def : Pat<(i32 (trunc GPR:$src)), 913 (i32 (EXTRACT_SUBREG GPR:$src, sub_32))>; 914 915// For i32 -> i64 anyext, we don't care about the high bits. 916def : Pat<(i64 (anyext GPR32:$src)), 917 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 918 919class STORE32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 920 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 921 (outs), 922 (ins GPR32:$src, MEMri:$addr), 923 "*("#OpcodeStr#" *)($addr) = $src", 924 Pattern> { 925 bits<4> src; 926 bits<20> addr; 927 928 let Inst{51-48} = addr{19-16}; // base reg 929 let Inst{55-52} = src; 930 let Inst{47-32} = addr{15-0}; // offset 931 let BPFClass = BPF_STX; 932} 933 934class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> 935 : STORE32<Opc, OpcodeStr, [(OpNode i32:$src, ADDRri:$addr)]>; 936 937let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 938 def STW32 : STOREi32<BPF_W, "u32", store>; 939 def STH32 : STOREi32<BPF_H, "u16", truncstorei16>; 940 def STB32 : STOREi32<BPF_B, "u8", truncstorei8>; 941} 942 943class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 944 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 945 (outs GPR32:$dst), 946 (ins MEMri:$addr), 947 "$dst = *("#OpcodeStr#" *)($addr)", 948 Pattern> { 949 bits<4> dst; 950 bits<20> addr; 951 952 let Inst{51-48} = dst; 953 let Inst{55-52} = addr{19-16}; 954 let Inst{47-32} = addr{15-0}; 955 let BPFClass = BPF_LDX; 956} 957 958class LOADi32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 959 : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>; 960 961let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 962 def LDW32 : LOADi32<BPF_W, "u32", load>; 963 def LDH32 : LOADi32<BPF_H, "u16", zextloadi16>; 964 def LDB32 : LOADi32<BPF_B, "u8", zextloadi8>; 965} 966 967let Predicates = [BPFHasALU32] in { 968 def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst), 969 (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 970 def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst), 971 (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 972 def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst), 973 (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 974 def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>; 975 def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>; 976 def : Pat<(i64 (zextloadi8 ADDRri:$src)), 977 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; 978 def : Pat<(i64 (zextloadi16 ADDRri:$src)), 979 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; 980 def : Pat<(i64 (zextloadi32 ADDRri:$src)), 981 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; 982 def : Pat<(i64 (extloadi8 ADDRri:$src)), 983 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; 984 def : Pat<(i64 (extloadi16 ADDRri:$src)), 985 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; 986 def : Pat<(i64 (extloadi32 ADDRri:$src)), 987 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; 988} 989 990let usesCustomInserter = 1, isCodeGenOnly = 1 in { 991 def MEMCPY : Pseudo< 992 (outs), 993 (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops), 994 "#memcpy dst: $dst, src: $src, len: $len, align: $align", 995 [(BPFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>; 996} 997