1//===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the BPF instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "BPFInstrFormats.td" 14 15// Instruction Operands and Patterns 16 17// These are target-independent nodes, but have target-specific formats. 18def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, 19 SDTCisVT<1, iPTR>]>; 20def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 21def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; 23def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>, 24 SDTCisSameAs<0, 4>, 25 SDTCisSameAs<4, 5>]>; 26def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>, 27 SDTCisVT<3, OtherVT>]>; 28def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 29 SDTCisPtrTy<0>]>; 30def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>, 31 SDTCisVT<1, i64>, 32 SDTCisVT<2, i64>, 33 SDTCisVT<3, i64>]>; 34 35def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall, 36 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 37 SDNPVariadic]>; 38def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone, 39 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 40def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart, 41 [SDNPHasChain, SDNPOutGlue]>; 42def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd, 43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 44def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC, 45 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>; 46 47def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>; 48def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>; 49def BPFmemcpy : SDNode<"BPFISD::MEMCPY", SDT_BPFMEMCPY, 50 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 51 SDNPMayStore, SDNPMayLoad]>; 52def BPFIsLittleEndian : Predicate<"CurDAG->getDataLayout().isLittleEndian()">; 53def BPFIsBigEndian : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">; 54def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">; 55def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">; 56 57def brtarget : Operand<OtherVT> { 58 let PrintMethod = "printBrTargetOperand"; 59} 60def calltarget : Operand<i64>; 61 62def u64imm : Operand<i64> { 63 let PrintMethod = "printImm64Operand"; 64} 65 66def i64immSExt32 : PatLeaf<(i64 imm), 67 [{return isInt<32>(N->getSExtValue()); }]>; 68def i32immSExt32 : PatLeaf<(i32 imm), 69 [{return isInt<32>(N->getSExtValue()); }]>; 70 71// Addressing modes. 72def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>; 73def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>; 74 75// Address operands 76def MEMri : Operand<i64> { 77 let PrintMethod = "printMemOperand"; 78 let EncoderMethod = "getMemoryOpValue"; 79 let DecoderMethod = "decodeMemoryOpValue"; 80 let MIOperandInfo = (ops GPR, i16imm); 81} 82 83// Conditional code predicates - used for pattern matching for jump instructions 84def BPF_CC_EQ : PatLeaf<(i64 imm), 85 [{return (N->getZExtValue() == ISD::SETEQ);}]>; 86def BPF_CC_NE : PatLeaf<(i64 imm), 87 [{return (N->getZExtValue() == ISD::SETNE);}]>; 88def BPF_CC_GE : PatLeaf<(i64 imm), 89 [{return (N->getZExtValue() == ISD::SETGE);}]>; 90def BPF_CC_GT : PatLeaf<(i64 imm), 91 [{return (N->getZExtValue() == ISD::SETGT);}]>; 92def BPF_CC_GTU : PatLeaf<(i64 imm), 93 [{return (N->getZExtValue() == ISD::SETUGT);}]>; 94def BPF_CC_GEU : PatLeaf<(i64 imm), 95 [{return (N->getZExtValue() == ISD::SETUGE);}]>; 96def BPF_CC_LE : PatLeaf<(i64 imm), 97 [{return (N->getZExtValue() == ISD::SETLE);}]>; 98def BPF_CC_LT : PatLeaf<(i64 imm), 99 [{return (N->getZExtValue() == ISD::SETLT);}]>; 100def BPF_CC_LTU : PatLeaf<(i64 imm), 101 [{return (N->getZExtValue() == ISD::SETULT);}]>; 102def BPF_CC_LEU : PatLeaf<(i64 imm), 103 [{return (N->getZExtValue() == ISD::SETULE);}]>; 104def BPF_CC_EQ_32 : PatLeaf<(i32 imm), 105 [{return (N->getZExtValue() == ISD::SETEQ);}]>; 106def BPF_CC_NE_32 : PatLeaf<(i32 imm), 107 [{return (N->getZExtValue() == ISD::SETNE);}]>; 108def BPF_CC_GE_32 : PatLeaf<(i32 imm), 109 [{return (N->getZExtValue() == ISD::SETGE);}]>; 110def BPF_CC_GT_32 : PatLeaf<(i32 imm), 111 [{return (N->getZExtValue() == ISD::SETGT);}]>; 112def BPF_CC_GTU_32 : PatLeaf<(i32 imm), 113 [{return (N->getZExtValue() == ISD::SETUGT);}]>; 114def BPF_CC_GEU_32 : PatLeaf<(i32 imm), 115 [{return (N->getZExtValue() == ISD::SETUGE);}]>; 116def BPF_CC_LE_32 : PatLeaf<(i32 imm), 117 [{return (N->getZExtValue() == ISD::SETLE);}]>; 118def BPF_CC_LT_32 : PatLeaf<(i32 imm), 119 [{return (N->getZExtValue() == ISD::SETLT);}]>; 120def BPF_CC_LTU_32 : PatLeaf<(i32 imm), 121 [{return (N->getZExtValue() == ISD::SETULT);}]>; 122def BPF_CC_LEU_32 : PatLeaf<(i32 imm), 123 [{return (N->getZExtValue() == ISD::SETULE);}]>; 124 125// For arithmetic and jump instructions the 8-bit 'code' 126// field is divided into three parts: 127// 128// +----------------+--------+--------------------+ 129// | 4 bits | 1 bit | 3 bits | 130// | operation code | source | instruction class | 131// +----------------+--------+--------------------+ 132// (MSB) (LSB) 133class TYPE_ALU_JMP<bits<4> op, bits<1> srctype, 134 dag outs, dag ins, string asmstr, list<dag> pattern> 135 : InstBPF<outs, ins, asmstr, pattern> { 136 137 let Inst{63-60} = op; 138 let Inst{59} = srctype; 139} 140 141//For load and store instructions the 8-bit 'code' field is divided as: 142// 143// +--------+--------+-------------------+ 144// | 3 bits | 2 bits | 3 bits | 145// | mode | size | instruction class | 146// +--------+--------+-------------------+ 147// (MSB) (LSB) 148class TYPE_LD_ST<bits<3> mode, bits<2> size, 149 dag outs, dag ins, string asmstr, list<dag> pattern> 150 : InstBPF<outs, ins, asmstr, pattern> { 151 152 let Inst{63-61} = mode; 153 let Inst{60-59} = size; 154} 155 156// jump instructions 157class JMP_RR<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 158 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, 159 (outs), 160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst), 161 "if $dst "#OpcodeStr#" $src goto $BrDst", 162 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> { 163 bits<4> dst; 164 bits<4> src; 165 bits<16> BrDst; 166 167 let Inst{55-52} = src; 168 let Inst{51-48} = dst; 169 let Inst{47-32} = BrDst; 170 let BPFClass = BPF_JMP; 171} 172 173class JMP_RI<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 174 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 175 (outs), 176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst), 177 "if $dst "#OpcodeStr#" $imm goto $BrDst", 178 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> { 179 bits<4> dst; 180 bits<16> BrDst; 181 bits<32> imm; 182 183 let Inst{51-48} = dst; 184 let Inst{47-32} = BrDst; 185 let Inst{31-0} = imm; 186 let BPFClass = BPF_JMP; 187} 188 189class JMP_RR_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 190 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, 191 (outs), 192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst), 193 "if $dst "#OpcodeStr#" $src goto $BrDst", 194 [(BPFbrcc i32:$dst, i32:$src, Cond, bb:$BrDst)]> { 195 bits<4> dst; 196 bits<4> src; 197 bits<16> BrDst; 198 199 let Inst{55-52} = src; 200 let Inst{51-48} = dst; 201 let Inst{47-32} = BrDst; 202 let BPFClass = BPF_JMP32; 203} 204 205class JMP_RI_32<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond> 206 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 207 (outs), 208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst), 209 "if $dst "#OpcodeStr#" $imm goto $BrDst", 210 [(BPFbrcc i32:$dst, i32immSExt32:$imm, Cond, bb:$BrDst)]> { 211 bits<4> dst; 212 bits<16> BrDst; 213 bits<32> imm; 214 215 let Inst{51-48} = dst; 216 let Inst{47-32} = BrDst; 217 let Inst{31-0} = imm; 218 let BPFClass = BPF_JMP32; 219} 220 221multiclass J<BPFJumpOp Opc, string OpcodeStr, PatLeaf Cond, PatLeaf Cond32> { 222 def _rr : JMP_RR<Opc, OpcodeStr, Cond>; 223 def _ri : JMP_RI<Opc, OpcodeStr, Cond>; 224 def _rr_32 : JMP_RR_32<Opc, OpcodeStr, Cond32>; 225 def _ri_32 : JMP_RI_32<Opc, OpcodeStr, Cond32>; 226} 227 228let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in { 229// cmp+goto instructions 230defm JEQ : J<BPF_JEQ, "==", BPF_CC_EQ, BPF_CC_EQ_32>; 231defm JUGT : J<BPF_JGT, ">", BPF_CC_GTU, BPF_CC_GTU_32>; 232defm JUGE : J<BPF_JGE, ">=", BPF_CC_GEU, BPF_CC_GEU_32>; 233defm JNE : J<BPF_JNE, "!=", BPF_CC_NE, BPF_CC_NE_32>; 234defm JSGT : J<BPF_JSGT, "s>", BPF_CC_GT, BPF_CC_GT_32>; 235defm JSGE : J<BPF_JSGE, "s>=", BPF_CC_GE, BPF_CC_GE_32>; 236defm JULT : J<BPF_JLT, "<", BPF_CC_LTU, BPF_CC_LTU_32>; 237defm JULE : J<BPF_JLE, "<=", BPF_CC_LEU, BPF_CC_LEU_32>; 238defm JSLT : J<BPF_JSLT, "s<", BPF_CC_LT, BPF_CC_LT_32>; 239defm JSLE : J<BPF_JSLE, "s<=", BPF_CC_LE, BPF_CC_LE_32>; 240} 241 242// ALU instructions 243class ALU_RI<BPFOpClass Class, BPFArithOp Opc, 244 dag outs, dag ins, string asmstr, list<dag> pattern> 245 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, outs, ins, asmstr, pattern> { 246 bits<4> dst; 247 bits<32> imm; 248 249 let Inst{51-48} = dst; 250 let Inst{31-0} = imm; 251 let BPFClass = Class; 252} 253 254class ALU_RR<BPFOpClass Class, BPFArithOp Opc, 255 dag outs, dag ins, string asmstr, list<dag> pattern> 256 : TYPE_ALU_JMP<Opc.Value, BPF_X.Value, outs, ins, asmstr, pattern> { 257 bits<4> dst; 258 bits<4> src; 259 260 let Inst{55-52} = src; 261 let Inst{51-48} = dst; 262 let BPFClass = Class; 263} 264 265multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> { 266 def _rr : ALU_RR<BPF_ALU64, Opc, 267 (outs GPR:$dst), 268 (ins GPR:$src2, GPR:$src), 269 "$dst "#OpcodeStr#" $src", 270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>; 271 def _ri : ALU_RI<BPF_ALU64, Opc, 272 (outs GPR:$dst), 273 (ins GPR:$src2, i64imm:$imm), 274 "$dst "#OpcodeStr#" $imm", 275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>; 276 def _rr_32 : ALU_RR<BPF_ALU, Opc, 277 (outs GPR32:$dst), 278 (ins GPR32:$src2, GPR32:$src), 279 "$dst "#OpcodeStr#" $src", 280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>; 281 def _ri_32 : ALU_RI<BPF_ALU, Opc, 282 (outs GPR32:$dst), 283 (ins GPR32:$src2, i32imm:$imm), 284 "$dst "#OpcodeStr#" $imm", 285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>; 286} 287 288let Constraints = "$dst = $src2" in { 289let isAsCheapAsAMove = 1 in { 290 defm ADD : ALU<BPF_ADD, "+=", add>; 291 defm SUB : ALU<BPF_SUB, "-=", sub>; 292 defm OR : ALU<BPF_OR, "|=", or>; 293 defm AND : ALU<BPF_AND, "&=", and>; 294 defm SLL : ALU<BPF_LSH, "<<=", shl>; 295 defm SRL : ALU<BPF_RSH, ">>=", srl>; 296 defm XOR : ALU<BPF_XOR, "^=", xor>; 297 defm SRA : ALU<BPF_ARSH, "s>>=", sra>; 298} 299 defm MUL : ALU<BPF_MUL, "*=", mul>; 300 defm DIV : ALU<BPF_DIV, "/=", udiv>; 301} 302 303class NEG_RR<BPFOpClass Class, BPFArithOp Opc, 304 dag outs, dag ins, string asmstr, list<dag> pattern> 305 : TYPE_ALU_JMP<Opc.Value, 0, outs, ins, asmstr, pattern> { 306 bits<4> dst; 307 308 let Inst{51-48} = dst; 309 let BPFClass = Class; 310} 311 312let Constraints = "$dst = $src", isAsCheapAsAMove = 1 in { 313 def NEG_64: NEG_RR<BPF_ALU64, BPF_NEG, (outs GPR:$dst), (ins GPR:$src), 314 "$dst = -$src", 315 [(set GPR:$dst, (ineg i64:$src))]>; 316 def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src), 317 "$dst = -$src", 318 [(set GPR32:$dst, (ineg i32:$src))]>; 319} 320 321class LD_IMM64<bits<4> Pseudo, string OpcodeStr> 322 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 323 (outs GPR:$dst), 324 (ins u64imm:$imm), 325 "$dst "#OpcodeStr#" ${imm} ll", 326 [(set GPR:$dst, (i64 imm:$imm))]> { 327 328 bits<4> dst; 329 bits<64> imm; 330 331 let Inst{51-48} = dst; 332 let Inst{55-52} = Pseudo; 333 let Inst{47-32} = 0; 334 let Inst{31-0} = imm{31-0}; 335 let BPFClass = BPF_LD; 336} 337 338let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 339def LD_imm64 : LD_IMM64<0, "=">; 340def MOV_rr : ALU_RR<BPF_ALU64, BPF_MOV, 341 (outs GPR:$dst), 342 (ins GPR:$src), 343 "$dst = $src", 344 []>; 345def MOV_ri : ALU_RI<BPF_ALU64, BPF_MOV, 346 (outs GPR:$dst), 347 (ins i64imm:$imm), 348 "$dst = $imm", 349 [(set GPR:$dst, (i64 i64immSExt32:$imm))]>; 350def MOV_rr_32 : ALU_RR<BPF_ALU, BPF_MOV, 351 (outs GPR32:$dst), 352 (ins GPR32:$src), 353 "$dst = $src", 354 []>; 355def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV, 356 (outs GPR32:$dst), 357 (ins i32imm:$imm), 358 "$dst = $imm", 359 [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>; 360} 361 362def FI_ri 363 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 364 (outs GPR:$dst), 365 (ins MEMri:$addr), 366 "lea\t$dst, $addr", 367 [(set i64:$dst, FIri:$addr)]> { 368 // This is a tentative instruction, and will be replaced 369 // with MOV_rr and ADD_ri in PEI phase 370 let Inst{51-48} = 0; 371 let Inst{55-52} = 2; 372 let Inst{47-32} = 0; 373 let Inst{31-0} = 0; 374 let BPFClass = BPF_LD; 375} 376 377def LD_pseudo 378 : TYPE_LD_ST<BPF_IMM.Value, BPF_DW.Value, 379 (outs GPR:$dst), 380 (ins i64imm:$pseudo, u64imm:$imm), 381 "ld_pseudo\t$dst, $pseudo, $imm", 382 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> { 383 384 bits<4> dst; 385 bits<64> imm; 386 bits<4> pseudo; 387 388 let Inst{51-48} = dst; 389 let Inst{55-52} = pseudo; 390 let Inst{47-32} = 0; 391 let Inst{31-0} = imm{31-0}; 392 let BPFClass = BPF_LD; 393} 394 395// STORE instructions 396class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 397 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 398 (outs), 399 (ins GPR:$src, MEMri:$addr), 400 "*("#OpcodeStr#" *)($addr) = $src", 401 Pattern> { 402 bits<4> src; 403 bits<20> addr; 404 405 let Inst{51-48} = addr{19-16}; // base reg 406 let Inst{55-52} = src; 407 let Inst{47-32} = addr{15-0}; // offset 408 let BPFClass = BPF_STX; 409} 410 411class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> 412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>; 413 414let Predicates = [BPFNoALU32] in { 415 def STW : STOREi64<BPF_W, "u32", truncstorei32>; 416 def STH : STOREi64<BPF_H, "u16", truncstorei16>; 417 def STB : STOREi64<BPF_B, "u8", truncstorei8>; 418} 419def STD : STOREi64<BPF_DW, "u64", store>; 420 421// LOAD instructions 422class LOAD<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 423 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 424 (outs GPR:$dst), 425 (ins MEMri:$addr), 426 "$dst = *("#OpcodeStr#" *)($addr)", 427 Pattern> { 428 bits<4> dst; 429 bits<20> addr; 430 431 let Inst{51-48} = dst; 432 let Inst{55-52} = addr{19-16}; 433 let Inst{47-32} = addr{15-0}; 434 let BPFClass = BPF_LDX; 435} 436 437class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 438 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>; 439 440let isCodeGenOnly = 1 in { 441 def CORE_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value, 442 (outs GPR:$dst), 443 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 444 "$dst = core_mem($opcode, $src, $offset)", 445 []>; 446 def CORE_ALU32_MEM : TYPE_LD_ST<BPF_MEM.Value, BPF_W.Value, 447 (outs GPR32:$dst), 448 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 449 "$dst = core_alu32_mem($opcode, $src, $offset)", 450 []>; 451 let Constraints = "$dst = $src" in { 452 def CORE_SHIFT : ALU_RR<BPF_ALU64, BPF_LSH, 453 (outs GPR:$dst), 454 (ins u64imm:$opcode, GPR:$src, u64imm:$offset), 455 "$dst = core_shift($opcode, $src, $offset)", 456 []>; 457 } 458} 459 460let Predicates = [BPFNoALU32] in { 461 def LDW : LOADi64<BPF_W, "u32", zextloadi32>; 462 def LDH : LOADi64<BPF_H, "u16", zextloadi16>; 463 def LDB : LOADi64<BPF_B, "u8", zextloadi8>; 464} 465 466def LDD : LOADi64<BPF_DW, "u64", load>; 467 468class BRANCH<BPFJumpOp Opc, string OpcodeStr, list<dag> Pattern> 469 : TYPE_ALU_JMP<Opc.Value, BPF_K.Value, 470 (outs), 471 (ins brtarget:$BrDst), 472 !strconcat(OpcodeStr, " $BrDst"), 473 Pattern> { 474 bits<16> BrDst; 475 476 let Inst{47-32} = BrDst; 477 let BPFClass = BPF_JMP; 478} 479 480class CALL<string OpcodeStr> 481 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_K.Value, 482 (outs), 483 (ins calltarget:$BrDst), 484 !strconcat(OpcodeStr, " $BrDst"), 485 []> { 486 bits<32> BrDst; 487 488 let Inst{31-0} = BrDst; 489 let BPFClass = BPF_JMP; 490} 491 492class CALLX<string OpcodeStr> 493 : TYPE_ALU_JMP<BPF_CALL.Value, BPF_X.Value, 494 (outs), 495 (ins GPR:$BrDst), 496 !strconcat(OpcodeStr, " $BrDst"), 497 []> { 498 bits<32> BrDst; 499 500 let Inst{31-0} = BrDst; 501 let BPFClass = BPF_JMP; 502} 503 504// Jump always 505let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in { 506 def JMP : BRANCH<BPF_JA, "goto", [(br bb:$BrDst)]>; 507} 508 509// Jump and link 510let isCall=1, hasDelaySlot=0, Uses = [R11], 511 // Potentially clobbered registers 512 Defs = [R0, R1, R2, R3, R4, R5] in { 513 def JAL : CALL<"call">; 514 def JALX : CALLX<"callx">; 515} 516 517class NOP_I<string OpcodeStr> 518 : TYPE_ALU_JMP<BPF_MOV.Value, BPF_X.Value, 519 (outs), 520 (ins i32imm:$imm), 521 !strconcat(OpcodeStr, "\t$imm"), 522 []> { 523 // mov r0, r0 == nop 524 let Inst{55-52} = 0; 525 let Inst{51-48} = 0; 526 let BPFClass = BPF_ALU64; 527} 528 529let hasSideEffects = 0, isCodeGenOnly = 1 in 530 def NOP : NOP_I<"nop">; 531 532class RET<string OpcodeStr> 533 : TYPE_ALU_JMP<BPF_EXIT.Value, BPF_K.Value, 534 (outs), 535 (ins), 536 !strconcat(OpcodeStr, ""), 537 [(BPFretflag)]> { 538 let Inst{31-0} = 0; 539 let BPFClass = BPF_JMP; 540} 541 542let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1, 543 isNotDuplicable = 1 in { 544 def RET : RET<"exit">; 545} 546 547// ADJCALLSTACKDOWN/UP pseudo insns 548let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in { 549def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 550 "#ADJCALLSTACKDOWN $amt1 $amt2", 551 [(BPFcallseq_start timm:$amt1, timm:$amt2)]>; 552def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 553 "#ADJCALLSTACKUP $amt1 $amt2", 554 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>; 555} 556 557let usesCustomInserter = 1, isCodeGenOnly = 1 in { 558 def Select : Pseudo<(outs GPR:$dst), 559 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), 560 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 561 [(set i64:$dst, 562 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>; 563 def Select_Ri : Pseudo<(outs GPR:$dst), 564 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR:$src, GPR:$src2), 565 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 566 [(set i64:$dst, 567 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i64:$src, i64:$src2))]>; 568 def Select_64_32 : Pseudo<(outs GPR32:$dst), 569 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), 570 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 571 [(set i32:$dst, 572 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i32:$src, i32:$src2))]>; 573 def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst), 574 (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2), 575 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 576 [(set i32:$dst, 577 (BPFselectcc i64:$lhs, (i64immSExt32:$rhs), (i64 imm:$imm), i32:$src, i32:$src2))]>; 578 def Select_32 : Pseudo<(outs GPR32:$dst), 579 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), 580 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 581 [(set i32:$dst, 582 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i32:$src, i32:$src2))]>; 583 def Select_Ri_32 : Pseudo<(outs GPR32:$dst), 584 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2), 585 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 586 [(set i32:$dst, 587 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i32:$src, i32:$src2))]>; 588 def Select_32_64 : Pseudo<(outs GPR:$dst), 589 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), 590 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 591 [(set i64:$dst, 592 (BPFselectcc i32:$lhs, i32:$rhs, (i32 imm:$imm), i64:$src, i64:$src2))]>; 593 def Select_Ri_32_64 : Pseudo<(outs GPR:$dst), 594 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR:$src, GPR:$src2), 595 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", 596 [(set i64:$dst, 597 (BPFselectcc i32:$lhs, (i32immSExt32:$rhs), (i32 imm:$imm), i64:$src, i64:$src2))]>; 598} 599 600// load 64-bit global addr into register 601def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>; 602 603// 0xffffFFFF doesn't fit into simm32, optimize common case 604def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)), 605 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>; 606 607// Calls 608def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>; 609def : Pat<(BPFcall texternalsym:$dst), (JAL texternalsym:$dst)>; 610def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>; 611def : Pat<(BPFcall GPR:$dst), (JALX GPR:$dst)>; 612 613// Loads 614let Predicates = [BPFNoALU32] in { 615 def : Pat<(i64 (extloadi8 ADDRri:$src)), (i64 (LDB ADDRri:$src))>; 616 def : Pat<(i64 (extloadi16 ADDRri:$src)), (i64 (LDH ADDRri:$src))>; 617 def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>; 618} 619 620// Atomic XADD for BPFNoALU32 621class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 622 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 623 (outs GPR:$dst), 624 (ins MEMri:$addr, GPR:$val), 625 "lock *("#OpcodeStr#" *)($addr) += $val", 626 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { 627 bits<4> dst; 628 bits<20> addr; 629 630 let Inst{51-48} = addr{19-16}; // base reg 631 let Inst{55-52} = dst; 632 let Inst{47-32} = addr{15-0}; // offset 633 let Inst{7-4} = BPF_ADD.Value; 634 let BPFClass = BPF_STX; 635} 636 637let Constraints = "$dst = $val" in { 638 let Predicates = [BPFNoALU32] in { 639 def XADDW : XADD<BPF_W, "u32", atomic_load_add_32>; 640 } 641} 642 643// Atomic add, and, or, xor 644class ATOMIC_NOFETCH<BPFArithOp Opc, string Opstr> 645 : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_DW.Value, 646 (outs GPR:$dst), 647 (ins MEMri:$addr, GPR:$val), 648 "lock *(u64 *)($addr) " #Opstr# "= $val", 649 []> { 650 bits<4> dst; 651 bits<20> addr; 652 653 let Inst{51-48} = addr{19-16}; // base reg 654 let Inst{55-52} = dst; 655 let Inst{47-32} = addr{15-0}; // offset 656 let Inst{7-4} = Opc.Value; 657 let BPFClass = BPF_STX; 658} 659 660class ATOMIC32_NOFETCH<BPFArithOp Opc, string Opstr> 661 : TYPE_LD_ST<BPF_ATOMIC.Value, BPF_W.Value, 662 (outs GPR32:$dst), 663 (ins MEMri:$addr, GPR32:$val), 664 "lock *(u32 *)($addr) " #Opstr# "= $val", 665 []> { 666 bits<4> dst; 667 bits<20> addr; 668 669 let Inst{51-48} = addr{19-16}; // base reg 670 let Inst{55-52} = dst; 671 let Inst{47-32} = addr{15-0}; // offset 672 let Inst{7-4} = Opc.Value; 673 let BPFClass = BPF_STX; 674} 675 676let Constraints = "$dst = $val" in { 677 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 678 def XADDW32 : ATOMIC32_NOFETCH<BPF_ADD, "+">; 679 def XANDW32 : ATOMIC32_NOFETCH<BPF_AND, "&">; 680 def XORW32 : ATOMIC32_NOFETCH<BPF_OR, "|">; 681 def XXORW32 : ATOMIC32_NOFETCH<BPF_XOR, "^">; 682 } 683 684 def XADDD : ATOMIC_NOFETCH<BPF_ADD, "+">; 685 def XANDD : ATOMIC_NOFETCH<BPF_AND, "&">; 686 def XORD : ATOMIC_NOFETCH<BPF_OR, "|">; 687 def XXORD : ATOMIC_NOFETCH<BPF_XOR, "^">; 688} 689 690// Atomic Fetch-and-<add, and, or, xor> operations 691class XFALU64<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, 692 string OpcStr, PatFrag OpNode> 693 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 694 (outs GPR:$dst), 695 (ins MEMri:$addr, GPR:$val), 696 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", 697 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> { 698 bits<4> dst; 699 bits<20> addr; 700 701 let Inst{51-48} = addr{19-16}; // base reg 702 let Inst{55-52} = dst; 703 let Inst{47-32} = addr{15-0}; // offset 704 let Inst{7-4} = Opc.Value; 705 let Inst{3-0} = BPF_FETCH.Value; 706 let BPFClass = BPF_STX; 707} 708 709class XFALU32<BPFWidthModifer SizeOp, BPFArithOp Opc, string OpcodeStr, 710 string OpcStr, PatFrag OpNode> 711 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 712 (outs GPR32:$dst), 713 (ins MEMri:$addr, GPR32:$val), 714 "$dst = atomic_fetch_"#OpcStr#"(("#OpcodeStr#" *)($addr), $val)", 715 [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$val))]> { 716 bits<4> dst; 717 bits<20> addr; 718 719 let Inst{51-48} = addr{19-16}; // base reg 720 let Inst{55-52} = dst; 721 let Inst{47-32} = addr{15-0}; // offset 722 let Inst{7-4} = Opc.Value; 723 let Inst{3-0} = BPF_FETCH.Value; 724 let BPFClass = BPF_STX; 725} 726 727let Constraints = "$dst = $val" in { 728 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 729 def XFADDW32 : XFALU32<BPF_W, BPF_ADD, "u32", "add", atomic_load_add_32>; 730 def XFANDW32 : XFALU32<BPF_W, BPF_AND, "u32", "and", atomic_load_and_32>; 731 def XFORW32 : XFALU32<BPF_W, BPF_OR, "u32", "or", atomic_load_or_32>; 732 def XFXORW32 : XFALU32<BPF_W, BPF_XOR, "u32", "xor", atomic_load_xor_32>; 733 } 734 735 def XFADDD : XFALU64<BPF_DW, BPF_ADD, "u64", "add", atomic_load_add_64>; 736 def XFANDD : XFALU64<BPF_DW, BPF_AND, "u64", "and", atomic_load_and_64>; 737 def XFORD : XFALU64<BPF_DW, BPF_OR, "u64", "or", atomic_load_or_64>; 738 def XFXORD : XFALU64<BPF_DW, BPF_XOR, "u64", "xor", atomic_load_xor_64>; 739} 740 741// atomic_load_sub can be represented as a neg followed 742// by an atomic_load_add. 743def : Pat<(atomic_load_sub_32 ADDRri:$addr, GPR32:$val), 744 (XFADDW32 ADDRri:$addr, (NEG_32 GPR32:$val))>; 745def : Pat<(atomic_load_sub_64 ADDRri:$addr, GPR:$val), 746 (XFADDD ADDRri:$addr, (NEG_64 GPR:$val))>; 747 748// Atomic Exchange 749class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 750 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 751 (outs GPR:$dst), 752 (ins MEMri:$addr, GPR:$val), 753 "$dst = xchg_"#OpcodeStr#"($addr, $val)", 754 [(set GPR:$dst, (OpNode ADDRri:$addr,GPR:$val))]> { 755 bits<4> dst; 756 bits<20> addr; 757 758 let Inst{51-48} = addr{19-16}; // base reg 759 let Inst{55-52} = dst; 760 let Inst{47-32} = addr{15-0}; // offset 761 let Inst{7-4} = BPF_XCHG.Value; 762 let Inst{3-0} = BPF_FETCH.Value; 763 let BPFClass = BPF_STX; 764} 765 766class XCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 767 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 768 (outs GPR32:$dst), 769 (ins MEMri:$addr, GPR32:$val), 770 "$dst = xchg32_"#OpcodeStr#"($addr, $val)", 771 [(set GPR32:$dst, (OpNode ADDRri:$addr,GPR32:$val))]> { 772 bits<4> dst; 773 bits<20> addr; 774 775 let Inst{51-48} = addr{19-16}; // base reg 776 let Inst{55-52} = dst; 777 let Inst{47-32} = addr{15-0}; // offset 778 let Inst{7-4} = BPF_XCHG.Value; 779 let Inst{3-0} = BPF_FETCH.Value; 780 let BPFClass = BPF_STX; 781} 782 783let Constraints = "$dst = $val" in { 784 let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 785 def XCHGW32 : XCHG32<BPF_W, "32", atomic_swap_32>; 786 } 787 788 def XCHGD : XCHG<BPF_DW, "64", atomic_swap_64>; 789} 790 791// Compare-And-Exchange 792class CMPXCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 793 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 794 (outs), 795 (ins MEMri:$addr, GPR:$new), 796 "r0 = cmpxchg_"#OpcodeStr#"($addr, r0, $new)", 797 [(set R0, (OpNode ADDRri:$addr, R0, GPR:$new))]> { 798 bits<4> new; 799 bits<20> addr; 800 801 let Inst{51-48} = addr{19-16}; // base reg 802 let Inst{55-52} = new; 803 let Inst{47-32} = addr{15-0}; // offset 804 let Inst{7-4} = BPF_CMPXCHG.Value; 805 let Inst{3-0} = BPF_FETCH.Value; 806 let BPFClass = BPF_STX; 807} 808 809class CMPXCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 810 : TYPE_LD_ST<BPF_ATOMIC.Value, SizeOp.Value, 811 (outs), 812 (ins MEMri:$addr, GPR32:$new), 813 "w0 = cmpxchg32_"#OpcodeStr#"($addr, w0, $new)", 814 [(set W0, (OpNode ADDRri:$addr, W0, GPR32:$new))]> { 815 bits<4> new; 816 bits<20> addr; 817 818 let Inst{51-48} = addr{19-16}; // base reg 819 let Inst{55-52} = new; 820 let Inst{47-32} = addr{15-0}; // offset 821 let Inst{7-4} = BPF_CMPXCHG.Value; 822 let Inst{3-0} = BPF_FETCH.Value; 823 let BPFClass = BPF_STX; 824} 825 826let Predicates = [BPFHasALU32], Defs = [W0], Uses = [W0], 827 DecoderNamespace = "BPFALU32" in { 828 def CMPXCHGW32 : CMPXCHG32<BPF_W, "32", atomic_cmp_swap_32>; 829} 830 831let Defs = [R0], Uses = [R0] in { 832 def CMPXCHGD : CMPXCHG<BPF_DW, "64", atomic_cmp_swap_64>; 833} 834 835// bswap16, bswap32, bswap64 836class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern> 837 : TYPE_ALU_JMP<BPF_END.Value, SrcType.Value, 838 (outs GPR:$dst), 839 (ins GPR:$src), 840 "$dst = "#OpcodeStr#" $src", 841 Pattern> { 842 bits<4> dst; 843 844 let Inst{51-48} = dst; 845 let Inst{31-0} = SizeOp; 846 let BPFClass = BPF_ALU; 847} 848 849 850let Constraints = "$dst = $src" in { 851 let Predicates = [BPFIsLittleEndian] in { 852 def BE16 : BSWAP<16, "be16", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; 853 def BE32 : BSWAP<32, "be32", BPF_TO_BE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; 854 def BE64 : BSWAP<64, "be64", BPF_TO_BE, [(set GPR:$dst, (bswap GPR:$src))]>; 855 } 856 let Predicates = [BPFIsBigEndian] in { 857 def LE16 : BSWAP<16, "le16", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>; 858 def LE32 : BSWAP<32, "le32", BPF_TO_LE, [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>; 859 def LE64 : BSWAP<64, "le64", BPF_TO_LE, [(set GPR:$dst, (bswap GPR:$src))]>; 860 } 861} 862 863let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1, 864 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in { 865class LOAD_ABS<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode> 866 : TYPE_LD_ST<BPF_ABS.Value, SizeOp.Value, 867 (outs), 868 (ins GPR:$skb, i64imm:$imm), 869 "r0 = *("#OpcodeStr#" *)skb[$imm]", 870 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> { 871 bits<32> imm; 872 873 let Inst{31-0} = imm; 874 let BPFClass = BPF_LD; 875} 876 877class LOAD_IND<BPFWidthModifer SizeOp, string OpcodeStr, Intrinsic OpNode> 878 : TYPE_LD_ST<BPF_IND.Value, SizeOp.Value, 879 (outs), 880 (ins GPR:$skb, GPR:$val), 881 "r0 = *("#OpcodeStr#" *)skb[$val]", 882 [(set R0, (OpNode GPR:$skb, GPR:$val))]> { 883 bits<4> val; 884 885 let Inst{55-52} = val; 886 let BPFClass = BPF_LD; 887} 888} 889 890def LD_ABS_B : LOAD_ABS<BPF_B, "u8", int_bpf_load_byte>; 891def LD_ABS_H : LOAD_ABS<BPF_H, "u16", int_bpf_load_half>; 892def LD_ABS_W : LOAD_ABS<BPF_W, "u32", int_bpf_load_word>; 893 894def LD_IND_B : LOAD_IND<BPF_B, "u8", int_bpf_load_byte>; 895def LD_IND_H : LOAD_IND<BPF_H, "u16", int_bpf_load_half>; 896def LD_IND_W : LOAD_IND<BPF_W, "u32", int_bpf_load_word>; 897 898let isCodeGenOnly = 1 in { 899 def MOV_32_64 : ALU_RR<BPF_ALU, BPF_MOV, 900 (outs GPR:$dst), (ins GPR32:$src), 901 "$dst = $src", []>; 902} 903 904def : Pat<(i64 (sext GPR32:$src)), 905 (SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>; 906 907def : Pat<(i64 (zext GPR32:$src)), (MOV_32_64 GPR32:$src)>; 908 909// For i64 -> i32 truncation, use the 32-bit subregister directly. 910def : Pat<(i32 (trunc GPR:$src)), 911 (i32 (EXTRACT_SUBREG GPR:$src, sub_32))>; 912 913// For i32 -> i64 anyext, we don't care about the high bits. 914def : Pat<(i64 (anyext GPR32:$src)), 915 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>; 916 917class STORE32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 918 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 919 (outs), 920 (ins GPR32:$src, MEMri:$addr), 921 "*("#OpcodeStr#" *)($addr) = $src", 922 Pattern> { 923 bits<4> src; 924 bits<20> addr; 925 926 let Inst{51-48} = addr{19-16}; // base reg 927 let Inst{55-52} = src; 928 let Inst{47-32} = addr{15-0}; // offset 929 let BPFClass = BPF_STX; 930} 931 932class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode> 933 : STORE32<Opc, OpcodeStr, [(OpNode i32:$src, ADDRri:$addr)]>; 934 935let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 936 def STW32 : STOREi32<BPF_W, "u32", store>; 937 def STH32 : STOREi32<BPF_H, "u16", truncstorei16>; 938 def STB32 : STOREi32<BPF_B, "u8", truncstorei8>; 939} 940 941class LOAD32<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 942 : TYPE_LD_ST<BPF_MEM.Value, SizeOp.Value, 943 (outs GPR32:$dst), 944 (ins MEMri:$addr), 945 "$dst = *("#OpcodeStr#" *)($addr)", 946 Pattern> { 947 bits<4> dst; 948 bits<20> addr; 949 950 let Inst{51-48} = dst; 951 let Inst{55-52} = addr{19-16}; 952 let Inst{47-32} = addr{15-0}; 953 let BPFClass = BPF_LDX; 954} 955 956class LOADi32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode> 957 : LOAD32<SizeOp, OpcodeStr, [(set i32:$dst, (OpNode ADDRri:$addr))]>; 958 959let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in { 960 def LDW32 : LOADi32<BPF_W, "u32", load>; 961 def LDH32 : LOADi32<BPF_H, "u16", zextloadi16>; 962 def LDB32 : LOADi32<BPF_B, "u8", zextloadi8>; 963} 964 965let Predicates = [BPFHasALU32] in { 966 def : Pat<(truncstorei8 GPR:$src, ADDRri:$dst), 967 (STB32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 968 def : Pat<(truncstorei16 GPR:$src, ADDRri:$dst), 969 (STH32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 970 def : Pat<(truncstorei32 GPR:$src, ADDRri:$dst), 971 (STW32 (EXTRACT_SUBREG GPR:$src, sub_32), ADDRri:$dst)>; 972 def : Pat<(i32 (extloadi8 ADDRri:$src)), (i32 (LDB32 ADDRri:$src))>; 973 def : Pat<(i32 (extloadi16 ADDRri:$src)), (i32 (LDH32 ADDRri:$src))>; 974 def : Pat<(i64 (zextloadi8 ADDRri:$src)), 975 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; 976 def : Pat<(i64 (zextloadi16 ADDRri:$src)), 977 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; 978 def : Pat<(i64 (zextloadi32 ADDRri:$src)), 979 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; 980 def : Pat<(i64 (extloadi8 ADDRri:$src)), 981 (SUBREG_TO_REG (i64 0), (LDB32 ADDRri:$src), sub_32)>; 982 def : Pat<(i64 (extloadi16 ADDRri:$src)), 983 (SUBREG_TO_REG (i64 0), (LDH32 ADDRri:$src), sub_32)>; 984 def : Pat<(i64 (extloadi32 ADDRri:$src)), 985 (SUBREG_TO_REG (i64 0), (LDW32 ADDRri:$src), sub_32)>; 986} 987 988let usesCustomInserter = 1, isCodeGenOnly = 1 in { 989 def MEMCPY : Pseudo< 990 (outs), 991 (ins GPR:$dst, GPR:$src, i64imm:$len, i64imm:$align, variable_ops), 992 "#memcpy dst: $dst, src: $src, len: $len, align: $align", 993 [(BPFmemcpy GPR:$dst, GPR:$src, imm:$len, imm:$align)]>; 994} 995