1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that BPF uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "BPFISelLowering.h" 15 #include "BPF.h" 16 #include "BPFSubtarget.h" 17 #include "BPFTargetMachine.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/SelectionDAGISel.h" 24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/IR/DiagnosticInfo.h" 27 #include "llvm/IR/DiagnosticPrinter.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/raw_ostream.h" 31 using namespace llvm; 32 33 #define DEBUG_TYPE "bpf-lower" 34 35 static cl::opt<bool> BPFExpandMemcpyInOrder("bpf-expand-memcpy-in-order", 36 cl::Hidden, cl::init(false), 37 cl::desc("Expand memcpy into load/store pairs in order")); 38 39 static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) { 40 MachineFunction &MF = DAG.getMachineFunction(); 41 DAG.getContext()->diagnose( 42 DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc())); 43 } 44 45 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, 46 SDValue Val) { 47 MachineFunction &MF = DAG.getMachineFunction(); 48 std::string Str; 49 raw_string_ostream OS(Str); 50 OS << Msg; 51 Val->print(OS); 52 OS.flush(); 53 DAG.getContext()->diagnose( 54 DiagnosticInfoUnsupported(MF.getFunction(), Str, DL.getDebugLoc())); 55 } 56 57 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM, 58 const BPFSubtarget &STI) 59 : TargetLowering(TM) { 60 61 // Set up the register classes. 62 addRegisterClass(MVT::i64, &BPF::GPRRegClass); 63 if (STI.getHasAlu32()) 64 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); 65 66 // Compute derived properties from the register classes 67 computeRegisterProperties(STI.getRegisterInfo()); 68 69 setStackPointerRegisterToSaveRestore(BPF::R11); 70 71 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 72 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 73 setOperationAction(ISD::BRIND, MVT::Other, Expand); 74 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 75 76 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 77 78 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 79 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 80 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 81 82 for (auto VT : { MVT::i32, MVT::i64 }) { 83 if (VT == MVT::i32 && !STI.getHasAlu32()) 84 continue; 85 86 setOperationAction(ISD::SDIVREM, VT, Expand); 87 setOperationAction(ISD::UDIVREM, VT, Expand); 88 setOperationAction(ISD::SREM, VT, Expand); 89 setOperationAction(ISD::UREM, VT, Expand); 90 setOperationAction(ISD::MULHU, VT, Expand); 91 setOperationAction(ISD::MULHS, VT, Expand); 92 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 93 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 94 setOperationAction(ISD::ROTR, VT, Expand); 95 setOperationAction(ISD::ROTL, VT, Expand); 96 setOperationAction(ISD::SHL_PARTS, VT, Expand); 97 setOperationAction(ISD::SRL_PARTS, VT, Expand); 98 setOperationAction(ISD::SRA_PARTS, VT, Expand); 99 setOperationAction(ISD::CTPOP, VT, Expand); 100 101 setOperationAction(ISD::SETCC, VT, Expand); 102 setOperationAction(ISD::SELECT, VT, Expand); 103 setOperationAction(ISD::SELECT_CC, VT, Custom); 104 } 105 106 if (STI.getHasAlu32()) { 107 setOperationAction(ISD::BSWAP, MVT::i32, Promote); 108 setOperationAction(ISD::BR_CC, MVT::i32, 109 STI.getHasJmp32() ? Custom : Promote); 110 } 111 112 setOperationAction(ISD::CTTZ, MVT::i64, Custom); 113 setOperationAction(ISD::CTLZ, MVT::i64, Custom); 114 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom); 115 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom); 116 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); 121 122 // Extended load operations for i1 types must be promoted 123 for (MVT VT : MVT::integer_valuetypes()) { 124 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 127 128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 129 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 130 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); 131 } 132 133 setBooleanContents(ZeroOrOneBooleanContent); 134 135 // Function alignments (log2) 136 setMinFunctionAlignment(3); 137 setPrefFunctionAlignment(3); 138 139 if (BPFExpandMemcpyInOrder) { 140 // LLVM generic code will try to expand memcpy into load/store pairs at this 141 // stage which is before quite a few IR optimization passes, therefore the 142 // loads and stores could potentially be moved apart from each other which 143 // will cause trouble to memcpy pattern matcher inside kernel eBPF JIT 144 // compilers. 145 // 146 // When -bpf-expand-memcpy-in-order specified, we want to defer the expand 147 // of memcpy to later stage in IR optimization pipeline so those load/store 148 // pairs won't be touched and could be kept in order. Hence, we set 149 // MaxStoresPerMem* to zero to disable the generic getMemcpyLoadsAndStores 150 // code path, and ask LLVM to use target expander EmitTargetCodeForMemcpy. 151 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 0; 152 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 0; 153 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 0; 154 } else { 155 // inline memcpy() for kernel to see explicit copy 156 unsigned CommonMaxStores = 157 STI.getSelectionDAGInfo()->getCommonMaxStoresPerMemFunc(); 158 159 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = CommonMaxStores; 160 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = CommonMaxStores; 161 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = CommonMaxStores; 162 } 163 164 // CPU/Feature control 165 HasAlu32 = STI.getHasAlu32(); 166 HasJmp32 = STI.getHasJmp32(); 167 HasJmpExt = STI.getHasJmpExt(); 168 } 169 170 bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 171 return false; 172 } 173 174 std::pair<unsigned, const TargetRegisterClass *> 175 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 176 StringRef Constraint, 177 MVT VT) const { 178 if (Constraint.size() == 1) 179 // GCC Constraint Letters 180 switch (Constraint[0]) { 181 case 'r': // GENERAL_REGS 182 return std::make_pair(0U, &BPF::GPRRegClass); 183 default: 184 break; 185 } 186 187 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 188 } 189 190 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 191 switch (Op.getOpcode()) { 192 case ISD::BR_CC: 193 return LowerBR_CC(Op, DAG); 194 case ISD::GlobalAddress: 195 return LowerGlobalAddress(Op, DAG); 196 case ISD::SELECT_CC: 197 return LowerSELECT_CC(Op, DAG); 198 default: 199 llvm_unreachable("unimplemented operand"); 200 } 201 } 202 203 // Calling Convention Implementation 204 #include "BPFGenCallingConv.inc" 205 206 SDValue BPFTargetLowering::LowerFormalArguments( 207 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 208 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 209 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 210 switch (CallConv) { 211 default: 212 report_fatal_error("Unsupported calling convention"); 213 case CallingConv::C: 214 case CallingConv::Fast: 215 break; 216 } 217 218 MachineFunction &MF = DAG.getMachineFunction(); 219 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 220 221 // Assign locations to all of the incoming arguments. 222 SmallVector<CCValAssign, 16> ArgLocs; 223 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 224 CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64); 225 226 for (auto &VA : ArgLocs) { 227 if (VA.isRegLoc()) { 228 // Arguments passed in registers 229 EVT RegVT = VA.getLocVT(); 230 MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy; 231 switch (SimpleTy) { 232 default: { 233 errs() << "LowerFormalArguments Unhandled argument type: " 234 << RegVT.getEVTString() << '\n'; 235 llvm_unreachable(0); 236 } 237 case MVT::i32: 238 case MVT::i64: 239 unsigned VReg = RegInfo.createVirtualRegister(SimpleTy == MVT::i64 ? 240 &BPF::GPRRegClass : 241 &BPF::GPR32RegClass); 242 RegInfo.addLiveIn(VA.getLocReg(), VReg); 243 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); 244 245 // If this is an value that has been promoted to wider types, insert an 246 // assert[sz]ext to capture this, then truncate to the right size. 247 if (VA.getLocInfo() == CCValAssign::SExt) 248 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, 249 DAG.getValueType(VA.getValVT())); 250 else if (VA.getLocInfo() == CCValAssign::ZExt) 251 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, 252 DAG.getValueType(VA.getValVT())); 253 254 if (VA.getLocInfo() != CCValAssign::Full) 255 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); 256 257 InVals.push_back(ArgValue); 258 259 break; 260 } 261 } else { 262 fail(DL, DAG, "defined with too many args"); 263 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); 264 } 265 } 266 267 if (IsVarArg || MF.getFunction().hasStructRetAttr()) { 268 fail(DL, DAG, "functions with VarArgs or StructRet are not supported"); 269 } 270 271 return Chain; 272 } 273 274 const unsigned BPFTargetLowering::MaxArgs = 5; 275 276 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 277 SmallVectorImpl<SDValue> &InVals) const { 278 SelectionDAG &DAG = CLI.DAG; 279 auto &Outs = CLI.Outs; 280 auto &OutVals = CLI.OutVals; 281 auto &Ins = CLI.Ins; 282 SDValue Chain = CLI.Chain; 283 SDValue Callee = CLI.Callee; 284 bool &IsTailCall = CLI.IsTailCall; 285 CallingConv::ID CallConv = CLI.CallConv; 286 bool IsVarArg = CLI.IsVarArg; 287 MachineFunction &MF = DAG.getMachineFunction(); 288 289 // BPF target does not support tail call optimization. 290 IsTailCall = false; 291 292 switch (CallConv) { 293 default: 294 report_fatal_error("Unsupported calling convention"); 295 case CallingConv::Fast: 296 case CallingConv::C: 297 break; 298 } 299 300 // Analyze operands of the call, assigning locations to each operand. 301 SmallVector<CCValAssign, 16> ArgLocs; 302 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); 303 304 CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64); 305 306 unsigned NumBytes = CCInfo.getNextStackOffset(); 307 308 if (Outs.size() > MaxArgs) 309 fail(CLI.DL, DAG, "too many args to ", Callee); 310 311 for (auto &Arg : Outs) { 312 ISD::ArgFlagsTy Flags = Arg.Flags; 313 if (!Flags.isByVal()) 314 continue; 315 316 fail(CLI.DL, DAG, "pass by value not supported ", Callee); 317 } 318 319 auto PtrVT = getPointerTy(MF.getDataLayout()); 320 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL); 321 322 SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass; 323 324 // Walk arg assignments 325 for (unsigned i = 0, 326 e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs); 327 i != e; ++i) { 328 CCValAssign &VA = ArgLocs[i]; 329 SDValue Arg = OutVals[i]; 330 331 // Promote the value if needed. 332 switch (VA.getLocInfo()) { 333 default: 334 llvm_unreachable("Unknown loc info"); 335 case CCValAssign::Full: 336 break; 337 case CCValAssign::SExt: 338 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); 339 break; 340 case CCValAssign::ZExt: 341 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); 342 break; 343 case CCValAssign::AExt: 344 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); 345 break; 346 } 347 348 // Push arguments into RegsToPass vector 349 if (VA.isRegLoc()) 350 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 351 else 352 llvm_unreachable("call arg pass bug"); 353 } 354 355 SDValue InFlag; 356 357 // Build a sequence of copy-to-reg nodes chained together with token chain and 358 // flag operands which copy the outgoing args into registers. The InFlag in 359 // necessary since all emitted instructions must be stuck together. 360 for (auto &Reg : RegsToPass) { 361 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag); 362 InFlag = Chain.getValue(1); 363 } 364 365 // If the callee is a GlobalAddress node (quite common, every direct call is) 366 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 367 // Likewise ExternalSymbol -> TargetExternalSymbol. 368 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 369 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT, 370 G->getOffset(), 0); 371 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) { 372 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); 373 fail(CLI.DL, DAG, Twine("A call to built-in function '" 374 + StringRef(E->getSymbol()) 375 + "' is not supported.")); 376 } 377 378 // Returns a chain & a flag for retval copy to use. 379 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 380 SmallVector<SDValue, 8> Ops; 381 Ops.push_back(Chain); 382 Ops.push_back(Callee); 383 384 // Add argument registers to the end of the list so that they are 385 // known live into the call. 386 for (auto &Reg : RegsToPass) 387 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 388 389 if (InFlag.getNode()) 390 Ops.push_back(InFlag); 391 392 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops); 393 InFlag = Chain.getValue(1); 394 395 // Create the CALLSEQ_END node. 396 Chain = DAG.getCALLSEQ_END( 397 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), 398 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL); 399 InFlag = Chain.getValue(1); 400 401 // Handle result values, copying them out of physregs into vregs that we 402 // return. 403 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG, 404 InVals); 405 } 406 407 SDValue 408 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 409 bool IsVarArg, 410 const SmallVectorImpl<ISD::OutputArg> &Outs, 411 const SmallVectorImpl<SDValue> &OutVals, 412 const SDLoc &DL, SelectionDAG &DAG) const { 413 unsigned Opc = BPFISD::RET_FLAG; 414 415 // CCValAssign - represent the assignment of the return value to a location 416 SmallVector<CCValAssign, 16> RVLocs; 417 MachineFunction &MF = DAG.getMachineFunction(); 418 419 // CCState - Info about the registers and stack slot. 420 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 421 422 if (MF.getFunction().getReturnType()->isAggregateType()) { 423 fail(DL, DAG, "only integer returns supported"); 424 return DAG.getNode(Opc, DL, MVT::Other, Chain); 425 } 426 427 // Analize return values. 428 CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); 429 430 SDValue Flag; 431 SmallVector<SDValue, 4> RetOps(1, Chain); 432 433 // Copy the result values into the output registers. 434 for (unsigned i = 0; i != RVLocs.size(); ++i) { 435 CCValAssign &VA = RVLocs[i]; 436 assert(VA.isRegLoc() && "Can only return in registers!"); 437 438 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); 439 440 // Guarantee that all emitted copies are stuck together, 441 // avoiding something bad. 442 Flag = Chain.getValue(1); 443 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 444 } 445 446 RetOps[0] = Chain; // Update chain. 447 448 // Add the flag if we have it. 449 if (Flag.getNode()) 450 RetOps.push_back(Flag); 451 452 return DAG.getNode(Opc, DL, MVT::Other, RetOps); 453 } 454 455 SDValue BPFTargetLowering::LowerCallResult( 456 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, 457 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, 458 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 459 460 MachineFunction &MF = DAG.getMachineFunction(); 461 // Assign locations to each value returned by this call. 462 SmallVector<CCValAssign, 16> RVLocs; 463 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 464 465 if (Ins.size() >= 2) { 466 fail(DL, DAG, "only small returns supported"); 467 for (unsigned i = 0, e = Ins.size(); i != e; ++i) 468 InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT)); 469 return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1); 470 } 471 472 CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64); 473 474 // Copy all of the result registers out of their specified physreg. 475 for (auto &Val : RVLocs) { 476 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), 477 Val.getValVT(), InFlag).getValue(1); 478 InFlag = Chain.getValue(2); 479 InVals.push_back(Chain.getValue(0)); 480 } 481 482 return Chain; 483 } 484 485 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) { 486 switch (CC) { 487 default: 488 break; 489 case ISD::SETULT: 490 case ISD::SETULE: 491 case ISD::SETLT: 492 case ISD::SETLE: 493 CC = ISD::getSetCCSwappedOperands(CC); 494 std::swap(LHS, RHS); 495 break; 496 } 497 } 498 499 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 500 SDValue Chain = Op.getOperand(0); 501 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 502 SDValue LHS = Op.getOperand(2); 503 SDValue RHS = Op.getOperand(3); 504 SDValue Dest = Op.getOperand(4); 505 SDLoc DL(Op); 506 507 if (!getHasJmpExt()) 508 NegateCC(LHS, RHS, CC); 509 510 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 511 DAG.getConstant(CC, DL, LHS.getValueType()), Dest); 512 } 513 514 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 515 SDValue LHS = Op.getOperand(0); 516 SDValue RHS = Op.getOperand(1); 517 SDValue TrueV = Op.getOperand(2); 518 SDValue FalseV = Op.getOperand(3); 519 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 520 SDLoc DL(Op); 521 522 if (!getHasJmpExt()) 523 NegateCC(LHS, RHS, CC); 524 525 SDValue TargetCC = DAG.getConstant(CC, DL, LHS.getValueType()); 526 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 527 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; 528 529 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); 530 } 531 532 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const { 533 switch ((BPFISD::NodeType)Opcode) { 534 case BPFISD::FIRST_NUMBER: 535 break; 536 case BPFISD::RET_FLAG: 537 return "BPFISD::RET_FLAG"; 538 case BPFISD::CALL: 539 return "BPFISD::CALL"; 540 case BPFISD::SELECT_CC: 541 return "BPFISD::SELECT_CC"; 542 case BPFISD::BR_CC: 543 return "BPFISD::BR_CC"; 544 case BPFISD::Wrapper: 545 return "BPFISD::Wrapper"; 546 case BPFISD::MEMCPY: 547 return "BPFISD::MEMCPY"; 548 } 549 return nullptr; 550 } 551 552 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op, 553 SelectionDAG &DAG) const { 554 auto N = cast<GlobalAddressSDNode>(Op); 555 assert(N->getOffset() == 0 && "Invalid offset for global address"); 556 557 SDLoc DL(Op); 558 const GlobalValue *GV = N->getGlobal(); 559 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64); 560 561 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA); 562 } 563 564 unsigned 565 BPFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, 566 unsigned Reg, bool isSigned) const { 567 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 568 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); 569 int RShiftOp = isSigned ? BPF::SRA_ri : BPF::SRL_ri; 570 MachineFunction *F = BB->getParent(); 571 DebugLoc DL = MI.getDebugLoc(); 572 573 MachineRegisterInfo &RegInfo = F->getRegInfo(); 574 unsigned PromotedReg0 = RegInfo.createVirtualRegister(RC); 575 unsigned PromotedReg1 = RegInfo.createVirtualRegister(RC); 576 unsigned PromotedReg2 = RegInfo.createVirtualRegister(RC); 577 BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg); 578 BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1) 579 .addReg(PromotedReg0).addImm(32); 580 BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2) 581 .addReg(PromotedReg1).addImm(32); 582 583 return PromotedReg2; 584 } 585 586 MachineBasicBlock * 587 BPFTargetLowering::EmitInstrWithCustomInserterMemcpy(MachineInstr &MI, 588 MachineBasicBlock *BB) 589 const { 590 MachineFunction *MF = MI.getParent()->getParent(); 591 MachineRegisterInfo &MRI = MF->getRegInfo(); 592 MachineInstrBuilder MIB(*MF, MI); 593 unsigned ScratchReg; 594 595 // This function does custom insertion during lowering BPFISD::MEMCPY which 596 // only has two register operands from memcpy semantics, the copy source 597 // address and the copy destination address. 598 // 599 // Because we will expand BPFISD::MEMCPY into load/store pairs, we will need 600 // a third scratch register to serve as the destination register of load and 601 // source register of store. 602 // 603 // The scratch register here is with the Define | Dead | EarlyClobber flags. 604 // The EarlyClobber flag has the semantic property that the operand it is 605 // attached to is clobbered before the rest of the inputs are read. Hence it 606 // must be unique among the operands to the instruction. The Define flag is 607 // needed to coerce the machine verifier that an Undef value isn't a problem 608 // as we anyway is loading memory into it. The Dead flag is needed as the 609 // value in scratch isn't supposed to be used by any other instruction. 610 ScratchReg = MRI.createVirtualRegister(&BPF::GPRRegClass); 611 MIB.addReg(ScratchReg, 612 RegState::Define | RegState::Dead | RegState::EarlyClobber); 613 614 return BB; 615 } 616 617 MachineBasicBlock * 618 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 619 MachineBasicBlock *BB) const { 620 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); 621 DebugLoc DL = MI.getDebugLoc(); 622 unsigned Opc = MI.getOpcode(); 623 bool isSelectRROp = (Opc == BPF::Select || 624 Opc == BPF::Select_64_32 || 625 Opc == BPF::Select_32 || 626 Opc == BPF::Select_32_64); 627 628 bool isMemcpyOp = Opc == BPF::MEMCPY; 629 630 #ifndef NDEBUG 631 bool isSelectRIOp = (Opc == BPF::Select_Ri || 632 Opc == BPF::Select_Ri_64_32 || 633 Opc == BPF::Select_Ri_32 || 634 Opc == BPF::Select_Ri_32_64); 635 636 637 assert((isSelectRROp || isSelectRIOp || isMemcpyOp) && 638 "Unexpected instr type to insert"); 639 #endif 640 641 if (isMemcpyOp) 642 return EmitInstrWithCustomInserterMemcpy(MI, BB); 643 644 bool is32BitCmp = (Opc == BPF::Select_32 || 645 Opc == BPF::Select_32_64 || 646 Opc == BPF::Select_Ri_32 || 647 Opc == BPF::Select_Ri_32_64); 648 649 // To "insert" a SELECT instruction, we actually have to insert the diamond 650 // control-flow pattern. The incoming instruction knows the destination vreg 651 // to set, the condition code register to branch on, the true/false values to 652 // select between, and a branch opcode to use. 653 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 654 MachineFunction::iterator I = ++BB->getIterator(); 655 656 // ThisMBB: 657 // ... 658 // TrueVal = ... 659 // jmp_XX r1, r2 goto Copy1MBB 660 // fallthrough --> Copy0MBB 661 MachineBasicBlock *ThisMBB = BB; 662 MachineFunction *F = BB->getParent(); 663 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 664 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 665 666 F->insert(I, Copy0MBB); 667 F->insert(I, Copy1MBB); 668 // Update machine-CFG edges by transferring all successors of the current 669 // block to the new block which will contain the Phi node for the select. 670 Copy1MBB->splice(Copy1MBB->begin(), BB, 671 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 672 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 673 // Next, add the true and fallthrough blocks as its successors. 674 BB->addSuccessor(Copy0MBB); 675 BB->addSuccessor(Copy1MBB); 676 677 // Insert Branch if Flag 678 int CC = MI.getOperand(3).getImm(); 679 int NewCC; 680 switch (CC) { 681 #define SET_NEWCC(X, Y) \ 682 case ISD::X: \ 683 if (is32BitCmp && HasJmp32) \ 684 NewCC = isSelectRROp ? BPF::Y##_rr_32 : BPF::Y##_ri_32; \ 685 else \ 686 NewCC = isSelectRROp ? BPF::Y##_rr : BPF::Y##_ri; \ 687 break 688 SET_NEWCC(SETGT, JSGT); 689 SET_NEWCC(SETUGT, JUGT); 690 SET_NEWCC(SETGE, JSGE); 691 SET_NEWCC(SETUGE, JUGE); 692 SET_NEWCC(SETEQ, JEQ); 693 SET_NEWCC(SETNE, JNE); 694 SET_NEWCC(SETLT, JSLT); 695 SET_NEWCC(SETULT, JULT); 696 SET_NEWCC(SETLE, JSLE); 697 SET_NEWCC(SETULE, JULE); 698 default: 699 report_fatal_error("unimplemented select CondCode " + Twine(CC)); 700 } 701 702 unsigned LHS = MI.getOperand(1).getReg(); 703 bool isSignedCmp = (CC == ISD::SETGT || 704 CC == ISD::SETGE || 705 CC == ISD::SETLT || 706 CC == ISD::SETLE); 707 708 // eBPF at the moment only has 64-bit comparison. Any 32-bit comparison need 709 // to be promoted, however if the 32-bit comparison operands are destination 710 // registers then they are implicitly zero-extended already, there is no 711 // need of explicit zero-extend sequence for them. 712 // 713 // We simply do extension for all situations in this method, but we will 714 // try to remove those unnecessary in BPFMIPeephole pass. 715 if (is32BitCmp && !HasJmp32) 716 LHS = EmitSubregExt(MI, BB, LHS, isSignedCmp); 717 718 if (isSelectRROp) { 719 unsigned RHS = MI.getOperand(2).getReg(); 720 721 if (is32BitCmp && !HasJmp32) 722 RHS = EmitSubregExt(MI, BB, RHS, isSignedCmp); 723 724 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB); 725 } else { 726 int64_t imm32 = MI.getOperand(2).getImm(); 727 // sanity check before we build J*_ri instruction. 728 assert (isInt<32>(imm32)); 729 BuildMI(BB, DL, TII.get(NewCC)) 730 .addReg(LHS).addImm(imm32).addMBB(Copy1MBB); 731 } 732 733 // Copy0MBB: 734 // %FalseValue = ... 735 // # fallthrough to Copy1MBB 736 BB = Copy0MBB; 737 738 // Update machine-CFG edges 739 BB->addSuccessor(Copy1MBB); 740 741 // Copy1MBB: 742 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ] 743 // ... 744 BB = Copy1MBB; 745 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg()) 746 .addReg(MI.getOperand(5).getReg()) 747 .addMBB(Copy0MBB) 748 .addReg(MI.getOperand(4).getReg()) 749 .addMBB(ThisMBB); 750 751 MI.eraseFromParent(); // The pseudo instruction is gone now. 752 return BB; 753 } 754 755 EVT BPFTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, 756 EVT VT) const { 757 return getHasAlu32() ? MVT::i32 : MVT::i64; 758 } 759 760 MVT BPFTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, 761 EVT VT) const { 762 return (getHasAlu32() && VT == MVT::i32) ? MVT::i32 : MVT::i64; 763 } 764