1*0b57cec5SDimitry Andric //===-- AVRRegisterInfo.h - AVR Register Information Impl -------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the AVR implementation of the TargetRegisterInfo class. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_AVR_REGISTER_INFO_H 14*0b57cec5SDimitry Andric #define LLVM_AVR_REGISTER_INFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric #define GET_REGINFO_HEADER 19*0b57cec5SDimitry Andric #include "AVRGenRegisterInfo.inc" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric namespace llvm { 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric /// Utilities relating to AVR registers. 24*0b57cec5SDimitry Andric class AVRRegisterInfo : public AVRGenRegisterInfo { 25*0b57cec5SDimitry Andric public: 26*0b57cec5SDimitry Andric AVRRegisterInfo(); 27*0b57cec5SDimitry Andric 28*0b57cec5SDimitry Andric public: 29*0b57cec5SDimitry Andric const uint16_t * 30*0b57cec5SDimitry Andric getCalleeSavedRegs(const MachineFunction *MF = 0) const override; 31*0b57cec5SDimitry Andric const uint32_t *getCallPreservedMask(const MachineFunction &MF, 32*0b57cec5SDimitry Andric CallingConv::ID CC) const override; 33*0b57cec5SDimitry Andric BitVector getReservedRegs(const MachineFunction &MF) const override; 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric const TargetRegisterClass * 36*0b57cec5SDimitry Andric getLargestLegalSuperClass(const TargetRegisterClass *RC, 37*0b57cec5SDimitry Andric const MachineFunction &MF) const override; 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andric /// Stack Frame Processing Methods 40*0b57cec5SDimitry Andric void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 41*0b57cec5SDimitry Andric unsigned FIOperandNum, 42*0b57cec5SDimitry Andric RegScavenger *RS = NULL) const override; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric Register getFrameRegister(const MachineFunction &MF) const override; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric const TargetRegisterClass * 47*0b57cec5SDimitry Andric getPointerRegClass(const MachineFunction &MF, 48*0b57cec5SDimitry Andric unsigned Kind = 0) const override; 49*0b57cec5SDimitry Andric 50*0b57cec5SDimitry Andric /// Splits a 16-bit `DREGS` register into the lo/hi register pair. 51*0b57cec5SDimitry Andric /// \param Reg A 16-bit register to split. 52*0b57cec5SDimitry Andric void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const; 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andric bool trackLivenessAfterRegAlloc(const MachineFunction &) const override { 55*0b57cec5SDimitry Andric return true; 56*0b57cec5SDimitry Andric } 57*0b57cec5SDimitry Andric 58*0b57cec5SDimitry Andric bool shouldCoalesce(MachineInstr *MI, 59*0b57cec5SDimitry Andric const TargetRegisterClass *SrcRC, 60*0b57cec5SDimitry Andric unsigned SubReg, 61*0b57cec5SDimitry Andric const TargetRegisterClass *DstRC, 62*0b57cec5SDimitry Andric unsigned DstSubReg, 63*0b57cec5SDimitry Andric const TargetRegisterClass *NewRC, 64*0b57cec5SDimitry Andric LiveIntervals &LIS) const override; 65*0b57cec5SDimitry Andric }; 66*0b57cec5SDimitry Andric 67*0b57cec5SDimitry Andric } // end namespace llvm 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric #endif // LLVM_AVR_REGISTER_INFO_H 70