1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the AVR instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13include "AVRInstrFormats.td" 14 15//===----------------------------------------------------------------------===// 16// AVR Type Profiles 17//===----------------------------------------------------------------------===// 18 19def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 20def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; 21def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 22def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 23def SDT_AVRBrcond 24 : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>; 25def SDT_AVRCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 26def SDT_AVRTst : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 27def SDT_AVRSelectCC 28 : SDTypeProfile<1, 3, 29 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 30 31//===----------------------------------------------------------------------===// 32// AVR Specific Node Definitions 33//===----------------------------------------------------------------------===// 34 35def AVRretflag : SDNode<"AVRISD::RET_FLAG", SDTNone, 36 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 37def AVRretiflag : SDNode<"AVRISD::RETI_FLAG", SDTNone, 38 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 39 40def AVRcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AVRCallSeqStart, 41 [SDNPHasChain, SDNPOutGlue]>; 42def AVRcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AVRCallSeqEnd, 43 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 44 45def AVRcall : SDNode<"AVRISD::CALL", SDT_AVRCall, 46 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; 47 48def AVRWrapper : SDNode<"AVRISD::WRAPPER", SDT_AVRWrapper>; 49 50def AVRbrcond 51 : SDNode<"AVRISD::BRCOND", SDT_AVRBrcond, [SDNPHasChain, SDNPInGlue]>; 52def AVRcmp : SDNode<"AVRISD::CMP", SDT_AVRCmp, [SDNPOutGlue]>; 53def AVRcmpc : SDNode<"AVRISD::CMPC", SDT_AVRCmp, [SDNPInGlue, SDNPOutGlue]>; 54def AVRtst : SDNode<"AVRISD::TST", SDT_AVRTst, [SDNPOutGlue]>; 55def AVRselectcc : SDNode<"AVRISD::SELECT_CC", SDT_AVRSelectCC, [SDNPInGlue]>; 56 57// Shift nodes. 58def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>; 59def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>; 60def AVRrol : SDNode<"AVRISD::ROL", SDTIntUnaryOp>; 61def AVRror : SDNode<"AVRISD::ROR", SDTIntUnaryOp>; 62def AVRasr : SDNode<"AVRISD::ASR", SDTIntUnaryOp>; 63def AVRlslhi : SDNode<"AVRISD::LSLHI", SDTIntUnaryOp>; 64def AVRlsrlo : SDNode<"AVRISD::LSRLO", SDTIntUnaryOp>; 65def AVRasrlo : SDNode<"AVRISD::ASRLO", SDTIntUnaryOp>; 66def AVRlslbn : SDNode<"AVRISD::LSLBN", SDTIntBinOp>; 67def AVRlsrbn : SDNode<"AVRISD::LSRBN", SDTIntBinOp>; 68def AVRasrbn : SDNode<"AVRISD::ASRBN", SDTIntBinOp>; 69def AVRlslwn : SDNode<"AVRISD::LSLWN", SDTIntBinOp>; 70def AVRlsrwn : SDNode<"AVRISD::LSRWN", SDTIntBinOp>; 71def AVRasrwn : SDNode<"AVRISD::ASRWN", SDTIntBinOp>; 72 73// Pseudo shift nodes for non-constant shift amounts. 74def AVRlslLoop : SDNode<"AVRISD::LSLLOOP", SDTIntShiftOp>; 75def AVRlsrLoop : SDNode<"AVRISD::LSRLOOP", SDTIntShiftOp>; 76def AVRrolLoop : SDNode<"AVRISD::ROLLOOP", SDTIntShiftOp>; 77def AVRrorLoop : SDNode<"AVRISD::RORLOOP", SDTIntShiftOp>; 78def AVRasrLoop : SDNode<"AVRISD::ASRLOOP", SDTIntShiftOp>; 79 80// SWAP node. 81def AVRSwap : SDNode<"AVRISD::SWAP", SDTIntUnaryOp>; 82 83//===----------------------------------------------------------------------===// 84// AVR Operands, Complex Patterns and Transformations Definitions. 85//===----------------------------------------------------------------------===// 86 87def imm8_neg_XFORM : SDNodeXForm<imm, [{ 88 return CurDAG->getTargetConstant( 89 -N->getAPIntValue(), SDLoc(N), MVT::i8); 90 }]>; 91 92def imm16_neg_XFORM 93 : SDNodeXForm<imm, [{ 94 return CurDAG->getTargetConstant(-N->getAPIntValue(), 95 SDLoc(N), MVT::i16); 96 }]>; 97 98def imm0_63_neg : PatLeaf<(imm), [{ 99 int64_t val = -N->getSExtValue(); 100 return val >= 0 && val < 64; 101 }], 102 imm16_neg_XFORM>; 103 104def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>; 105 106// imm_com8_XFORM - Return the complement of a imm_com8 value 107def imm_com8_XFORM 108 : SDNodeXForm<imm, [{ 109 return CurDAG->getTargetConstant( 110 ~((uint8_t) N->getZExtValue()), SDLoc(N), MVT::i8); 111 }]>; 112 113// imm_com8 - Match an immediate that is a complement 114// of a 8-bit immediate. 115// Note: this pattern doesn't require an encoder method and such, as it's 116// only used on aliases (Pat<> and InstAlias<>). The actual encoding 117// is handled by the destination instructions, which use imm_com8. 118def imm_com8_asmoperand : AsmOperandClass { let Name = "ImmCom8"; } 119def imm_com8 : Operand<i8> { let ParserMatchClass = imm_com8_asmoperand; } 120 121def ioaddr_XFORM 122 : SDNodeXForm<imm, [{ 123 uint8_t offset = Subtarget->getIORegisterOffset(); 124 return CurDAG->getTargetConstant( 125 uint8_t(N->getZExtValue()) - offset, SDLoc(N), MVT::i8); 126 }]>; 127 128def iobitpos8_XFORM 129 : SDNodeXForm<imm, [{ 130 return CurDAG->getTargetConstant( 131 Log2_32(uint8_t(N->getZExtValue())), SDLoc(N), MVT::i8); 132 }]>; 133 134def iobitposn8_XFORM : SDNodeXForm<imm, [{ 135 return CurDAG->getTargetConstant( 136 Log2_32(uint8_t(~N->getZExtValue())), 137 SDLoc(N), MVT::i8); 138 }]>; 139 140def ioaddr8 : PatLeaf<(imm), [{ 141 uint8_t offset = Subtarget->getIORegisterOffset(); 142 uint64_t val = N->getZExtValue() - offset; 143 return val < 0x40; 144 }], 145 ioaddr_XFORM>; 146 147def lowioaddr8 : PatLeaf<(imm), [{ 148 uint8_t offset = Subtarget->getIORegisterOffset(); 149 uint64_t val = N->getZExtValue() - offset; 150 return val < 0x20; 151 }], 152 ioaddr_XFORM>; 153 154def ioaddr16 : PatLeaf<(imm), [{ 155 uint8_t offset = Subtarget->getIORegisterOffset(); 156 uint64_t val = N->getZExtValue() - offset; 157 return val < 0x3f; 158 }], 159 ioaddr_XFORM>; 160 161def iobitpos8 162 : PatLeaf<(imm), [{ return isPowerOf2_32(uint8_t(N->getZExtValue())); }], 163 iobitpos8_XFORM>; 164 165def iobitposn8 166 : PatLeaf<(imm), [{ return isPowerOf2_32(uint8_t(~N->getZExtValue())); }], 167 iobitposn8_XFORM>; 168 169def MemriAsmOperand : AsmOperandClass { 170 let Name = "Memri"; 171 let ParserMethod = "parseMemriOperand"; 172} 173 174/// Address operand for `reg+imm` used by STD and LDD. 175def memri : Operand<iPTR> { 176 let MIOperandInfo = (ops PTRDISPREGS, i16imm); 177 178 let PrintMethod = "printMemri"; 179 let EncoderMethod = "encodeMemri"; 180 181 let ParserMatchClass = MemriAsmOperand; 182} 183 184// Address operand for `SP+imm` used by STD{W}SPQRr 185def memspi : Operand<iPTR> { let MIOperandInfo = (ops GPRSP, i16imm); } 186 187def relbrtarget_7 : Operand<OtherVT> { 188 let PrintMethod = "printPCRelImm"; 189 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>"; 190} 191 192def brtarget_13 : Operand<OtherVT> { 193 let PrintMethod = "printPCRelImm"; 194 let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>"; 195} 196 197// The target of a 22 or 16-bit call/jmp instruction. 198def call_target : Operand<iPTR> { 199 let EncoderMethod = "encodeCallTarget"; 200 let DecoderMethod = "decodeCallTarget"; 201} 202 203// A 16-bit address (which can lead to an R_AVR_16 relocation). 204def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; } 205 206/// A 6-bit immediate used in the ADIW/SBIW instructions. 207def imm_arith6 : Operand<i16> { 208 let EncoderMethod = "encodeImm<AVR::fixup_6_adiw, 0>"; 209} 210 211/// An 8-bit immediate inside an instruction with the same format 212/// as the `LDI` instruction (the `FRdK` format). 213def imm_ldi8 : Operand<i8> { 214 let EncoderMethod = "encodeImm<AVR::fixup_ldi, 0>"; 215} 216 217/// A 5-bit port number used in SBIC and friends (the `FIOBIT` format). 218def imm_port5 : Operand<i8> { 219 let EncoderMethod = "encodeImm<AVR::fixup_port5, 0>"; 220} 221 222/// A 6-bit port number used in the `IN` instruction and friends (the 223/// `FIORdA` format. 224def imm_port6 : Operand<i8> { 225 let EncoderMethod = "encodeImm<AVR::fixup_port6, 0>"; 226} 227 228// Addressing mode pattern reg+imm6 229def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], [SDNPWantRoot]>; 230 231// AsmOperand class for a pointer register. 232// Used with the LD/ST family of instructions. 233// See FSTLD in AVRInstrFormats.td 234def PtrRegAsmOperand : AsmOperandClass { let Name = "Reg"; } 235 236// A special operand type for the LD/ST instructions. 237// It converts the pointer register number into a two-bit field used in the 238// instruction. 239def LDSTPtrReg : Operand<i16> { 240 let MIOperandInfo = (ops PTRREGS); 241 let EncoderMethod = "encodeLDSTPtrReg"; 242 243 let ParserMatchClass = PtrRegAsmOperand; 244} 245 246// A special operand type for the LDD/STD instructions. 247// It behaves identically to the LD/ST version, except restricts 248// the pointer registers to Y and Z. 249def LDDSTDPtrReg : Operand<i16> { 250 let MIOperandInfo = (ops PTRDISPREGS); 251 let EncoderMethod = "encodeLDSTPtrReg"; 252 253 let ParserMatchClass = PtrRegAsmOperand; 254} 255 256//===----------------------------------------------------------------------===// 257// AVR predicates for subtarget features 258//===----------------------------------------------------------------------===// 259 260def HasSRAM : Predicate<"Subtarget->hasSRAM()">, 261 AssemblerPredicate<(all_of FeatureSRAM)>; 262 263def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">, 264 AssemblerPredicate<(all_of FeatureJMPCALL)>; 265 266def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">, 267 AssemblerPredicate<(all_of FeatureIJMPCALL)>; 268 269def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">, 270 AssemblerPredicate<(all_of FeatureEIJMPCALL)>; 271 272def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">, 273 AssemblerPredicate<(all_of FeatureADDSUBIW)>; 274 275def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">, 276 AssemblerPredicate<(all_of FeatureSmallStack)>; 277 278def HasMOVW : Predicate<"Subtarget->hasMOVW()">, 279 AssemblerPredicate<(all_of FeatureMOVW)>; 280 281def HasLPM : Predicate<"Subtarget->hasLPM()">, 282 AssemblerPredicate<(all_of FeatureLPM)>; 283 284def HasLPMX : Predicate<"Subtarget->hasLPMX()">, 285 AssemblerPredicate<(all_of FeatureLPMX)>; 286 287def HasELPM : Predicate<"Subtarget->hasELPM()">, 288 AssemblerPredicate<(all_of FeatureELPM)>; 289 290def HasELPMX : Predicate<"Subtarget->hasELPMX()">, 291 AssemblerPredicate<(all_of FeatureELPMX)>; 292 293def HasSPM : Predicate<"Subtarget->hasSPM()">, 294 AssemblerPredicate<(all_of FeatureSPM)>; 295 296def HasSPMX : Predicate<"Subtarget->hasSPMX()">, 297 AssemblerPredicate<(all_of FeatureSPMX)>; 298 299def HasDES : Predicate<"Subtarget->hasDES()">, 300 AssemblerPredicate<(all_of FeatureDES)>; 301 302def SupportsRMW : Predicate<"Subtarget->supportsRMW()">, 303 AssemblerPredicate<(all_of FeatureRMW)>; 304 305def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">, 306 AssemblerPredicate<(all_of FeatureMultiplication)>; 307 308def HasBREAK : Predicate<"Subtarget->hasBREAK()">, 309 AssemblerPredicate<(all_of FeatureBREAK)>; 310 311def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">, 312 AssemblerPredicate<(all_of FeatureTinyEncoding)>; 313 314// AVR specific condition code. These correspond to AVR_*_COND in 315// AVRInstrInfo.td. They must be kept in synch. 316def AVR_COND_EQ : PatLeaf<(i8 0)>; 317def AVR_COND_NE : PatLeaf<(i8 1)>; 318def AVR_COND_GE : PatLeaf<(i8 2)>; 319def AVR_COND_LT : PatLeaf<(i8 3)>; 320def AVR_COND_SH : PatLeaf<(i8 4)>; 321def AVR_COND_LO : PatLeaf<(i8 5)>; 322def AVR_COND_MI : PatLeaf<(i8 6)>; 323def AVR_COND_PL : PatLeaf<(i8 7)>; 324 325//===----------------------------------------------------------------------===// 326//===----------------------------------------------------------------------===// 327// AVR Instruction list 328//===----------------------------------------------------------------------===// 329//===----------------------------------------------------------------------===// 330 331// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into 332// a stack adjustment and the codegen must know that they may modify the stack 333// pointer before prolog-epilog rewriting occurs. 334// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become 335// sub / add which can clobber SREG. 336let Defs = [SP, SREG], Uses = [SP] in { 337 def ADJCALLSTACKDOWN : Pseudo<(outs), 338 (ins i16imm 339 : $amt, i16imm 340 : $amt2), 341 "#ADJCALLSTACKDOWN", [(AVRcallseq_start timm 342 : $amt, timm 343 : $amt2)]>; 344 345 // R31R30 is used to update SP. It is normally free because it is a 346 // call-clobbered register but it is necessary to set it as a def as the 347 // register allocator might use it in rare cases (for rematerialization, it 348 // seems). hasSideEffects needs to be set to true so this instruction isn't 349 // considered dead. 350 let Defs = [R31R30], hasSideEffects = 1 in def ADJCALLSTACKUP 351 : Pseudo<(outs), 352 (ins i16imm 353 : $amt1, i16imm 354 : $amt2), 355 "#ADJCALLSTACKUP", [(AVRcallseq_end timm 356 : $amt1, timm 357 : $amt2)]>; 358} 359 360//===----------------------------------------------------------------------===// 361// Addition 362//===----------------------------------------------------------------------===// 363let isCommutable = 1, Constraints = "$src = $rd", Defs = [SREG] in { 364 // ADD Rd, Rr 365 // Adds two 8-bit registers. 366 def ADDRdRr 367 : FRdRr<0b0000, 0b11, 368 (outs GPR8 369 : $rd), 370 (ins GPR8 371 : $src, GPR8 372 : $rr), 373 "add\t$rd, $rr", 374 [(set i8 375 : $rd, (add i8 376 : $src, i8 377 : $rr)), 378 (implicit SREG)]>; 379 380 // ADDW Rd+1:Rd, Rr+1:Rr 381 // Pseudo instruction to add four 8-bit registers as two 16-bit values. 382 // 383 // Expands to: 384 // add Rd, Rr 385 // adc Rd+1, Rr+1 386 def ADDWRdRr 387 : Pseudo<(outs DREGS 388 : $rd), 389 (ins DREGS 390 : $src, DREGS 391 : $rr), 392 "addw\t$rd, $rr", 393 [(set i16 394 : $rd, (add i16 395 : $src, i16 396 : $rr)), 397 (implicit SREG)]>; 398 399 // ADC Rd, Rr 400 // Adds two 8-bit registers with carry. 401 let Uses = [SREG] in def ADCRdRr 402 : FRdRr<0b0001, 0b11, 403 (outs GPR8 404 : $rd), 405 (ins GPR8 406 : $src, GPR8 407 : $rr), 408 "adc\t$rd, $rr", 409 [(set i8 410 : $rd, (adde i8 411 : $src, i8 412 : $rr)), 413 (implicit SREG)]>; 414 415 // ADCW Rd+1:Rd, Rr+1:Rr 416 // Pseudo instruction to add four 8-bit registers as two 16-bit values with 417 // carry. 418 // 419 // Expands to: 420 // adc Rd, Rr 421 // adc Rd+1, Rr+1 422 let Uses = [SREG] in def ADCWRdRr : Pseudo<(outs DREGS 423 : $rd), 424 (ins DREGS 425 : $src, DREGS 426 : $rr), 427 "adcw\t$rd, $rr", [ 428 (set i16 429 : $rd, (adde i16 430 : $src, i16 431 : $rr)), 432 (implicit SREG) 433 ]>; 434 435 // AIDW Rd, k 436 // Adds an immediate 6-bit value K to Rd, placing the result in Rd. 437 def ADIWRdK 438 : FWRdK<0b0, 439 (outs IWREGS 440 : $rd), 441 (ins IWREGS 442 : $src, imm_arith6 443 : $k), 444 "adiw\t$rd, $k", 445 [(set i16 446 : $rd, (add i16 447 : $src, uimm6 448 : $k)), 449 (implicit SREG)]>, 450 Requires<[HasADDSUBIW]>; 451} 452 453//===----------------------------------------------------------------------===// 454// Subtraction 455//===----------------------------------------------------------------------===// 456let Constraints = "$src = $rd", Defs = [SREG] in { 457 // SUB Rd, Rr 458 // Subtracts the 8-bit value of Rr from Rd and places the value in Rd. 459 def SUBRdRr 460 : FRdRr<0b0001, 0b10, 461 (outs GPR8 462 : $rd), 463 (ins GPR8 464 : $src, GPR8 465 : $rr), 466 "sub\t$rd, $rr", 467 [(set i8 468 : $rd, (sub i8 469 : $src, i8 470 : $rr)), 471 (implicit SREG)]>; 472 473 // SUBW Rd+1:Rd, Rr+1:Rr 474 // Subtracts two 16-bit values and places the result into Rd. 475 // 476 // Expands to: 477 // sub Rd, Rr 478 // sbc Rd+1, Rr+1 479 def SUBWRdRr 480 : Pseudo<(outs DREGS 481 : $rd), 482 (ins DREGS 483 : $src, DREGS 484 : $rr), 485 "subw\t$rd, $rr", 486 [(set i16 487 : $rd, (sub i16 488 : $src, i16 489 : $rr)), 490 (implicit SREG)]>; 491 492 def SUBIRdK 493 : FRdK<0b0101, 494 (outs LD8 495 : $rd), 496 (ins LD8 497 : $src, imm_ldi8 498 : $k), 499 "subi\t$rd, $k", 500 [(set i8 501 : $rd, (sub i8 502 : $src, imm 503 : $k)), 504 (implicit SREG)]>; 505 506 // SUBIW Rd+1:Rd, K+1:K 507 // 508 // Expands to: 509 // subi Rd, K 510 // sbci Rd+1, K+1 511 def SUBIWRdK 512 : Pseudo<(outs DLDREGS 513 : $rd), 514 (ins DLDREGS 515 : $src, i16imm 516 : $rr), 517 "subiw\t$rd, $rr", 518 [(set i16 519 : $rd, (sub i16 520 : $src, imm 521 : $rr)), 522 (implicit SREG)]>; 523 524 def SBIWRdK 525 : FWRdK<0b1, 526 (outs IWREGS 527 : $rd), 528 (ins IWREGS 529 : $src, imm_arith6 530 : $k), 531 "sbiw\t$rd, $k", 532 [(set i16 533 : $rd, (sub i16 534 : $src, uimm6 535 : $k)), 536 (implicit SREG)]>, 537 Requires<[HasADDSUBIW]>; 538 539 // Subtract with carry operations which must read the carry flag in SREG. 540 let Uses = [SREG] in { 541 def SBCRdRr 542 : FRdRr<0b0000, 0b10, 543 (outs GPR8 544 : $rd), 545 (ins GPR8 546 : $src, GPR8 547 : $rr), 548 "sbc\t$rd, $rr", 549 [(set i8 550 : $rd, (sube i8 551 : $src, i8 552 : $rr)), 553 (implicit SREG)]>; 554 555 // SBCW Rd+1:Rd, Rr+1:Rr 556 // 557 // Expands to: 558 // sbc Rd, Rr 559 // sbc Rd+1, Rr+1 560 def SBCWRdRr : Pseudo<(outs DREGS 561 : $rd), 562 (ins DREGS 563 : $src, DREGS 564 : $rr), 565 "sbcw\t$rd, $rr", [ 566 (set i16 567 : $rd, (sube i16 568 : $src, i16 569 : $rr)), 570 (implicit SREG) 571 ]>; 572 573 def SBCIRdK 574 : FRdK<0b0100, 575 (outs LD8 576 : $rd), 577 (ins LD8 578 : $src, imm_ldi8 579 : $k), 580 "sbci\t$rd, $k", 581 [(set i8 582 : $rd, (sube i8 583 : $src, imm 584 : $k)), 585 (implicit SREG)]>; 586 587 // SBCIW Rd+1:Rd, K+1:K 588 // sbci Rd, K 589 // sbci Rd+1, K+1 590 def SBCIWRdK : Pseudo<(outs DLDREGS 591 : $rd), 592 (ins DLDREGS 593 : $src, i16imm 594 : $rr), 595 "sbciw\t$rd, $rr", [ 596 (set i16 597 : $rd, (sube i16 598 : $src, imm 599 : $rr)), 600 (implicit SREG) 601 ]>; 602 } 603} 604 605//===----------------------------------------------------------------------===// 606// Increment and Decrement 607//===----------------------------------------------------------------------===// 608let Constraints = "$src = $rd", Defs = [SREG] in { 609 def INCRd 610 : FRd<0b1001, 0b0100011, 611 (outs GPR8 612 : $rd), 613 (ins GPR8 614 : $src), 615 "inc\t$rd", [(set i8 616 : $rd, (add i8 617 : $src, 1)), 618 (implicit SREG)]>; 619 620 def DECRd 621 : FRd<0b1001, 0b0101010, 622 (outs GPR8 623 : $rd), 624 (ins GPR8 625 : $src), 626 "dec\t$rd", [(set i8 627 : $rd, (add i8 628 : $src, -1)), 629 (implicit SREG)]>; 630} 631 632//===----------------------------------------------------------------------===// 633// Multiplication 634//===----------------------------------------------------------------------===// 635 636let isCommutable = 1, Defs = [R1, R0, SREG] in { 637 // MUL Rd, Rr 638 // Multiplies Rd by Rr and places the result into R1:R0. 639 let usesCustomInserter = 1 in { 640 def MULRdRr : FRdRr<0b1001, 0b11, (outs), 641 (ins GPR8 642 : $lhs, GPR8 643 : $rhs), 644 "mul\t$lhs, $rhs", 645 [/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>, 646 Requires<[SupportsMultiplication]>; 647 648 def MULSRdRr : FMUL2RdRr<0, (outs), 649 (ins LD8 650 : $lhs, LD8 651 : $rhs), 652 "muls\t$lhs, $rhs", []>, 653 Requires<[SupportsMultiplication]>; 654 } 655 656 def MULSURdRr : FMUL2RdRr<1, (outs), 657 (ins LD8lo 658 : $lhs, LD8lo 659 : $rhs), 660 "mulsu\t$lhs, $rhs", []>, 661 Requires<[SupportsMultiplication]>; 662 663 def FMUL : FFMULRdRr<0b01, (outs), 664 (ins LD8lo 665 : $lhs, LD8lo 666 : $rhs), 667 "fmul\t$lhs, $rhs", []>, 668 Requires<[SupportsMultiplication]>; 669 670 def FMULS : FFMULRdRr<0b10, (outs), 671 (ins LD8lo 672 : $lhs, LD8lo 673 : $rhs), 674 "fmuls\t$lhs, $rhs", []>, 675 Requires<[SupportsMultiplication]>; 676 677 def FMULSU : FFMULRdRr<0b11, (outs), 678 (ins LD8lo 679 : $lhs, LD8lo 680 : $rhs), 681 "fmulsu\t$lhs, $rhs", []>, 682 Requires<[SupportsMultiplication]>; 683} 684 685let Defs = 686 [R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R1, 687 R0] in def DESK : FDES<(outs), 688 (ins i8imm 689 : $k), 690 "des\t$k", []>, 691 Requires<[HasDES]>; 692 693//===----------------------------------------------------------------------===// 694// Logic 695//===----------------------------------------------------------------------===// 696let Constraints = "$src = $rd", Defs = [SREG] in { 697 // Register-Register logic instructions (which have the 698 // property of commutativity). 699 let isCommutable = 1 in { 700 def ANDRdRr 701 : FRdRr<0b0010, 0b00, 702 (outs GPR8 703 : $rd), 704 (ins GPR8 705 : $src, GPR8 706 : $rr), 707 "and\t$rd, $rr", 708 [(set i8 709 : $rd, (and i8 710 : $src, i8 711 : $rr)), 712 (implicit SREG)]>; 713 714 // ANDW Rd+1:Rd, Rr+1:Rr 715 // 716 // Expands to: 717 // and Rd, Rr 718 // and Rd+1, Rr+1 719 def ANDWRdRr : Pseudo<(outs DREGS 720 : $rd), 721 (ins DREGS 722 : $src, DREGS 723 : $rr), 724 "andw\t$rd, $rr", [ 725 (set i16 726 : $rd, (and i16 727 : $src, i16 728 : $rr)), 729 (implicit SREG) 730 ]>; 731 732 def ORRdRr 733 : FRdRr<0b0010, 0b10, 734 (outs GPR8 735 : $rd), 736 (ins GPR8 737 : $src, GPR8 738 : $rr), 739 "or\t$rd, $rr", 740 [(set i8 741 : $rd, (or i8 742 : $src, i8 743 : $rr)), 744 (implicit SREG)]>; 745 746 // ORW Rd+1:Rd, Rr+1:Rr 747 // 748 // Expands to: 749 // or Rd, Rr 750 // or Rd+1, Rr+1 751 def ORWRdRr : Pseudo<(outs DREGS 752 : $rd), 753 (ins DREGS 754 : $src, DREGS 755 : $rr), 756 "orw\t$rd, $rr", [ 757 (set i16 758 : $rd, (or i16 759 : $src, i16 760 : $rr)), 761 (implicit SREG) 762 ]>; 763 764 def EORRdRr 765 : FRdRr<0b0010, 0b01, 766 (outs GPR8 767 : $rd), 768 (ins GPR8 769 : $src, GPR8 770 : $rr), 771 "eor\t$rd, $rr", 772 [(set i8 773 : $rd, (xor i8 774 : $src, i8 775 : $rr)), 776 (implicit SREG)]>; 777 778 // EORW Rd+1:Rd, Rr+1:Rr 779 // 780 // Expands to: 781 // eor Rd, Rr 782 // eor Rd+1, Rr+1 783 def EORWRdRr : Pseudo<(outs DREGS 784 : $rd), 785 (ins DREGS 786 : $src, DREGS 787 : $rr), 788 "eorw\t$rd, $rr", [ 789 (set i16 790 : $rd, (xor i16 791 : $src, i16 792 : $rr)), 793 (implicit SREG) 794 ]>; 795 } 796 797 def ANDIRdK 798 : FRdK<0b0111, 799 (outs LD8 800 : $rd), 801 (ins LD8 802 : $src, imm_ldi8 803 : $k), 804 "andi\t$rd, $k", 805 [(set i8 806 : $rd, (and i8 807 : $src, imm 808 : $k)), 809 (implicit SREG)]>; 810 811 // ANDI Rd+1:Rd, K+1:K 812 // 813 // Expands to: 814 // andi Rd, K 815 // andi Rd+1, K+1 816 def ANDIWRdK 817 : Pseudo<(outs DLDREGS 818 : $rd), 819 (ins DLDREGS 820 : $src, i16imm 821 : $k), 822 "andiw\t$rd, $k", 823 [(set i16 824 : $rd, (and i16 825 : $src, imm 826 : $k)), 827 (implicit SREG)]>; 828 829 def ORIRdK 830 : FRdK<0b0110, 831 (outs LD8 832 : $rd), 833 (ins LD8 834 : $src, imm_ldi8 835 : $k), 836 "ori\t$rd, $k", 837 [(set i8 838 : $rd, (or i8 839 : $src, imm 840 : $k)), 841 (implicit SREG)]>; 842 843 // ORIW Rd+1:Rd, K+1,K 844 // 845 // Expands to: 846 // ori Rd, K 847 // ori Rd+1, K+1 848 def ORIWRdK 849 : Pseudo<(outs DLDREGS 850 : $rd), 851 (ins DLDREGS 852 : $src, i16imm 853 : $rr), 854 "oriw\t$rd, $rr", 855 [(set i16 856 : $rd, (or i16 857 : $src, imm 858 : $rr)), 859 (implicit SREG)]>; 860} 861 862//===----------------------------------------------------------------------===// 863// One's/Two's Complement 864//===----------------------------------------------------------------------===// 865let Constraints = "$src = $rd", Defs = [SREG] in { 866 def COMRd 867 : FRd<0b1001, 0b0100000, 868 (outs GPR8 869 : $rd), 870 (ins GPR8 871 : $src), 872 "com\t$rd", [(set i8 873 : $rd, (not i8 874 : $src)), 875 (implicit SREG)]>; 876 877 // COMW Rd+1:Rd 878 // 879 // Expands to: 880 // com Rd 881 // com Rd+1 882 def COMWRd : Pseudo<(outs DREGS 883 : $rd), 884 (ins DREGS 885 : $src), 886 "comw\t$rd", 887 [(set i16 888 : $rd, (not i16 889 : $src)), 890 (implicit SREG)]>; 891 892 def NEGRd 893 : FRd<0b1001, 0b0100001, 894 (outs GPR8 895 : $rd), 896 (ins GPR8 897 : $src), 898 "neg\t$rd", [(set i8 899 : $rd, (ineg i8 900 : $src)), 901 (implicit SREG)]>; 902 903 // NEGW Rd+1:Rd 904 // 905 // Expands to: 906 // neg Rd+1 907 // neg Rd 908 // sbc Rd+1, r1 909 def NEGWRd : Pseudo<(outs DREGS 910 : $rd), 911 (ins DREGS 912 : $src), 913 "negw\t$rd", 914 [(set i16 915 : $rd, (ineg i16 916 : $src)), 917 (implicit SREG)]>; 918} 919 920// TST Rd 921// Test for zero of minus. 922// This operation is identical to a `Rd AND Rd`. 923def : InstAlias<"tst\t$rd", (ANDRdRr GPR8 : $rd, GPR8 : $rd)>; 924 925// SBR Rd, K 926// 927// Mnemonic alias to 'ORI Rd, K'. Same bit pattern, same operands, 928// same everything. 929def : InstAlias<"sbr\t$rd, $k", 930 (ORIRdK LD8 931 : $rd, imm_ldi8 932 : $k), 933 /* Disable display, so we don't override ORI */ 0>; 934 935//===----------------------------------------------------------------------===// 936// Jump instructions 937//===----------------------------------------------------------------------===// 938let isBarrier = 1, isBranch = 1, isTerminator = 1 in { 939 def RJMPk : FBRk<0, (outs), 940 (ins brtarget_13 941 : $target), 942 "rjmp\t$target", [(br bb 943 : $target)]>; 944 945 let isIndirectBranch = 1, 946 Uses = [R31R30] in def IJMP 947 : F16<0b1001010000001001, (outs), (ins), "ijmp", []>, 948 Requires<[HasIJMPCALL]>; 949 950 let isIndirectBranch = 1, 951 Uses = [R31R30] in def EIJMP 952 : F16<0b1001010000011001, (outs), (ins), "eijmp", []>, 953 Requires<[HasEIJMPCALL]>; 954 955 def JMPk : F32BRk<0b110, (outs), 956 (ins call_target 957 : $k), 958 "jmp\t$k", []>, 959 Requires<[HasJMPCALL]>; 960} 961 962//===----------------------------------------------------------------------===// 963// Call instructions 964//===----------------------------------------------------------------------===// 965let isCall = 1 in { 966 // SP is marked as a use to prevent stack-pointer assignments that appear 967 // immediately before calls from potentially appearing dead. 968 let Uses = [SP] in def RCALLk : FBRk<1, (outs), 969 (ins brtarget_13 970 : $target), 971 "rcall\t$target", []>; 972 973 // SP is marked as a use to prevent stack-pointer assignments that appear 974 // immediately before calls from potentially appearing dead. 975 let Uses = [SP, R31R30] in def ICALL 976 : F16<0b1001010100001001, (outs), (ins variable_ops), "icall", []>, 977 Requires<[HasIJMPCALL]>; 978 979 // SP is marked as a use to prevent stack-pointer assignments that appear 980 // immediately before calls from potentially appearing dead. 981 let Uses = [SP, R31R30] in def EICALL 982 : F16<0b1001010100011001, (outs), (ins variable_ops), "eicall", []>, 983 Requires<[HasEIJMPCALL]>; 984 985 // SP is marked as a use to prevent stack-pointer assignments that appear 986 // immediately before calls from potentially appearing dead. 987 // 988 //: TODO: the imm field can be either 16 or 22 bits in devices with more 989 // than 64k of ROM, fix it once we support the largest devices. 990 let Uses = [SP] in def CALLk : F32BRk<0b111, (outs), 991 (ins call_target 992 : $k), 993 "call\t$k", [(AVRcall imm 994 : $k)]>, 995 Requires<[HasJMPCALL]>; 996} 997 998//===----------------------------------------------------------------------===// 999// Return instructions. 1000//===----------------------------------------------------------------------===// 1001let isTerminator = 1, isReturn = 1, isBarrier = 1 in { 1002 def RET : F16<0b1001010100001000, (outs), (ins), "ret", [(AVRretflag)]>; 1003 1004 def RETI : F16<0b1001010100011000, (outs), (ins), "reti", [(AVRretiflag)]>; 1005} 1006 1007//===----------------------------------------------------------------------===// 1008// Compare operations. 1009//===----------------------------------------------------------------------===// 1010let Defs = [SREG] in { 1011 // CPSE Rd, Rr 1012 // Compare Rd and Rr, skipping the next instruction if they are equal. 1013 let isBarrier = 1, isBranch = 1, 1014 isTerminator = 1 in def CPSE : FRdRr<0b0001, 0b00, (outs), 1015 (ins GPR8 1016 : $rd, GPR8 1017 : $rr), 1018 "cpse\t$rd, $rr", []>; 1019 1020 def CPRdRr 1021 : FRdRr<0b0001, 0b01, (outs), 1022 (ins GPR8 1023 : $rd, GPR8 1024 : $rr), 1025 "cp\t$rd, $rr", [(AVRcmp i8 1026 : $rd, i8 1027 : $rr), 1028 (implicit SREG)]>; 1029 1030 // CPW Rd+1:Rd, Rr+1:Rr 1031 // 1032 // Expands to: 1033 // cp Rd, Rr 1034 // cpc Rd+1, Rr+1 1035 def CPWRdRr : Pseudo<(outs), 1036 (ins DREGS 1037 : $src, DREGS 1038 : $src2), 1039 "cpw\t$src, $src2", 1040 [(AVRcmp i16 1041 : $src, i16 1042 : $src2), 1043 (implicit SREG)]>; 1044 1045 let Uses = [SREG] in def CPCRdRr 1046 : FRdRr<0b0000, 0b01, (outs), 1047 (ins GPR8 1048 : $rd, GPR8 1049 : $rr), 1050 "cpc\t$rd, $rr", [(AVRcmpc i8 1051 : $rd, i8 1052 : $rr), 1053 (implicit SREG)]>; 1054 1055 // CPCW Rd+1:Rd. Rr+1:Rr 1056 // 1057 // Expands to: 1058 // cpc Rd, Rr 1059 // cpc Rd+1, Rr+1 1060 let Uses = [SREG] in def CPCWRdRr 1061 : Pseudo<(outs), 1062 (ins DREGS 1063 : $src, DREGS 1064 : $src2), 1065 "cpcw\t$src, $src2", 1066 [(AVRcmpc i16 1067 : $src, i16 1068 : $src2), 1069 (implicit SREG)]>; 1070 1071 // CPI Rd, K 1072 // Compares a register with an 8 bit immediate. 1073 def CPIRdK 1074 : FRdK<0b0011, (outs), 1075 (ins LD8 1076 : $rd, imm_ldi8 1077 : $k), 1078 "cpi\t$rd, $k", [(AVRcmp i8 1079 : $rd, imm 1080 : $k), 1081 (implicit SREG)]>; 1082} 1083 1084//===----------------------------------------------------------------------===// 1085// Register conditional skipping/branching operations. 1086//===----------------------------------------------------------------------===// 1087let isBranch = 1, isTerminator = 1 in { 1088 // Conditional skipping on GPR register bits, and 1089 // conditional skipping on IO register bits. 1090 let isBarrier = 1 in { 1091 def SBRCRrB : FRdB<0b10, (outs), 1092 (ins GPR8 1093 : $rr, i8imm 1094 : $b), 1095 "sbrc\t$rr, $b", []>; 1096 1097 def SBRSRrB : FRdB<0b11, (outs), 1098 (ins GPR8 1099 : $rr, i8imm 1100 : $b), 1101 "sbrs\t$rr, $b", []>; 1102 1103 def SBICAb : FIOBIT<0b01, (outs), 1104 (ins imm_port5 1105 : $a, i8imm 1106 : $b), 1107 "sbic\t$a, $b", []>; 1108 1109 def SBISAb : FIOBIT<0b11, (outs), 1110 (ins imm_port5 1111 : $a, i8imm 1112 : $b), 1113 "sbis\t$a, $b", []>; 1114 } 1115 1116 // Relative branches on status flag bits. 1117 let Uses = [SREG] in { 1118 // BRBS s, k 1119 // Branch if `s` flag in status register is set. 1120 def BRBSsk : FSK<0, (outs), 1121 (ins i8imm 1122 : $s, relbrtarget_7 1123 : $k), 1124 "brbs\t$s, $k", []>; 1125 1126 // BRBC s, k 1127 // Branch if `s` flag in status register is clear. 1128 def BRBCsk : FSK<1, (outs), 1129 (ins i8imm 1130 : $s, relbrtarget_7 1131 : $k), 1132 "brbc\t$s, $k", []>; 1133 } 1134} 1135 1136// BRCS k 1137// Branch if carry flag is set 1138def : InstAlias<"brcs\t$k", (BRBSsk 0, relbrtarget_7 : $k)>; 1139 1140// BRCC k 1141// Branch if carry flag is clear 1142def : InstAlias<"brcc\t$k", (BRBCsk 0, relbrtarget_7 : $k)>; 1143 1144// BRHS k 1145// Branch if half carry flag is set 1146def : InstAlias<"brhs\t$k", (BRBSsk 5, relbrtarget_7 : $k)>; 1147 1148// BRHC k 1149// Branch if half carry flag is clear 1150def : InstAlias<"brhc\t$k", (BRBCsk 5, relbrtarget_7 : $k)>; 1151 1152// BRTS k 1153// Branch if the T flag is set 1154def : InstAlias<"brts\t$k", (BRBSsk 6, relbrtarget_7 : $k)>; 1155 1156// BRTC k 1157// Branch if the T flag is clear 1158def : InstAlias<"brtc\t$k", (BRBCsk 6, relbrtarget_7 : $k)>; 1159 1160// BRVS k 1161// Branch if the overflow flag is set 1162def : InstAlias<"brvs\t$k", (BRBSsk 3, relbrtarget_7 : $k)>; 1163 1164// BRVC k 1165// Branch if the overflow flag is clear 1166def : InstAlias<"brvc\t$k", (BRBCsk 3, relbrtarget_7 : $k)>; 1167 1168// BRIE k 1169// Branch if the global interrupt flag is enabled 1170def : InstAlias<"brie\t$k", (BRBSsk 7, relbrtarget_7 : $k)>; 1171 1172// BRID k 1173// Branch if the global interrupt flag is disabled 1174def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>; 1175 1176//===----------------------------------------------------------------------===// 1177// PC-relative conditional branches 1178//===----------------------------------------------------------------------===// 1179// Based on status register. We cannot simplify these into instruction aliases 1180// because we also need to be able to specify a pattern to match for ISel. 1181let isBranch = 1, isTerminator = 1, Uses = [SREG] in { 1182 def BREQk : FBRsk<0, 0b001, (outs), 1183 (ins relbrtarget_7 1184 : $target), 1185 "breq\t$target", [(AVRbrcond bb 1186 : $target, AVR_COND_EQ)]>; 1187 1188 def BRNEk : FBRsk<1, 0b001, (outs), 1189 (ins relbrtarget_7 1190 : $target), 1191 "brne\t$target", [(AVRbrcond bb 1192 : $target, AVR_COND_NE)]>; 1193 1194 def BRSHk : FBRsk<1, 0b000, (outs), 1195 (ins relbrtarget_7 1196 : $target), 1197 "brsh\t$target", [(AVRbrcond bb 1198 : $target, AVR_COND_SH)]>; 1199 1200 def BRLOk : FBRsk<0, 0b000, (outs), 1201 (ins relbrtarget_7 1202 : $target), 1203 "brlo\t$target", [(AVRbrcond bb 1204 : $target, AVR_COND_LO)]>; 1205 1206 def BRMIk : FBRsk<0, 0b010, (outs), 1207 (ins relbrtarget_7 1208 : $target), 1209 "brmi\t$target", [(AVRbrcond bb 1210 : $target, AVR_COND_MI)]>; 1211 1212 def BRPLk : FBRsk<1, 0b010, (outs), 1213 (ins relbrtarget_7 1214 : $target), 1215 "brpl\t$target", [(AVRbrcond bb 1216 : $target, AVR_COND_PL)]>; 1217 1218 def BRGEk : FBRsk<1, 0b100, (outs), 1219 (ins relbrtarget_7 1220 : $target), 1221 "brge\t$target", [(AVRbrcond bb 1222 : $target, AVR_COND_GE)]>; 1223 1224 def BRLTk : FBRsk<0, 0b100, (outs), 1225 (ins relbrtarget_7 1226 : $target), 1227 "brlt\t$target", [(AVRbrcond bb 1228 : $target, AVR_COND_LT)]>; 1229} 1230 1231//===----------------------------------------------------------------------===// 1232// Data transfer instructions 1233//===----------------------------------------------------------------------===// 1234// 8 and 16-bit register move instructions. 1235let hasSideEffects = 0 in { 1236 def MOVRdRr : FRdRr<0b0010, 0b11, 1237 (outs GPR8 1238 : $rd), 1239 (ins GPR8 1240 : $rr), 1241 "mov\t$rd, $rr", []>; 1242 1243 def MOVWRdRr : FMOVWRdRr<(outs DREGS 1244 : $dst), 1245 (ins DREGS 1246 : $src), 1247 "movw\t$dst, $src", []>, 1248 Requires<[HasMOVW]>; 1249} 1250 1251// Load immediate values into registers. 1252let isReMaterializable = 1 in { 1253 def LDIRdK : FRdK<0b1110, 1254 (outs LD8 1255 : $rd), 1256 (ins imm_ldi8 1257 : $k), 1258 "ldi\t$rd, $k", [(set i8 1259 : $rd, imm 1260 : $k)]>; 1261 1262 // LDIW Rd+1:Rd, K+1:K 1263 // 1264 // Expands to: 1265 // ldi Rd, K 1266 // ldi Rd+1, K+1 1267 def LDIWRdK : Pseudo<(outs DLDREGS 1268 : $dst), 1269 (ins i16imm 1270 : $src), 1271 "ldiw\t$dst, $src", [(set i16 1272 : $dst, imm 1273 : $src)]>; 1274} 1275 1276// Load from data space into register. 1277let canFoldAsLoad = 1, isReMaterializable = 1 in { 1278 def LDSRdK : F32DM<0b0, 1279 (outs GPR8 1280 : $rd), 1281 (ins imm16 1282 : $k), 1283 "lds\t$rd, $k", [(set i8 1284 : $rd, (load imm 1285 : $k))]>, 1286 Requires<[HasSRAM]>; 1287 1288 // LDSW Rd+1:Rd, K+1:K 1289 // 1290 // Expands to: 1291 // lds Rd, (K+1:K) 1292 // lds Rd+1 (K+1:K) + 1 1293 def LDSWRdK : Pseudo<(outs DREGS 1294 : $dst), 1295 (ins i16imm 1296 : $src), 1297 "ldsw\t$dst, $src", [(set i16 1298 : $dst, (load imm 1299 : $src))]>, 1300 Requires<[HasSRAM]>; 1301} 1302 1303// Indirect loads. 1304let canFoldAsLoad = 1, isReMaterializable = 1 in { 1305 def LDRdPtr : FSTLD<0, 0b00, 1306 (outs GPR8 1307 : $reg), 1308 (ins LDSTPtrReg 1309 : $ptrreg), 1310 "ld\t$reg, $ptrreg", [(set GPR8 1311 : $reg, (load i16 1312 : $ptrreg))]>, 1313 Requires<[HasSRAM]>; 1314 1315 // LDW Rd+1:Rd, P 1316 // 1317 // Expands to: 1318 // ld Rd, P 1319 // ldd Rd+1, P+1 1320 let Constraints = "@earlyclobber $reg" in def LDWRdPtr 1321 : Pseudo<(outs DREGS 1322 : $reg), 1323 (ins PTRDISPREGS 1324 : $ptrreg), 1325 "ldw\t$reg, $ptrreg", [(set i16 1326 : $reg, (load i16 1327 : $ptrreg))]>, 1328 Requires<[HasSRAM]>; 1329} 1330 1331// Indirect loads (with postincrement or predecrement). 1332let mayLoad = 1, hasSideEffects = 0, 1333 Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in { 1334 def LDRdPtrPi : FSTLD<0, 0b01, 1335 (outs GPR8 1336 : $reg, PTRREGS 1337 : $base_wb), 1338 (ins LDSTPtrReg 1339 : $ptrreg), 1340 "ld\t$reg, $ptrreg+", []>, 1341 Requires<[HasSRAM]>; 1342 1343 // LDW Rd+1:Rd, P+ 1344 // Expands to: 1345 // ld Rd, P+ 1346 // ld Rd+1, P+ 1347 def LDWRdPtrPi : Pseudo<(outs DREGS 1348 : $reg, PTRREGS 1349 : $base_wb), 1350 (ins PTRREGS 1351 : $ptrreg), 1352 "ldw\t$reg, $ptrreg+", []>, 1353 Requires<[HasSRAM]>; 1354 1355 def LDRdPtrPd : FSTLD<0, 0b10, 1356 (outs GPR8 1357 : $reg, PTRREGS 1358 : $base_wb), 1359 (ins LDSTPtrReg 1360 : $ptrreg), 1361 "ld\t$reg, -$ptrreg", []>, 1362 Requires<[HasSRAM]>; 1363 1364 // LDW Rd+1:Rd, -P 1365 // 1366 // Expands to: 1367 // ld Rd+1, -P 1368 // ld Rd, -P 1369 def LDWRdPtrPd : Pseudo<(outs DREGS 1370 : $reg, PTRREGS 1371 : $base_wb), 1372 (ins PTRREGS 1373 : $ptrreg), 1374 "ldw\t$reg, -$ptrreg", []>, 1375 Requires<[HasSRAM]>; 1376} 1377 1378// Load indirect with displacement operations. 1379let canFoldAsLoad = 1, isReMaterializable = 1 in { 1380 let Constraints = "@earlyclobber $reg" in def LDDRdPtrQ 1381 : FSTDLDD<0, 1382 (outs GPR8 1383 : $reg), 1384 (ins memri 1385 : $memri), 1386 "ldd\t$reg, $memri", [(set i8 1387 : $reg, (load addr 1388 : $memri))]>, 1389 Requires<[HasSRAM]>; 1390 1391 // LDDW Rd+1:Rd, P+q 1392 // 1393 // Expands to: 1394 // ldd Rd, P+q 1395 // ldd Rd+1, P+q+1 1396 let Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ 1397 : Pseudo<(outs DREGS 1398 : $dst), 1399 (ins memri 1400 : $memri), 1401 "lddw\t$dst, $memri", [(set i16 1402 : $dst, (load addr 1403 : $memri))]>, 1404 Requires<[HasSRAM]>; 1405 1406 // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y 1407 // register and without the @earlyclobber flag. 1408 // 1409 // Used to work around a bug caused by the register allocator not 1410 // being able to handle the expansion of a COPY into an machine instruction 1411 // that has an earlyclobber flag. This is because the register allocator will 1412 // try expand a copy from a register slot into an earlyclobber instruction. 1413 // Instructions that are earlyclobber need to be in a dedicated earlyclobber 1414 // slot. 1415 // 1416 // This pseudo instruction can be used pre-AVR pseudo expansion in order to 1417 // get a frame index load without directly using earlyclobber instructions. 1418 // 1419 // The pseudo expansion pass trivially expands this into LDDWRdPtrQ. 1420 // 1421 // This instruction may be removed once PR13375 is fixed. 1422 let mayLoad = 1, 1423 hasSideEffects = 0 in def LDDWRdYQ : Pseudo<(outs DREGS 1424 : $dst), 1425 (ins memri 1426 : $memri), 1427 "lddw\t$dst, $memri", []>, 1428 Requires<[HasSRAM]>; 1429} 1430 1431class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC> 1432 : Pseudo<(outs DRC 1433 : $rd), 1434 (ins PTRRC 1435 : $rr), 1436 "atomic_op", [(set DRC 1437 : $rd, (Op i16 1438 : $rr))]>; 1439 1440class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC> 1441 : Pseudo<(outs), 1442 (ins PTRRC 1443 : $rd, DRC 1444 : $rr), 1445 "atomic_op", [(Op i16 1446 : $rd, DRC 1447 : $rr)]>; 1448 1449let Constraints = 1450 "@earlyclobber $rd" in class AtomicLoadOp<PatFrag Op, RegisterClass DRC, 1451 RegisterClass PTRRC> 1452 : Pseudo<(outs DRC 1453 : $rd), 1454 (ins PTRRC 1455 : $rr, DRC 1456 : $operand), 1457 "atomic_op", [(set DRC 1458 : $rd, (Op i16 1459 : $rr, DRC 1460 : $operand))]>; 1461 1462// FIXME: I think 16-bit atomic binary ops need to mark 1463// r0 as clobbered. 1464 1465// Atomic instructions 1466// =================== 1467// 1468// These are all expanded by AVRExpandPseudoInsts 1469// 1470// 8-bit operations can use any pointer register because 1471// they are expanded directly into an LD/ST instruction. 1472// 1473// 16-bit operations use 16-bit load/store postincrement instructions, 1474// which require PTRDISPREGS. 1475 1476def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>; 1477def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>; 1478 1479def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>; 1480def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>; 1481 1482class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>; 1483class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>; 1484 1485def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>; 1486def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>; 1487def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>; 1488def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>; 1489def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>; 1490def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>; 1491def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>; 1492def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>; 1493def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>; 1494def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>; 1495def AtomicFence 1496 : Pseudo<(outs), (ins), "atomic_fence", [(atomic_fence timm, timm)]>; 1497 1498// Indirect store from register to data space. 1499def STSKRr : F32DM<0b1, (outs), 1500 (ins imm16 1501 : $k, GPR8 1502 : $rd), 1503 "sts\t$k, $rd", [(store i8 1504 : $rd, imm 1505 : $k)]>, 1506 Requires<[HasSRAM]>; 1507 1508// STSW K+1:K, Rr+1:Rr 1509// 1510// Expands to: 1511// sts Rr+1, (K+1:K) + 1 1512// sts Rr, (K+1:K) 1513def STSWKRr : Pseudo<(outs), 1514 (ins i16imm 1515 : $dst, DREGS 1516 : $src), 1517 "stsw\t$dst, $src", [(store i16 1518 : $src, imm 1519 : $dst)]>, 1520 Requires<[HasSRAM]>; 1521 1522// Indirect stores. 1523// ST P, Rr 1524// Stores the value of Rr into the location addressed by pointer P. 1525def STPtrRr : FSTLD<1, 0b00, (outs), 1526 (ins LDSTPtrReg 1527 : $ptrreg, GPR8 1528 : $reg), 1529 "st\t$ptrreg, $reg", [(store GPR8 1530 : $reg, i16 1531 : $ptrreg)]>, 1532 Requires<[HasSRAM]>; 1533 1534// STW P, Rr+1:Rr 1535// Stores the value of Rr into the location addressed by pointer P. 1536// 1537// Expands to: 1538// st P, Rr 1539// std P+1, Rr+1 1540def STWPtrRr : Pseudo<(outs), 1541 (ins PTRDISPREGS 1542 : $ptrreg, DREGS 1543 : $reg), 1544 "stw\t$ptrreg, $reg", [(store i16 1545 : $reg, i16 1546 : $ptrreg)]>, 1547 Requires<[HasSRAM]>; 1548 1549// Indirect stores (with postincrement or predecrement). 1550let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in { 1551 1552 // ST P+, Rr 1553 // Stores the value of Rr into the location addressed by pointer P. 1554 // Post increments P. 1555 def STPtrPiRr : FSTLD<1, 0b01, 1556 (outs LDSTPtrReg 1557 : $base_wb), 1558 (ins LDSTPtrReg 1559 : $ptrreg, GPR8 1560 : $reg, i8imm 1561 : $offs), 1562 "st\t$ptrreg+, $reg", [(set i16 1563 : $base_wb, (post_store GPR8 1564 : $reg, i16 1565 : $ptrreg, imm 1566 : $offs))]>, 1567 Requires<[HasSRAM]>; 1568 1569 // STW P+, Rr+1:Rr 1570 // Stores the value of Rr into the location addressed by pointer P. 1571 // Post increments P. 1572 // 1573 // Expands to: 1574 // st P+, Rr 1575 // st P+, Rr+1 1576 def STWPtrPiRr : Pseudo<(outs PTRREGS 1577 : $base_wb), 1578 (ins PTRREGS 1579 : $ptrreg, DREGS 1580 : $trh, i8imm 1581 : $offs), 1582 "stw\t$ptrreg+, $trh", [(set PTRREGS 1583 : $base_wb, (post_store DREGS 1584 : $trh, PTRREGS 1585 : $ptrreg, imm 1586 : $offs))]>, 1587 Requires<[HasSRAM]>; 1588 1589 // ST -P, Rr 1590 // Stores the value of Rr into the location addressed by pointer P. 1591 // Pre decrements P. 1592 def STPtrPdRr : FSTLD<1, 0b10, 1593 (outs LDSTPtrReg 1594 : $base_wb), 1595 (ins LDSTPtrReg 1596 : $ptrreg, GPR8 1597 : $reg, i8imm 1598 : $offs), 1599 "st\t-$ptrreg, $reg", [(set i16 1600 : $base_wb, (pre_store GPR8 1601 : $reg, i16 1602 : $ptrreg, imm 1603 : $offs))]>, 1604 Requires<[HasSRAM]>; 1605 1606 // STW -P, Rr+1:Rr 1607 // Stores the value of Rr into the location addressed by pointer P. 1608 // Pre decrements P. 1609 // 1610 // Expands to: 1611 // st -P, Rr+1 1612 // st -P, Rr 1613 def STWPtrPdRr : Pseudo<(outs PTRREGS 1614 : $base_wb), 1615 (ins PTRREGS 1616 : $ptrreg, DREGS 1617 : $reg, i8imm 1618 : $offs), 1619 "stw\t-$ptrreg, $reg", [(set PTRREGS 1620 : $base_wb, (pre_store i16 1621 : $reg, i16 1622 : $ptrreg, imm 1623 : $offs))]>, 1624 Requires<[HasSRAM]>; 1625} 1626 1627// Store indirect with displacement operations. 1628// STD P+q, Rr 1629// Stores the value of Rr into the location addressed by pointer P with a 1630// displacement of q. Does not modify P. 1631def STDPtrQRr : FSTDLDD<1, (outs), 1632 (ins memri 1633 : $memri, GPR8 1634 : $reg), 1635 "std\t$memri, $reg", [(store i8 1636 : $reg, addr 1637 : $memri)]>, 1638 Requires<[HasSRAM]>; 1639 1640// STDW P+q, Rr+1:Rr 1641// Stores the value of Rr into the location addressed by pointer P with a 1642// displacement of q. Does not modify P. 1643// 1644// Expands to: 1645// std P+q, Rr 1646// std P+q+1, Rr+1 1647def STDWPtrQRr : Pseudo<(outs), 1648 (ins memri 1649 : $memri, DREGS 1650 : $src), 1651 "stdw\t$memri, $src", [(store i16 1652 : $src, addr 1653 : $memri)]>, 1654 Requires<[HasSRAM]>; 1655 1656// Load program memory operations. 1657let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1, 1658 hasSideEffects = 0 in { 1659 let Defs = [R0], 1660 Uses = [R31R30] in def LPM 1661 : F16<0b1001010111001000, (outs), (ins), "lpm", []>, 1662 Requires<[HasLPM]>; 1663 1664 def LPMRdZ : FLPMX<0, 0, 1665 (outs GPR8 1666 : $dst), 1667 (ins ZREG 1668 : $z), 1669 "lpm\t$dst, $z", []>, 1670 Requires<[HasLPMX]>; 1671 1672 // Load program memory, while postincrementing the Z register. 1673 let Defs = [R31R30] in { 1674 def LPMRdZPi : FLPMX<0, 1, 1675 (outs GPR8 1676 : $dst), 1677 (ins ZREG 1678 : $z), 1679 "lpm\t$dst, $z+", []>, 1680 Requires<[HasLPMX]>; 1681 1682 def LPMWRdZ : Pseudo<(outs DREGS 1683 : $dst), 1684 (ins ZREG 1685 : $z), 1686 "lpmw\t$dst, $z", []>, 1687 Requires<[HasLPMX]>; 1688 1689 def LPMWRdZPi : Pseudo<(outs DREGS 1690 : $dst), 1691 (ins ZREG 1692 : $z), 1693 "lpmw\t$dst, $z+", []>, 1694 Requires<[HasLPMX]>; 1695 } 1696} 1697 1698// Extended load program memory operations. 1699let mayLoad = 1, hasSideEffects = 0 in { 1700 let Defs = [R0], 1701 Uses = [R31R30] in def ELPM 1702 : F16<0b1001010111011000, (outs), (ins), "elpm", []>, 1703 Requires<[HasELPM]>; 1704 1705 def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$dst), (ins ZREG:$z), 1706 "elpm\t$dst, $z", []>, 1707 Requires<[HasELPMX]>; 1708 1709 let Defs = [R31R30] in { 1710 def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$dst), (ins ZREG:$z), 1711 "elpm\t$dst, $z+", []>, 1712 Requires<[HasELPMX]>; 1713 } 1714 1715 // These pseudos are combination of the OUT and ELPM instructions. 1716 let Defs = [R31R30], hasSideEffects = 1 in { 1717 def ELPMBRdZ : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p), 1718 "elpmb\t$dst, $z, $p", []>, 1719 Requires<[HasELPMX]>; 1720 1721 def ELPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p), 1722 "elpmw\t$dst, $z, $p", []>, 1723 Requires<[HasELPMX]>; 1724 1725 def ELPMBRdZPi : Pseudo<(outs GPR8:$dst), (ins ZREG:$z, LD8:$p), 1726 "elpmb\t$dst, $z+, $p", []>, 1727 Requires<[HasELPMX]>; 1728 1729 def ELPMWRdZPi : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p), 1730 "elpmw\t$dst, $z+, $p", []>, 1731 Requires<[HasELPMX]>; 1732 } 1733} 1734 1735// Store program memory operations. 1736let Uses = [R1, R0] in { 1737 let Uses = [R31R30, R1, R0] in def SPM 1738 : F16<0b1001010111101000, (outs), (ins), "spm", []>, 1739 Requires<[HasSPM]>; 1740 1741 let Defs = [R31R30] in def SPMZPi : F16<0b1001010111111000, (outs), 1742 (ins ZREG 1743 : $z), 1744 "spm $z+", []>, 1745 Requires<[HasSPMX]>; 1746} 1747 1748// Read data from IO location operations. 1749let canFoldAsLoad = 1, isReMaterializable = 1 in { 1750 def INRdA : FIORdA<(outs GPR8 1751 : $dst), 1752 (ins imm_port6 1753 : $src), 1754 "in\t$dst, $src", [(set i8 1755 : $dst, (load ioaddr8 1756 : $src))]>; 1757 1758 def INWRdA : Pseudo<(outs DREGS 1759 : $dst), 1760 (ins imm_port6 1761 : $src), 1762 "inw\t$dst, $src", [(set i16 1763 : $dst, (load ioaddr16 1764 : $src))]>; 1765} 1766 1767// Write data to IO location operations. 1768def OUTARr : FIOARr<(outs), 1769 (ins imm_port6 1770 : $dst, GPR8 1771 : $src), 1772 "out\t$dst, $src", [(store i8 1773 : $src, ioaddr8 1774 : $dst)]>; 1775 1776def OUTWARr : Pseudo<(outs), 1777 (ins imm_port6 1778 : $dst, DREGS 1779 : $src), 1780 "outw\t$dst, $src", [(store i16 1781 : $src, ioaddr16 1782 : $dst)]>; 1783 1784// Stack push/pop operations. 1785let Defs = [SP], Uses = [SP], hasSideEffects = 0 in { 1786 // Stack push operations. 1787 let mayStore = 1 in { 1788 def PUSHRr : FRd<0b1001, 0b0011111, (outs), 1789 (ins GPR8 1790 : $reg), 1791 "push\t$reg", []>, 1792 Requires<[HasSRAM]>; 1793 1794 def PUSHWRr : Pseudo<(outs), 1795 (ins DREGS 1796 : $reg), 1797 "pushw\t$reg", []>, 1798 Requires<[HasSRAM]>; 1799 } 1800 1801 // Stack pop operations. 1802 let mayLoad = 1 in { 1803 def POPRd : FRd<0b1001, 0b0001111, 1804 (outs GPR8 1805 : $reg), 1806 (ins), "pop\t$reg", []>, 1807 Requires<[HasSRAM]>; 1808 1809 def POPWRd : Pseudo<(outs DREGS 1810 : $reg), 1811 (ins), "popw\t$reg", []>, 1812 Requires<[HasSRAM]>; 1813 } 1814} 1815 1816// Read-Write-Modify (RMW) instructions. 1817def XCHZRd : FZRd<0b100, 1818 (outs GPR8 1819 : $rd), 1820 (ins ZREG 1821 : $z), 1822 "xch\t$z, $rd", []>, 1823 Requires<[SupportsRMW]>; 1824 1825def LASZRd : FZRd<0b101, 1826 (outs GPR8 1827 : $rd), 1828 (ins ZREG 1829 : $z), 1830 "las\t$z, $rd", []>, 1831 Requires<[SupportsRMW]>; 1832 1833def LACZRd : FZRd<0b110, 1834 (outs GPR8 1835 : $rd), 1836 (ins ZREG 1837 : $z), 1838 "lac\t$z, $rd", []>, 1839 Requires<[SupportsRMW]>; 1840 1841def LATZRd : FZRd<0b111, 1842 (outs GPR8 1843 : $rd), 1844 (ins ZREG 1845 : $z), 1846 "lat\t$z, $rd", []>, 1847 Requires<[SupportsRMW]>; 1848 1849//===----------------------------------------------------------------------===// 1850// Bit and bit-test instructions 1851//===----------------------------------------------------------------------===// 1852 1853// Bit shift/rotate operations. 1854let Constraints = "$src = $rd", Defs = [SREG] in { 1855 // 8-bit LSL is an alias of ADD Rd, Rd 1856 1857 def LSLWRd : Pseudo<(outs DREGS 1858 : $rd), 1859 (ins DREGS 1860 : $src), 1861 "lslw\t$rd", 1862 [(set i16 1863 : $rd, (AVRlsl i16 1864 : $src)), 1865 (implicit SREG)]>; 1866 1867 def LSLWHiRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lslwhi\t$rd", 1868 [(set i16:$rd, (AVRlslhi i16:$src)), (implicit SREG)]>; 1869 1870 def LSLWNRd : Pseudo<(outs DLDREGS 1871 : $rd), 1872 (ins DREGS 1873 : $src, imm16 1874 : $bits), 1875 "lslwn\t$rd, $bits", [ 1876 (set i16 1877 : $rd, (AVRlslwn i16 1878 : $src, imm 1879 : $bits)), 1880 (implicit SREG) 1881 ]>; 1882 1883 def LSLBNRd : Pseudo<(outs LD8 1884 : $rd), 1885 (ins GPR8 1886 : $src, imm_ldi8 1887 : $bits), 1888 "lslbn\t$rd, $bits", [ 1889 (set i8 1890 : $rd, (AVRlslbn i8 1891 : $src, imm 1892 : $bits)), 1893 (implicit SREG) 1894 ]>; 1895 1896 def LSRRd 1897 : FRd<0b1001, 0b0100110, 1898 (outs GPR8 1899 : $rd), 1900 (ins GPR8 1901 : $src), 1902 "lsr\t$rd", [(set i8 1903 : $rd, (AVRlsr i8 1904 : $src)), 1905 (implicit SREG)]>; 1906 1907 def LSRWRd : Pseudo<(outs DREGS 1908 : $rd), 1909 (ins DREGS 1910 : $src), 1911 "lsrw\t$rd", 1912 [(set i16 1913 : $rd, (AVRlsr i16 1914 : $src)), 1915 (implicit SREG)]>; 1916 1917 def LSRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "lsrwlo\t$rd", 1918 [(set i16:$rd, (AVRlsrlo i16:$src)), (implicit SREG)]>; 1919 1920 def LSRWNRd : Pseudo<(outs DLDREGS 1921 : $rd), 1922 (ins DREGS 1923 : $src, imm16 1924 : $bits), 1925 "lsrwn\t$rd, $bits", [ 1926 (set i16 1927 : $rd, (AVRlsrwn i16 1928 : $src, imm 1929 : $bits)), 1930 (implicit SREG) 1931 ]>; 1932 1933 def LSRBNRd : Pseudo<(outs LD8 1934 : $rd), 1935 (ins GPR8 1936 : $src, imm_ldi8 1937 : $bits), 1938 "lsrbn\t$rd, $bits", [ 1939 (set i8 1940 : $rd, (AVRlsrbn i8 1941 : $src, imm 1942 : $bits)), 1943 (implicit SREG) 1944 ]>; 1945 1946 def ASRRd 1947 : FRd<0b1001, 0b0100101, 1948 (outs GPR8 1949 : $rd), 1950 (ins GPR8 1951 : $src), 1952 "asr\t$rd", [(set i8 1953 : $rd, (AVRasr i8 1954 : $src)), 1955 (implicit SREG)]>; 1956 1957 def ASRWNRd : Pseudo<(outs DLDREGS 1958 : $rd), 1959 (ins DREGS 1960 : $src, imm16 1961 : $bits), 1962 "asrwn\t$rd, $bits", [ 1963 (set i16 1964 : $rd, (AVRasrwn i16 1965 : $src, imm 1966 : $bits)), 1967 (implicit SREG) 1968 ]>; 1969 1970 def ASRBNRd : Pseudo<(outs LD8 1971 : $rd), 1972 (ins GPR8 1973 : $src, imm_ldi8 1974 : $bits), 1975 "asrbn\t$rd, $bits", [ 1976 (set i8 1977 : $rd, (AVRasrbn i8 1978 : $src, imm 1979 : $bits)), 1980 (implicit SREG) 1981 ]>; 1982 1983 def ASRWRd : Pseudo<(outs DREGS 1984 : $rd), 1985 (ins DREGS 1986 : $src), 1987 "asrw\t$rd", 1988 [(set i16 1989 : $rd, (AVRasr i16 1990 : $src)), 1991 (implicit SREG)]>; 1992 1993 def ASRWLoRd : Pseudo<(outs DREGS:$rd), (ins DREGS:$src), "asrwlo\t$rd", 1994 [(set i16:$rd, (AVRasrlo i16:$src)), (implicit SREG)]>; 1995 1996 def ROLBRd : Pseudo<(outs GPR8 1997 : $rd), 1998 (ins GPR8 1999 : $src), 2000 "rolb\t$rd", 2001 [(set i8 2002 : $rd, (AVRrol i8 2003 : $src)), 2004 (implicit SREG)]>; 2005 2006 def RORBRd : Pseudo<(outs GPR8 2007 : $rd), 2008 (ins GPR8 2009 : $src), 2010 "rorb\t$rd", 2011 [(set i8 2012 : $rd, (AVRror i8 2013 : $src)), 2014 (implicit SREG)]>; 2015 2016 // Bit rotate operations. 2017 let Uses = [SREG] in { 2018 2019 def ROLWRd 2020 : Pseudo<(outs DREGS 2021 : $rd), 2022 (ins DREGS 2023 : $src), 2024 "rolw\t$rd", 2025 [(set i16 2026 : $rd, (AVRrol i16 2027 : $src)), 2028 (implicit SREG)]>; 2029 2030 def RORRd : FRd<0b1001, 0b0100111, 2031 (outs GPR8 2032 : $rd), 2033 (ins GPR8 2034 : $src), 2035 "ror\t$rd", []>; 2036 2037 def RORWRd 2038 : Pseudo<(outs DREGS 2039 : $rd), 2040 (ins DREGS 2041 : $src), 2042 "rorw\t$rd", 2043 [(set i16 2044 : $rd, (AVRror i16 2045 : $src)), 2046 (implicit SREG)]>; 2047 } 2048} 2049 2050// SWAP Rd 2051// Swaps the high and low nibbles in a register. 2052let Constraints = 2053 "$src = $rd" in def SWAPRd : FRd<0b1001, 0b0100010, 2054 (outs GPR8 2055 : $rd), 2056 (ins GPR8 2057 : $src), 2058 "swap\t$rd", [(set i8 2059 : $rd, (AVRSwap i8 2060 : $src))]>; 2061 2062// IO register bit set/clear operations. 2063//: TODO: add patterns when popcount(imm)==2 to be expanded with 2 sbi/cbi 2064// instead of in+ori+out which requires one more instr. 2065def SBIAb : FIOBIT<0b10, (outs), 2066 (ins imm_port5 2067 : $addr, i8imm 2068 : $bit), 2069 "sbi\t$addr, $bit", [(store(or(i8(load lowioaddr8 2070 : $addr)), 2071 iobitpos8 2072 : $bit), 2073 lowioaddr8 2074 : $addr)]>; 2075 2076def CBIAb : FIOBIT<0b00, (outs), 2077 (ins imm_port5 2078 : $addr, i8imm 2079 : $bit), 2080 "cbi\t$addr, $bit", [(store(and(i8(load lowioaddr8 2081 : $addr)), 2082 iobitposn8 2083 : $bit), 2084 lowioaddr8 2085 : $addr)]>; 2086 2087// Status register bit load/store operations. 2088let Defs = [SREG] in def BST : FRdB<0b01, (outs), 2089 (ins GPR8 2090 : $rd, i8imm 2091 : $b), 2092 "bst\t$rd, $b", []>; 2093 2094let Constraints = "$src = $rd", 2095 Uses = [SREG] in def BLD : FRdB<0b00, 2096 (outs GPR8 2097 : $rd), 2098 (ins GPR8 2099 : $src, i8imm 2100 : $b), 2101 "bld\t$rd, $b", []>; 2102 2103def CBR : InstAlias<"cbr\t$rd, $k", (ANDIRdK LD8 : $rd, imm_com8 : $k), 0>; 2104 2105// CLR Rd 2106// Alias for EOR Rd, Rd 2107// ------------- 2108// Clears all bits in a register. 2109def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8 : $rd, GPR8 : $rd)>; 2110 2111// LSL Rd 2112// Alias for ADD Rd, Rd 2113// -------------- 2114// Logical shift left one bit. 2115def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>; 2116 2117def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>; 2118 2119// SER Rd 2120// Alias for LDI Rd, 0xff 2121// --------- 2122// Sets all bits in a register. 2123def : InstAlias<"ser\t$rd", (LDIRdK LD8 : $rd, 0xff), 0>; 2124 2125let Defs = [SREG] in def BSETs : FS<0, (outs), 2126 (ins i8imm 2127 : $s), 2128 "bset\t$s", []>; 2129 2130let Defs = [SREG] in def BCLRs : FS<1, (outs), 2131 (ins i8imm 2132 : $s), 2133 "bclr\t$s", []>; 2134 2135// Set/clear aliases for the carry (C) status flag (bit 0). 2136def : InstAlias<"sec", (BSETs 0)>; 2137def : InstAlias<"clc", (BCLRs 0)>; 2138 2139// Set/clear aliases for the zero (Z) status flag (bit 1). 2140def : InstAlias<"sez", (BSETs 1)>; 2141def : InstAlias<"clz", (BCLRs 1)>; 2142 2143// Set/clear aliases for the negative (N) status flag (bit 2). 2144def : InstAlias<"sen", (BSETs 2)>; 2145def : InstAlias<"cln", (BCLRs 2)>; 2146 2147// Set/clear aliases for the overflow (V) status flag (bit 3). 2148def : InstAlias<"sev", (BSETs 3)>; 2149def : InstAlias<"clv", (BCLRs 3)>; 2150 2151// Set/clear aliases for the signed (S) status flag (bit 4). 2152def : InstAlias<"ses", (BSETs 4)>; 2153def : InstAlias<"cls", (BCLRs 4)>; 2154 2155// Set/clear aliases for the half-carry (H) status flag (bit 5). 2156def : InstAlias<"seh", (BSETs 5)>; 2157def : InstAlias<"clh", (BCLRs 5)>; 2158 2159// Set/clear aliases for the T status flag (bit 6). 2160def : InstAlias<"set", (BSETs 6)>; 2161def : InstAlias<"clt", (BCLRs 6)>; 2162 2163// Set/clear aliases for the interrupt (I) status flag (bit 7). 2164def : InstAlias<"sei", (BSETs 7)>; 2165def : InstAlias<"cli", (BCLRs 7)>; 2166 2167//===----------------------------------------------------------------------===// 2168// Special/Control instructions 2169//===----------------------------------------------------------------------===// 2170 2171// BREAK 2172// Breakpoint instruction 2173// --------- 2174// <|1001|0101|1001|1000> 2175def BREAK : F16<0b1001010110011000, (outs), (ins), "break", []>, 2176 Requires<[HasBREAK]>; 2177 2178// NOP 2179// No-operation instruction 2180// --------- 2181// <|0000|0000|0000|0000> 2182def NOP : F16<0b0000000000000000, (outs), (ins), "nop", []>; 2183 2184// SLEEP 2185// Sleep instruction 2186// --------- 2187// <|1001|0101|1000|1000> 2188def SLEEP : F16<0b1001010110001000, (outs), (ins), "sleep", []>; 2189 2190// WDR 2191// Watchdog reset 2192// --------- 2193// <|1001|0101|1010|1000> 2194def WDR : F16<0b1001010110101000, (outs), (ins), "wdr", []>; 2195 2196//===----------------------------------------------------------------------===// 2197// Pseudo instructions for later expansion 2198//===----------------------------------------------------------------------===// 2199 2200//: TODO: Optimize this for wider types AND optimize the following code 2201// compile int foo(char a, char b, char c, char d) {return d+b;} 2202// looks like a missed sext_inreg opportunity. 2203def SEXT 2204 : ExtensionPseudo<(outs DREGS 2205 : $dst), 2206 (ins GPR8 2207 : $src), 2208 "sext\t$dst, $src", 2209 [(set i16 2210 : $dst, (sext i8 2211 : $src)), 2212 (implicit SREG)]>; 2213 2214def ZEXT 2215 : ExtensionPseudo<(outs DREGS 2216 : $dst), 2217 (ins GPR8 2218 : $src), 2219 "zext\t$dst, $src", 2220 [(set i16 2221 : $dst, (zext i8 2222 : $src)), 2223 (implicit SREG)]>; 2224 2225// This pseudo gets expanded into a movw+adiw thus it clobbers SREG. 2226let Defs = [SREG], 2227 hasSideEffects = 0 in def FRMIDX : Pseudo<(outs DLDREGS 2228 : $dst), 2229 (ins DLDREGS 2230 : $src, i16imm 2231 : $src2), 2232 "frmidx\t$dst, $src, $src2", []>; 2233 2234// This pseudo is either converted to a regular store or a push which clobbers 2235// SP. 2236def STDSPQRr : StorePseudo<(outs), 2237 (ins memspi 2238 : $dst, GPR8 2239 : $src), 2240 "stdstk\t$dst, $src", [(store i8 2241 : $src, addr 2242 : $dst)]>; 2243 2244// This pseudo is either converted to a regular store or a push which clobbers 2245// SP. 2246def STDWSPQRr : StorePseudo<(outs), 2247 (ins memspi 2248 : $dst, DREGS 2249 : $src), 2250 "stdwstk\t$dst, $src", [(store i16 2251 : $src, addr 2252 : $dst)]>; 2253 2254// SP read/write pseudos. 2255let hasSideEffects = 0 in { 2256 let Uses = [SP] in def SPREAD : Pseudo<(outs DREGS 2257 : $dst), 2258 (ins GPRSP 2259 : $src), 2260 "spread\t$dst, $src", []>; 2261 2262 let Defs = [SP] in def SPWRITE : Pseudo<(outs GPRSP 2263 : $dst), 2264 (ins DREGS 2265 : $src), 2266 "spwrite\t$dst, $src", []>; 2267} 2268 2269def Select8 : SelectPseudo<(outs GPR8 2270 : $dst), 2271 (ins GPR8 2272 : $src, GPR8 2273 : $src2, i8imm 2274 : $cc), 2275 "# Select8 PSEUDO", [(set i8 2276 : $dst, (AVRselectcc i8 2277 : $src, i8 2278 : $src2, imm 2279 : $cc))]>; 2280 2281def Select16 : SelectPseudo<(outs DREGS 2282 : $dst), 2283 (ins DREGS 2284 : $src, DREGS 2285 : $src2, i8imm 2286 : $cc), 2287 "# Select16 PSEUDO", [(set i16 2288 : $dst, (AVRselectcc i16 2289 : $src, i16 2290 : $src2, imm 2291 : $cc))]>; 2292 2293def Lsl8 : ShiftPseudo<(outs GPR8 2294 : $dst), 2295 (ins GPR8 2296 : $src, GPR8 2297 : $cnt), 2298 "# Lsl8 PSEUDO", [(set i8 2299 : $dst, (AVRlslLoop i8 2300 : $src, i8 2301 : $cnt))]>; 2302 2303def Lsl16 : ShiftPseudo<(outs DREGS 2304 : $dst), 2305 (ins DREGS 2306 : $src, GPR8 2307 : $cnt), 2308 "# Lsl16 PSEUDO", [(set i16 2309 : $dst, (AVRlslLoop i16 2310 : $src, i8 2311 : $cnt))]>; 2312 2313def Lsr8 : ShiftPseudo<(outs GPR8 2314 : $dst), 2315 (ins GPR8 2316 : $src, GPR8 2317 : $cnt), 2318 "# Lsr8 PSEUDO", [(set i8 2319 : $dst, (AVRlsrLoop i8 2320 : $src, i8 2321 : $cnt))]>; 2322 2323def Lsr16 : ShiftPseudo<(outs DREGS 2324 : $dst), 2325 (ins DREGS 2326 : $src, GPR8 2327 : $cnt), 2328 "# Lsr16 PSEUDO", [(set i16 2329 : $dst, (AVRlsrLoop i16 2330 : $src, i8 2331 : $cnt))]>; 2332 2333def Rol8 : ShiftPseudo<(outs GPR8 2334 : $dst), 2335 (ins GPR8 2336 : $src, GPR8 2337 : $cnt), 2338 "# Rol8 PSEUDO", [(set i8 2339 : $dst, (AVRrolLoop i8 2340 : $src, i8 2341 : $cnt))]>; 2342 2343def Rol16 : ShiftPseudo<(outs DREGS 2344 : $dst), 2345 (ins DREGS 2346 : $src, GPR8 2347 : $cnt), 2348 "# Rol16 PSEUDO", [(set i16 2349 : $dst, (AVRrolLoop i16 2350 : $src, i8 2351 : $cnt))]>; 2352 2353def Ror8 : ShiftPseudo<(outs GPR8 2354 : $dst), 2355 (ins GPR8 2356 : $src, GPR8 2357 : $cnt), 2358 "# Ror8 PSEUDO", [(set i8 2359 : $dst, (AVRrorLoop i8 2360 : $src, i8 2361 : $cnt))]>; 2362 2363def Ror16 : ShiftPseudo<(outs DREGS 2364 : $dst), 2365 (ins DREGS 2366 : $src, GPR8 2367 : $cnt), 2368 "# Ror16 PSEUDO", [(set i16 2369 : $dst, (AVRrorLoop i16 2370 : $src, i8 2371 : $cnt))]>; 2372 2373def Asr8 : ShiftPseudo<(outs GPR8 2374 : $dst), 2375 (ins GPR8 2376 : $src, GPR8 2377 : $cnt), 2378 "# Asr8 PSEUDO", [(set i8 2379 : $dst, (AVRasrLoop i8 2380 : $src, i8 2381 : $cnt))]>; 2382 2383def Asr16 : ShiftPseudo<(outs DREGS 2384 : $dst), 2385 (ins DREGS 2386 : $src, GPR8 2387 : $cnt), 2388 "# Asr16 PSEUDO", [(set i16 2389 : $dst, (AVRasrLoop i16 2390 : $src, i8 2391 : $cnt))]>; 2392 2393// lowered to a copy from R1, which contains the value zero. 2394let usesCustomInserter=1 in 2395def CopyR1 : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>; 2396 2397//===----------------------------------------------------------------------===// 2398// Non-Instruction Patterns 2399//===----------------------------------------------------------------------===// 2400 2401//: TODO: look in x86InstrCompiler.td for odd encoding trick related to 2402// add x, 128 -> sub x, -128. Clang is emitting an eor for this (ldi+eor) 2403 2404// the add instruction always writes the carry flag 2405def : Pat<(addc i8 : $src, i8 : $src2), (ADDRdRr i8 : $src, i8 : $src2)>; 2406def : Pat<(addc DREGS 2407 : $src, DREGS 2408 : $src2), 2409 (ADDWRdRr DREGS 2410 : $src, DREGS 2411 : $src2)>; 2412 2413// all sub instruction variants always writes the carry flag 2414def : Pat<(subc i8 : $src, i8 : $src2), (SUBRdRr i8 : $src, i8 : $src2)>; 2415def : Pat<(subc i16 : $src, i16 : $src2), (SUBWRdRr i16 : $src, i16 : $src2)>; 2416def : Pat<(subc i8 : $src, imm : $src2), (SUBIRdK i8 : $src, imm : $src2)>; 2417def : Pat<(subc i16 : $src, imm : $src2), (SUBIWRdK i16 : $src, imm : $src2)>; 2418 2419// These patterns convert add (x, -imm) to sub (x, imm) since we dont have 2420// any add with imm instructions. Also take care of the adiw/sbiw instructions. 2421def : Pat<(add i16 2422 : $src1, imm0_63_neg 2423 : $src2), 2424 (SBIWRdK i16 2425 : $src1, (imm0_63_neg 2426 : $src2))>; 2427def : Pat<(add i16 2428 : $src1, imm 2429 : $src2), 2430 (SUBIWRdK i16 2431 : $src1, (imm16_neg_XFORM imm 2432 : $src2))>; 2433def : Pat<(addc i16 2434 : $src1, imm 2435 : $src2), 2436 (SUBIWRdK i16 2437 : $src1, (imm16_neg_XFORM imm 2438 : $src2))>; 2439 2440def : Pat<(add i8 2441 : $src1, imm 2442 : $src2), 2443 (SUBIRdK i8 2444 : $src1, (imm8_neg_XFORM imm 2445 : $src2))>; 2446def : Pat<(addc i8 2447 : $src1, imm 2448 : $src2), 2449 (SUBIRdK i8 2450 : $src1, (imm8_neg_XFORM imm 2451 : $src2))>; 2452def : Pat<(adde i8 2453 : $src1, imm 2454 : $src2), 2455 (SBCIRdK i8 2456 : $src1, (imm8_neg_XFORM imm 2457 : $src2))>; 2458 2459// Calls. 2460def : Pat<(AVRcall(i16 tglobaladdr : $dst)), (CALLk tglobaladdr : $dst)>; 2461def : Pat<(AVRcall(i16 texternalsym : $dst)), (CALLk texternalsym : $dst)>; 2462 2463// `anyext` 2464def : Pat<(i16(anyext i8 2465 : $src)), 2466 (INSERT_SUBREG(i16(IMPLICIT_DEF)), i8 2467 : $src, sub_lo)>; 2468 2469// `trunc` 2470def : Pat<(i8(trunc i16 : $src)), (EXTRACT_SUBREG i16 : $src, sub_lo)>; 2471 2472// sext_inreg 2473def : Pat<(sext_inreg i16 2474 : $src, i8), 2475 (SEXT(i8(EXTRACT_SUBREG i16 2476 : $src, sub_lo)))>; 2477 2478// GlobalAddress 2479def : Pat<(i16(AVRWrapper tglobaladdr : $dst)), (LDIWRdK tglobaladdr : $dst)>; 2480def : Pat<(add i16 2481 : $src, (AVRWrapper tglobaladdr 2482 : $src2)), 2483 (SUBIWRdK i16 2484 : $src, tglobaladdr 2485 : $src2)>; 2486def : Pat<(i8(load(AVRWrapper tglobaladdr 2487 : $dst))), 2488 (LDSRdK tglobaladdr 2489 : $dst)>; 2490def : Pat<(i16(load(AVRWrapper tglobaladdr 2491 : $dst))), 2492 (LDSWRdK tglobaladdr 2493 : $dst)>; 2494def : Pat<(store i8 2495 : $src, (i16(AVRWrapper tglobaladdr 2496 : $dst))), 2497 (STSKRr tglobaladdr 2498 : $dst, i8 2499 : $src)>; 2500def : Pat<(store i16 2501 : $src, (i16(AVRWrapper tglobaladdr 2502 : $dst))), 2503 (STSWKRr tglobaladdr 2504 : $dst, i16 2505 : $src)>; 2506 2507// BlockAddress 2508def : Pat<(i16(AVRWrapper tblockaddress 2509 : $dst)), 2510 (LDIWRdK tblockaddress 2511 : $dst)>; 2512 2513def : Pat<(i8(trunc(AVRlsrwn DLDREGS 2514 : $src, (i16 8)))), 2515 (EXTRACT_SUBREG DREGS 2516 : $src, sub_hi)>; 2517 2518// :FIXME: DAGCombiner produces an shl node after legalization from these seq: 2519// BR_JT -> (mul x, 2) -> (shl x, 1) 2520def : Pat<(shl i16 : $src1, (i8 1)), (LSLWRd i16 : $src1)>; 2521 2522// Lowering of 'tst' node to 'TST' instruction. 2523// TST is an alias of AND Rd, Rd. 2524def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>; 2525 2526// Lowering of 'lsl' node to 'LSL' instruction. 2527// LSL is an alias of 'ADD Rd, Rd' 2528def : Pat<(AVRlsl i8 : $rd), (ADDRdRr GPR8 : $rd, GPR8 : $rd)>; 2529