10b57cec5SDimitry Andric //===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the AVR implementation of the TargetInstrInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_AVR_INSTR_INFO_H 140b57cec5SDimitry Andric #define LLVM_AVR_INSTR_INFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include "AVRRegisterInfo.h" 190b57cec5SDimitry Andric 200b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 210b57cec5SDimitry Andric #include "AVRGenInstrInfo.inc" 220b57cec5SDimitry Andric #undef GET_INSTRINFO_HEADER 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric namespace llvm { 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric namespace AVRCC { 270b57cec5SDimitry Andric 280b57cec5SDimitry Andric /// AVR specific condition codes. 290b57cec5SDimitry Andric /// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`. 300b57cec5SDimitry Andric /// They must be kept in synch. 310b57cec5SDimitry Andric enum CondCodes { 320b57cec5SDimitry Andric COND_EQ, //!< Equal 330b57cec5SDimitry Andric COND_NE, //!< Not equal 340b57cec5SDimitry Andric COND_GE, //!< Greater than or equal 350b57cec5SDimitry Andric COND_LT, //!< Less than 360b57cec5SDimitry Andric COND_SH, //!< Unsigned same or higher 370b57cec5SDimitry Andric COND_LO, //!< Unsigned lower 380b57cec5SDimitry Andric COND_MI, //!< Minus 390b57cec5SDimitry Andric COND_PL, //!< Plus 400b57cec5SDimitry Andric COND_INVALID 410b57cec5SDimitry Andric }; 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric } // end of namespace AVRCC 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric namespace AVRII { 460b57cec5SDimitry Andric 470b57cec5SDimitry Andric /// Specifies a target operand flag. 480b57cec5SDimitry Andric enum TOF { 490b57cec5SDimitry Andric MO_NO_FLAG, 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric /// On a symbol operand, this represents the lo part. 520b57cec5SDimitry Andric MO_LO = (1 << 1), 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric /// On a symbol operand, this represents the hi part. 550b57cec5SDimitry Andric MO_HI = (1 << 2), 560b57cec5SDimitry Andric 570b57cec5SDimitry Andric /// On a symbol operand, this represents it has to be negated. 580b57cec5SDimitry Andric MO_NEG = (1 << 3) 590b57cec5SDimitry Andric }; 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric } // end of namespace AVRII 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric /// Utilities related to the AVR instruction set. 640b57cec5SDimitry Andric class AVRInstrInfo : public AVRGenInstrInfo { 650b57cec5SDimitry Andric public: 660b57cec5SDimitry Andric explicit AVRInstrInfo(); 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric const AVRRegisterInfo &getRegisterInfo() const { return RI; } 690b57cec5SDimitry Andric const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const; 700b57cec5SDimitry Andric AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const; 710b57cec5SDimitry Andric AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const; 720b57cec5SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 75480093f4SDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 760b57cec5SDimitry Andric bool KillSrc) const override; 770b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 78*5ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register SrcReg, 790b57cec5SDimitry Andric bool isKill, int FrameIndex, 800b57cec5SDimitry Andric const TargetRegisterClass *RC, 810b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 820b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 83*5ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register DestReg, 840b57cec5SDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 850b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 860b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 870b57cec5SDimitry Andric int &FrameIndex) const override; 880b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 890b57cec5SDimitry Andric int &FrameIndex) const override; 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric // Branch analysis. 920b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 930b57cec5SDimitry Andric MachineBasicBlock *&FBB, 940b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 950b57cec5SDimitry Andric bool AllowModify = false) const override; 960b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 970b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 980b57cec5SDimitry Andric const DebugLoc &DL, 990b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 1000b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 1010b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 1020b57cec5SDimitry Andric bool 1030b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 1060b57cec5SDimitry Andric 1070b57cec5SDimitry Andric bool isBranchOffsetInRange(unsigned BranchOpc, 1080b57cec5SDimitry Andric int64_t BrOffset) const override; 1090b57cec5SDimitry Andric 1100b57cec5SDimitry Andric unsigned insertIndirectBranch(MachineBasicBlock &MBB, 1110b57cec5SDimitry Andric MachineBasicBlock &NewDestBB, 1120b57cec5SDimitry Andric const DebugLoc &DL, 1130b57cec5SDimitry Andric int64_t BrOffset, 1140b57cec5SDimitry Andric RegScavenger *RS) const override; 1150b57cec5SDimitry Andric private: 1160b57cec5SDimitry Andric const AVRRegisterInfo RI; 1170b57cec5SDimitry Andric }; 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric } // end namespace llvm 1200b57cec5SDimitry Andric 1210b57cec5SDimitry Andric #endif // LLVM_AVR_INSTR_INFO_H 122