xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AVRISelLowering.h (revision 4d3fc8b0570b29fb0d6ee9525f104d52176ff0d4)
1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_AVR_ISEL_LOWERING_H
15 #define LLVM_AVR_ISEL_LOWERING_H
16 
17 #include "llvm/CodeGen/CallingConvLower.h"
18 #include "llvm/CodeGen/TargetLowering.h"
19 
20 namespace llvm {
21 
22 namespace AVRISD {
23 
24 /// AVR Specific DAG Nodes
25 enum NodeType {
26   /// Start the numbering where the builtin ops leave off.
27   FIRST_NUMBER = ISD::BUILTIN_OP_END,
28   /// Return from subroutine.
29   RET_FLAG,
30   /// Return from ISR.
31   RETI_FLAG,
32   /// Represents an abstract call instruction,
33   /// which includes a bunch of information.
34   CALL,
35   /// A wrapper node for TargetConstantPool,
36   /// TargetExternalSymbol, and TargetGlobalAddress.
37   WRAPPER,
38   LSL,     ///< Logical shift left.
39   LSLBN,   ///< Byte logical shift left N bits.
40   LSLWN,   ///< Word logical shift left N bits.
41   LSLHI,   ///< Higher 8-bit of word logical shift left.
42   LSR,     ///< Logical shift right.
43   LSRBN,   ///< Byte logical shift right N bits.
44   LSRWN,   ///< Word logical shift right N bits.
45   LSRLO,   ///< Lower 8-bit of word logical shift right.
46   ASR,     ///< Arithmetic shift right.
47   ASRBN,   ///< Byte arithmetic shift right N bits.
48   ASRWN,   ///< Word arithmetic shift right N bits.
49   ASRLO,   ///< Lower 8-bit of word arithmetic shift right.
50   ROR,     ///< Bit rotate right.
51   ROL,     ///< Bit rotate left.
52   LSLLOOP, ///< A loop of single logical shift left instructions.
53   LSRLOOP, ///< A loop of single logical shift right instructions.
54   ROLLOOP, ///< A loop of single left bit rotate instructions.
55   RORLOOP, ///< A loop of single right bit rotate instructions.
56   ASRLOOP, ///< A loop of single arithmetic shift right instructions.
57   /// AVR conditional branches. Operand 0 is the chain operand, operand 1
58   /// is the block to branch if condition is true, operand 2 is the
59   /// condition code, and operand 3 is the flag operand produced by a CMP
60   /// or TEST instruction.
61   BRCOND,
62   /// Compare instruction.
63   CMP,
64   /// Compare with carry instruction.
65   CMPC,
66   /// Test for zero or minus instruction.
67   TST,
68   /// Swap Rd[7:4] <-> Rd[3:0].
69   SWAP,
70   /// Operand 0 and operand 1 are selection variable, operand 2
71   /// is condition code and operand 3 is flag operand.
72   SELECT_CC
73 };
74 
75 } // end of namespace AVRISD
76 
77 class AVRSubtarget;
78 class AVRTargetMachine;
79 
80 /// Performs target lowering for the AVR.
81 class AVRTargetLowering : public TargetLowering {
82 public:
83   explicit AVRTargetLowering(const AVRTargetMachine &TM,
84                              const AVRSubtarget &STI);
85 
86 public:
87   MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
88     return MVT::i8;
89   }
90 
91   MVT::SimpleValueType getCmpLibcallReturnType() const override {
92     return MVT::i8;
93   }
94 
95   const char *getTargetNodeName(unsigned Opcode) const override;
96 
97   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
98 
99   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
100                           SelectionDAG &DAG) const override;
101 
102   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
103                              unsigned AS,
104                              Instruction *I = nullptr) const override;
105 
106   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
107                                  ISD::MemIndexedMode &AM,
108                                  SelectionDAG &DAG) const override;
109 
110   bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
111                                   SDValue &Offset, ISD::MemIndexedMode &AM,
112                                   SelectionDAG &DAG) const override;
113 
114   bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
115 
116   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
117                          EVT VT) const override;
118 
119   MachineBasicBlock *
120   EmitInstrWithCustomInserter(MachineInstr &MI,
121                               MachineBasicBlock *MBB) const override;
122 
123   ConstraintType getConstraintType(StringRef Constraint) const override;
124 
125   ConstraintWeight
126   getSingleConstraintMatchWeight(AsmOperandInfo &info,
127                                  const char *constraint) const override;
128 
129   std::pair<unsigned, const TargetRegisterClass *>
130   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
131                                StringRef Constraint, MVT VT) const override;
132 
133   unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
134 
135   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
136                                     std::vector<SDValue> &Ops,
137                                     SelectionDAG &DAG) const override;
138 
139   Register getRegisterByName(const char *RegName, LLT VT,
140                              const MachineFunction &MF) const override;
141 
142   bool shouldSplitFunctionArgumentsAsLittleEndian(
143       const DataLayout &DL) const override {
144     return false;
145   }
146 
147 private:
148   SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
149                     SelectionDAG &DAG, SDLoc dl) const;
150   SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
151                     SDLoc dl) const;
152   SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
153   SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
154   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
155   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
156   SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
157   SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
158   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
159   SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
160   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
161 
162   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
163                       bool isVarArg,
164                       const SmallVectorImpl<ISD::OutputArg> &Outs,
165                       LLVMContext &Context) const override;
166 
167   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
168                       const SmallVectorImpl<ISD::OutputArg> &Outs,
169                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
170                       SelectionDAG &DAG) const override;
171   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
172                                bool isVarArg,
173                                const SmallVectorImpl<ISD::InputArg> &Ins,
174                                const SDLoc &dl, SelectionDAG &DAG,
175                                SmallVectorImpl<SDValue> &InVals) const override;
176   SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
177                     SmallVectorImpl<SDValue> &InVals) const override;
178   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
179                           CallingConv::ID CallConv, bool isVarArg,
180                           const SmallVectorImpl<ISD::InputArg> &Ins,
181                           const SDLoc &dl, SelectionDAG &DAG,
182                           SmallVectorImpl<SDValue> &InVals) const;
183 
184 protected:
185   const AVRSubtarget &Subtarget;
186 
187 private:
188   MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
189   MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
190   MachineBasicBlock *insertCopyR1(MachineInstr &MI,
191                                   MachineBasicBlock *BB) const;
192   MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
193                                               MachineBasicBlock *BB,
194                                               unsigned Opcode, int Width) const;
195 };
196 
197 } // end namespace llvm
198 
199 #endif // LLVM_AVR_ISEL_LOWERING_H
200