1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that AVR uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AVRISelLowering.h" 15 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/CodeGen/CallingConvLower.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/ErrorHandling.h" 26 27 #include "AVR.h" 28 #include "AVRMachineFunctionInfo.h" 29 #include "AVRSubtarget.h" 30 #include "AVRTargetMachine.h" 31 #include "MCTargetDesc/AVRMCTargetDesc.h" 32 33 namespace llvm { 34 35 AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM, 36 const AVRSubtarget &STI) 37 : TargetLowering(TM), Subtarget(STI) { 38 // Set up the register classes. 39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass); 40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); 41 42 // Compute derived properties from the register classes. 43 computeRegisterProperties(Subtarget.getRegisterInfo()); 44 45 setBooleanContents(ZeroOrOneBooleanContent); 46 setBooleanVectorContents(ZeroOrOneBooleanContent); 47 setSchedulingPreference(Sched::RegPressure); 48 setStackPointerRegisterToSaveRestore(AVR::SP); 49 setSupportsUnalignedAtomics(true); 50 51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); 52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); 53 54 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 55 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); 57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); 58 59 for (MVT VT : MVT::integer_valuetypes()) { 60 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { 61 setLoadExtAction(N, VT, MVT::i1, Promote); 62 setLoadExtAction(N, VT, MVT::i8, Expand); 63 } 64 } 65 66 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 67 68 for (MVT VT : MVT::integer_valuetypes()) { 69 setOperationAction(ISD::ADDC, VT, Legal); 70 setOperationAction(ISD::SUBC, VT, Legal); 71 setOperationAction(ISD::ADDE, VT, Legal); 72 setOperationAction(ISD::SUBE, VT, Legal); 73 } 74 75 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types 76 // revert into a sub since we don't have an add with immediate instruction. 77 setOperationAction(ISD::ADD, MVT::i32, Custom); 78 setOperationAction(ISD::ADD, MVT::i64, Custom); 79 80 // our shift instructions are only able to shift 1 bit at a time, so handle 81 // this in a custom way. 82 setOperationAction(ISD::SRA, MVT::i8, Custom); 83 setOperationAction(ISD::SHL, MVT::i8, Custom); 84 setOperationAction(ISD::SRL, MVT::i8, Custom); 85 setOperationAction(ISD::SRA, MVT::i16, Custom); 86 setOperationAction(ISD::SHL, MVT::i16, Custom); 87 setOperationAction(ISD::SRL, MVT::i16, Custom); 88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); 89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); 90 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); 91 92 setOperationAction(ISD::ROTL, MVT::i8, Custom); 93 setOperationAction(ISD::ROTL, MVT::i16, Expand); 94 setOperationAction(ISD::ROTR, MVT::i8, Custom); 95 setOperationAction(ISD::ROTR, MVT::i16, Expand); 96 97 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 98 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 99 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 100 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 101 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 102 103 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); 104 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); 105 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 107 setOperationAction(ISD::SETCC, MVT::i8, Custom); 108 setOperationAction(ISD::SETCC, MVT::i16, Custom); 109 setOperationAction(ISD::SETCC, MVT::i32, Custom); 110 setOperationAction(ISD::SETCC, MVT::i64, Custom); 111 setOperationAction(ISD::SELECT, MVT::i8, Expand); 112 setOperationAction(ISD::SELECT, MVT::i16, Expand); 113 114 setOperationAction(ISD::BSWAP, MVT::i16, Expand); 115 116 // Add support for postincrement and predecrement load/stores. 117 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 118 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 119 setIndexedLoadAction(ISD::PRE_DEC, MVT::i8, Legal); 120 setIndexedLoadAction(ISD::PRE_DEC, MVT::i16, Legal); 121 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 122 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 123 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); 124 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); 125 126 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 127 128 setOperationAction(ISD::VASTART, MVT::Other, Custom); 129 setOperationAction(ISD::VAEND, MVT::Other, Expand); 130 setOperationAction(ISD::VAARG, MVT::Other, Expand); 131 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 132 133 // Atomic operations which must be lowered to rtlib calls 134 for (MVT VT : MVT::integer_valuetypes()) { 135 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); 136 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); 142 } 143 144 // Division/remainder 145 setOperationAction(ISD::UDIV, MVT::i8, Expand); 146 setOperationAction(ISD::UDIV, MVT::i16, Expand); 147 setOperationAction(ISD::UREM, MVT::i8, Expand); 148 setOperationAction(ISD::UREM, MVT::i16, Expand); 149 setOperationAction(ISD::SDIV, MVT::i8, Expand); 150 setOperationAction(ISD::SDIV, MVT::i16, Expand); 151 setOperationAction(ISD::SREM, MVT::i8, Expand); 152 setOperationAction(ISD::SREM, MVT::i16, Expand); 153 154 // Make division and modulus custom 155 setOperationAction(ISD::UDIVREM, MVT::i8, Custom); 156 setOperationAction(ISD::UDIVREM, MVT::i16, Custom); 157 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 158 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); 159 setOperationAction(ISD::SDIVREM, MVT::i16, Custom); 160 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 161 162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co. 163 setOperationAction(ISD::MUL, MVT::i8, Expand); 164 setOperationAction(ISD::MUL, MVT::i16, Expand); 165 166 // Expand 16 bit multiplications. 167 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); 168 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); 169 170 // Expand multiplications to libcalls when there is 171 // no hardware MUL. 172 if (!Subtarget.supportsMultiplication()) { 173 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); 174 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); 175 } 176 177 for (MVT VT : MVT::integer_valuetypes()) { 178 setOperationAction(ISD::MULHS, VT, Expand); 179 setOperationAction(ISD::MULHU, VT, Expand); 180 } 181 182 for (MVT VT : MVT::integer_valuetypes()) { 183 setOperationAction(ISD::CTPOP, VT, Expand); 184 setOperationAction(ISD::CTLZ, VT, Expand); 185 setOperationAction(ISD::CTTZ, VT, Expand); 186 } 187 188 for (MVT VT : MVT::integer_valuetypes()) { 189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 190 // TODO: The generated code is pretty poor. Investigate using the 191 // same "shift and subtract with carry" trick that we do for 192 // extending 8-bit to 16-bit. This may require infrastructure 193 // improvements in how we treat 16-bit "registers" to be feasible. 194 } 195 196 // Division rtlib functions (not supported), use divmod functions instead 197 setLibcallName(RTLIB::SDIV_I8, nullptr); 198 setLibcallName(RTLIB::SDIV_I16, nullptr); 199 setLibcallName(RTLIB::SDIV_I32, nullptr); 200 setLibcallName(RTLIB::UDIV_I8, nullptr); 201 setLibcallName(RTLIB::UDIV_I16, nullptr); 202 setLibcallName(RTLIB::UDIV_I32, nullptr); 203 204 // Modulus rtlib functions (not supported), use divmod functions instead 205 setLibcallName(RTLIB::SREM_I8, nullptr); 206 setLibcallName(RTLIB::SREM_I16, nullptr); 207 setLibcallName(RTLIB::SREM_I32, nullptr); 208 setLibcallName(RTLIB::UREM_I8, nullptr); 209 setLibcallName(RTLIB::UREM_I16, nullptr); 210 setLibcallName(RTLIB::UREM_I32, nullptr); 211 212 // Division and modulus rtlib functions 213 setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4"); 214 setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4"); 215 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 216 setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4"); 217 setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4"); 218 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 219 220 // Several of the runtime library functions use a special calling conv 221 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::AVR_BUILTIN); 222 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::AVR_BUILTIN); 223 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::AVR_BUILTIN); 224 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::AVR_BUILTIN); 225 226 // Trigonometric rtlib functions 227 setLibcallName(RTLIB::SIN_F32, "sin"); 228 setLibcallName(RTLIB::COS_F32, "cos"); 229 230 setMinFunctionAlignment(Align(2)); 231 setMinimumJumpTableEntries(UINT_MAX); 232 } 233 234 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const { 235 #define NODE(name) \ 236 case AVRISD::name: \ 237 return #name 238 239 switch (Opcode) { 240 default: 241 return nullptr; 242 NODE(RET_FLAG); 243 NODE(RETI_FLAG); 244 NODE(CALL); 245 NODE(WRAPPER); 246 NODE(LSL); 247 NODE(LSR); 248 NODE(ROL); 249 NODE(ROR); 250 NODE(ASR); 251 NODE(LSLLOOP); 252 NODE(LSRLOOP); 253 NODE(ROLLOOP); 254 NODE(RORLOOP); 255 NODE(ASRLOOP); 256 NODE(BRCOND); 257 NODE(CMP); 258 NODE(CMPC); 259 NODE(TST); 260 NODE(SELECT_CC); 261 #undef NODE 262 } 263 } 264 265 EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, 266 EVT VT) const { 267 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); 268 return MVT::i8; 269 } 270 271 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const { 272 //: TODO: this function has to be completely rewritten to produce optimal 273 // code, for now it's producing very long but correct code. 274 unsigned Opc8; 275 const SDNode *N = Op.getNode(); 276 EVT VT = Op.getValueType(); 277 SDLoc dl(N); 278 assert(isPowerOf2_32(VT.getSizeInBits()) && 279 "Expected power-of-2 shift amount"); 280 281 // Expand non-constant shifts to loops. 282 if (!isa<ConstantSDNode>(N->getOperand(1))) { 283 switch (Op.getOpcode()) { 284 default: 285 llvm_unreachable("Invalid shift opcode!"); 286 case ISD::SHL: 287 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), 288 N->getOperand(1)); 289 case ISD::SRL: 290 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), 291 N->getOperand(1)); 292 case ISD::ROTL: { 293 SDValue Amt = N->getOperand(1); 294 EVT AmtVT = Amt.getValueType(); 295 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, 296 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); 297 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); 298 } 299 case ISD::ROTR: { 300 SDValue Amt = N->getOperand(1); 301 EVT AmtVT = Amt.getValueType(); 302 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, 303 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); 304 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); 305 } 306 case ISD::SRA: 307 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), 308 N->getOperand(1)); 309 } 310 } 311 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 313 SDValue Victim = N->getOperand(0); 314 315 switch (Op.getOpcode()) { 316 case ISD::SRA: 317 Opc8 = AVRISD::ASR; 318 break; 319 case ISD::ROTL: 320 Opc8 = AVRISD::ROL; 321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); 322 break; 323 case ISD::ROTR: 324 Opc8 = AVRISD::ROR; 325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); 326 break; 327 case ISD::SRL: 328 Opc8 = AVRISD::LSR; 329 break; 330 case ISD::SHL: 331 Opc8 = AVRISD::LSL; 332 break; 333 default: 334 llvm_unreachable("Invalid shift opcode"); 335 } 336 337 // Optimize int8/int16 shifts. 338 if (VT.getSizeInBits() == 8) { 339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { 340 // Optimize LSL when 4 <= ShiftAmount <= 6. 341 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); 342 Victim = 343 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); 344 ShiftAmount -= 4; 345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && 346 ShiftAmount < 7) { 347 // Optimize LSR when 4 <= ShiftAmount <= 6. 348 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); 349 Victim = 350 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); 351 ShiftAmount -= 4; 352 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) { 353 // Optimize LSL when ShiftAmount == 7. 354 Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, 355 DAG.getConstant(7, dl, VT)); 356 ShiftAmount = 0; 357 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) { 358 // Optimize LSR when ShiftAmount == 7. 359 Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, 360 DAG.getConstant(7, dl, VT)); 361 ShiftAmount = 0; 362 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { 363 // Optimize ASR when ShiftAmount == 6. 364 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, 365 DAG.getConstant(6, dl, VT)); 366 ShiftAmount = 0; 367 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { 368 // Optimize ASR when ShiftAmount == 7. 369 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, 370 DAG.getConstant(7, dl, VT)); 371 ShiftAmount = 0; 372 } 373 } else if (VT.getSizeInBits() == 16) { 374 if (4 <= ShiftAmount && ShiftAmount < 8) 375 switch (Op.getOpcode()) { 376 case ISD::SHL: 377 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, 378 DAG.getConstant(4, dl, VT)); 379 ShiftAmount -= 4; 380 break; 381 case ISD::SRL: 382 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, 383 DAG.getConstant(4, dl, VT)); 384 ShiftAmount -= 4; 385 break; 386 default: 387 break; 388 } 389 else if (8 <= ShiftAmount && ShiftAmount < 12) 390 switch (Op.getOpcode()) { 391 case ISD::SHL: 392 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, 393 DAG.getConstant(8, dl, VT)); 394 ShiftAmount -= 8; 395 // Only operate on the higher byte for remaining shift bits. 396 Opc8 = AVRISD::LSLHI; 397 break; 398 case ISD::SRL: 399 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, 400 DAG.getConstant(8, dl, VT)); 401 ShiftAmount -= 8; 402 // Only operate on the lower byte for remaining shift bits. 403 Opc8 = AVRISD::LSRLO; 404 break; 405 case ISD::SRA: 406 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, 407 DAG.getConstant(8, dl, VT)); 408 ShiftAmount -= 8; 409 // Only operate on the lower byte for remaining shift bits. 410 Opc8 = AVRISD::ASRLO; 411 break; 412 default: 413 break; 414 } 415 else if (12 <= ShiftAmount) 416 switch (Op.getOpcode()) { 417 case ISD::SHL: 418 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, 419 DAG.getConstant(12, dl, VT)); 420 ShiftAmount -= 12; 421 // Only operate on the higher byte for remaining shift bits. 422 Opc8 = AVRISD::LSLHI; 423 break; 424 case ISD::SRL: 425 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, 426 DAG.getConstant(12, dl, VT)); 427 ShiftAmount -= 12; 428 // Only operate on the lower byte for remaining shift bits. 429 Opc8 = AVRISD::LSRLO; 430 break; 431 case ISD::SRA: 432 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, 433 DAG.getConstant(8, dl, VT)); 434 ShiftAmount -= 8; 435 // Only operate on the lower byte for remaining shift bits. 436 Opc8 = AVRISD::ASRLO; 437 break; 438 default: 439 break; 440 } 441 } 442 443 while (ShiftAmount--) { 444 Victim = DAG.getNode(Opc8, dl, VT, Victim); 445 } 446 447 return Victim; 448 } 449 450 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const { 451 unsigned Opcode = Op->getOpcode(); 452 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && 453 "Invalid opcode for Div/Rem lowering"); 454 bool IsSigned = (Opcode == ISD::SDIVREM); 455 EVT VT = Op->getValueType(0); 456 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); 457 458 RTLIB::Libcall LC; 459 switch (VT.getSimpleVT().SimpleTy) { 460 default: 461 llvm_unreachable("Unexpected request for libcall!"); 462 case MVT::i8: 463 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; 464 break; 465 case MVT::i16: 466 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; 467 break; 468 case MVT::i32: 469 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; 470 break; 471 } 472 473 SDValue InChain = DAG.getEntryNode(); 474 475 TargetLowering::ArgListTy Args; 476 TargetLowering::ArgListEntry Entry; 477 for (SDValue const &Value : Op->op_values()) { 478 Entry.Node = Value; 479 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext()); 480 Entry.IsSExt = IsSigned; 481 Entry.IsZExt = !IsSigned; 482 Args.push_back(Entry); 483 } 484 485 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), 486 getPointerTy(DAG.getDataLayout())); 487 488 Type *RetTy = (Type *)StructType::get(Ty, Ty); 489 490 SDLoc dl(Op); 491 TargetLowering::CallLoweringInfo CLI(DAG); 492 CLI.setDebugLoc(dl) 493 .setChain(InChain) 494 .setLibCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) 495 .setInRegister() 496 .setSExtResult(IsSigned) 497 .setZExtResult(!IsSigned); 498 499 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 500 return CallInfo.first; 501 } 502 503 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op, 504 SelectionDAG &DAG) const { 505 auto DL = DAG.getDataLayout(); 506 507 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 508 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 509 510 // Create the TargetGlobalAddress node, folding in the constant offset. 511 SDValue Result = 512 DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset); 513 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 514 } 515 516 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op, 517 SelectionDAG &DAG) const { 518 auto DL = DAG.getDataLayout(); 519 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 520 521 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL)); 522 523 return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result); 524 } 525 526 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC. 527 static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) { 528 switch (CC) { 529 default: 530 llvm_unreachable("Unknown condition code!"); 531 case ISD::SETEQ: 532 return AVRCC::COND_EQ; 533 case ISD::SETNE: 534 return AVRCC::COND_NE; 535 case ISD::SETGE: 536 return AVRCC::COND_GE; 537 case ISD::SETLT: 538 return AVRCC::COND_LT; 539 case ISD::SETUGE: 540 return AVRCC::COND_SH; 541 case ISD::SETULT: 542 return AVRCC::COND_LO; 543 } 544 } 545 546 /// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands. 547 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, 548 SelectionDAG &DAG, SDLoc DL) const { 549 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) && 550 "LHS and RHS have different types"); 551 assert(((LHS.getSimpleValueType() == MVT::i16) || 552 (LHS.getSimpleValueType() == MVT::i8)) && 553 "invalid comparison type"); 554 555 SDValue Cmp; 556 557 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(RHS)) { 558 // Generate a CPI/CPC pair if RHS is a 16-bit constant. 559 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, 560 DAG.getIntPtrConstant(0, DL)); 561 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS, 562 DAG.getIntPtrConstant(1, DL)); 563 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, 564 DAG.getIntPtrConstant(0, DL)); 565 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, RHS, 566 DAG.getIntPtrConstant(1, DL)); 567 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo); 568 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); 569 } else { 570 // Generate ordinary 16-bit comparison. 571 Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS); 572 } 573 574 return Cmp; 575 } 576 577 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for 578 /// the given operands. 579 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 580 SDValue &AVRcc, SelectionDAG &DAG, 581 SDLoc DL) const { 582 SDValue Cmp; 583 EVT VT = LHS.getValueType(); 584 bool UseTest = false; 585 586 switch (CC) { 587 default: 588 break; 589 case ISD::SETLE: { 590 // Swap operands and reverse the branching condition. 591 std::swap(LHS, RHS); 592 CC = ISD::SETGE; 593 break; 594 } 595 case ISD::SETGT: { 596 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 597 switch (C->getSExtValue()) { 598 case -1: { 599 // When doing lhs > -1 use a tst instruction on the top part of lhs 600 // and use brpl instead of using a chain of cp/cpc. 601 UseTest = true; 602 AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8); 603 break; 604 } 605 case 0: { 606 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with 607 // __zero_reg__ in lhs. 608 RHS = LHS; 609 LHS = DAG.getConstant(0, DL, VT); 610 CC = ISD::SETLT; 611 break; 612 } 613 default: { 614 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows 615 // us to fold the constant into the cmp instruction. 616 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 617 CC = ISD::SETGE; 618 break; 619 } 620 } 621 break; 622 } 623 // Swap operands and reverse the branching condition. 624 std::swap(LHS, RHS); 625 CC = ISD::SETLT; 626 break; 627 } 628 case ISD::SETLT: { 629 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 630 switch (C->getSExtValue()) { 631 case 1: { 632 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with 633 // __zero_reg__ in lhs. 634 RHS = LHS; 635 LHS = DAG.getConstant(0, DL, VT); 636 CC = ISD::SETGE; 637 break; 638 } 639 case 0: { 640 // When doing lhs < 0 use a tst instruction on the top part of lhs 641 // and use brmi instead of using a chain of cp/cpc. 642 UseTest = true; 643 AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8); 644 break; 645 } 646 } 647 } 648 break; 649 } 650 case ISD::SETULE: { 651 // Swap operands and reverse the branching condition. 652 std::swap(LHS, RHS); 653 CC = ISD::SETUGE; 654 break; 655 } 656 case ISD::SETUGT: { 657 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to 658 // fold the constant into the cmp instruction. 659 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) { 660 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); 661 CC = ISD::SETUGE; 662 break; 663 } 664 // Swap operands and reverse the branching condition. 665 std::swap(LHS, RHS); 666 CC = ISD::SETULT; 667 break; 668 } 669 } 670 671 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of 672 // using the default and/or/xor expansion code which is much longer. 673 if (VT == MVT::i32) { 674 SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 675 DAG.getIntPtrConstant(0, DL)); 676 SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS, 677 DAG.getIntPtrConstant(1, DL)); 678 SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 679 DAG.getIntPtrConstant(0, DL)); 680 SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS, 681 DAG.getIntPtrConstant(1, DL)); 682 683 if (UseTest) { 684 // When using tst we only care about the highest part. 685 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi, 686 DAG.getIntPtrConstant(1, DL)); 687 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 688 } else { 689 Cmp = getAVRCmp(LHSlo, RHSlo, DAG, DL); 690 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp); 691 } 692 } else if (VT == MVT::i64) { 693 SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 694 DAG.getIntPtrConstant(0, DL)); 695 SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS, 696 DAG.getIntPtrConstant(1, DL)); 697 698 SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 699 DAG.getIntPtrConstant(0, DL)); 700 SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0, 701 DAG.getIntPtrConstant(1, DL)); 702 SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 703 DAG.getIntPtrConstant(0, DL)); 704 SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1, 705 DAG.getIntPtrConstant(1, DL)); 706 707 SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 708 DAG.getIntPtrConstant(0, DL)); 709 SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS, 710 DAG.getIntPtrConstant(1, DL)); 711 712 SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 713 DAG.getIntPtrConstant(0, DL)); 714 SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0, 715 DAG.getIntPtrConstant(1, DL)); 716 SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 717 DAG.getIntPtrConstant(0, DL)); 718 SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1, 719 DAG.getIntPtrConstant(1, DL)); 720 721 if (UseTest) { 722 // When using tst we only care about the highest part. 723 SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3, 724 DAG.getIntPtrConstant(1, DL)); 725 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top); 726 } else { 727 Cmp = getAVRCmp(LHS0, RHS0, DAG, DL); 728 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp); 729 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp); 730 Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp); 731 } 732 } else if (VT == MVT::i8 || VT == MVT::i16) { 733 if (UseTest) { 734 // When using tst we only care about the highest part. 735 Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, 736 (VT == MVT::i8) 737 ? LHS 738 : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, 739 LHS, DAG.getIntPtrConstant(1, DL))); 740 } else { 741 Cmp = getAVRCmp(LHS, RHS, DAG, DL); 742 } 743 } else { 744 llvm_unreachable("Invalid comparison size"); 745 } 746 747 // When using a test instruction AVRcc is already set. 748 if (!UseTest) { 749 AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8); 750 } 751 752 return Cmp; 753 } 754 755 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 756 SDValue Chain = Op.getOperand(0); 757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 758 SDValue LHS = Op.getOperand(2); 759 SDValue RHS = Op.getOperand(3); 760 SDValue Dest = Op.getOperand(4); 761 SDLoc dl(Op); 762 763 SDValue TargetCC; 764 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 765 766 return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC, 767 Cmp); 768 } 769 770 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 771 SDValue LHS = Op.getOperand(0); 772 SDValue RHS = Op.getOperand(1); 773 SDValue TrueV = Op.getOperand(2); 774 SDValue FalseV = Op.getOperand(3); 775 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 776 SDLoc dl(Op); 777 778 SDValue TargetCC; 779 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl); 780 781 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 782 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 783 784 return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops); 785 } 786 787 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 788 SDValue LHS = Op.getOperand(0); 789 SDValue RHS = Op.getOperand(1); 790 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 791 SDLoc DL(Op); 792 793 SDValue TargetCC; 794 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL); 795 796 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType()); 797 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType()); 798 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 799 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp}; 800 801 return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops); 802 } 803 804 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 805 const MachineFunction &MF = DAG.getMachineFunction(); 806 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 807 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 808 auto DL = DAG.getDataLayout(); 809 SDLoc dl(Op); 810 811 // Vastart just stores the address of the VarArgsFrameIndex slot into the 812 // memory location argument. 813 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL)); 814 815 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 816 MachinePointerInfo(SV)); 817 } 818 819 SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 820 switch (Op.getOpcode()) { 821 default: 822 llvm_unreachable("Don't know how to custom lower this!"); 823 case ISD::SHL: 824 case ISD::SRA: 825 case ISD::SRL: 826 case ISD::ROTL: 827 case ISD::ROTR: 828 return LowerShifts(Op, DAG); 829 case ISD::GlobalAddress: 830 return LowerGlobalAddress(Op, DAG); 831 case ISD::BlockAddress: 832 return LowerBlockAddress(Op, DAG); 833 case ISD::BR_CC: 834 return LowerBR_CC(Op, DAG); 835 case ISD::SELECT_CC: 836 return LowerSELECT_CC(Op, DAG); 837 case ISD::SETCC: 838 return LowerSETCC(Op, DAG); 839 case ISD::VASTART: 840 return LowerVASTART(Op, DAG); 841 case ISD::SDIVREM: 842 case ISD::UDIVREM: 843 return LowerDivRem(Op, DAG); 844 } 845 846 return SDValue(); 847 } 848 849 /// Replace a node with an illegal result type 850 /// with a new node built out of custom code. 851 void AVRTargetLowering::ReplaceNodeResults(SDNode *N, 852 SmallVectorImpl<SDValue> &Results, 853 SelectionDAG &DAG) const { 854 SDLoc DL(N); 855 856 switch (N->getOpcode()) { 857 case ISD::ADD: { 858 // Convert add (x, imm) into sub (x, -imm). 859 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) { 860 SDValue Sub = DAG.getNode( 861 ISD::SUB, DL, N->getValueType(0), N->getOperand(0), 862 DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0))); 863 Results.push_back(Sub); 864 } 865 break; 866 } 867 default: { 868 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 869 870 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 871 Results.push_back(Res.getValue(I)); 872 873 break; 874 } 875 } 876 } 877 878 /// Return true if the addressing mode represented 879 /// by AM is legal for this target, for a load/store of the specified type. 880 bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL, 881 const AddrMode &AM, Type *Ty, 882 unsigned AS, 883 Instruction *I) const { 884 int64_t Offs = AM.BaseOffs; 885 886 // Allow absolute addresses. 887 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { 888 return true; 889 } 890 891 // Flash memory instructions only allow zero offsets. 892 if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) { 893 return false; 894 } 895 896 // Allow reg+<6bit> offset. 897 if (Offs < 0) 898 Offs = -Offs; 899 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && 900 isUInt<6>(Offs)) { 901 return true; 902 } 903 904 return false; 905 } 906 907 /// Returns true by value, base pointer and 908 /// offset pointer and addressing mode by reference if the node's address 909 /// can be legally represented as pre-indexed load / store address. 910 bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 911 SDValue &Offset, 912 ISD::MemIndexedMode &AM, 913 SelectionDAG &DAG) const { 914 EVT VT; 915 const SDNode *Op; 916 SDLoc DL(N); 917 918 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 919 VT = LD->getMemoryVT(); 920 Op = LD->getBasePtr().getNode(); 921 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 922 return false; 923 if (AVR::isProgramMemoryAccess(LD)) { 924 return false; 925 } 926 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 927 VT = ST->getMemoryVT(); 928 Op = ST->getBasePtr().getNode(); 929 if (AVR::isProgramMemoryAccess(ST)) { 930 return false; 931 } 932 } else { 933 return false; 934 } 935 936 if (VT != MVT::i8 && VT != MVT::i16) { 937 return false; 938 } 939 940 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 941 return false; 942 } 943 944 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 945 int RHSC = RHS->getSExtValue(); 946 if (Op->getOpcode() == ISD::SUB) 947 RHSC = -RHSC; 948 949 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { 950 return false; 951 } 952 953 Base = Op->getOperand(0); 954 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 955 AM = ISD::PRE_DEC; 956 957 return true; 958 } 959 960 return false; 961 } 962 963 /// Returns true by value, base pointer and 964 /// offset pointer and addressing mode by reference if this node can be 965 /// combined with a load / store to form a post-indexed load / store. 966 bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 967 SDValue &Base, 968 SDValue &Offset, 969 ISD::MemIndexedMode &AM, 970 SelectionDAG &DAG) const { 971 EVT VT; 972 SDLoc DL(N); 973 974 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 975 VT = LD->getMemoryVT(); 976 if (LD->getExtensionType() != ISD::NON_EXTLOAD) 977 return false; 978 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 979 VT = ST->getMemoryVT(); 980 if (AVR::isProgramMemoryAccess(ST)) { 981 return false; 982 } 983 } else { 984 return false; 985 } 986 987 if (VT != MVT::i8 && VT != MVT::i16) { 988 return false; 989 } 990 991 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) { 992 return false; 993 } 994 995 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { 996 int RHSC = RHS->getSExtValue(); 997 if (Op->getOpcode() == ISD::SUB) 998 RHSC = -RHSC; 999 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { 1000 return false; 1001 } 1002 1003 Base = Op->getOperand(0); 1004 Offset = DAG.getConstant(RHSC, DL, MVT::i8); 1005 AM = ISD::POST_INC; 1006 1007 return true; 1008 } 1009 1010 return false; 1011 } 1012 1013 bool AVRTargetLowering::isOffsetFoldingLegal( 1014 const GlobalAddressSDNode *GA) const { 1015 return true; 1016 } 1017 1018 //===----------------------------------------------------------------------===// 1019 // Formal Arguments Calling Convention Implementation 1020 //===----------------------------------------------------------------------===// 1021 1022 #include "AVRGenCallingConv.inc" 1023 1024 /// Registers for calling conventions, ordered in reverse as required by ABI. 1025 /// Both arrays must be of the same length. 1026 static const MCPhysReg RegList8[] = { 1027 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, 1028 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, 1029 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8}; 1030 static const MCPhysReg RegList16[] = { 1031 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21, 1032 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16, 1033 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11, 1034 AVR::R11R10, AVR::R10R9, AVR::R9R8}; 1035 1036 static_assert(array_lengthof(RegList8) == array_lengthof(RegList16), 1037 "8-bit and 16-bit register arrays must be of equal length"); 1038 1039 /// Analyze incoming and outgoing function arguments. We need custom C++ code 1040 /// to handle special constraints in the ABI. 1041 /// In addition, all pieces of a certain argument have to be passed either 1042 /// using registers or the stack but never mixing both. 1043 template <typename ArgT> 1044 static void 1045 analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, 1046 const DataLayout *TD, const SmallVectorImpl<ArgT> &Args, 1047 SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) { 1048 unsigned NumArgs = Args.size(); 1049 // This is the index of the last used register, in RegList*. 1050 // -1 means R26 (R26 is never actually used in CC). 1051 int RegLastIdx = -1; 1052 // Once a value is passed to the stack it will always be used 1053 bool UseStack = false; 1054 for (unsigned i = 0; i != NumArgs;) { 1055 MVT VT = Args[i].VT; 1056 // We have to count the number of bytes for each function argument, that is 1057 // those Args with the same OrigArgIndex. This is important in case the 1058 // function takes an aggregate type. 1059 // Current argument will be between [i..j). 1060 unsigned ArgIndex = Args[i].OrigArgIndex; 1061 unsigned TotalBytes = VT.getStoreSize(); 1062 unsigned j = i + 1; 1063 for (; j != NumArgs; ++j) { 1064 if (Args[j].OrigArgIndex != ArgIndex) 1065 break; 1066 TotalBytes += Args[j].VT.getStoreSize(); 1067 } 1068 // Round up to even number of bytes. 1069 TotalBytes = alignTo(TotalBytes, 2); 1070 // Skip zero sized arguments 1071 if (TotalBytes == 0) 1072 continue; 1073 // The index of the first register to be used 1074 unsigned RegIdx = RegLastIdx + TotalBytes; 1075 RegLastIdx = RegIdx; 1076 // If there are not enough registers, use the stack 1077 if (RegIdx >= array_lengthof(RegList8)) { 1078 UseStack = true; 1079 } 1080 for (; i != j; ++i) { 1081 MVT VT = Args[i].VT; 1082 1083 if (UseStack) { 1084 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); 1085 unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt), 1086 TD->getABITypeAlign(evt)); 1087 CCInfo.addLoc( 1088 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); 1089 } else { 1090 unsigned Reg; 1091 if (VT == MVT::i8) { 1092 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1093 } else if (VT == MVT::i16) { 1094 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1095 } else { 1096 llvm_unreachable( 1097 "calling convention can only manage i8 and i16 types"); 1098 } 1099 assert(Reg && "register not available in calling convention"); 1100 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); 1101 // Registers inside a particular argument are sorted in increasing order 1102 // (remember the array is reversed). 1103 RegIdx -= VT.getStoreSize(); 1104 } 1105 } 1106 } 1107 } 1108 1109 /// Count the total number of bytes needed to pass or return these arguments. 1110 template <typename ArgT> 1111 static unsigned 1112 getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) { 1113 unsigned TotalBytes = 0; 1114 1115 for (const ArgT &Arg : Args) { 1116 TotalBytes += Arg.VT.getStoreSize(); 1117 } 1118 return TotalBytes; 1119 } 1120 1121 /// Analyze incoming and outgoing value of returning from a function. 1122 /// The algorithm is similar to analyzeArguments, but there can only be 1123 /// one value, possibly an aggregate, and it is limited to 8 bytes. 1124 template <typename ArgT> 1125 static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args, 1126 CCState &CCInfo) { 1127 unsigned NumArgs = Args.size(); 1128 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args); 1129 // CanLowerReturn() guarantees this assertion. 1130 assert(TotalBytes <= 8 && 1131 "return values greater than 8 bytes cannot be lowered"); 1132 1133 // GCC-ABI says that the size is rounded up to the next even number, 1134 // but actually once it is more than 4 it will always round up to 8. 1135 if (TotalBytes > 4) { 1136 TotalBytes = 8; 1137 } else { 1138 TotalBytes = alignTo(TotalBytes, 2); 1139 } 1140 1141 // The index of the first register to use. 1142 int RegIdx = TotalBytes - 1; 1143 for (unsigned i = 0; i != NumArgs; ++i) { 1144 MVT VT = Args[i].VT; 1145 unsigned Reg; 1146 if (VT == MVT::i8) { 1147 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); 1148 } else if (VT == MVT::i16) { 1149 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); 1150 } else { 1151 llvm_unreachable("calling convention can only manage i8 and i16 types"); 1152 } 1153 assert(Reg && "register not available in calling convention"); 1154 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); 1155 // Registers sort in increasing order 1156 RegIdx -= VT.getStoreSize(); 1157 } 1158 } 1159 1160 SDValue AVRTargetLowering::LowerFormalArguments( 1161 SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 1162 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1163 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 1164 MachineFunction &MF = DAG.getMachineFunction(); 1165 MachineFrameInfo &MFI = MF.getFrameInfo(); 1166 auto DL = DAG.getDataLayout(); 1167 1168 // Assign locations to all of the incoming arguments. 1169 SmallVector<CCValAssign, 16> ArgLocs; 1170 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1171 *DAG.getContext()); 1172 1173 // Variadic functions do not need all the analysis below. 1174 if (isVarArg) { 1175 CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg); 1176 } else { 1177 analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo); 1178 } 1179 1180 SDValue ArgValue; 1181 for (CCValAssign &VA : ArgLocs) { 1182 1183 // Arguments stored on registers. 1184 if (VA.isRegLoc()) { 1185 EVT RegVT = VA.getLocVT(); 1186 const TargetRegisterClass *RC; 1187 if (RegVT == MVT::i8) { 1188 RC = &AVR::GPR8RegClass; 1189 } else if (RegVT == MVT::i16) { 1190 RC = &AVR::DREGSRegClass; 1191 } else { 1192 llvm_unreachable("Unknown argument type!"); 1193 } 1194 1195 Register Reg = MF.addLiveIn(VA.getLocReg(), RC); 1196 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1197 1198 // :NOTE: Clang should not promote any i8 into i16 but for safety the 1199 // following code will handle zexts or sexts generated by other 1200 // front ends. Otherwise: 1201 // If this is an 8 bit value, it is really passed promoted 1202 // to 16 bits. Insert an assert[sz]ext to capture this, then 1203 // truncate to the right size. 1204 switch (VA.getLocInfo()) { 1205 default: 1206 llvm_unreachable("Unknown loc info!"); 1207 case CCValAssign::Full: 1208 break; 1209 case CCValAssign::BCvt: 1210 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1211 break; 1212 case CCValAssign::SExt: 1213 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1214 DAG.getValueType(VA.getValVT())); 1215 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1216 break; 1217 case CCValAssign::ZExt: 1218 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1219 DAG.getValueType(VA.getValVT())); 1220 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1221 break; 1222 } 1223 1224 InVals.push_back(ArgValue); 1225 } else { 1226 // Only arguments passed on the stack should make it here. 1227 assert(VA.isMemLoc()); 1228 1229 EVT LocVT = VA.getLocVT(); 1230 1231 // Create the frame index object for this incoming parameter. 1232 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, 1233 VA.getLocMemOffset(), true); 1234 1235 // Create the SelectionDAG nodes corresponding to a load 1236 // from this parameter. 1237 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL)); 1238 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN, 1239 MachinePointerInfo::getFixedStack(MF, FI))); 1240 } 1241 } 1242 1243 // If the function takes variable number of arguments, make a frame index for 1244 // the start of the first vararg value... for expansion of llvm.va_start. 1245 if (isVarArg) { 1246 unsigned StackSize = CCInfo.getNextStackOffset(); 1247 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 1248 1249 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true)); 1250 } 1251 1252 return Chain; 1253 } 1254 1255 //===----------------------------------------------------------------------===// 1256 // Call Calling Convention Implementation 1257 //===----------------------------------------------------------------------===// 1258 1259 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1260 SmallVectorImpl<SDValue> &InVals) const { 1261 SelectionDAG &DAG = CLI.DAG; 1262 SDLoc &DL = CLI.DL; 1263 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1264 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1265 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1266 SDValue Chain = CLI.Chain; 1267 SDValue Callee = CLI.Callee; 1268 bool &isTailCall = CLI.IsTailCall; 1269 CallingConv::ID CallConv = CLI.CallConv; 1270 bool isVarArg = CLI.IsVarArg; 1271 1272 MachineFunction &MF = DAG.getMachineFunction(); 1273 1274 // AVR does not yet support tail call optimization. 1275 isTailCall = false; 1276 1277 // Analyze operands of the call, assigning locations to each operand. 1278 SmallVector<CCValAssign, 16> ArgLocs; 1279 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1280 *DAG.getContext()); 1281 1282 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1283 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1284 // node so that legalize doesn't hack it. 1285 const Function *F = nullptr; 1286 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1287 const GlobalValue *GV = G->getGlobal(); 1288 1289 F = cast<Function>(GV); 1290 Callee = 1291 DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout())); 1292 } else if (const ExternalSymbolSDNode *ES = 1293 dyn_cast<ExternalSymbolSDNode>(Callee)) { 1294 Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), 1295 getPointerTy(DAG.getDataLayout())); 1296 } 1297 1298 // Variadic functions do not need all the analysis below. 1299 if (isVarArg) { 1300 CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg); 1301 } else { 1302 analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo); 1303 } 1304 1305 // Get a count of how many bytes are to be pushed on the stack. 1306 unsigned NumBytes = CCInfo.getNextStackOffset(); 1307 1308 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL); 1309 1310 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1311 1312 // First, walk the register assignments, inserting copies. 1313 unsigned AI, AE; 1314 bool HasStackArgs = false; 1315 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) { 1316 CCValAssign &VA = ArgLocs[AI]; 1317 EVT RegVT = VA.getLocVT(); 1318 SDValue Arg = OutVals[AI]; 1319 1320 // Promote the value if needed. With Clang this should not happen. 1321 switch (VA.getLocInfo()) { 1322 default: 1323 llvm_unreachable("Unknown loc info!"); 1324 case CCValAssign::Full: 1325 break; 1326 case CCValAssign::SExt: 1327 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); 1328 break; 1329 case CCValAssign::ZExt: 1330 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); 1331 break; 1332 case CCValAssign::AExt: 1333 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); 1334 break; 1335 case CCValAssign::BCvt: 1336 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); 1337 break; 1338 } 1339 1340 // Stop when we encounter a stack argument, we need to process them 1341 // in reverse order in the loop below. 1342 if (VA.isMemLoc()) { 1343 HasStackArgs = true; 1344 break; 1345 } 1346 1347 // Arguments that can be passed on registers must be kept in the RegsToPass 1348 // vector. 1349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1350 } 1351 1352 // Second, stack arguments have to walked. 1353 // Previously this code created chained stores but those chained stores appear 1354 // to be unchained in the legalization phase. Therefore, do not attempt to 1355 // chain them here. In fact, chaining them here somehow causes the first and 1356 // second store to be reversed which is the exact opposite of the intended 1357 // effect. 1358 if (HasStackArgs) { 1359 SmallVector<SDValue, 8> MemOpChains; 1360 for (; AI != AE; AI++) { 1361 CCValAssign &VA = ArgLocs[AI]; 1362 SDValue Arg = OutVals[AI]; 1363 1364 assert(VA.isMemLoc()); 1365 1366 // SP points to one stack slot further so add one to adjust it. 1367 SDValue PtrOff = DAG.getNode( 1368 ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), 1369 DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())), 1370 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL)); 1371 1372 MemOpChains.push_back( 1373 DAG.getStore(Chain, DL, Arg, PtrOff, 1374 MachinePointerInfo::getStack(MF, VA.getLocMemOffset()))); 1375 } 1376 1377 if (!MemOpChains.empty()) 1378 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); 1379 } 1380 1381 // Build a sequence of copy-to-reg nodes chained together with token chain and 1382 // flag operands which copy the outgoing args into registers. The InFlag in 1383 // necessary since all emited instructions must be stuck together. 1384 SDValue InFlag; 1385 for (auto Reg : RegsToPass) { 1386 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag); 1387 InFlag = Chain.getValue(1); 1388 } 1389 1390 // Returns a chain & a flag for retval copy to use. 1391 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1392 SmallVector<SDValue, 8> Ops; 1393 Ops.push_back(Chain); 1394 Ops.push_back(Callee); 1395 1396 // Add argument registers to the end of the list so that they are known live 1397 // into the call. 1398 for (auto Reg : RegsToPass) { 1399 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType())); 1400 } 1401 1402 // Add a register mask operand representing the call-preserved registers. 1403 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 1404 const uint32_t *Mask = 1405 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv); 1406 assert(Mask && "Missing call preserved mask for calling convention"); 1407 Ops.push_back(DAG.getRegisterMask(Mask)); 1408 1409 if (InFlag.getNode()) { 1410 Ops.push_back(InFlag); 1411 } 1412 1413 Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops); 1414 InFlag = Chain.getValue(1); 1415 1416 // Create the CALLSEQ_END node. 1417 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true), 1418 DAG.getIntPtrConstant(0, DL, true), InFlag, DL); 1419 1420 if (!Ins.empty()) { 1421 InFlag = Chain.getValue(1); 1422 } 1423 1424 // Handle result values, copying them out of physregs into vregs that we 1425 // return. 1426 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG, 1427 InVals); 1428 } 1429 1430 /// Lower the result values of a call into the 1431 /// appropriate copies out of appropriate physical registers. 1432 /// 1433 SDValue AVRTargetLowering::LowerCallResult( 1434 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, 1435 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, 1436 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { 1437 1438 // Assign locations to each value returned by this call. 1439 SmallVector<CCValAssign, 16> RVLocs; 1440 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1441 *DAG.getContext()); 1442 1443 // Handle runtime calling convs. 1444 if (CallConv == CallingConv::AVR_BUILTIN) { 1445 CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN); 1446 } else { 1447 analyzeReturnValues(Ins, CCInfo); 1448 } 1449 1450 // Copy all of the result registers out of their specified physreg. 1451 for (CCValAssign const &RVLoc : RVLocs) { 1452 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(), 1453 InFlag) 1454 .getValue(1); 1455 InFlag = Chain.getValue(2); 1456 InVals.push_back(Chain.getValue(0)); 1457 } 1458 1459 return Chain; 1460 } 1461 1462 //===----------------------------------------------------------------------===// 1463 // Return Value Calling Convention Implementation 1464 //===----------------------------------------------------------------------===// 1465 1466 bool AVRTargetLowering::CanLowerReturn( 1467 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, 1468 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { 1469 if (CallConv == CallingConv::AVR_BUILTIN) { 1470 SmallVector<CCValAssign, 16> RVLocs; 1471 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1472 return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN); 1473 } 1474 1475 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs); 1476 return TotalBytes <= 8; 1477 } 1478 1479 SDValue 1480 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, 1481 bool isVarArg, 1482 const SmallVectorImpl<ISD::OutputArg> &Outs, 1483 const SmallVectorImpl<SDValue> &OutVals, 1484 const SDLoc &dl, SelectionDAG &DAG) const { 1485 // CCValAssign - represent the assignment of the return value to locations. 1486 SmallVector<CCValAssign, 16> RVLocs; 1487 1488 // CCState - Info about the registers and stack slot. 1489 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1490 *DAG.getContext()); 1491 1492 MachineFunction &MF = DAG.getMachineFunction(); 1493 1494 // Analyze return values. 1495 if (CallConv == CallingConv::AVR_BUILTIN) { 1496 CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN); 1497 } else { 1498 analyzeReturnValues(Outs, CCInfo); 1499 } 1500 1501 SDValue Flag; 1502 SmallVector<SDValue, 4> RetOps(1, Chain); 1503 // Copy the result values into the output registers. 1504 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1505 CCValAssign &VA = RVLocs[i]; 1506 assert(VA.isRegLoc() && "Can only return in registers!"); 1507 1508 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 1509 1510 // Guarantee that all emitted copies are stuck together with flags. 1511 Flag = Chain.getValue(1); 1512 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1513 } 1514 1515 // Don't emit the ret/reti instruction when the naked attribute is present in 1516 // the function being compiled. 1517 if (MF.getFunction().getAttributes().hasFnAttr(Attribute::Naked)) { 1518 return Chain; 1519 } 1520 1521 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>(); 1522 1523 unsigned RetOpc = 1524 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_FLAG : AVRISD::RET_FLAG; 1525 1526 RetOps[0] = Chain; // Update chain. 1527 1528 if (Flag.getNode()) { 1529 RetOps.push_back(Flag); 1530 } 1531 1532 return DAG.getNode(RetOpc, dl, MVT::Other, RetOps); 1533 } 1534 1535 //===----------------------------------------------------------------------===// 1536 // Custom Inserters 1537 //===----------------------------------------------------------------------===// 1538 1539 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI, 1540 MachineBasicBlock *BB) const { 1541 unsigned Opc; 1542 const TargetRegisterClass *RC; 1543 bool HasRepeatedOperand = false; 1544 MachineFunction *F = BB->getParent(); 1545 MachineRegisterInfo &RI = F->getRegInfo(); 1546 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1547 DebugLoc dl = MI.getDebugLoc(); 1548 1549 switch (MI.getOpcode()) { 1550 default: 1551 llvm_unreachable("Invalid shift opcode!"); 1552 case AVR::Lsl8: 1553 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd 1554 RC = &AVR::GPR8RegClass; 1555 HasRepeatedOperand = true; 1556 break; 1557 case AVR::Lsl16: 1558 Opc = AVR::LSLWRd; 1559 RC = &AVR::DREGSRegClass; 1560 break; 1561 case AVR::Asr8: 1562 Opc = AVR::ASRRd; 1563 RC = &AVR::GPR8RegClass; 1564 break; 1565 case AVR::Asr16: 1566 Opc = AVR::ASRWRd; 1567 RC = &AVR::DREGSRegClass; 1568 break; 1569 case AVR::Lsr8: 1570 Opc = AVR::LSRRd; 1571 RC = &AVR::GPR8RegClass; 1572 break; 1573 case AVR::Lsr16: 1574 Opc = AVR::LSRWRd; 1575 RC = &AVR::DREGSRegClass; 1576 break; 1577 case AVR::Rol8: 1578 Opc = AVR::ROLBRd; 1579 RC = &AVR::GPR8RegClass; 1580 break; 1581 case AVR::Rol16: 1582 Opc = AVR::ROLWRd; 1583 RC = &AVR::DREGSRegClass; 1584 break; 1585 case AVR::Ror8: 1586 Opc = AVR::RORBRd; 1587 RC = &AVR::GPR8RegClass; 1588 break; 1589 case AVR::Ror16: 1590 Opc = AVR::RORWRd; 1591 RC = &AVR::DREGSRegClass; 1592 break; 1593 } 1594 1595 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1596 1597 MachineFunction::iterator I; 1598 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I) 1599 ; 1600 if (I != F->end()) 1601 ++I; 1602 1603 // Create loop block. 1604 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); 1605 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(LLVM_BB); 1606 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); 1607 1608 F->insert(I, LoopBB); 1609 F->insert(I, CheckBB); 1610 F->insert(I, RemBB); 1611 1612 // Update machine-CFG edges by transferring all successors of the current 1613 // block to the block containing instructions after shift. 1614 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 1615 BB->end()); 1616 RemBB->transferSuccessorsAndUpdatePHIs(BB); 1617 1618 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB. 1619 BB->addSuccessor(CheckBB); 1620 LoopBB->addSuccessor(CheckBB); 1621 CheckBB->addSuccessor(LoopBB); 1622 CheckBB->addSuccessor(RemBB); 1623 1624 Register ShiftAmtReg = RI.createVirtualRegister(&AVR::GPR8RegClass); 1625 Register ShiftAmtReg2 = RI.createVirtualRegister(&AVR::GPR8RegClass); 1626 Register ShiftReg = RI.createVirtualRegister(RC); 1627 Register ShiftReg2 = RI.createVirtualRegister(RC); 1628 Register ShiftAmtSrcReg = MI.getOperand(2).getReg(); 1629 Register SrcReg = MI.getOperand(1).getReg(); 1630 Register DstReg = MI.getOperand(0).getReg(); 1631 1632 // BB: 1633 // rjmp CheckBB 1634 BuildMI(BB, dl, TII.get(AVR::RJMPk)).addMBB(CheckBB); 1635 1636 // LoopBB: 1637 // ShiftReg2 = shift ShiftReg 1638 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); 1639 if (HasRepeatedOperand) 1640 ShiftMI.addReg(ShiftReg); 1641 1642 // CheckBB: 1643 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] 1644 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] 1645 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] 1646 // ShiftAmt2 = ShiftAmt - 1; 1647 // if (ShiftAmt2 >= 0) goto LoopBB; 1648 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) 1649 .addReg(SrcReg) 1650 .addMBB(BB) 1651 .addReg(ShiftReg2) 1652 .addMBB(LoopBB); 1653 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftAmtReg) 1654 .addReg(ShiftAmtSrcReg) 1655 .addMBB(BB) 1656 .addReg(ShiftAmtReg2) 1657 .addMBB(LoopBB); 1658 BuildMI(CheckBB, dl, TII.get(AVR::PHI), DstReg) 1659 .addReg(SrcReg) 1660 .addMBB(BB) 1661 .addReg(ShiftReg2) 1662 .addMBB(LoopBB); 1663 1664 BuildMI(CheckBB, dl, TII.get(AVR::DECRd), ShiftAmtReg2).addReg(ShiftAmtReg); 1665 BuildMI(CheckBB, dl, TII.get(AVR::BRPLk)).addMBB(LoopBB); 1666 1667 MI.eraseFromParent(); // The pseudo instruction is gone now. 1668 return RemBB; 1669 } 1670 1671 static bool isCopyMulResult(MachineBasicBlock::iterator const &I) { 1672 if (I->getOpcode() == AVR::COPY) { 1673 Register SrcReg = I->getOperand(1).getReg(); 1674 return (SrcReg == AVR::R0 || SrcReg == AVR::R1); 1675 } 1676 1677 return false; 1678 } 1679 1680 // The mul instructions wreak havock on our zero_reg R1. We need to clear it 1681 // after the result has been evacuated. This is probably not the best way to do 1682 // it, but it works for now. 1683 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI, 1684 MachineBasicBlock *BB) const { 1685 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1686 MachineBasicBlock::iterator I(MI); 1687 ++I; // in any case insert *after* the mul instruction 1688 if (isCopyMulResult(I)) 1689 ++I; 1690 if (isCopyMulResult(I)) 1691 ++I; 1692 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1) 1693 .addReg(AVR::R1) 1694 .addReg(AVR::R1); 1695 return BB; 1696 } 1697 1698 // Insert a read from R1, which almost always contains the value 0. 1699 MachineBasicBlock * 1700 AVRTargetLowering::insertCopyR1(MachineInstr &MI, MachineBasicBlock *BB) const { 1701 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1702 MachineBasicBlock::iterator I(MI); 1703 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::COPY)) 1704 .add(MI.getOperand(0)) 1705 .addReg(AVR::R1); 1706 MI.eraseFromParent(); 1707 return BB; 1708 } 1709 1710 MachineBasicBlock * 1711 AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, 1712 MachineBasicBlock *MBB) const { 1713 int Opc = MI.getOpcode(); 1714 1715 // Pseudo shift instructions with a non constant shift amount are expanded 1716 // into a loop. 1717 switch (Opc) { 1718 case AVR::Lsl8: 1719 case AVR::Lsl16: 1720 case AVR::Lsr8: 1721 case AVR::Lsr16: 1722 case AVR::Rol8: 1723 case AVR::Rol16: 1724 case AVR::Ror8: 1725 case AVR::Ror16: 1726 case AVR::Asr8: 1727 case AVR::Asr16: 1728 return insertShift(MI, MBB); 1729 case AVR::MULRdRr: 1730 case AVR::MULSRdRr: 1731 return insertMul(MI, MBB); 1732 case AVR::CopyR1: 1733 return insertCopyR1(MI, MBB); 1734 } 1735 1736 assert((Opc == AVR::Select16 || Opc == AVR::Select8) && 1737 "Unexpected instr type to insert"); 1738 1739 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent() 1740 ->getParent() 1741 ->getSubtarget() 1742 .getInstrInfo(); 1743 DebugLoc dl = MI.getDebugLoc(); 1744 1745 // To "insert" a SELECT instruction, we insert the diamond 1746 // control-flow pattern. The incoming instruction knows the 1747 // destination vreg to set, the condition code register to branch 1748 // on, the true/false values to select between, and a branch opcode 1749 // to use. 1750 1751 MachineFunction *MF = MBB->getParent(); 1752 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 1753 MachineBasicBlock *FallThrough = MBB->getFallThrough(); 1754 1755 // If the current basic block falls through to another basic block, 1756 // we must insert an unconditional branch to the fallthrough destination 1757 // if we are to insert basic blocks at the prior fallthrough point. 1758 if (FallThrough != nullptr) { 1759 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough); 1760 } 1761 1762 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1763 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1764 1765 MachineFunction::iterator I; 1766 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I) 1767 ; 1768 if (I != MF->end()) 1769 ++I; 1770 MF->insert(I, trueMBB); 1771 MF->insert(I, falseMBB); 1772 1773 // Transfer remaining instructions and all successors of the current 1774 // block to the block which will contain the Phi node for the 1775 // select. 1776 trueMBB->splice(trueMBB->begin(), MBB, 1777 std::next(MachineBasicBlock::iterator(MI)), MBB->end()); 1778 trueMBB->transferSuccessorsAndUpdatePHIs(MBB); 1779 1780 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm(); 1781 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB); 1782 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB); 1783 MBB->addSuccessor(falseMBB); 1784 MBB->addSuccessor(trueMBB); 1785 1786 // Unconditionally flow back to the true block 1787 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB); 1788 falseMBB->addSuccessor(trueMBB); 1789 1790 // Set up the Phi node to determine where we came from 1791 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), 1792 MI.getOperand(0).getReg()) 1793 .addReg(MI.getOperand(1).getReg()) 1794 .addMBB(MBB) 1795 .addReg(MI.getOperand(2).getReg()) 1796 .addMBB(falseMBB); 1797 1798 MI.eraseFromParent(); // The pseudo instruction is gone now. 1799 return trueMBB; 1800 } 1801 1802 //===----------------------------------------------------------------------===// 1803 // Inline Asm Support 1804 //===----------------------------------------------------------------------===// 1805 1806 AVRTargetLowering::ConstraintType 1807 AVRTargetLowering::getConstraintType(StringRef Constraint) const { 1808 if (Constraint.size() == 1) { 1809 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html 1810 switch (Constraint[0]) { 1811 default: 1812 break; 1813 case 'a': // Simple upper registers 1814 case 'b': // Base pointer registers pairs 1815 case 'd': // Upper register 1816 case 'l': // Lower registers 1817 case 'e': // Pointer register pairs 1818 case 'q': // Stack pointer register 1819 case 'r': // Any register 1820 case 'w': // Special upper register pairs 1821 return C_RegisterClass; 1822 case 't': // Temporary register 1823 case 'x': 1824 case 'X': // Pointer register pair X 1825 case 'y': 1826 case 'Y': // Pointer register pair Y 1827 case 'z': 1828 case 'Z': // Pointer register pair Z 1829 return C_Register; 1830 case 'Q': // A memory address based on Y or Z pointer with displacement. 1831 return C_Memory; 1832 case 'G': // Floating point constant 1833 case 'I': // 6-bit positive integer constant 1834 case 'J': // 6-bit negative integer constant 1835 case 'K': // Integer constant (Range: 2) 1836 case 'L': // Integer constant (Range: 0) 1837 case 'M': // 8-bit integer constant 1838 case 'N': // Integer constant (Range: -1) 1839 case 'O': // Integer constant (Range: 8, 16, 24) 1840 case 'P': // Integer constant (Range: 1) 1841 case 'R': // Integer constant (Range: -6 to 5)x 1842 return C_Immediate; 1843 } 1844 } 1845 1846 return TargetLowering::getConstraintType(Constraint); 1847 } 1848 1849 unsigned 1850 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { 1851 // Not sure if this is actually the right thing to do, but we got to do 1852 // *something* [agnat] 1853 switch (ConstraintCode[0]) { 1854 case 'Q': 1855 return InlineAsm::Constraint_Q; 1856 } 1857 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 1858 } 1859 1860 AVRTargetLowering::ConstraintWeight 1861 AVRTargetLowering::getSingleConstraintMatchWeight( 1862 AsmOperandInfo &info, const char *constraint) const { 1863 ConstraintWeight weight = CW_Invalid; 1864 Value *CallOperandVal = info.CallOperandVal; 1865 1866 // If we don't have a value, we can't do a match, 1867 // but allow it at the lowest weight. 1868 // (this behaviour has been copied from the ARM backend) 1869 if (!CallOperandVal) { 1870 return CW_Default; 1871 } 1872 1873 // Look at the constraint type. 1874 switch (*constraint) { 1875 default: 1876 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 1877 break; 1878 case 'd': 1879 case 'r': 1880 case 'l': 1881 weight = CW_Register; 1882 break; 1883 case 'a': 1884 case 'b': 1885 case 'e': 1886 case 'q': 1887 case 't': 1888 case 'w': 1889 case 'x': 1890 case 'X': 1891 case 'y': 1892 case 'Y': 1893 case 'z': 1894 case 'Z': 1895 weight = CW_SpecificReg; 1896 break; 1897 case 'G': 1898 if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) { 1899 if (C->isZero()) { 1900 weight = CW_Constant; 1901 } 1902 } 1903 break; 1904 case 'I': 1905 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1906 if (isUInt<6>(C->getZExtValue())) { 1907 weight = CW_Constant; 1908 } 1909 } 1910 break; 1911 case 'J': 1912 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1913 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) { 1914 weight = CW_Constant; 1915 } 1916 } 1917 break; 1918 case 'K': 1919 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1920 if (C->getZExtValue() == 2) { 1921 weight = CW_Constant; 1922 } 1923 } 1924 break; 1925 case 'L': 1926 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1927 if (C->getZExtValue() == 0) { 1928 weight = CW_Constant; 1929 } 1930 } 1931 break; 1932 case 'M': 1933 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1934 if (isUInt<8>(C->getZExtValue())) { 1935 weight = CW_Constant; 1936 } 1937 } 1938 break; 1939 case 'N': 1940 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1941 if (C->getSExtValue() == -1) { 1942 weight = CW_Constant; 1943 } 1944 } 1945 break; 1946 case 'O': 1947 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1948 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) || 1949 (C->getZExtValue() == 24)) { 1950 weight = CW_Constant; 1951 } 1952 } 1953 break; 1954 case 'P': 1955 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1956 if (C->getZExtValue() == 1) { 1957 weight = CW_Constant; 1958 } 1959 } 1960 break; 1961 case 'R': 1962 if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 1963 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) { 1964 weight = CW_Constant; 1965 } 1966 } 1967 break; 1968 case 'Q': 1969 weight = CW_Memory; 1970 break; 1971 } 1972 1973 return weight; 1974 } 1975 1976 std::pair<unsigned, const TargetRegisterClass *> 1977 AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1978 StringRef Constraint, 1979 MVT VT) const { 1980 if (Constraint.size() == 1) { 1981 switch (Constraint[0]) { 1982 case 'a': // Simple upper registers r16..r23. 1983 if (VT == MVT::i8) 1984 return std::make_pair(0U, &AVR::LD8loRegClass); 1985 else if (VT == MVT::i16) 1986 return std::make_pair(0U, &AVR::DREGSLD8loRegClass); 1987 break; 1988 case 'b': // Base pointer registers: y, z. 1989 if (VT == MVT::i8 || VT == MVT::i16) 1990 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass); 1991 break; 1992 case 'd': // Upper registers r16..r31. 1993 if (VT == MVT::i8) 1994 return std::make_pair(0U, &AVR::LD8RegClass); 1995 else if (VT == MVT::i16) 1996 return std::make_pair(0U, &AVR::DLDREGSRegClass); 1997 break; 1998 case 'l': // Lower registers r0..r15. 1999 if (VT == MVT::i8) 2000 return std::make_pair(0U, &AVR::GPR8loRegClass); 2001 else if (VT == MVT::i16) 2002 return std::make_pair(0U, &AVR::DREGSloRegClass); 2003 break; 2004 case 'e': // Pointer register pairs: x, y, z. 2005 if (VT == MVT::i8 || VT == MVT::i16) 2006 return std::make_pair(0U, &AVR::PTRREGSRegClass); 2007 break; 2008 case 'q': // Stack pointer register: SPH:SPL. 2009 return std::make_pair(0U, &AVR::GPRSPRegClass); 2010 case 'r': // Any register: r0..r31. 2011 if (VT == MVT::i8) 2012 return std::make_pair(0U, &AVR::GPR8RegClass); 2013 else if (VT == MVT::i16) 2014 return std::make_pair(0U, &AVR::DREGSRegClass); 2015 break; 2016 case 't': // Temporary register: r0. 2017 if (VT == MVT::i8) 2018 return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass); 2019 break; 2020 case 'w': // Special upper register pairs: r24, r26, r28, r30. 2021 if (VT == MVT::i8 || VT == MVT::i16) 2022 return std::make_pair(0U, &AVR::IWREGSRegClass); 2023 break; 2024 case 'x': // Pointer register pair X: r27:r26. 2025 case 'X': 2026 if (VT == MVT::i8 || VT == MVT::i16) 2027 return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass); 2028 break; 2029 case 'y': // Pointer register pair Y: r29:r28. 2030 case 'Y': 2031 if (VT == MVT::i8 || VT == MVT::i16) 2032 return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass); 2033 break; 2034 case 'z': // Pointer register pair Z: r31:r30. 2035 case 'Z': 2036 if (VT == MVT::i8 || VT == MVT::i16) 2037 return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass); 2038 break; 2039 default: 2040 break; 2041 } 2042 } 2043 2044 return TargetLowering::getRegForInlineAsmConstraint( 2045 Subtarget.getRegisterInfo(), Constraint, VT); 2046 } 2047 2048 void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2049 std::string &Constraint, 2050 std::vector<SDValue> &Ops, 2051 SelectionDAG &DAG) const { 2052 SDValue Result; 2053 SDLoc DL(Op); 2054 EVT Ty = Op.getValueType(); 2055 2056 // Currently only support length 1 constraints. 2057 if (Constraint.length() != 1) { 2058 return; 2059 } 2060 2061 char ConstraintLetter = Constraint[0]; 2062 switch (ConstraintLetter) { 2063 default: 2064 break; 2065 // Deal with integers first: 2066 case 'I': 2067 case 'J': 2068 case 'K': 2069 case 'L': 2070 case 'M': 2071 case 'N': 2072 case 'O': 2073 case 'P': 2074 case 'R': { 2075 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2076 if (!C) { 2077 return; 2078 } 2079 2080 int64_t CVal64 = C->getSExtValue(); 2081 uint64_t CUVal64 = C->getZExtValue(); 2082 switch (ConstraintLetter) { 2083 case 'I': // 0..63 2084 if (!isUInt<6>(CUVal64)) 2085 return; 2086 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2087 break; 2088 case 'J': // -63..0 2089 if (CVal64 < -63 || CVal64 > 0) 2090 return; 2091 Result = DAG.getTargetConstant(CVal64, DL, Ty); 2092 break; 2093 case 'K': // 2 2094 if (CUVal64 != 2) 2095 return; 2096 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2097 break; 2098 case 'L': // 0 2099 if (CUVal64 != 0) 2100 return; 2101 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2102 break; 2103 case 'M': // 0..255 2104 if (!isUInt<8>(CUVal64)) 2105 return; 2106 // i8 type may be printed as a negative number, 2107 // e.g. 254 would be printed as -2, 2108 // so we force it to i16 at least. 2109 if (Ty.getSimpleVT() == MVT::i8) { 2110 Ty = MVT::i16; 2111 } 2112 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2113 break; 2114 case 'N': // -1 2115 if (CVal64 != -1) 2116 return; 2117 Result = DAG.getTargetConstant(CVal64, DL, Ty); 2118 break; 2119 case 'O': // 8, 16, 24 2120 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24) 2121 return; 2122 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2123 break; 2124 case 'P': // 1 2125 if (CUVal64 != 1) 2126 return; 2127 Result = DAG.getTargetConstant(CUVal64, DL, Ty); 2128 break; 2129 case 'R': // -6..5 2130 if (CVal64 < -6 || CVal64 > 5) 2131 return; 2132 Result = DAG.getTargetConstant(CVal64, DL, Ty); 2133 break; 2134 } 2135 2136 break; 2137 } 2138 case 'G': 2139 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Op); 2140 if (!FC || !FC->isZero()) 2141 return; 2142 // Soften float to i8 0 2143 Result = DAG.getTargetConstant(0, DL, MVT::i8); 2144 break; 2145 } 2146 2147 if (Result.getNode()) { 2148 Ops.push_back(Result); 2149 return; 2150 } 2151 2152 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 2153 } 2154 2155 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, 2156 const MachineFunction &MF) const { 2157 Register Reg; 2158 2159 if (VT == LLT::scalar(8)) { 2160 Reg = StringSwitch<unsigned>(RegName) 2161 .Case("r0", AVR::R0) 2162 .Case("r1", AVR::R1) 2163 .Default(0); 2164 } else { 2165 Reg = StringSwitch<unsigned>(RegName) 2166 .Case("r0", AVR::R1R0) 2167 .Case("sp", AVR::SP) 2168 .Default(0); 2169 } 2170 2171 if (Reg) 2172 return Reg; 2173 2174 report_fatal_error( 2175 Twine("Invalid register name \"" + StringRef(RegName) + "\".")); 2176 } 2177 2178 } // end of namespace llvm 2179