xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AVRAsmPrinter.cpp (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric //===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
2*0b57cec5SDimitry Andric //
3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric //
7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
8*0b57cec5SDimitry Andric //
9*0b57cec5SDimitry Andric // This file contains a printer that converts from our internal representation
10*0b57cec5SDimitry Andric // of machine-dependent LLVM code to GAS-format AVR assembly language.
11*0b57cec5SDimitry Andric //
12*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
13*0b57cec5SDimitry Andric 
14*0b57cec5SDimitry Andric #include "AVR.h"
15*0b57cec5SDimitry Andric #include "AVRMCInstLower.h"
16*0b57cec5SDimitry Andric #include "AVRSubtarget.h"
17*0b57cec5SDimitry Andric #include "MCTargetDesc/AVRInstPrinter.h"
18*0b57cec5SDimitry Andric #include "TargetInfo/AVRTargetInfo.h"
19*0b57cec5SDimitry Andric 
20*0b57cec5SDimitry Andric #include "llvm/CodeGen/AsmPrinter.h"
21*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineFunction.h"
22*0b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstr.h"
23*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h"
24*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetSubtargetInfo.h"
25*0b57cec5SDimitry Andric #include "llvm/IR/Mangler.h"
26*0b57cec5SDimitry Andric #include "llvm/MC/MCInst.h"
27*0b57cec5SDimitry Andric #include "llvm/MC/MCStreamer.h"
28*0b57cec5SDimitry Andric #include "llvm/MC/MCSymbol.h"
29*0b57cec5SDimitry Andric #include "llvm/Support/ErrorHandling.h"
30*0b57cec5SDimitry Andric #include "llvm/Support/TargetRegistry.h"
31*0b57cec5SDimitry Andric #include "llvm/Support/raw_ostream.h"
32*0b57cec5SDimitry Andric 
33*0b57cec5SDimitry Andric #define DEBUG_TYPE "avr-asm-printer"
34*0b57cec5SDimitry Andric 
35*0b57cec5SDimitry Andric namespace llvm {
36*0b57cec5SDimitry Andric 
37*0b57cec5SDimitry Andric /// An AVR assembly code printer.
38*0b57cec5SDimitry Andric class AVRAsmPrinter : public AsmPrinter {
39*0b57cec5SDimitry Andric public:
40*0b57cec5SDimitry Andric   AVRAsmPrinter(TargetMachine &TM,
41*0b57cec5SDimitry Andric                 std::unique_ptr<MCStreamer> Streamer)
42*0b57cec5SDimitry Andric       : AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) { }
43*0b57cec5SDimitry Andric 
44*0b57cec5SDimitry Andric   StringRef getPassName() const override { return "AVR Assembly Printer"; }
45*0b57cec5SDimitry Andric 
46*0b57cec5SDimitry Andric   void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
47*0b57cec5SDimitry Andric 
48*0b57cec5SDimitry Andric   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
49*0b57cec5SDimitry Andric                        const char *ExtraCode, raw_ostream &O) override;
50*0b57cec5SDimitry Andric 
51*0b57cec5SDimitry Andric   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
52*0b57cec5SDimitry Andric                              const char *ExtraCode, raw_ostream &O) override;
53*0b57cec5SDimitry Andric 
54*0b57cec5SDimitry Andric   void EmitInstruction(const MachineInstr *MI) override;
55*0b57cec5SDimitry Andric 
56*0b57cec5SDimitry Andric private:
57*0b57cec5SDimitry Andric   const MCRegisterInfo &MRI;
58*0b57cec5SDimitry Andric };
59*0b57cec5SDimitry Andric 
60*0b57cec5SDimitry Andric void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
61*0b57cec5SDimitry Andric                                  raw_ostream &O) {
62*0b57cec5SDimitry Andric   const MachineOperand &MO = MI->getOperand(OpNo);
63*0b57cec5SDimitry Andric 
64*0b57cec5SDimitry Andric   switch (MO.getType()) {
65*0b57cec5SDimitry Andric   case MachineOperand::MO_Register:
66*0b57cec5SDimitry Andric     O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI);
67*0b57cec5SDimitry Andric     break;
68*0b57cec5SDimitry Andric   case MachineOperand::MO_Immediate:
69*0b57cec5SDimitry Andric     O << MO.getImm();
70*0b57cec5SDimitry Andric     break;
71*0b57cec5SDimitry Andric   case MachineOperand::MO_GlobalAddress:
72*0b57cec5SDimitry Andric     O << getSymbol(MO.getGlobal());
73*0b57cec5SDimitry Andric     break;
74*0b57cec5SDimitry Andric   case MachineOperand::MO_ExternalSymbol:
75*0b57cec5SDimitry Andric     O << *GetExternalSymbolSymbol(MO.getSymbolName());
76*0b57cec5SDimitry Andric     break;
77*0b57cec5SDimitry Andric   case MachineOperand::MO_MachineBasicBlock:
78*0b57cec5SDimitry Andric     O << *MO.getMBB()->getSymbol();
79*0b57cec5SDimitry Andric     break;
80*0b57cec5SDimitry Andric   default:
81*0b57cec5SDimitry Andric     llvm_unreachable("Not implemented yet!");
82*0b57cec5SDimitry Andric   }
83*0b57cec5SDimitry Andric }
84*0b57cec5SDimitry Andric 
85*0b57cec5SDimitry Andric bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
86*0b57cec5SDimitry Andric                                     const char *ExtraCode, raw_ostream &O) {
87*0b57cec5SDimitry Andric   // Default asm printer can only deal with some extra codes,
88*0b57cec5SDimitry Andric   // so try it first.
89*0b57cec5SDimitry Andric   bool Error = AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
90*0b57cec5SDimitry Andric 
91*0b57cec5SDimitry Andric   if (Error && ExtraCode && ExtraCode[0]) {
92*0b57cec5SDimitry Andric     if (ExtraCode[1] != 0)
93*0b57cec5SDimitry Andric       return true; // Unknown modifier.
94*0b57cec5SDimitry Andric 
95*0b57cec5SDimitry Andric     if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
96*0b57cec5SDimitry Andric       const MachineOperand &RegOp = MI->getOperand(OpNum);
97*0b57cec5SDimitry Andric 
98*0b57cec5SDimitry Andric       assert(RegOp.isReg() && "Operand must be a register when you're"
99*0b57cec5SDimitry Andric                               "using 'A'..'Z' operand extracodes.");
100*0b57cec5SDimitry Andric       unsigned Reg = RegOp.getReg();
101*0b57cec5SDimitry Andric 
102*0b57cec5SDimitry Andric       unsigned ByteNumber = ExtraCode[0] - 'A';
103*0b57cec5SDimitry Andric 
104*0b57cec5SDimitry Andric       unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
105*0b57cec5SDimitry Andric       unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
106*0b57cec5SDimitry Andric       (void)NumOpRegs;
107*0b57cec5SDimitry Andric 
108*0b57cec5SDimitry Andric       const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
109*0b57cec5SDimitry Andric       const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
110*0b57cec5SDimitry Andric 
111*0b57cec5SDimitry Andric       const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
112*0b57cec5SDimitry Andric       unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
113*0b57cec5SDimitry Andric       assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
114*0b57cec5SDimitry Andric 
115*0b57cec5SDimitry Andric       unsigned RegIdx = ByteNumber / BytesPerReg;
116*0b57cec5SDimitry Andric       assert(RegIdx < NumOpRegs && "Multibyte index out of range.");
117*0b57cec5SDimitry Andric 
118*0b57cec5SDimitry Andric       Reg = MI->getOperand(OpNum + RegIdx).getReg();
119*0b57cec5SDimitry Andric 
120*0b57cec5SDimitry Andric       if (BytesPerReg == 2) {
121*0b57cec5SDimitry Andric         Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
122*0b57cec5SDimitry Andric                                                           : AVR::sub_lo);
123*0b57cec5SDimitry Andric       }
124*0b57cec5SDimitry Andric 
125*0b57cec5SDimitry Andric       O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
126*0b57cec5SDimitry Andric       return false;
127*0b57cec5SDimitry Andric     }
128*0b57cec5SDimitry Andric   }
129*0b57cec5SDimitry Andric 
130*0b57cec5SDimitry Andric   if (Error)
131*0b57cec5SDimitry Andric     printOperand(MI, OpNum, O);
132*0b57cec5SDimitry Andric 
133*0b57cec5SDimitry Andric   return false;
134*0b57cec5SDimitry Andric }
135*0b57cec5SDimitry Andric 
136*0b57cec5SDimitry Andric bool AVRAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
137*0b57cec5SDimitry Andric                                           unsigned OpNum, const char *ExtraCode,
138*0b57cec5SDimitry Andric                                           raw_ostream &O) {
139*0b57cec5SDimitry Andric   if (ExtraCode && ExtraCode[0]) {
140*0b57cec5SDimitry Andric     llvm_unreachable("This branch is not implemented yet");
141*0b57cec5SDimitry Andric   }
142*0b57cec5SDimitry Andric 
143*0b57cec5SDimitry Andric   const MachineOperand &MO = MI->getOperand(OpNum);
144*0b57cec5SDimitry Andric   (void)MO;
145*0b57cec5SDimitry Andric   assert(MO.isReg() && "Unexpected inline asm memory operand");
146*0b57cec5SDimitry Andric 
147*0b57cec5SDimitry Andric   // TODO: We should be able to look up the alternative name for
148*0b57cec5SDimitry Andric   // the register if it's given.
149*0b57cec5SDimitry Andric   // TableGen doesn't expose a way of getting retrieving names
150*0b57cec5SDimitry Andric   // for registers.
151*0b57cec5SDimitry Andric   if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
152*0b57cec5SDimitry Andric     O << "Z";
153*0b57cec5SDimitry Andric   } else {
154*0b57cec5SDimitry Andric     assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
155*0b57cec5SDimitry Andric            "Wrong register class for memory operand.");
156*0b57cec5SDimitry Andric     O << "Y";
157*0b57cec5SDimitry Andric   }
158*0b57cec5SDimitry Andric 
159*0b57cec5SDimitry Andric   // If NumOpRegs == 2, then we assume it is product of a FrameIndex expansion
160*0b57cec5SDimitry Andric   // and the second operand is an Imm.
161*0b57cec5SDimitry Andric   unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
162*0b57cec5SDimitry Andric   unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
163*0b57cec5SDimitry Andric 
164*0b57cec5SDimitry Andric   if (NumOpRegs == 2) {
165*0b57cec5SDimitry Andric     O << '+' << MI->getOperand(OpNum + 1).getImm();
166*0b57cec5SDimitry Andric   }
167*0b57cec5SDimitry Andric 
168*0b57cec5SDimitry Andric   return false;
169*0b57cec5SDimitry Andric }
170*0b57cec5SDimitry Andric 
171*0b57cec5SDimitry Andric void AVRAsmPrinter::EmitInstruction(const MachineInstr *MI) {
172*0b57cec5SDimitry Andric   AVRMCInstLower MCInstLowering(OutContext, *this);
173*0b57cec5SDimitry Andric 
174*0b57cec5SDimitry Andric   MCInst I;
175*0b57cec5SDimitry Andric   MCInstLowering.lowerInstruction(*MI, I);
176*0b57cec5SDimitry Andric   EmitToStreamer(*OutStreamer, I);
177*0b57cec5SDimitry Andric }
178*0b57cec5SDimitry Andric 
179*0b57cec5SDimitry Andric } // end of namespace llvm
180*0b57cec5SDimitry Andric 
181*0b57cec5SDimitry Andric extern "C" void LLVMInitializeAVRAsmPrinter() {
182*0b57cec5SDimitry Andric   llvm::RegisterAsmPrinter<llvm::AVRAsmPrinter> X(llvm::getTheAVRTarget());
183*0b57cec5SDimitry Andric }
184*0b57cec5SDimitry Andric 
185