1*0b57cec5SDimitry Andric//===-- AVR.td - Describe the AVR Target Machine ----------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// This is the top level entry point for the AVR target. 9*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 10*0b57cec5SDimitry Andric 11*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 13*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 18*0b57cec5SDimitry Andric// AVR Device Definitions 19*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andricinclude "AVRDevices.td" 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 24*0b57cec5SDimitry Andric// Register File Description 25*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andricinclude "AVRRegisterInfo.td" 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 30*0b57cec5SDimitry Andric// Instruction Descriptions 31*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andricinclude "AVRInstrInfo.td" 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andricdef AVRInstrInfo : InstrInfo; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 38*0b57cec5SDimitry Andric// Calling Conventions 39*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 40*0b57cec5SDimitry Andric 41*0b57cec5SDimitry Andricinclude "AVRCallingConv.td" 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 44*0b57cec5SDimitry Andric// Assembly Printers 45*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andricdef AVRAsmWriter : AsmWriter { 48*0b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 49*0b57cec5SDimitry Andric bit isMCAsmWriter = 1; 50*0b57cec5SDimitry Andric} 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 53*0b57cec5SDimitry Andric// Assembly Parsers 54*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 55*0b57cec5SDimitry Andric 56*0b57cec5SDimitry Andricdef AVRAsmParser : AsmParser { 57*0b57cec5SDimitry Andric let ShouldEmitMatchRegisterName = 1; 58*0b57cec5SDimitry Andric let ShouldEmitMatchRegisterAltName = 1; 59*0b57cec5SDimitry Andric} 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andricdef AVRAsmParserVariant : AsmParserVariant { 62*0b57cec5SDimitry Andric int Variant = 0; 63*0b57cec5SDimitry Andric 64*0b57cec5SDimitry Andric // Recognize hard coded registers. 65*0b57cec5SDimitry Andric string RegisterPrefix = "$"; 66*0b57cec5SDimitry Andric string TokenizingCharacters = "+"; 67*0b57cec5SDimitry Andric} 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 70*0b57cec5SDimitry Andric// Target Declaration 71*0b57cec5SDimitry Andric//===---------------------------------------------------------------------===// 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andricdef AVR : Target { 74*0b57cec5SDimitry Andric let InstructionSet = AVRInstrInfo; 75*0b57cec5SDimitry Andric let AssemblyWriters = [AVRAsmWriter]; 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andric let AssemblyParsers = [AVRAsmParser]; 78*0b57cec5SDimitry Andric let AssemblyParserVariants = [AVRAsmParserVariant]; 79*0b57cec5SDimitry Andric} 80