1 //===-- ARMBaseInfo.cpp - ARM Base encoding information------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides basic encoding and assembly information for ARM. 10 // 11 //===----------------------------------------------------------------------===// 12 #include "ARMBaseInfo.h" 13 #include "llvm/ADT/ArrayRef.h" 14 #include "llvm/ADT/SmallVector.h" 15 16 using namespace llvm; 17 namespace llvm { 18 ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, 19 ARMVCC::VPTCodes Kind) { 20 using PredBlockMask = ARM::PredBlockMask; 21 assert(Kind != ARMVCC::None && "Cannot expand a mask with None!"); 22 assert(countTrailingZeros((unsigned)BlockMask) != 0 && 23 "Mask is already full"); 24 25 auto ChooseMask = [&](PredBlockMask AddedThen, PredBlockMask AddedElse) { 26 return Kind == ARMVCC::Then ? AddedThen : AddedElse; 27 }; 28 29 switch (BlockMask) { 30 case PredBlockMask::T: 31 return ChooseMask(PredBlockMask::TT, PredBlockMask::TE); 32 case PredBlockMask::TT: 33 return ChooseMask(PredBlockMask::TTT, PredBlockMask::TTE); 34 case PredBlockMask::TE: 35 return ChooseMask(PredBlockMask::TET, PredBlockMask::TEE); 36 case PredBlockMask::TTT: 37 return ChooseMask(PredBlockMask::TTTT, PredBlockMask::TTTE); 38 case PredBlockMask::TTE: 39 return ChooseMask(PredBlockMask::TTET, PredBlockMask::TTEE); 40 case PredBlockMask::TET: 41 return ChooseMask(PredBlockMask::TETT, PredBlockMask::TETE); 42 case PredBlockMask::TEE: 43 return ChooseMask(PredBlockMask::TEET, PredBlockMask::TEEE); 44 default: 45 llvm_unreachable("Unknown Mask"); 46 } 47 } 48 49 namespace ARMSysReg { 50 51 // lookup system register using 12-bit SYSm value. 52 // Note: the search is uniqued using M1 mask 53 const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm) { 54 return lookupMClassSysRegByM1Encoding12(SYSm); 55 } 56 57 // returns APSR with _<bits> qualifier. 58 // Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier 59 const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm) { 60 return lookupMClassSysRegByM2M3Encoding8((1<<9)|(SYSm & 0xFF)); 61 } 62 63 // lookup system registers using 8-bit SYSm value 64 const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm) { 65 return ARMSysReg::lookupMClassSysRegByM2M3Encoding8((1<<8)|(SYSm & 0xFF)); 66 } 67 68 #define GET_MCLASSSYSREG_IMPL 69 #include "ARMGenSystemRegister.inc" 70 71 } // end namespace ARMSysReg 72 73 namespace ARMBankedReg { 74 #define GET_BANKEDREG_IMPL 75 #include "ARMGenSystemRegister.inc" 76 } // end namespce ARMSysReg 77 } // end namespace llvm 78