10b57cec5SDimitry Andric //===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the Thumb implementation of the TargetRegisterInfo 100b57cec5SDimitry Andric // class. With the exception of emitLoadConstPool Thumb2 tracks 110b57cec5SDimitry Andric // ARMBaseRegisterInfo, Thumb1 overloads the functions below. 120b57cec5SDimitry Andric // 130b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 160b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include "ARMBaseRegisterInfo.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric namespace llvm { 220b57cec5SDimitry Andric class ARMSubtarget; 230b57cec5SDimitry Andric class ARMBaseInstrInfo; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric struct ThumbRegisterInfo : public ARMBaseRegisterInfo { 260b57cec5SDimitry Andric public: 270b57cec5SDimitry Andric ThumbRegisterInfo(); 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric const TargetRegisterClass * 300b57cec5SDimitry Andric getLargestLegalSuperClass(const TargetRegisterClass *RC, 310b57cec5SDimitry Andric const MachineFunction &MF) const override; 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric const TargetRegisterClass * 340b57cec5SDimitry Andric getPointerRegClass(const MachineFunction &MF, 350b57cec5SDimitry Andric unsigned Kind = 0) const override; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric /// emitLoadConstPool - Emits a load from constpool to materialize the 380b57cec5SDimitry Andric /// specified immediate. 390b57cec5SDimitry Andric void 400b57cec5SDimitry Andric emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 41*5ffd83dbSDimitry Andric const DebugLoc &dl, Register DestReg, unsigned SubIdx, 420b57cec5SDimitry Andric int Val, ARMCC::CondCodes Pred = ARMCC::AL, 43*5ffd83dbSDimitry Andric Register PredReg = Register(), 440b57cec5SDimitry Andric unsigned MIFlags = MachineInstr::NoFlags) const override; 450b57cec5SDimitry Andric 460b57cec5SDimitry Andric // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be 470b57cec5SDimitry Andric // however much remains to be handled. Return 'true' if no further 480b57cec5SDimitry Andric // work is required. 490b57cec5SDimitry Andric bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, 50*5ffd83dbSDimitry Andric Register FrameReg, int &Offset, 510b57cec5SDimitry Andric const ARMBaseInstrInfo &TII) const; 52*5ffd83dbSDimitry Andric void resolveFrameIndex(MachineInstr &MI, Register BaseReg, 530b57cec5SDimitry Andric int64_t Offset) const override; 540b57cec5SDimitry Andric void eliminateFrameIndex(MachineBasicBlock::iterator II, 550b57cec5SDimitry Andric int SPAdj, unsigned FIOperandNum, 560b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 570b57cec5SDimitry Andric bool useFPForScavengingIndex(const MachineFunction &MF) const override; 580b57cec5SDimitry Andric }; 590b57cec5SDimitry Andric } 600b57cec5SDimitry Andric 610b57cec5SDimitry Andric #endif 62