1*0b57cec5SDimitry Andric //===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the Thumb implementation of the TargetRegisterInfo 10*0b57cec5SDimitry Andric // class. With the exception of emitLoadConstPool Thumb2 tracks 11*0b57cec5SDimitry Andric // ARMBaseRegisterInfo, Thumb1 overloads the functions below. 12*0b57cec5SDimitry Andric // 13*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 16*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric #include "ARMBaseRegisterInfo.h" 19*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetRegisterInfo.h" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric namespace llvm { 22*0b57cec5SDimitry Andric class ARMSubtarget; 23*0b57cec5SDimitry Andric class ARMBaseInstrInfo; 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andric struct ThumbRegisterInfo : public ARMBaseRegisterInfo { 26*0b57cec5SDimitry Andric public: 27*0b57cec5SDimitry Andric ThumbRegisterInfo(); 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric const TargetRegisterClass * 30*0b57cec5SDimitry Andric getLargestLegalSuperClass(const TargetRegisterClass *RC, 31*0b57cec5SDimitry Andric const MachineFunction &MF) const override; 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andric const TargetRegisterClass * 34*0b57cec5SDimitry Andric getPointerRegClass(const MachineFunction &MF, 35*0b57cec5SDimitry Andric unsigned Kind = 0) const override; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andric /// emitLoadConstPool - Emits a load from constpool to materialize the 38*0b57cec5SDimitry Andric /// specified immediate. 39*0b57cec5SDimitry Andric void 40*0b57cec5SDimitry Andric emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 41*0b57cec5SDimitry Andric const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, 42*0b57cec5SDimitry Andric int Val, ARMCC::CondCodes Pred = ARMCC::AL, 43*0b57cec5SDimitry Andric unsigned PredReg = 0, 44*0b57cec5SDimitry Andric unsigned MIFlags = MachineInstr::NoFlags) const override; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andric // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be 47*0b57cec5SDimitry Andric // however much remains to be handled. Return 'true' if no further 48*0b57cec5SDimitry Andric // work is required. 49*0b57cec5SDimitry Andric bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, 50*0b57cec5SDimitry Andric unsigned FrameReg, int &Offset, 51*0b57cec5SDimitry Andric const ARMBaseInstrInfo &TII) const; 52*0b57cec5SDimitry Andric void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 53*0b57cec5SDimitry Andric int64_t Offset) const override; 54*0b57cec5SDimitry Andric void eliminateFrameIndex(MachineBasicBlock::iterator II, 55*0b57cec5SDimitry Andric int SPAdj, unsigned FIOperandNum, 56*0b57cec5SDimitry Andric RegScavenger *RS = nullptr) const override; 57*0b57cec5SDimitry Andric bool useFPForScavengingIndex(const MachineFunction &MF) const override; 58*0b57cec5SDimitry Andric }; 59*0b57cec5SDimitry Andric } 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andric #endif 62