1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H 14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H 15 16 #include "ARMBaseInstrInfo.h" 17 #include "ThumbRegisterInfo.h" 18 19 namespace llvm { 20 class ARMSubtarget; 21 22 class Thumb2InstrInfo : public ARMBaseInstrInfo { 23 ThumbRegisterInfo RI; 24 public: 25 explicit Thumb2InstrInfo(const ARMSubtarget &STI); 26 27 /// Return the noop instruction to use for a noop. 28 MCInst getNop() const override; 29 30 // Return the non-pre/post incrementing version of 'Opc'. Return 0 31 // if there is not such an opcode. 32 unsigned getUnindexedOpcode(unsigned Opc) const override; 33 34 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 35 MachineBasicBlock *NewDest) const override; 36 37 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 38 MachineBasicBlock::iterator MBBI) const override; 39 40 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 41 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 42 bool KillSrc) const override; 43 44 void storeRegToStackSlot(MachineBasicBlock &MBB, 45 MachineBasicBlock::iterator MBBI, 46 Register SrcReg, bool isKill, int FrameIndex, 47 const TargetRegisterClass *RC, 48 const TargetRegisterInfo *TRI) const override; 49 50 void loadRegFromStackSlot(MachineBasicBlock &MBB, 51 MachineBasicBlock::iterator MBBI, 52 Register DestReg, int FrameIndex, 53 const TargetRegisterClass *RC, 54 const TargetRegisterInfo *TRI) const override; 55 56 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 57 /// such, whenever a client has an instance of instruction info, it should 58 /// always be able to get register info as well (through this method). 59 /// 60 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; } 61 62 MachineInstr *optimizeSelect(MachineInstr &MI, 63 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 64 bool) const override; 65 66 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 67 unsigned OpIdx1, 68 unsigned OpIdx2) const override; 69 70 private: 71 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; 72 }; 73 74 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 75 /// to llvm::getInstrPredicate except it returns AL for conditional branch 76 /// instructions which are "predicated", but are not in IT blocks. 77 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg); 78 79 // getVPTInstrPredicate: VPT analogue of that, plus a helper function 80 // corresponding to MachineInstr::findFirstPredOperandIdx. 81 int findFirstVPTPredOperandIdx(const MachineInstr &MI); 82 ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, 83 Register &PredReg); 84 inline ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI) { 85 Register PredReg; 86 return getVPTInstrPredicate(MI, PredReg); 87 } 88 89 // Recomputes the Block Mask of Instr, a VPT or VPST instruction. 90 // This rebuilds the block mask of the instruction depending on the predicates 91 // of the instructions following it. This should only be used after the 92 // MVEVPTBlockInsertion pass has run, and should be used whenever a predicated 93 // instruction is added to/removed from the block. 94 void recomputeVPTBlockMask(MachineInstr &Instr); 95 } // namespace llvm 96 97 #endif 98