1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARM.h" 10 #include "ARMMachineFunctionInfo.h" 11 #include "ARMSubtarget.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "Thumb2InstrInfo.h" 14 #include "llvm/ADT/SmallSet.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/Statistic.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/CodeGen/MachineBasicBlock.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/MachineInstr.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineInstrBundle.h" 24 #include "llvm/CodeGen/MachineOperand.h" 25 #include "llvm/IR/DebugLoc.h" 26 #include "llvm/MC/MCInstrDesc.h" 27 #include "llvm/MC/MCRegisterInfo.h" 28 #include <cassert> 29 #include <new> 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "thumb2-it" 34 #define PASS_NAME "Thumb IT blocks insertion pass" 35 36 STATISTIC(NumITs, "Number of IT blocks inserted"); 37 STATISTIC(NumMovedInsts, "Number of predicated instructions moved"); 38 39 using RegisterSet = SmallSet<unsigned, 4>; 40 41 namespace { 42 43 class Thumb2ITBlock : public MachineFunctionPass { 44 public: 45 static char ID; 46 47 bool restrictIT; 48 const Thumb2InstrInfo *TII; 49 const TargetRegisterInfo *TRI; 50 ARMFunctionInfo *AFI; 51 52 Thumb2ITBlock() : MachineFunctionPass(ID) {} 53 54 bool runOnMachineFunction(MachineFunction &Fn) override; 55 56 MachineFunctionProperties getRequiredProperties() const override { 57 return MachineFunctionProperties().set( 58 MachineFunctionProperties::Property::NoVRegs); 59 } 60 61 StringRef getPassName() const override { 62 return PASS_NAME; 63 } 64 65 private: 66 bool MoveCopyOutOfITBlock(MachineInstr *MI, 67 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 68 RegisterSet &Defs, RegisterSet &Uses); 69 bool InsertITInstructions(MachineBasicBlock &Block); 70 }; 71 72 char Thumb2ITBlock::ID = 0; 73 74 } // end anonymous namespace 75 76 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false) 77 78 /// TrackDefUses - Tracking what registers are being defined and used by 79 /// instructions in the IT block. This also tracks "dependencies", i.e. uses 80 /// in the IT block that are defined before the IT instruction. 81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, 82 const TargetRegisterInfo *TRI) { 83 using RegList = SmallVector<unsigned, 4>; 84 RegList LocalDefs; 85 RegList LocalUses; 86 87 for (auto &MO : MI->operands()) { 88 if (!MO.isReg()) 89 continue; 90 Register Reg = MO.getReg(); 91 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP) 92 continue; 93 if (MO.isUse()) 94 LocalUses.push_back(Reg); 95 else 96 LocalDefs.push_back(Reg); 97 } 98 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { 100 for (unsigned Reg : Regs) 101 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); 102 Subreg.isValid(); ++Subreg) 103 UsesDefs.insert(*Subreg); 104 }; 105 106 InsertUsesDefs(LocalDefs, Defs); 107 InsertUsesDefs(LocalUses, Uses); 108 } 109 110 /// Clear kill flags for any uses in the given set. This will likely 111 /// conservatively remove more kill flags than are necessary, but removing them 112 /// is safer than incorrect kill flags remaining on instructions. 113 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) { 114 for (MachineOperand &MO : MI->operands()) { 115 if (!MO.isReg() || MO.isDef() || !MO.isKill()) 116 continue; 117 if (!Uses.count(MO.getReg())) 118 continue; 119 MO.setIsKill(false); 120 } 121 } 122 123 static bool isCopy(MachineInstr *MI) { 124 switch (MI->getOpcode()) { 125 default: 126 return false; 127 case ARM::MOVr: 128 case ARM::MOVr_TC: 129 case ARM::tMOVr: 130 case ARM::t2MOVr: 131 return true; 132 } 133 } 134 135 bool 136 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI, 137 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 138 RegisterSet &Defs, RegisterSet &Uses) { 139 if (!isCopy(MI)) 140 return false; 141 // llvm models select's as two-address instructions. That means a copy 142 // is inserted before a t2MOVccr, etc. If the copy is scheduled in 143 // between selects we would end up creating multiple IT blocks. 144 assert(MI->getOperand(0).getSubReg() == 0 && 145 MI->getOperand(1).getSubReg() == 0 && 146 "Sub-register indices still around?"); 147 148 Register DstReg = MI->getOperand(0).getReg(); 149 Register SrcReg = MI->getOperand(1).getReg(); 150 151 // First check if it's safe to move it. 152 if (Uses.count(DstReg) || Defs.count(SrcReg)) 153 return false; 154 155 // If the CPSR is defined by this copy, then we don't want to move it. E.g., 156 // if we have: 157 // 158 // movs r1, r1 159 // rsb r1, 0 160 // movs r2, r2 161 // rsb r2, 0 162 // 163 // we don't want this to be converted to: 164 // 165 // movs r1, r1 166 // movs r2, r2 167 // itt mi 168 // rsb r1, 0 169 // rsb r2, 0 170 // 171 const MCInstrDesc &MCID = MI->getDesc(); 172 if (MI->hasOptionalDef() && 173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) 174 return false; 175 176 // Then peek at the next instruction to see if it's predicated on CC or OCC. 177 // If not, then there is nothing to be gained by moving the copy. 178 MachineBasicBlock::iterator I = MI; 179 ++I; 180 MachineBasicBlock::iterator E = MI->getParent()->end(); 181 182 while (I != E && I->isDebugInstr()) 183 ++I; 184 185 if (I != E) { 186 Register NPredReg; 187 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); 188 if (NCC == CC || NCC == OCC) 189 return true; 190 } 191 return false; 192 } 193 194 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { 195 bool Modified = false; 196 RegisterSet Defs, Uses; 197 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 198 199 while (MBBI != E) { 200 MachineInstr *MI = &*MBBI; 201 DebugLoc dl = MI->getDebugLoc(); 202 Register PredReg; 203 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); 204 if (CC == ARMCC::AL) { 205 ++MBBI; 206 continue; 207 } 208 209 Defs.clear(); 210 Uses.clear(); 211 TrackDefUses(MI, Defs, Uses, TRI); 212 213 // Insert an IT instruction. 214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 215 .addImm(CC); 216 217 // Add implicit use of ITSTATE to IT block instructions. 218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 219 true/*isImp*/, false/*isKill*/)); 220 221 MachineInstr *LastITMI = MI; 222 MachineBasicBlock::iterator InsertPos = MIB.getInstr(); 223 ++MBBI; 224 225 // Form IT block. 226 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 227 unsigned Mask = 0, Pos = 3; 228 229 // IT blocks are limited to one conditional op if -arm-restrict-it 230 // is set: skip the loop 231 if (!restrictIT) { 232 LLVM_DEBUG(dbgs() << "Allowing complex IT block\n";); 233 // Branches, including tricky ones like LDM_RET, need to end an IT 234 // block so check the instruction we just put in the block. 235 for (; MBBI != E && Pos && 236 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { 237 if (MBBI->isDebugInstr()) 238 continue; 239 240 MachineInstr *NMI = &*MBBI; 241 MI = NMI; 242 243 Register NPredReg; 244 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); 245 if (NCC == CC || NCC == OCC) { 246 Mask |= ((NCC ^ CC) & 1) << Pos; 247 // Add implicit use of ITSTATE. 248 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 249 true/*isImp*/, false/*isKill*/)); 250 LastITMI = NMI; 251 } else { 252 if (NCC == ARMCC::AL && 253 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { 254 --MBBI; 255 MBB.remove(NMI); 256 MBB.insert(InsertPos, NMI); 257 ClearKillFlags(MI, Uses); 258 ++NumMovedInsts; 259 continue; 260 } 261 break; 262 } 263 TrackDefUses(NMI, Defs, Uses, TRI); 264 --Pos; 265 } 266 } 267 268 // Finalize IT mask. 269 Mask |= (1 << Pos); 270 MIB.addImm(Mask); 271 272 // Last instruction in IT block kills ITSTATE. 273 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill(); 274 275 // Finalize the bundle. 276 finalizeBundle(MBB, InsertPos.getInstrIterator(), 277 ++LastITMI->getIterator()); 278 279 Modified = true; 280 ++NumITs; 281 } 282 283 return Modified; 284 } 285 286 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) { 287 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>(); 288 if (!STI.isThumb2()) 289 return false; 290 AFI = Fn.getInfo<ARMFunctionInfo>(); 291 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo()); 292 TRI = STI.getRegisterInfo(); 293 restrictIT = STI.restrictIT(); 294 295 if (!AFI->isThumbFunction()) 296 return false; 297 298 bool Modified = false; 299 for (auto &MBB : Fn ) 300 Modified |= InsertITInstructions(MBB); 301 302 if (Modified) 303 AFI->setHasITBlocks(true); 304 305 return Modified; 306 } 307 308 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks 309 /// insertion pass. 310 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); } 311