1 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "Thumb1InstrInfo.h" 14 #include "ARMSubtarget.h" 15 #include "llvm/CodeGen/MachineFrameInfo.h" 16 #include "llvm/CodeGen/MachineInstrBuilder.h" 17 #include "llvm/CodeGen/MachineMemOperand.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstBuilder.h" 20 21 using namespace llvm; 22 23 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 24 : ARMBaseInstrInfo(STI) {} 25 26 /// Return the noop instruction to use for a noop. 27 MCInst Thumb1InstrInfo::getNop() const { 28 return MCInstBuilder(ARM::tMOVr) 29 .addReg(ARM::R8) 30 .addReg(ARM::R8) 31 .addImm(ARMCC::AL) 32 .addReg(0); 33 } 34 35 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 36 return 0; 37 } 38 39 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 40 MachineBasicBlock::iterator I, 41 const DebugLoc &DL, MCRegister DestReg, 42 MCRegister SrcReg, bool KillSrc) const { 43 // Need to check the arch. 44 MachineFunction &MF = *MBB.getParent(); 45 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>(); 46 47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 48 "Thumb1 can only copy GPR registers"); 49 50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) 51 || !ARM::tGPRRegClass.contains(DestReg)) 52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 53 .addReg(SrcReg, getKillRegState(KillSrc)) 54 .add(predOps(ARMCC::AL)); 55 else { 56 // FIXME: Can also use 'mov hi, $src; mov $dst, hi', 57 // with hi as either r10 or r11. 58 59 const TargetRegisterInfo *RegInfo = st.getRegisterInfo(); 60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) 61 == MachineBasicBlock::LQR_Dead) { 62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) 63 .addReg(SrcReg, getKillRegState(KillSrc)) 64 ->addRegisterDead(ARM::CPSR, RegInfo); 65 return; 66 } 67 68 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it 69 BuildMI(MBB, I, DL, get(ARM::tPUSH)) 70 .add(predOps(ARMCC::AL)) 71 .addReg(SrcReg, getKillRegState(KillSrc)); 72 BuildMI(MBB, I, DL, get(ARM::tPOP)) 73 .add(predOps(ARMCC::AL)) 74 .addReg(DestReg, getDefRegState(true)); 75 } 76 } 77 78 void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator I, 80 Register SrcReg, bool isKill, int FI, 81 const TargetRegisterClass *RC, 82 const TargetRegisterInfo *TRI, 83 Register VReg) const { 84 assert((RC == &ARM::tGPRRegClass || 85 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) && 86 "Unknown regclass!"); 87 88 if (RC == &ARM::tGPRRegClass || 89 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) { 90 DebugLoc DL; 91 if (I != MBB.end()) DL = I->getDebugLoc(); 92 93 MachineFunction &MF = *MBB.getParent(); 94 MachineFrameInfo &MFI = MF.getFrameInfo(); 95 MachineMemOperand *MMO = MF.getMachineMemOperand( 96 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore, 97 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 98 BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 99 .addReg(SrcReg, getKillRegState(isKill)) 100 .addFrameIndex(FI) 101 .addImm(0) 102 .addMemOperand(MMO) 103 .add(predOps(ARMCC::AL)); 104 } 105 } 106 107 void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator I, 109 Register DestReg, int FI, 110 const TargetRegisterClass *RC, 111 const TargetRegisterInfo *TRI, 112 Register VReg) const { 113 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) || 114 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && 115 "Unknown regclass!"); 116 117 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || 118 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { 119 DebugLoc DL; 120 if (I != MBB.end()) DL = I->getDebugLoc(); 121 122 MachineFunction &MF = *MBB.getParent(); 123 MachineFrameInfo &MFI = MF.getFrameInfo(); 124 MachineMemOperand *MMO = MF.getMachineMemOperand( 125 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad, 126 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 127 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 128 .addFrameIndex(FI) 129 .addImm(0) 130 .addMemOperand(MMO) 131 .add(predOps(ARMCC::AL)); 132 } 133 } 134 135 void Thumb1InstrInfo::expandLoadStackGuard( 136 MachineBasicBlock::iterator MI) const { 137 MachineFunction &MF = *MI->getParent()->getParent(); 138 const TargetMachine &TM = MF.getTarget(); 139 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); 140 141 assert(MF.getFunction().getParent()->getStackProtectorGuard() != "tls" && 142 "TLS stack protector not supported for Thumb1 targets"); 143 144 unsigned Instr; 145 if (TM.isPositionIndependent()) 146 Instr = ARM::tLDRLIT_ga_pcrel; 147 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps()) 148 Instr = ARM::t2MOVi32imm; 149 else if (ST.genExecuteOnly()) 150 Instr = ARM::tMOVi32imm; 151 else 152 Instr = ARM::tLDRLIT_ga_abs; 153 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi); 154 } 155 156 bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const { 157 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR 158 // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS 159 // even if they have glue. 160 // FIXME. Actually implement the cross-copy where it is possible (post v6) 161 // because these copies entail more spilling. 162 unsigned Opcode = N->getMachineOpcode(); 163 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS) 164 return true; 165 166 return false; 167 } 168