1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides ARM specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 15 16 #include "llvm/Support/DataTypes.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include <memory> 19 #include <string> 20 21 namespace llvm { 22 class formatted_raw_ostream; 23 class MCAsmBackend; 24 class MCCodeEmitter; 25 class MCContext; 26 class MCInstrInfo; 27 class MCInstPrinter; 28 class MCObjectTargetWriter; 29 class MCObjectWriter; 30 class MCRegisterInfo; 31 class MCSubtargetInfo; 32 class MCStreamer; 33 class MCTargetOptions; 34 class MCRelocationInfo; 35 class MCTargetStreamer; 36 class StringRef; 37 class Target; 38 class Triple; 39 40 namespace ARM_MC { 41 std::string ParseARMTriple(const Triple &TT, StringRef CPU); 42 void initLLVMToCVRegMapping(MCRegisterInfo *MRI); 43 44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII); 45 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII); 46 47 template<class Inst> 48 bool isLDMBaseRegInList(const Inst &MI) { 49 auto BaseReg = MI.getOperand(0).getReg(); 50 for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) { 51 const auto &Op = MI.getOperand(I); 52 if (Op.isReg() && Op.getReg() == BaseReg) 53 return true; 54 } 55 return false; 56 } 57 58 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, 59 int64_t Imm); 60 61 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. 62 /// do not need to go through TargetRegistry. 63 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, 64 StringRef FS); 65 } 66 67 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); 68 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, 69 formatted_raw_ostream &OS, 70 MCInstPrinter *InstPrint, 71 bool isVerboseAsm); 72 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, 73 const MCSubtargetInfo &STI); 74 MCTargetStreamer *createARMObjectTargetELFStreamer(MCStreamer &S); 75 MCTargetStreamer *createARMObjectTargetWinCOFFStreamer(MCStreamer &S); 76 77 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 78 MCContext &Ctx); 79 80 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 81 MCContext &Ctx); 82 83 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 84 const MCRegisterInfo &MRI, 85 const MCTargetOptions &Options); 86 87 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 88 const MCRegisterInfo &MRI, 89 const MCTargetOptions &Options); 90 91 // Construct a PE/COFF machine code streamer which will generate a PE/COFF 92 // object file. 93 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, 94 std::unique_ptr<MCAsmBackend> &&MAB, 95 std::unique_ptr<MCObjectWriter> &&OW, 96 std::unique_ptr<MCCodeEmitter> &&Emitter, 97 bool RelaxAll, 98 bool IncrementalLinkerCompatible); 99 100 /// Construct an ELF Mach-O object writer. 101 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI); 102 103 /// Construct an ARM Mach-O object writer. 104 std::unique_ptr<MCObjectTargetWriter> 105 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, 106 uint32_t CPUSubtype); 107 108 /// Construct an ARM PE/COFF object writer. 109 std::unique_ptr<MCObjectTargetWriter> 110 createARMWinCOFFObjectWriter(); 111 112 /// Construct ARM Mach-O relocation info. 113 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 114 115 namespace ARM { 116 enum OperandType { 117 OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET, 118 OPERAND_VPRED_N, 119 }; 120 inline bool isVpred(OperandType op) { 121 return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N; 122 } 123 inline bool isVpred(uint8_t op) { 124 return isVpred(static_cast<OperandType>(op)); 125 } 126 127 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI); 128 129 } // end namespace ARM 130 131 } // End llvm namespace 132 133 // Defines symbolic names for ARM registers. This defines a mapping from 134 // register name to register number. 135 // 136 #define GET_REGINFO_ENUM 137 #include "ARMGenRegisterInfo.inc" 138 139 // Defines symbolic names for the ARM instructions. 140 // 141 #define GET_INSTRINFO_ENUM 142 #define GET_INSTRINFO_MC_HELPER_DECLS 143 #include "ARMGenInstrInfo.inc" 144 145 #define GET_SUBTARGETINFO_ENUM 146 #include "ARMGenSubtargetInfo.inc" 147 148 #endif 149