1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides ARM specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 15 16 #include "llvm/Support/DataTypes.h" 17 #include "llvm/MC/MCInstrDesc.h" 18 #include <memory> 19 #include <string> 20 21 namespace llvm { 22 class formatted_raw_ostream; 23 class MCAsmBackend; 24 class MCCodeEmitter; 25 class MCContext; 26 class MCInstrInfo; 27 class MCInstPrinter; 28 class MCObjectTargetWriter; 29 class MCObjectWriter; 30 class MCRegisterInfo; 31 class MCSubtargetInfo; 32 class MCStreamer; 33 class MCTargetOptions; 34 class MCRelocationInfo; 35 class MCTargetStreamer; 36 class StringRef; 37 class Target; 38 class Triple; 39 40 namespace ARM_MC { 41 std::string ParseARMTriple(const Triple &TT, StringRef CPU); 42 void initLLVMToCVRegMapping(MCRegisterInfo *MRI); 43 44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII); 45 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII); 46 47 template<class Inst> 48 bool isLDMBaseRegInList(const Inst &MI) { 49 auto BaseReg = MI.getOperand(0).getReg(); 50 for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) { 51 const auto &Op = MI.getOperand(I); 52 if (Op.isReg() && Op.getReg() == BaseReg) 53 return true; 54 } 55 return false; 56 } 57 58 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, 59 int64_t Imm); 60 61 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. 62 /// do not need to go through TargetRegistry. 63 MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, 64 StringRef FS); 65 } 66 67 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); 68 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, 69 formatted_raw_ostream &OS, 70 MCInstPrinter *InstPrint); 71 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, 72 const MCSubtargetInfo &STI); 73 MCTargetStreamer *createARMObjectTargetELFStreamer(MCStreamer &S); 74 MCTargetStreamer *createARMObjectTargetWinCOFFStreamer(MCStreamer &S); 75 76 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 77 MCContext &Ctx); 78 79 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 80 MCContext &Ctx); 81 82 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 83 const MCRegisterInfo &MRI, 84 const MCTargetOptions &Options); 85 86 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 87 const MCRegisterInfo &MRI, 88 const MCTargetOptions &Options); 89 90 // Construct a PE/COFF machine code streamer which will generate a PE/COFF 91 // object file. 92 MCStreamer *createARMWinCOFFStreamer(MCContext &Context, 93 std::unique_ptr<MCAsmBackend> &&MAB, 94 std::unique_ptr<MCObjectWriter> &&OW, 95 std::unique_ptr<MCCodeEmitter> &&Emitter); 96 97 /// Construct an ELF Mach-O object writer. 98 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI); 99 100 /// Construct an ARM Mach-O object writer. 101 std::unique_ptr<MCObjectTargetWriter> 102 createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, 103 uint32_t CPUSubtype); 104 105 /// Construct an ARM PE/COFF object writer. 106 std::unique_ptr<MCObjectTargetWriter> 107 createARMWinCOFFObjectWriter(); 108 109 /// Construct ARM Mach-O relocation info. 110 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 111 112 namespace ARM { 113 enum OperandType { 114 OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET, 115 OPERAND_VPRED_N, 116 }; 117 inline bool isVpred(OperandType op) { 118 return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N; 119 } 120 inline bool isVpred(uint8_t op) { 121 return isVpred(static_cast<OperandType>(op)); 122 } 123 124 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI); 125 126 } // end namespace ARM 127 128 } // End llvm namespace 129 130 // Defines symbolic names for ARM registers. This defines a mapping from 131 // register name to register number. 132 // 133 #define GET_REGINFO_ENUM 134 #include "ARMGenRegisterInfo.inc" 135 136 // Defines symbolic names for the ARM instructions. 137 // 138 #define GET_INSTRINFO_ENUM 139 #define GET_INSTRINFO_MC_HELPER_DECLS 140 #include "ARMGenInstrInfo.inc" 141 142 #define GET_SUBTARGETINFO_ENUM 143 #include "ARMGenSubtargetInfo.inc" 144 145 #endif 146