1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides ARM specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARMMCTargetDesc.h" 14 #include "ARMAddressingModes.h" 15 #include "ARMBaseInfo.h" 16 #include "ARMInstPrinter.h" 17 #include "ARMMCAsmInfo.h" 18 #include "TargetInfo/ARMTargetInfo.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/DebugInfo/CodeView/CodeView.h" 21 #include "llvm/MC/MCAsmBackend.h" 22 #include "llvm/MC/MCCodeEmitter.h" 23 #include "llvm/MC/MCELFStreamer.h" 24 #include "llvm/MC/MCInstrAnalysis.h" 25 #include "llvm/MC/MCInstrInfo.h" 26 #include "llvm/MC/MCObjectWriter.h" 27 #include "llvm/MC/MCRegisterInfo.h" 28 #include "llvm/MC/MCStreamer.h" 29 #include "llvm/MC/MCSubtargetInfo.h" 30 #include "llvm/MC/TargetRegistry.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/TargetParser.h" 33 34 using namespace llvm; 35 36 #define GET_REGINFO_MC_DESC 37 #include "ARMGenRegisterInfo.inc" 38 39 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 40 std::string &Info) { 41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && 42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && 43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && 44 // Checks for the deprecated CP15ISB encoding: 45 // mcr p15, #0, rX, c7, c5, #4 46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { 47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { 48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { 49 Info = "deprecated since v7, use 'isb'"; 50 return true; 51 } 52 53 // Checks for the deprecated CP15DSB encoding: 54 // mcr p15, #0, rX, c7, c10, #4 55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { 56 Info = "deprecated since v7, use 'dsb'"; 57 return true; 58 } 59 } 60 // Checks for the deprecated CP15DMB encoding: 61 // mcr p15, #0, rX, c7, c10, #5 62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && 63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { 64 Info = "deprecated since v7, use 'dmb'"; 65 return true; 66 } 67 } 68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && 69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || 70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { 71 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " 72 "point instructions"; 73 return true; 74 } 75 return false; 76 } 77 78 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 79 std::string &Info) { 80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && 81 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || 82 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { 83 Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating " 84 "point instructions"; 85 return true; 86 } 87 return false; 88 } 89 90 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 91 std::string &Info) { 92 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 93 "cannot predicate thumb instructions"); 94 95 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 96 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 97 assert(MI.getOperand(OI).isReg() && "expected register"); 98 if (MI.getOperand(OI).getReg() == ARM::PC) { 99 Info = "use of PC in the list is deprecated"; 100 return true; 101 } 102 } 103 return false; 104 } 105 106 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, 107 std::string &Info) { 108 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && 109 "cannot predicate thumb instructions"); 110 111 assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments"); 112 bool ListContainsPC = false, ListContainsLR = false; 113 for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) { 114 assert(MI.getOperand(OI).isReg() && "expected register"); 115 switch (MI.getOperand(OI).getReg()) { 116 default: 117 break; 118 case ARM::LR: 119 ListContainsLR = true; 120 break; 121 case ARM::PC: 122 ListContainsPC = true; 123 break; 124 } 125 } 126 127 if (ListContainsPC && ListContainsLR) { 128 Info = "use of LR and PC simultaneously in the list is deprecated"; 129 return true; 130 } 131 132 return false; 133 } 134 135 #define GET_INSTRINFO_MC_DESC 136 #define ENABLE_INSTR_PREDICATE_VERIFIER 137 #include "ARMGenInstrInfo.inc" 138 139 #define GET_SUBTARGETINFO_MC_DESC 140 #include "ARMGenSubtargetInfo.inc" 141 142 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { 143 std::string ARMArchFeature; 144 145 ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); 146 if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) 147 ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str(); 148 149 if (TT.isThumb()) { 150 if (!ARMArchFeature.empty()) 151 ARMArchFeature += ","; 152 ARMArchFeature += "+thumb-mode,+v4t"; 153 } 154 155 if (TT.isOSNaCl()) { 156 if (!ARMArchFeature.empty()) 157 ARMArchFeature += ","; 158 ARMArchFeature += "+nacl-trap"; 159 } 160 161 if (TT.isOSWindows()) { 162 if (!ARMArchFeature.empty()) 163 ARMArchFeature += ","; 164 ARMArchFeature += "+noarm"; 165 } 166 167 return ARMArchFeature; 168 } 169 170 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) { 171 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 172 int PredOpIdx = Desc.findFirstPredOperandIdx(); 173 return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL; 174 } 175 176 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) { 177 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 178 for (unsigned I = 0; I < MI.getNumOperands(); ++I) { 179 const MCOperand &MO = MI.getOperand(I); 180 if (MO.isReg() && MO.getReg() == ARM::CPSR && 181 Desc.operands()[I].isOptionalDef()) 182 return true; 183 } 184 return false; 185 } 186 187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, 188 uint64_t Addr, int64_t Imm) { 189 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it 190 // is 4 bytes. 191 uint64_t Offset = 192 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; 193 194 // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code 195 // which is 32-bit aligned. The target address for the case is calculated as 196 // targetAddress = Align(PC,4) + imm32; 197 // where 198 // Align(x, y) = y * (x DIV y); 199 if (InstDesc.getOpcode() == ARM::tBLXi) 200 Addr &= ~0x3; 201 202 return Addr + Imm + Offset; 203 } 204 205 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, 206 StringRef CPU, StringRef FS) { 207 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); 208 if (!FS.empty()) { 209 if (!ArchFS.empty()) 210 ArchFS = (Twine(ArchFS) + "," + FS).str(); 211 else 212 ArchFS = std::string(FS); 213 } 214 215 return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); 216 } 217 218 static MCInstrInfo *createARMMCInstrInfo() { 219 MCInstrInfo *X = new MCInstrInfo(); 220 InitARMMCInstrInfo(X); 221 return X; 222 } 223 224 void ARM_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 225 // Mapping from CodeView to MC register id. 226 static const struct { 227 codeview::RegisterId CVReg; 228 MCPhysReg Reg; 229 } RegMap[] = { 230 {codeview::RegisterId::ARM_R0, ARM::R0}, 231 {codeview::RegisterId::ARM_R1, ARM::R1}, 232 {codeview::RegisterId::ARM_R2, ARM::R2}, 233 {codeview::RegisterId::ARM_R3, ARM::R3}, 234 {codeview::RegisterId::ARM_R4, ARM::R4}, 235 {codeview::RegisterId::ARM_R5, ARM::R5}, 236 {codeview::RegisterId::ARM_R6, ARM::R6}, 237 {codeview::RegisterId::ARM_R7, ARM::R7}, 238 {codeview::RegisterId::ARM_R8, ARM::R8}, 239 {codeview::RegisterId::ARM_R9, ARM::R9}, 240 {codeview::RegisterId::ARM_R10, ARM::R10}, 241 {codeview::RegisterId::ARM_R11, ARM::R11}, 242 {codeview::RegisterId::ARM_R12, ARM::R12}, 243 {codeview::RegisterId::ARM_SP, ARM::SP}, 244 {codeview::RegisterId::ARM_LR, ARM::LR}, 245 {codeview::RegisterId::ARM_PC, ARM::PC}, 246 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, 247 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR}, 248 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC}, 249 {codeview::RegisterId::ARM_FS0, ARM::S0}, 250 {codeview::RegisterId::ARM_FS1, ARM::S1}, 251 {codeview::RegisterId::ARM_FS2, ARM::S2}, 252 {codeview::RegisterId::ARM_FS3, ARM::S3}, 253 {codeview::RegisterId::ARM_FS4, ARM::S4}, 254 {codeview::RegisterId::ARM_FS5, ARM::S5}, 255 {codeview::RegisterId::ARM_FS6, ARM::S6}, 256 {codeview::RegisterId::ARM_FS7, ARM::S7}, 257 {codeview::RegisterId::ARM_FS8, ARM::S8}, 258 {codeview::RegisterId::ARM_FS9, ARM::S9}, 259 {codeview::RegisterId::ARM_FS10, ARM::S10}, 260 {codeview::RegisterId::ARM_FS11, ARM::S11}, 261 {codeview::RegisterId::ARM_FS12, ARM::S12}, 262 {codeview::RegisterId::ARM_FS13, ARM::S13}, 263 {codeview::RegisterId::ARM_FS14, ARM::S14}, 264 {codeview::RegisterId::ARM_FS15, ARM::S15}, 265 {codeview::RegisterId::ARM_FS16, ARM::S16}, 266 {codeview::RegisterId::ARM_FS17, ARM::S17}, 267 {codeview::RegisterId::ARM_FS18, ARM::S18}, 268 {codeview::RegisterId::ARM_FS19, ARM::S19}, 269 {codeview::RegisterId::ARM_FS20, ARM::S20}, 270 {codeview::RegisterId::ARM_FS21, ARM::S21}, 271 {codeview::RegisterId::ARM_FS22, ARM::S22}, 272 {codeview::RegisterId::ARM_FS23, ARM::S23}, 273 {codeview::RegisterId::ARM_FS24, ARM::S24}, 274 {codeview::RegisterId::ARM_FS25, ARM::S25}, 275 {codeview::RegisterId::ARM_FS26, ARM::S26}, 276 {codeview::RegisterId::ARM_FS27, ARM::S27}, 277 {codeview::RegisterId::ARM_FS28, ARM::S28}, 278 {codeview::RegisterId::ARM_FS29, ARM::S29}, 279 {codeview::RegisterId::ARM_FS30, ARM::S30}, 280 {codeview::RegisterId::ARM_FS31, ARM::S31}, 281 {codeview::RegisterId::ARM_ND0, ARM::D0}, 282 {codeview::RegisterId::ARM_ND1, ARM::D1}, 283 {codeview::RegisterId::ARM_ND2, ARM::D2}, 284 {codeview::RegisterId::ARM_ND3, ARM::D3}, 285 {codeview::RegisterId::ARM_ND4, ARM::D4}, 286 {codeview::RegisterId::ARM_ND5, ARM::D5}, 287 {codeview::RegisterId::ARM_ND6, ARM::D6}, 288 {codeview::RegisterId::ARM_ND7, ARM::D7}, 289 {codeview::RegisterId::ARM_ND8, ARM::D8}, 290 {codeview::RegisterId::ARM_ND9, ARM::D9}, 291 {codeview::RegisterId::ARM_ND10, ARM::D10}, 292 {codeview::RegisterId::ARM_ND11, ARM::D11}, 293 {codeview::RegisterId::ARM_ND12, ARM::D12}, 294 {codeview::RegisterId::ARM_ND13, ARM::D13}, 295 {codeview::RegisterId::ARM_ND14, ARM::D14}, 296 {codeview::RegisterId::ARM_ND15, ARM::D15}, 297 {codeview::RegisterId::ARM_ND16, ARM::D16}, 298 {codeview::RegisterId::ARM_ND17, ARM::D17}, 299 {codeview::RegisterId::ARM_ND18, ARM::D18}, 300 {codeview::RegisterId::ARM_ND19, ARM::D19}, 301 {codeview::RegisterId::ARM_ND20, ARM::D20}, 302 {codeview::RegisterId::ARM_ND21, ARM::D21}, 303 {codeview::RegisterId::ARM_ND22, ARM::D22}, 304 {codeview::RegisterId::ARM_ND23, ARM::D23}, 305 {codeview::RegisterId::ARM_ND24, ARM::D24}, 306 {codeview::RegisterId::ARM_ND25, ARM::D25}, 307 {codeview::RegisterId::ARM_ND26, ARM::D26}, 308 {codeview::RegisterId::ARM_ND27, ARM::D27}, 309 {codeview::RegisterId::ARM_ND28, ARM::D28}, 310 {codeview::RegisterId::ARM_ND29, ARM::D29}, 311 {codeview::RegisterId::ARM_ND30, ARM::D30}, 312 {codeview::RegisterId::ARM_ND31, ARM::D31}, 313 {codeview::RegisterId::ARM_NQ0, ARM::Q0}, 314 {codeview::RegisterId::ARM_NQ1, ARM::Q1}, 315 {codeview::RegisterId::ARM_NQ2, ARM::Q2}, 316 {codeview::RegisterId::ARM_NQ3, ARM::Q3}, 317 {codeview::RegisterId::ARM_NQ4, ARM::Q4}, 318 {codeview::RegisterId::ARM_NQ5, ARM::Q5}, 319 {codeview::RegisterId::ARM_NQ6, ARM::Q6}, 320 {codeview::RegisterId::ARM_NQ7, ARM::Q7}, 321 {codeview::RegisterId::ARM_NQ8, ARM::Q8}, 322 {codeview::RegisterId::ARM_NQ9, ARM::Q9}, 323 {codeview::RegisterId::ARM_NQ10, ARM::Q10}, 324 {codeview::RegisterId::ARM_NQ11, ARM::Q11}, 325 {codeview::RegisterId::ARM_NQ12, ARM::Q12}, 326 {codeview::RegisterId::ARM_NQ13, ARM::Q13}, 327 {codeview::RegisterId::ARM_NQ14, ARM::Q14}, 328 {codeview::RegisterId::ARM_NQ15, ARM::Q15}, 329 }; 330 for (const auto &I : RegMap) 331 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 332 } 333 334 static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { 335 MCRegisterInfo *X = new MCRegisterInfo(); 336 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); 337 ARM_MC::initLLVMToCVRegMapping(X); 338 return X; 339 } 340 341 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, 342 const Triple &TheTriple, 343 const MCTargetOptions &Options) { 344 MCAsmInfo *MAI; 345 if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) 346 MAI = new ARMMCAsmInfoDarwin(TheTriple); 347 else if (TheTriple.isWindowsMSVCEnvironment()) 348 MAI = new ARMCOFFMCAsmInfoMicrosoft(); 349 else if (TheTriple.isOSWindows()) 350 MAI = new ARMCOFFMCAsmInfoGNU(); 351 else 352 MAI = new ARMELFMCAsmInfo(TheTriple); 353 354 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); 355 MAI->addInitialFrameState(MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0)); 356 357 return MAI; 358 } 359 360 static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, 361 std::unique_ptr<MCAsmBackend> &&MAB, 362 std::unique_ptr<MCObjectWriter> &&OW, 363 std::unique_ptr<MCCodeEmitter> &&Emitter, 364 bool RelaxAll) { 365 return createARMELFStreamer( 366 Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false, 367 (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb), 368 T.isAndroid()); 369 } 370 371 static MCStreamer * 372 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB, 373 std::unique_ptr<MCObjectWriter> &&OW, 374 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, 375 bool DWARFMustBeAtTheEnd) { 376 return createMachOStreamer(Ctx, std::move(MAB), std::move(OW), 377 std::move(Emitter), false, DWARFMustBeAtTheEnd); 378 } 379 380 static MCInstPrinter *createARMMCInstPrinter(const Triple &T, 381 unsigned SyntaxVariant, 382 const MCAsmInfo &MAI, 383 const MCInstrInfo &MII, 384 const MCRegisterInfo &MRI) { 385 if (SyntaxVariant == 0) 386 return new ARMInstPrinter(MAI, MII, MRI); 387 return nullptr; 388 } 389 390 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, 391 MCContext &Ctx) { 392 if (TT.isOSBinFormatMachO()) 393 return createARMMachORelocationInfo(Ctx); 394 // Default to the stock relocation info. 395 return llvm::createMCRelocationInfo(TT, Ctx); 396 } 397 398 namespace { 399 400 class ARMMCInstrAnalysis : public MCInstrAnalysis { 401 public: 402 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 403 404 bool isUnconditionalBranch(const MCInst &Inst) const override { 405 // BCCs with the "always" predicate are unconditional branches. 406 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 407 return true; 408 return MCInstrAnalysis::isUnconditionalBranch(Inst); 409 } 410 411 bool isConditionalBranch(const MCInst &Inst) const override { 412 // BCCs with the "always" predicate are unconditional branches. 413 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 414 return false; 415 return MCInstrAnalysis::isConditionalBranch(Inst); 416 } 417 418 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 419 uint64_t &Target) const override { 420 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 421 422 // Find the PC-relative immediate operand in the instruction. 423 for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) { 424 if (Inst.getOperand(OpNum).isImm() && 425 Desc.operands()[OpNum].OperandType == MCOI::OPERAND_PCREL) { 426 int64_t Imm = Inst.getOperand(OpNum).getImm(); 427 Target = ARM_MC::evaluateBranchTarget(Desc, Addr, Imm); 428 return true; 429 } 430 } 431 return false; 432 } 433 434 std::optional<uint64_t> 435 evaluateMemoryOperandAddress(const MCInst &Inst, const MCSubtargetInfo *STI, 436 uint64_t Addr, uint64_t Size) const override; 437 }; 438 439 } // namespace 440 441 static std::optional<uint64_t> 442 // NOLINTNEXTLINE(readability-identifier-naming) 443 evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, 444 unsigned MemOpIndex, uint64_t Addr) { 445 if (MemOpIndex + 1 >= Desc.getNumOperands()) 446 return std::nullopt; 447 448 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 449 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 450 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 451 return std::nullopt; 452 453 int32_t OffImm = (int32_t)MO2.getImm(); 454 // Special value for #-0. All others are normal. 455 if (OffImm == INT32_MIN) 456 OffImm = 0; 457 return Addr + OffImm; 458 } 459 460 static std::optional<uint64_t> 461 evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, 462 unsigned MemOpIndex, uint64_t Addr) { 463 if (MemOpIndex + 2 >= Desc.getNumOperands()) 464 return std::nullopt; 465 466 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 467 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 468 const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2); 469 if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm()) 470 return std::nullopt; 471 472 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()); 473 ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm()); 474 475 if (Op == ARM_AM::sub) 476 return Addr - ImmOffs; 477 return Addr + ImmOffs; 478 } 479 480 static std::optional<uint64_t> 481 evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, 482 unsigned MemOpIndex, uint64_t Addr) { 483 if (MemOpIndex + 1 >= Desc.getNumOperands()) 484 return std::nullopt; 485 486 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 487 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 488 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 489 return std::nullopt; 490 491 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); 492 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); 493 494 if (Op == ARM_AM::sub) 495 return Addr - ImmOffs * 4; 496 return Addr + ImmOffs * 4; 497 } 498 499 static std::optional<uint64_t> 500 evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, 501 unsigned MemOpIndex, uint64_t Addr) { 502 if (MemOpIndex + 1 >= Desc.getNumOperands()) 503 return std::nullopt; 504 505 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 506 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 507 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 508 return std::nullopt; 509 510 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm()); 511 ARM_AM::AddrOpc Op = ARM_AM::getAM5FP16Op(MO2.getImm()); 512 513 if (Op == ARM_AM::sub) 514 return Addr - ImmOffs * 2; 515 return Addr + ImmOffs * 2; 516 } 517 518 static std::optional<uint64_t> 519 // NOLINTNEXTLINE(readability-identifier-naming) 520 evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, 521 unsigned MemOpIndex, uint64_t Addr) { 522 if (MemOpIndex + 1 >= Desc.getNumOperands()) 523 return std::nullopt; 524 525 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 526 const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1); 527 if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm()) 528 return std::nullopt; 529 530 int32_t OffImm = (int32_t)MO2.getImm(); 531 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!"); 532 533 // Special value for #-0. All others are normal. 534 if (OffImm == INT32_MIN) 535 OffImm = 0; 536 return Addr + OffImm; 537 } 538 539 static std::optional<uint64_t> 540 // NOLINTNEXTLINE(readability-identifier-naming) 541 evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, 542 unsigned MemOpIndex, uint64_t Addr) { 543 const MCOperand &MO1 = Inst.getOperand(MemOpIndex); 544 if (!MO1.isImm()) 545 return std::nullopt; 546 547 int32_t OffImm = (int32_t)MO1.getImm(); 548 549 // Special value for #-0. All others are normal. 550 if (OffImm == INT32_MIN) 551 OffImm = 0; 552 return Addr + OffImm; 553 } 554 555 static std::optional<uint64_t> 556 // NOLINTNEXTLINE(readability-identifier-naming) 557 evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, 558 unsigned MemOpIndex, uint64_t Addr) { 559 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr); 560 } 561 562 std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress( 563 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, 564 uint64_t Size) const { 565 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 566 567 // Only load instructions can have PC-relative memory addressing. 568 if (!Desc.mayLoad()) 569 return std::nullopt; 570 571 // PC-relative addressing does not update the base register. 572 uint64_t TSFlags = Desc.TSFlags; 573 unsigned IndexMode = 574 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; 575 if (IndexMode != ARMII::IndexModeNone) 576 return std::nullopt; 577 578 // Find the memory addressing operand in the instruction. 579 unsigned OpIndex = Desc.NumDefs; 580 while (OpIndex < Desc.getNumOperands() && 581 Desc.operands()[OpIndex].OperandType != MCOI::OPERAND_MEMORY) 582 ++OpIndex; 583 if (OpIndex == Desc.getNumOperands()) 584 return std::nullopt; 585 586 // Base address for PC-relative addressing is always 32-bit aligned. 587 Addr &= ~0x3; 588 589 // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it 590 // is 4 bytes. 591 switch (Desc.TSFlags & ARMII::FormMask) { 592 default: 593 Addr += 8; 594 break; 595 case ARMII::ThumbFrm: 596 Addr += 4; 597 break; 598 // VLDR* instructions share the same opcode (and thus the same form) for Arm 599 // and Thumb. Use a bit longer route through STI in that case. 600 case ARMII::VFPLdStFrm: 601 Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8; 602 break; 603 } 604 605 // Eveluate the address depending on the addressing mode 606 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); 607 switch (AddrMode) { 608 default: 609 return std::nullopt; 610 case ARMII::AddrMode_i12: 611 return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr); 612 case ARMII::AddrMode3: 613 return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr); 614 case ARMII::AddrMode5: 615 return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr); 616 case ARMII::AddrMode5FP16: 617 return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr); 618 case ARMII::AddrModeT2_i8s4: 619 return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr); 620 case ARMII::AddrModeT2_pc: 621 return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr); 622 case ARMII::AddrModeT1_s: 623 return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr); 624 } 625 } 626 627 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { 628 return new ARMMCInstrAnalysis(Info); 629 } 630 631 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) { 632 // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have 633 // to rely on feature bits. 634 if (Coproc >= 8) 635 return false; 636 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; 637 } 638 639 // Force static initialization. 640 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC() { 641 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), 642 &getTheThumbLETarget(), &getTheThumbBETarget()}) { 643 // Register the MC asm info. 644 RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); 645 646 // Register the MC instruction info. 647 TargetRegistry::RegisterMCInstrInfo(*T, createARMMCInstrInfo); 648 649 // Register the MC register info. 650 TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo); 651 652 // Register the MC subtarget info. 653 TargetRegistry::RegisterMCSubtargetInfo(*T, 654 ARM_MC::createARMMCSubtargetInfo); 655 656 TargetRegistry::RegisterELFStreamer(*T, createELFStreamer); 657 TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer); 658 TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer); 659 660 // Register the obj target streamer. 661 TargetRegistry::RegisterObjectTargetStreamer(*T, 662 createARMObjectTargetStreamer); 663 664 // Register the asm streamer. 665 TargetRegistry::RegisterAsmTargetStreamer(*T, createARMTargetAsmStreamer); 666 667 // Register the null TargetStreamer. 668 TargetRegistry::RegisterNullTargetStreamer(*T, createARMNullTargetStreamer); 669 670 // Register the MCInstPrinter. 671 TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter); 672 673 // Register the MC relocation info. 674 TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo); 675 } 676 677 // Register the MC instruction analyzer. 678 for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(), 679 &getTheThumbLETarget(), &getTheThumbBETarget()}) 680 TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis); 681 682 for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) { 683 TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter); 684 TargetRegistry::RegisterMCAsmBackend(*T, createARMLEAsmBackend); 685 } 686 for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) { 687 TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter); 688 TargetRegistry::RegisterMCAsmBackend(*T, createARMBEAsmBackend); 689 } 690 } 691