1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the ARM target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H 17 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H 18 19 #include "ARMMCTargetDesc.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "Utils/ARMBaseInfo.h" 22 23 namespace llvm { 24 25 namespace ARM_PROC { 26 enum IMod { 27 IE = 2, 28 ID = 3 29 }; 30 31 enum IFlags { 32 F = 1, 33 I = 2, 34 A = 4 35 }; 36 37 inline static const char *IFlagsToString(unsigned val) { 38 switch (val) { 39 default: llvm_unreachable("Unknown iflags operand"); 40 case F: return "f"; 41 case I: return "i"; 42 case A: return "a"; 43 } 44 } 45 46 inline static const char *IModToString(unsigned val) { 47 switch (val) { 48 default: llvm_unreachable("Unknown imod operand"); 49 case IE: return "ie"; 50 case ID: return "id"; 51 } 52 } 53 } 54 55 namespace ARM_MB { 56 // The Memory Barrier Option constants map directly to the 4-bit encoding of 57 // the option field for memory barrier operations. 58 enum MemBOpt { 59 RESERVED_0 = 0, 60 OSHLD = 1, 61 OSHST = 2, 62 OSH = 3, 63 RESERVED_4 = 4, 64 NSHLD = 5, 65 NSHST = 6, 66 NSH = 7, 67 RESERVED_8 = 8, 68 ISHLD = 9, 69 ISHST = 10, 70 ISH = 11, 71 RESERVED_12 = 12, 72 LD = 13, 73 ST = 14, 74 SY = 15 75 }; 76 77 inline static const char *MemBOptToString(unsigned val, bool HasV8) { 78 switch (val) { 79 default: llvm_unreachable("Unknown memory operation"); 80 case SY: return "sy"; 81 case ST: return "st"; 82 case LD: return HasV8 ? "ld" : "#0xd"; 83 case RESERVED_12: return "#0xc"; 84 case ISH: return "ish"; 85 case ISHST: return "ishst"; 86 case ISHLD: return HasV8 ? "ishld" : "#0x9"; 87 case RESERVED_8: return "#0x8"; 88 case NSH: return "nsh"; 89 case NSHST: return "nshst"; 90 case NSHLD: return HasV8 ? "nshld" : "#0x5"; 91 case RESERVED_4: return "#0x4"; 92 case OSH: return "osh"; 93 case OSHST: return "oshst"; 94 case OSHLD: return HasV8 ? "oshld" : "#0x1"; 95 case RESERVED_0: return "#0x0"; 96 } 97 } 98 } // namespace ARM_MB 99 100 namespace ARM_TSB { 101 enum TraceSyncBOpt { 102 CSYNC = 0 103 }; 104 105 inline static const char *TraceSyncBOptToString(unsigned val) { 106 switch (val) { 107 default: 108 llvm_unreachable("Unknown trace synchronization barrier operation"); 109 case CSYNC: return "csync"; 110 } 111 } 112 } // namespace ARM_TSB 113 114 namespace ARM_ISB { 115 enum InstSyncBOpt { 116 RESERVED_0 = 0, 117 RESERVED_1 = 1, 118 RESERVED_2 = 2, 119 RESERVED_3 = 3, 120 RESERVED_4 = 4, 121 RESERVED_5 = 5, 122 RESERVED_6 = 6, 123 RESERVED_7 = 7, 124 RESERVED_8 = 8, 125 RESERVED_9 = 9, 126 RESERVED_10 = 10, 127 RESERVED_11 = 11, 128 RESERVED_12 = 12, 129 RESERVED_13 = 13, 130 RESERVED_14 = 14, 131 SY = 15 132 }; 133 134 inline static const char *InstSyncBOptToString(unsigned val) { 135 switch (val) { 136 default: 137 llvm_unreachable("Unknown memory operation"); 138 case RESERVED_0: return "#0x0"; 139 case RESERVED_1: return "#0x1"; 140 case RESERVED_2: return "#0x2"; 141 case RESERVED_3: return "#0x3"; 142 case RESERVED_4: return "#0x4"; 143 case RESERVED_5: return "#0x5"; 144 case RESERVED_6: return "#0x6"; 145 case RESERVED_7: return "#0x7"; 146 case RESERVED_8: return "#0x8"; 147 case RESERVED_9: return "#0x9"; 148 case RESERVED_10: return "#0xa"; 149 case RESERVED_11: return "#0xb"; 150 case RESERVED_12: return "#0xc"; 151 case RESERVED_13: return "#0xd"; 152 case RESERVED_14: return "#0xe"; 153 case SY: return "sy"; 154 } 155 } 156 } // namespace ARM_ISB 157 158 /// isARMLowRegister - Returns true if the register is a low register (r0-r7). 159 /// 160 static inline bool isARMLowRegister(unsigned Reg) { 161 using namespace ARM; 162 switch (Reg) { 163 case R0: case R1: case R2: case R3: 164 case R4: case R5: case R6: case R7: 165 return true; 166 default: 167 return false; 168 } 169 } 170 171 /// ARMII - This namespace holds all of the target specific flags that 172 /// instruction info tracks. 173 /// 174 namespace ARMII { 175 176 /// ARM Index Modes 177 enum IndexMode { 178 IndexModeNone = 0, 179 IndexModePre = 1, 180 IndexModePost = 2, 181 IndexModeUpd = 3 182 }; 183 184 /// ARM Addressing Modes 185 enum AddrMode { 186 AddrModeNone = 0, 187 AddrMode1 = 1, 188 AddrMode2 = 2, 189 AddrMode3 = 3, 190 AddrMode4 = 4, 191 AddrMode5 = 5, 192 AddrMode6 = 6, 193 AddrModeT1_1 = 7, 194 AddrModeT1_2 = 8, 195 AddrModeT1_4 = 9, 196 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data 197 AddrModeT2_i12 = 11, 198 AddrModeT2_i8 = 12, // +/- i8 199 AddrModeT2_i8pos = 13, // + i8 200 AddrModeT2_i8neg = 14, // - i8 201 AddrModeT2_so = 15, 202 AddrModeT2_pc = 16, // +/- i12 for pc relative data 203 AddrModeT2_i8s4 = 17, // i8 * 4 204 AddrMode_i12 = 18, 205 AddrMode5FP16 = 19, // i8 * 2 206 AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst 207 AddrModeT2_i7s4 = 21, // i7 * 4 208 AddrModeT2_i7s2 = 22, // i7 * 2 209 AddrModeT2_i7 = 23, // i7 * 1 210 }; 211 212 inline static const char *AddrModeToString(AddrMode addrmode) { 213 switch (addrmode) { 214 case AddrModeNone: return "AddrModeNone"; 215 case AddrMode1: return "AddrMode1"; 216 case AddrMode2: return "AddrMode2"; 217 case AddrMode3: return "AddrMode3"; 218 case AddrMode4: return "AddrMode4"; 219 case AddrMode5: return "AddrMode5"; 220 case AddrMode5FP16: return "AddrMode5FP16"; 221 case AddrMode6: return "AddrMode6"; 222 case AddrModeT1_1: return "AddrModeT1_1"; 223 case AddrModeT1_2: return "AddrModeT1_2"; 224 case AddrModeT1_4: return "AddrModeT1_4"; 225 case AddrModeT1_s: return "AddrModeT1_s"; 226 case AddrModeT2_i12: return "AddrModeT2_i12"; 227 case AddrModeT2_i8: return "AddrModeT2_i8"; 228 case AddrModeT2_i8pos: return "AddrModeT2_i8pos"; 229 case AddrModeT2_i8neg: return "AddrModeT2_i8neg"; 230 case AddrModeT2_so: return "AddrModeT2_so"; 231 case AddrModeT2_pc: return "AddrModeT2_pc"; 232 case AddrModeT2_i8s4: return "AddrModeT2_i8s4"; 233 case AddrMode_i12: return "AddrMode_i12"; 234 case AddrModeT2_ldrex:return "AddrModeT2_ldrex"; 235 case AddrModeT2_i7s4: return "AddrModeT2_i7s4"; 236 case AddrModeT2_i7s2: return "AddrModeT2_i7s2"; 237 case AddrModeT2_i7: return "AddrModeT2_i7"; 238 } 239 } 240 241 /// Target Operand Flag enum. 242 enum TOF { 243 //===------------------------------------------------------------------===// 244 // ARM Specific MachineOperand flags. 245 246 MO_NO_FLAG = 0, 247 248 /// MO_LO16 - On a symbol operand, this represents a relocation containing 249 /// lower 16 bit of the address. Used only via movw instruction. 250 MO_LO16 = 0x1, 251 252 /// MO_HI16 - On a symbol operand, this represents a relocation containing 253 /// higher 16 bit of the address. Used only via movt instruction. 254 MO_HI16 = 0x2, 255 256 /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects 257 /// just that part of the flag set. 258 MO_OPTION_MASK = 0x3, 259 260 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 261 /// reference is actually to the ".refptr.FOO" symbol. This is used for 262 /// stub symbols on windows. 263 MO_COFFSTUB = 0x4, 264 265 /// MO_GOT - On a symbol operand, this represents a GOT relative relocation. 266 MO_GOT = 0x8, 267 268 /// MO_SBREL - On a symbol operand, this represents a static base relative 269 /// relocation. Used in movw and movt instructions. 270 MO_SBREL = 0x10, 271 272 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference 273 /// to the symbol is for an import stub. This is used for DLL import 274 /// storage class indication on Windows. 275 MO_DLLIMPORT = 0x20, 276 277 /// MO_SECREL - On a symbol operand this indicates that the immediate is 278 /// the offset from beginning of section. 279 /// 280 /// This is the TLS offset for the COFF/Windows TLS mechanism. 281 MO_SECREL = 0x40, 282 283 /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it 284 /// represents a symbol which, if indirect, will get special Darwin mangling 285 /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be 286 /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for 287 /// example). 288 MO_NONLAZY = 0x80, 289 290 // It's undefined behaviour if an enum overflows the range between its 291 // smallest and largest values, but since these are |ed together, it can 292 // happen. Put a sentinel in (values of this enum are stored as "unsigned 293 // char"). 294 MO_UNUSED_MAXIMUM = 0xff 295 }; 296 297 enum { 298 //===------------------------------------------------------------------===// 299 // Instruction Flags. 300 301 //===------------------------------------------------------------------===// 302 // This four-bit field describes the addressing mode used. 303 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h 304 305 // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load 306 // and store ops only. Generic "updating" flag is used for ld/st multiple. 307 // The index mode enums are declared in ARMBaseInfo.h 308 IndexModeShift = 5, 309 IndexModeMask = 3 << IndexModeShift, 310 311 //===------------------------------------------------------------------===// 312 // Instruction encoding formats. 313 // 314 FormShift = 7, 315 FormMask = 0x3f << FormShift, 316 317 // Pseudo instructions 318 Pseudo = 0 << FormShift, 319 320 // Multiply instructions 321 MulFrm = 1 << FormShift, 322 323 // Branch instructions 324 BrFrm = 2 << FormShift, 325 BrMiscFrm = 3 << FormShift, 326 327 // Data Processing instructions 328 DPFrm = 4 << FormShift, 329 DPSoRegFrm = 5 << FormShift, 330 331 // Load and Store 332 LdFrm = 6 << FormShift, 333 StFrm = 7 << FormShift, 334 LdMiscFrm = 8 << FormShift, 335 StMiscFrm = 9 << FormShift, 336 LdStMulFrm = 10 << FormShift, 337 338 LdStExFrm = 11 << FormShift, 339 340 // Miscellaneous arithmetic instructions 341 ArithMiscFrm = 12 << FormShift, 342 SatFrm = 13 << FormShift, 343 344 // Extend instructions 345 ExtFrm = 14 << FormShift, 346 347 // VFP formats 348 VFPUnaryFrm = 15 << FormShift, 349 VFPBinaryFrm = 16 << FormShift, 350 VFPConv1Frm = 17 << FormShift, 351 VFPConv2Frm = 18 << FormShift, 352 VFPConv3Frm = 19 << FormShift, 353 VFPConv4Frm = 20 << FormShift, 354 VFPConv5Frm = 21 << FormShift, 355 VFPLdStFrm = 22 << FormShift, 356 VFPLdStMulFrm = 23 << FormShift, 357 VFPMiscFrm = 24 << FormShift, 358 359 // Thumb format 360 ThumbFrm = 25 << FormShift, 361 362 // Miscelleaneous format 363 MiscFrm = 26 << FormShift, 364 365 // NEON formats 366 NGetLnFrm = 27 << FormShift, 367 NSetLnFrm = 28 << FormShift, 368 NDupFrm = 29 << FormShift, 369 NLdStFrm = 30 << FormShift, 370 N1RegModImmFrm= 31 << FormShift, 371 N2RegFrm = 32 << FormShift, 372 NVCVTFrm = 33 << FormShift, 373 NVDupLnFrm = 34 << FormShift, 374 N2RegVShLFrm = 35 << FormShift, 375 N2RegVShRFrm = 36 << FormShift, 376 N3RegFrm = 37 << FormShift, 377 N3RegVShFrm = 38 << FormShift, 378 NVExtFrm = 39 << FormShift, 379 NVMulSLFrm = 40 << FormShift, 380 NVTBLFrm = 41 << FormShift, 381 N3RegCplxFrm = 43 << FormShift, 382 383 //===------------------------------------------------------------------===// 384 // Misc flags. 385 386 // UnaryDP - Indicates this is a unary data processing instruction, i.e. 387 // it doesn't have a Rn operand. 388 UnaryDP = 1 << 13, 389 390 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into 391 // a 16-bit Thumb instruction if certain conditions are met. 392 Xform16Bit = 1 << 14, 393 394 // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb 395 // instruction. Used by the parser to determine whether to require the 'S' 396 // suffix on the mnemonic (when not in an IT block) or preclude it (when 397 // in an IT block). 398 ThumbArithFlagSetting = 1 << 19, 399 400 // Whether an instruction can be included in an MVE tail-predicated loop, 401 // though extra validity checks may need to be performed too. 402 ValidForTailPredication = 1 << 20, 403 404 // Whether an instruction writes to the top/bottom half of a vector element 405 // and leaves the other half untouched. 406 RetainsPreviousHalfElement = 1 << 21, 407 408 // Whether the instruction produces a scalar result from vector operands. 409 HorizontalReduction = 1 << 22, 410 411 // Whether this instruction produces a vector result that is larger than 412 // its input, typically reading from the top/bottom halves of the input(s). 413 DoubleWidthResult = 1 << 23, 414 415 // The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32 416 // and 11 = i64. This is the largest type if multiple are present, so a 417 // MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are 418 // some caveats so cannot be used blindly, such as exchanging VMLADAVA's and 419 // complex instructions, which may use different input lanes. 420 VecSizeShift = 24, 421 VecSize = 3 << VecSizeShift, 422 423 //===------------------------------------------------------------------===// 424 // Code domain. 425 DomainShift = 15, 426 DomainMask = 15 << DomainShift, 427 DomainGeneral = 0 << DomainShift, 428 DomainVFP = 1 << DomainShift, 429 DomainNEON = 2 << DomainShift, 430 DomainNEONA8 = 4 << DomainShift, 431 DomainMVE = 8 << DomainShift, 432 433 //===------------------------------------------------------------------===// 434 // Field shifts - such shifts are used to set field while generating 435 // machine instructions. 436 // 437 // FIXME: This list will need adjusting/fixing as the MC code emitter 438 // takes shape and the ARMCodeEmitter.cpp bits go away. 439 ShiftTypeShift = 4, 440 441 M_BitShift = 5, 442 ShiftImmShift = 5, 443 ShiftShift = 7, 444 N_BitShift = 7, 445 ImmHiShift = 8, 446 SoRotImmShift = 8, 447 RegRsShift = 8, 448 ExtRotImmShift = 10, 449 RegRdLoShift = 12, 450 RegRdShift = 12, 451 RegRdHiShift = 16, 452 RegRnShift = 16, 453 S_BitShift = 20, 454 W_BitShift = 21, 455 AM3_I_BitShift = 22, 456 D_BitShift = 22, 457 U_BitShift = 23, 458 P_BitShift = 24, 459 I_BitShift = 25, 460 CondShift = 28 461 }; 462 463 } // end namespace ARMII 464 465 } // end namespace llvm; 466 467 #endif 468