1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDecoderOps.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include "llvm/TargetParser/SubtargetFeature.h" 28 #include <algorithm> 29 #include <cassert> 30 #include <cstdint> 31 #include <vector> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "arm-disassembler" 36 37 using DecodeStatus = MCDisassembler::DecodeStatus; 38 39 namespace { 40 41 // Handles the condition code status of instructions in IT blocks 42 class ITStatus 43 { 44 public: 45 // Returns the condition code for instruction in IT block 46 unsigned getITCC() { 47 unsigned CC = ARMCC::AL; 48 if (instrInITBlock()) 49 CC = ITStates.back(); 50 return CC; 51 } 52 53 // Advances the IT block state to the next T or E 54 void advanceITState() { 55 ITStates.pop_back(); 56 } 57 58 // Returns true if the current instruction is in an IT block 59 bool instrInITBlock() { 60 return !ITStates.empty(); 61 } 62 63 // Returns true if current instruction is the last instruction in an IT block 64 bool instrLastInITBlock() { 65 return ITStates.size() == 1; 66 } 67 68 // Called when decoding an IT instruction. Sets the IT state for 69 // the following instructions that for the IT block. Firstcond 70 // corresponds to the field in the IT instruction encoding; Mask 71 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 72 void setITState(char Firstcond, char Mask) { 73 // (3 - the number of trailing zeros) is the number of then / else. 74 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 76 assert(NumTZ <= 3 && "Invalid IT mask!"); 77 // push condition codes onto the stack the correct order for the pops 78 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 79 unsigned Else = (Mask >> Pos) & 1; 80 ITStates.push_back(CCBits ^ Else); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 class VPTStatus 90 { 91 public: 92 unsigned getVPTPred() { 93 unsigned Pred = ARMVCC::None; 94 if (instrInVPTBlock()) 95 Pred = VPTStates.back(); 96 return Pred; 97 } 98 99 void advanceVPTState() { 100 VPTStates.pop_back(); 101 } 102 103 bool instrInVPTBlock() { 104 return !VPTStates.empty(); 105 } 106 107 bool instrLastInVPTBlock() { 108 return VPTStates.size() == 1; 109 } 110 111 void setVPTState(char Mask) { 112 // (3 - the number of trailing zeros) is the number of then / else. 113 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 114 assert(NumTZ <= 3 && "Invalid VPT mask!"); 115 // push predicates onto the stack the correct order for the pops 116 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 117 bool T = ((Mask >> Pos) & 1) == 0; 118 if (T) 119 VPTStates.push_back(ARMVCC::Then); 120 else 121 VPTStates.push_back(ARMVCC::Else); 122 } 123 VPTStates.push_back(ARMVCC::Then); 124 } 125 126 private: 127 SmallVector<unsigned char, 4> VPTStates; 128 }; 129 130 /// ARM disassembler for all ARM platforms. 131 class ARMDisassembler : public MCDisassembler { 132 public: 133 std::unique_ptr<const MCInstrInfo> MCII; 134 135 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 136 const MCInstrInfo *MCII) 137 : MCDisassembler(STI, Ctx), MCII(MCII) { 138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) 139 ? llvm::endianness::big 140 : llvm::endianness::little; 141 } 142 143 ~ARMDisassembler() override = default; 144 145 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 146 ArrayRef<uint8_t> Bytes, uint64_t Address, 147 raw_ostream &CStream) const override; 148 149 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 150 uint64_t Address) const override; 151 152 private: 153 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &CStream) const; 156 157 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 158 ArrayRef<uint8_t> Bytes, uint64_t Address, 159 raw_ostream &CStream) const; 160 161 mutable ITStatus ITBlock; 162 mutable VPTStatus VPTBlock; 163 164 void AddThumb1SBit(MCInst &MI, bool InITBlock) const; 165 bool isVectorPredicable(const MCInst &MI) const; 166 DecodeStatus AddThumbPredicate(MCInst&) const; 167 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 168 169 llvm::endianness InstructionEndianness; 170 }; 171 172 } // end anonymous namespace 173 174 // Forward declare these because the autogenerated code will reference them. 175 // Definitions are further down. 176 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, 187 const MCDisassembler *Decoder); 188 static DecodeStatus 189 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 193 uint64_t Address, 194 const MCDisassembler *Decoder); 195 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198 static DecodeStatus 199 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 200 const MCDisassembler *Decoder); 201 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204 static DecodeStatus 205 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 206 const MCDisassembler *Decoder); 207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, 215 const MCDisassembler *Decoder); 216 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, 218 const MCDisassembler *Decoder); 219 static DecodeStatus 220 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 221 const MCDisassembler *Decoder); 222 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, 227 const MCDisassembler *Decoder); 228 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, 233 const MCDisassembler *Decoder); 234 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, 236 const MCDisassembler *Decoder); 237 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 238 uint64_t Address, 239 const MCDisassembler *Decoder); 240 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 241 uint64_t Address, 242 const MCDisassembler *Decoder); 243 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 244 uint64_t Address, 245 const MCDisassembler *Decoder); 246 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 247 uint64_t Address, 248 const MCDisassembler *Decoder); 249 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 250 uint64_t Address, 251 const MCDisassembler *Decoder); 252 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 253 uint64_t Address, 254 const MCDisassembler *Decoder); 255 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258 static DecodeStatus 259 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 260 const MCDisassembler *Decoder); 261 262 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 263 uint64_t Address, 264 const MCDisassembler *Decoder); 265 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 266 uint64_t Address, 267 const MCDisassembler *Decoder); 268 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, 270 const MCDisassembler *Decoder); 271 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 272 uint64_t Address, 273 const MCDisassembler *Decoder); 274 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 275 uint64_t Address, 276 const MCDisassembler *Decoder); 277 278 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284 static DecodeStatus 285 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const MCDisassembler *Decoder); 287 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 288 uint64_t Address, 289 const MCDisassembler *Decoder); 290 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, 292 const MCDisassembler *Decoder); 293 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 297 uint64_t Address, 298 const MCDisassembler *Decoder); 299 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 300 uint64_t Address, 301 const MCDisassembler *Decoder); 302 303 static DecodeStatus 304 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 305 uint64_t Adddress, 306 const MCDisassembler *Decoder); 307 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 308 uint64_t Address, 309 const MCDisassembler *Decoder); 310 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 311 uint64_t Address, 312 const MCDisassembler *Decoder); 313 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 314 uint64_t Address, 315 const MCDisassembler *Decoder); 316 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const MCDisassembler *Decoder); 319 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, 321 const MCDisassembler *Decoder); 322 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, 327 const MCDisassembler *Decoder); 328 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, 330 const MCDisassembler *Decoder); 331 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, 333 const MCDisassembler *Decoder); 334 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 338 uint64_t Address, 339 const MCDisassembler *Decoder); 340 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 341 uint64_t Address, 342 const MCDisassembler *Decoder); 343 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 344 uint64_t Address, 345 const MCDisassembler *Decoder); 346 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 347 uint64_t Address, 348 const MCDisassembler *Decoder); 349 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 350 uint64_t Address, 351 const MCDisassembler *Decoder); 352 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 353 uint64_t Address, 354 const MCDisassembler *Decoder); 355 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 356 uint64_t Address, 357 const MCDisassembler *Decoder); 358 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 359 uint64_t Address, 360 const MCDisassembler *Decoder); 361 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 362 uint64_t Address, 363 const MCDisassembler *Decoder); 364 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 365 uint64_t Address, 366 const MCDisassembler *Decoder); 367 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, 372 const MCDisassembler *Decoder); 373 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const MCDisassembler *Decoder); 376 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, 378 const MCDisassembler *Decoder); 379 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 380 uint64_t Address, 381 const MCDisassembler *Decoder); 382 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, 387 const MCDisassembler *Decoder); 388 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 389 uint64_t Address, 390 const MCDisassembler *Decoder); 391 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 392 uint64_t Address, 393 const MCDisassembler *Decoder); 394 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 395 uint64_t Address, 396 const MCDisassembler *Decoder); 397 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 398 uint64_t Address, 399 const MCDisassembler *Decoder); 400 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 401 uint64_t Address, 402 const MCDisassembler *Decoder); 403 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 404 uint64_t Address, 405 const MCDisassembler *Decoder); 406 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 407 uint64_t Address, 408 const MCDisassembler *Decoder); 409 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const MCDisassembler *Decoder); 412 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 413 uint64_t Address, 414 const MCDisassembler *Decoder); 415 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 416 uint64_t Address, 417 const MCDisassembler *Decoder); 418 template <int shift> 419 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 426 uint64_t Address, 427 const MCDisassembler *Decoder); 428 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 429 uint64_t Address, 430 const MCDisassembler *Decoder); 431 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 432 const MCDisassembler *Decoder); 433 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const MCDisassembler *Decoder); 436 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 437 uint64_t Address, 438 const MCDisassembler *Decoder); 439 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const MCDisassembler *Decoder); 442 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const MCDisassembler *Decoder); 448 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 449 uint64_t Address, 450 const MCDisassembler *Decoder); 451 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const MCDisassembler *Decoder); 454 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 455 const MCDisassembler *Decoder); 456 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 457 const MCDisassembler *Decoder); 458 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const MCDisassembler *Decoder); 476 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const MCDisassembler *Decoder); 478 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const MCDisassembler *Decoder); 480 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 481 uint64_t Address, 482 const MCDisassembler *Decoder); 483 static DecodeStatus 484 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 485 const MCDisassembler *Decoder); 486 487 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 488 uint64_t Address, 489 const MCDisassembler *Decoder); 490 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const MCDisassembler *Decoder); 493 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const MCDisassembler *Decoder); 496 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const MCDisassembler *Decoder); 499 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const MCDisassembler *Decoder); 502 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const MCDisassembler *Decoder); 505 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const MCDisassembler *Decoder); 508 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const MCDisassembler *Decoder); 511 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const MCDisassembler *Decoder); 514 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const MCDisassembler *Decoder); 517 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const MCDisassembler *Decoder); 520 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const MCDisassembler *Decoder); 523 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 524 const MCDisassembler *Decoder); 525 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const MCDisassembler *Decoder); 528 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 529 const MCDisassembler *Decoder); 530 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 531 const MCDisassembler *Decoder); 532 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const MCDisassembler *Decoder); 535 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 536 uint64_t Address, 537 const MCDisassembler *Decoder); 538 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const MCDisassembler *Decoder); 541 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 542 const MCDisassembler *Decoder); 543 template <int shift> 544 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 545 const MCDisassembler *Decoder); 546 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const MCDisassembler *Decoder); 549 template <int shift> 550 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 551 uint64_t Address, 552 const MCDisassembler *Decoder); 553 template <int shift, int WriteBack> 554 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 558 uint64_t Address, 559 const MCDisassembler *Decoder); 560 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 561 uint64_t Address, 562 const MCDisassembler *Decoder); 563 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 564 uint64_t Address, 565 const MCDisassembler *Decoder); 566 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const MCDisassembler *Decoder); 569 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const MCDisassembler *Decoder); 572 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 573 uint64_t Address, 574 const MCDisassembler *Decoder); 575 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 576 uint64_t Address, 577 const MCDisassembler *Decoder); 578 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 579 uint64_t Address, 580 const MCDisassembler *Decoder); 581 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 582 const MCDisassembler *Decoder); 583 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 584 uint64_t Address, 585 const MCDisassembler *Decoder); 586 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 587 uint64_t Address, 588 const MCDisassembler *Decoder); 589 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 590 const MCDisassembler *Decoder); 591 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 592 uint64_t Address, 593 const MCDisassembler *Decoder); 594 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 595 uint64_t Address, 596 const MCDisassembler *Decoder); 597 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 598 const MCDisassembler *Decoder); 599 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 600 uint64_t Address, 601 const MCDisassembler *Decoder); 602 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 603 uint64_t Address, 604 const MCDisassembler *Decoder); 605 606 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 607 const MCDisassembler *Decoder); 608 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 609 uint64_t Address, 610 const MCDisassembler *Decoder); 611 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 612 uint64_t Address, 613 const MCDisassembler *Decoder); 614 615 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 616 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 617 uint64_t Address, 618 const MCDisassembler *Decoder); 619 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 620 uint64_t Address, 621 const MCDisassembler *Decoder); 622 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 623 uint64_t Address, 624 const MCDisassembler *Decoder); 625 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 626 const MCDisassembler *Decoder); 627 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 628 uint64_t Address, 629 const MCDisassembler *Decoder); 630 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 631 const MCDisassembler *Decoder); 632 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 633 uint64_t Address, 634 const MCDisassembler *Decoder); 635 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 636 uint64_t Address, 637 const MCDisassembler *Decoder); 638 static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, 639 uint64_t Address, 640 const MCDisassembler *Decoder); 641 static DecodeStatus 642 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 643 const MCDisassembler *Decoder); 644 static DecodeStatus 645 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 646 const MCDisassembler *Decoder); 647 static DecodeStatus 648 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 649 const MCDisassembler *Decoder); 650 static DecodeStatus 651 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 652 const MCDisassembler *Decoder); 653 template <bool Writeback> 654 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const MCDisassembler *Decoder); 657 template <int shift> 658 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 659 uint64_t Address, 660 const MCDisassembler *Decoder); 661 template <int shift> 662 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 663 uint64_t Address, 664 const MCDisassembler *Decoder); 665 template <int shift> 666 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 667 uint64_t Address, 668 const MCDisassembler *Decoder); 669 template <unsigned MinLog, unsigned MaxLog> 670 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 671 uint64_t Address, 672 const MCDisassembler *Decoder); 673 template <unsigned start> 674 static DecodeStatus 675 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 676 const MCDisassembler *Decoder); 677 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 678 uint64_t Address, 679 const MCDisassembler *Decoder); 680 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 681 uint64_t Address, 682 const MCDisassembler *Decoder); 683 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 684 uint64_t Address, 685 const MCDisassembler *Decoder); 686 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 687 uint64_t Address, 688 const MCDisassembler *Decoder); 689 template <bool scalar, OperandDecoder predicate_decoder> 690 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const MCDisassembler *Decoder); 692 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const MCDisassembler *Decoder); 694 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 695 uint64_t Address, 696 const MCDisassembler *Decoder); 697 static DecodeStatus 698 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 699 const MCDisassembler *Decoder); 700 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 701 uint64_t Address, 702 const MCDisassembler *Decoder); 703 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 704 uint64_t Address, 705 const MCDisassembler *Decoder); 706 707 #include "ARMGenDisassemblerTables.inc" 708 709 static MCDisassembler *createARMDisassembler(const Target &T, 710 const MCSubtargetInfo &STI, 711 MCContext &Ctx) { 712 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo()); 713 } 714 715 // Post-decoding checks 716 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 717 uint64_t Address, raw_ostream &CS, 718 uint32_t Insn, 719 DecodeStatus Result) { 720 switch (MI.getOpcode()) { 721 case ARM::HVC: { 722 // HVC is undefined if condition = 0xf otherwise upredictable 723 // if condition != 0xe 724 uint32_t Cond = (Insn >> 28) & 0xF; 725 if (Cond == 0xF) 726 return MCDisassembler::Fail; 727 if (Cond != 0xE) 728 return MCDisassembler::SoftFail; 729 return Result; 730 } 731 case ARM::t2ADDri: 732 case ARM::t2ADDri12: 733 case ARM::t2ADDrr: 734 case ARM::t2ADDrs: 735 case ARM::t2SUBri: 736 case ARM::t2SUBri12: 737 case ARM::t2SUBrr: 738 case ARM::t2SUBrs: 739 if (MI.getOperand(0).getReg() == ARM::SP && 740 MI.getOperand(1).getReg() != ARM::SP) 741 return MCDisassembler::SoftFail; 742 return Result; 743 default: return Result; 744 } 745 } 746 747 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 748 uint64_t Address) const { 749 // In Arm state, instructions are always 4 bytes wide, so there's no 750 // point in skipping any smaller number of bytes if an instruction 751 // can't be decoded. 752 if (!STI.hasFeature(ARM::ModeThumb)) 753 return 4; 754 755 // In a Thumb instruction stream, a halfword is a standalone 2-byte 756 // instruction if and only if its value is less than 0xE800. 757 // Otherwise, it's the first halfword of a 4-byte instruction. 758 // 759 // So, if we can see the upcoming halfword, we can judge on that 760 // basis, and maybe skip a whole 4-byte instruction that we don't 761 // know how to decode, without accidentally trying to interpret its 762 // second half as something else. 763 // 764 // If we don't have the instruction data available, we just have to 765 // recommend skipping the minimum sensible distance, which is 2 766 // bytes. 767 if (Bytes.size() < 2) 768 return 2; 769 770 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 771 Bytes.data(), InstructionEndianness); 772 return Insn16 < 0xE800 ? 2 : 4; 773 } 774 775 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 776 ArrayRef<uint8_t> Bytes, 777 uint64_t Address, 778 raw_ostream &CS) const { 779 if (STI.hasFeature(ARM::ModeThumb)) 780 return getThumbInstruction(MI, Size, Bytes, Address, CS); 781 return getARMInstruction(MI, Size, Bytes, Address, CS); 782 } 783 784 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 785 ArrayRef<uint8_t> Bytes, 786 uint64_t Address, 787 raw_ostream &CS) const { 788 CommentStream = &CS; 789 790 assert(!STI.hasFeature(ARM::ModeThumb) && 791 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 792 "mode!"); 793 794 // We want to read exactly 4 bytes of data. 795 if (Bytes.size() < 4) { 796 Size = 0; 797 return MCDisassembler::Fail; 798 } 799 800 // Encoded as a 32-bit word in the stream. 801 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(), 802 InstructionEndianness); 803 804 // Calling the auto-generated decoder function. 805 DecodeStatus Result = 806 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 807 if (Result != MCDisassembler::Fail) { 808 Size = 4; 809 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 810 } 811 812 struct DecodeTable { 813 const uint8_t *P; 814 bool DecodePred; 815 }; 816 817 const DecodeTable Tables[] = { 818 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 819 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 820 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 821 {DecoderTablev8Crypto32, false}, 822 }; 823 824 for (auto Table : Tables) { 825 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 826 if (Result != MCDisassembler::Fail) { 827 Size = 4; 828 // Add a fake predicate operand, because we share these instruction 829 // definitions with Thumb2 where these instructions are predicable. 830 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 831 return MCDisassembler::Fail; 832 return Result; 833 } 834 } 835 836 Result = 837 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 838 if (Result != MCDisassembler::Fail) { 839 Size = 4; 840 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 841 } 842 843 Size = 4; 844 return MCDisassembler::Fail; 845 } 846 847 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 848 /// immediate Value in the MCInst. The immediate Value has had any PC 849 /// adjustment made by the caller. If the instruction is a branch instruction 850 /// then isBranch is true, else false. If the getOpInfo() function was set as 851 /// part of the setupForSymbolicDisassembly() call then that function is called 852 /// to get any symbolic information at the Address for this instruction. If 853 /// that returns non-zero then the symbolic information it returns is used to 854 /// create an MCExpr and that is added as an operand to the MCInst. If 855 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 856 /// Value is done and if a symbol is found an MCExpr is created with that, else 857 /// an MCExpr with Value is created. This function returns true if it adds an 858 /// operand to the MCInst and false otherwise. 859 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 860 bool isBranch, uint64_t InstSize, 861 MCInst &MI, 862 const MCDisassembler *Decoder) { 863 // FIXME: Does it make sense for value to be negative? 864 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 865 isBranch, /*Offset=*/0, /*OpSize=*/0, 866 InstSize); 867 } 868 869 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 870 /// referenced by a load instruction with the base register that is the Pc. 871 /// These can often be values in a literal pool near the Address of the 872 /// instruction. The Address of the instruction and its immediate Value are 873 /// used as a possible literal pool entry. The SymbolLookUp call back will 874 /// return the name of a symbol referenced by the literal pool's entry if 875 /// the referenced address is that of a symbol. Or it will return a pointer to 876 /// a literal 'C' string if the referenced address of the literal pool's entry 877 /// is an address into a section with 'C' string literals. 878 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 879 const MCDisassembler *Decoder) { 880 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 881 Dis->tryAddingPcLoadReferenceComment(Value, Address); 882 } 883 884 // Thumb1 instructions don't have explicit S bits. Rather, they 885 // implicitly set CPSR. Since it's not represented in the encoding, the 886 // auto-generated decoder won't inject the CPSR operand. We need to fix 887 // that as a post-pass. 888 void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const { 889 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 890 MCInst::iterator I = MI.begin(); 891 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) { 892 if (I == MI.end()) break; 893 if (MCID.operands()[i].isOptionalDef() && 894 MCID.operands()[i].RegClass == ARM::CCRRegClassID) { 895 if (i > 0 && MCID.operands()[i - 1].isPredicate()) 896 continue; 897 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 898 return; 899 } 900 } 901 902 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 903 } 904 905 bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const { 906 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 907 for (unsigned i = 0; i < MCID.NumOperands; ++i) { 908 if (ARM::isVpred(MCID.operands()[i].OperandType)) 909 return true; 910 } 911 return false; 912 } 913 914 // Most Thumb instructions don't have explicit predicates in the 915 // encoding, but rather get their predicates from IT context. We need 916 // to fix up the predicate operands using this context information as a 917 // post-pass. 918 MCDisassembler::DecodeStatus 919 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 920 MCDisassembler::DecodeStatus S = Success; 921 922 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 923 924 // A few instructions actually have predicates encoded in them. Don't 925 // try to overwrite it if we're seeing one of those. 926 switch (MI.getOpcode()) { 927 case ARM::tBcc: 928 case ARM::t2Bcc: 929 case ARM::tCBZ: 930 case ARM::tCBNZ: 931 case ARM::tCPS: 932 case ARM::t2CPS3p: 933 case ARM::t2CPS2p: 934 case ARM::t2CPS1p: 935 case ARM::t2CSEL: 936 case ARM::t2CSINC: 937 case ARM::t2CSINV: 938 case ARM::t2CSNEG: 939 case ARM::tMOVSr: 940 case ARM::tSETEND: 941 // Some instructions (mostly conditional branches) are not 942 // allowed in IT blocks. 943 if (ITBlock.instrInITBlock()) 944 S = SoftFail; 945 else 946 return Success; 947 break; 948 case ARM::t2HINT: 949 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 950 S = SoftFail; 951 break; 952 case ARM::tB: 953 case ARM::t2B: 954 case ARM::t2TBB: 955 case ARM::t2TBH: 956 // Some instructions (mostly unconditional branches) can 957 // only appears at the end of, or outside of, an IT. 958 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 959 S = SoftFail; 960 break; 961 default: 962 break; 963 } 964 965 // Warn on non-VPT predicable instruction in a VPT block and a VPT 966 // predicable instruction in an IT block 967 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) || 968 (isVectorPredicable(MI) && ITBlock.instrInITBlock())) 969 S = SoftFail; 970 971 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 972 // assume a predicate of AL. 973 unsigned CC = ARMCC::AL; 974 unsigned VCC = ARMVCC::None; 975 if (ITBlock.instrInITBlock()) { 976 CC = ITBlock.getITCC(); 977 ITBlock.advanceITState(); 978 } else if (VPTBlock.instrInVPTBlock()) { 979 VCC = VPTBlock.getVPTPred(); 980 VPTBlock.advanceVPTState(); 981 } 982 983 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 984 985 MCInst::iterator CCI = MI.begin(); 986 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) { 987 if (MCID.operands()[i].isPredicate() || CCI == MI.end()) 988 break; 989 } 990 991 if (MCID.isPredicable()) { 992 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 993 ++CCI; 994 if (CC == ARMCC::AL) 995 MI.insert(CCI, MCOperand::createReg(0)); 996 else 997 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 998 } else if (CC != ARMCC::AL) { 999 Check(S, SoftFail); 1000 } 1001 1002 MCInst::iterator VCCI = MI.begin(); 1003 unsigned VCCPos; 1004 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) { 1005 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end()) 1006 break; 1007 } 1008 1009 if (isVectorPredicable(MI)) { 1010 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1011 ++VCCI; 1012 if (VCC == ARMVCC::None) 1013 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1014 else 1015 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1016 ++VCCI; 1017 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1018 ++VCCI; 1019 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1020 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); 1021 assert(TiedOp >= 0 && 1022 "Inactive register in vpred_r is not tied to an output!"); 1023 // Copy the operand to ensure it's not invalidated when MI grows. 1024 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1025 } 1026 } else if (VCC != ARMVCC::None) { 1027 Check(S, SoftFail); 1028 } 1029 1030 return S; 1031 } 1032 1033 // Thumb VFP instructions are a special case. Because we share their 1034 // encodings between ARM and Thumb modes, and they are predicable in ARM 1035 // mode, the auto-generated decoder will give them an (incorrect) 1036 // predicate operand. We need to rewrite these operands based on the IT 1037 // context as a post-pass. 1038 void ARMDisassembler::UpdateThumbVFPPredicate( 1039 DecodeStatus &S, MCInst &MI) const { 1040 unsigned CC; 1041 CC = ITBlock.getITCC(); 1042 if (CC == 0xF) 1043 CC = ARMCC::AL; 1044 if (ITBlock.instrInITBlock()) 1045 ITBlock.advanceITState(); 1046 else if (VPTBlock.instrInVPTBlock()) { 1047 CC = VPTBlock.getVPTPred(); 1048 VPTBlock.advanceVPTState(); 1049 } 1050 1051 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 1052 ArrayRef<MCOperandInfo> OpInfo = MCID.operands(); 1053 MCInst::iterator I = MI.begin(); 1054 unsigned short NumOps = MCID.NumOperands; 1055 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1056 if (OpInfo[i].isPredicate() ) { 1057 if (CC != ARMCC::AL && !MCID.isPredicable()) 1058 Check(S, SoftFail); 1059 I->setImm(CC); 1060 ++I; 1061 if (CC == ARMCC::AL) 1062 I->setReg(0); 1063 else 1064 I->setReg(ARM::CPSR); 1065 return; 1066 } 1067 } 1068 } 1069 1070 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1071 ArrayRef<uint8_t> Bytes, 1072 uint64_t Address, 1073 raw_ostream &CS) const { 1074 CommentStream = &CS; 1075 1076 assert(STI.hasFeature(ARM::ModeThumb) && 1077 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1078 1079 // We want to read exactly 2 bytes of data. 1080 if (Bytes.size() < 2) { 1081 Size = 0; 1082 return MCDisassembler::Fail; 1083 } 1084 1085 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 1086 Bytes.data(), InstructionEndianness); 1087 DecodeStatus Result = 1088 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1089 if (Result != MCDisassembler::Fail) { 1090 Size = 2; 1091 Check(Result, AddThumbPredicate(MI)); 1092 return Result; 1093 } 1094 1095 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1096 STI); 1097 if (Result) { 1098 Size = 2; 1099 bool InITBlock = ITBlock.instrInITBlock(); 1100 Check(Result, AddThumbPredicate(MI)); 1101 AddThumb1SBit(MI, InITBlock); 1102 return Result; 1103 } 1104 1105 Result = 1106 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1107 if (Result != MCDisassembler::Fail) { 1108 Size = 2; 1109 1110 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1111 // the Thumb predicate. 1112 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1113 Result = MCDisassembler::SoftFail; 1114 1115 Check(Result, AddThumbPredicate(MI)); 1116 1117 // If we find an IT instruction, we need to parse its condition 1118 // code and mask operands so that we can apply them correctly 1119 // to the subsequent instructions. 1120 if (MI.getOpcode() == ARM::t2IT) { 1121 unsigned Firstcond = MI.getOperand(0).getImm(); 1122 unsigned Mask = MI.getOperand(1).getImm(); 1123 ITBlock.setITState(Firstcond, Mask); 1124 1125 // An IT instruction that would give a 'NV' predicate is unpredictable. 1126 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1127 CS << "unpredictable IT predicate sequence"; 1128 } 1129 1130 return Result; 1131 } 1132 1133 // We want to read exactly 4 bytes of data. 1134 if (Bytes.size() < 4) { 1135 Size = 0; 1136 return MCDisassembler::Fail; 1137 } 1138 1139 uint32_t Insn32 = 1140 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>( 1141 Bytes.data() + 2, InstructionEndianness); 1142 1143 Result = 1144 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1145 if (Result != MCDisassembler::Fail) { 1146 Size = 4; 1147 1148 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1149 // the VPT predicate. 1150 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1151 Result = MCDisassembler::SoftFail; 1152 1153 Check(Result, AddThumbPredicate(MI)); 1154 1155 if (isVPTOpcode(MI.getOpcode())) { 1156 unsigned Mask = MI.getOperand(0).getImm(); 1157 VPTBlock.setVPTState(Mask); 1158 } 1159 1160 return Result; 1161 } 1162 1163 Result = 1164 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1165 if (Result != MCDisassembler::Fail) { 1166 Size = 4; 1167 bool InITBlock = ITBlock.instrInITBlock(); 1168 Check(Result, AddThumbPredicate(MI)); 1169 AddThumb1SBit(MI, InITBlock); 1170 return Result; 1171 } 1172 1173 Result = 1174 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1175 if (Result != MCDisassembler::Fail) { 1176 Size = 4; 1177 Check(Result, AddThumbPredicate(MI)); 1178 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1179 } 1180 1181 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1182 Result = 1183 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1184 if (Result != MCDisassembler::Fail) { 1185 Size = 4; 1186 UpdateThumbVFPPredicate(Result, MI); 1187 return Result; 1188 } 1189 } 1190 1191 Result = 1192 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1193 if (Result != MCDisassembler::Fail) { 1194 Size = 4; 1195 return Result; 1196 } 1197 1198 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1199 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1200 STI); 1201 if (Result != MCDisassembler::Fail) { 1202 Size = 4; 1203 Check(Result, AddThumbPredicate(MI)); 1204 return Result; 1205 } 1206 } 1207 1208 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1209 uint32_t NEONLdStInsn = Insn32; 1210 NEONLdStInsn &= 0xF0FFFFFF; 1211 NEONLdStInsn |= 0x04000000; 1212 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1213 Address, this, STI); 1214 if (Result != MCDisassembler::Fail) { 1215 Size = 4; 1216 Check(Result, AddThumbPredicate(MI)); 1217 return Result; 1218 } 1219 } 1220 1221 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1222 uint32_t NEONDataInsn = Insn32; 1223 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1224 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1225 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1226 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1227 Address, this, STI); 1228 if (Result != MCDisassembler::Fail) { 1229 Size = 4; 1230 Check(Result, AddThumbPredicate(MI)); 1231 return Result; 1232 } 1233 1234 uint32_t NEONCryptoInsn = Insn32; 1235 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1236 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1237 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1238 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1239 Address, this, STI); 1240 if (Result != MCDisassembler::Fail) { 1241 Size = 4; 1242 return Result; 1243 } 1244 1245 uint32_t NEONv8Insn = Insn32; 1246 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1247 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1248 this, STI); 1249 if (Result != MCDisassembler::Fail) { 1250 Size = 4; 1251 return Result; 1252 } 1253 } 1254 1255 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1256 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1257 ? DecoderTableThumb2CDE32 1258 : DecoderTableThumb2CoProc32; 1259 Result = 1260 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1261 if (Result != MCDisassembler::Fail) { 1262 Size = 4; 1263 Check(Result, AddThumbPredicate(MI)); 1264 return Result; 1265 } 1266 1267 Size = 0; 1268 return MCDisassembler::Fail; 1269 } 1270 1271 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1272 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1273 createARMDisassembler); 1274 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1275 createARMDisassembler); 1276 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1277 createARMDisassembler); 1278 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1279 createARMDisassembler); 1280 } 1281 1282 static const uint16_t GPRDecoderTable[] = { 1283 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1284 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1285 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1286 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1287 }; 1288 1289 static const uint16_t CLRMGPRDecoderTable[] = { 1290 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1291 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1292 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1293 ARM::R12, 0, ARM::LR, ARM::APSR 1294 }; 1295 1296 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, 1298 const MCDisassembler *Decoder) { 1299 if (RegNo > 15) 1300 return MCDisassembler::Fail; 1301 1302 unsigned Register = GPRDecoderTable[RegNo]; 1303 Inst.addOperand(MCOperand::createReg(Register)); 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1308 uint64_t Address, 1309 const MCDisassembler *Decoder) { 1310 if (RegNo > 15) 1311 return MCDisassembler::Fail; 1312 1313 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1314 if (Register == 0) 1315 return MCDisassembler::Fail; 1316 1317 Inst.addOperand(MCOperand::createReg(Register)); 1318 return MCDisassembler::Success; 1319 } 1320 1321 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1322 uint64_t Address, 1323 const MCDisassembler *Decoder) { 1324 DecodeStatus S = MCDisassembler::Success; 1325 1326 if (RegNo == 15) 1327 S = MCDisassembler::SoftFail; 1328 1329 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1330 1331 return S; 1332 } 1333 1334 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1335 uint64_t Address, 1336 const MCDisassembler *Decoder) { 1337 DecodeStatus S = MCDisassembler::Success; 1338 1339 if (RegNo == 13) 1340 S = MCDisassembler::SoftFail; 1341 1342 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1343 1344 return S; 1345 } 1346 1347 static DecodeStatus 1348 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1349 const MCDisassembler *Decoder) { 1350 DecodeStatus S = MCDisassembler::Success; 1351 1352 if (RegNo == 15) 1353 { 1354 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1355 return MCDisassembler::Success; 1356 } 1357 1358 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1359 return S; 1360 } 1361 1362 static DecodeStatus 1363 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1364 const MCDisassembler *Decoder) { 1365 DecodeStatus S = MCDisassembler::Success; 1366 1367 if (RegNo == 15) 1368 { 1369 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1370 return MCDisassembler::Success; 1371 } 1372 1373 if (RegNo == 13) 1374 Check(S, MCDisassembler::SoftFail); 1375 1376 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1377 return S; 1378 } 1379 1380 static DecodeStatus 1381 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1382 const MCDisassembler *Decoder) { 1383 DecodeStatus S = MCDisassembler::Success; 1384 if (RegNo == 13) 1385 return MCDisassembler::Fail; 1386 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1387 return S; 1388 } 1389 1390 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1391 uint64_t Address, 1392 const MCDisassembler *Decoder) { 1393 if (RegNo > 7) 1394 return MCDisassembler::Fail; 1395 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1396 } 1397 1398 static const uint16_t GPRPairDecoderTable[] = { 1399 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1400 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1401 }; 1402 1403 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1404 uint64_t Address, 1405 const MCDisassembler *Decoder) { 1406 DecodeStatus S = MCDisassembler::Success; 1407 1408 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1409 // rather than SoftFail as there is no GPRPair table entry for index 7. 1410 if (RegNo > 13) 1411 return MCDisassembler::Fail; 1412 1413 if (RegNo & 1) 1414 S = MCDisassembler::SoftFail; 1415 1416 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1417 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1418 return S; 1419 } 1420 1421 static DecodeStatus 1422 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1423 const MCDisassembler *Decoder) { 1424 if (RegNo > 13) 1425 return MCDisassembler::Fail; 1426 1427 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1428 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1429 1430 if ((RegNo & 1) || RegNo > 10) 1431 return MCDisassembler::SoftFail; 1432 return MCDisassembler::Success; 1433 } 1434 1435 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1436 uint64_t Address, 1437 const MCDisassembler *Decoder) { 1438 if (RegNo != 13) 1439 return MCDisassembler::Fail; 1440 1441 unsigned Register = GPRDecoderTable[RegNo]; 1442 Inst.addOperand(MCOperand::createReg(Register)); 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1447 uint64_t Address, 1448 const MCDisassembler *Decoder) { 1449 unsigned Register = 0; 1450 switch (RegNo) { 1451 case 0: 1452 Register = ARM::R0; 1453 break; 1454 case 1: 1455 Register = ARM::R1; 1456 break; 1457 case 2: 1458 Register = ARM::R2; 1459 break; 1460 case 3: 1461 Register = ARM::R3; 1462 break; 1463 case 9: 1464 Register = ARM::R9; 1465 break; 1466 case 12: 1467 Register = ARM::R12; 1468 break; 1469 default: 1470 return MCDisassembler::Fail; 1471 } 1472 1473 Inst.addOperand(MCOperand::createReg(Register)); 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1478 uint64_t Address, 1479 const MCDisassembler *Decoder) { 1480 DecodeStatus S = MCDisassembler::Success; 1481 1482 const FeatureBitset &featureBits = 1483 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1484 1485 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1486 S = MCDisassembler::SoftFail; 1487 1488 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1489 return S; 1490 } 1491 1492 static const uint16_t SPRDecoderTable[] = { 1493 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1494 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1495 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1496 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1501 }; 1502 1503 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1504 uint64_t Address, 1505 const MCDisassembler *Decoder) { 1506 if (RegNo > 31) 1507 return MCDisassembler::Fail; 1508 1509 unsigned Register = SPRDecoderTable[RegNo]; 1510 Inst.addOperand(MCOperand::createReg(Register)); 1511 return MCDisassembler::Success; 1512 } 1513 1514 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1515 uint64_t Address, 1516 const MCDisassembler *Decoder) { 1517 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1518 } 1519 1520 static const uint16_t DPRDecoderTable[] = { 1521 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1522 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1523 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1524 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1525 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1526 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1527 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1528 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1529 }; 1530 1531 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1532 uint64_t Address, 1533 const MCDisassembler *Decoder) { 1534 const FeatureBitset &featureBits = 1535 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1536 1537 bool hasD32 = featureBits[ARM::FeatureD32]; 1538 1539 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1540 return MCDisassembler::Fail; 1541 1542 unsigned Register = DPRDecoderTable[RegNo]; 1543 Inst.addOperand(MCOperand::createReg(Register)); 1544 return MCDisassembler::Success; 1545 } 1546 1547 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1548 uint64_t Address, 1549 const MCDisassembler *Decoder) { 1550 if (RegNo > 7) 1551 return MCDisassembler::Fail; 1552 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1553 } 1554 1555 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1556 uint64_t Address, 1557 const MCDisassembler *Decoder) { 1558 if (RegNo > 15) 1559 return MCDisassembler::Fail; 1560 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1561 } 1562 1563 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1564 uint64_t Address, 1565 const MCDisassembler *Decoder) { 1566 if (RegNo > 15) 1567 return MCDisassembler::Fail; 1568 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1569 } 1570 1571 static const uint16_t QPRDecoderTable[] = { 1572 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1574 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1575 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1576 }; 1577 1578 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1579 uint64_t Address, 1580 const MCDisassembler *Decoder) { 1581 if (RegNo > 31 || (RegNo & 1) != 0) 1582 return MCDisassembler::Fail; 1583 RegNo >>= 1; 1584 1585 unsigned Register = QPRDecoderTable[RegNo]; 1586 Inst.addOperand(MCOperand::createReg(Register)); 1587 return MCDisassembler::Success; 1588 } 1589 1590 static const uint16_t DPairDecoderTable[] = { 1591 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1594 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1595 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1596 ARM::Q15 1597 }; 1598 1599 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1600 uint64_t Address, 1601 const MCDisassembler *Decoder) { 1602 if (RegNo > 30) 1603 return MCDisassembler::Fail; 1604 1605 unsigned Register = DPairDecoderTable[RegNo]; 1606 Inst.addOperand(MCOperand::createReg(Register)); 1607 return MCDisassembler::Success; 1608 } 1609 1610 static const uint16_t DPairSpacedDecoderTable[] = { 1611 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1612 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1613 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1614 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1615 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1616 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1617 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1618 ARM::D28_D30, ARM::D29_D31 1619 }; 1620 1621 static DecodeStatus 1622 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1623 const MCDisassembler *Decoder) { 1624 if (RegNo > 29) 1625 return MCDisassembler::Fail; 1626 1627 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1628 Inst.addOperand(MCOperand::createReg(Register)); 1629 return MCDisassembler::Success; 1630 } 1631 1632 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1633 uint64_t Address, 1634 const MCDisassembler *Decoder) { 1635 DecodeStatus S = MCDisassembler::Success; 1636 if (Val == 0xF) return MCDisassembler::Fail; 1637 // AL predicate is not allowed on Thumb1 branches. 1638 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1639 return MCDisassembler::Fail; 1640 const MCInstrInfo *MCII = 1641 static_cast<const ARMDisassembler *>(Decoder)->MCII.get(); 1642 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable()) 1643 Check(S, MCDisassembler::SoftFail); 1644 Inst.addOperand(MCOperand::createImm(Val)); 1645 if (Val == ARMCC::AL) { 1646 Inst.addOperand(MCOperand::createReg(0)); 1647 } else 1648 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1649 return S; 1650 } 1651 1652 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1653 uint64_t Address, 1654 const MCDisassembler *Decoder) { 1655 if (Val) 1656 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1657 else 1658 Inst.addOperand(MCOperand::createReg(0)); 1659 return MCDisassembler::Success; 1660 } 1661 1662 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1663 uint64_t Address, 1664 const MCDisassembler *Decoder) { 1665 DecodeStatus S = MCDisassembler::Success; 1666 1667 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1668 unsigned type = fieldFromInstruction(Val, 5, 2); 1669 unsigned imm = fieldFromInstruction(Val, 7, 5); 1670 1671 // Register-immediate 1672 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1673 return MCDisassembler::Fail; 1674 1675 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1676 switch (type) { 1677 case 0: 1678 Shift = ARM_AM::lsl; 1679 break; 1680 case 1: 1681 Shift = ARM_AM::lsr; 1682 break; 1683 case 2: 1684 Shift = ARM_AM::asr; 1685 break; 1686 case 3: 1687 Shift = ARM_AM::ror; 1688 break; 1689 } 1690 1691 if (Shift == ARM_AM::ror && imm == 0) 1692 Shift = ARM_AM::rrx; 1693 1694 unsigned Op = Shift | (imm << 3); 1695 Inst.addOperand(MCOperand::createImm(Op)); 1696 1697 return S; 1698 } 1699 1700 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1701 uint64_t Address, 1702 const MCDisassembler *Decoder) { 1703 DecodeStatus S = MCDisassembler::Success; 1704 1705 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1706 unsigned type = fieldFromInstruction(Val, 5, 2); 1707 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1708 1709 // Register-register 1710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1713 return MCDisassembler::Fail; 1714 1715 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1716 switch (type) { 1717 case 0: 1718 Shift = ARM_AM::lsl; 1719 break; 1720 case 1: 1721 Shift = ARM_AM::lsr; 1722 break; 1723 case 2: 1724 Shift = ARM_AM::asr; 1725 break; 1726 case 3: 1727 Shift = ARM_AM::ror; 1728 break; 1729 } 1730 1731 Inst.addOperand(MCOperand::createImm(Shift)); 1732 1733 return S; 1734 } 1735 1736 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1737 uint64_t Address, 1738 const MCDisassembler *Decoder) { 1739 DecodeStatus S = MCDisassembler::Success; 1740 1741 bool NeedDisjointWriteback = false; 1742 unsigned WritebackReg = 0; 1743 bool CLRM = false; 1744 switch (Inst.getOpcode()) { 1745 default: 1746 break; 1747 case ARM::LDMIA_UPD: 1748 case ARM::LDMDB_UPD: 1749 case ARM::LDMIB_UPD: 1750 case ARM::LDMDA_UPD: 1751 case ARM::t2LDMIA_UPD: 1752 case ARM::t2LDMDB_UPD: 1753 case ARM::t2STMIA_UPD: 1754 case ARM::t2STMDB_UPD: 1755 NeedDisjointWriteback = true; 1756 WritebackReg = Inst.getOperand(0).getReg(); 1757 break; 1758 case ARM::t2CLRM: 1759 CLRM = true; 1760 break; 1761 } 1762 1763 // Empty register lists are not allowed. 1764 if (Val == 0) return MCDisassembler::Fail; 1765 for (unsigned i = 0; i < 16; ++i) { 1766 if (Val & (1 << i)) { 1767 if (CLRM) { 1768 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1769 return MCDisassembler::Fail; 1770 } 1771 } else { 1772 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1773 return MCDisassembler::Fail; 1774 // Writeback not allowed if Rn is in the target list. 1775 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1776 Check(S, MCDisassembler::SoftFail); 1777 } 1778 } 1779 } 1780 1781 return S; 1782 } 1783 1784 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1785 uint64_t Address, 1786 const MCDisassembler *Decoder) { 1787 DecodeStatus S = MCDisassembler::Success; 1788 1789 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1790 unsigned regs = fieldFromInstruction(Val, 0, 8); 1791 1792 // In case of unpredictable encoding, tweak the operands. 1793 if (regs == 0 || (Vd + regs) > 32) { 1794 regs = Vd + regs > 32 ? 32 - Vd : regs; 1795 regs = std::max( 1u, regs); 1796 S = MCDisassembler::SoftFail; 1797 } 1798 1799 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1800 return MCDisassembler::Fail; 1801 for (unsigned i = 0; i < (regs - 1); ++i) { 1802 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1803 return MCDisassembler::Fail; 1804 } 1805 1806 return S; 1807 } 1808 1809 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1810 uint64_t Address, 1811 const MCDisassembler *Decoder) { 1812 DecodeStatus S = MCDisassembler::Success; 1813 1814 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1815 unsigned regs = fieldFromInstruction(Val, 1, 7); 1816 1817 // In case of unpredictable encoding, tweak the operands. 1818 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1819 regs = Vd + regs > 32 ? 32 - Vd : regs; 1820 regs = std::max( 1u, regs); 1821 regs = std::min(16u, regs); 1822 S = MCDisassembler::SoftFail; 1823 } 1824 1825 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1826 return MCDisassembler::Fail; 1827 for (unsigned i = 0; i < (regs - 1); ++i) { 1828 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1829 return MCDisassembler::Fail; 1830 } 1831 1832 return S; 1833 } 1834 1835 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1836 uint64_t Address, 1837 const MCDisassembler *Decoder) { 1838 // This operand encodes a mask of contiguous zeros between a specified MSB 1839 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1840 // the mask of all bits LSB-and-lower, and then xor them to create 1841 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1842 // create the final mask. 1843 unsigned msb = fieldFromInstruction(Val, 5, 5); 1844 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1845 1846 DecodeStatus S = MCDisassembler::Success; 1847 if (lsb > msb) { 1848 Check(S, MCDisassembler::SoftFail); 1849 // The check above will cause the warning for the "potentially undefined 1850 // instruction encoding" but we can't build a bad MCOperand value here 1851 // with a lsb > msb or else printing the MCInst will cause a crash. 1852 lsb = msb; 1853 } 1854 1855 uint32_t msb_mask = 0xFFFFFFFF; 1856 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1857 uint32_t lsb_mask = (1U << lsb) - 1; 1858 1859 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1860 return S; 1861 } 1862 1863 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1864 uint64_t Address, 1865 const MCDisassembler *Decoder) { 1866 DecodeStatus S = MCDisassembler::Success; 1867 1868 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1869 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1870 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1871 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1872 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1873 unsigned U = fieldFromInstruction(Insn, 23, 1); 1874 const FeatureBitset &featureBits = 1875 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1876 1877 switch (Inst.getOpcode()) { 1878 case ARM::LDC_OFFSET: 1879 case ARM::LDC_PRE: 1880 case ARM::LDC_POST: 1881 case ARM::LDC_OPTION: 1882 case ARM::LDCL_OFFSET: 1883 case ARM::LDCL_PRE: 1884 case ARM::LDCL_POST: 1885 case ARM::LDCL_OPTION: 1886 case ARM::STC_OFFSET: 1887 case ARM::STC_PRE: 1888 case ARM::STC_POST: 1889 case ARM::STC_OPTION: 1890 case ARM::STCL_OFFSET: 1891 case ARM::STCL_PRE: 1892 case ARM::STCL_POST: 1893 case ARM::STCL_OPTION: 1894 case ARM::t2LDC_OFFSET: 1895 case ARM::t2LDC_PRE: 1896 case ARM::t2LDC_POST: 1897 case ARM::t2LDC_OPTION: 1898 case ARM::t2LDCL_OFFSET: 1899 case ARM::t2LDCL_PRE: 1900 case ARM::t2LDCL_POST: 1901 case ARM::t2LDCL_OPTION: 1902 case ARM::t2STC_OFFSET: 1903 case ARM::t2STC_PRE: 1904 case ARM::t2STC_POST: 1905 case ARM::t2STC_OPTION: 1906 case ARM::t2STCL_OFFSET: 1907 case ARM::t2STCL_PRE: 1908 case ARM::t2STCL_POST: 1909 case ARM::t2STCL_OPTION: 1910 case ARM::t2LDC2_OFFSET: 1911 case ARM::t2LDC2L_OFFSET: 1912 case ARM::t2LDC2_PRE: 1913 case ARM::t2LDC2L_PRE: 1914 case ARM::t2STC2_OFFSET: 1915 case ARM::t2STC2L_OFFSET: 1916 case ARM::t2STC2_PRE: 1917 case ARM::t2STC2L_PRE: 1918 case ARM::LDC2_OFFSET: 1919 case ARM::LDC2L_OFFSET: 1920 case ARM::LDC2_PRE: 1921 case ARM::LDC2L_PRE: 1922 case ARM::STC2_OFFSET: 1923 case ARM::STC2L_OFFSET: 1924 case ARM::STC2_PRE: 1925 case ARM::STC2L_PRE: 1926 case ARM::t2LDC2_OPTION: 1927 case ARM::t2STC2_OPTION: 1928 case ARM::t2LDC2_POST: 1929 case ARM::t2LDC2L_POST: 1930 case ARM::t2STC2_POST: 1931 case ARM::t2STC2L_POST: 1932 case ARM::LDC2_POST: 1933 case ARM::LDC2L_POST: 1934 case ARM::STC2_POST: 1935 case ARM::STC2L_POST: 1936 if (coproc == 0xA || coproc == 0xB || 1937 (featureBits[ARM::HasV8_1MMainlineOps] && 1938 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1939 coproc == 0xE || coproc == 0xF))) 1940 return MCDisassembler::Fail; 1941 break; 1942 default: 1943 break; 1944 } 1945 1946 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1947 return MCDisassembler::Fail; 1948 1949 Inst.addOperand(MCOperand::createImm(coproc)); 1950 Inst.addOperand(MCOperand::createImm(CRd)); 1951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1952 return MCDisassembler::Fail; 1953 1954 switch (Inst.getOpcode()) { 1955 case ARM::t2LDC2_OFFSET: 1956 case ARM::t2LDC2L_OFFSET: 1957 case ARM::t2LDC2_PRE: 1958 case ARM::t2LDC2L_PRE: 1959 case ARM::t2STC2_OFFSET: 1960 case ARM::t2STC2L_OFFSET: 1961 case ARM::t2STC2_PRE: 1962 case ARM::t2STC2L_PRE: 1963 case ARM::LDC2_OFFSET: 1964 case ARM::LDC2L_OFFSET: 1965 case ARM::LDC2_PRE: 1966 case ARM::LDC2L_PRE: 1967 case ARM::STC2_OFFSET: 1968 case ARM::STC2L_OFFSET: 1969 case ARM::STC2_PRE: 1970 case ARM::STC2L_PRE: 1971 case ARM::t2LDC_OFFSET: 1972 case ARM::t2LDCL_OFFSET: 1973 case ARM::t2LDC_PRE: 1974 case ARM::t2LDCL_PRE: 1975 case ARM::t2STC_OFFSET: 1976 case ARM::t2STCL_OFFSET: 1977 case ARM::t2STC_PRE: 1978 case ARM::t2STCL_PRE: 1979 case ARM::LDC_OFFSET: 1980 case ARM::LDCL_OFFSET: 1981 case ARM::LDC_PRE: 1982 case ARM::LDCL_PRE: 1983 case ARM::STC_OFFSET: 1984 case ARM::STCL_OFFSET: 1985 case ARM::STC_PRE: 1986 case ARM::STCL_PRE: 1987 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1988 Inst.addOperand(MCOperand::createImm(imm)); 1989 break; 1990 case ARM::t2LDC2_POST: 1991 case ARM::t2LDC2L_POST: 1992 case ARM::t2STC2_POST: 1993 case ARM::t2STC2L_POST: 1994 case ARM::LDC2_POST: 1995 case ARM::LDC2L_POST: 1996 case ARM::STC2_POST: 1997 case ARM::STC2L_POST: 1998 case ARM::t2LDC_POST: 1999 case ARM::t2LDCL_POST: 2000 case ARM::t2STC_POST: 2001 case ARM::t2STCL_POST: 2002 case ARM::LDC_POST: 2003 case ARM::LDCL_POST: 2004 case ARM::STC_POST: 2005 case ARM::STCL_POST: 2006 imm |= U << 8; 2007 [[fallthrough]]; 2008 default: 2009 // The 'option' variant doesn't encode 'U' in the immediate since 2010 // the immediate is unsigned [0,255]. 2011 Inst.addOperand(MCOperand::createImm(imm)); 2012 break; 2013 } 2014 2015 switch (Inst.getOpcode()) { 2016 case ARM::LDC_OFFSET: 2017 case ARM::LDC_PRE: 2018 case ARM::LDC_POST: 2019 case ARM::LDC_OPTION: 2020 case ARM::LDCL_OFFSET: 2021 case ARM::LDCL_PRE: 2022 case ARM::LDCL_POST: 2023 case ARM::LDCL_OPTION: 2024 case ARM::STC_OFFSET: 2025 case ARM::STC_PRE: 2026 case ARM::STC_POST: 2027 case ARM::STC_OPTION: 2028 case ARM::STCL_OFFSET: 2029 case ARM::STCL_PRE: 2030 case ARM::STCL_POST: 2031 case ARM::STCL_OPTION: 2032 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2033 return MCDisassembler::Fail; 2034 break; 2035 default: 2036 break; 2037 } 2038 2039 return S; 2040 } 2041 2042 static DecodeStatus 2043 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2044 const MCDisassembler *Decoder) { 2045 DecodeStatus S = MCDisassembler::Success; 2046 2047 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2048 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2049 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2050 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2051 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2052 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2053 unsigned P = fieldFromInstruction(Insn, 24, 1); 2054 unsigned W = fieldFromInstruction(Insn, 21, 1); 2055 2056 // On stores, the writeback operand precedes Rt. 2057 switch (Inst.getOpcode()) { 2058 case ARM::STR_POST_IMM: 2059 case ARM::STR_POST_REG: 2060 case ARM::STRB_POST_IMM: 2061 case ARM::STRB_POST_REG: 2062 case ARM::STRT_POST_REG: 2063 case ARM::STRT_POST_IMM: 2064 case ARM::STRBT_POST_REG: 2065 case ARM::STRBT_POST_IMM: 2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2067 return MCDisassembler::Fail; 2068 break; 2069 default: 2070 break; 2071 } 2072 2073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2074 return MCDisassembler::Fail; 2075 2076 // On loads, the writeback operand comes after Rt. 2077 switch (Inst.getOpcode()) { 2078 case ARM::LDR_POST_IMM: 2079 case ARM::LDR_POST_REG: 2080 case ARM::LDRB_POST_IMM: 2081 case ARM::LDRB_POST_REG: 2082 case ARM::LDRBT_POST_REG: 2083 case ARM::LDRBT_POST_IMM: 2084 case ARM::LDRT_POST_REG: 2085 case ARM::LDRT_POST_IMM: 2086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2087 return MCDisassembler::Fail; 2088 break; 2089 default: 2090 break; 2091 } 2092 2093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2094 return MCDisassembler::Fail; 2095 2096 ARM_AM::AddrOpc Op = ARM_AM::add; 2097 if (!fieldFromInstruction(Insn, 23, 1)) 2098 Op = ARM_AM::sub; 2099 2100 bool writeback = (P == 0) || (W == 1); 2101 unsigned idx_mode = 0; 2102 if (P && writeback) 2103 idx_mode = ARMII::IndexModePre; 2104 else if (!P && writeback) 2105 idx_mode = ARMII::IndexModePost; 2106 2107 if (writeback && (Rn == 15 || Rn == Rt)) 2108 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2109 2110 if (reg) { 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2114 switch( fieldFromInstruction(Insn, 5, 2)) { 2115 case 0: 2116 Opc = ARM_AM::lsl; 2117 break; 2118 case 1: 2119 Opc = ARM_AM::lsr; 2120 break; 2121 case 2: 2122 Opc = ARM_AM::asr; 2123 break; 2124 case 3: 2125 Opc = ARM_AM::ror; 2126 break; 2127 default: 2128 return MCDisassembler::Fail; 2129 } 2130 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2131 if (Opc == ARM_AM::ror && amt == 0) 2132 Opc = ARM_AM::rrx; 2133 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2134 2135 Inst.addOperand(MCOperand::createImm(imm)); 2136 } else { 2137 Inst.addOperand(MCOperand::createReg(0)); 2138 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2139 Inst.addOperand(MCOperand::createImm(tmp)); 2140 } 2141 2142 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2143 return MCDisassembler::Fail; 2144 2145 return S; 2146 } 2147 2148 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2149 uint64_t Address, 2150 const MCDisassembler *Decoder) { 2151 DecodeStatus S = MCDisassembler::Success; 2152 2153 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2154 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2155 unsigned type = fieldFromInstruction(Val, 5, 2); 2156 unsigned imm = fieldFromInstruction(Val, 7, 5); 2157 unsigned U = fieldFromInstruction(Val, 12, 1); 2158 2159 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2160 switch (type) { 2161 case 0: 2162 ShOp = ARM_AM::lsl; 2163 break; 2164 case 1: 2165 ShOp = ARM_AM::lsr; 2166 break; 2167 case 2: 2168 ShOp = ARM_AM::asr; 2169 break; 2170 case 3: 2171 ShOp = ARM_AM::ror; 2172 break; 2173 } 2174 2175 if (ShOp == ARM_AM::ror && imm == 0) 2176 ShOp = ARM_AM::rrx; 2177 2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2181 return MCDisassembler::Fail; 2182 unsigned shift; 2183 if (U) 2184 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2185 else 2186 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2187 Inst.addOperand(MCOperand::createImm(shift)); 2188 2189 return S; 2190 } 2191 2192 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2193 uint64_t Address, 2194 const MCDisassembler *Decoder) { 2195 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2196 return MCDisassembler::Fail; 2197 2198 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2199 // the only available operand), but LLVM expects the instruction to have one 2200 // operand, so we need to add the csync when decoding. 2201 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2202 return MCDisassembler::Success; 2203 } 2204 2205 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2206 uint64_t Address, 2207 const MCDisassembler *Decoder) { 2208 DecodeStatus S = MCDisassembler::Success; 2209 2210 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2211 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2212 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2213 unsigned type = fieldFromInstruction(Insn, 22, 1); 2214 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2215 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2216 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2217 unsigned W = fieldFromInstruction(Insn, 21, 1); 2218 unsigned P = fieldFromInstruction(Insn, 24, 1); 2219 unsigned Rt2 = Rt + 1; 2220 2221 bool writeback = (W == 1) | (P == 0); 2222 2223 // For {LD,ST}RD, Rt must be even, else undefined. 2224 switch (Inst.getOpcode()) { 2225 case ARM::STRD: 2226 case ARM::STRD_PRE: 2227 case ARM::STRD_POST: 2228 case ARM::LDRD: 2229 case ARM::LDRD_PRE: 2230 case ARM::LDRD_POST: 2231 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2232 break; 2233 default: 2234 break; 2235 } 2236 switch (Inst.getOpcode()) { 2237 case ARM::STRD: 2238 case ARM::STRD_PRE: 2239 case ARM::STRD_POST: 2240 if (P == 0 && W == 1) 2241 S = MCDisassembler::SoftFail; 2242 2243 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2244 S = MCDisassembler::SoftFail; 2245 if (type && Rm == 15) 2246 S = MCDisassembler::SoftFail; 2247 if (Rt2 == 15) 2248 S = MCDisassembler::SoftFail; 2249 if (!type && fieldFromInstruction(Insn, 8, 4)) 2250 S = MCDisassembler::SoftFail; 2251 break; 2252 case ARM::STRH: 2253 case ARM::STRH_PRE: 2254 case ARM::STRH_POST: 2255 if (Rt == 15) 2256 S = MCDisassembler::SoftFail; 2257 if (writeback && (Rn == 15 || Rn == Rt)) 2258 S = MCDisassembler::SoftFail; 2259 if (!type && Rm == 15) 2260 S = MCDisassembler::SoftFail; 2261 break; 2262 case ARM::LDRD: 2263 case ARM::LDRD_PRE: 2264 case ARM::LDRD_POST: 2265 if (type && Rn == 15) { 2266 if (Rt2 == 15) 2267 S = MCDisassembler::SoftFail; 2268 break; 2269 } 2270 if (P == 0 && W == 1) 2271 S = MCDisassembler::SoftFail; 2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2273 S = MCDisassembler::SoftFail; 2274 if (!type && writeback && Rn == 15) 2275 S = MCDisassembler::SoftFail; 2276 if (writeback && (Rn == Rt || Rn == Rt2)) 2277 S = MCDisassembler::SoftFail; 2278 break; 2279 case ARM::LDRH: 2280 case ARM::LDRH_PRE: 2281 case ARM::LDRH_POST: 2282 if (type && Rn == 15) { 2283 if (Rt == 15) 2284 S = MCDisassembler::SoftFail; 2285 break; 2286 } 2287 if (Rt == 15) 2288 S = MCDisassembler::SoftFail; 2289 if (!type && Rm == 15) 2290 S = MCDisassembler::SoftFail; 2291 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2292 S = MCDisassembler::SoftFail; 2293 break; 2294 case ARM::LDRSH: 2295 case ARM::LDRSH_PRE: 2296 case ARM::LDRSH_POST: 2297 case ARM::LDRSB: 2298 case ARM::LDRSB_PRE: 2299 case ARM::LDRSB_POST: 2300 if (type && Rn == 15) { 2301 if (Rt == 15) 2302 S = MCDisassembler::SoftFail; 2303 break; 2304 } 2305 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2306 S = MCDisassembler::SoftFail; 2307 if (!type && (Rt == 15 || Rm == 15)) 2308 S = MCDisassembler::SoftFail; 2309 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2310 S = MCDisassembler::SoftFail; 2311 break; 2312 default: 2313 break; 2314 } 2315 2316 if (writeback) { // Writeback 2317 if (P) 2318 U |= ARMII::IndexModePre << 9; 2319 else 2320 U |= ARMII::IndexModePost << 9; 2321 2322 // On stores, the writeback operand precedes Rt. 2323 switch (Inst.getOpcode()) { 2324 case ARM::STRD: 2325 case ARM::STRD_PRE: 2326 case ARM::STRD_POST: 2327 case ARM::STRH: 2328 case ARM::STRH_PRE: 2329 case ARM::STRH_POST: 2330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2331 return MCDisassembler::Fail; 2332 break; 2333 default: 2334 break; 2335 } 2336 } 2337 2338 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2339 return MCDisassembler::Fail; 2340 switch (Inst.getOpcode()) { 2341 case ARM::STRD: 2342 case ARM::STRD_PRE: 2343 case ARM::STRD_POST: 2344 case ARM::LDRD: 2345 case ARM::LDRD_PRE: 2346 case ARM::LDRD_POST: 2347 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2348 return MCDisassembler::Fail; 2349 break; 2350 default: 2351 break; 2352 } 2353 2354 if (writeback) { 2355 // On loads, the writeback operand comes after Rt. 2356 switch (Inst.getOpcode()) { 2357 case ARM::LDRD: 2358 case ARM::LDRD_PRE: 2359 case ARM::LDRD_POST: 2360 case ARM::LDRH: 2361 case ARM::LDRH_PRE: 2362 case ARM::LDRH_POST: 2363 case ARM::LDRSH: 2364 case ARM::LDRSH_PRE: 2365 case ARM::LDRSH_POST: 2366 case ARM::LDRSB: 2367 case ARM::LDRSB_PRE: 2368 case ARM::LDRSB_POST: 2369 case ARM::LDRHTr: 2370 case ARM::LDRSBTr: 2371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2372 return MCDisassembler::Fail; 2373 break; 2374 default: 2375 break; 2376 } 2377 } 2378 2379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2380 return MCDisassembler::Fail; 2381 2382 if (type) { 2383 Inst.addOperand(MCOperand::createReg(0)); 2384 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2385 } else { 2386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2387 return MCDisassembler::Fail; 2388 Inst.addOperand(MCOperand::createImm(U)); 2389 } 2390 2391 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2392 return MCDisassembler::Fail; 2393 2394 return S; 2395 } 2396 2397 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2398 uint64_t Address, 2399 const MCDisassembler *Decoder) { 2400 DecodeStatus S = MCDisassembler::Success; 2401 2402 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2403 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2404 2405 switch (mode) { 2406 case 0: 2407 mode = ARM_AM::da; 2408 break; 2409 case 1: 2410 mode = ARM_AM::ia; 2411 break; 2412 case 2: 2413 mode = ARM_AM::db; 2414 break; 2415 case 3: 2416 mode = ARM_AM::ib; 2417 break; 2418 } 2419 2420 Inst.addOperand(MCOperand::createImm(mode)); 2421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2422 return MCDisassembler::Fail; 2423 2424 return S; 2425 } 2426 2427 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2428 uint64_t Address, 2429 const MCDisassembler *Decoder) { 2430 DecodeStatus S = MCDisassembler::Success; 2431 2432 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2433 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2434 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2435 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2436 2437 if (pred == 0xF) 2438 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2439 2440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2445 return MCDisassembler::Fail; 2446 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 return S; 2449 } 2450 2451 static DecodeStatus 2452 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2453 uint64_t Address, 2454 const MCDisassembler *Decoder) { 2455 DecodeStatus S = MCDisassembler::Success; 2456 2457 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2458 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2459 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2460 2461 if (pred == 0xF) { 2462 // Ambiguous with RFE and SRS 2463 switch (Inst.getOpcode()) { 2464 case ARM::LDMDA: 2465 Inst.setOpcode(ARM::RFEDA); 2466 break; 2467 case ARM::LDMDA_UPD: 2468 Inst.setOpcode(ARM::RFEDA_UPD); 2469 break; 2470 case ARM::LDMDB: 2471 Inst.setOpcode(ARM::RFEDB); 2472 break; 2473 case ARM::LDMDB_UPD: 2474 Inst.setOpcode(ARM::RFEDB_UPD); 2475 break; 2476 case ARM::LDMIA: 2477 Inst.setOpcode(ARM::RFEIA); 2478 break; 2479 case ARM::LDMIA_UPD: 2480 Inst.setOpcode(ARM::RFEIA_UPD); 2481 break; 2482 case ARM::LDMIB: 2483 Inst.setOpcode(ARM::RFEIB); 2484 break; 2485 case ARM::LDMIB_UPD: 2486 Inst.setOpcode(ARM::RFEIB_UPD); 2487 break; 2488 case ARM::STMDA: 2489 Inst.setOpcode(ARM::SRSDA); 2490 break; 2491 case ARM::STMDA_UPD: 2492 Inst.setOpcode(ARM::SRSDA_UPD); 2493 break; 2494 case ARM::STMDB: 2495 Inst.setOpcode(ARM::SRSDB); 2496 break; 2497 case ARM::STMDB_UPD: 2498 Inst.setOpcode(ARM::SRSDB_UPD); 2499 break; 2500 case ARM::STMIA: 2501 Inst.setOpcode(ARM::SRSIA); 2502 break; 2503 case ARM::STMIA_UPD: 2504 Inst.setOpcode(ARM::SRSIA_UPD); 2505 break; 2506 case ARM::STMIB: 2507 Inst.setOpcode(ARM::SRSIB); 2508 break; 2509 case ARM::STMIB_UPD: 2510 Inst.setOpcode(ARM::SRSIB_UPD); 2511 break; 2512 default: 2513 return MCDisassembler::Fail; 2514 } 2515 2516 // For stores (which become SRS's, the only operand is the mode. 2517 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2518 // Check SRS encoding constraints 2519 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2520 fieldFromInstruction(Insn, 20, 1) == 0)) 2521 return MCDisassembler::Fail; 2522 2523 Inst.addOperand( 2524 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2525 return S; 2526 } 2527 2528 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2529 } 2530 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2534 return MCDisassembler::Fail; // Tied 2535 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2538 return MCDisassembler::Fail; 2539 2540 return S; 2541 } 2542 2543 // Check for UNPREDICTABLE predicated ESB instruction 2544 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2545 uint64_t Address, 2546 const MCDisassembler *Decoder) { 2547 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2548 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2549 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2550 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2551 2552 DecodeStatus S = MCDisassembler::Success; 2553 2554 Inst.addOperand(MCOperand::createImm(imm8)); 2555 2556 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2557 return MCDisassembler::Fail; 2558 2559 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2560 // so all predicates should be allowed. 2561 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2562 S = MCDisassembler::SoftFail; 2563 2564 return S; 2565 } 2566 2567 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2568 uint64_t Address, 2569 const MCDisassembler *Decoder) { 2570 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2571 unsigned M = fieldFromInstruction(Insn, 17, 1); 2572 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2573 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2574 2575 DecodeStatus S = MCDisassembler::Success; 2576 2577 // This decoder is called from multiple location that do not check 2578 // the full encoding is valid before they do. 2579 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2580 fieldFromInstruction(Insn, 16, 1) != 0 || 2581 fieldFromInstruction(Insn, 20, 8) != 0x10) 2582 return MCDisassembler::Fail; 2583 2584 // imod == '01' --> UNPREDICTABLE 2585 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2586 // return failure here. The '01' imod value is unprintable, so there's 2587 // nothing useful we could do even if we returned UNPREDICTABLE. 2588 2589 if (imod == 1) return MCDisassembler::Fail; 2590 2591 if (imod && M) { 2592 Inst.setOpcode(ARM::CPS3p); 2593 Inst.addOperand(MCOperand::createImm(imod)); 2594 Inst.addOperand(MCOperand::createImm(iflags)); 2595 Inst.addOperand(MCOperand::createImm(mode)); 2596 } else if (imod && !M) { 2597 Inst.setOpcode(ARM::CPS2p); 2598 Inst.addOperand(MCOperand::createImm(imod)); 2599 Inst.addOperand(MCOperand::createImm(iflags)); 2600 if (mode) S = MCDisassembler::SoftFail; 2601 } else if (!imod && M) { 2602 Inst.setOpcode(ARM::CPS1p); 2603 Inst.addOperand(MCOperand::createImm(mode)); 2604 if (iflags) S = MCDisassembler::SoftFail; 2605 } else { 2606 // imod == '00' && M == '0' --> UNPREDICTABLE 2607 Inst.setOpcode(ARM::CPS1p); 2608 Inst.addOperand(MCOperand::createImm(mode)); 2609 S = MCDisassembler::SoftFail; 2610 } 2611 2612 return S; 2613 } 2614 2615 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2616 uint64_t Address, 2617 const MCDisassembler *Decoder) { 2618 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2619 unsigned M = fieldFromInstruction(Insn, 8, 1); 2620 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2621 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2622 2623 DecodeStatus S = MCDisassembler::Success; 2624 2625 // imod == '01' --> UNPREDICTABLE 2626 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2627 // return failure here. The '01' imod value is unprintable, so there's 2628 // nothing useful we could do even if we returned UNPREDICTABLE. 2629 2630 if (imod == 1) return MCDisassembler::Fail; 2631 2632 if (imod && M) { 2633 Inst.setOpcode(ARM::t2CPS3p); 2634 Inst.addOperand(MCOperand::createImm(imod)); 2635 Inst.addOperand(MCOperand::createImm(iflags)); 2636 Inst.addOperand(MCOperand::createImm(mode)); 2637 } else if (imod && !M) { 2638 Inst.setOpcode(ARM::t2CPS2p); 2639 Inst.addOperand(MCOperand::createImm(imod)); 2640 Inst.addOperand(MCOperand::createImm(iflags)); 2641 if (mode) S = MCDisassembler::SoftFail; 2642 } else if (!imod && M) { 2643 Inst.setOpcode(ARM::t2CPS1p); 2644 Inst.addOperand(MCOperand::createImm(mode)); 2645 if (iflags) S = MCDisassembler::SoftFail; 2646 } else { 2647 // imod == '00' && M == '0' --> this is a HINT instruction 2648 int imm = fieldFromInstruction(Insn, 0, 8); 2649 // HINT are defined only for immediate in [0..4] 2650 if(imm > 4) return MCDisassembler::Fail; 2651 Inst.setOpcode(ARM::t2HINT); 2652 Inst.addOperand(MCOperand::createImm(imm)); 2653 } 2654 2655 return S; 2656 } 2657 2658 static DecodeStatus 2659 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2660 const MCDisassembler *Decoder) { 2661 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2662 2663 unsigned Opcode = ARM::t2HINT; 2664 2665 if (imm == 0x0D) { 2666 Opcode = ARM::t2PACBTI; 2667 } else if (imm == 0x1D) { 2668 Opcode = ARM::t2PAC; 2669 } else if (imm == 0x2D) { 2670 Opcode = ARM::t2AUT; 2671 } else if (imm == 0x0F) { 2672 Opcode = ARM::t2BTI; 2673 } 2674 2675 Inst.setOpcode(Opcode); 2676 if (Opcode == ARM::t2HINT) { 2677 Inst.addOperand(MCOperand::createImm(imm)); 2678 } 2679 2680 return MCDisassembler::Success; 2681 } 2682 2683 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2684 uint64_t Address, 2685 const MCDisassembler *Decoder) { 2686 DecodeStatus S = MCDisassembler::Success; 2687 2688 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2689 unsigned imm = 0; 2690 2691 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2692 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2693 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2694 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2695 2696 if (Inst.getOpcode() == ARM::t2MOVTi16) 2697 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2698 return MCDisassembler::Fail; 2699 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2700 return MCDisassembler::Fail; 2701 2702 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2703 Inst.addOperand(MCOperand::createImm(imm)); 2704 2705 return S; 2706 } 2707 2708 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2709 uint64_t Address, 2710 const MCDisassembler *Decoder) { 2711 DecodeStatus S = MCDisassembler::Success; 2712 2713 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2714 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2715 unsigned imm = 0; 2716 2717 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2718 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2719 2720 if (Inst.getOpcode() == ARM::MOVTi16) 2721 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 2724 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 2727 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2728 Inst.addOperand(MCOperand::createImm(imm)); 2729 2730 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 2733 return S; 2734 } 2735 2736 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2737 uint64_t Address, 2738 const MCDisassembler *Decoder) { 2739 DecodeStatus S = MCDisassembler::Success; 2740 2741 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2742 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2743 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2744 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2745 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2746 2747 if (pred == 0xF) 2748 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2749 2750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2755 return MCDisassembler::Fail; 2756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 2759 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2760 return MCDisassembler::Fail; 2761 2762 return S; 2763 } 2764 2765 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2766 uint64_t Address, 2767 const MCDisassembler *Decoder) { 2768 DecodeStatus S = MCDisassembler::Success; 2769 2770 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2771 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2772 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2773 2774 if (Pred == 0xF) 2775 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2776 2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2782 return MCDisassembler::Fail; 2783 2784 return S; 2785 } 2786 2787 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2788 uint64_t Address, 2789 const MCDisassembler *Decoder) { 2790 DecodeStatus S = MCDisassembler::Success; 2791 2792 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2793 2794 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2795 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2796 2797 if (!FeatureBits[ARM::HasV8_1aOps] || 2798 !FeatureBits[ARM::HasV8Ops]) 2799 return MCDisassembler::Fail; 2800 2801 // Decoder can be called from DecodeTST, which does not check the full 2802 // encoding is valid. 2803 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2804 fieldFromInstruction(Insn, 4,4) != 0) 2805 return MCDisassembler::Fail; 2806 if (fieldFromInstruction(Insn, 10,10) != 0 || 2807 fieldFromInstruction(Insn, 0,4) != 0) 2808 S = MCDisassembler::SoftFail; 2809 2810 Inst.setOpcode(ARM::SETPAN); 2811 Inst.addOperand(MCOperand::createImm(Imm)); 2812 2813 return S; 2814 } 2815 2816 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2817 uint64_t Address, 2818 const MCDisassembler *Decoder) { 2819 DecodeStatus S = MCDisassembler::Success; 2820 2821 unsigned add = fieldFromInstruction(Val, 12, 1); 2822 unsigned imm = fieldFromInstruction(Val, 0, 12); 2823 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2824 2825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2826 return MCDisassembler::Fail; 2827 2828 if (!add) imm *= -1; 2829 if (imm == 0 && !add) imm = INT32_MIN; 2830 Inst.addOperand(MCOperand::createImm(imm)); 2831 if (Rn == 15) 2832 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2833 2834 return S; 2835 } 2836 2837 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2838 uint64_t Address, 2839 const MCDisassembler *Decoder) { 2840 DecodeStatus S = MCDisassembler::Success; 2841 2842 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2843 // U == 1 to add imm, 0 to subtract it. 2844 unsigned U = fieldFromInstruction(Val, 8, 1); 2845 unsigned imm = fieldFromInstruction(Val, 0, 8); 2846 2847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2848 return MCDisassembler::Fail; 2849 2850 if (U) 2851 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2852 else 2853 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2854 2855 return S; 2856 } 2857 2858 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2859 uint64_t Address, 2860 const MCDisassembler *Decoder) { 2861 DecodeStatus S = MCDisassembler::Success; 2862 2863 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2864 // U == 1 to add imm, 0 to subtract it. 2865 unsigned U = fieldFromInstruction(Val, 8, 1); 2866 unsigned imm = fieldFromInstruction(Val, 0, 8); 2867 2868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2869 return MCDisassembler::Fail; 2870 2871 if (U) 2872 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2873 else 2874 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2875 2876 return S; 2877 } 2878 2879 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2880 uint64_t Address, 2881 const MCDisassembler *Decoder) { 2882 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2883 } 2884 2885 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2886 uint64_t Address, 2887 const MCDisassembler *Decoder) { 2888 DecodeStatus Status = MCDisassembler::Success; 2889 2890 // Note the J1 and J2 values are from the encoded instruction. So here 2891 // change them to I1 and I2 values via as documented: 2892 // I1 = NOT(J1 EOR S); 2893 // I2 = NOT(J2 EOR S); 2894 // and build the imm32 with one trailing zero as documented: 2895 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2896 unsigned S = fieldFromInstruction(Insn, 26, 1); 2897 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2898 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2899 unsigned I1 = !(J1 ^ S); 2900 unsigned I2 = !(J2 ^ S); 2901 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2902 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2903 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2904 int imm32 = SignExtend32<25>(tmp << 1); 2905 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2906 true, 4, Inst, Decoder)) 2907 Inst.addOperand(MCOperand::createImm(imm32)); 2908 2909 return Status; 2910 } 2911 2912 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2913 uint64_t Address, 2914 const MCDisassembler *Decoder) { 2915 DecodeStatus S = MCDisassembler::Success; 2916 2917 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2918 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2919 2920 if (pred == 0xF) { 2921 Inst.setOpcode(ARM::BLXi); 2922 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2923 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2924 true, 4, Inst, Decoder)) 2925 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2926 return S; 2927 } 2928 2929 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2930 true, 4, Inst, Decoder)) 2931 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2932 2933 // We already have BL_pred for BL w/ predicate, no need to add addition 2934 // predicate opreands for BL 2935 if (Inst.getOpcode() != ARM::BL) 2936 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2937 return MCDisassembler::Fail; 2938 2939 return S; 2940 } 2941 2942 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2943 uint64_t Address, 2944 const MCDisassembler *Decoder) { 2945 DecodeStatus S = MCDisassembler::Success; 2946 2947 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2948 unsigned align = fieldFromInstruction(Val, 4, 2); 2949 2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2951 return MCDisassembler::Fail; 2952 if (!align) 2953 Inst.addOperand(MCOperand::createImm(0)); 2954 else 2955 Inst.addOperand(MCOperand::createImm(4 << align)); 2956 2957 return S; 2958 } 2959 2960 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2961 uint64_t Address, 2962 const MCDisassembler *Decoder) { 2963 DecodeStatus S = MCDisassembler::Success; 2964 2965 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2966 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2967 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2968 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2969 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2971 2972 // First output register 2973 switch (Inst.getOpcode()) { 2974 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2975 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2976 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2977 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2978 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2979 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2980 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2981 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2982 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2983 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2984 return MCDisassembler::Fail; 2985 break; 2986 case ARM::VLD2b16: 2987 case ARM::VLD2b32: 2988 case ARM::VLD2b8: 2989 case ARM::VLD2b16wb_fixed: 2990 case ARM::VLD2b16wb_register: 2991 case ARM::VLD2b32wb_fixed: 2992 case ARM::VLD2b32wb_register: 2993 case ARM::VLD2b8wb_fixed: 2994 case ARM::VLD2b8wb_register: 2995 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2996 return MCDisassembler::Fail; 2997 break; 2998 default: 2999 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3000 return MCDisassembler::Fail; 3001 } 3002 3003 // Second output register 3004 switch (Inst.getOpcode()) { 3005 case ARM::VLD3d8: 3006 case ARM::VLD3d16: 3007 case ARM::VLD3d32: 3008 case ARM::VLD3d8_UPD: 3009 case ARM::VLD3d16_UPD: 3010 case ARM::VLD3d32_UPD: 3011 case ARM::VLD4d8: 3012 case ARM::VLD4d16: 3013 case ARM::VLD4d32: 3014 case ARM::VLD4d8_UPD: 3015 case ARM::VLD4d16_UPD: 3016 case ARM::VLD4d32_UPD: 3017 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3018 return MCDisassembler::Fail; 3019 break; 3020 case ARM::VLD3q8: 3021 case ARM::VLD3q16: 3022 case ARM::VLD3q32: 3023 case ARM::VLD3q8_UPD: 3024 case ARM::VLD3q16_UPD: 3025 case ARM::VLD3q32_UPD: 3026 case ARM::VLD4q8: 3027 case ARM::VLD4q16: 3028 case ARM::VLD4q32: 3029 case ARM::VLD4q8_UPD: 3030 case ARM::VLD4q16_UPD: 3031 case ARM::VLD4q32_UPD: 3032 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3033 return MCDisassembler::Fail; 3034 break; 3035 default: 3036 break; 3037 } 3038 3039 // Third output register 3040 switch(Inst.getOpcode()) { 3041 case ARM::VLD3d8: 3042 case ARM::VLD3d16: 3043 case ARM::VLD3d32: 3044 case ARM::VLD3d8_UPD: 3045 case ARM::VLD3d16_UPD: 3046 case ARM::VLD3d32_UPD: 3047 case ARM::VLD4d8: 3048 case ARM::VLD4d16: 3049 case ARM::VLD4d32: 3050 case ARM::VLD4d8_UPD: 3051 case ARM::VLD4d16_UPD: 3052 case ARM::VLD4d32_UPD: 3053 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3054 return MCDisassembler::Fail; 3055 break; 3056 case ARM::VLD3q8: 3057 case ARM::VLD3q16: 3058 case ARM::VLD3q32: 3059 case ARM::VLD3q8_UPD: 3060 case ARM::VLD3q16_UPD: 3061 case ARM::VLD3q32_UPD: 3062 case ARM::VLD4q8: 3063 case ARM::VLD4q16: 3064 case ARM::VLD4q32: 3065 case ARM::VLD4q8_UPD: 3066 case ARM::VLD4q16_UPD: 3067 case ARM::VLD4q32_UPD: 3068 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3069 return MCDisassembler::Fail; 3070 break; 3071 default: 3072 break; 3073 } 3074 3075 // Fourth output register 3076 switch (Inst.getOpcode()) { 3077 case ARM::VLD4d8: 3078 case ARM::VLD4d16: 3079 case ARM::VLD4d32: 3080 case ARM::VLD4d8_UPD: 3081 case ARM::VLD4d16_UPD: 3082 case ARM::VLD4d32_UPD: 3083 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3084 return MCDisassembler::Fail; 3085 break; 3086 case ARM::VLD4q8: 3087 case ARM::VLD4q16: 3088 case ARM::VLD4q32: 3089 case ARM::VLD4q8_UPD: 3090 case ARM::VLD4q16_UPD: 3091 case ARM::VLD4q32_UPD: 3092 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3093 return MCDisassembler::Fail; 3094 break; 3095 default: 3096 break; 3097 } 3098 3099 // Writeback operand 3100 switch (Inst.getOpcode()) { 3101 case ARM::VLD1d8wb_fixed: 3102 case ARM::VLD1d16wb_fixed: 3103 case ARM::VLD1d32wb_fixed: 3104 case ARM::VLD1d64wb_fixed: 3105 case ARM::VLD1d8wb_register: 3106 case ARM::VLD1d16wb_register: 3107 case ARM::VLD1d32wb_register: 3108 case ARM::VLD1d64wb_register: 3109 case ARM::VLD1q8wb_fixed: 3110 case ARM::VLD1q16wb_fixed: 3111 case ARM::VLD1q32wb_fixed: 3112 case ARM::VLD1q64wb_fixed: 3113 case ARM::VLD1q8wb_register: 3114 case ARM::VLD1q16wb_register: 3115 case ARM::VLD1q32wb_register: 3116 case ARM::VLD1q64wb_register: 3117 case ARM::VLD1d8Twb_fixed: 3118 case ARM::VLD1d8Twb_register: 3119 case ARM::VLD1d16Twb_fixed: 3120 case ARM::VLD1d16Twb_register: 3121 case ARM::VLD1d32Twb_fixed: 3122 case ARM::VLD1d32Twb_register: 3123 case ARM::VLD1d64Twb_fixed: 3124 case ARM::VLD1d64Twb_register: 3125 case ARM::VLD1d8Qwb_fixed: 3126 case ARM::VLD1d8Qwb_register: 3127 case ARM::VLD1d16Qwb_fixed: 3128 case ARM::VLD1d16Qwb_register: 3129 case ARM::VLD1d32Qwb_fixed: 3130 case ARM::VLD1d32Qwb_register: 3131 case ARM::VLD1d64Qwb_fixed: 3132 case ARM::VLD1d64Qwb_register: 3133 case ARM::VLD2d8wb_fixed: 3134 case ARM::VLD2d16wb_fixed: 3135 case ARM::VLD2d32wb_fixed: 3136 case ARM::VLD2q8wb_fixed: 3137 case ARM::VLD2q16wb_fixed: 3138 case ARM::VLD2q32wb_fixed: 3139 case ARM::VLD2d8wb_register: 3140 case ARM::VLD2d16wb_register: 3141 case ARM::VLD2d32wb_register: 3142 case ARM::VLD2q8wb_register: 3143 case ARM::VLD2q16wb_register: 3144 case ARM::VLD2q32wb_register: 3145 case ARM::VLD2b8wb_fixed: 3146 case ARM::VLD2b16wb_fixed: 3147 case ARM::VLD2b32wb_fixed: 3148 case ARM::VLD2b8wb_register: 3149 case ARM::VLD2b16wb_register: 3150 case ARM::VLD2b32wb_register: 3151 Inst.addOperand(MCOperand::createImm(0)); 3152 break; 3153 case ARM::VLD3d8_UPD: 3154 case ARM::VLD3d16_UPD: 3155 case ARM::VLD3d32_UPD: 3156 case ARM::VLD3q8_UPD: 3157 case ARM::VLD3q16_UPD: 3158 case ARM::VLD3q32_UPD: 3159 case ARM::VLD4d8_UPD: 3160 case ARM::VLD4d16_UPD: 3161 case ARM::VLD4d32_UPD: 3162 case ARM::VLD4q8_UPD: 3163 case ARM::VLD4q16_UPD: 3164 case ARM::VLD4q32_UPD: 3165 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3166 return MCDisassembler::Fail; 3167 break; 3168 default: 3169 break; 3170 } 3171 3172 // AddrMode6 Base (register+alignment) 3173 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3174 return MCDisassembler::Fail; 3175 3176 // AddrMode6 Offset (register) 3177 switch (Inst.getOpcode()) { 3178 default: 3179 // The below have been updated to have explicit am6offset split 3180 // between fixed and register offset. For those instructions not 3181 // yet updated, we need to add an additional reg0 operand for the 3182 // fixed variant. 3183 // 3184 // The fixed offset encodes as Rm == 0xd, so we check for that. 3185 if (Rm == 0xd) { 3186 Inst.addOperand(MCOperand::createReg(0)); 3187 break; 3188 } 3189 // Fall through to handle the register offset variant. 3190 [[fallthrough]]; 3191 case ARM::VLD1d8wb_fixed: 3192 case ARM::VLD1d16wb_fixed: 3193 case ARM::VLD1d32wb_fixed: 3194 case ARM::VLD1d64wb_fixed: 3195 case ARM::VLD1d8Twb_fixed: 3196 case ARM::VLD1d16Twb_fixed: 3197 case ARM::VLD1d32Twb_fixed: 3198 case ARM::VLD1d64Twb_fixed: 3199 case ARM::VLD1d8Qwb_fixed: 3200 case ARM::VLD1d16Qwb_fixed: 3201 case ARM::VLD1d32Qwb_fixed: 3202 case ARM::VLD1d64Qwb_fixed: 3203 case ARM::VLD1d8wb_register: 3204 case ARM::VLD1d16wb_register: 3205 case ARM::VLD1d32wb_register: 3206 case ARM::VLD1d64wb_register: 3207 case ARM::VLD1q8wb_fixed: 3208 case ARM::VLD1q16wb_fixed: 3209 case ARM::VLD1q32wb_fixed: 3210 case ARM::VLD1q64wb_fixed: 3211 case ARM::VLD1q8wb_register: 3212 case ARM::VLD1q16wb_register: 3213 case ARM::VLD1q32wb_register: 3214 case ARM::VLD1q64wb_register: 3215 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3216 // variant encodes Rm == 0xf. Anything else is a register offset post- 3217 // increment and we need to add the register operand to the instruction. 3218 if (Rm != 0xD && Rm != 0xF && 3219 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3220 return MCDisassembler::Fail; 3221 break; 3222 case ARM::VLD2d8wb_fixed: 3223 case ARM::VLD2d16wb_fixed: 3224 case ARM::VLD2d32wb_fixed: 3225 case ARM::VLD2b8wb_fixed: 3226 case ARM::VLD2b16wb_fixed: 3227 case ARM::VLD2b32wb_fixed: 3228 case ARM::VLD2q8wb_fixed: 3229 case ARM::VLD2q16wb_fixed: 3230 case ARM::VLD2q32wb_fixed: 3231 break; 3232 } 3233 3234 return S; 3235 } 3236 3237 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3238 uint64_t Address, 3239 const MCDisassembler *Decoder) { 3240 unsigned type = fieldFromInstruction(Insn, 8, 4); 3241 unsigned align = fieldFromInstruction(Insn, 4, 2); 3242 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3243 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3244 if (type == 10 && align == 3) return MCDisassembler::Fail; 3245 3246 unsigned load = fieldFromInstruction(Insn, 21, 1); 3247 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3248 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3249 } 3250 3251 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3252 uint64_t Address, 3253 const MCDisassembler *Decoder) { 3254 unsigned size = fieldFromInstruction(Insn, 6, 2); 3255 if (size == 3) return MCDisassembler::Fail; 3256 3257 unsigned type = fieldFromInstruction(Insn, 8, 4); 3258 unsigned align = fieldFromInstruction(Insn, 4, 2); 3259 if (type == 8 && align == 3) return MCDisassembler::Fail; 3260 if (type == 9 && align == 3) return MCDisassembler::Fail; 3261 3262 unsigned load = fieldFromInstruction(Insn, 21, 1); 3263 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3264 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3265 } 3266 3267 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3268 uint64_t Address, 3269 const MCDisassembler *Decoder) { 3270 unsigned size = fieldFromInstruction(Insn, 6, 2); 3271 if (size == 3) return MCDisassembler::Fail; 3272 3273 unsigned align = fieldFromInstruction(Insn, 4, 2); 3274 if (align & 2) return MCDisassembler::Fail; 3275 3276 unsigned load = fieldFromInstruction(Insn, 21, 1); 3277 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3278 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3279 } 3280 3281 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3282 uint64_t Address, 3283 const MCDisassembler *Decoder) { 3284 unsigned size = fieldFromInstruction(Insn, 6, 2); 3285 if (size == 3) return MCDisassembler::Fail; 3286 3287 unsigned load = fieldFromInstruction(Insn, 21, 1); 3288 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3289 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3290 } 3291 3292 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3293 uint64_t Address, 3294 const MCDisassembler *Decoder) { 3295 DecodeStatus S = MCDisassembler::Success; 3296 3297 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3298 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3299 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3300 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3301 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3302 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3303 3304 // Writeback Operand 3305 switch (Inst.getOpcode()) { 3306 case ARM::VST1d8wb_fixed: 3307 case ARM::VST1d16wb_fixed: 3308 case ARM::VST1d32wb_fixed: 3309 case ARM::VST1d64wb_fixed: 3310 case ARM::VST1d8wb_register: 3311 case ARM::VST1d16wb_register: 3312 case ARM::VST1d32wb_register: 3313 case ARM::VST1d64wb_register: 3314 case ARM::VST1q8wb_fixed: 3315 case ARM::VST1q16wb_fixed: 3316 case ARM::VST1q32wb_fixed: 3317 case ARM::VST1q64wb_fixed: 3318 case ARM::VST1q8wb_register: 3319 case ARM::VST1q16wb_register: 3320 case ARM::VST1q32wb_register: 3321 case ARM::VST1q64wb_register: 3322 case ARM::VST1d8Twb_fixed: 3323 case ARM::VST1d16Twb_fixed: 3324 case ARM::VST1d32Twb_fixed: 3325 case ARM::VST1d64Twb_fixed: 3326 case ARM::VST1d8Twb_register: 3327 case ARM::VST1d16Twb_register: 3328 case ARM::VST1d32Twb_register: 3329 case ARM::VST1d64Twb_register: 3330 case ARM::VST1d8Qwb_fixed: 3331 case ARM::VST1d16Qwb_fixed: 3332 case ARM::VST1d32Qwb_fixed: 3333 case ARM::VST1d64Qwb_fixed: 3334 case ARM::VST1d8Qwb_register: 3335 case ARM::VST1d16Qwb_register: 3336 case ARM::VST1d32Qwb_register: 3337 case ARM::VST1d64Qwb_register: 3338 case ARM::VST2d8wb_fixed: 3339 case ARM::VST2d16wb_fixed: 3340 case ARM::VST2d32wb_fixed: 3341 case ARM::VST2d8wb_register: 3342 case ARM::VST2d16wb_register: 3343 case ARM::VST2d32wb_register: 3344 case ARM::VST2q8wb_fixed: 3345 case ARM::VST2q16wb_fixed: 3346 case ARM::VST2q32wb_fixed: 3347 case ARM::VST2q8wb_register: 3348 case ARM::VST2q16wb_register: 3349 case ARM::VST2q32wb_register: 3350 case ARM::VST2b8wb_fixed: 3351 case ARM::VST2b16wb_fixed: 3352 case ARM::VST2b32wb_fixed: 3353 case ARM::VST2b8wb_register: 3354 case ARM::VST2b16wb_register: 3355 case ARM::VST2b32wb_register: 3356 if (Rm == 0xF) 3357 return MCDisassembler::Fail; 3358 Inst.addOperand(MCOperand::createImm(0)); 3359 break; 3360 case ARM::VST3d8_UPD: 3361 case ARM::VST3d16_UPD: 3362 case ARM::VST3d32_UPD: 3363 case ARM::VST3q8_UPD: 3364 case ARM::VST3q16_UPD: 3365 case ARM::VST3q32_UPD: 3366 case ARM::VST4d8_UPD: 3367 case ARM::VST4d16_UPD: 3368 case ARM::VST4d32_UPD: 3369 case ARM::VST4q8_UPD: 3370 case ARM::VST4q16_UPD: 3371 case ARM::VST4q32_UPD: 3372 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 break; 3375 default: 3376 break; 3377 } 3378 3379 // AddrMode6 Base (register+alignment) 3380 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3381 return MCDisassembler::Fail; 3382 3383 // AddrMode6 Offset (register) 3384 switch (Inst.getOpcode()) { 3385 default: 3386 if (Rm == 0xD) 3387 Inst.addOperand(MCOperand::createReg(0)); 3388 else if (Rm != 0xF) { 3389 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3390 return MCDisassembler::Fail; 3391 } 3392 break; 3393 case ARM::VST1d8wb_fixed: 3394 case ARM::VST1d16wb_fixed: 3395 case ARM::VST1d32wb_fixed: 3396 case ARM::VST1d64wb_fixed: 3397 case ARM::VST1q8wb_fixed: 3398 case ARM::VST1q16wb_fixed: 3399 case ARM::VST1q32wb_fixed: 3400 case ARM::VST1q64wb_fixed: 3401 case ARM::VST1d8Twb_fixed: 3402 case ARM::VST1d16Twb_fixed: 3403 case ARM::VST1d32Twb_fixed: 3404 case ARM::VST1d64Twb_fixed: 3405 case ARM::VST1d8Qwb_fixed: 3406 case ARM::VST1d16Qwb_fixed: 3407 case ARM::VST1d32Qwb_fixed: 3408 case ARM::VST1d64Qwb_fixed: 3409 case ARM::VST2d8wb_fixed: 3410 case ARM::VST2d16wb_fixed: 3411 case ARM::VST2d32wb_fixed: 3412 case ARM::VST2q8wb_fixed: 3413 case ARM::VST2q16wb_fixed: 3414 case ARM::VST2q32wb_fixed: 3415 case ARM::VST2b8wb_fixed: 3416 case ARM::VST2b16wb_fixed: 3417 case ARM::VST2b32wb_fixed: 3418 break; 3419 } 3420 3421 // First input register 3422 switch (Inst.getOpcode()) { 3423 case ARM::VST1q16: 3424 case ARM::VST1q32: 3425 case ARM::VST1q64: 3426 case ARM::VST1q8: 3427 case ARM::VST1q16wb_fixed: 3428 case ARM::VST1q16wb_register: 3429 case ARM::VST1q32wb_fixed: 3430 case ARM::VST1q32wb_register: 3431 case ARM::VST1q64wb_fixed: 3432 case ARM::VST1q64wb_register: 3433 case ARM::VST1q8wb_fixed: 3434 case ARM::VST1q8wb_register: 3435 case ARM::VST2d16: 3436 case ARM::VST2d32: 3437 case ARM::VST2d8: 3438 case ARM::VST2d16wb_fixed: 3439 case ARM::VST2d16wb_register: 3440 case ARM::VST2d32wb_fixed: 3441 case ARM::VST2d32wb_register: 3442 case ARM::VST2d8wb_fixed: 3443 case ARM::VST2d8wb_register: 3444 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3445 return MCDisassembler::Fail; 3446 break; 3447 case ARM::VST2b16: 3448 case ARM::VST2b32: 3449 case ARM::VST2b8: 3450 case ARM::VST2b16wb_fixed: 3451 case ARM::VST2b16wb_register: 3452 case ARM::VST2b32wb_fixed: 3453 case ARM::VST2b32wb_register: 3454 case ARM::VST2b8wb_fixed: 3455 case ARM::VST2b8wb_register: 3456 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 break; 3459 default: 3460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 } 3463 3464 // Second input register 3465 switch (Inst.getOpcode()) { 3466 case ARM::VST3d8: 3467 case ARM::VST3d16: 3468 case ARM::VST3d32: 3469 case ARM::VST3d8_UPD: 3470 case ARM::VST3d16_UPD: 3471 case ARM::VST3d32_UPD: 3472 case ARM::VST4d8: 3473 case ARM::VST4d16: 3474 case ARM::VST4d32: 3475 case ARM::VST4d8_UPD: 3476 case ARM::VST4d16_UPD: 3477 case ARM::VST4d32_UPD: 3478 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 break; 3481 case ARM::VST3q8: 3482 case ARM::VST3q16: 3483 case ARM::VST3q32: 3484 case ARM::VST3q8_UPD: 3485 case ARM::VST3q16_UPD: 3486 case ARM::VST3q32_UPD: 3487 case ARM::VST4q8: 3488 case ARM::VST4q16: 3489 case ARM::VST4q32: 3490 case ARM::VST4q8_UPD: 3491 case ARM::VST4q16_UPD: 3492 case ARM::VST4q32_UPD: 3493 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3494 return MCDisassembler::Fail; 3495 break; 3496 default: 3497 break; 3498 } 3499 3500 // Third input register 3501 switch (Inst.getOpcode()) { 3502 case ARM::VST3d8: 3503 case ARM::VST3d16: 3504 case ARM::VST3d32: 3505 case ARM::VST3d8_UPD: 3506 case ARM::VST3d16_UPD: 3507 case ARM::VST3d32_UPD: 3508 case ARM::VST4d8: 3509 case ARM::VST4d16: 3510 case ARM::VST4d32: 3511 case ARM::VST4d8_UPD: 3512 case ARM::VST4d16_UPD: 3513 case ARM::VST4d32_UPD: 3514 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3515 return MCDisassembler::Fail; 3516 break; 3517 case ARM::VST3q8: 3518 case ARM::VST3q16: 3519 case ARM::VST3q32: 3520 case ARM::VST3q8_UPD: 3521 case ARM::VST3q16_UPD: 3522 case ARM::VST3q32_UPD: 3523 case ARM::VST4q8: 3524 case ARM::VST4q16: 3525 case ARM::VST4q32: 3526 case ARM::VST4q8_UPD: 3527 case ARM::VST4q16_UPD: 3528 case ARM::VST4q32_UPD: 3529 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3530 return MCDisassembler::Fail; 3531 break; 3532 default: 3533 break; 3534 } 3535 3536 // Fourth input register 3537 switch (Inst.getOpcode()) { 3538 case ARM::VST4d8: 3539 case ARM::VST4d16: 3540 case ARM::VST4d32: 3541 case ARM::VST4d8_UPD: 3542 case ARM::VST4d16_UPD: 3543 case ARM::VST4d32_UPD: 3544 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 break; 3547 case ARM::VST4q8: 3548 case ARM::VST4q16: 3549 case ARM::VST4q32: 3550 case ARM::VST4q8_UPD: 3551 case ARM::VST4q16_UPD: 3552 case ARM::VST4q32_UPD: 3553 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3554 return MCDisassembler::Fail; 3555 break; 3556 default: 3557 break; 3558 } 3559 3560 return S; 3561 } 3562 3563 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3564 uint64_t Address, 3565 const MCDisassembler *Decoder) { 3566 DecodeStatus S = MCDisassembler::Success; 3567 3568 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3569 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3570 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3571 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3572 unsigned align = fieldFromInstruction(Insn, 4, 1); 3573 unsigned size = fieldFromInstruction(Insn, 6, 2); 3574 3575 if (size == 0 && align == 1) 3576 return MCDisassembler::Fail; 3577 align *= (1 << size); 3578 3579 switch (Inst.getOpcode()) { 3580 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3581 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3582 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3583 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3584 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3585 return MCDisassembler::Fail; 3586 break; 3587 default: 3588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3589 return MCDisassembler::Fail; 3590 break; 3591 } 3592 if (Rm != 0xF) { 3593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 } 3596 3597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3598 return MCDisassembler::Fail; 3599 Inst.addOperand(MCOperand::createImm(align)); 3600 3601 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3602 // variant encodes Rm == 0xf. Anything else is a register offset post- 3603 // increment and we need to add the register operand to the instruction. 3604 if (Rm != 0xD && Rm != 0xF && 3605 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3606 return MCDisassembler::Fail; 3607 3608 return S; 3609 } 3610 3611 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3612 uint64_t Address, 3613 const MCDisassembler *Decoder) { 3614 DecodeStatus S = MCDisassembler::Success; 3615 3616 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3617 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3618 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3619 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3620 unsigned align = fieldFromInstruction(Insn, 4, 1); 3621 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3622 align *= 2*size; 3623 3624 switch (Inst.getOpcode()) { 3625 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3626 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3627 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3628 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3629 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3630 return MCDisassembler::Fail; 3631 break; 3632 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3633 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3634 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3635 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3636 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 break; 3639 default: 3640 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3641 return MCDisassembler::Fail; 3642 break; 3643 } 3644 3645 if (Rm != 0xF) 3646 Inst.addOperand(MCOperand::createImm(0)); 3647 3648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3649 return MCDisassembler::Fail; 3650 Inst.addOperand(MCOperand::createImm(align)); 3651 3652 if (Rm != 0xD && Rm != 0xF) { 3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3654 return MCDisassembler::Fail; 3655 } 3656 3657 return S; 3658 } 3659 3660 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3661 uint64_t Address, 3662 const MCDisassembler *Decoder) { 3663 DecodeStatus S = MCDisassembler::Success; 3664 3665 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3666 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3667 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3668 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3669 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3670 3671 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 if (Rm != 0xF) { 3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3679 return MCDisassembler::Fail; 3680 } 3681 3682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3683 return MCDisassembler::Fail; 3684 Inst.addOperand(MCOperand::createImm(0)); 3685 3686 if (Rm == 0xD) 3687 Inst.addOperand(MCOperand::createReg(0)); 3688 else if (Rm != 0xF) { 3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3690 return MCDisassembler::Fail; 3691 } 3692 3693 return S; 3694 } 3695 3696 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3697 uint64_t Address, 3698 const MCDisassembler *Decoder) { 3699 DecodeStatus S = MCDisassembler::Success; 3700 3701 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3702 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3703 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3704 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3705 unsigned size = fieldFromInstruction(Insn, 6, 2); 3706 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3707 unsigned align = fieldFromInstruction(Insn, 4, 1); 3708 3709 if (size == 0x3) { 3710 if (align == 0) 3711 return MCDisassembler::Fail; 3712 align = 16; 3713 } else { 3714 if (size == 2) { 3715 align *= 8; 3716 } else { 3717 size = 1 << size; 3718 align *= 4*size; 3719 } 3720 } 3721 3722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3723 return MCDisassembler::Fail; 3724 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3725 return MCDisassembler::Fail; 3726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 if (Rm != 0xF) { 3731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3732 return MCDisassembler::Fail; 3733 } 3734 3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3736 return MCDisassembler::Fail; 3737 Inst.addOperand(MCOperand::createImm(align)); 3738 3739 if (Rm == 0xD) 3740 Inst.addOperand(MCOperand::createReg(0)); 3741 else if (Rm != 0xF) { 3742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3743 return MCDisassembler::Fail; 3744 } 3745 3746 return S; 3747 } 3748 3749 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3750 uint64_t Address, 3751 const MCDisassembler *Decoder) { 3752 DecodeStatus S = MCDisassembler::Success; 3753 3754 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3755 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3756 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3757 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3758 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3759 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3760 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3761 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3762 3763 if (Q) { 3764 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 } else { 3767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3768 return MCDisassembler::Fail; 3769 } 3770 3771 Inst.addOperand(MCOperand::createImm(imm)); 3772 3773 switch (Inst.getOpcode()) { 3774 case ARM::VORRiv4i16: 3775 case ARM::VORRiv2i32: 3776 case ARM::VBICiv4i16: 3777 case ARM::VBICiv2i32: 3778 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3779 return MCDisassembler::Fail; 3780 break; 3781 case ARM::VORRiv8i16: 3782 case ARM::VORRiv4i32: 3783 case ARM::VBICiv8i16: 3784 case ARM::VBICiv4i32: 3785 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3786 return MCDisassembler::Fail; 3787 break; 3788 default: 3789 break; 3790 } 3791 3792 return S; 3793 } 3794 3795 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3796 uint64_t Address, 3797 const MCDisassembler *Decoder) { 3798 DecodeStatus S = MCDisassembler::Success; 3799 3800 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3801 fieldFromInstruction(Insn, 13, 3)); 3802 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3803 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3804 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3805 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3806 imm |= cmode << 8; 3807 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3808 3809 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3810 return MCDisassembler::Fail; 3811 3812 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3813 return MCDisassembler::Fail; 3814 3815 Inst.addOperand(MCOperand::createImm(imm)); 3816 3817 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3818 Inst.addOperand(MCOperand::createReg(0)); 3819 Inst.addOperand(MCOperand::createImm(0)); 3820 3821 return S; 3822 } 3823 3824 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3825 uint64_t Address, 3826 const MCDisassembler *Decoder) { 3827 DecodeStatus S = MCDisassembler::Success; 3828 3829 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3830 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3831 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3832 return MCDisassembler::Fail; 3833 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3834 3835 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3836 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3837 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3838 return MCDisassembler::Fail; 3839 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3840 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3841 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3842 return MCDisassembler::Fail; 3843 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3844 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3845 Inst.addOperand(MCOperand::createImm(Qd)); 3846 3847 return S; 3848 } 3849 3850 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3851 uint64_t Address, 3852 const MCDisassembler *Decoder) { 3853 DecodeStatus S = MCDisassembler::Success; 3854 3855 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3856 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3857 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3858 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3859 unsigned size = fieldFromInstruction(Insn, 18, 2); 3860 3861 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3862 return MCDisassembler::Fail; 3863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3864 return MCDisassembler::Fail; 3865 Inst.addOperand(MCOperand::createImm(8 << size)); 3866 3867 return S; 3868 } 3869 3870 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3871 uint64_t Address, 3872 const MCDisassembler *Decoder) { 3873 Inst.addOperand(MCOperand::createImm(8 - Val)); 3874 return MCDisassembler::Success; 3875 } 3876 3877 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3878 uint64_t Address, 3879 const MCDisassembler *Decoder) { 3880 Inst.addOperand(MCOperand::createImm(16 - Val)); 3881 return MCDisassembler::Success; 3882 } 3883 3884 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3885 uint64_t Address, 3886 const MCDisassembler *Decoder) { 3887 Inst.addOperand(MCOperand::createImm(32 - Val)); 3888 return MCDisassembler::Success; 3889 } 3890 3891 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3892 uint64_t Address, 3893 const MCDisassembler *Decoder) { 3894 Inst.addOperand(MCOperand::createImm(64 - Val)); 3895 return MCDisassembler::Success; 3896 } 3897 3898 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3899 uint64_t Address, 3900 const MCDisassembler *Decoder) { 3901 DecodeStatus S = MCDisassembler::Success; 3902 3903 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3904 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3905 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3906 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3907 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3908 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3909 unsigned op = fieldFromInstruction(Insn, 6, 1); 3910 3911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3912 return MCDisassembler::Fail; 3913 if (op) { 3914 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3915 return MCDisassembler::Fail; // Writeback 3916 } 3917 3918 switch (Inst.getOpcode()) { 3919 case ARM::VTBL2: 3920 case ARM::VTBX2: 3921 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3922 return MCDisassembler::Fail; 3923 break; 3924 default: 3925 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3926 return MCDisassembler::Fail; 3927 } 3928 3929 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3930 return MCDisassembler::Fail; 3931 3932 return S; 3933 } 3934 3935 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3936 uint64_t Address, 3937 const MCDisassembler *Decoder) { 3938 DecodeStatus S = MCDisassembler::Success; 3939 3940 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3941 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3942 3943 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3944 return MCDisassembler::Fail; 3945 3946 switch(Inst.getOpcode()) { 3947 default: 3948 return MCDisassembler::Fail; 3949 case ARM::tADR: 3950 break; // tADR does not explicitly represent the PC as an operand. 3951 case ARM::tADDrSPi: 3952 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3953 break; 3954 } 3955 3956 Inst.addOperand(MCOperand::createImm(imm)); 3957 return S; 3958 } 3959 3960 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3961 uint64_t Address, 3962 const MCDisassembler *Decoder) { 3963 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3964 true, 2, Inst, Decoder)) 3965 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3966 return MCDisassembler::Success; 3967 } 3968 3969 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3970 uint64_t Address, 3971 const MCDisassembler *Decoder) { 3972 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3973 true, 4, Inst, Decoder)) 3974 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3975 return MCDisassembler::Success; 3976 } 3977 3978 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3979 uint64_t Address, 3980 const MCDisassembler *Decoder) { 3981 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3982 true, 2, Inst, Decoder)) 3983 Inst.addOperand(MCOperand::createImm(Val << 1)); 3984 return MCDisassembler::Success; 3985 } 3986 3987 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3988 uint64_t Address, 3989 const MCDisassembler *Decoder) { 3990 DecodeStatus S = MCDisassembler::Success; 3991 3992 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3993 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3994 3995 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3998 return MCDisassembler::Fail; 3999 4000 return S; 4001 } 4002 4003 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 4004 uint64_t Address, 4005 const MCDisassembler *Decoder) { 4006 DecodeStatus S = MCDisassembler::Success; 4007 4008 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4009 unsigned imm = fieldFromInstruction(Val, 3, 5); 4010 4011 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4012 return MCDisassembler::Fail; 4013 Inst.addOperand(MCOperand::createImm(imm)); 4014 4015 return S; 4016 } 4017 4018 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4019 uint64_t Address, 4020 const MCDisassembler *Decoder) { 4021 unsigned imm = Val << 2; 4022 4023 Inst.addOperand(MCOperand::createImm(imm)); 4024 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4025 4026 return MCDisassembler::Success; 4027 } 4028 4029 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4030 uint64_t Address, 4031 const MCDisassembler *Decoder) { 4032 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4033 Inst.addOperand(MCOperand::createImm(Val)); 4034 4035 return MCDisassembler::Success; 4036 } 4037 4038 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4039 uint64_t Address, 4040 const MCDisassembler *Decoder) { 4041 DecodeStatus S = MCDisassembler::Success; 4042 4043 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4044 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4045 unsigned imm = fieldFromInstruction(Val, 0, 2); 4046 4047 // Thumb stores cannot use PC as dest register. 4048 switch (Inst.getOpcode()) { 4049 case ARM::t2STRHs: 4050 case ARM::t2STRBs: 4051 case ARM::t2STRs: 4052 if (Rn == 15) 4053 return MCDisassembler::Fail; 4054 break; 4055 default: 4056 break; 4057 } 4058 4059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4060 return MCDisassembler::Fail; 4061 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4062 return MCDisassembler::Fail; 4063 Inst.addOperand(MCOperand::createImm(imm)); 4064 4065 return S; 4066 } 4067 4068 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4069 uint64_t Address, 4070 const MCDisassembler *Decoder) { 4071 DecodeStatus S = MCDisassembler::Success; 4072 4073 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4074 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4075 4076 const FeatureBitset &featureBits = 4077 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4078 4079 bool hasMP = featureBits[ARM::FeatureMP]; 4080 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4081 4082 if (Rn == 15) { 4083 switch (Inst.getOpcode()) { 4084 case ARM::t2LDRBs: 4085 Inst.setOpcode(ARM::t2LDRBpci); 4086 break; 4087 case ARM::t2LDRHs: 4088 Inst.setOpcode(ARM::t2LDRHpci); 4089 break; 4090 case ARM::t2LDRSHs: 4091 Inst.setOpcode(ARM::t2LDRSHpci); 4092 break; 4093 case ARM::t2LDRSBs: 4094 Inst.setOpcode(ARM::t2LDRSBpci); 4095 break; 4096 case ARM::t2LDRs: 4097 Inst.setOpcode(ARM::t2LDRpci); 4098 break; 4099 case ARM::t2PLDs: 4100 Inst.setOpcode(ARM::t2PLDpci); 4101 break; 4102 case ARM::t2PLIs: 4103 Inst.setOpcode(ARM::t2PLIpci); 4104 break; 4105 default: 4106 return MCDisassembler::Fail; 4107 } 4108 4109 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4110 } 4111 4112 if (Rt == 15) { 4113 switch (Inst.getOpcode()) { 4114 case ARM::t2LDRSHs: 4115 return MCDisassembler::Fail; 4116 case ARM::t2LDRHs: 4117 Inst.setOpcode(ARM::t2PLDWs); 4118 break; 4119 case ARM::t2LDRSBs: 4120 Inst.setOpcode(ARM::t2PLIs); 4121 break; 4122 default: 4123 break; 4124 } 4125 } 4126 4127 switch (Inst.getOpcode()) { 4128 case ARM::t2PLDs: 4129 break; 4130 case ARM::t2PLIs: 4131 if (!hasV7Ops) 4132 return MCDisassembler::Fail; 4133 break; 4134 case ARM::t2PLDWs: 4135 if (!hasV7Ops || !hasMP) 4136 return MCDisassembler::Fail; 4137 break; 4138 default: 4139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4140 return MCDisassembler::Fail; 4141 } 4142 4143 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4144 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4145 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4146 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 4149 return S; 4150 } 4151 4152 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4153 uint64_t Address, 4154 const MCDisassembler *Decoder) { 4155 DecodeStatus S = MCDisassembler::Success; 4156 4157 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4158 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4159 unsigned U = fieldFromInstruction(Insn, 9, 1); 4160 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4161 imm |= (U << 8); 4162 imm |= (Rn << 9); 4163 unsigned add = fieldFromInstruction(Insn, 9, 1); 4164 4165 const FeatureBitset &featureBits = 4166 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4167 4168 bool hasMP = featureBits[ARM::FeatureMP]; 4169 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4170 4171 if (Rn == 15) { 4172 switch (Inst.getOpcode()) { 4173 case ARM::t2LDRi8: 4174 Inst.setOpcode(ARM::t2LDRpci); 4175 break; 4176 case ARM::t2LDRBi8: 4177 Inst.setOpcode(ARM::t2LDRBpci); 4178 break; 4179 case ARM::t2LDRSBi8: 4180 Inst.setOpcode(ARM::t2LDRSBpci); 4181 break; 4182 case ARM::t2LDRHi8: 4183 Inst.setOpcode(ARM::t2LDRHpci); 4184 break; 4185 case ARM::t2LDRSHi8: 4186 Inst.setOpcode(ARM::t2LDRSHpci); 4187 break; 4188 case ARM::t2PLDi8: 4189 Inst.setOpcode(ARM::t2PLDpci); 4190 break; 4191 case ARM::t2PLIi8: 4192 Inst.setOpcode(ARM::t2PLIpci); 4193 break; 4194 default: 4195 return MCDisassembler::Fail; 4196 } 4197 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4198 } 4199 4200 if (Rt == 15) { 4201 switch (Inst.getOpcode()) { 4202 case ARM::t2LDRSHi8: 4203 return MCDisassembler::Fail; 4204 case ARM::t2LDRHi8: 4205 if (!add) 4206 Inst.setOpcode(ARM::t2PLDWi8); 4207 break; 4208 case ARM::t2LDRSBi8: 4209 Inst.setOpcode(ARM::t2PLIi8); 4210 break; 4211 default: 4212 break; 4213 } 4214 } 4215 4216 switch (Inst.getOpcode()) { 4217 case ARM::t2PLDi8: 4218 break; 4219 case ARM::t2PLIi8: 4220 if (!hasV7Ops) 4221 return MCDisassembler::Fail; 4222 break; 4223 case ARM::t2PLDWi8: 4224 if (!hasV7Ops || !hasMP) 4225 return MCDisassembler::Fail; 4226 break; 4227 default: 4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 } 4231 4232 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4233 return MCDisassembler::Fail; 4234 return S; 4235 } 4236 4237 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4238 uint64_t Address, 4239 const MCDisassembler *Decoder) { 4240 DecodeStatus S = MCDisassembler::Success; 4241 4242 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4243 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4244 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4245 imm |= (Rn << 13); 4246 4247 const FeatureBitset &featureBits = 4248 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4249 4250 bool hasMP = featureBits[ARM::FeatureMP]; 4251 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4252 4253 if (Rn == 15) { 4254 switch (Inst.getOpcode()) { 4255 case ARM::t2LDRi12: 4256 Inst.setOpcode(ARM::t2LDRpci); 4257 break; 4258 case ARM::t2LDRHi12: 4259 Inst.setOpcode(ARM::t2LDRHpci); 4260 break; 4261 case ARM::t2LDRSHi12: 4262 Inst.setOpcode(ARM::t2LDRSHpci); 4263 break; 4264 case ARM::t2LDRBi12: 4265 Inst.setOpcode(ARM::t2LDRBpci); 4266 break; 4267 case ARM::t2LDRSBi12: 4268 Inst.setOpcode(ARM::t2LDRSBpci); 4269 break; 4270 case ARM::t2PLDi12: 4271 Inst.setOpcode(ARM::t2PLDpci); 4272 break; 4273 case ARM::t2PLIi12: 4274 Inst.setOpcode(ARM::t2PLIpci); 4275 break; 4276 default: 4277 return MCDisassembler::Fail; 4278 } 4279 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4280 } 4281 4282 if (Rt == 15) { 4283 switch (Inst.getOpcode()) { 4284 case ARM::t2LDRSHi12: 4285 return MCDisassembler::Fail; 4286 case ARM::t2LDRHi12: 4287 Inst.setOpcode(ARM::t2PLDWi12); 4288 break; 4289 case ARM::t2LDRSBi12: 4290 Inst.setOpcode(ARM::t2PLIi12); 4291 break; 4292 default: 4293 break; 4294 } 4295 } 4296 4297 switch (Inst.getOpcode()) { 4298 case ARM::t2PLDi12: 4299 break; 4300 case ARM::t2PLIi12: 4301 if (!hasV7Ops) 4302 return MCDisassembler::Fail; 4303 break; 4304 case ARM::t2PLDWi12: 4305 if (!hasV7Ops || !hasMP) 4306 return MCDisassembler::Fail; 4307 break; 4308 default: 4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4310 return MCDisassembler::Fail; 4311 } 4312 4313 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 return S; 4316 } 4317 4318 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4319 const MCDisassembler *Decoder) { 4320 DecodeStatus S = MCDisassembler::Success; 4321 4322 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4323 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4324 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4325 imm |= (Rn << 9); 4326 4327 if (Rn == 15) { 4328 switch (Inst.getOpcode()) { 4329 case ARM::t2LDRT: 4330 Inst.setOpcode(ARM::t2LDRpci); 4331 break; 4332 case ARM::t2LDRBT: 4333 Inst.setOpcode(ARM::t2LDRBpci); 4334 break; 4335 case ARM::t2LDRHT: 4336 Inst.setOpcode(ARM::t2LDRHpci); 4337 break; 4338 case ARM::t2LDRSBT: 4339 Inst.setOpcode(ARM::t2LDRSBpci); 4340 break; 4341 case ARM::t2LDRSHT: 4342 Inst.setOpcode(ARM::t2LDRSHpci); 4343 break; 4344 default: 4345 return MCDisassembler::Fail; 4346 } 4347 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4348 } 4349 4350 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4353 return MCDisassembler::Fail; 4354 return S; 4355 } 4356 4357 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4358 uint64_t Address, 4359 const MCDisassembler *Decoder) { 4360 DecodeStatus S = MCDisassembler::Success; 4361 4362 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4363 unsigned U = fieldFromInstruction(Insn, 23, 1); 4364 int imm = fieldFromInstruction(Insn, 0, 12); 4365 4366 const FeatureBitset &featureBits = 4367 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4368 4369 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4370 4371 if (Rt == 15) { 4372 switch (Inst.getOpcode()) { 4373 case ARM::t2LDRBpci: 4374 case ARM::t2LDRHpci: 4375 Inst.setOpcode(ARM::t2PLDpci); 4376 break; 4377 case ARM::t2LDRSBpci: 4378 Inst.setOpcode(ARM::t2PLIpci); 4379 break; 4380 case ARM::t2LDRSHpci: 4381 return MCDisassembler::Fail; 4382 default: 4383 break; 4384 } 4385 } 4386 4387 switch(Inst.getOpcode()) { 4388 case ARM::t2PLDpci: 4389 break; 4390 case ARM::t2PLIpci: 4391 if (!hasV7Ops) 4392 return MCDisassembler::Fail; 4393 break; 4394 default: 4395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4396 return MCDisassembler::Fail; 4397 } 4398 4399 if (!U) { 4400 // Special case for #-0. 4401 if (imm == 0) 4402 imm = INT32_MIN; 4403 else 4404 imm = -imm; 4405 } 4406 Inst.addOperand(MCOperand::createImm(imm)); 4407 4408 return S; 4409 } 4410 4411 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4412 const MCDisassembler *Decoder) { 4413 if (Val == 0) 4414 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4415 else { 4416 int imm = Val & 0xFF; 4417 4418 if (!(Val & 0x100)) imm *= -1; 4419 Inst.addOperand(MCOperand::createImm(imm * 4)); 4420 } 4421 4422 return MCDisassembler::Success; 4423 } 4424 4425 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4426 const MCDisassembler *Decoder) { 4427 if (Val == 0) 4428 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4429 else { 4430 int imm = Val & 0x7F; 4431 4432 if (!(Val & 0x80)) 4433 imm *= -1; 4434 Inst.addOperand(MCOperand::createImm(imm * 4)); 4435 } 4436 4437 return MCDisassembler::Success; 4438 } 4439 4440 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4441 uint64_t Address, 4442 const MCDisassembler *Decoder) { 4443 DecodeStatus S = MCDisassembler::Success; 4444 4445 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4446 unsigned imm = fieldFromInstruction(Val, 0, 9); 4447 4448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4449 return MCDisassembler::Fail; 4450 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 4453 return S; 4454 } 4455 4456 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4457 uint64_t Address, 4458 const MCDisassembler *Decoder) { 4459 DecodeStatus S = MCDisassembler::Success; 4460 4461 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4462 unsigned imm = fieldFromInstruction(Val, 0, 8); 4463 4464 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4467 return MCDisassembler::Fail; 4468 4469 return S; 4470 } 4471 4472 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4473 uint64_t Address, 4474 const MCDisassembler *Decoder) { 4475 DecodeStatus S = MCDisassembler::Success; 4476 4477 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4478 unsigned imm = fieldFromInstruction(Val, 0, 8); 4479 4480 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4481 return MCDisassembler::Fail; 4482 4483 Inst.addOperand(MCOperand::createImm(imm)); 4484 4485 return S; 4486 } 4487 4488 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4489 const MCDisassembler *Decoder) { 4490 int imm = Val & 0xFF; 4491 if (Val == 0) 4492 imm = INT32_MIN; 4493 else if (!(Val & 0x100)) 4494 imm *= -1; 4495 Inst.addOperand(MCOperand::createImm(imm)); 4496 4497 return MCDisassembler::Success; 4498 } 4499 4500 template <int shift> 4501 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4502 const MCDisassembler *Decoder) { 4503 int imm = Val & 0x7F; 4504 if (Val == 0) 4505 imm = INT32_MIN; 4506 else if (!(Val & 0x80)) 4507 imm *= -1; 4508 if (imm != INT32_MIN) 4509 imm *= (1U << shift); 4510 Inst.addOperand(MCOperand::createImm(imm)); 4511 4512 return MCDisassembler::Success; 4513 } 4514 4515 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4516 uint64_t Address, 4517 const MCDisassembler *Decoder) { 4518 DecodeStatus S = MCDisassembler::Success; 4519 4520 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4521 unsigned imm = fieldFromInstruction(Val, 0, 9); 4522 4523 // Thumb stores cannot use PC as dest register. 4524 switch (Inst.getOpcode()) { 4525 case ARM::t2STRT: 4526 case ARM::t2STRBT: 4527 case ARM::t2STRHT: 4528 case ARM::t2STRi8: 4529 case ARM::t2STRHi8: 4530 case ARM::t2STRBi8: 4531 if (Rn == 15) 4532 return MCDisassembler::Fail; 4533 break; 4534 default: 4535 break; 4536 } 4537 4538 // Some instructions always use an additive offset. 4539 switch (Inst.getOpcode()) { 4540 case ARM::t2LDRT: 4541 case ARM::t2LDRBT: 4542 case ARM::t2LDRHT: 4543 case ARM::t2LDRSBT: 4544 case ARM::t2LDRSHT: 4545 case ARM::t2STRT: 4546 case ARM::t2STRBT: 4547 case ARM::t2STRHT: 4548 imm |= 0x100; 4549 break; 4550 default: 4551 break; 4552 } 4553 4554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4555 return MCDisassembler::Fail; 4556 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4557 return MCDisassembler::Fail; 4558 4559 return S; 4560 } 4561 4562 template <int shift> 4563 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4564 uint64_t Address, 4565 const MCDisassembler *Decoder) { 4566 DecodeStatus S = MCDisassembler::Success; 4567 4568 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4569 unsigned imm = fieldFromInstruction(Val, 0, 8); 4570 4571 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4574 return MCDisassembler::Fail; 4575 4576 return S; 4577 } 4578 4579 template <int shift, int WriteBack> 4580 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4581 uint64_t Address, 4582 const MCDisassembler *Decoder) { 4583 DecodeStatus S = MCDisassembler::Success; 4584 4585 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4586 unsigned imm = fieldFromInstruction(Val, 0, 8); 4587 if (WriteBack) { 4588 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4591 return MCDisassembler::Fail; 4592 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4593 return MCDisassembler::Fail; 4594 4595 return S; 4596 } 4597 4598 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4599 uint64_t Address, 4600 const MCDisassembler *Decoder) { 4601 DecodeStatus S = MCDisassembler::Success; 4602 4603 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4604 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4605 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4606 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4607 addr |= Rn << 9; 4608 unsigned load = fieldFromInstruction(Insn, 20, 1); 4609 4610 if (Rn == 15) { 4611 switch (Inst.getOpcode()) { 4612 case ARM::t2LDR_PRE: 4613 case ARM::t2LDR_POST: 4614 Inst.setOpcode(ARM::t2LDRpci); 4615 break; 4616 case ARM::t2LDRB_PRE: 4617 case ARM::t2LDRB_POST: 4618 Inst.setOpcode(ARM::t2LDRBpci); 4619 break; 4620 case ARM::t2LDRH_PRE: 4621 case ARM::t2LDRH_POST: 4622 Inst.setOpcode(ARM::t2LDRHpci); 4623 break; 4624 case ARM::t2LDRSB_PRE: 4625 case ARM::t2LDRSB_POST: 4626 if (Rt == 15) 4627 Inst.setOpcode(ARM::t2PLIpci); 4628 else 4629 Inst.setOpcode(ARM::t2LDRSBpci); 4630 break; 4631 case ARM::t2LDRSH_PRE: 4632 case ARM::t2LDRSH_POST: 4633 Inst.setOpcode(ARM::t2LDRSHpci); 4634 break; 4635 default: 4636 return MCDisassembler::Fail; 4637 } 4638 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4639 } 4640 4641 if (!load) { 4642 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4643 return MCDisassembler::Fail; 4644 } 4645 4646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4647 return MCDisassembler::Fail; 4648 4649 if (load) { 4650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4651 return MCDisassembler::Fail; 4652 } 4653 4654 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4655 return MCDisassembler::Fail; 4656 4657 return S; 4658 } 4659 4660 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4661 uint64_t Address, 4662 const MCDisassembler *Decoder) { 4663 DecodeStatus S = MCDisassembler::Success; 4664 4665 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4666 unsigned imm = fieldFromInstruction(Val, 0, 12); 4667 4668 // Thumb stores cannot use PC as dest register. 4669 switch (Inst.getOpcode()) { 4670 case ARM::t2STRi12: 4671 case ARM::t2STRBi12: 4672 case ARM::t2STRHi12: 4673 if (Rn == 15) 4674 return MCDisassembler::Fail; 4675 break; 4676 default: 4677 break; 4678 } 4679 4680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4681 return MCDisassembler::Fail; 4682 Inst.addOperand(MCOperand::createImm(imm)); 4683 4684 return S; 4685 } 4686 4687 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4688 uint64_t Address, 4689 const MCDisassembler *Decoder) { 4690 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4691 4692 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4693 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4694 Inst.addOperand(MCOperand::createImm(imm)); 4695 4696 return MCDisassembler::Success; 4697 } 4698 4699 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4700 uint64_t Address, 4701 const MCDisassembler *Decoder) { 4702 DecodeStatus S = MCDisassembler::Success; 4703 4704 if (Inst.getOpcode() == ARM::tADDrSP) { 4705 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4706 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4707 4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 } else if (Inst.getOpcode() == ARM::tADDspr) { 4714 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4715 4716 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4717 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4718 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4719 return MCDisassembler::Fail; 4720 } 4721 4722 return S; 4723 } 4724 4725 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4726 uint64_t Address, 4727 const MCDisassembler *Decoder) { 4728 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4729 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4730 4731 Inst.addOperand(MCOperand::createImm(imod)); 4732 Inst.addOperand(MCOperand::createImm(flags)); 4733 4734 return MCDisassembler::Success; 4735 } 4736 4737 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4738 uint64_t Address, 4739 const MCDisassembler *Decoder) { 4740 DecodeStatus S = MCDisassembler::Success; 4741 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4742 unsigned add = fieldFromInstruction(Insn, 4, 1); 4743 4744 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4745 return MCDisassembler::Fail; 4746 Inst.addOperand(MCOperand::createImm(add)); 4747 4748 return S; 4749 } 4750 4751 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4752 uint64_t Address, 4753 const MCDisassembler *Decoder) { 4754 DecodeStatus S = MCDisassembler::Success; 4755 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4756 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4757 4758 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4759 return MCDisassembler::Fail; 4760 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4761 return MCDisassembler::Fail; 4762 4763 return S; 4764 } 4765 4766 template <int shift> 4767 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4768 uint64_t Address, 4769 const MCDisassembler *Decoder) { 4770 DecodeStatus S = MCDisassembler::Success; 4771 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4772 int imm = fieldFromInstruction(Insn, 0, 7); 4773 4774 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4775 return MCDisassembler::Fail; 4776 4777 if(!fieldFromInstruction(Insn, 7, 1)) { 4778 if (imm == 0) 4779 imm = INT32_MIN; // indicate -0 4780 else 4781 imm *= -1; 4782 } 4783 if (imm != INT32_MIN) 4784 imm *= (1U << shift); 4785 Inst.addOperand(MCOperand::createImm(imm)); 4786 4787 return S; 4788 } 4789 4790 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4791 uint64_t Address, 4792 const MCDisassembler *Decoder) { 4793 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4794 // Note only one trailing zero not two. Also the J1 and J2 values are from 4795 // the encoded instruction. So here change to I1 and I2 values via: 4796 // I1 = NOT(J1 EOR S); 4797 // I2 = NOT(J2 EOR S); 4798 // and build the imm32 with two trailing zeros as documented: 4799 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4800 unsigned S = (Val >> 23) & 1; 4801 unsigned J1 = (Val >> 22) & 1; 4802 unsigned J2 = (Val >> 21) & 1; 4803 unsigned I1 = !(J1 ^ S); 4804 unsigned I2 = !(J2 ^ S); 4805 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4806 int imm32 = SignExtend32<25>(tmp << 1); 4807 4808 if (!tryAddingSymbolicOperand(Address, 4809 (Address & ~2u) + imm32 + 4, 4810 true, 4, Inst, Decoder)) 4811 Inst.addOperand(MCOperand::createImm(imm32)); 4812 return MCDisassembler::Success; 4813 } 4814 4815 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4816 uint64_t Address, 4817 const MCDisassembler *Decoder) { 4818 if (Val == 0xA || Val == 0xB) 4819 return MCDisassembler::Fail; 4820 4821 const FeatureBitset &featureBits = 4822 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4823 4824 if (!isValidCoprocessorNumber(Val, featureBits)) 4825 return MCDisassembler::Fail; 4826 4827 Inst.addOperand(MCOperand::createImm(Val)); 4828 return MCDisassembler::Success; 4829 } 4830 4831 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4832 uint64_t Address, 4833 const MCDisassembler *Decoder) { 4834 const FeatureBitset &FeatureBits = 4835 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4836 DecodeStatus S = MCDisassembler::Success; 4837 4838 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4839 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4840 4841 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4845 return MCDisassembler::Fail; 4846 return S; 4847 } 4848 4849 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4850 uint64_t Address, 4851 const MCDisassembler *Decoder) { 4852 DecodeStatus S = MCDisassembler::Success; 4853 4854 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4855 if (pred == 0xE || pred == 0xF) { 4856 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4857 switch (opc) { 4858 default: 4859 return MCDisassembler::Fail; 4860 case 0xf3bf8f4: 4861 Inst.setOpcode(ARM::t2DSB); 4862 break; 4863 case 0xf3bf8f5: 4864 Inst.setOpcode(ARM::t2DMB); 4865 break; 4866 case 0xf3bf8f6: 4867 Inst.setOpcode(ARM::t2ISB); 4868 break; 4869 } 4870 4871 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4872 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4873 } 4874 4875 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4876 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4877 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4878 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4879 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4880 4881 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4882 return MCDisassembler::Fail; 4883 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4884 return MCDisassembler::Fail; 4885 4886 return S; 4887 } 4888 4889 // Decode a shifted immediate operand. These basically consist 4890 // of an 8-bit value, and a 4-bit directive that specifies either 4891 // a splat operation or a rotation. 4892 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4893 const MCDisassembler *Decoder) { 4894 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4895 if (ctrl == 0) { 4896 unsigned byte = fieldFromInstruction(Val, 8, 2); 4897 unsigned imm = fieldFromInstruction(Val, 0, 8); 4898 switch (byte) { 4899 case 0: 4900 Inst.addOperand(MCOperand::createImm(imm)); 4901 break; 4902 case 1: 4903 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4904 break; 4905 case 2: 4906 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4907 break; 4908 case 3: 4909 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4910 (imm << 8) | imm)); 4911 break; 4912 } 4913 } else { 4914 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4915 unsigned rot = fieldFromInstruction(Val, 7, 5); 4916 unsigned imm = llvm::rotr<uint32_t>(unrot, rot); 4917 Inst.addOperand(MCOperand::createImm(imm)); 4918 } 4919 4920 return MCDisassembler::Success; 4921 } 4922 4923 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4924 uint64_t Address, 4925 const MCDisassembler *Decoder) { 4926 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4927 true, 2, Inst, Decoder)) 4928 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4929 return MCDisassembler::Success; 4930 } 4931 4932 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4933 uint64_t Address, 4934 const MCDisassembler *Decoder) { 4935 // Val is passed in as S:J1:J2:imm10:imm11 4936 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4937 // the encoded instruction. So here change to I1 and I2 values via: 4938 // I1 = NOT(J1 EOR S); 4939 // I2 = NOT(J2 EOR S); 4940 // and build the imm32 with one trailing zero as documented: 4941 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4942 unsigned S = (Val >> 23) & 1; 4943 unsigned J1 = (Val >> 22) & 1; 4944 unsigned J2 = (Val >> 21) & 1; 4945 unsigned I1 = !(J1 ^ S); 4946 unsigned I2 = !(J2 ^ S); 4947 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4948 int imm32 = SignExtend32<25>(tmp << 1); 4949 4950 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4951 true, 4, Inst, Decoder)) 4952 Inst.addOperand(MCOperand::createImm(imm32)); 4953 return MCDisassembler::Success; 4954 } 4955 4956 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4957 uint64_t Address, 4958 const MCDisassembler *Decoder) { 4959 if (Val & ~0xf) 4960 return MCDisassembler::Fail; 4961 4962 Inst.addOperand(MCOperand::createImm(Val)); 4963 return MCDisassembler::Success; 4964 } 4965 4966 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4967 uint64_t Address, 4968 const MCDisassembler *Decoder) { 4969 if (Val & ~0xf) 4970 return MCDisassembler::Fail; 4971 4972 Inst.addOperand(MCOperand::createImm(Val)); 4973 return MCDisassembler::Success; 4974 } 4975 4976 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4977 const MCDisassembler *Decoder) { 4978 DecodeStatus S = MCDisassembler::Success; 4979 const FeatureBitset &FeatureBits = 4980 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4981 4982 if (FeatureBits[ARM::FeatureMClass]) { 4983 unsigned ValLow = Val & 0xff; 4984 4985 // Validate the SYSm value first. 4986 switch (ValLow) { 4987 case 0: // apsr 4988 case 1: // iapsr 4989 case 2: // eapsr 4990 case 3: // xpsr 4991 case 5: // ipsr 4992 case 6: // epsr 4993 case 7: // iepsr 4994 case 8: // msp 4995 case 9: // psp 4996 case 16: // primask 4997 case 20: // control 4998 break; 4999 case 17: // basepri 5000 case 18: // basepri_max 5001 case 19: // faultmask 5002 if (!(FeatureBits[ARM::HasV7Ops])) 5003 // Values basepri, basepri_max and faultmask are only valid for v7m. 5004 return MCDisassembler::Fail; 5005 break; 5006 case 0x8a: // msplim_ns 5007 case 0x8b: // psplim_ns 5008 case 0x91: // basepri_ns 5009 case 0x93: // faultmask_ns 5010 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5011 return MCDisassembler::Fail; 5012 [[fallthrough]]; 5013 case 10: // msplim 5014 case 11: // psplim 5015 case 0x88: // msp_ns 5016 case 0x89: // psp_ns 5017 case 0x90: // primask_ns 5018 case 0x94: // control_ns 5019 case 0x98: // sp_ns 5020 if (!(FeatureBits[ARM::Feature8MSecExt])) 5021 return MCDisassembler::Fail; 5022 break; 5023 case 0x20: // pac_key_p_0 5024 case 0x21: // pac_key_p_1 5025 case 0x22: // pac_key_p_2 5026 case 0x23: // pac_key_p_3 5027 case 0x24: // pac_key_u_0 5028 case 0x25: // pac_key_u_1 5029 case 0x26: // pac_key_u_2 5030 case 0x27: // pac_key_u_3 5031 case 0xa0: // pac_key_p_0_ns 5032 case 0xa1: // pac_key_p_1_ns 5033 case 0xa2: // pac_key_p_2_ns 5034 case 0xa3: // pac_key_p_3_ns 5035 case 0xa4: // pac_key_u_0_ns 5036 case 0xa5: // pac_key_u_1_ns 5037 case 0xa6: // pac_key_u_2_ns 5038 case 0xa7: // pac_key_u_3_ns 5039 if (!(FeatureBits[ARM::FeaturePACBTI])) 5040 return MCDisassembler::Fail; 5041 break; 5042 default: 5043 // Architecturally defined as unpredictable 5044 S = MCDisassembler::SoftFail; 5045 break; 5046 } 5047 5048 if (Inst.getOpcode() == ARM::t2MSR_M) { 5049 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5050 if (!(FeatureBits[ARM::HasV7Ops])) { 5051 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5052 // unpredictable. 5053 if (Mask != 2) 5054 S = MCDisassembler::SoftFail; 5055 } 5056 else { 5057 // The ARMv7-M architecture stores an additional 2-bit mask value in 5058 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5059 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5060 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5061 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5062 // only if the processor includes the DSP extension. 5063 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5064 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5065 S = MCDisassembler::SoftFail; 5066 } 5067 } 5068 } else { 5069 // A/R class 5070 if (Val == 0) 5071 return MCDisassembler::Fail; 5072 } 5073 Inst.addOperand(MCOperand::createImm(Val)); 5074 return S; 5075 } 5076 5077 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5078 uint64_t Address, 5079 const MCDisassembler *Decoder) { 5080 unsigned R = fieldFromInstruction(Val, 5, 1); 5081 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5082 5083 // The table of encodings for these banked registers comes from B9.2.3 of the 5084 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5085 // neater. So by fiat, these values are UNPREDICTABLE: 5086 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5087 return MCDisassembler::Fail; 5088 5089 Inst.addOperand(MCOperand::createImm(Val)); 5090 return MCDisassembler::Success; 5091 } 5092 5093 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5094 uint64_t Address, 5095 const MCDisassembler *Decoder) { 5096 DecodeStatus S = MCDisassembler::Success; 5097 5098 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5099 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5100 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5101 5102 if (Rn == 0xF) 5103 S = MCDisassembler::SoftFail; 5104 5105 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5106 return MCDisassembler::Fail; 5107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5108 return MCDisassembler::Fail; 5109 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5110 return MCDisassembler::Fail; 5111 5112 return S; 5113 } 5114 5115 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5116 uint64_t Address, 5117 const MCDisassembler *Decoder) { 5118 DecodeStatus S = MCDisassembler::Success; 5119 5120 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5121 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5122 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5123 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5124 5125 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5126 return MCDisassembler::Fail; 5127 5128 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5129 S = MCDisassembler::SoftFail; 5130 5131 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5134 return MCDisassembler::Fail; 5135 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5136 return MCDisassembler::Fail; 5137 5138 return S; 5139 } 5140 5141 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5142 uint64_t Address, 5143 const MCDisassembler *Decoder) { 5144 DecodeStatus S = MCDisassembler::Success; 5145 5146 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5147 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5148 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5149 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5150 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5151 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5152 5153 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5154 5155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5156 return MCDisassembler::Fail; 5157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5158 return MCDisassembler::Fail; 5159 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5160 return MCDisassembler::Fail; 5161 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5162 return MCDisassembler::Fail; 5163 5164 return S; 5165 } 5166 5167 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5168 uint64_t Address, 5169 const MCDisassembler *Decoder) { 5170 DecodeStatus S = MCDisassembler::Success; 5171 5172 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5173 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5174 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5175 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5176 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5177 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5178 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5179 5180 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5181 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5182 5183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5184 return MCDisassembler::Fail; 5185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5186 return MCDisassembler::Fail; 5187 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5188 return MCDisassembler::Fail; 5189 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5190 return MCDisassembler::Fail; 5191 5192 return S; 5193 } 5194 5195 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5196 uint64_t Address, 5197 const MCDisassembler *Decoder) { 5198 DecodeStatus S = MCDisassembler::Success; 5199 5200 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5201 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5202 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5203 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5204 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5205 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5206 5207 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5208 5209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5212 return MCDisassembler::Fail; 5213 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5214 return MCDisassembler::Fail; 5215 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5216 return MCDisassembler::Fail; 5217 5218 return S; 5219 } 5220 5221 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5222 uint64_t Address, 5223 const MCDisassembler *Decoder) { 5224 DecodeStatus S = MCDisassembler::Success; 5225 5226 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5227 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5228 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5229 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5230 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5231 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5232 5233 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5234 5235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5238 return MCDisassembler::Fail; 5239 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5240 return MCDisassembler::Fail; 5241 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5242 return MCDisassembler::Fail; 5243 5244 return S; 5245 } 5246 5247 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5248 const MCDisassembler *Decoder) { 5249 DecodeStatus S = MCDisassembler::Success; 5250 5251 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5252 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5253 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5254 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5255 unsigned size = fieldFromInstruction(Insn, 10, 2); 5256 5257 unsigned align = 0; 5258 unsigned index = 0; 5259 switch (size) { 5260 default: 5261 return MCDisassembler::Fail; 5262 case 0: 5263 if (fieldFromInstruction(Insn, 4, 1)) 5264 return MCDisassembler::Fail; // UNDEFINED 5265 index = fieldFromInstruction(Insn, 5, 3); 5266 break; 5267 case 1: 5268 if (fieldFromInstruction(Insn, 5, 1)) 5269 return MCDisassembler::Fail; // UNDEFINED 5270 index = fieldFromInstruction(Insn, 6, 2); 5271 if (fieldFromInstruction(Insn, 4, 1)) 5272 align = 2; 5273 break; 5274 case 2: 5275 if (fieldFromInstruction(Insn, 6, 1)) 5276 return MCDisassembler::Fail; // UNDEFINED 5277 index = fieldFromInstruction(Insn, 7, 1); 5278 5279 switch (fieldFromInstruction(Insn, 4, 2)) { 5280 case 0 : 5281 align = 0; break; 5282 case 3: 5283 align = 4; break; 5284 default: 5285 return MCDisassembler::Fail; 5286 } 5287 break; 5288 } 5289 5290 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5291 return MCDisassembler::Fail; 5292 if (Rm != 0xF) { // Writeback 5293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5294 return MCDisassembler::Fail; 5295 } 5296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5297 return MCDisassembler::Fail; 5298 Inst.addOperand(MCOperand::createImm(align)); 5299 if (Rm != 0xF) { 5300 if (Rm != 0xD) { 5301 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5302 return MCDisassembler::Fail; 5303 } else 5304 Inst.addOperand(MCOperand::createReg(0)); 5305 } 5306 5307 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 Inst.addOperand(MCOperand::createImm(index)); 5310 5311 return S; 5312 } 5313 5314 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5315 const MCDisassembler *Decoder) { 5316 DecodeStatus S = MCDisassembler::Success; 5317 5318 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5319 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5320 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5321 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5322 unsigned size = fieldFromInstruction(Insn, 10, 2); 5323 5324 unsigned align = 0; 5325 unsigned index = 0; 5326 switch (size) { 5327 default: 5328 return MCDisassembler::Fail; 5329 case 0: 5330 if (fieldFromInstruction(Insn, 4, 1)) 5331 return MCDisassembler::Fail; // UNDEFINED 5332 index = fieldFromInstruction(Insn, 5, 3); 5333 break; 5334 case 1: 5335 if (fieldFromInstruction(Insn, 5, 1)) 5336 return MCDisassembler::Fail; // UNDEFINED 5337 index = fieldFromInstruction(Insn, 6, 2); 5338 if (fieldFromInstruction(Insn, 4, 1)) 5339 align = 2; 5340 break; 5341 case 2: 5342 if (fieldFromInstruction(Insn, 6, 1)) 5343 return MCDisassembler::Fail; // UNDEFINED 5344 index = fieldFromInstruction(Insn, 7, 1); 5345 5346 switch (fieldFromInstruction(Insn, 4, 2)) { 5347 case 0: 5348 align = 0; break; 5349 case 3: 5350 align = 4; break; 5351 default: 5352 return MCDisassembler::Fail; 5353 } 5354 break; 5355 } 5356 5357 if (Rm != 0xF) { // Writeback 5358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5359 return MCDisassembler::Fail; 5360 } 5361 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5362 return MCDisassembler::Fail; 5363 Inst.addOperand(MCOperand::createImm(align)); 5364 if (Rm != 0xF) { 5365 if (Rm != 0xD) { 5366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5367 return MCDisassembler::Fail; 5368 } else 5369 Inst.addOperand(MCOperand::createReg(0)); 5370 } 5371 5372 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5373 return MCDisassembler::Fail; 5374 Inst.addOperand(MCOperand::createImm(index)); 5375 5376 return S; 5377 } 5378 5379 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5380 const MCDisassembler *Decoder) { 5381 DecodeStatus S = MCDisassembler::Success; 5382 5383 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5384 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5385 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5386 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5387 unsigned size = fieldFromInstruction(Insn, 10, 2); 5388 5389 unsigned align = 0; 5390 unsigned index = 0; 5391 unsigned inc = 1; 5392 switch (size) { 5393 default: 5394 return MCDisassembler::Fail; 5395 case 0: 5396 index = fieldFromInstruction(Insn, 5, 3); 5397 if (fieldFromInstruction(Insn, 4, 1)) 5398 align = 2; 5399 break; 5400 case 1: 5401 index = fieldFromInstruction(Insn, 6, 2); 5402 if (fieldFromInstruction(Insn, 4, 1)) 5403 align = 4; 5404 if (fieldFromInstruction(Insn, 5, 1)) 5405 inc = 2; 5406 break; 5407 case 2: 5408 if (fieldFromInstruction(Insn, 5, 1)) 5409 return MCDisassembler::Fail; // UNDEFINED 5410 index = fieldFromInstruction(Insn, 7, 1); 5411 if (fieldFromInstruction(Insn, 4, 1) != 0) 5412 align = 8; 5413 if (fieldFromInstruction(Insn, 6, 1)) 5414 inc = 2; 5415 break; 5416 } 5417 5418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5419 return MCDisassembler::Fail; 5420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 if (Rm != 0xF) { // Writeback 5423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 } 5426 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5427 return MCDisassembler::Fail; 5428 Inst.addOperand(MCOperand::createImm(align)); 5429 if (Rm != 0xF) { 5430 if (Rm != 0xD) { 5431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5432 return MCDisassembler::Fail; 5433 } else 5434 Inst.addOperand(MCOperand::createReg(0)); 5435 } 5436 5437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5438 return MCDisassembler::Fail; 5439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5440 return MCDisassembler::Fail; 5441 Inst.addOperand(MCOperand::createImm(index)); 5442 5443 return S; 5444 } 5445 5446 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5447 const MCDisassembler *Decoder) { 5448 DecodeStatus S = MCDisassembler::Success; 5449 5450 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5451 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5452 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5453 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5454 unsigned size = fieldFromInstruction(Insn, 10, 2); 5455 5456 unsigned align = 0; 5457 unsigned index = 0; 5458 unsigned inc = 1; 5459 switch (size) { 5460 default: 5461 return MCDisassembler::Fail; 5462 case 0: 5463 index = fieldFromInstruction(Insn, 5, 3); 5464 if (fieldFromInstruction(Insn, 4, 1)) 5465 align = 2; 5466 break; 5467 case 1: 5468 index = fieldFromInstruction(Insn, 6, 2); 5469 if (fieldFromInstruction(Insn, 4, 1)) 5470 align = 4; 5471 if (fieldFromInstruction(Insn, 5, 1)) 5472 inc = 2; 5473 break; 5474 case 2: 5475 if (fieldFromInstruction(Insn, 5, 1)) 5476 return MCDisassembler::Fail; // UNDEFINED 5477 index = fieldFromInstruction(Insn, 7, 1); 5478 if (fieldFromInstruction(Insn, 4, 1) != 0) 5479 align = 8; 5480 if (fieldFromInstruction(Insn, 6, 1)) 5481 inc = 2; 5482 break; 5483 } 5484 5485 if (Rm != 0xF) { // Writeback 5486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 } 5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5490 return MCDisassembler::Fail; 5491 Inst.addOperand(MCOperand::createImm(align)); 5492 if (Rm != 0xF) { 5493 if (Rm != 0xD) { 5494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5495 return MCDisassembler::Fail; 5496 } else 5497 Inst.addOperand(MCOperand::createReg(0)); 5498 } 5499 5500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5501 return MCDisassembler::Fail; 5502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5503 return MCDisassembler::Fail; 5504 Inst.addOperand(MCOperand::createImm(index)); 5505 5506 return S; 5507 } 5508 5509 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5510 const MCDisassembler *Decoder) { 5511 DecodeStatus S = MCDisassembler::Success; 5512 5513 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5514 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5515 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5516 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5517 unsigned size = fieldFromInstruction(Insn, 10, 2); 5518 5519 unsigned align = 0; 5520 unsigned index = 0; 5521 unsigned inc = 1; 5522 switch (size) { 5523 default: 5524 return MCDisassembler::Fail; 5525 case 0: 5526 if (fieldFromInstruction(Insn, 4, 1)) 5527 return MCDisassembler::Fail; // UNDEFINED 5528 index = fieldFromInstruction(Insn, 5, 3); 5529 break; 5530 case 1: 5531 if (fieldFromInstruction(Insn, 4, 1)) 5532 return MCDisassembler::Fail; // UNDEFINED 5533 index = fieldFromInstruction(Insn, 6, 2); 5534 if (fieldFromInstruction(Insn, 5, 1)) 5535 inc = 2; 5536 break; 5537 case 2: 5538 if (fieldFromInstruction(Insn, 4, 2)) 5539 return MCDisassembler::Fail; // UNDEFINED 5540 index = fieldFromInstruction(Insn, 7, 1); 5541 if (fieldFromInstruction(Insn, 6, 1)) 5542 inc = 2; 5543 break; 5544 } 5545 5546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5547 return MCDisassembler::Fail; 5548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5549 return MCDisassembler::Fail; 5550 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5551 return MCDisassembler::Fail; 5552 5553 if (Rm != 0xF) { // Writeback 5554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5555 return MCDisassembler::Fail; 5556 } 5557 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5558 return MCDisassembler::Fail; 5559 Inst.addOperand(MCOperand::createImm(align)); 5560 if (Rm != 0xF) { 5561 if (Rm != 0xD) { 5562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5563 return MCDisassembler::Fail; 5564 } else 5565 Inst.addOperand(MCOperand::createReg(0)); 5566 } 5567 5568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5573 return MCDisassembler::Fail; 5574 Inst.addOperand(MCOperand::createImm(index)); 5575 5576 return S; 5577 } 5578 5579 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5580 const MCDisassembler *Decoder) { 5581 DecodeStatus S = MCDisassembler::Success; 5582 5583 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5584 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5585 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5586 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5587 unsigned size = fieldFromInstruction(Insn, 10, 2); 5588 5589 unsigned align = 0; 5590 unsigned index = 0; 5591 unsigned inc = 1; 5592 switch (size) { 5593 default: 5594 return MCDisassembler::Fail; 5595 case 0: 5596 if (fieldFromInstruction(Insn, 4, 1)) 5597 return MCDisassembler::Fail; // UNDEFINED 5598 index = fieldFromInstruction(Insn, 5, 3); 5599 break; 5600 case 1: 5601 if (fieldFromInstruction(Insn, 4, 1)) 5602 return MCDisassembler::Fail; // UNDEFINED 5603 index = fieldFromInstruction(Insn, 6, 2); 5604 if (fieldFromInstruction(Insn, 5, 1)) 5605 inc = 2; 5606 break; 5607 case 2: 5608 if (fieldFromInstruction(Insn, 4, 2)) 5609 return MCDisassembler::Fail; // UNDEFINED 5610 index = fieldFromInstruction(Insn, 7, 1); 5611 if (fieldFromInstruction(Insn, 6, 1)) 5612 inc = 2; 5613 break; 5614 } 5615 5616 if (Rm != 0xF) { // Writeback 5617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5618 return MCDisassembler::Fail; 5619 } 5620 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5621 return MCDisassembler::Fail; 5622 Inst.addOperand(MCOperand::createImm(align)); 5623 if (Rm != 0xF) { 5624 if (Rm != 0xD) { 5625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5626 return MCDisassembler::Fail; 5627 } else 5628 Inst.addOperand(MCOperand::createReg(0)); 5629 } 5630 5631 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5632 return MCDisassembler::Fail; 5633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5634 return MCDisassembler::Fail; 5635 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5636 return MCDisassembler::Fail; 5637 Inst.addOperand(MCOperand::createImm(index)); 5638 5639 return S; 5640 } 5641 5642 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5643 const MCDisassembler *Decoder) { 5644 DecodeStatus S = MCDisassembler::Success; 5645 5646 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5647 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5648 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5649 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5650 unsigned size = fieldFromInstruction(Insn, 10, 2); 5651 5652 unsigned align = 0; 5653 unsigned index = 0; 5654 unsigned inc = 1; 5655 switch (size) { 5656 default: 5657 return MCDisassembler::Fail; 5658 case 0: 5659 if (fieldFromInstruction(Insn, 4, 1)) 5660 align = 4; 5661 index = fieldFromInstruction(Insn, 5, 3); 5662 break; 5663 case 1: 5664 if (fieldFromInstruction(Insn, 4, 1)) 5665 align = 8; 5666 index = fieldFromInstruction(Insn, 6, 2); 5667 if (fieldFromInstruction(Insn, 5, 1)) 5668 inc = 2; 5669 break; 5670 case 2: 5671 switch (fieldFromInstruction(Insn, 4, 2)) { 5672 case 0: 5673 align = 0; break; 5674 case 3: 5675 return MCDisassembler::Fail; 5676 default: 5677 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5678 } 5679 5680 index = fieldFromInstruction(Insn, 7, 1); 5681 if (fieldFromInstruction(Insn, 6, 1)) 5682 inc = 2; 5683 break; 5684 } 5685 5686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5687 return MCDisassembler::Fail; 5688 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5689 return MCDisassembler::Fail; 5690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5691 return MCDisassembler::Fail; 5692 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5693 return MCDisassembler::Fail; 5694 5695 if (Rm != 0xF) { // Writeback 5696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5697 return MCDisassembler::Fail; 5698 } 5699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5700 return MCDisassembler::Fail; 5701 Inst.addOperand(MCOperand::createImm(align)); 5702 if (Rm != 0xF) { 5703 if (Rm != 0xD) { 5704 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5705 return MCDisassembler::Fail; 5706 } else 5707 Inst.addOperand(MCOperand::createReg(0)); 5708 } 5709 5710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5711 return MCDisassembler::Fail; 5712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5713 return MCDisassembler::Fail; 5714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5715 return MCDisassembler::Fail; 5716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5717 return MCDisassembler::Fail; 5718 Inst.addOperand(MCOperand::createImm(index)); 5719 5720 return S; 5721 } 5722 5723 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5724 const MCDisassembler *Decoder) { 5725 DecodeStatus S = MCDisassembler::Success; 5726 5727 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5728 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5729 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5730 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5731 unsigned size = fieldFromInstruction(Insn, 10, 2); 5732 5733 unsigned align = 0; 5734 unsigned index = 0; 5735 unsigned inc = 1; 5736 switch (size) { 5737 default: 5738 return MCDisassembler::Fail; 5739 case 0: 5740 if (fieldFromInstruction(Insn, 4, 1)) 5741 align = 4; 5742 index = fieldFromInstruction(Insn, 5, 3); 5743 break; 5744 case 1: 5745 if (fieldFromInstruction(Insn, 4, 1)) 5746 align = 8; 5747 index = fieldFromInstruction(Insn, 6, 2); 5748 if (fieldFromInstruction(Insn, 5, 1)) 5749 inc = 2; 5750 break; 5751 case 2: 5752 switch (fieldFromInstruction(Insn, 4, 2)) { 5753 case 0: 5754 align = 0; break; 5755 case 3: 5756 return MCDisassembler::Fail; 5757 default: 5758 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5759 } 5760 5761 index = fieldFromInstruction(Insn, 7, 1); 5762 if (fieldFromInstruction(Insn, 6, 1)) 5763 inc = 2; 5764 break; 5765 } 5766 5767 if (Rm != 0xF) { // Writeback 5768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5769 return MCDisassembler::Fail; 5770 } 5771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5772 return MCDisassembler::Fail; 5773 Inst.addOperand(MCOperand::createImm(align)); 5774 if (Rm != 0xF) { 5775 if (Rm != 0xD) { 5776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5777 return MCDisassembler::Fail; 5778 } else 5779 Inst.addOperand(MCOperand::createReg(0)); 5780 } 5781 5782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5785 return MCDisassembler::Fail; 5786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5787 return MCDisassembler::Fail; 5788 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5789 return MCDisassembler::Fail; 5790 Inst.addOperand(MCOperand::createImm(index)); 5791 5792 return S; 5793 } 5794 5795 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5796 const MCDisassembler *Decoder) { 5797 DecodeStatus S = MCDisassembler::Success; 5798 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5799 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5800 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5801 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5802 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5803 5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5805 S = MCDisassembler::SoftFail; 5806 5807 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5808 return MCDisassembler::Fail; 5809 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5810 return MCDisassembler::Fail; 5811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5812 return MCDisassembler::Fail; 5813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5814 return MCDisassembler::Fail; 5815 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5816 return MCDisassembler::Fail; 5817 5818 return S; 5819 } 5820 5821 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5822 const MCDisassembler *Decoder) { 5823 DecodeStatus S = MCDisassembler::Success; 5824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5825 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5826 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5827 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5828 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5829 5830 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5831 S = MCDisassembler::SoftFail; 5832 5833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5834 return MCDisassembler::Fail; 5835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5836 return MCDisassembler::Fail; 5837 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5838 return MCDisassembler::Fail; 5839 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5842 return MCDisassembler::Fail; 5843 5844 return S; 5845 } 5846 5847 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5848 const MCDisassembler *Decoder) { 5849 DecodeStatus S = MCDisassembler::Success; 5850 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5851 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5852 5853 if (pred == 0xF) { 5854 pred = 0xE; 5855 S = MCDisassembler::SoftFail; 5856 } 5857 5858 if (mask == 0x0) 5859 return MCDisassembler::Fail; 5860 5861 // IT masks are encoded as a sequence of replacement low-order bits 5862 // for the condition code. So if the low bit of the starting 5863 // condition code is 1, then we have to flip all the bits above the 5864 // terminating bit (which is the lowest 1 bit). 5865 if (pred & 1) { 5866 unsigned LowBit = mask & -mask; 5867 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5868 mask ^= BitsAboveLowBit; 5869 } 5870 5871 Inst.addOperand(MCOperand::createImm(pred)); 5872 Inst.addOperand(MCOperand::createImm(mask)); 5873 return S; 5874 } 5875 5876 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5877 uint64_t Address, 5878 const MCDisassembler *Decoder) { 5879 DecodeStatus S = MCDisassembler::Success; 5880 5881 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5882 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5883 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5884 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5885 unsigned W = fieldFromInstruction(Insn, 21, 1); 5886 unsigned U = fieldFromInstruction(Insn, 23, 1); 5887 unsigned P = fieldFromInstruction(Insn, 24, 1); 5888 bool writeback = (W == 1) | (P == 0); 5889 5890 addr |= (U << 8) | (Rn << 9); 5891 5892 if (writeback && (Rn == Rt || Rn == Rt2)) 5893 Check(S, MCDisassembler::SoftFail); 5894 if (Rt == Rt2) 5895 Check(S, MCDisassembler::SoftFail); 5896 5897 // Rt 5898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5899 return MCDisassembler::Fail; 5900 // Rt2 5901 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5902 return MCDisassembler::Fail; 5903 // Writeback operand 5904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5905 return MCDisassembler::Fail; 5906 // addr 5907 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5908 return MCDisassembler::Fail; 5909 5910 return S; 5911 } 5912 5913 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5914 uint64_t Address, 5915 const MCDisassembler *Decoder) { 5916 DecodeStatus S = MCDisassembler::Success; 5917 5918 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5919 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5920 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5921 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5922 unsigned W = fieldFromInstruction(Insn, 21, 1); 5923 unsigned U = fieldFromInstruction(Insn, 23, 1); 5924 unsigned P = fieldFromInstruction(Insn, 24, 1); 5925 bool writeback = (W == 1) | (P == 0); 5926 5927 addr |= (U << 8) | (Rn << 9); 5928 5929 if (writeback && (Rn == Rt || Rn == Rt2)) 5930 Check(S, MCDisassembler::SoftFail); 5931 5932 // Writeback operand 5933 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5934 return MCDisassembler::Fail; 5935 // Rt 5936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5937 return MCDisassembler::Fail; 5938 // Rt2 5939 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5940 return MCDisassembler::Fail; 5941 // addr 5942 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5943 return MCDisassembler::Fail; 5944 5945 return S; 5946 } 5947 5948 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5949 const MCDisassembler *Decoder) { 5950 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5951 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5952 if (sign1 != sign2) return MCDisassembler::Fail; 5953 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5954 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5955 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5956 5957 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5958 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5959 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5960 // If sign, then it is decreasing the address. 5961 if (sign1) { 5962 // Following ARMv7 Architecture Manual, when the offset 5963 // is zero, it is decoded as a subw, not as a adr.w 5964 if (!Val) { 5965 Inst.setOpcode(ARM::t2SUBri12); 5966 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5967 } else 5968 Val = -Val; 5969 } 5970 Inst.addOperand(MCOperand::createImm(Val)); 5971 return S; 5972 } 5973 5974 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5975 uint64_t Address, 5976 const MCDisassembler *Decoder) { 5977 DecodeStatus S = MCDisassembler::Success; 5978 5979 // Shift of "asr #32" is not allowed in Thumb2 mode. 5980 if (Val == 0x20) S = MCDisassembler::Fail; 5981 Inst.addOperand(MCOperand::createImm(Val)); 5982 return S; 5983 } 5984 5985 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5986 const MCDisassembler *Decoder) { 5987 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5988 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5989 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5990 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5991 5992 if (pred == 0xF) 5993 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5994 5995 DecodeStatus S = MCDisassembler::Success; 5996 5997 if (Rt == Rn || Rn == Rt2) 5998 S = MCDisassembler::SoftFail; 5999 6000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6001 return MCDisassembler::Fail; 6002 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6003 return MCDisassembler::Fail; 6004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6005 return MCDisassembler::Fail; 6006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6007 return MCDisassembler::Fail; 6008 6009 return S; 6010 } 6011 6012 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6013 const MCDisassembler *Decoder) { 6014 const FeatureBitset &featureBits = 6015 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6016 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6017 6018 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6019 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6020 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6021 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6022 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6023 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6024 unsigned op = fieldFromInstruction(Insn, 5, 1); 6025 6026 DecodeStatus S = MCDisassembler::Success; 6027 6028 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6029 if (!(imm & 0x38)) { 6030 if (cmode == 0xF) { 6031 if (op == 1) return MCDisassembler::Fail; 6032 Inst.setOpcode(ARM::VMOVv2f32); 6033 } 6034 if (hasFullFP16) { 6035 if (cmode == 0xE) { 6036 if (op == 1) { 6037 Inst.setOpcode(ARM::VMOVv1i64); 6038 } else { 6039 Inst.setOpcode(ARM::VMOVv8i8); 6040 } 6041 } 6042 if (cmode == 0xD) { 6043 if (op == 1) { 6044 Inst.setOpcode(ARM::VMVNv2i32); 6045 } else { 6046 Inst.setOpcode(ARM::VMOVv2i32); 6047 } 6048 } 6049 if (cmode == 0xC) { 6050 if (op == 1) { 6051 Inst.setOpcode(ARM::VMVNv2i32); 6052 } else { 6053 Inst.setOpcode(ARM::VMOVv2i32); 6054 } 6055 } 6056 } 6057 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6058 } 6059 6060 if (!(imm & 0x20)) return MCDisassembler::Fail; 6061 6062 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6063 return MCDisassembler::Fail; 6064 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6065 return MCDisassembler::Fail; 6066 Inst.addOperand(MCOperand::createImm(64 - imm)); 6067 6068 return S; 6069 } 6070 6071 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6072 const MCDisassembler *Decoder) { 6073 const FeatureBitset &featureBits = 6074 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6075 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6076 6077 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6078 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6079 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6080 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6081 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6082 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6083 unsigned op = fieldFromInstruction(Insn, 5, 1); 6084 6085 DecodeStatus S = MCDisassembler::Success; 6086 6087 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6088 if (!(imm & 0x38)) { 6089 if (cmode == 0xF) { 6090 if (op == 1) return MCDisassembler::Fail; 6091 Inst.setOpcode(ARM::VMOVv4f32); 6092 } 6093 if (hasFullFP16) { 6094 if (cmode == 0xE) { 6095 if (op == 1) { 6096 Inst.setOpcode(ARM::VMOVv2i64); 6097 } else { 6098 Inst.setOpcode(ARM::VMOVv16i8); 6099 } 6100 } 6101 if (cmode == 0xD) { 6102 if (op == 1) { 6103 Inst.setOpcode(ARM::VMVNv4i32); 6104 } else { 6105 Inst.setOpcode(ARM::VMOVv4i32); 6106 } 6107 } 6108 if (cmode == 0xC) { 6109 if (op == 1) { 6110 Inst.setOpcode(ARM::VMVNv4i32); 6111 } else { 6112 Inst.setOpcode(ARM::VMOVv4i32); 6113 } 6114 } 6115 } 6116 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6117 } 6118 6119 if (!(imm & 0x20)) return MCDisassembler::Fail; 6120 6121 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6122 return MCDisassembler::Fail; 6123 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6124 return MCDisassembler::Fail; 6125 Inst.addOperand(MCOperand::createImm(64 - imm)); 6126 6127 return S; 6128 } 6129 6130 static DecodeStatus 6131 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6132 uint64_t Address, 6133 const MCDisassembler *Decoder) { 6134 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6135 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6136 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6137 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6138 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6139 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6140 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6141 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6142 6143 DecodeStatus S = MCDisassembler::Success; 6144 6145 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6146 6147 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6148 return MCDisassembler::Fail; 6149 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6150 return MCDisassembler::Fail; 6151 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6152 return MCDisassembler::Fail; 6153 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6154 return MCDisassembler::Fail; 6155 // The lane index does not have any bits in the encoding, because it can only 6156 // be 0. 6157 Inst.addOperand(MCOperand::createImm(0)); 6158 Inst.addOperand(MCOperand::createImm(rotate)); 6159 6160 return S; 6161 } 6162 6163 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6164 const MCDisassembler *Decoder) { 6165 DecodeStatus S = MCDisassembler::Success; 6166 6167 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6168 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6169 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6170 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6171 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6172 6173 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6174 S = MCDisassembler::SoftFail; 6175 6176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6177 return MCDisassembler::Fail; 6178 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6179 return MCDisassembler::Fail; 6180 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6181 return MCDisassembler::Fail; 6182 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6183 return MCDisassembler::Fail; 6184 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6185 return MCDisassembler::Fail; 6186 6187 return S; 6188 } 6189 6190 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6191 uint64_t Address, 6192 const MCDisassembler *Decoder) { 6193 DecodeStatus S = MCDisassembler::Success; 6194 6195 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6196 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6197 unsigned cop = fieldFromInstruction(Val, 8, 4); 6198 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6199 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6200 6201 if ((cop & ~0x1) == 0xa) 6202 return MCDisassembler::Fail; 6203 6204 if (Rt == Rt2) 6205 S = MCDisassembler::SoftFail; 6206 6207 // We have to check if the instruction is MRRC2 6208 // or MCRR2 when constructing the operands for 6209 // Inst. Reason is because MRRC2 stores to two 6210 // registers so it's tablegen desc has two 6211 // outputs whereas MCRR doesn't store to any 6212 // registers so all of it's operands are listed 6213 // as inputs, therefore the operand order for 6214 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6215 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6216 6217 if (Inst.getOpcode() == ARM::MRRC2) { 6218 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6219 return MCDisassembler::Fail; 6220 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6221 return MCDisassembler::Fail; 6222 } 6223 Inst.addOperand(MCOperand::createImm(cop)); 6224 Inst.addOperand(MCOperand::createImm(opc1)); 6225 if (Inst.getOpcode() == ARM::MCRR2) { 6226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6227 return MCDisassembler::Fail; 6228 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6229 return MCDisassembler::Fail; 6230 } 6231 Inst.addOperand(MCOperand::createImm(CRm)); 6232 6233 return S; 6234 } 6235 6236 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6237 uint64_t Address, 6238 const MCDisassembler *Decoder) { 6239 const FeatureBitset &featureBits = 6240 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6241 DecodeStatus S = MCDisassembler::Success; 6242 6243 // Add explicit operand for the destination sysreg, for cases where 6244 // we have to model it for code generation purposes. 6245 switch (Inst.getOpcode()) { 6246 case ARM::VMSR_FPSCR_NZCVQC: 6247 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6248 break; 6249 case ARM::VMSR_P0: 6250 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6251 break; 6252 } 6253 6254 if (Inst.getOpcode() != ARM::FMSTAT) { 6255 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6256 6257 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6258 if (Rt == 13 || Rt == 15) 6259 S = MCDisassembler::SoftFail; 6260 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6261 } else 6262 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6263 } 6264 6265 // Add explicit operand for the source sysreg, similarly to above. 6266 switch (Inst.getOpcode()) { 6267 case ARM::VMRS_FPSCR_NZCVQC: 6268 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6269 break; 6270 case ARM::VMRS_P0: 6271 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6272 break; 6273 } 6274 6275 if (featureBits[ARM::ModeThumb]) { 6276 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6277 Inst.addOperand(MCOperand::createReg(0)); 6278 } else { 6279 unsigned pred = fieldFromInstruction(Val, 28, 4); 6280 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6281 return MCDisassembler::Fail; 6282 } 6283 6284 return S; 6285 } 6286 6287 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6288 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6289 uint64_t Address, 6290 const MCDisassembler *Decoder) { 6291 DecodeStatus S = MCDisassembler::Success; 6292 if (Val == 0 && !zeroPermitted) 6293 S = MCDisassembler::Fail; 6294 6295 uint64_t DecVal; 6296 if (isSigned) 6297 DecVal = SignExtend32<size + 1>(Val << 1); 6298 else 6299 DecVal = (Val << 1); 6300 6301 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6302 Decoder)) 6303 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6304 return S; 6305 } 6306 6307 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6308 uint64_t Address, 6309 const MCDisassembler *Decoder) { 6310 6311 uint64_t LocImm = Inst.getOperand(0).getImm(); 6312 Val = LocImm + (2 << Val); 6313 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6314 Decoder)) 6315 Inst.addOperand(MCOperand::createImm(Val)); 6316 return MCDisassembler::Success; 6317 } 6318 6319 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6320 uint64_t Address, 6321 const MCDisassembler *Decoder) { 6322 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6323 return MCDisassembler::Fail; 6324 Inst.addOperand(MCOperand::createImm(Val)); 6325 return MCDisassembler::Success; 6326 } 6327 6328 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6329 const MCDisassembler *Decoder) { 6330 DecodeStatus S = MCDisassembler::Success; 6331 6332 if (Inst.getOpcode() == ARM::MVE_LCTP) 6333 return S; 6334 6335 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6336 fieldFromInstruction(Insn, 1, 10) << 1; 6337 switch (Inst.getOpcode()) { 6338 case ARM::t2LEUpdate: 6339 case ARM::MVE_LETP: 6340 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6341 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6342 [[fallthrough]]; 6343 case ARM::t2LE: 6344 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6345 Inst, Imm, Address, Decoder))) 6346 return MCDisassembler::Fail; 6347 break; 6348 case ARM::t2WLS: 6349 case ARM::MVE_WLSTP_8: 6350 case ARM::MVE_WLSTP_16: 6351 case ARM::MVE_WLSTP_32: 6352 case ARM::MVE_WLSTP_64: 6353 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6354 if (!Check(S, 6355 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6356 Address, Decoder)) || 6357 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6358 Inst, Imm, Address, Decoder))) 6359 return MCDisassembler::Fail; 6360 break; 6361 case ARM::t2DLS: 6362 case ARM::MVE_DLSTP_8: 6363 case ARM::MVE_DLSTP_16: 6364 case ARM::MVE_DLSTP_32: 6365 case ARM::MVE_DLSTP_64: 6366 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6367 if (Rn == 0xF) { 6368 // Enforce all the rest of the instruction bits in LCTP, which 6369 // won't have been reliably checked based on LCTP's own tablegen 6370 // record, because we came to this decode by a roundabout route. 6371 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6372 if ((Insn & ~SBZMask) != CanonicalLCTP) 6373 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6374 if (Insn != CanonicalLCTP) 6375 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6376 6377 Inst.setOpcode(ARM::MVE_LCTP); 6378 } else { 6379 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6380 if (!Check(S, DecoderGPRRegisterClass(Inst, 6381 fieldFromInstruction(Insn, 16, 4), 6382 Address, Decoder))) 6383 return MCDisassembler::Fail; 6384 } 6385 break; 6386 } 6387 return S; 6388 } 6389 6390 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6391 uint64_t Address, 6392 const MCDisassembler *Decoder) { 6393 DecodeStatus S = MCDisassembler::Success; 6394 6395 if (Val == 0) 6396 Val = 32; 6397 6398 Inst.addOperand(MCOperand::createImm(Val)); 6399 6400 return S; 6401 } 6402 6403 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6404 uint64_t Address, 6405 const MCDisassembler *Decoder) { 6406 if ((RegNo) + 1 > 11) 6407 return MCDisassembler::Fail; 6408 6409 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6410 Inst.addOperand(MCOperand::createReg(Register)); 6411 return MCDisassembler::Success; 6412 } 6413 6414 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6415 uint64_t Address, 6416 const MCDisassembler *Decoder) { 6417 if ((RegNo) > 14) 6418 return MCDisassembler::Fail; 6419 6420 unsigned Register = GPRDecoderTable[(RegNo)]; 6421 Inst.addOperand(MCOperand::createReg(Register)); 6422 return MCDisassembler::Success; 6423 } 6424 6425 static DecodeStatus 6426 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6427 uint64_t Address, 6428 const MCDisassembler *Decoder) { 6429 if (RegNo == 15) { 6430 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6431 return MCDisassembler::Success; 6432 } 6433 6434 unsigned Register = GPRDecoderTable[RegNo]; 6435 Inst.addOperand(MCOperand::createReg(Register)); 6436 6437 if (RegNo == 13) 6438 return MCDisassembler::SoftFail; 6439 6440 return MCDisassembler::Success; 6441 } 6442 6443 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6444 const MCDisassembler *Decoder) { 6445 DecodeStatus S = MCDisassembler::Success; 6446 6447 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6448 Inst.addOperand(MCOperand::createReg(0)); 6449 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6450 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6451 (fieldFromInstruction(Insn, 12, 4) << 8) | 6452 (fieldFromInstruction(Insn, 22, 1) << 12); 6453 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6454 return MCDisassembler::Fail; 6455 } 6456 } else { 6457 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6458 (fieldFromInstruction(Insn, 22, 1) << 8) | 6459 (fieldFromInstruction(Insn, 12, 4) << 9); 6460 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6461 return MCDisassembler::Fail; 6462 } 6463 } 6464 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6465 6466 return S; 6467 } 6468 6469 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6470 uint64_t Address, 6471 const MCDisassembler *Decoder) { 6472 if (RegNo > 7) 6473 return MCDisassembler::Fail; 6474 6475 unsigned Register = QPRDecoderTable[RegNo]; 6476 Inst.addOperand(MCOperand::createReg(Register)); 6477 return MCDisassembler::Success; 6478 } 6479 6480 static const uint16_t QQPRDecoderTable[] = { 6481 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6482 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6483 }; 6484 6485 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6486 uint64_t Address, 6487 const MCDisassembler *Decoder) { 6488 if (RegNo > 6) 6489 return MCDisassembler::Fail; 6490 6491 unsigned Register = QQPRDecoderTable[RegNo]; 6492 Inst.addOperand(MCOperand::createReg(Register)); 6493 return MCDisassembler::Success; 6494 } 6495 6496 static const uint16_t QQQQPRDecoderTable[] = { 6497 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6498 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6499 }; 6500 6501 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6502 uint64_t Address, 6503 const MCDisassembler *Decoder) { 6504 if (RegNo > 4) 6505 return MCDisassembler::Fail; 6506 6507 unsigned Register = QQQQPRDecoderTable[RegNo]; 6508 Inst.addOperand(MCOperand::createReg(Register)); 6509 return MCDisassembler::Success; 6510 } 6511 6512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6513 uint64_t Address, 6514 const MCDisassembler *Decoder) { 6515 DecodeStatus S = MCDisassembler::Success; 6516 6517 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6518 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6519 // 't' as 0 and finish with a 1. 6520 unsigned Imm = 0; 6521 // We always start with a 't'. 6522 unsigned CurBit = 0; 6523 for (int i = 3; i >= 0; --i) { 6524 // If the bit we are looking at is not the same as last one, invert the 6525 // CurBit, if it is the same leave it as is. 6526 CurBit ^= (Val >> i) & 1U; 6527 6528 // Encode the CurBit at the right place in the immediate. 6529 Imm |= (CurBit << i); 6530 6531 // If we are done, finish the encoding with a 1. 6532 if ((Val & ~(~0U << i)) == 0) { 6533 Imm |= 1U << i; 6534 break; 6535 } 6536 } 6537 6538 Inst.addOperand(MCOperand::createImm(Imm)); 6539 6540 return S; 6541 } 6542 6543 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6544 uint64_t Address, 6545 const MCDisassembler *Decoder) { 6546 // The vpred_r operand type includes an MQPR register field derived 6547 // from the encoding. But we don't actually want to add an operand 6548 // to the MCInst at this stage, because AddThumbPredicate will do it 6549 // later, and will infer the register number from the TIED_TO 6550 // constraint. So this is a deliberately empty decoder method that 6551 // will inhibit the auto-generated disassembly code from adding an 6552 // operand at all. 6553 return MCDisassembler::Success; 6554 } 6555 6556 [[maybe_unused]] static DecodeStatus 6557 DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, 6558 const MCDisassembler *Decoder) { 6559 // Similar to above, we want to ensure that no operands are added for the 6560 // vpred operands. (This is marked "maybe_unused" for the moment; because 6561 // DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6562 // the decoder doesn't actually call it yet. That will be addressed in a 6563 // future change.) 6564 return MCDisassembler::Success; 6565 } 6566 6567 static DecodeStatus 6568 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6569 const MCDisassembler *Decoder) { 6570 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6571 return MCDisassembler::Success; 6572 } 6573 6574 static DecodeStatus 6575 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6576 const MCDisassembler *Decoder) { 6577 unsigned Code; 6578 switch (Val & 0x3) { 6579 case 0: 6580 Code = ARMCC::GE; 6581 break; 6582 case 1: 6583 Code = ARMCC::LT; 6584 break; 6585 case 2: 6586 Code = ARMCC::GT; 6587 break; 6588 case 3: 6589 Code = ARMCC::LE; 6590 break; 6591 } 6592 Inst.addOperand(MCOperand::createImm(Code)); 6593 return MCDisassembler::Success; 6594 } 6595 6596 static DecodeStatus 6597 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6598 const MCDisassembler *Decoder) { 6599 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6600 return MCDisassembler::Success; 6601 } 6602 6603 static DecodeStatus 6604 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6605 const MCDisassembler *Decoder) { 6606 unsigned Code; 6607 switch (Val) { 6608 default: 6609 return MCDisassembler::Fail; 6610 case 0: 6611 Code = ARMCC::EQ; 6612 break; 6613 case 1: 6614 Code = ARMCC::NE; 6615 break; 6616 case 4: 6617 Code = ARMCC::GE; 6618 break; 6619 case 5: 6620 Code = ARMCC::LT; 6621 break; 6622 case 6: 6623 Code = ARMCC::GT; 6624 break; 6625 case 7: 6626 Code = ARMCC::LE; 6627 break; 6628 } 6629 6630 Inst.addOperand(MCOperand::createImm(Code)); 6631 return MCDisassembler::Success; 6632 } 6633 6634 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6635 uint64_t Address, 6636 const MCDisassembler *Decoder) { 6637 DecodeStatus S = MCDisassembler::Success; 6638 6639 unsigned DecodedVal = 64 - Val; 6640 6641 switch (Inst.getOpcode()) { 6642 case ARM::MVE_VCVTf16s16_fix: 6643 case ARM::MVE_VCVTs16f16_fix: 6644 case ARM::MVE_VCVTf16u16_fix: 6645 case ARM::MVE_VCVTu16f16_fix: 6646 if (DecodedVal > 16) 6647 return MCDisassembler::Fail; 6648 break; 6649 case ARM::MVE_VCVTf32s32_fix: 6650 case ARM::MVE_VCVTs32f32_fix: 6651 case ARM::MVE_VCVTf32u32_fix: 6652 case ARM::MVE_VCVTu32f32_fix: 6653 if (DecodedVal > 32) 6654 return MCDisassembler::Fail; 6655 break; 6656 } 6657 6658 Inst.addOperand(MCOperand::createImm(64 - Val)); 6659 6660 return S; 6661 } 6662 6663 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6664 switch (Opcode) { 6665 case ARM::VSTR_P0_off: 6666 case ARM::VSTR_P0_pre: 6667 case ARM::VSTR_P0_post: 6668 case ARM::VLDR_P0_off: 6669 case ARM::VLDR_P0_pre: 6670 case ARM::VLDR_P0_post: 6671 return ARM::P0; 6672 default: 6673 return 0; 6674 } 6675 } 6676 6677 template <bool Writeback> 6678 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6679 uint64_t Address, 6680 const MCDisassembler *Decoder) { 6681 switch (Inst.getOpcode()) { 6682 case ARM::VSTR_FPSCR_pre: 6683 case ARM::VSTR_FPSCR_NZCVQC_pre: 6684 case ARM::VLDR_FPSCR_pre: 6685 case ARM::VLDR_FPSCR_NZCVQC_pre: 6686 case ARM::VSTR_FPSCR_off: 6687 case ARM::VSTR_FPSCR_NZCVQC_off: 6688 case ARM::VLDR_FPSCR_off: 6689 case ARM::VLDR_FPSCR_NZCVQC_off: 6690 case ARM::VSTR_FPSCR_post: 6691 case ARM::VSTR_FPSCR_NZCVQC_post: 6692 case ARM::VLDR_FPSCR_post: 6693 case ARM::VLDR_FPSCR_NZCVQC_post: 6694 const FeatureBitset &featureBits = 6695 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6696 6697 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6698 return MCDisassembler::Fail; 6699 } 6700 6701 DecodeStatus S = MCDisassembler::Success; 6702 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6703 Inst.addOperand(MCOperand::createReg(Sysreg)); 6704 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6705 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6706 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6707 6708 if (Writeback) { 6709 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6710 return MCDisassembler::Fail; 6711 } 6712 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6713 return MCDisassembler::Fail; 6714 6715 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6716 Inst.addOperand(MCOperand::createReg(0)); 6717 6718 return S; 6719 } 6720 6721 static inline DecodeStatus 6722 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6723 const MCDisassembler *Decoder, unsigned Rn, 6724 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6725 DecodeStatus S = MCDisassembler::Success; 6726 6727 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6728 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6729 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6730 6731 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6732 return MCDisassembler::Fail; 6733 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6734 return MCDisassembler::Fail; 6735 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6736 return MCDisassembler::Fail; 6737 6738 return S; 6739 } 6740 6741 template <int shift> 6742 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6743 uint64_t Address, 6744 const MCDisassembler *Decoder) { 6745 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6746 fieldFromInstruction(Val, 16, 3), 6747 DecodetGPRRegisterClass, 6748 DecodeTAddrModeImm7<shift>); 6749 } 6750 6751 template <int shift> 6752 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6753 uint64_t Address, 6754 const MCDisassembler *Decoder) { 6755 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6756 fieldFromInstruction(Val, 16, 4), 6757 DecoderGPRRegisterClass, 6758 DecodeT2AddrModeImm7<shift,1>); 6759 } 6760 6761 template <int shift> 6762 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6763 uint64_t Address, 6764 const MCDisassembler *Decoder) { 6765 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6766 fieldFromInstruction(Val, 17, 3), 6767 DecodeMQPRRegisterClass, 6768 DecodeMveAddrModeQ<shift>); 6769 } 6770 6771 template <unsigned MinLog, unsigned MaxLog> 6772 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6773 uint64_t Address, 6774 const MCDisassembler *Decoder) { 6775 DecodeStatus S = MCDisassembler::Success; 6776 6777 if (Val < MinLog || Val > MaxLog) 6778 return MCDisassembler::Fail; 6779 6780 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6781 return S; 6782 } 6783 6784 template <unsigned start> 6785 static DecodeStatus 6786 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6787 const MCDisassembler *Decoder) { 6788 DecodeStatus S = MCDisassembler::Success; 6789 6790 Inst.addOperand(MCOperand::createImm(start + Val)); 6791 6792 return S; 6793 } 6794 6795 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6796 uint64_t Address, 6797 const MCDisassembler *Decoder) { 6798 DecodeStatus S = MCDisassembler::Success; 6799 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6800 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6801 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6802 fieldFromInstruction(Insn, 13, 3)); 6803 unsigned index = fieldFromInstruction(Insn, 4, 1); 6804 6805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6806 return MCDisassembler::Fail; 6807 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6808 return MCDisassembler::Fail; 6809 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6810 return MCDisassembler::Fail; 6811 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6812 return MCDisassembler::Fail; 6813 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6814 return MCDisassembler::Fail; 6815 6816 return S; 6817 } 6818 6819 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6820 uint64_t Address, 6821 const MCDisassembler *Decoder) { 6822 DecodeStatus S = MCDisassembler::Success; 6823 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6824 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6825 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6826 fieldFromInstruction(Insn, 13, 3)); 6827 unsigned index = fieldFromInstruction(Insn, 4, 1); 6828 6829 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6830 return MCDisassembler::Fail; 6831 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6832 return MCDisassembler::Fail; 6833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6834 return MCDisassembler::Fail; 6835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6836 return MCDisassembler::Fail; 6837 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6838 return MCDisassembler::Fail; 6839 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6840 return MCDisassembler::Fail; 6841 6842 return S; 6843 } 6844 6845 static DecodeStatus 6846 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6847 const MCDisassembler *Decoder) { 6848 DecodeStatus S = MCDisassembler::Success; 6849 6850 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6851 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6852 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6853 6854 if (RdaHi == 14) { 6855 // This value of RdaHi (really indicating pc, because RdaHi has to 6856 // be an odd-numbered register, so the low bit will be set by the 6857 // decode function below) indicates that we must decode as SQRSHR 6858 // or UQRSHL, which both have a single Rda register field with all 6859 // four bits. 6860 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6861 6862 switch (Inst.getOpcode()) { 6863 case ARM::MVE_ASRLr: 6864 case ARM::MVE_SQRSHRL: 6865 Inst.setOpcode(ARM::MVE_SQRSHR); 6866 break; 6867 case ARM::MVE_LSLLr: 6868 case ARM::MVE_UQRSHLL: 6869 Inst.setOpcode(ARM::MVE_UQRSHL); 6870 break; 6871 default: 6872 llvm_unreachable("Unexpected starting opcode!"); 6873 } 6874 6875 // Rda as output parameter 6876 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6877 return MCDisassembler::Fail; 6878 6879 // Rda again as input parameter 6880 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6881 return MCDisassembler::Fail; 6882 6883 // Rm, the amount to shift by 6884 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6885 return MCDisassembler::Fail; 6886 6887 if (fieldFromInstruction (Insn, 6, 3) != 4) 6888 return MCDisassembler::SoftFail; 6889 6890 if (Rda == Rm) 6891 return MCDisassembler::SoftFail; 6892 6893 return S; 6894 } 6895 6896 // Otherwise, we decode as whichever opcode our caller has already 6897 // put into Inst. Those all look the same: 6898 6899 // RdaLo,RdaHi as output parameters 6900 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6901 return MCDisassembler::Fail; 6902 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6903 return MCDisassembler::Fail; 6904 6905 // RdaLo,RdaHi again as input parameters 6906 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6907 return MCDisassembler::Fail; 6908 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6909 return MCDisassembler::Fail; 6910 6911 // Rm, the amount to shift by 6912 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6913 return MCDisassembler::Fail; 6914 6915 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6916 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6917 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6918 // Saturate, the bit position for saturation 6919 Inst.addOperand(MCOperand::createImm(Saturate)); 6920 } 6921 6922 return S; 6923 } 6924 6925 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6926 uint64_t Address, 6927 const MCDisassembler *Decoder) { 6928 DecodeStatus S = MCDisassembler::Success; 6929 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6930 fieldFromInstruction(Insn, 13, 3)); 6931 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6932 fieldFromInstruction(Insn, 1, 3)); 6933 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6934 6935 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6936 return MCDisassembler::Fail; 6937 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6938 return MCDisassembler::Fail; 6939 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6940 return MCDisassembler::Fail; 6941 6942 return S; 6943 } 6944 6945 template <bool scalar, OperandDecoder predicate_decoder> 6946 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6947 const MCDisassembler *Decoder) { 6948 DecodeStatus S = MCDisassembler::Success; 6949 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6950 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6951 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6952 return MCDisassembler::Fail; 6953 6954 unsigned fc; 6955 6956 if (scalar) { 6957 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6958 fieldFromInstruction(Insn, 7, 1) | 6959 fieldFromInstruction(Insn, 5, 1) << 1; 6960 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6961 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6962 return MCDisassembler::Fail; 6963 } else { 6964 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6965 fieldFromInstruction(Insn, 7, 1) | 6966 fieldFromInstruction(Insn, 0, 1) << 1; 6967 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6968 fieldFromInstruction(Insn, 1, 3); 6969 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6970 return MCDisassembler::Fail; 6971 } 6972 6973 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6974 return MCDisassembler::Fail; 6975 6976 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6977 Inst.addOperand(MCOperand::createReg(0)); 6978 Inst.addOperand(MCOperand::createImm(0)); 6979 6980 return S; 6981 } 6982 6983 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6984 const MCDisassembler *Decoder) { 6985 DecodeStatus S = MCDisassembler::Success; 6986 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6987 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6989 return MCDisassembler::Fail; 6990 return S; 6991 } 6992 6993 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6994 uint64_t Address, 6995 const MCDisassembler *Decoder) { 6996 DecodeStatus S = MCDisassembler::Success; 6997 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6998 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6999 return S; 7000 } 7001 7002 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 7003 uint64_t Address, 7004 const MCDisassembler *Decoder) { 7005 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 7006 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7007 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 7008 fieldFromInstruction(Insn, 12, 3) << 8 | 7009 fieldFromInstruction(Insn, 0, 8); 7010 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 7011 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 7012 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7013 unsigned S = fieldFromInstruction(Insn, 20, 1); 7014 if (sign1 != sign2) 7015 return MCDisassembler::Fail; 7016 7017 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7018 DecodeStatus DS = MCDisassembler::Success; 7019 if ((!Check(DS, 7020 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7021 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7022 return MCDisassembler::Fail; 7023 if (TypeT3) { 7024 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7025 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7026 } else { 7027 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7028 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7029 return MCDisassembler::Fail; 7030 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7031 return MCDisassembler::Fail; 7032 } 7033 7034 return DS; 7035 } 7036 7037 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn, 7038 uint64_t Address, 7039 const MCDisassembler *Decoder) { 7040 DecodeStatus S = MCDisassembler::Success; 7041 7042 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7043 // Adding Rn, holding memory location to save/load to/from, the only argument 7044 // that is being encoded. 7045 // '$Rn' in the assembly. 7046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 7047 return MCDisassembler::Fail; 7048 // An optional predicate, '$p' in the assembly. 7049 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder); 7050 // An immediate that represents a floating point registers list. '$regs' in 7051 // the assembly. 7052 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect. 7053 7054 return S; 7055 } 7056