1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDecoderOps.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/MathExtras.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 143 uint64_t Address) const override; 144 145 private: 146 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 147 ArrayRef<uint8_t> Bytes, uint64_t Address, 148 raw_ostream &CStream) const; 149 150 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 151 ArrayRef<uint8_t> Bytes, uint64_t Address, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, 182 const MCDisassembler *Decoder); 183 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, 185 const MCDisassembler *Decoder); 186 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, 188 const MCDisassembler *Decoder); 189 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192 static DecodeStatus 193 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 194 uint64_t Address, 195 const MCDisassembler *Decoder); 196 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 197 uint64_t Address, 198 const MCDisassembler *Decoder); 199 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, 201 const MCDisassembler *Decoder); 202 static DecodeStatus 203 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 204 const MCDisassembler *Decoder); 205 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, 207 const MCDisassembler *Decoder); 208 static DecodeStatus 209 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 210 const MCDisassembler *Decoder); 211 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, 213 const MCDisassembler *Decoder); 214 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, 216 const MCDisassembler *Decoder); 217 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 218 uint64_t Address, 219 const MCDisassembler *Decoder); 220 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, 222 const MCDisassembler *Decoder); 223 static DecodeStatus 224 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 225 const MCDisassembler *Decoder); 226 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, 228 const MCDisassembler *Decoder); 229 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, 231 const MCDisassembler *Decoder); 232 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, 234 const MCDisassembler *Decoder); 235 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 236 uint64_t Address, 237 const MCDisassembler *Decoder); 238 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 239 uint64_t Address, 240 const MCDisassembler *Decoder); 241 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 242 uint64_t Address, 243 const MCDisassembler *Decoder); 244 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 245 uint64_t Address, 246 const MCDisassembler *Decoder); 247 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 248 uint64_t Address, 249 const MCDisassembler *Decoder); 250 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 251 uint64_t Address, 252 const MCDisassembler *Decoder); 253 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 254 uint64_t Address, 255 const MCDisassembler *Decoder); 256 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 257 uint64_t Address, 258 const MCDisassembler *Decoder); 259 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 260 uint64_t Address, 261 const MCDisassembler *Decoder); 262 static DecodeStatus 263 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 264 const MCDisassembler *Decoder); 265 266 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 267 uint64_t Address, 268 const MCDisassembler *Decoder); 269 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 270 uint64_t Address, 271 const MCDisassembler *Decoder); 272 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 273 uint64_t Address, 274 const MCDisassembler *Decoder); 275 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 276 uint64_t Address, 277 const MCDisassembler *Decoder); 278 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281 282 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 283 uint64_t Address, 284 const MCDisassembler *Decoder); 285 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 286 uint64_t Address, 287 const MCDisassembler *Decoder); 288 static DecodeStatus 289 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 290 const MCDisassembler *Decoder); 291 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 292 uint64_t Address, 293 const MCDisassembler *Decoder); 294 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 295 uint64_t Address, 296 const MCDisassembler *Decoder); 297 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 298 uint64_t Address, 299 const MCDisassembler *Decoder); 300 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 301 uint64_t Address, 302 const MCDisassembler *Decoder); 303 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 304 uint64_t Address, 305 const MCDisassembler *Decoder); 306 307 static DecodeStatus 308 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 309 uint64_t Adddress, 310 const MCDisassembler *Decoder); 311 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 312 uint64_t Address, 313 const MCDisassembler *Decoder); 314 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 315 uint64_t Address, 316 const MCDisassembler *Decoder); 317 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 318 uint64_t Address, 319 const MCDisassembler *Decoder); 320 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 321 uint64_t Address, 322 const MCDisassembler *Decoder); 323 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 324 uint64_t Address, 325 const MCDisassembler *Decoder); 326 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 327 uint64_t Address, 328 const MCDisassembler *Decoder); 329 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 330 uint64_t Address, 331 const MCDisassembler *Decoder); 332 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 333 uint64_t Address, 334 const MCDisassembler *Decoder); 335 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 336 uint64_t Address, 337 const MCDisassembler *Decoder); 338 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 339 uint64_t Address, 340 const MCDisassembler *Decoder); 341 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 342 uint64_t Address, 343 const MCDisassembler *Decoder); 344 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 345 uint64_t Address, 346 const MCDisassembler *Decoder); 347 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 348 uint64_t Address, 349 const MCDisassembler *Decoder); 350 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 351 uint64_t Address, 352 const MCDisassembler *Decoder); 353 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 354 uint64_t Address, 355 const MCDisassembler *Decoder); 356 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 357 uint64_t Address, 358 const MCDisassembler *Decoder); 359 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 360 uint64_t Address, 361 const MCDisassembler *Decoder); 362 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 363 uint64_t Address, 364 const MCDisassembler *Decoder); 365 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 366 uint64_t Address, 367 const MCDisassembler *Decoder); 368 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 369 uint64_t Address, 370 const MCDisassembler *Decoder); 371 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 372 uint64_t Address, 373 const MCDisassembler *Decoder); 374 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 375 uint64_t Address, 376 const MCDisassembler *Decoder); 377 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 378 uint64_t Address, 379 const MCDisassembler *Decoder); 380 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 381 uint64_t Address, 382 const MCDisassembler *Decoder); 383 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 384 uint64_t Address, 385 const MCDisassembler *Decoder); 386 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 387 uint64_t Address, 388 const MCDisassembler *Decoder); 389 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 390 uint64_t Address, 391 const MCDisassembler *Decoder); 392 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 393 uint64_t Address, 394 const MCDisassembler *Decoder); 395 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 396 uint64_t Address, 397 const MCDisassembler *Decoder); 398 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 399 uint64_t Address, 400 const MCDisassembler *Decoder); 401 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 402 uint64_t Address, 403 const MCDisassembler *Decoder); 404 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 405 uint64_t Address, 406 const MCDisassembler *Decoder); 407 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 408 uint64_t Address, 409 const MCDisassembler *Decoder); 410 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 411 uint64_t Address, 412 const MCDisassembler *Decoder); 413 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 414 uint64_t Address, 415 const MCDisassembler *Decoder); 416 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 417 uint64_t Address, 418 const MCDisassembler *Decoder); 419 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422 template <int shift> 423 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 424 uint64_t Address, 425 const MCDisassembler *Decoder); 426 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 427 uint64_t Address, 428 const MCDisassembler *Decoder); 429 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 430 uint64_t Address, 431 const MCDisassembler *Decoder); 432 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 433 uint64_t Address, 434 const MCDisassembler *Decoder); 435 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 436 const MCDisassembler *Decoder); 437 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 438 uint64_t Address, 439 const MCDisassembler *Decoder); 440 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 441 uint64_t Address, 442 const MCDisassembler *Decoder); 443 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 444 uint64_t Address, 445 const MCDisassembler *Decoder); 446 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 447 uint64_t Address, 448 const MCDisassembler *Decoder); 449 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 450 uint64_t Address, 451 const MCDisassembler *Decoder); 452 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 453 uint64_t Address, 454 const MCDisassembler *Decoder); 455 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 456 uint64_t Address, 457 const MCDisassembler *Decoder); 458 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const MCDisassembler *Decoder); 476 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const MCDisassembler *Decoder); 478 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const MCDisassembler *Decoder); 480 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 481 const MCDisassembler *Decoder); 482 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 483 const MCDisassembler *Decoder); 484 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 485 uint64_t Address, 486 const MCDisassembler *Decoder); 487 static DecodeStatus 488 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 489 const MCDisassembler *Decoder); 490 491 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 492 uint64_t Address, 493 const MCDisassembler *Decoder); 494 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 495 uint64_t Address, 496 const MCDisassembler *Decoder); 497 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const MCDisassembler *Decoder); 500 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 501 uint64_t Address, 502 const MCDisassembler *Decoder); 503 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 504 uint64_t Address, 505 const MCDisassembler *Decoder); 506 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 507 uint64_t Address, 508 const MCDisassembler *Decoder); 509 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 510 uint64_t Address, 511 const MCDisassembler *Decoder); 512 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 513 uint64_t Address, 514 const MCDisassembler *Decoder); 515 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 516 uint64_t Address, 517 const MCDisassembler *Decoder); 518 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 519 uint64_t Address, 520 const MCDisassembler *Decoder); 521 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 522 uint64_t Address, 523 const MCDisassembler *Decoder); 524 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 525 uint64_t Address, 526 const MCDisassembler *Decoder); 527 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 528 const MCDisassembler *Decoder); 529 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 530 uint64_t Address, 531 const MCDisassembler *Decoder); 532 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 533 const MCDisassembler *Decoder); 534 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 535 const MCDisassembler *Decoder); 536 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 537 uint64_t Address, 538 const MCDisassembler *Decoder); 539 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 540 uint64_t Address, 541 const MCDisassembler *Decoder); 542 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 543 uint64_t Address, 544 const MCDisassembler *Decoder); 545 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 546 const MCDisassembler *Decoder); 547 template <int shift> 548 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 549 const MCDisassembler *Decoder); 550 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 551 uint64_t Address, 552 const MCDisassembler *Decoder); 553 template <int shift> 554 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557 template <int shift, int WriteBack> 558 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 559 uint64_t Address, 560 const MCDisassembler *Decoder); 561 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 562 uint64_t Address, 563 const MCDisassembler *Decoder); 564 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 565 uint64_t Address, 566 const MCDisassembler *Decoder); 567 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 568 uint64_t Address, 569 const MCDisassembler *Decoder); 570 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 571 uint64_t Address, 572 const MCDisassembler *Decoder); 573 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 574 uint64_t Address, 575 const MCDisassembler *Decoder); 576 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 577 uint64_t Address, 578 const MCDisassembler *Decoder); 579 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 580 uint64_t Address, 581 const MCDisassembler *Decoder); 582 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 583 uint64_t Address, 584 const MCDisassembler *Decoder); 585 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 586 const MCDisassembler *Decoder); 587 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 588 uint64_t Address, 589 const MCDisassembler *Decoder); 590 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 591 uint64_t Address, 592 const MCDisassembler *Decoder); 593 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 594 const MCDisassembler *Decoder); 595 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 596 uint64_t Address, 597 const MCDisassembler *Decoder); 598 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 599 uint64_t Address, 600 const MCDisassembler *Decoder); 601 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 602 const MCDisassembler *Decoder); 603 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 604 uint64_t Address, 605 const MCDisassembler *Decoder); 606 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 607 uint64_t Address, 608 const MCDisassembler *Decoder); 609 610 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 611 const MCDisassembler *Decoder); 612 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 613 uint64_t Address, 614 const MCDisassembler *Decoder); 615 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 616 uint64_t Address, 617 const MCDisassembler *Decoder); 618 619 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 620 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 621 uint64_t Address, 622 const MCDisassembler *Decoder); 623 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 624 uint64_t Address, 625 const MCDisassembler *Decoder); 626 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 627 uint64_t Address, 628 const MCDisassembler *Decoder); 629 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 630 const MCDisassembler *Decoder); 631 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 632 uint64_t Address, 633 const MCDisassembler *Decoder); 634 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 635 const MCDisassembler *Decoder); 636 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 637 uint64_t Address, 638 const MCDisassembler *Decoder); 639 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 640 uint64_t Address, 641 const MCDisassembler *Decoder); 642 static DecodeStatus 643 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 644 const MCDisassembler *Decoder); 645 static DecodeStatus 646 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 647 const MCDisassembler *Decoder); 648 static DecodeStatus 649 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 650 const MCDisassembler *Decoder); 651 static DecodeStatus 652 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 653 const MCDisassembler *Decoder); 654 template <bool Writeback> 655 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 656 uint64_t Address, 657 const MCDisassembler *Decoder); 658 template <int shift> 659 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 660 uint64_t Address, 661 const MCDisassembler *Decoder); 662 template <int shift> 663 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 664 uint64_t Address, 665 const MCDisassembler *Decoder); 666 template <int shift> 667 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 668 uint64_t Address, 669 const MCDisassembler *Decoder); 670 template <unsigned MinLog, unsigned MaxLog> 671 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 672 uint64_t Address, 673 const MCDisassembler *Decoder); 674 template <unsigned start> 675 static DecodeStatus 676 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 677 const MCDisassembler *Decoder); 678 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 679 uint64_t Address, 680 const MCDisassembler *Decoder); 681 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 682 uint64_t Address, 683 const MCDisassembler *Decoder); 684 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 685 uint64_t Address, 686 const MCDisassembler *Decoder); 687 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 688 uint64_t Address, 689 const MCDisassembler *Decoder); 690 template <bool scalar, OperandDecoder predicate_decoder> 691 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 692 const MCDisassembler *Decoder); 693 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 694 const MCDisassembler *Decoder); 695 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 696 uint64_t Address, 697 const MCDisassembler *Decoder); 698 static DecodeStatus 699 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 700 const MCDisassembler *Decoder); 701 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 702 uint64_t Address, 703 const MCDisassembler *Decoder); 704 705 #include "ARMGenDisassemblerTables.inc" 706 707 static MCDisassembler *createARMDisassembler(const Target &T, 708 const MCSubtargetInfo &STI, 709 MCContext &Ctx) { 710 return new ARMDisassembler(STI, Ctx); 711 } 712 713 // Post-decoding checks 714 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 715 uint64_t Address, raw_ostream &CS, 716 uint32_t Insn, 717 DecodeStatus Result) { 718 switch (MI.getOpcode()) { 719 case ARM::HVC: { 720 // HVC is undefined if condition = 0xf otherwise upredictable 721 // if condition != 0xe 722 uint32_t Cond = (Insn >> 28) & 0xF; 723 if (Cond == 0xF) 724 return MCDisassembler::Fail; 725 if (Cond != 0xE) 726 return MCDisassembler::SoftFail; 727 return Result; 728 } 729 case ARM::t2ADDri: 730 case ARM::t2ADDri12: 731 case ARM::t2ADDrr: 732 case ARM::t2ADDrs: 733 case ARM::t2SUBri: 734 case ARM::t2SUBri12: 735 case ARM::t2SUBrr: 736 case ARM::t2SUBrs: 737 if (MI.getOperand(0).getReg() == ARM::SP && 738 MI.getOperand(1).getReg() != ARM::SP) 739 return MCDisassembler::SoftFail; 740 return Result; 741 default: return Result; 742 } 743 } 744 745 uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 746 uint64_t Address) const { 747 // In Arm state, instructions are always 4 bytes wide, so there's no 748 // point in skipping any smaller number of bytes if an instruction 749 // can't be decoded. 750 if (!STI.getFeatureBits()[ARM::ModeThumb]) 751 return 4; 752 753 // In a Thumb instruction stream, a halfword is a standalone 2-byte 754 // instruction if and only if its value is less than 0xE800. 755 // Otherwise, it's the first halfword of a 4-byte instruction. 756 // 757 // So, if we can see the upcoming halfword, we can judge on that 758 // basis, and maybe skip a whole 4-byte instruction that we don't 759 // know how to decode, without accidentally trying to interpret its 760 // second half as something else. 761 // 762 // If we don't have the instruction data available, we just have to 763 // recommend skipping the minimum sensible distance, which is 2 764 // bytes. 765 if (Bytes.size() < 2) 766 return 2; 767 768 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 769 return Insn16 < 0xE800 ? 2 : 4; 770 } 771 772 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 773 ArrayRef<uint8_t> Bytes, 774 uint64_t Address, 775 raw_ostream &CS) const { 776 if (STI.getFeatureBits()[ARM::ModeThumb]) 777 return getThumbInstruction(MI, Size, Bytes, Address, CS); 778 return getARMInstruction(MI, Size, Bytes, Address, CS); 779 } 780 781 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 782 ArrayRef<uint8_t> Bytes, 783 uint64_t Address, 784 raw_ostream &CS) const { 785 CommentStream = &CS; 786 787 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 788 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 789 "mode!"); 790 791 // We want to read exactly 4 bytes of data. 792 if (Bytes.size() < 4) { 793 Size = 0; 794 return MCDisassembler::Fail; 795 } 796 797 // Encoded as a small-endian 32-bit word in the stream. 798 uint32_t Insn = 799 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 800 801 // Calling the auto-generated decoder function. 802 DecodeStatus Result = 803 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 804 if (Result != MCDisassembler::Fail) { 805 Size = 4; 806 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 807 } 808 809 struct DecodeTable { 810 const uint8_t *P; 811 bool DecodePred; 812 }; 813 814 const DecodeTable Tables[] = { 815 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 816 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 817 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 818 {DecoderTablev8Crypto32, false}, 819 }; 820 821 for (auto Table : Tables) { 822 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 823 if (Result != MCDisassembler::Fail) { 824 Size = 4; 825 // Add a fake predicate operand, because we share these instruction 826 // definitions with Thumb2 where these instructions are predicable. 827 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 828 return MCDisassembler::Fail; 829 return Result; 830 } 831 } 832 833 Result = 834 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 838 } 839 840 Size = 4; 841 return MCDisassembler::Fail; 842 } 843 844 namespace llvm { 845 846 extern const MCInstrDesc ARMInsts[]; 847 848 } // end namespace llvm 849 850 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 851 /// immediate Value in the MCInst. The immediate Value has had any PC 852 /// adjustment made by the caller. If the instruction is a branch instruction 853 /// then isBranch is true, else false. If the getOpInfo() function was set as 854 /// part of the setupForSymbolicDisassembly() call then that function is called 855 /// to get any symbolic information at the Address for this instruction. If 856 /// that returns non-zero then the symbolic information it returns is used to 857 /// create an MCExpr and that is added as an operand to the MCInst. If 858 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 859 /// Value is done and if a symbol is found an MCExpr is created with that, else 860 /// an MCExpr with Value is created. This function returns true if it adds an 861 /// operand to the MCInst and false otherwise. 862 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 863 bool isBranch, uint64_t InstSize, 864 MCInst &MI, 865 const MCDisassembler *Decoder) { 866 // FIXME: Does it make sense for value to be negative? 867 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 868 isBranch, /*Offset=*/0, /*OpSize=*/0, 869 InstSize); 870 } 871 872 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 873 /// referenced by a load instruction with the base register that is the Pc. 874 /// These can often be values in a literal pool near the Address of the 875 /// instruction. The Address of the instruction and its immediate Value are 876 /// used as a possible literal pool entry. The SymbolLookUp call back will 877 /// return the name of a symbol referenced by the literal pool's entry if 878 /// the referenced address is that of a symbol. Or it will return a pointer to 879 /// a literal 'C' string if the referenced address of the literal pool's entry 880 /// is an address into a section with 'C' string literals. 881 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 882 const MCDisassembler *Decoder) { 883 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 884 Dis->tryAddingPcLoadReferenceComment(Value, Address); 885 } 886 887 // Thumb1 instructions don't have explicit S bits. Rather, they 888 // implicitly set CPSR. Since it's not represented in the encoding, the 889 // auto-generated decoder won't inject the CPSR operand. We need to fix 890 // that as a post-pass. 891 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 892 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 893 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 894 MCInst::iterator I = MI.begin(); 895 for (unsigned i = 0; i < NumOps; ++i, ++I) { 896 if (I == MI.end()) break; 897 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 898 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 899 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 900 return; 901 } 902 } 903 904 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 905 } 906 907 static bool isVectorPredicable(unsigned Opcode) { 908 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 909 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 910 for (unsigned i = 0; i < NumOps; ++i) { 911 if (ARM::isVpred(OpInfo[i].OperandType)) 912 return true; 913 } 914 return false; 915 } 916 917 // Most Thumb instructions don't have explicit predicates in the 918 // encoding, but rather get their predicates from IT context. We need 919 // to fix up the predicate operands using this context information as a 920 // post-pass. 921 MCDisassembler::DecodeStatus 922 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 923 MCDisassembler::DecodeStatus S = Success; 924 925 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 926 927 // A few instructions actually have predicates encoded in them. Don't 928 // try to overwrite it if we're seeing one of those. 929 switch (MI.getOpcode()) { 930 case ARM::tBcc: 931 case ARM::t2Bcc: 932 case ARM::tCBZ: 933 case ARM::tCBNZ: 934 case ARM::tCPS: 935 case ARM::t2CPS3p: 936 case ARM::t2CPS2p: 937 case ARM::t2CPS1p: 938 case ARM::t2CSEL: 939 case ARM::t2CSINC: 940 case ARM::t2CSINV: 941 case ARM::t2CSNEG: 942 case ARM::tMOVSr: 943 case ARM::tSETEND: 944 // Some instructions (mostly conditional branches) are not 945 // allowed in IT blocks. 946 if (ITBlock.instrInITBlock()) 947 S = SoftFail; 948 else 949 return Success; 950 break; 951 case ARM::t2HINT: 952 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 953 S = SoftFail; 954 break; 955 case ARM::tB: 956 case ARM::t2B: 957 case ARM::t2TBB: 958 case ARM::t2TBH: 959 // Some instructions (mostly unconditional branches) can 960 // only appears at the end of, or outside of, an IT. 961 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 962 S = SoftFail; 963 break; 964 default: 965 break; 966 } 967 968 // Warn on non-VPT predicable instruction in a VPT block and a VPT 969 // predicable instruction in an IT block 970 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 971 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 972 S = SoftFail; 973 974 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 975 // assume a predicate of AL. 976 unsigned CC = ARMCC::AL; 977 unsigned VCC = ARMVCC::None; 978 if (ITBlock.instrInITBlock()) { 979 CC = ITBlock.getITCC(); 980 ITBlock.advanceITState(); 981 } else if (VPTBlock.instrInVPTBlock()) { 982 VCC = VPTBlock.getVPTPred(); 983 VPTBlock.advanceVPTState(); 984 } 985 986 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 987 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 988 989 MCInst::iterator CCI = MI.begin(); 990 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 991 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 992 } 993 994 if (ARMInsts[MI.getOpcode()].isPredicable()) { 995 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 996 ++CCI; 997 if (CC == ARMCC::AL) 998 MI.insert(CCI, MCOperand::createReg(0)); 999 else 1000 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 1001 } else if (CC != ARMCC::AL) { 1002 Check(S, SoftFail); 1003 } 1004 1005 MCInst::iterator VCCI = MI.begin(); 1006 unsigned VCCPos; 1007 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 1008 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 1009 } 1010 1011 if (isVectorPredicable(MI.getOpcode())) { 1012 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1013 ++VCCI; 1014 if (VCC == ARMVCC::None) 1015 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1016 else 1017 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1018 ++VCCI; 1019 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1020 ++VCCI; 1021 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1022 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 1023 VCCPos + 3, MCOI::TIED_TO); 1024 assert(TiedOp >= 0 && 1025 "Inactive register in vpred_r is not tied to an output!"); 1026 // Copy the operand to ensure it's not invalidated when MI grows. 1027 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1028 } 1029 } else if (VCC != ARMVCC::None) { 1030 Check(S, SoftFail); 1031 } 1032 1033 return S; 1034 } 1035 1036 // Thumb VFP instructions are a special case. Because we share their 1037 // encodings between ARM and Thumb modes, and they are predicable in ARM 1038 // mode, the auto-generated decoder will give them an (incorrect) 1039 // predicate operand. We need to rewrite these operands based on the IT 1040 // context as a post-pass. 1041 void ARMDisassembler::UpdateThumbVFPPredicate( 1042 DecodeStatus &S, MCInst &MI) const { 1043 unsigned CC; 1044 CC = ITBlock.getITCC(); 1045 if (CC == 0xF) 1046 CC = ARMCC::AL; 1047 if (ITBlock.instrInITBlock()) 1048 ITBlock.advanceITState(); 1049 else if (VPTBlock.instrInVPTBlock()) { 1050 CC = VPTBlock.getVPTPred(); 1051 VPTBlock.advanceVPTState(); 1052 } 1053 1054 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 1055 MCInst::iterator I = MI.begin(); 1056 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 1057 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1058 if (OpInfo[i].isPredicate() ) { 1059 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 1060 Check(S, SoftFail); 1061 I->setImm(CC); 1062 ++I; 1063 if (CC == ARMCC::AL) 1064 I->setReg(0); 1065 else 1066 I->setReg(ARM::CPSR); 1067 return; 1068 } 1069 } 1070 } 1071 1072 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1073 ArrayRef<uint8_t> Bytes, 1074 uint64_t Address, 1075 raw_ostream &CS) const { 1076 CommentStream = &CS; 1077 1078 assert(STI.getFeatureBits()[ARM::ModeThumb] && 1079 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1080 1081 // We want to read exactly 2 bytes of data. 1082 if (Bytes.size() < 2) { 1083 Size = 0; 1084 return MCDisassembler::Fail; 1085 } 1086 1087 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 1088 DecodeStatus Result = 1089 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1090 if (Result != MCDisassembler::Fail) { 1091 Size = 2; 1092 Check(Result, AddThumbPredicate(MI)); 1093 return Result; 1094 } 1095 1096 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1097 STI); 1098 if (Result) { 1099 Size = 2; 1100 bool InITBlock = ITBlock.instrInITBlock(); 1101 Check(Result, AddThumbPredicate(MI)); 1102 AddThumb1SBit(MI, InITBlock); 1103 return Result; 1104 } 1105 1106 Result = 1107 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1108 if (Result != MCDisassembler::Fail) { 1109 Size = 2; 1110 1111 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1112 // the Thumb predicate. 1113 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1114 Result = MCDisassembler::SoftFail; 1115 1116 Check(Result, AddThumbPredicate(MI)); 1117 1118 // If we find an IT instruction, we need to parse its condition 1119 // code and mask operands so that we can apply them correctly 1120 // to the subsequent instructions. 1121 if (MI.getOpcode() == ARM::t2IT) { 1122 unsigned Firstcond = MI.getOperand(0).getImm(); 1123 unsigned Mask = MI.getOperand(1).getImm(); 1124 ITBlock.setITState(Firstcond, Mask); 1125 1126 // An IT instruction that would give a 'NV' predicate is unpredictable. 1127 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1128 CS << "unpredictable IT predicate sequence"; 1129 } 1130 1131 return Result; 1132 } 1133 1134 // We want to read exactly 4 bytes of data. 1135 if (Bytes.size() < 4) { 1136 Size = 0; 1137 return MCDisassembler::Fail; 1138 } 1139 1140 uint32_t Insn32 = 1141 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 1142 1143 Result = 1144 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1145 if (Result != MCDisassembler::Fail) { 1146 Size = 4; 1147 1148 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1149 // the VPT predicate. 1150 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1151 Result = MCDisassembler::SoftFail; 1152 1153 Check(Result, AddThumbPredicate(MI)); 1154 1155 if (isVPTOpcode(MI.getOpcode())) { 1156 unsigned Mask = MI.getOperand(0).getImm(); 1157 VPTBlock.setVPTState(Mask); 1158 } 1159 1160 return Result; 1161 } 1162 1163 Result = 1164 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1165 if (Result != MCDisassembler::Fail) { 1166 Size = 4; 1167 bool InITBlock = ITBlock.instrInITBlock(); 1168 Check(Result, AddThumbPredicate(MI)); 1169 AddThumb1SBit(MI, InITBlock); 1170 return Result; 1171 } 1172 1173 Result = 1174 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1175 if (Result != MCDisassembler::Fail) { 1176 Size = 4; 1177 Check(Result, AddThumbPredicate(MI)); 1178 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1179 } 1180 1181 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1182 Result = 1183 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1184 if (Result != MCDisassembler::Fail) { 1185 Size = 4; 1186 UpdateThumbVFPPredicate(Result, MI); 1187 return Result; 1188 } 1189 } 1190 1191 Result = 1192 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1193 if (Result != MCDisassembler::Fail) { 1194 Size = 4; 1195 return Result; 1196 } 1197 1198 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1199 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1200 STI); 1201 if (Result != MCDisassembler::Fail) { 1202 Size = 4; 1203 Check(Result, AddThumbPredicate(MI)); 1204 return Result; 1205 } 1206 } 1207 1208 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1209 uint32_t NEONLdStInsn = Insn32; 1210 NEONLdStInsn &= 0xF0FFFFFF; 1211 NEONLdStInsn |= 0x04000000; 1212 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1213 Address, this, STI); 1214 if (Result != MCDisassembler::Fail) { 1215 Size = 4; 1216 Check(Result, AddThumbPredicate(MI)); 1217 return Result; 1218 } 1219 } 1220 1221 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1222 uint32_t NEONDataInsn = Insn32; 1223 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1224 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1225 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1226 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1227 Address, this, STI); 1228 if (Result != MCDisassembler::Fail) { 1229 Size = 4; 1230 Check(Result, AddThumbPredicate(MI)); 1231 return Result; 1232 } 1233 1234 uint32_t NEONCryptoInsn = Insn32; 1235 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1236 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1237 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1238 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1239 Address, this, STI); 1240 if (Result != MCDisassembler::Fail) { 1241 Size = 4; 1242 return Result; 1243 } 1244 1245 uint32_t NEONv8Insn = Insn32; 1246 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1247 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1248 this, STI); 1249 if (Result != MCDisassembler::Fail) { 1250 Size = 4; 1251 return Result; 1252 } 1253 } 1254 1255 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1256 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1257 ? DecoderTableThumb2CDE32 1258 : DecoderTableThumb2CoProc32; 1259 Result = 1260 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1261 if (Result != MCDisassembler::Fail) { 1262 Size = 4; 1263 Check(Result, AddThumbPredicate(MI)); 1264 return Result; 1265 } 1266 1267 Size = 0; 1268 return MCDisassembler::Fail; 1269 } 1270 1271 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1272 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1273 createARMDisassembler); 1274 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1275 createARMDisassembler); 1276 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1277 createARMDisassembler); 1278 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1279 createARMDisassembler); 1280 } 1281 1282 static const uint16_t GPRDecoderTable[] = { 1283 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1284 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1285 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1286 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1287 }; 1288 1289 static const uint16_t CLRMGPRDecoderTable[] = { 1290 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1291 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1292 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1293 ARM::R12, 0, ARM::LR, ARM::APSR 1294 }; 1295 1296 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, 1298 const MCDisassembler *Decoder) { 1299 if (RegNo > 15) 1300 return MCDisassembler::Fail; 1301 1302 unsigned Register = GPRDecoderTable[RegNo]; 1303 Inst.addOperand(MCOperand::createReg(Register)); 1304 return MCDisassembler::Success; 1305 } 1306 1307 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1308 uint64_t Address, 1309 const MCDisassembler *Decoder) { 1310 if (RegNo > 15) 1311 return MCDisassembler::Fail; 1312 1313 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1314 if (Register == 0) 1315 return MCDisassembler::Fail; 1316 1317 Inst.addOperand(MCOperand::createReg(Register)); 1318 return MCDisassembler::Success; 1319 } 1320 1321 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1322 uint64_t Address, 1323 const MCDisassembler *Decoder) { 1324 DecodeStatus S = MCDisassembler::Success; 1325 1326 if (RegNo == 15) 1327 S = MCDisassembler::SoftFail; 1328 1329 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1330 1331 return S; 1332 } 1333 1334 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1335 uint64_t Address, 1336 const MCDisassembler *Decoder) { 1337 DecodeStatus S = MCDisassembler::Success; 1338 1339 if (RegNo == 13) 1340 S = MCDisassembler::SoftFail; 1341 1342 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1343 1344 return S; 1345 } 1346 1347 static DecodeStatus 1348 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1349 const MCDisassembler *Decoder) { 1350 DecodeStatus S = MCDisassembler::Success; 1351 1352 if (RegNo == 15) 1353 { 1354 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1355 return MCDisassembler::Success; 1356 } 1357 1358 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1359 return S; 1360 } 1361 1362 static DecodeStatus 1363 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1364 const MCDisassembler *Decoder) { 1365 DecodeStatus S = MCDisassembler::Success; 1366 1367 if (RegNo == 15) 1368 { 1369 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1370 return MCDisassembler::Success; 1371 } 1372 1373 if (RegNo == 13) 1374 Check(S, MCDisassembler::SoftFail); 1375 1376 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1377 return S; 1378 } 1379 1380 static DecodeStatus 1381 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1382 const MCDisassembler *Decoder) { 1383 DecodeStatus S = MCDisassembler::Success; 1384 if (RegNo == 13) 1385 return MCDisassembler::Fail; 1386 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1387 return S; 1388 } 1389 1390 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1391 uint64_t Address, 1392 const MCDisassembler *Decoder) { 1393 if (RegNo > 7) 1394 return MCDisassembler::Fail; 1395 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1396 } 1397 1398 static const uint16_t GPRPairDecoderTable[] = { 1399 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1400 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1401 }; 1402 1403 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1404 uint64_t Address, 1405 const MCDisassembler *Decoder) { 1406 DecodeStatus S = MCDisassembler::Success; 1407 1408 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1409 // rather than SoftFail as there is no GPRPair table entry for index 7. 1410 if (RegNo > 13) 1411 return MCDisassembler::Fail; 1412 1413 if (RegNo & 1) 1414 S = MCDisassembler::SoftFail; 1415 1416 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1417 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1418 return S; 1419 } 1420 1421 static DecodeStatus 1422 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1423 const MCDisassembler *Decoder) { 1424 if (RegNo > 13) 1425 return MCDisassembler::Fail; 1426 1427 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1428 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1429 1430 if ((RegNo & 1) || RegNo > 10) 1431 return MCDisassembler::SoftFail; 1432 return MCDisassembler::Success; 1433 } 1434 1435 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1436 uint64_t Address, 1437 const MCDisassembler *Decoder) { 1438 if (RegNo != 13) 1439 return MCDisassembler::Fail; 1440 1441 unsigned Register = GPRDecoderTable[RegNo]; 1442 Inst.addOperand(MCOperand::createReg(Register)); 1443 return MCDisassembler::Success; 1444 } 1445 1446 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1447 uint64_t Address, 1448 const MCDisassembler *Decoder) { 1449 unsigned Register = 0; 1450 switch (RegNo) { 1451 case 0: 1452 Register = ARM::R0; 1453 break; 1454 case 1: 1455 Register = ARM::R1; 1456 break; 1457 case 2: 1458 Register = ARM::R2; 1459 break; 1460 case 3: 1461 Register = ARM::R3; 1462 break; 1463 case 9: 1464 Register = ARM::R9; 1465 break; 1466 case 12: 1467 Register = ARM::R12; 1468 break; 1469 default: 1470 return MCDisassembler::Fail; 1471 } 1472 1473 Inst.addOperand(MCOperand::createReg(Register)); 1474 return MCDisassembler::Success; 1475 } 1476 1477 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1478 uint64_t Address, 1479 const MCDisassembler *Decoder) { 1480 DecodeStatus S = MCDisassembler::Success; 1481 1482 const FeatureBitset &featureBits = 1483 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1484 1485 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1486 S = MCDisassembler::SoftFail; 1487 1488 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1489 return S; 1490 } 1491 1492 static const uint16_t SPRDecoderTable[] = { 1493 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1494 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1495 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1496 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1501 }; 1502 1503 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1504 uint64_t Address, 1505 const MCDisassembler *Decoder) { 1506 if (RegNo > 31) 1507 return MCDisassembler::Fail; 1508 1509 unsigned Register = SPRDecoderTable[RegNo]; 1510 Inst.addOperand(MCOperand::createReg(Register)); 1511 return MCDisassembler::Success; 1512 } 1513 1514 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1515 uint64_t Address, 1516 const MCDisassembler *Decoder) { 1517 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1518 } 1519 1520 static const uint16_t DPRDecoderTable[] = { 1521 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1522 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1523 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1524 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1525 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1526 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1527 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1528 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1529 }; 1530 1531 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1532 uint64_t Address, 1533 const MCDisassembler *Decoder) { 1534 const FeatureBitset &featureBits = 1535 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1536 1537 bool hasD32 = featureBits[ARM::FeatureD32]; 1538 1539 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1540 return MCDisassembler::Fail; 1541 1542 unsigned Register = DPRDecoderTable[RegNo]; 1543 Inst.addOperand(MCOperand::createReg(Register)); 1544 return MCDisassembler::Success; 1545 } 1546 1547 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1548 uint64_t Address, 1549 const MCDisassembler *Decoder) { 1550 if (RegNo > 7) 1551 return MCDisassembler::Fail; 1552 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1553 } 1554 1555 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1556 uint64_t Address, 1557 const MCDisassembler *Decoder) { 1558 if (RegNo > 15) 1559 return MCDisassembler::Fail; 1560 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1561 } 1562 1563 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1564 uint64_t Address, 1565 const MCDisassembler *Decoder) { 1566 if (RegNo > 15) 1567 return MCDisassembler::Fail; 1568 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1569 } 1570 1571 static const uint16_t QPRDecoderTable[] = { 1572 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1574 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1575 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1576 }; 1577 1578 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1579 uint64_t Address, 1580 const MCDisassembler *Decoder) { 1581 if (RegNo > 31 || (RegNo & 1) != 0) 1582 return MCDisassembler::Fail; 1583 RegNo >>= 1; 1584 1585 unsigned Register = QPRDecoderTable[RegNo]; 1586 Inst.addOperand(MCOperand::createReg(Register)); 1587 return MCDisassembler::Success; 1588 } 1589 1590 static const uint16_t DPairDecoderTable[] = { 1591 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1592 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1594 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1595 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1596 ARM::Q15 1597 }; 1598 1599 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1600 uint64_t Address, 1601 const MCDisassembler *Decoder) { 1602 if (RegNo > 30) 1603 return MCDisassembler::Fail; 1604 1605 unsigned Register = DPairDecoderTable[RegNo]; 1606 Inst.addOperand(MCOperand::createReg(Register)); 1607 return MCDisassembler::Success; 1608 } 1609 1610 static const uint16_t DPairSpacedDecoderTable[] = { 1611 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1612 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1613 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1614 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1615 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1616 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1617 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1618 ARM::D28_D30, ARM::D29_D31 1619 }; 1620 1621 static DecodeStatus 1622 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1623 const MCDisassembler *Decoder) { 1624 if (RegNo > 29) 1625 return MCDisassembler::Fail; 1626 1627 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1628 Inst.addOperand(MCOperand::createReg(Register)); 1629 return MCDisassembler::Success; 1630 } 1631 1632 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1633 uint64_t Address, 1634 const MCDisassembler *Decoder) { 1635 DecodeStatus S = MCDisassembler::Success; 1636 if (Val == 0xF) return MCDisassembler::Fail; 1637 // AL predicate is not allowed on Thumb1 branches. 1638 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1639 return MCDisassembler::Fail; 1640 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1641 Check(S, MCDisassembler::SoftFail); 1642 Inst.addOperand(MCOperand::createImm(Val)); 1643 if (Val == ARMCC::AL) { 1644 Inst.addOperand(MCOperand::createReg(0)); 1645 } else 1646 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1647 return S; 1648 } 1649 1650 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1651 uint64_t Address, 1652 const MCDisassembler *Decoder) { 1653 if (Val) 1654 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1655 else 1656 Inst.addOperand(MCOperand::createReg(0)); 1657 return MCDisassembler::Success; 1658 } 1659 1660 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1661 uint64_t Address, 1662 const MCDisassembler *Decoder) { 1663 DecodeStatus S = MCDisassembler::Success; 1664 1665 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1666 unsigned type = fieldFromInstruction(Val, 5, 2); 1667 unsigned imm = fieldFromInstruction(Val, 7, 5); 1668 1669 // Register-immediate 1670 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1671 return MCDisassembler::Fail; 1672 1673 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1674 switch (type) { 1675 case 0: 1676 Shift = ARM_AM::lsl; 1677 break; 1678 case 1: 1679 Shift = ARM_AM::lsr; 1680 break; 1681 case 2: 1682 Shift = ARM_AM::asr; 1683 break; 1684 case 3: 1685 Shift = ARM_AM::ror; 1686 break; 1687 } 1688 1689 if (Shift == ARM_AM::ror && imm == 0) 1690 Shift = ARM_AM::rrx; 1691 1692 unsigned Op = Shift | (imm << 3); 1693 Inst.addOperand(MCOperand::createImm(Op)); 1694 1695 return S; 1696 } 1697 1698 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1699 uint64_t Address, 1700 const MCDisassembler *Decoder) { 1701 DecodeStatus S = MCDisassembler::Success; 1702 1703 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1704 unsigned type = fieldFromInstruction(Val, 5, 2); 1705 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1706 1707 // Register-register 1708 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1709 return MCDisassembler::Fail; 1710 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1711 return MCDisassembler::Fail; 1712 1713 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1714 switch (type) { 1715 case 0: 1716 Shift = ARM_AM::lsl; 1717 break; 1718 case 1: 1719 Shift = ARM_AM::lsr; 1720 break; 1721 case 2: 1722 Shift = ARM_AM::asr; 1723 break; 1724 case 3: 1725 Shift = ARM_AM::ror; 1726 break; 1727 } 1728 1729 Inst.addOperand(MCOperand::createImm(Shift)); 1730 1731 return S; 1732 } 1733 1734 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1735 uint64_t Address, 1736 const MCDisassembler *Decoder) { 1737 DecodeStatus S = MCDisassembler::Success; 1738 1739 bool NeedDisjointWriteback = false; 1740 unsigned WritebackReg = 0; 1741 bool CLRM = false; 1742 switch (Inst.getOpcode()) { 1743 default: 1744 break; 1745 case ARM::LDMIA_UPD: 1746 case ARM::LDMDB_UPD: 1747 case ARM::LDMIB_UPD: 1748 case ARM::LDMDA_UPD: 1749 case ARM::t2LDMIA_UPD: 1750 case ARM::t2LDMDB_UPD: 1751 case ARM::t2STMIA_UPD: 1752 case ARM::t2STMDB_UPD: 1753 NeedDisjointWriteback = true; 1754 WritebackReg = Inst.getOperand(0).getReg(); 1755 break; 1756 case ARM::t2CLRM: 1757 CLRM = true; 1758 break; 1759 } 1760 1761 // Empty register lists are not allowed. 1762 if (Val == 0) return MCDisassembler::Fail; 1763 for (unsigned i = 0; i < 16; ++i) { 1764 if (Val & (1 << i)) { 1765 if (CLRM) { 1766 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1767 return MCDisassembler::Fail; 1768 } 1769 } else { 1770 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1771 return MCDisassembler::Fail; 1772 // Writeback not allowed if Rn is in the target list. 1773 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1774 Check(S, MCDisassembler::SoftFail); 1775 } 1776 } 1777 } 1778 1779 return S; 1780 } 1781 1782 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1783 uint64_t Address, 1784 const MCDisassembler *Decoder) { 1785 DecodeStatus S = MCDisassembler::Success; 1786 1787 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1788 unsigned regs = fieldFromInstruction(Val, 0, 8); 1789 1790 // In case of unpredictable encoding, tweak the operands. 1791 if (regs == 0 || (Vd + regs) > 32) { 1792 regs = Vd + regs > 32 ? 32 - Vd : regs; 1793 regs = std::max( 1u, regs); 1794 S = MCDisassembler::SoftFail; 1795 } 1796 1797 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1798 return MCDisassembler::Fail; 1799 for (unsigned i = 0; i < (regs - 1); ++i) { 1800 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 } 1803 1804 return S; 1805 } 1806 1807 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1808 uint64_t Address, 1809 const MCDisassembler *Decoder) { 1810 DecodeStatus S = MCDisassembler::Success; 1811 1812 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1813 unsigned regs = fieldFromInstruction(Val, 1, 7); 1814 1815 // In case of unpredictable encoding, tweak the operands. 1816 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1817 regs = Vd + regs > 32 ? 32 - Vd : regs; 1818 regs = std::max( 1u, regs); 1819 regs = std::min(16u, regs); 1820 S = MCDisassembler::SoftFail; 1821 } 1822 1823 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1824 return MCDisassembler::Fail; 1825 for (unsigned i = 0; i < (regs - 1); ++i) { 1826 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1827 return MCDisassembler::Fail; 1828 } 1829 1830 return S; 1831 } 1832 1833 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1834 uint64_t Address, 1835 const MCDisassembler *Decoder) { 1836 // This operand encodes a mask of contiguous zeros between a specified MSB 1837 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1838 // the mask of all bits LSB-and-lower, and then xor them to create 1839 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1840 // create the final mask. 1841 unsigned msb = fieldFromInstruction(Val, 5, 5); 1842 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1843 1844 DecodeStatus S = MCDisassembler::Success; 1845 if (lsb > msb) { 1846 Check(S, MCDisassembler::SoftFail); 1847 // The check above will cause the warning for the "potentially undefined 1848 // instruction encoding" but we can't build a bad MCOperand value here 1849 // with a lsb > msb or else printing the MCInst will cause a crash. 1850 lsb = msb; 1851 } 1852 1853 uint32_t msb_mask = 0xFFFFFFFF; 1854 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1855 uint32_t lsb_mask = (1U << lsb) - 1; 1856 1857 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1858 return S; 1859 } 1860 1861 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1862 uint64_t Address, 1863 const MCDisassembler *Decoder) { 1864 DecodeStatus S = MCDisassembler::Success; 1865 1866 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1867 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1868 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1869 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1870 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1871 unsigned U = fieldFromInstruction(Insn, 23, 1); 1872 const FeatureBitset &featureBits = 1873 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1874 1875 switch (Inst.getOpcode()) { 1876 case ARM::LDC_OFFSET: 1877 case ARM::LDC_PRE: 1878 case ARM::LDC_POST: 1879 case ARM::LDC_OPTION: 1880 case ARM::LDCL_OFFSET: 1881 case ARM::LDCL_PRE: 1882 case ARM::LDCL_POST: 1883 case ARM::LDCL_OPTION: 1884 case ARM::STC_OFFSET: 1885 case ARM::STC_PRE: 1886 case ARM::STC_POST: 1887 case ARM::STC_OPTION: 1888 case ARM::STCL_OFFSET: 1889 case ARM::STCL_PRE: 1890 case ARM::STCL_POST: 1891 case ARM::STCL_OPTION: 1892 case ARM::t2LDC_OFFSET: 1893 case ARM::t2LDC_PRE: 1894 case ARM::t2LDC_POST: 1895 case ARM::t2LDC_OPTION: 1896 case ARM::t2LDCL_OFFSET: 1897 case ARM::t2LDCL_PRE: 1898 case ARM::t2LDCL_POST: 1899 case ARM::t2LDCL_OPTION: 1900 case ARM::t2STC_OFFSET: 1901 case ARM::t2STC_PRE: 1902 case ARM::t2STC_POST: 1903 case ARM::t2STC_OPTION: 1904 case ARM::t2STCL_OFFSET: 1905 case ARM::t2STCL_PRE: 1906 case ARM::t2STCL_POST: 1907 case ARM::t2STCL_OPTION: 1908 case ARM::t2LDC2_OFFSET: 1909 case ARM::t2LDC2L_OFFSET: 1910 case ARM::t2LDC2_PRE: 1911 case ARM::t2LDC2L_PRE: 1912 case ARM::t2STC2_OFFSET: 1913 case ARM::t2STC2L_OFFSET: 1914 case ARM::t2STC2_PRE: 1915 case ARM::t2STC2L_PRE: 1916 case ARM::LDC2_OFFSET: 1917 case ARM::LDC2L_OFFSET: 1918 case ARM::LDC2_PRE: 1919 case ARM::LDC2L_PRE: 1920 case ARM::STC2_OFFSET: 1921 case ARM::STC2L_OFFSET: 1922 case ARM::STC2_PRE: 1923 case ARM::STC2L_PRE: 1924 case ARM::t2LDC2_OPTION: 1925 case ARM::t2STC2_OPTION: 1926 case ARM::t2LDC2_POST: 1927 case ARM::t2LDC2L_POST: 1928 case ARM::t2STC2_POST: 1929 case ARM::t2STC2L_POST: 1930 case ARM::LDC2_POST: 1931 case ARM::LDC2L_POST: 1932 case ARM::STC2_POST: 1933 case ARM::STC2L_POST: 1934 if (coproc == 0xA || coproc == 0xB || 1935 (featureBits[ARM::HasV8_1MMainlineOps] && 1936 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1937 coproc == 0xE || coproc == 0xF))) 1938 return MCDisassembler::Fail; 1939 break; 1940 default: 1941 break; 1942 } 1943 1944 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1945 return MCDisassembler::Fail; 1946 1947 Inst.addOperand(MCOperand::createImm(coproc)); 1948 Inst.addOperand(MCOperand::createImm(CRd)); 1949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1950 return MCDisassembler::Fail; 1951 1952 switch (Inst.getOpcode()) { 1953 case ARM::t2LDC2_OFFSET: 1954 case ARM::t2LDC2L_OFFSET: 1955 case ARM::t2LDC2_PRE: 1956 case ARM::t2LDC2L_PRE: 1957 case ARM::t2STC2_OFFSET: 1958 case ARM::t2STC2L_OFFSET: 1959 case ARM::t2STC2_PRE: 1960 case ARM::t2STC2L_PRE: 1961 case ARM::LDC2_OFFSET: 1962 case ARM::LDC2L_OFFSET: 1963 case ARM::LDC2_PRE: 1964 case ARM::LDC2L_PRE: 1965 case ARM::STC2_OFFSET: 1966 case ARM::STC2L_OFFSET: 1967 case ARM::STC2_PRE: 1968 case ARM::STC2L_PRE: 1969 case ARM::t2LDC_OFFSET: 1970 case ARM::t2LDCL_OFFSET: 1971 case ARM::t2LDC_PRE: 1972 case ARM::t2LDCL_PRE: 1973 case ARM::t2STC_OFFSET: 1974 case ARM::t2STCL_OFFSET: 1975 case ARM::t2STC_PRE: 1976 case ARM::t2STCL_PRE: 1977 case ARM::LDC_OFFSET: 1978 case ARM::LDCL_OFFSET: 1979 case ARM::LDC_PRE: 1980 case ARM::LDCL_PRE: 1981 case ARM::STC_OFFSET: 1982 case ARM::STCL_OFFSET: 1983 case ARM::STC_PRE: 1984 case ARM::STCL_PRE: 1985 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1986 Inst.addOperand(MCOperand::createImm(imm)); 1987 break; 1988 case ARM::t2LDC2_POST: 1989 case ARM::t2LDC2L_POST: 1990 case ARM::t2STC2_POST: 1991 case ARM::t2STC2L_POST: 1992 case ARM::LDC2_POST: 1993 case ARM::LDC2L_POST: 1994 case ARM::STC2_POST: 1995 case ARM::STC2L_POST: 1996 case ARM::t2LDC_POST: 1997 case ARM::t2LDCL_POST: 1998 case ARM::t2STC_POST: 1999 case ARM::t2STCL_POST: 2000 case ARM::LDC_POST: 2001 case ARM::LDCL_POST: 2002 case ARM::STC_POST: 2003 case ARM::STCL_POST: 2004 imm |= U << 8; 2005 LLVM_FALLTHROUGH; 2006 default: 2007 // The 'option' variant doesn't encode 'U' in the immediate since 2008 // the immediate is unsigned [0,255]. 2009 Inst.addOperand(MCOperand::createImm(imm)); 2010 break; 2011 } 2012 2013 switch (Inst.getOpcode()) { 2014 case ARM::LDC_OFFSET: 2015 case ARM::LDC_PRE: 2016 case ARM::LDC_POST: 2017 case ARM::LDC_OPTION: 2018 case ARM::LDCL_OFFSET: 2019 case ARM::LDCL_PRE: 2020 case ARM::LDCL_POST: 2021 case ARM::LDCL_OPTION: 2022 case ARM::STC_OFFSET: 2023 case ARM::STC_PRE: 2024 case ARM::STC_POST: 2025 case ARM::STC_OPTION: 2026 case ARM::STCL_OFFSET: 2027 case ARM::STCL_PRE: 2028 case ARM::STCL_POST: 2029 case ARM::STCL_OPTION: 2030 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2031 return MCDisassembler::Fail; 2032 break; 2033 default: 2034 break; 2035 } 2036 2037 return S; 2038 } 2039 2040 static DecodeStatus 2041 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2042 const MCDisassembler *Decoder) { 2043 DecodeStatus S = MCDisassembler::Success; 2044 2045 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2046 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2047 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2048 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2049 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2050 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2051 unsigned P = fieldFromInstruction(Insn, 24, 1); 2052 unsigned W = fieldFromInstruction(Insn, 21, 1); 2053 2054 // On stores, the writeback operand precedes Rt. 2055 switch (Inst.getOpcode()) { 2056 case ARM::STR_POST_IMM: 2057 case ARM::STR_POST_REG: 2058 case ARM::STRB_POST_IMM: 2059 case ARM::STRB_POST_REG: 2060 case ARM::STRT_POST_REG: 2061 case ARM::STRT_POST_IMM: 2062 case ARM::STRBT_POST_REG: 2063 case ARM::STRBT_POST_IMM: 2064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2065 return MCDisassembler::Fail; 2066 break; 2067 default: 2068 break; 2069 } 2070 2071 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2072 return MCDisassembler::Fail; 2073 2074 // On loads, the writeback operand comes after Rt. 2075 switch (Inst.getOpcode()) { 2076 case ARM::LDR_POST_IMM: 2077 case ARM::LDR_POST_REG: 2078 case ARM::LDRB_POST_IMM: 2079 case ARM::LDRB_POST_REG: 2080 case ARM::LDRBT_POST_REG: 2081 case ARM::LDRBT_POST_IMM: 2082 case ARM::LDRT_POST_REG: 2083 case ARM::LDRT_POST_IMM: 2084 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2085 return MCDisassembler::Fail; 2086 break; 2087 default: 2088 break; 2089 } 2090 2091 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2092 return MCDisassembler::Fail; 2093 2094 ARM_AM::AddrOpc Op = ARM_AM::add; 2095 if (!fieldFromInstruction(Insn, 23, 1)) 2096 Op = ARM_AM::sub; 2097 2098 bool writeback = (P == 0) || (W == 1); 2099 unsigned idx_mode = 0; 2100 if (P && writeback) 2101 idx_mode = ARMII::IndexModePre; 2102 else if (!P && writeback) 2103 idx_mode = ARMII::IndexModePost; 2104 2105 if (writeback && (Rn == 15 || Rn == Rt)) 2106 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2107 2108 if (reg) { 2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2112 switch( fieldFromInstruction(Insn, 5, 2)) { 2113 case 0: 2114 Opc = ARM_AM::lsl; 2115 break; 2116 case 1: 2117 Opc = ARM_AM::lsr; 2118 break; 2119 case 2: 2120 Opc = ARM_AM::asr; 2121 break; 2122 case 3: 2123 Opc = ARM_AM::ror; 2124 break; 2125 default: 2126 return MCDisassembler::Fail; 2127 } 2128 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2129 if (Opc == ARM_AM::ror && amt == 0) 2130 Opc = ARM_AM::rrx; 2131 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2132 2133 Inst.addOperand(MCOperand::createImm(imm)); 2134 } else { 2135 Inst.addOperand(MCOperand::createReg(0)); 2136 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2137 Inst.addOperand(MCOperand::createImm(tmp)); 2138 } 2139 2140 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2141 return MCDisassembler::Fail; 2142 2143 return S; 2144 } 2145 2146 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2147 uint64_t Address, 2148 const MCDisassembler *Decoder) { 2149 DecodeStatus S = MCDisassembler::Success; 2150 2151 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2152 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2153 unsigned type = fieldFromInstruction(Val, 5, 2); 2154 unsigned imm = fieldFromInstruction(Val, 7, 5); 2155 unsigned U = fieldFromInstruction(Val, 12, 1); 2156 2157 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2158 switch (type) { 2159 case 0: 2160 ShOp = ARM_AM::lsl; 2161 break; 2162 case 1: 2163 ShOp = ARM_AM::lsr; 2164 break; 2165 case 2: 2166 ShOp = ARM_AM::asr; 2167 break; 2168 case 3: 2169 ShOp = ARM_AM::ror; 2170 break; 2171 } 2172 2173 if (ShOp == ARM_AM::ror && imm == 0) 2174 ShOp = ARM_AM::rrx; 2175 2176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2177 return MCDisassembler::Fail; 2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 unsigned shift; 2181 if (U) 2182 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2183 else 2184 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2185 Inst.addOperand(MCOperand::createImm(shift)); 2186 2187 return S; 2188 } 2189 2190 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2191 uint64_t Address, 2192 const MCDisassembler *Decoder) { 2193 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2194 return MCDisassembler::Fail; 2195 2196 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2197 // the only available operand), but LLVM expects the instruction to have one 2198 // operand, so we need to add the csync when decoding. 2199 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2200 return MCDisassembler::Success; 2201 } 2202 2203 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2204 uint64_t Address, 2205 const MCDisassembler *Decoder) { 2206 DecodeStatus S = MCDisassembler::Success; 2207 2208 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2210 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2211 unsigned type = fieldFromInstruction(Insn, 22, 1); 2212 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2213 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2214 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2215 unsigned W = fieldFromInstruction(Insn, 21, 1); 2216 unsigned P = fieldFromInstruction(Insn, 24, 1); 2217 unsigned Rt2 = Rt + 1; 2218 2219 bool writeback = (W == 1) | (P == 0); 2220 2221 // For {LD,ST}RD, Rt must be even, else undefined. 2222 switch (Inst.getOpcode()) { 2223 case ARM::STRD: 2224 case ARM::STRD_PRE: 2225 case ARM::STRD_POST: 2226 case ARM::LDRD: 2227 case ARM::LDRD_PRE: 2228 case ARM::LDRD_POST: 2229 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2230 break; 2231 default: 2232 break; 2233 } 2234 switch (Inst.getOpcode()) { 2235 case ARM::STRD: 2236 case ARM::STRD_PRE: 2237 case ARM::STRD_POST: 2238 if (P == 0 && W == 1) 2239 S = MCDisassembler::SoftFail; 2240 2241 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2242 S = MCDisassembler::SoftFail; 2243 if (type && Rm == 15) 2244 S = MCDisassembler::SoftFail; 2245 if (Rt2 == 15) 2246 S = MCDisassembler::SoftFail; 2247 if (!type && fieldFromInstruction(Insn, 8, 4)) 2248 S = MCDisassembler::SoftFail; 2249 break; 2250 case ARM::STRH: 2251 case ARM::STRH_PRE: 2252 case ARM::STRH_POST: 2253 if (Rt == 15) 2254 S = MCDisassembler::SoftFail; 2255 if (writeback && (Rn == 15 || Rn == Rt)) 2256 S = MCDisassembler::SoftFail; 2257 if (!type && Rm == 15) 2258 S = MCDisassembler::SoftFail; 2259 break; 2260 case ARM::LDRD: 2261 case ARM::LDRD_PRE: 2262 case ARM::LDRD_POST: 2263 if (type && Rn == 15) { 2264 if (Rt2 == 15) 2265 S = MCDisassembler::SoftFail; 2266 break; 2267 } 2268 if (P == 0 && W == 1) 2269 S = MCDisassembler::SoftFail; 2270 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2271 S = MCDisassembler::SoftFail; 2272 if (!type && writeback && Rn == 15) 2273 S = MCDisassembler::SoftFail; 2274 if (writeback && (Rn == Rt || Rn == Rt2)) 2275 S = MCDisassembler::SoftFail; 2276 break; 2277 case ARM::LDRH: 2278 case ARM::LDRH_PRE: 2279 case ARM::LDRH_POST: 2280 if (type && Rn == 15) { 2281 if (Rt == 15) 2282 S = MCDisassembler::SoftFail; 2283 break; 2284 } 2285 if (Rt == 15) 2286 S = MCDisassembler::SoftFail; 2287 if (!type && Rm == 15) 2288 S = MCDisassembler::SoftFail; 2289 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2290 S = MCDisassembler::SoftFail; 2291 break; 2292 case ARM::LDRSH: 2293 case ARM::LDRSH_PRE: 2294 case ARM::LDRSH_POST: 2295 case ARM::LDRSB: 2296 case ARM::LDRSB_PRE: 2297 case ARM::LDRSB_POST: 2298 if (type && Rn == 15) { 2299 if (Rt == 15) 2300 S = MCDisassembler::SoftFail; 2301 break; 2302 } 2303 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2304 S = MCDisassembler::SoftFail; 2305 if (!type && (Rt == 15 || Rm == 15)) 2306 S = MCDisassembler::SoftFail; 2307 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2308 S = MCDisassembler::SoftFail; 2309 break; 2310 default: 2311 break; 2312 } 2313 2314 if (writeback) { // Writeback 2315 if (P) 2316 U |= ARMII::IndexModePre << 9; 2317 else 2318 U |= ARMII::IndexModePost << 9; 2319 2320 // On stores, the writeback operand precedes Rt. 2321 switch (Inst.getOpcode()) { 2322 case ARM::STRD: 2323 case ARM::STRD_PRE: 2324 case ARM::STRD_POST: 2325 case ARM::STRH: 2326 case ARM::STRH_PRE: 2327 case ARM::STRH_POST: 2328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 break; 2331 default: 2332 break; 2333 } 2334 } 2335 2336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2337 return MCDisassembler::Fail; 2338 switch (Inst.getOpcode()) { 2339 case ARM::STRD: 2340 case ARM::STRD_PRE: 2341 case ARM::STRD_POST: 2342 case ARM::LDRD: 2343 case ARM::LDRD_PRE: 2344 case ARM::LDRD_POST: 2345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2346 return MCDisassembler::Fail; 2347 break; 2348 default: 2349 break; 2350 } 2351 2352 if (writeback) { 2353 // On loads, the writeback operand comes after Rt. 2354 switch (Inst.getOpcode()) { 2355 case ARM::LDRD: 2356 case ARM::LDRD_PRE: 2357 case ARM::LDRD_POST: 2358 case ARM::LDRH: 2359 case ARM::LDRH_PRE: 2360 case ARM::LDRH_POST: 2361 case ARM::LDRSH: 2362 case ARM::LDRSH_PRE: 2363 case ARM::LDRSH_POST: 2364 case ARM::LDRSB: 2365 case ARM::LDRSB_PRE: 2366 case ARM::LDRSB_POST: 2367 case ARM::LDRHTr: 2368 case ARM::LDRSBTr: 2369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2370 return MCDisassembler::Fail; 2371 break; 2372 default: 2373 break; 2374 } 2375 } 2376 2377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2378 return MCDisassembler::Fail; 2379 2380 if (type) { 2381 Inst.addOperand(MCOperand::createReg(0)); 2382 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2383 } else { 2384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2385 return MCDisassembler::Fail; 2386 Inst.addOperand(MCOperand::createImm(U)); 2387 } 2388 2389 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2390 return MCDisassembler::Fail; 2391 2392 return S; 2393 } 2394 2395 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2396 uint64_t Address, 2397 const MCDisassembler *Decoder) { 2398 DecodeStatus S = MCDisassembler::Success; 2399 2400 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2401 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2402 2403 switch (mode) { 2404 case 0: 2405 mode = ARM_AM::da; 2406 break; 2407 case 1: 2408 mode = ARM_AM::ia; 2409 break; 2410 case 2: 2411 mode = ARM_AM::db; 2412 break; 2413 case 3: 2414 mode = ARM_AM::ib; 2415 break; 2416 } 2417 2418 Inst.addOperand(MCOperand::createImm(mode)); 2419 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2420 return MCDisassembler::Fail; 2421 2422 return S; 2423 } 2424 2425 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2426 uint64_t Address, 2427 const MCDisassembler *Decoder) { 2428 DecodeStatus S = MCDisassembler::Success; 2429 2430 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2431 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2432 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2433 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2434 2435 if (pred == 0xF) 2436 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2437 2438 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2439 return MCDisassembler::Fail; 2440 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2443 return MCDisassembler::Fail; 2444 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2445 return MCDisassembler::Fail; 2446 return S; 2447 } 2448 2449 static DecodeStatus 2450 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2451 uint64_t Address, 2452 const MCDisassembler *Decoder) { 2453 DecodeStatus S = MCDisassembler::Success; 2454 2455 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2456 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2457 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2458 2459 if (pred == 0xF) { 2460 // Ambiguous with RFE and SRS 2461 switch (Inst.getOpcode()) { 2462 case ARM::LDMDA: 2463 Inst.setOpcode(ARM::RFEDA); 2464 break; 2465 case ARM::LDMDA_UPD: 2466 Inst.setOpcode(ARM::RFEDA_UPD); 2467 break; 2468 case ARM::LDMDB: 2469 Inst.setOpcode(ARM::RFEDB); 2470 break; 2471 case ARM::LDMDB_UPD: 2472 Inst.setOpcode(ARM::RFEDB_UPD); 2473 break; 2474 case ARM::LDMIA: 2475 Inst.setOpcode(ARM::RFEIA); 2476 break; 2477 case ARM::LDMIA_UPD: 2478 Inst.setOpcode(ARM::RFEIA_UPD); 2479 break; 2480 case ARM::LDMIB: 2481 Inst.setOpcode(ARM::RFEIB); 2482 break; 2483 case ARM::LDMIB_UPD: 2484 Inst.setOpcode(ARM::RFEIB_UPD); 2485 break; 2486 case ARM::STMDA: 2487 Inst.setOpcode(ARM::SRSDA); 2488 break; 2489 case ARM::STMDA_UPD: 2490 Inst.setOpcode(ARM::SRSDA_UPD); 2491 break; 2492 case ARM::STMDB: 2493 Inst.setOpcode(ARM::SRSDB); 2494 break; 2495 case ARM::STMDB_UPD: 2496 Inst.setOpcode(ARM::SRSDB_UPD); 2497 break; 2498 case ARM::STMIA: 2499 Inst.setOpcode(ARM::SRSIA); 2500 break; 2501 case ARM::STMIA_UPD: 2502 Inst.setOpcode(ARM::SRSIA_UPD); 2503 break; 2504 case ARM::STMIB: 2505 Inst.setOpcode(ARM::SRSIB); 2506 break; 2507 case ARM::STMIB_UPD: 2508 Inst.setOpcode(ARM::SRSIB_UPD); 2509 break; 2510 default: 2511 return MCDisassembler::Fail; 2512 } 2513 2514 // For stores (which become SRS's, the only operand is the mode. 2515 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2516 // Check SRS encoding constraints 2517 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2518 fieldFromInstruction(Insn, 20, 1) == 0)) 2519 return MCDisassembler::Fail; 2520 2521 Inst.addOperand( 2522 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2523 return S; 2524 } 2525 2526 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2527 } 2528 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2532 return MCDisassembler::Fail; // Tied 2533 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2536 return MCDisassembler::Fail; 2537 2538 return S; 2539 } 2540 2541 // Check for UNPREDICTABLE predicated ESB instruction 2542 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2543 uint64_t Address, 2544 const MCDisassembler *Decoder) { 2545 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2546 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2548 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2549 2550 DecodeStatus S = MCDisassembler::Success; 2551 2552 Inst.addOperand(MCOperand::createImm(imm8)); 2553 2554 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2555 return MCDisassembler::Fail; 2556 2557 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2558 // so all predicates should be allowed. 2559 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2560 S = MCDisassembler::SoftFail; 2561 2562 return S; 2563 } 2564 2565 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2566 uint64_t Address, 2567 const MCDisassembler *Decoder) { 2568 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2569 unsigned M = fieldFromInstruction(Insn, 17, 1); 2570 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2571 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2572 2573 DecodeStatus S = MCDisassembler::Success; 2574 2575 // This decoder is called from multiple location that do not check 2576 // the full encoding is valid before they do. 2577 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2578 fieldFromInstruction(Insn, 16, 1) != 0 || 2579 fieldFromInstruction(Insn, 20, 8) != 0x10) 2580 return MCDisassembler::Fail; 2581 2582 // imod == '01' --> UNPREDICTABLE 2583 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2584 // return failure here. The '01' imod value is unprintable, so there's 2585 // nothing useful we could do even if we returned UNPREDICTABLE. 2586 2587 if (imod == 1) return MCDisassembler::Fail; 2588 2589 if (imod && M) { 2590 Inst.setOpcode(ARM::CPS3p); 2591 Inst.addOperand(MCOperand::createImm(imod)); 2592 Inst.addOperand(MCOperand::createImm(iflags)); 2593 Inst.addOperand(MCOperand::createImm(mode)); 2594 } else if (imod && !M) { 2595 Inst.setOpcode(ARM::CPS2p); 2596 Inst.addOperand(MCOperand::createImm(imod)); 2597 Inst.addOperand(MCOperand::createImm(iflags)); 2598 if (mode) S = MCDisassembler::SoftFail; 2599 } else if (!imod && M) { 2600 Inst.setOpcode(ARM::CPS1p); 2601 Inst.addOperand(MCOperand::createImm(mode)); 2602 if (iflags) S = MCDisassembler::SoftFail; 2603 } else { 2604 // imod == '00' && M == '0' --> UNPREDICTABLE 2605 Inst.setOpcode(ARM::CPS1p); 2606 Inst.addOperand(MCOperand::createImm(mode)); 2607 S = MCDisassembler::SoftFail; 2608 } 2609 2610 return S; 2611 } 2612 2613 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2614 uint64_t Address, 2615 const MCDisassembler *Decoder) { 2616 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2617 unsigned M = fieldFromInstruction(Insn, 8, 1); 2618 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2619 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2620 2621 DecodeStatus S = MCDisassembler::Success; 2622 2623 // imod == '01' --> UNPREDICTABLE 2624 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2625 // return failure here. The '01' imod value is unprintable, so there's 2626 // nothing useful we could do even if we returned UNPREDICTABLE. 2627 2628 if (imod == 1) return MCDisassembler::Fail; 2629 2630 if (imod && M) { 2631 Inst.setOpcode(ARM::t2CPS3p); 2632 Inst.addOperand(MCOperand::createImm(imod)); 2633 Inst.addOperand(MCOperand::createImm(iflags)); 2634 Inst.addOperand(MCOperand::createImm(mode)); 2635 } else if (imod && !M) { 2636 Inst.setOpcode(ARM::t2CPS2p); 2637 Inst.addOperand(MCOperand::createImm(imod)); 2638 Inst.addOperand(MCOperand::createImm(iflags)); 2639 if (mode) S = MCDisassembler::SoftFail; 2640 } else if (!imod && M) { 2641 Inst.setOpcode(ARM::t2CPS1p); 2642 Inst.addOperand(MCOperand::createImm(mode)); 2643 if (iflags) S = MCDisassembler::SoftFail; 2644 } else { 2645 // imod == '00' && M == '0' --> this is a HINT instruction 2646 int imm = fieldFromInstruction(Insn, 0, 8); 2647 // HINT are defined only for immediate in [0..4] 2648 if(imm > 4) return MCDisassembler::Fail; 2649 Inst.setOpcode(ARM::t2HINT); 2650 Inst.addOperand(MCOperand::createImm(imm)); 2651 } 2652 2653 return S; 2654 } 2655 2656 static DecodeStatus 2657 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2658 const MCDisassembler *Decoder) { 2659 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2660 2661 unsigned Opcode = ARM::t2HINT; 2662 2663 if (imm == 0x0D) { 2664 Opcode = ARM::t2PACBTI; 2665 } else if (imm == 0x1D) { 2666 Opcode = ARM::t2PAC; 2667 } else if (imm == 0x2D) { 2668 Opcode = ARM::t2AUT; 2669 } else if (imm == 0x0F) { 2670 Opcode = ARM::t2BTI; 2671 } 2672 2673 Inst.setOpcode(Opcode); 2674 if (Opcode == ARM::t2HINT) { 2675 Inst.addOperand(MCOperand::createImm(imm)); 2676 } 2677 2678 return MCDisassembler::Success; 2679 } 2680 2681 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2682 uint64_t Address, 2683 const MCDisassembler *Decoder) { 2684 DecodeStatus S = MCDisassembler::Success; 2685 2686 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2687 unsigned imm = 0; 2688 2689 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2690 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2691 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2692 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2693 2694 if (Inst.getOpcode() == ARM::t2MOVTi16) 2695 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2696 return MCDisassembler::Fail; 2697 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2698 return MCDisassembler::Fail; 2699 2700 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2701 Inst.addOperand(MCOperand::createImm(imm)); 2702 2703 return S; 2704 } 2705 2706 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2707 uint64_t Address, 2708 const MCDisassembler *Decoder) { 2709 DecodeStatus S = MCDisassembler::Success; 2710 2711 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2712 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2713 unsigned imm = 0; 2714 2715 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2716 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2717 2718 if (Inst.getOpcode() == ARM::MOVTi16) 2719 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2720 return MCDisassembler::Fail; 2721 2722 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2723 return MCDisassembler::Fail; 2724 2725 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2726 Inst.addOperand(MCOperand::createImm(imm)); 2727 2728 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2729 return MCDisassembler::Fail; 2730 2731 return S; 2732 } 2733 2734 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2735 uint64_t Address, 2736 const MCDisassembler *Decoder) { 2737 DecodeStatus S = MCDisassembler::Success; 2738 2739 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2740 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2741 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2742 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2743 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2744 2745 if (pred == 0xF) 2746 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2747 2748 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2751 return MCDisassembler::Fail; 2752 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2753 return MCDisassembler::Fail; 2754 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2755 return MCDisassembler::Fail; 2756 2757 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2758 return MCDisassembler::Fail; 2759 2760 return S; 2761 } 2762 2763 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2764 uint64_t Address, 2765 const MCDisassembler *Decoder) { 2766 DecodeStatus S = MCDisassembler::Success; 2767 2768 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2769 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2770 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2771 2772 if (Pred == 0xF) 2773 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2774 2775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2776 return MCDisassembler::Fail; 2777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2780 return MCDisassembler::Fail; 2781 2782 return S; 2783 } 2784 2785 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2786 uint64_t Address, 2787 const MCDisassembler *Decoder) { 2788 DecodeStatus S = MCDisassembler::Success; 2789 2790 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2791 2792 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2793 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2794 2795 if (!FeatureBits[ARM::HasV8_1aOps] || 2796 !FeatureBits[ARM::HasV8Ops]) 2797 return MCDisassembler::Fail; 2798 2799 // Decoder can be called from DecodeTST, which does not check the full 2800 // encoding is valid. 2801 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2802 fieldFromInstruction(Insn, 4,4) != 0) 2803 return MCDisassembler::Fail; 2804 if (fieldFromInstruction(Insn, 10,10) != 0 || 2805 fieldFromInstruction(Insn, 0,4) != 0) 2806 S = MCDisassembler::SoftFail; 2807 2808 Inst.setOpcode(ARM::SETPAN); 2809 Inst.addOperand(MCOperand::createImm(Imm)); 2810 2811 return S; 2812 } 2813 2814 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2815 uint64_t Address, 2816 const MCDisassembler *Decoder) { 2817 DecodeStatus S = MCDisassembler::Success; 2818 2819 unsigned add = fieldFromInstruction(Val, 12, 1); 2820 unsigned imm = fieldFromInstruction(Val, 0, 12); 2821 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2822 2823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 2826 if (!add) imm *= -1; 2827 if (imm == 0 && !add) imm = INT32_MIN; 2828 Inst.addOperand(MCOperand::createImm(imm)); 2829 if (Rn == 15) 2830 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2831 2832 return S; 2833 } 2834 2835 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2836 uint64_t Address, 2837 const MCDisassembler *Decoder) { 2838 DecodeStatus S = MCDisassembler::Success; 2839 2840 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2841 // U == 1 to add imm, 0 to subtract it. 2842 unsigned U = fieldFromInstruction(Val, 8, 1); 2843 unsigned imm = fieldFromInstruction(Val, 0, 8); 2844 2845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2846 return MCDisassembler::Fail; 2847 2848 if (U) 2849 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2850 else 2851 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2852 2853 return S; 2854 } 2855 2856 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2857 uint64_t Address, 2858 const MCDisassembler *Decoder) { 2859 DecodeStatus S = MCDisassembler::Success; 2860 2861 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2862 // U == 1 to add imm, 0 to subtract it. 2863 unsigned U = fieldFromInstruction(Val, 8, 1); 2864 unsigned imm = fieldFromInstruction(Val, 0, 8); 2865 2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2867 return MCDisassembler::Fail; 2868 2869 if (U) 2870 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2871 else 2872 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2873 2874 return S; 2875 } 2876 2877 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2878 uint64_t Address, 2879 const MCDisassembler *Decoder) { 2880 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2881 } 2882 2883 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2884 uint64_t Address, 2885 const MCDisassembler *Decoder) { 2886 DecodeStatus Status = MCDisassembler::Success; 2887 2888 // Note the J1 and J2 values are from the encoded instruction. So here 2889 // change them to I1 and I2 values via as documented: 2890 // I1 = NOT(J1 EOR S); 2891 // I2 = NOT(J2 EOR S); 2892 // and build the imm32 with one trailing zero as documented: 2893 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2894 unsigned S = fieldFromInstruction(Insn, 26, 1); 2895 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2896 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2897 unsigned I1 = !(J1 ^ S); 2898 unsigned I2 = !(J2 ^ S); 2899 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2900 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2901 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2902 int imm32 = SignExtend32<25>(tmp << 1); 2903 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2904 true, 4, Inst, Decoder)) 2905 Inst.addOperand(MCOperand::createImm(imm32)); 2906 2907 return Status; 2908 } 2909 2910 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2911 uint64_t Address, 2912 const MCDisassembler *Decoder) { 2913 DecodeStatus S = MCDisassembler::Success; 2914 2915 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2916 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2917 2918 if (pred == 0xF) { 2919 Inst.setOpcode(ARM::BLXi); 2920 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2921 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2922 true, 4, Inst, Decoder)) 2923 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2924 return S; 2925 } 2926 2927 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2928 true, 4, Inst, Decoder)) 2929 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2930 2931 // We already have BL_pred for BL w/ predicate, no need to add addition 2932 // predicate opreands for BL 2933 if (Inst.getOpcode() != ARM::BL) 2934 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2935 return MCDisassembler::Fail; 2936 2937 return S; 2938 } 2939 2940 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2941 uint64_t Address, 2942 const MCDisassembler *Decoder) { 2943 DecodeStatus S = MCDisassembler::Success; 2944 2945 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2946 unsigned align = fieldFromInstruction(Val, 4, 2); 2947 2948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2949 return MCDisassembler::Fail; 2950 if (!align) 2951 Inst.addOperand(MCOperand::createImm(0)); 2952 else 2953 Inst.addOperand(MCOperand::createImm(4 << align)); 2954 2955 return S; 2956 } 2957 2958 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2959 uint64_t Address, 2960 const MCDisassembler *Decoder) { 2961 DecodeStatus S = MCDisassembler::Success; 2962 2963 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2964 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2965 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2967 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2968 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2969 2970 // First output register 2971 switch (Inst.getOpcode()) { 2972 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2973 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2974 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2975 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2976 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2977 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2978 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2979 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2980 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2981 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2982 return MCDisassembler::Fail; 2983 break; 2984 case ARM::VLD2b16: 2985 case ARM::VLD2b32: 2986 case ARM::VLD2b8: 2987 case ARM::VLD2b16wb_fixed: 2988 case ARM::VLD2b16wb_register: 2989 case ARM::VLD2b32wb_fixed: 2990 case ARM::VLD2b32wb_register: 2991 case ARM::VLD2b8wb_fixed: 2992 case ARM::VLD2b8wb_register: 2993 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2994 return MCDisassembler::Fail; 2995 break; 2996 default: 2997 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 } 3000 3001 // Second output register 3002 switch (Inst.getOpcode()) { 3003 case ARM::VLD3d8: 3004 case ARM::VLD3d16: 3005 case ARM::VLD3d32: 3006 case ARM::VLD3d8_UPD: 3007 case ARM::VLD3d16_UPD: 3008 case ARM::VLD3d32_UPD: 3009 case ARM::VLD4d8: 3010 case ARM::VLD4d16: 3011 case ARM::VLD4d32: 3012 case ARM::VLD4d8_UPD: 3013 case ARM::VLD4d16_UPD: 3014 case ARM::VLD4d32_UPD: 3015 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3016 return MCDisassembler::Fail; 3017 break; 3018 case ARM::VLD3q8: 3019 case ARM::VLD3q16: 3020 case ARM::VLD3q32: 3021 case ARM::VLD3q8_UPD: 3022 case ARM::VLD3q16_UPD: 3023 case ARM::VLD3q32_UPD: 3024 case ARM::VLD4q8: 3025 case ARM::VLD4q16: 3026 case ARM::VLD4q32: 3027 case ARM::VLD4q8_UPD: 3028 case ARM::VLD4q16_UPD: 3029 case ARM::VLD4q32_UPD: 3030 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 break; 3033 default: 3034 break; 3035 } 3036 3037 // Third output register 3038 switch(Inst.getOpcode()) { 3039 case ARM::VLD3d8: 3040 case ARM::VLD3d16: 3041 case ARM::VLD3d32: 3042 case ARM::VLD3d8_UPD: 3043 case ARM::VLD3d16_UPD: 3044 case ARM::VLD3d32_UPD: 3045 case ARM::VLD4d8: 3046 case ARM::VLD4d16: 3047 case ARM::VLD4d32: 3048 case ARM::VLD4d8_UPD: 3049 case ARM::VLD4d16_UPD: 3050 case ARM::VLD4d32_UPD: 3051 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 break; 3054 case ARM::VLD3q8: 3055 case ARM::VLD3q16: 3056 case ARM::VLD3q32: 3057 case ARM::VLD3q8_UPD: 3058 case ARM::VLD3q16_UPD: 3059 case ARM::VLD3q32_UPD: 3060 case ARM::VLD4q8: 3061 case ARM::VLD4q16: 3062 case ARM::VLD4q32: 3063 case ARM::VLD4q8_UPD: 3064 case ARM::VLD4q16_UPD: 3065 case ARM::VLD4q32_UPD: 3066 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3067 return MCDisassembler::Fail; 3068 break; 3069 default: 3070 break; 3071 } 3072 3073 // Fourth output register 3074 switch (Inst.getOpcode()) { 3075 case ARM::VLD4d8: 3076 case ARM::VLD4d16: 3077 case ARM::VLD4d32: 3078 case ARM::VLD4d8_UPD: 3079 case ARM::VLD4d16_UPD: 3080 case ARM::VLD4d32_UPD: 3081 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3082 return MCDisassembler::Fail; 3083 break; 3084 case ARM::VLD4q8: 3085 case ARM::VLD4q16: 3086 case ARM::VLD4q32: 3087 case ARM::VLD4q8_UPD: 3088 case ARM::VLD4q16_UPD: 3089 case ARM::VLD4q32_UPD: 3090 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3091 return MCDisassembler::Fail; 3092 break; 3093 default: 3094 break; 3095 } 3096 3097 // Writeback operand 3098 switch (Inst.getOpcode()) { 3099 case ARM::VLD1d8wb_fixed: 3100 case ARM::VLD1d16wb_fixed: 3101 case ARM::VLD1d32wb_fixed: 3102 case ARM::VLD1d64wb_fixed: 3103 case ARM::VLD1d8wb_register: 3104 case ARM::VLD1d16wb_register: 3105 case ARM::VLD1d32wb_register: 3106 case ARM::VLD1d64wb_register: 3107 case ARM::VLD1q8wb_fixed: 3108 case ARM::VLD1q16wb_fixed: 3109 case ARM::VLD1q32wb_fixed: 3110 case ARM::VLD1q64wb_fixed: 3111 case ARM::VLD1q8wb_register: 3112 case ARM::VLD1q16wb_register: 3113 case ARM::VLD1q32wb_register: 3114 case ARM::VLD1q64wb_register: 3115 case ARM::VLD1d8Twb_fixed: 3116 case ARM::VLD1d8Twb_register: 3117 case ARM::VLD1d16Twb_fixed: 3118 case ARM::VLD1d16Twb_register: 3119 case ARM::VLD1d32Twb_fixed: 3120 case ARM::VLD1d32Twb_register: 3121 case ARM::VLD1d64Twb_fixed: 3122 case ARM::VLD1d64Twb_register: 3123 case ARM::VLD1d8Qwb_fixed: 3124 case ARM::VLD1d8Qwb_register: 3125 case ARM::VLD1d16Qwb_fixed: 3126 case ARM::VLD1d16Qwb_register: 3127 case ARM::VLD1d32Qwb_fixed: 3128 case ARM::VLD1d32Qwb_register: 3129 case ARM::VLD1d64Qwb_fixed: 3130 case ARM::VLD1d64Qwb_register: 3131 case ARM::VLD2d8wb_fixed: 3132 case ARM::VLD2d16wb_fixed: 3133 case ARM::VLD2d32wb_fixed: 3134 case ARM::VLD2q8wb_fixed: 3135 case ARM::VLD2q16wb_fixed: 3136 case ARM::VLD2q32wb_fixed: 3137 case ARM::VLD2d8wb_register: 3138 case ARM::VLD2d16wb_register: 3139 case ARM::VLD2d32wb_register: 3140 case ARM::VLD2q8wb_register: 3141 case ARM::VLD2q16wb_register: 3142 case ARM::VLD2q32wb_register: 3143 case ARM::VLD2b8wb_fixed: 3144 case ARM::VLD2b16wb_fixed: 3145 case ARM::VLD2b32wb_fixed: 3146 case ARM::VLD2b8wb_register: 3147 case ARM::VLD2b16wb_register: 3148 case ARM::VLD2b32wb_register: 3149 Inst.addOperand(MCOperand::createImm(0)); 3150 break; 3151 case ARM::VLD3d8_UPD: 3152 case ARM::VLD3d16_UPD: 3153 case ARM::VLD3d32_UPD: 3154 case ARM::VLD3q8_UPD: 3155 case ARM::VLD3q16_UPD: 3156 case ARM::VLD3q32_UPD: 3157 case ARM::VLD4d8_UPD: 3158 case ARM::VLD4d16_UPD: 3159 case ARM::VLD4d32_UPD: 3160 case ARM::VLD4q8_UPD: 3161 case ARM::VLD4q16_UPD: 3162 case ARM::VLD4q32_UPD: 3163 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3164 return MCDisassembler::Fail; 3165 break; 3166 default: 3167 break; 3168 } 3169 3170 // AddrMode6 Base (register+alignment) 3171 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3172 return MCDisassembler::Fail; 3173 3174 // AddrMode6 Offset (register) 3175 switch (Inst.getOpcode()) { 3176 default: 3177 // The below have been updated to have explicit am6offset split 3178 // between fixed and register offset. For those instructions not 3179 // yet updated, we need to add an additional reg0 operand for the 3180 // fixed variant. 3181 // 3182 // The fixed offset encodes as Rm == 0xd, so we check for that. 3183 if (Rm == 0xd) { 3184 Inst.addOperand(MCOperand::createReg(0)); 3185 break; 3186 } 3187 // Fall through to handle the register offset variant. 3188 LLVM_FALLTHROUGH; 3189 case ARM::VLD1d8wb_fixed: 3190 case ARM::VLD1d16wb_fixed: 3191 case ARM::VLD1d32wb_fixed: 3192 case ARM::VLD1d64wb_fixed: 3193 case ARM::VLD1d8Twb_fixed: 3194 case ARM::VLD1d16Twb_fixed: 3195 case ARM::VLD1d32Twb_fixed: 3196 case ARM::VLD1d64Twb_fixed: 3197 case ARM::VLD1d8Qwb_fixed: 3198 case ARM::VLD1d16Qwb_fixed: 3199 case ARM::VLD1d32Qwb_fixed: 3200 case ARM::VLD1d64Qwb_fixed: 3201 case ARM::VLD1d8wb_register: 3202 case ARM::VLD1d16wb_register: 3203 case ARM::VLD1d32wb_register: 3204 case ARM::VLD1d64wb_register: 3205 case ARM::VLD1q8wb_fixed: 3206 case ARM::VLD1q16wb_fixed: 3207 case ARM::VLD1q32wb_fixed: 3208 case ARM::VLD1q64wb_fixed: 3209 case ARM::VLD1q8wb_register: 3210 case ARM::VLD1q16wb_register: 3211 case ARM::VLD1q32wb_register: 3212 case ARM::VLD1q64wb_register: 3213 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3214 // variant encodes Rm == 0xf. Anything else is a register offset post- 3215 // increment and we need to add the register operand to the instruction. 3216 if (Rm != 0xD && Rm != 0xF && 3217 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3218 return MCDisassembler::Fail; 3219 break; 3220 case ARM::VLD2d8wb_fixed: 3221 case ARM::VLD2d16wb_fixed: 3222 case ARM::VLD2d32wb_fixed: 3223 case ARM::VLD2b8wb_fixed: 3224 case ARM::VLD2b16wb_fixed: 3225 case ARM::VLD2b32wb_fixed: 3226 case ARM::VLD2q8wb_fixed: 3227 case ARM::VLD2q16wb_fixed: 3228 case ARM::VLD2q32wb_fixed: 3229 break; 3230 } 3231 3232 return S; 3233 } 3234 3235 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3236 uint64_t Address, 3237 const MCDisassembler *Decoder) { 3238 unsigned type = fieldFromInstruction(Insn, 8, 4); 3239 unsigned align = fieldFromInstruction(Insn, 4, 2); 3240 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3241 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3242 if (type == 10 && align == 3) return MCDisassembler::Fail; 3243 3244 unsigned load = fieldFromInstruction(Insn, 21, 1); 3245 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3246 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3247 } 3248 3249 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3250 uint64_t Address, 3251 const MCDisassembler *Decoder) { 3252 unsigned size = fieldFromInstruction(Insn, 6, 2); 3253 if (size == 3) return MCDisassembler::Fail; 3254 3255 unsigned type = fieldFromInstruction(Insn, 8, 4); 3256 unsigned align = fieldFromInstruction(Insn, 4, 2); 3257 if (type == 8 && align == 3) return MCDisassembler::Fail; 3258 if (type == 9 && align == 3) return MCDisassembler::Fail; 3259 3260 unsigned load = fieldFromInstruction(Insn, 21, 1); 3261 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3262 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3263 } 3264 3265 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3266 uint64_t Address, 3267 const MCDisassembler *Decoder) { 3268 unsigned size = fieldFromInstruction(Insn, 6, 2); 3269 if (size == 3) return MCDisassembler::Fail; 3270 3271 unsigned align = fieldFromInstruction(Insn, 4, 2); 3272 if (align & 2) return MCDisassembler::Fail; 3273 3274 unsigned load = fieldFromInstruction(Insn, 21, 1); 3275 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3276 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3277 } 3278 3279 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3280 uint64_t Address, 3281 const MCDisassembler *Decoder) { 3282 unsigned size = fieldFromInstruction(Insn, 6, 2); 3283 if (size == 3) return MCDisassembler::Fail; 3284 3285 unsigned load = fieldFromInstruction(Insn, 21, 1); 3286 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3287 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3288 } 3289 3290 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3291 uint64_t Address, 3292 const MCDisassembler *Decoder) { 3293 DecodeStatus S = MCDisassembler::Success; 3294 3295 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3296 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3297 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3298 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3299 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3300 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3301 3302 // Writeback Operand 3303 switch (Inst.getOpcode()) { 3304 case ARM::VST1d8wb_fixed: 3305 case ARM::VST1d16wb_fixed: 3306 case ARM::VST1d32wb_fixed: 3307 case ARM::VST1d64wb_fixed: 3308 case ARM::VST1d8wb_register: 3309 case ARM::VST1d16wb_register: 3310 case ARM::VST1d32wb_register: 3311 case ARM::VST1d64wb_register: 3312 case ARM::VST1q8wb_fixed: 3313 case ARM::VST1q16wb_fixed: 3314 case ARM::VST1q32wb_fixed: 3315 case ARM::VST1q64wb_fixed: 3316 case ARM::VST1q8wb_register: 3317 case ARM::VST1q16wb_register: 3318 case ARM::VST1q32wb_register: 3319 case ARM::VST1q64wb_register: 3320 case ARM::VST1d8Twb_fixed: 3321 case ARM::VST1d16Twb_fixed: 3322 case ARM::VST1d32Twb_fixed: 3323 case ARM::VST1d64Twb_fixed: 3324 case ARM::VST1d8Twb_register: 3325 case ARM::VST1d16Twb_register: 3326 case ARM::VST1d32Twb_register: 3327 case ARM::VST1d64Twb_register: 3328 case ARM::VST1d8Qwb_fixed: 3329 case ARM::VST1d16Qwb_fixed: 3330 case ARM::VST1d32Qwb_fixed: 3331 case ARM::VST1d64Qwb_fixed: 3332 case ARM::VST1d8Qwb_register: 3333 case ARM::VST1d16Qwb_register: 3334 case ARM::VST1d32Qwb_register: 3335 case ARM::VST1d64Qwb_register: 3336 case ARM::VST2d8wb_fixed: 3337 case ARM::VST2d16wb_fixed: 3338 case ARM::VST2d32wb_fixed: 3339 case ARM::VST2d8wb_register: 3340 case ARM::VST2d16wb_register: 3341 case ARM::VST2d32wb_register: 3342 case ARM::VST2q8wb_fixed: 3343 case ARM::VST2q16wb_fixed: 3344 case ARM::VST2q32wb_fixed: 3345 case ARM::VST2q8wb_register: 3346 case ARM::VST2q16wb_register: 3347 case ARM::VST2q32wb_register: 3348 case ARM::VST2b8wb_fixed: 3349 case ARM::VST2b16wb_fixed: 3350 case ARM::VST2b32wb_fixed: 3351 case ARM::VST2b8wb_register: 3352 case ARM::VST2b16wb_register: 3353 case ARM::VST2b32wb_register: 3354 if (Rm == 0xF) 3355 return MCDisassembler::Fail; 3356 Inst.addOperand(MCOperand::createImm(0)); 3357 break; 3358 case ARM::VST3d8_UPD: 3359 case ARM::VST3d16_UPD: 3360 case ARM::VST3d32_UPD: 3361 case ARM::VST3q8_UPD: 3362 case ARM::VST3q16_UPD: 3363 case ARM::VST3q32_UPD: 3364 case ARM::VST4d8_UPD: 3365 case ARM::VST4d16_UPD: 3366 case ARM::VST4d32_UPD: 3367 case ARM::VST4q8_UPD: 3368 case ARM::VST4q16_UPD: 3369 case ARM::VST4q32_UPD: 3370 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3371 return MCDisassembler::Fail; 3372 break; 3373 default: 3374 break; 3375 } 3376 3377 // AddrMode6 Base (register+alignment) 3378 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3379 return MCDisassembler::Fail; 3380 3381 // AddrMode6 Offset (register) 3382 switch (Inst.getOpcode()) { 3383 default: 3384 if (Rm == 0xD) 3385 Inst.addOperand(MCOperand::createReg(0)); 3386 else if (Rm != 0xF) { 3387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 } 3390 break; 3391 case ARM::VST1d8wb_fixed: 3392 case ARM::VST1d16wb_fixed: 3393 case ARM::VST1d32wb_fixed: 3394 case ARM::VST1d64wb_fixed: 3395 case ARM::VST1q8wb_fixed: 3396 case ARM::VST1q16wb_fixed: 3397 case ARM::VST1q32wb_fixed: 3398 case ARM::VST1q64wb_fixed: 3399 case ARM::VST1d8Twb_fixed: 3400 case ARM::VST1d16Twb_fixed: 3401 case ARM::VST1d32Twb_fixed: 3402 case ARM::VST1d64Twb_fixed: 3403 case ARM::VST1d8Qwb_fixed: 3404 case ARM::VST1d16Qwb_fixed: 3405 case ARM::VST1d32Qwb_fixed: 3406 case ARM::VST1d64Qwb_fixed: 3407 case ARM::VST2d8wb_fixed: 3408 case ARM::VST2d16wb_fixed: 3409 case ARM::VST2d32wb_fixed: 3410 case ARM::VST2q8wb_fixed: 3411 case ARM::VST2q16wb_fixed: 3412 case ARM::VST2q32wb_fixed: 3413 case ARM::VST2b8wb_fixed: 3414 case ARM::VST2b16wb_fixed: 3415 case ARM::VST2b32wb_fixed: 3416 break; 3417 } 3418 3419 // First input register 3420 switch (Inst.getOpcode()) { 3421 case ARM::VST1q16: 3422 case ARM::VST1q32: 3423 case ARM::VST1q64: 3424 case ARM::VST1q8: 3425 case ARM::VST1q16wb_fixed: 3426 case ARM::VST1q16wb_register: 3427 case ARM::VST1q32wb_fixed: 3428 case ARM::VST1q32wb_register: 3429 case ARM::VST1q64wb_fixed: 3430 case ARM::VST1q64wb_register: 3431 case ARM::VST1q8wb_fixed: 3432 case ARM::VST1q8wb_register: 3433 case ARM::VST2d16: 3434 case ARM::VST2d32: 3435 case ARM::VST2d8: 3436 case ARM::VST2d16wb_fixed: 3437 case ARM::VST2d16wb_register: 3438 case ARM::VST2d32wb_fixed: 3439 case ARM::VST2d32wb_register: 3440 case ARM::VST2d8wb_fixed: 3441 case ARM::VST2d8wb_register: 3442 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 break; 3445 case ARM::VST2b16: 3446 case ARM::VST2b32: 3447 case ARM::VST2b8: 3448 case ARM::VST2b16wb_fixed: 3449 case ARM::VST2b16wb_register: 3450 case ARM::VST2b32wb_fixed: 3451 case ARM::VST2b32wb_register: 3452 case ARM::VST2b8wb_fixed: 3453 case ARM::VST2b8wb_register: 3454 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 break; 3457 default: 3458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 } 3461 3462 // Second input register 3463 switch (Inst.getOpcode()) { 3464 case ARM::VST3d8: 3465 case ARM::VST3d16: 3466 case ARM::VST3d32: 3467 case ARM::VST3d8_UPD: 3468 case ARM::VST3d16_UPD: 3469 case ARM::VST3d32_UPD: 3470 case ARM::VST4d8: 3471 case ARM::VST4d16: 3472 case ARM::VST4d32: 3473 case ARM::VST4d8_UPD: 3474 case ARM::VST4d16_UPD: 3475 case ARM::VST4d32_UPD: 3476 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3477 return MCDisassembler::Fail; 3478 break; 3479 case ARM::VST3q8: 3480 case ARM::VST3q16: 3481 case ARM::VST3q32: 3482 case ARM::VST3q8_UPD: 3483 case ARM::VST3q16_UPD: 3484 case ARM::VST3q32_UPD: 3485 case ARM::VST4q8: 3486 case ARM::VST4q16: 3487 case ARM::VST4q32: 3488 case ARM::VST4q8_UPD: 3489 case ARM::VST4q16_UPD: 3490 case ARM::VST4q32_UPD: 3491 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3492 return MCDisassembler::Fail; 3493 break; 3494 default: 3495 break; 3496 } 3497 3498 // Third input register 3499 switch (Inst.getOpcode()) { 3500 case ARM::VST3d8: 3501 case ARM::VST3d16: 3502 case ARM::VST3d32: 3503 case ARM::VST3d8_UPD: 3504 case ARM::VST3d16_UPD: 3505 case ARM::VST3d32_UPD: 3506 case ARM::VST4d8: 3507 case ARM::VST4d16: 3508 case ARM::VST4d32: 3509 case ARM::VST4d8_UPD: 3510 case ARM::VST4d16_UPD: 3511 case ARM::VST4d32_UPD: 3512 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 break; 3515 case ARM::VST3q8: 3516 case ARM::VST3q16: 3517 case ARM::VST3q32: 3518 case ARM::VST3q8_UPD: 3519 case ARM::VST3q16_UPD: 3520 case ARM::VST3q32_UPD: 3521 case ARM::VST4q8: 3522 case ARM::VST4q16: 3523 case ARM::VST4q32: 3524 case ARM::VST4q8_UPD: 3525 case ARM::VST4q16_UPD: 3526 case ARM::VST4q32_UPD: 3527 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3528 return MCDisassembler::Fail; 3529 break; 3530 default: 3531 break; 3532 } 3533 3534 // Fourth input register 3535 switch (Inst.getOpcode()) { 3536 case ARM::VST4d8: 3537 case ARM::VST4d16: 3538 case ARM::VST4d32: 3539 case ARM::VST4d8_UPD: 3540 case ARM::VST4d16_UPD: 3541 case ARM::VST4d32_UPD: 3542 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3543 return MCDisassembler::Fail; 3544 break; 3545 case ARM::VST4q8: 3546 case ARM::VST4q16: 3547 case ARM::VST4q32: 3548 case ARM::VST4q8_UPD: 3549 case ARM::VST4q16_UPD: 3550 case ARM::VST4q32_UPD: 3551 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3552 return MCDisassembler::Fail; 3553 break; 3554 default: 3555 break; 3556 } 3557 3558 return S; 3559 } 3560 3561 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3562 uint64_t Address, 3563 const MCDisassembler *Decoder) { 3564 DecodeStatus S = MCDisassembler::Success; 3565 3566 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3567 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3568 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3569 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3570 unsigned align = fieldFromInstruction(Insn, 4, 1); 3571 unsigned size = fieldFromInstruction(Insn, 6, 2); 3572 3573 if (size == 0 && align == 1) 3574 return MCDisassembler::Fail; 3575 align *= (1 << size); 3576 3577 switch (Inst.getOpcode()) { 3578 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3579 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3580 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3581 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3582 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3583 return MCDisassembler::Fail; 3584 break; 3585 default: 3586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3587 return MCDisassembler::Fail; 3588 break; 3589 } 3590 if (Rm != 0xF) { 3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 } 3594 3595 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3596 return MCDisassembler::Fail; 3597 Inst.addOperand(MCOperand::createImm(align)); 3598 3599 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3600 // variant encodes Rm == 0xf. Anything else is a register offset post- 3601 // increment and we need to add the register operand to the instruction. 3602 if (Rm != 0xD && Rm != 0xF && 3603 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3604 return MCDisassembler::Fail; 3605 3606 return S; 3607 } 3608 3609 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3610 uint64_t Address, 3611 const MCDisassembler *Decoder) { 3612 DecodeStatus S = MCDisassembler::Success; 3613 3614 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3615 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3616 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3617 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3618 unsigned align = fieldFromInstruction(Insn, 4, 1); 3619 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3620 align *= 2*size; 3621 3622 switch (Inst.getOpcode()) { 3623 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3624 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3625 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3626 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3627 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3628 return MCDisassembler::Fail; 3629 break; 3630 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3631 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3632 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3633 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3634 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3635 return MCDisassembler::Fail; 3636 break; 3637 default: 3638 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3639 return MCDisassembler::Fail; 3640 break; 3641 } 3642 3643 if (Rm != 0xF) 3644 Inst.addOperand(MCOperand::createImm(0)); 3645 3646 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 Inst.addOperand(MCOperand::createImm(align)); 3649 3650 if (Rm != 0xD && Rm != 0xF) { 3651 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3652 return MCDisassembler::Fail; 3653 } 3654 3655 return S; 3656 } 3657 3658 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3659 uint64_t Address, 3660 const MCDisassembler *Decoder) { 3661 DecodeStatus S = MCDisassembler::Success; 3662 3663 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3664 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3665 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3666 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3667 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3668 3669 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3670 return MCDisassembler::Fail; 3671 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3672 return MCDisassembler::Fail; 3673 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3674 return MCDisassembler::Fail; 3675 if (Rm != 0xF) { 3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3677 return MCDisassembler::Fail; 3678 } 3679 3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3681 return MCDisassembler::Fail; 3682 Inst.addOperand(MCOperand::createImm(0)); 3683 3684 if (Rm == 0xD) 3685 Inst.addOperand(MCOperand::createReg(0)); 3686 else if (Rm != 0xF) { 3687 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3688 return MCDisassembler::Fail; 3689 } 3690 3691 return S; 3692 } 3693 3694 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3695 uint64_t Address, 3696 const MCDisassembler *Decoder) { 3697 DecodeStatus S = MCDisassembler::Success; 3698 3699 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3700 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3701 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3702 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3703 unsigned size = fieldFromInstruction(Insn, 6, 2); 3704 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3705 unsigned align = fieldFromInstruction(Insn, 4, 1); 3706 3707 if (size == 0x3) { 3708 if (align == 0) 3709 return MCDisassembler::Fail; 3710 align = 16; 3711 } else { 3712 if (size == 2) { 3713 align *= 8; 3714 } else { 3715 size = 1 << size; 3716 align *= 4*size; 3717 } 3718 } 3719 3720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3721 return MCDisassembler::Fail; 3722 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3723 return MCDisassembler::Fail; 3724 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3725 return MCDisassembler::Fail; 3726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3727 return MCDisassembler::Fail; 3728 if (Rm != 0xF) { 3729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3730 return MCDisassembler::Fail; 3731 } 3732 3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3734 return MCDisassembler::Fail; 3735 Inst.addOperand(MCOperand::createImm(align)); 3736 3737 if (Rm == 0xD) 3738 Inst.addOperand(MCOperand::createReg(0)); 3739 else if (Rm != 0xF) { 3740 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3741 return MCDisassembler::Fail; 3742 } 3743 3744 return S; 3745 } 3746 3747 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3748 uint64_t Address, 3749 const MCDisassembler *Decoder) { 3750 DecodeStatus S = MCDisassembler::Success; 3751 3752 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3753 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3754 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3755 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3756 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3757 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3758 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3759 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3760 3761 if (Q) { 3762 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3763 return MCDisassembler::Fail; 3764 } else { 3765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3766 return MCDisassembler::Fail; 3767 } 3768 3769 Inst.addOperand(MCOperand::createImm(imm)); 3770 3771 switch (Inst.getOpcode()) { 3772 case ARM::VORRiv4i16: 3773 case ARM::VORRiv2i32: 3774 case ARM::VBICiv4i16: 3775 case ARM::VBICiv2i32: 3776 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3777 return MCDisassembler::Fail; 3778 break; 3779 case ARM::VORRiv8i16: 3780 case ARM::VORRiv4i32: 3781 case ARM::VBICiv8i16: 3782 case ARM::VBICiv4i32: 3783 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3784 return MCDisassembler::Fail; 3785 break; 3786 default: 3787 break; 3788 } 3789 3790 return S; 3791 } 3792 3793 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3794 uint64_t Address, 3795 const MCDisassembler *Decoder) { 3796 DecodeStatus S = MCDisassembler::Success; 3797 3798 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3799 fieldFromInstruction(Insn, 13, 3)); 3800 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3801 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3802 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3803 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3804 imm |= cmode << 8; 3805 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3806 3807 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3808 return MCDisassembler::Fail; 3809 3810 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3811 return MCDisassembler::Fail; 3812 3813 Inst.addOperand(MCOperand::createImm(imm)); 3814 3815 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3816 Inst.addOperand(MCOperand::createReg(0)); 3817 Inst.addOperand(MCOperand::createImm(0)); 3818 3819 return S; 3820 } 3821 3822 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3823 uint64_t Address, 3824 const MCDisassembler *Decoder) { 3825 DecodeStatus S = MCDisassembler::Success; 3826 3827 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3828 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3829 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3832 3833 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3834 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3835 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3836 return MCDisassembler::Fail; 3837 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3838 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3839 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3840 return MCDisassembler::Fail; 3841 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3842 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3843 Inst.addOperand(MCOperand::createImm(Qd)); 3844 3845 return S; 3846 } 3847 3848 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3849 uint64_t Address, 3850 const MCDisassembler *Decoder) { 3851 DecodeStatus S = MCDisassembler::Success; 3852 3853 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3854 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3855 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3856 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3857 unsigned size = fieldFromInstruction(Insn, 18, 2); 3858 3859 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3860 return MCDisassembler::Fail; 3861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3862 return MCDisassembler::Fail; 3863 Inst.addOperand(MCOperand::createImm(8 << size)); 3864 3865 return S; 3866 } 3867 3868 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3869 uint64_t Address, 3870 const MCDisassembler *Decoder) { 3871 Inst.addOperand(MCOperand::createImm(8 - Val)); 3872 return MCDisassembler::Success; 3873 } 3874 3875 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3876 uint64_t Address, 3877 const MCDisassembler *Decoder) { 3878 Inst.addOperand(MCOperand::createImm(16 - Val)); 3879 return MCDisassembler::Success; 3880 } 3881 3882 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3883 uint64_t Address, 3884 const MCDisassembler *Decoder) { 3885 Inst.addOperand(MCOperand::createImm(32 - Val)); 3886 return MCDisassembler::Success; 3887 } 3888 3889 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3890 uint64_t Address, 3891 const MCDisassembler *Decoder) { 3892 Inst.addOperand(MCOperand::createImm(64 - Val)); 3893 return MCDisassembler::Success; 3894 } 3895 3896 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3897 uint64_t Address, 3898 const MCDisassembler *Decoder) { 3899 DecodeStatus S = MCDisassembler::Success; 3900 3901 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3902 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3903 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3904 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3905 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3906 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3907 unsigned op = fieldFromInstruction(Insn, 6, 1); 3908 3909 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3910 return MCDisassembler::Fail; 3911 if (op) { 3912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3913 return MCDisassembler::Fail; // Writeback 3914 } 3915 3916 switch (Inst.getOpcode()) { 3917 case ARM::VTBL2: 3918 case ARM::VTBX2: 3919 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3920 return MCDisassembler::Fail; 3921 break; 3922 default: 3923 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3924 return MCDisassembler::Fail; 3925 } 3926 3927 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3928 return MCDisassembler::Fail; 3929 3930 return S; 3931 } 3932 3933 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3934 uint64_t Address, 3935 const MCDisassembler *Decoder) { 3936 DecodeStatus S = MCDisassembler::Success; 3937 3938 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3939 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3940 3941 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3942 return MCDisassembler::Fail; 3943 3944 switch(Inst.getOpcode()) { 3945 default: 3946 return MCDisassembler::Fail; 3947 case ARM::tADR: 3948 break; // tADR does not explicitly represent the PC as an operand. 3949 case ARM::tADDrSPi: 3950 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3951 break; 3952 } 3953 3954 Inst.addOperand(MCOperand::createImm(imm)); 3955 return S; 3956 } 3957 3958 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3959 uint64_t Address, 3960 const MCDisassembler *Decoder) { 3961 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3962 true, 2, Inst, Decoder)) 3963 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3964 return MCDisassembler::Success; 3965 } 3966 3967 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3968 uint64_t Address, 3969 const MCDisassembler *Decoder) { 3970 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3971 true, 4, Inst, Decoder)) 3972 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3973 return MCDisassembler::Success; 3974 } 3975 3976 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3977 uint64_t Address, 3978 const MCDisassembler *Decoder) { 3979 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3980 true, 2, Inst, Decoder)) 3981 Inst.addOperand(MCOperand::createImm(Val << 1)); 3982 return MCDisassembler::Success; 3983 } 3984 3985 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3986 uint64_t Address, 3987 const MCDisassembler *Decoder) { 3988 DecodeStatus S = MCDisassembler::Success; 3989 3990 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3991 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3992 3993 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3994 return MCDisassembler::Fail; 3995 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3996 return MCDisassembler::Fail; 3997 3998 return S; 3999 } 4000 4001 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 4002 uint64_t Address, 4003 const MCDisassembler *Decoder) { 4004 DecodeStatus S = MCDisassembler::Success; 4005 4006 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4007 unsigned imm = fieldFromInstruction(Val, 3, 5); 4008 4009 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4010 return MCDisassembler::Fail; 4011 Inst.addOperand(MCOperand::createImm(imm)); 4012 4013 return S; 4014 } 4015 4016 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4017 uint64_t Address, 4018 const MCDisassembler *Decoder) { 4019 unsigned imm = Val << 2; 4020 4021 Inst.addOperand(MCOperand::createImm(imm)); 4022 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4023 4024 return MCDisassembler::Success; 4025 } 4026 4027 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4028 uint64_t Address, 4029 const MCDisassembler *Decoder) { 4030 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4031 Inst.addOperand(MCOperand::createImm(Val)); 4032 4033 return MCDisassembler::Success; 4034 } 4035 4036 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4037 uint64_t Address, 4038 const MCDisassembler *Decoder) { 4039 DecodeStatus S = MCDisassembler::Success; 4040 4041 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4042 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4043 unsigned imm = fieldFromInstruction(Val, 0, 2); 4044 4045 // Thumb stores cannot use PC as dest register. 4046 switch (Inst.getOpcode()) { 4047 case ARM::t2STRHs: 4048 case ARM::t2STRBs: 4049 case ARM::t2STRs: 4050 if (Rn == 15) 4051 return MCDisassembler::Fail; 4052 break; 4053 default: 4054 break; 4055 } 4056 4057 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4058 return MCDisassembler::Fail; 4059 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4060 return MCDisassembler::Fail; 4061 Inst.addOperand(MCOperand::createImm(imm)); 4062 4063 return S; 4064 } 4065 4066 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4067 uint64_t Address, 4068 const MCDisassembler *Decoder) { 4069 DecodeStatus S = MCDisassembler::Success; 4070 4071 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4072 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4073 4074 const FeatureBitset &featureBits = 4075 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4076 4077 bool hasMP = featureBits[ARM::FeatureMP]; 4078 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4079 4080 if (Rn == 15) { 4081 switch (Inst.getOpcode()) { 4082 case ARM::t2LDRBs: 4083 Inst.setOpcode(ARM::t2LDRBpci); 4084 break; 4085 case ARM::t2LDRHs: 4086 Inst.setOpcode(ARM::t2LDRHpci); 4087 break; 4088 case ARM::t2LDRSHs: 4089 Inst.setOpcode(ARM::t2LDRSHpci); 4090 break; 4091 case ARM::t2LDRSBs: 4092 Inst.setOpcode(ARM::t2LDRSBpci); 4093 break; 4094 case ARM::t2LDRs: 4095 Inst.setOpcode(ARM::t2LDRpci); 4096 break; 4097 case ARM::t2PLDs: 4098 Inst.setOpcode(ARM::t2PLDpci); 4099 break; 4100 case ARM::t2PLIs: 4101 Inst.setOpcode(ARM::t2PLIpci); 4102 break; 4103 default: 4104 return MCDisassembler::Fail; 4105 } 4106 4107 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4108 } 4109 4110 if (Rt == 15) { 4111 switch (Inst.getOpcode()) { 4112 case ARM::t2LDRSHs: 4113 return MCDisassembler::Fail; 4114 case ARM::t2LDRHs: 4115 Inst.setOpcode(ARM::t2PLDWs); 4116 break; 4117 case ARM::t2LDRSBs: 4118 Inst.setOpcode(ARM::t2PLIs); 4119 break; 4120 default: 4121 break; 4122 } 4123 } 4124 4125 switch (Inst.getOpcode()) { 4126 case ARM::t2PLDs: 4127 break; 4128 case ARM::t2PLIs: 4129 if (!hasV7Ops) 4130 return MCDisassembler::Fail; 4131 break; 4132 case ARM::t2PLDWs: 4133 if (!hasV7Ops || !hasMP) 4134 return MCDisassembler::Fail; 4135 break; 4136 default: 4137 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4138 return MCDisassembler::Fail; 4139 } 4140 4141 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4142 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4143 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4144 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4145 return MCDisassembler::Fail; 4146 4147 return S; 4148 } 4149 4150 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4151 uint64_t Address, 4152 const MCDisassembler *Decoder) { 4153 DecodeStatus S = MCDisassembler::Success; 4154 4155 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4156 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4157 unsigned U = fieldFromInstruction(Insn, 9, 1); 4158 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4159 imm |= (U << 8); 4160 imm |= (Rn << 9); 4161 unsigned add = fieldFromInstruction(Insn, 9, 1); 4162 4163 const FeatureBitset &featureBits = 4164 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4165 4166 bool hasMP = featureBits[ARM::FeatureMP]; 4167 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4168 4169 if (Rn == 15) { 4170 switch (Inst.getOpcode()) { 4171 case ARM::t2LDRi8: 4172 Inst.setOpcode(ARM::t2LDRpci); 4173 break; 4174 case ARM::t2LDRBi8: 4175 Inst.setOpcode(ARM::t2LDRBpci); 4176 break; 4177 case ARM::t2LDRSBi8: 4178 Inst.setOpcode(ARM::t2LDRSBpci); 4179 break; 4180 case ARM::t2LDRHi8: 4181 Inst.setOpcode(ARM::t2LDRHpci); 4182 break; 4183 case ARM::t2LDRSHi8: 4184 Inst.setOpcode(ARM::t2LDRSHpci); 4185 break; 4186 case ARM::t2PLDi8: 4187 Inst.setOpcode(ARM::t2PLDpci); 4188 break; 4189 case ARM::t2PLIi8: 4190 Inst.setOpcode(ARM::t2PLIpci); 4191 break; 4192 default: 4193 return MCDisassembler::Fail; 4194 } 4195 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4196 } 4197 4198 if (Rt == 15) { 4199 switch (Inst.getOpcode()) { 4200 case ARM::t2LDRSHi8: 4201 return MCDisassembler::Fail; 4202 case ARM::t2LDRHi8: 4203 if (!add) 4204 Inst.setOpcode(ARM::t2PLDWi8); 4205 break; 4206 case ARM::t2LDRSBi8: 4207 Inst.setOpcode(ARM::t2PLIi8); 4208 break; 4209 default: 4210 break; 4211 } 4212 } 4213 4214 switch (Inst.getOpcode()) { 4215 case ARM::t2PLDi8: 4216 break; 4217 case ARM::t2PLIi8: 4218 if (!hasV7Ops) 4219 return MCDisassembler::Fail; 4220 break; 4221 case ARM::t2PLDWi8: 4222 if (!hasV7Ops || !hasMP) 4223 return MCDisassembler::Fail; 4224 break; 4225 default: 4226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 } 4229 4230 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4231 return MCDisassembler::Fail; 4232 return S; 4233 } 4234 4235 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4236 uint64_t Address, 4237 const MCDisassembler *Decoder) { 4238 DecodeStatus S = MCDisassembler::Success; 4239 4240 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4241 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4242 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4243 imm |= (Rn << 13); 4244 4245 const FeatureBitset &featureBits = 4246 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4247 4248 bool hasMP = featureBits[ARM::FeatureMP]; 4249 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4250 4251 if (Rn == 15) { 4252 switch (Inst.getOpcode()) { 4253 case ARM::t2LDRi12: 4254 Inst.setOpcode(ARM::t2LDRpci); 4255 break; 4256 case ARM::t2LDRHi12: 4257 Inst.setOpcode(ARM::t2LDRHpci); 4258 break; 4259 case ARM::t2LDRSHi12: 4260 Inst.setOpcode(ARM::t2LDRSHpci); 4261 break; 4262 case ARM::t2LDRBi12: 4263 Inst.setOpcode(ARM::t2LDRBpci); 4264 break; 4265 case ARM::t2LDRSBi12: 4266 Inst.setOpcode(ARM::t2LDRSBpci); 4267 break; 4268 case ARM::t2PLDi12: 4269 Inst.setOpcode(ARM::t2PLDpci); 4270 break; 4271 case ARM::t2PLIi12: 4272 Inst.setOpcode(ARM::t2PLIpci); 4273 break; 4274 default: 4275 return MCDisassembler::Fail; 4276 } 4277 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4278 } 4279 4280 if (Rt == 15) { 4281 switch (Inst.getOpcode()) { 4282 case ARM::t2LDRSHi12: 4283 return MCDisassembler::Fail; 4284 case ARM::t2LDRHi12: 4285 Inst.setOpcode(ARM::t2PLDWi12); 4286 break; 4287 case ARM::t2LDRSBi12: 4288 Inst.setOpcode(ARM::t2PLIi12); 4289 break; 4290 default: 4291 break; 4292 } 4293 } 4294 4295 switch (Inst.getOpcode()) { 4296 case ARM::t2PLDi12: 4297 break; 4298 case ARM::t2PLIi12: 4299 if (!hasV7Ops) 4300 return MCDisassembler::Fail; 4301 break; 4302 case ARM::t2PLDWi12: 4303 if (!hasV7Ops || !hasMP) 4304 return MCDisassembler::Fail; 4305 break; 4306 default: 4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4308 return MCDisassembler::Fail; 4309 } 4310 4311 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4312 return MCDisassembler::Fail; 4313 return S; 4314 } 4315 4316 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4317 const MCDisassembler *Decoder) { 4318 DecodeStatus S = MCDisassembler::Success; 4319 4320 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4321 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4322 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4323 imm |= (Rn << 9); 4324 4325 if (Rn == 15) { 4326 switch (Inst.getOpcode()) { 4327 case ARM::t2LDRT: 4328 Inst.setOpcode(ARM::t2LDRpci); 4329 break; 4330 case ARM::t2LDRBT: 4331 Inst.setOpcode(ARM::t2LDRBpci); 4332 break; 4333 case ARM::t2LDRHT: 4334 Inst.setOpcode(ARM::t2LDRHpci); 4335 break; 4336 case ARM::t2LDRSBT: 4337 Inst.setOpcode(ARM::t2LDRSBpci); 4338 break; 4339 case ARM::t2LDRSHT: 4340 Inst.setOpcode(ARM::t2LDRSHpci); 4341 break; 4342 default: 4343 return MCDisassembler::Fail; 4344 } 4345 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4346 } 4347 4348 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4349 return MCDisassembler::Fail; 4350 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 return S; 4353 } 4354 4355 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4356 uint64_t Address, 4357 const MCDisassembler *Decoder) { 4358 DecodeStatus S = MCDisassembler::Success; 4359 4360 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4361 unsigned U = fieldFromInstruction(Insn, 23, 1); 4362 int imm = fieldFromInstruction(Insn, 0, 12); 4363 4364 const FeatureBitset &featureBits = 4365 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4366 4367 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4368 4369 if (Rt == 15) { 4370 switch (Inst.getOpcode()) { 4371 case ARM::t2LDRBpci: 4372 case ARM::t2LDRHpci: 4373 Inst.setOpcode(ARM::t2PLDpci); 4374 break; 4375 case ARM::t2LDRSBpci: 4376 Inst.setOpcode(ARM::t2PLIpci); 4377 break; 4378 case ARM::t2LDRSHpci: 4379 return MCDisassembler::Fail; 4380 default: 4381 break; 4382 } 4383 } 4384 4385 switch(Inst.getOpcode()) { 4386 case ARM::t2PLDpci: 4387 break; 4388 case ARM::t2PLIpci: 4389 if (!hasV7Ops) 4390 return MCDisassembler::Fail; 4391 break; 4392 default: 4393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4394 return MCDisassembler::Fail; 4395 } 4396 4397 if (!U) { 4398 // Special case for #-0. 4399 if (imm == 0) 4400 imm = INT32_MIN; 4401 else 4402 imm = -imm; 4403 } 4404 Inst.addOperand(MCOperand::createImm(imm)); 4405 4406 return S; 4407 } 4408 4409 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4410 const MCDisassembler *Decoder) { 4411 if (Val == 0) 4412 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4413 else { 4414 int imm = Val & 0xFF; 4415 4416 if (!(Val & 0x100)) imm *= -1; 4417 Inst.addOperand(MCOperand::createImm(imm * 4)); 4418 } 4419 4420 return MCDisassembler::Success; 4421 } 4422 4423 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4424 const MCDisassembler *Decoder) { 4425 if (Val == 0) 4426 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4427 else { 4428 int imm = Val & 0x7F; 4429 4430 if (!(Val & 0x80)) 4431 imm *= -1; 4432 Inst.addOperand(MCOperand::createImm(imm * 4)); 4433 } 4434 4435 return MCDisassembler::Success; 4436 } 4437 4438 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4439 uint64_t Address, 4440 const MCDisassembler *Decoder) { 4441 DecodeStatus S = MCDisassembler::Success; 4442 4443 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4444 unsigned imm = fieldFromInstruction(Val, 0, 9); 4445 4446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4447 return MCDisassembler::Fail; 4448 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4449 return MCDisassembler::Fail; 4450 4451 return S; 4452 } 4453 4454 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4455 uint64_t Address, 4456 const MCDisassembler *Decoder) { 4457 DecodeStatus S = MCDisassembler::Success; 4458 4459 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4460 unsigned imm = fieldFromInstruction(Val, 0, 8); 4461 4462 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4463 return MCDisassembler::Fail; 4464 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4465 return MCDisassembler::Fail; 4466 4467 return S; 4468 } 4469 4470 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4471 uint64_t Address, 4472 const MCDisassembler *Decoder) { 4473 DecodeStatus S = MCDisassembler::Success; 4474 4475 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4476 unsigned imm = fieldFromInstruction(Val, 0, 8); 4477 4478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4479 return MCDisassembler::Fail; 4480 4481 Inst.addOperand(MCOperand::createImm(imm)); 4482 4483 return S; 4484 } 4485 4486 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4487 const MCDisassembler *Decoder) { 4488 int imm = Val & 0xFF; 4489 if (Val == 0) 4490 imm = INT32_MIN; 4491 else if (!(Val & 0x100)) 4492 imm *= -1; 4493 Inst.addOperand(MCOperand::createImm(imm)); 4494 4495 return MCDisassembler::Success; 4496 } 4497 4498 template <int shift> 4499 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4500 const MCDisassembler *Decoder) { 4501 int imm = Val & 0x7F; 4502 if (Val == 0) 4503 imm = INT32_MIN; 4504 else if (!(Val & 0x80)) 4505 imm *= -1; 4506 if (imm != INT32_MIN) 4507 imm *= (1U << shift); 4508 Inst.addOperand(MCOperand::createImm(imm)); 4509 4510 return MCDisassembler::Success; 4511 } 4512 4513 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4514 uint64_t Address, 4515 const MCDisassembler *Decoder) { 4516 DecodeStatus S = MCDisassembler::Success; 4517 4518 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4519 unsigned imm = fieldFromInstruction(Val, 0, 9); 4520 4521 // Thumb stores cannot use PC as dest register. 4522 switch (Inst.getOpcode()) { 4523 case ARM::t2STRT: 4524 case ARM::t2STRBT: 4525 case ARM::t2STRHT: 4526 case ARM::t2STRi8: 4527 case ARM::t2STRHi8: 4528 case ARM::t2STRBi8: 4529 if (Rn == 15) 4530 return MCDisassembler::Fail; 4531 break; 4532 default: 4533 break; 4534 } 4535 4536 // Some instructions always use an additive offset. 4537 switch (Inst.getOpcode()) { 4538 case ARM::t2LDRT: 4539 case ARM::t2LDRBT: 4540 case ARM::t2LDRHT: 4541 case ARM::t2LDRSBT: 4542 case ARM::t2LDRSHT: 4543 case ARM::t2STRT: 4544 case ARM::t2STRBT: 4545 case ARM::t2STRHT: 4546 imm |= 0x100; 4547 break; 4548 default: 4549 break; 4550 } 4551 4552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4553 return MCDisassembler::Fail; 4554 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4555 return MCDisassembler::Fail; 4556 4557 return S; 4558 } 4559 4560 template <int shift> 4561 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4562 uint64_t Address, 4563 const MCDisassembler *Decoder) { 4564 DecodeStatus S = MCDisassembler::Success; 4565 4566 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4567 unsigned imm = fieldFromInstruction(Val, 0, 8); 4568 4569 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4570 return MCDisassembler::Fail; 4571 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 4574 return S; 4575 } 4576 4577 template <int shift, int WriteBack> 4578 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4579 uint64_t Address, 4580 const MCDisassembler *Decoder) { 4581 DecodeStatus S = MCDisassembler::Success; 4582 4583 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4584 unsigned imm = fieldFromInstruction(Val, 0, 8); 4585 if (WriteBack) { 4586 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4589 return MCDisassembler::Fail; 4590 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4591 return MCDisassembler::Fail; 4592 4593 return S; 4594 } 4595 4596 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4597 uint64_t Address, 4598 const MCDisassembler *Decoder) { 4599 DecodeStatus S = MCDisassembler::Success; 4600 4601 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4602 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4603 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4604 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4605 addr |= Rn << 9; 4606 unsigned load = fieldFromInstruction(Insn, 20, 1); 4607 4608 if (Rn == 15) { 4609 switch (Inst.getOpcode()) { 4610 case ARM::t2LDR_PRE: 4611 case ARM::t2LDR_POST: 4612 Inst.setOpcode(ARM::t2LDRpci); 4613 break; 4614 case ARM::t2LDRB_PRE: 4615 case ARM::t2LDRB_POST: 4616 Inst.setOpcode(ARM::t2LDRBpci); 4617 break; 4618 case ARM::t2LDRH_PRE: 4619 case ARM::t2LDRH_POST: 4620 Inst.setOpcode(ARM::t2LDRHpci); 4621 break; 4622 case ARM::t2LDRSB_PRE: 4623 case ARM::t2LDRSB_POST: 4624 if (Rt == 15) 4625 Inst.setOpcode(ARM::t2PLIpci); 4626 else 4627 Inst.setOpcode(ARM::t2LDRSBpci); 4628 break; 4629 case ARM::t2LDRSH_PRE: 4630 case ARM::t2LDRSH_POST: 4631 Inst.setOpcode(ARM::t2LDRSHpci); 4632 break; 4633 default: 4634 return MCDisassembler::Fail; 4635 } 4636 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4637 } 4638 4639 if (!load) { 4640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4641 return MCDisassembler::Fail; 4642 } 4643 4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4645 return MCDisassembler::Fail; 4646 4647 if (load) { 4648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4649 return MCDisassembler::Fail; 4650 } 4651 4652 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4653 return MCDisassembler::Fail; 4654 4655 return S; 4656 } 4657 4658 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4659 uint64_t Address, 4660 const MCDisassembler *Decoder) { 4661 DecodeStatus S = MCDisassembler::Success; 4662 4663 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4664 unsigned imm = fieldFromInstruction(Val, 0, 12); 4665 4666 // Thumb stores cannot use PC as dest register. 4667 switch (Inst.getOpcode()) { 4668 case ARM::t2STRi12: 4669 case ARM::t2STRBi12: 4670 case ARM::t2STRHi12: 4671 if (Rn == 15) 4672 return MCDisassembler::Fail; 4673 break; 4674 default: 4675 break; 4676 } 4677 4678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4679 return MCDisassembler::Fail; 4680 Inst.addOperand(MCOperand::createImm(imm)); 4681 4682 return S; 4683 } 4684 4685 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4686 uint64_t Address, 4687 const MCDisassembler *Decoder) { 4688 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4689 4690 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4691 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4692 Inst.addOperand(MCOperand::createImm(imm)); 4693 4694 return MCDisassembler::Success; 4695 } 4696 4697 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4698 uint64_t Address, 4699 const MCDisassembler *Decoder) { 4700 DecodeStatus S = MCDisassembler::Success; 4701 4702 if (Inst.getOpcode() == ARM::tADDrSP) { 4703 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4704 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4705 4706 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4707 return MCDisassembler::Fail; 4708 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4709 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4710 return MCDisassembler::Fail; 4711 } else if (Inst.getOpcode() == ARM::tADDspr) { 4712 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4713 4714 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4715 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4717 return MCDisassembler::Fail; 4718 } 4719 4720 return S; 4721 } 4722 4723 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4724 uint64_t Address, 4725 const MCDisassembler *Decoder) { 4726 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4727 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4728 4729 Inst.addOperand(MCOperand::createImm(imod)); 4730 Inst.addOperand(MCOperand::createImm(flags)); 4731 4732 return MCDisassembler::Success; 4733 } 4734 4735 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4736 uint64_t Address, 4737 const MCDisassembler *Decoder) { 4738 DecodeStatus S = MCDisassembler::Success; 4739 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4740 unsigned add = fieldFromInstruction(Insn, 4, 1); 4741 4742 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4743 return MCDisassembler::Fail; 4744 Inst.addOperand(MCOperand::createImm(add)); 4745 4746 return S; 4747 } 4748 4749 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4750 uint64_t Address, 4751 const MCDisassembler *Decoder) { 4752 DecodeStatus S = MCDisassembler::Success; 4753 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4754 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4755 4756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4757 return MCDisassembler::Fail; 4758 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4759 return MCDisassembler::Fail; 4760 4761 return S; 4762 } 4763 4764 template <int shift> 4765 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4766 uint64_t Address, 4767 const MCDisassembler *Decoder) { 4768 DecodeStatus S = MCDisassembler::Success; 4769 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4770 int imm = fieldFromInstruction(Insn, 0, 7); 4771 4772 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4773 return MCDisassembler::Fail; 4774 4775 if(!fieldFromInstruction(Insn, 7, 1)) { 4776 if (imm == 0) 4777 imm = INT32_MIN; // indicate -0 4778 else 4779 imm *= -1; 4780 } 4781 if (imm != INT32_MIN) 4782 imm *= (1U << shift); 4783 Inst.addOperand(MCOperand::createImm(imm)); 4784 4785 return S; 4786 } 4787 4788 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4789 uint64_t Address, 4790 const MCDisassembler *Decoder) { 4791 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4792 // Note only one trailing zero not two. Also the J1 and J2 values are from 4793 // the encoded instruction. So here change to I1 and I2 values via: 4794 // I1 = NOT(J1 EOR S); 4795 // I2 = NOT(J2 EOR S); 4796 // and build the imm32 with two trailing zeros as documented: 4797 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4798 unsigned S = (Val >> 23) & 1; 4799 unsigned J1 = (Val >> 22) & 1; 4800 unsigned J2 = (Val >> 21) & 1; 4801 unsigned I1 = !(J1 ^ S); 4802 unsigned I2 = !(J2 ^ S); 4803 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4804 int imm32 = SignExtend32<25>(tmp << 1); 4805 4806 if (!tryAddingSymbolicOperand(Address, 4807 (Address & ~2u) + imm32 + 4, 4808 true, 4, Inst, Decoder)) 4809 Inst.addOperand(MCOperand::createImm(imm32)); 4810 return MCDisassembler::Success; 4811 } 4812 4813 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4814 uint64_t Address, 4815 const MCDisassembler *Decoder) { 4816 if (Val == 0xA || Val == 0xB) 4817 return MCDisassembler::Fail; 4818 4819 const FeatureBitset &featureBits = 4820 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4821 4822 if (!isValidCoprocessorNumber(Val, featureBits)) 4823 return MCDisassembler::Fail; 4824 4825 Inst.addOperand(MCOperand::createImm(Val)); 4826 return MCDisassembler::Success; 4827 } 4828 4829 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4830 uint64_t Address, 4831 const MCDisassembler *Decoder) { 4832 const FeatureBitset &FeatureBits = 4833 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4834 DecodeStatus S = MCDisassembler::Success; 4835 4836 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4837 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4838 4839 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4840 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4841 return MCDisassembler::Fail; 4842 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4843 return MCDisassembler::Fail; 4844 return S; 4845 } 4846 4847 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4848 uint64_t Address, 4849 const MCDisassembler *Decoder) { 4850 DecodeStatus S = MCDisassembler::Success; 4851 4852 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4853 if (pred == 0xE || pred == 0xF) { 4854 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4855 switch (opc) { 4856 default: 4857 return MCDisassembler::Fail; 4858 case 0xf3bf8f4: 4859 Inst.setOpcode(ARM::t2DSB); 4860 break; 4861 case 0xf3bf8f5: 4862 Inst.setOpcode(ARM::t2DMB); 4863 break; 4864 case 0xf3bf8f6: 4865 Inst.setOpcode(ARM::t2ISB); 4866 break; 4867 } 4868 4869 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4870 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4871 } 4872 4873 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4874 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4875 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4876 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4877 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4878 4879 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4880 return MCDisassembler::Fail; 4881 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4882 return MCDisassembler::Fail; 4883 4884 return S; 4885 } 4886 4887 // Decode a shifted immediate operand. These basically consist 4888 // of an 8-bit value, and a 4-bit directive that specifies either 4889 // a splat operation or a rotation. 4890 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4891 const MCDisassembler *Decoder) { 4892 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4893 if (ctrl == 0) { 4894 unsigned byte = fieldFromInstruction(Val, 8, 2); 4895 unsigned imm = fieldFromInstruction(Val, 0, 8); 4896 switch (byte) { 4897 case 0: 4898 Inst.addOperand(MCOperand::createImm(imm)); 4899 break; 4900 case 1: 4901 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4902 break; 4903 case 2: 4904 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4905 break; 4906 case 3: 4907 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4908 (imm << 8) | imm)); 4909 break; 4910 } 4911 } else { 4912 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4913 unsigned rot = fieldFromInstruction(Val, 7, 5); 4914 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4915 Inst.addOperand(MCOperand::createImm(imm)); 4916 } 4917 4918 return MCDisassembler::Success; 4919 } 4920 4921 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4922 uint64_t Address, 4923 const MCDisassembler *Decoder) { 4924 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4925 true, 2, Inst, Decoder)) 4926 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4927 return MCDisassembler::Success; 4928 } 4929 4930 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4931 uint64_t Address, 4932 const MCDisassembler *Decoder) { 4933 // Val is passed in as S:J1:J2:imm10:imm11 4934 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4935 // the encoded instruction. So here change to I1 and I2 values via: 4936 // I1 = NOT(J1 EOR S); 4937 // I2 = NOT(J2 EOR S); 4938 // and build the imm32 with one trailing zero as documented: 4939 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4940 unsigned S = (Val >> 23) & 1; 4941 unsigned J1 = (Val >> 22) & 1; 4942 unsigned J2 = (Val >> 21) & 1; 4943 unsigned I1 = !(J1 ^ S); 4944 unsigned I2 = !(J2 ^ S); 4945 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4946 int imm32 = SignExtend32<25>(tmp << 1); 4947 4948 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4949 true, 4, Inst, Decoder)) 4950 Inst.addOperand(MCOperand::createImm(imm32)); 4951 return MCDisassembler::Success; 4952 } 4953 4954 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4955 uint64_t Address, 4956 const MCDisassembler *Decoder) { 4957 if (Val & ~0xf) 4958 return MCDisassembler::Fail; 4959 4960 Inst.addOperand(MCOperand::createImm(Val)); 4961 return MCDisassembler::Success; 4962 } 4963 4964 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4965 uint64_t Address, 4966 const MCDisassembler *Decoder) { 4967 if (Val & ~0xf) 4968 return MCDisassembler::Fail; 4969 4970 Inst.addOperand(MCOperand::createImm(Val)); 4971 return MCDisassembler::Success; 4972 } 4973 4974 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4975 const MCDisassembler *Decoder) { 4976 DecodeStatus S = MCDisassembler::Success; 4977 const FeatureBitset &FeatureBits = 4978 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4979 4980 if (FeatureBits[ARM::FeatureMClass]) { 4981 unsigned ValLow = Val & 0xff; 4982 4983 // Validate the SYSm value first. 4984 switch (ValLow) { 4985 case 0: // apsr 4986 case 1: // iapsr 4987 case 2: // eapsr 4988 case 3: // xpsr 4989 case 5: // ipsr 4990 case 6: // epsr 4991 case 7: // iepsr 4992 case 8: // msp 4993 case 9: // psp 4994 case 16: // primask 4995 case 20: // control 4996 break; 4997 case 17: // basepri 4998 case 18: // basepri_max 4999 case 19: // faultmask 5000 if (!(FeatureBits[ARM::HasV7Ops])) 5001 // Values basepri, basepri_max and faultmask are only valid for v7m. 5002 return MCDisassembler::Fail; 5003 break; 5004 case 0x8a: // msplim_ns 5005 case 0x8b: // psplim_ns 5006 case 0x91: // basepri_ns 5007 case 0x93: // faultmask_ns 5008 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5009 return MCDisassembler::Fail; 5010 LLVM_FALLTHROUGH; 5011 case 10: // msplim 5012 case 11: // psplim 5013 case 0x88: // msp_ns 5014 case 0x89: // psp_ns 5015 case 0x90: // primask_ns 5016 case 0x94: // control_ns 5017 case 0x98: // sp_ns 5018 if (!(FeatureBits[ARM::Feature8MSecExt])) 5019 return MCDisassembler::Fail; 5020 break; 5021 case 0x20: // pac_key_p_0 5022 case 0x21: // pac_key_p_1 5023 case 0x22: // pac_key_p_2 5024 case 0x23: // pac_key_p_3 5025 case 0x24: // pac_key_u_0 5026 case 0x25: // pac_key_u_1 5027 case 0x26: // pac_key_u_2 5028 case 0x27: // pac_key_u_3 5029 case 0xa0: // pac_key_p_0_ns 5030 case 0xa1: // pac_key_p_1_ns 5031 case 0xa2: // pac_key_p_2_ns 5032 case 0xa3: // pac_key_p_3_ns 5033 case 0xa4: // pac_key_u_0_ns 5034 case 0xa5: // pac_key_u_1_ns 5035 case 0xa6: // pac_key_u_2_ns 5036 case 0xa7: // pac_key_u_3_ns 5037 if (!(FeatureBits[ARM::FeaturePACBTI])) 5038 return MCDisassembler::Fail; 5039 break; 5040 default: 5041 // Architecturally defined as unpredictable 5042 S = MCDisassembler::SoftFail; 5043 break; 5044 } 5045 5046 if (Inst.getOpcode() == ARM::t2MSR_M) { 5047 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5048 if (!(FeatureBits[ARM::HasV7Ops])) { 5049 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5050 // unpredictable. 5051 if (Mask != 2) 5052 S = MCDisassembler::SoftFail; 5053 } 5054 else { 5055 // The ARMv7-M architecture stores an additional 2-bit mask value in 5056 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5057 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5058 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5059 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5060 // only if the processor includes the DSP extension. 5061 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5062 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5063 S = MCDisassembler::SoftFail; 5064 } 5065 } 5066 } else { 5067 // A/R class 5068 if (Val == 0) 5069 return MCDisassembler::Fail; 5070 } 5071 Inst.addOperand(MCOperand::createImm(Val)); 5072 return S; 5073 } 5074 5075 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5076 uint64_t Address, 5077 const MCDisassembler *Decoder) { 5078 unsigned R = fieldFromInstruction(Val, 5, 1); 5079 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5080 5081 // The table of encodings for these banked registers comes from B9.2.3 of the 5082 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5083 // neater. So by fiat, these values are UNPREDICTABLE: 5084 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5085 return MCDisassembler::Fail; 5086 5087 Inst.addOperand(MCOperand::createImm(Val)); 5088 return MCDisassembler::Success; 5089 } 5090 5091 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5092 uint64_t Address, 5093 const MCDisassembler *Decoder) { 5094 DecodeStatus S = MCDisassembler::Success; 5095 5096 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5097 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5098 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5099 5100 if (Rn == 0xF) 5101 S = MCDisassembler::SoftFail; 5102 5103 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5104 return MCDisassembler::Fail; 5105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5106 return MCDisassembler::Fail; 5107 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5108 return MCDisassembler::Fail; 5109 5110 return S; 5111 } 5112 5113 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5114 uint64_t Address, 5115 const MCDisassembler *Decoder) { 5116 DecodeStatus S = MCDisassembler::Success; 5117 5118 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5119 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5120 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5121 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5122 5123 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5124 return MCDisassembler::Fail; 5125 5126 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5127 S = MCDisassembler::SoftFail; 5128 5129 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5130 return MCDisassembler::Fail; 5131 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5132 return MCDisassembler::Fail; 5133 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5134 return MCDisassembler::Fail; 5135 5136 return S; 5137 } 5138 5139 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5140 uint64_t Address, 5141 const MCDisassembler *Decoder) { 5142 DecodeStatus S = MCDisassembler::Success; 5143 5144 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5145 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5146 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5147 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5148 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5149 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5150 5151 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5152 5153 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5154 return MCDisassembler::Fail; 5155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5156 return MCDisassembler::Fail; 5157 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5158 return MCDisassembler::Fail; 5159 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5160 return MCDisassembler::Fail; 5161 5162 return S; 5163 } 5164 5165 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5166 uint64_t Address, 5167 const MCDisassembler *Decoder) { 5168 DecodeStatus S = MCDisassembler::Success; 5169 5170 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5171 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5172 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5173 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5174 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5175 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5176 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5177 5178 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5179 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5180 5181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5182 return MCDisassembler::Fail; 5183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5184 return MCDisassembler::Fail; 5185 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5186 return MCDisassembler::Fail; 5187 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5188 return MCDisassembler::Fail; 5189 5190 return S; 5191 } 5192 5193 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5194 uint64_t Address, 5195 const MCDisassembler *Decoder) { 5196 DecodeStatus S = MCDisassembler::Success; 5197 5198 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5199 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5200 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5201 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5202 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5203 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5204 5205 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5206 5207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5208 return MCDisassembler::Fail; 5209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5210 return MCDisassembler::Fail; 5211 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5212 return MCDisassembler::Fail; 5213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5214 return MCDisassembler::Fail; 5215 5216 return S; 5217 } 5218 5219 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5220 uint64_t Address, 5221 const MCDisassembler *Decoder) { 5222 DecodeStatus S = MCDisassembler::Success; 5223 5224 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5225 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5226 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5227 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5228 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5229 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5230 5231 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5232 5233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5234 return MCDisassembler::Fail; 5235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5236 return MCDisassembler::Fail; 5237 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5238 return MCDisassembler::Fail; 5239 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5240 return MCDisassembler::Fail; 5241 5242 return S; 5243 } 5244 5245 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5246 const MCDisassembler *Decoder) { 5247 DecodeStatus S = MCDisassembler::Success; 5248 5249 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5250 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5251 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5252 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5253 unsigned size = fieldFromInstruction(Insn, 10, 2); 5254 5255 unsigned align = 0; 5256 unsigned index = 0; 5257 switch (size) { 5258 default: 5259 return MCDisassembler::Fail; 5260 case 0: 5261 if (fieldFromInstruction(Insn, 4, 1)) 5262 return MCDisassembler::Fail; // UNDEFINED 5263 index = fieldFromInstruction(Insn, 5, 3); 5264 break; 5265 case 1: 5266 if (fieldFromInstruction(Insn, 5, 1)) 5267 return MCDisassembler::Fail; // UNDEFINED 5268 index = fieldFromInstruction(Insn, 6, 2); 5269 if (fieldFromInstruction(Insn, 4, 1)) 5270 align = 2; 5271 break; 5272 case 2: 5273 if (fieldFromInstruction(Insn, 6, 1)) 5274 return MCDisassembler::Fail; // UNDEFINED 5275 index = fieldFromInstruction(Insn, 7, 1); 5276 5277 switch (fieldFromInstruction(Insn, 4, 2)) { 5278 case 0 : 5279 align = 0; break; 5280 case 3: 5281 align = 4; break; 5282 default: 5283 return MCDisassembler::Fail; 5284 } 5285 break; 5286 } 5287 5288 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5289 return MCDisassembler::Fail; 5290 if (Rm != 0xF) { // Writeback 5291 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5292 return MCDisassembler::Fail; 5293 } 5294 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5295 return MCDisassembler::Fail; 5296 Inst.addOperand(MCOperand::createImm(align)); 5297 if (Rm != 0xF) { 5298 if (Rm != 0xD) { 5299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5300 return MCDisassembler::Fail; 5301 } else 5302 Inst.addOperand(MCOperand::createReg(0)); 5303 } 5304 5305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5306 return MCDisassembler::Fail; 5307 Inst.addOperand(MCOperand::createImm(index)); 5308 5309 return S; 5310 } 5311 5312 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5313 const MCDisassembler *Decoder) { 5314 DecodeStatus S = MCDisassembler::Success; 5315 5316 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5317 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5318 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5319 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5320 unsigned size = fieldFromInstruction(Insn, 10, 2); 5321 5322 unsigned align = 0; 5323 unsigned index = 0; 5324 switch (size) { 5325 default: 5326 return MCDisassembler::Fail; 5327 case 0: 5328 if (fieldFromInstruction(Insn, 4, 1)) 5329 return MCDisassembler::Fail; // UNDEFINED 5330 index = fieldFromInstruction(Insn, 5, 3); 5331 break; 5332 case 1: 5333 if (fieldFromInstruction(Insn, 5, 1)) 5334 return MCDisassembler::Fail; // UNDEFINED 5335 index = fieldFromInstruction(Insn, 6, 2); 5336 if (fieldFromInstruction(Insn, 4, 1)) 5337 align = 2; 5338 break; 5339 case 2: 5340 if (fieldFromInstruction(Insn, 6, 1)) 5341 return MCDisassembler::Fail; // UNDEFINED 5342 index = fieldFromInstruction(Insn, 7, 1); 5343 5344 switch (fieldFromInstruction(Insn, 4, 2)) { 5345 case 0: 5346 align = 0; break; 5347 case 3: 5348 align = 4; break; 5349 default: 5350 return MCDisassembler::Fail; 5351 } 5352 break; 5353 } 5354 5355 if (Rm != 0xF) { // Writeback 5356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5357 return MCDisassembler::Fail; 5358 } 5359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5360 return MCDisassembler::Fail; 5361 Inst.addOperand(MCOperand::createImm(align)); 5362 if (Rm != 0xF) { 5363 if (Rm != 0xD) { 5364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5365 return MCDisassembler::Fail; 5366 } else 5367 Inst.addOperand(MCOperand::createReg(0)); 5368 } 5369 5370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5371 return MCDisassembler::Fail; 5372 Inst.addOperand(MCOperand::createImm(index)); 5373 5374 return S; 5375 } 5376 5377 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5378 const MCDisassembler *Decoder) { 5379 DecodeStatus S = MCDisassembler::Success; 5380 5381 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5382 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5383 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5385 unsigned size = fieldFromInstruction(Insn, 10, 2); 5386 5387 unsigned align = 0; 5388 unsigned index = 0; 5389 unsigned inc = 1; 5390 switch (size) { 5391 default: 5392 return MCDisassembler::Fail; 5393 case 0: 5394 index = fieldFromInstruction(Insn, 5, 3); 5395 if (fieldFromInstruction(Insn, 4, 1)) 5396 align = 2; 5397 break; 5398 case 1: 5399 index = fieldFromInstruction(Insn, 6, 2); 5400 if (fieldFromInstruction(Insn, 4, 1)) 5401 align = 4; 5402 if (fieldFromInstruction(Insn, 5, 1)) 5403 inc = 2; 5404 break; 5405 case 2: 5406 if (fieldFromInstruction(Insn, 5, 1)) 5407 return MCDisassembler::Fail; // UNDEFINED 5408 index = fieldFromInstruction(Insn, 7, 1); 5409 if (fieldFromInstruction(Insn, 4, 1) != 0) 5410 align = 8; 5411 if (fieldFromInstruction(Insn, 6, 1)) 5412 inc = 2; 5413 break; 5414 } 5415 5416 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5417 return MCDisassembler::Fail; 5418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5419 return MCDisassembler::Fail; 5420 if (Rm != 0xF) { // Writeback 5421 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5422 return MCDisassembler::Fail; 5423 } 5424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 Inst.addOperand(MCOperand::createImm(align)); 5427 if (Rm != 0xF) { 5428 if (Rm != 0xD) { 5429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5430 return MCDisassembler::Fail; 5431 } else 5432 Inst.addOperand(MCOperand::createReg(0)); 5433 } 5434 5435 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5436 return MCDisassembler::Fail; 5437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5438 return MCDisassembler::Fail; 5439 Inst.addOperand(MCOperand::createImm(index)); 5440 5441 return S; 5442 } 5443 5444 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5445 const MCDisassembler *Decoder) { 5446 DecodeStatus S = MCDisassembler::Success; 5447 5448 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5449 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5450 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5452 unsigned size = fieldFromInstruction(Insn, 10, 2); 5453 5454 unsigned align = 0; 5455 unsigned index = 0; 5456 unsigned inc = 1; 5457 switch (size) { 5458 default: 5459 return MCDisassembler::Fail; 5460 case 0: 5461 index = fieldFromInstruction(Insn, 5, 3); 5462 if (fieldFromInstruction(Insn, 4, 1)) 5463 align = 2; 5464 break; 5465 case 1: 5466 index = fieldFromInstruction(Insn, 6, 2); 5467 if (fieldFromInstruction(Insn, 4, 1)) 5468 align = 4; 5469 if (fieldFromInstruction(Insn, 5, 1)) 5470 inc = 2; 5471 break; 5472 case 2: 5473 if (fieldFromInstruction(Insn, 5, 1)) 5474 return MCDisassembler::Fail; // UNDEFINED 5475 index = fieldFromInstruction(Insn, 7, 1); 5476 if (fieldFromInstruction(Insn, 4, 1) != 0) 5477 align = 8; 5478 if (fieldFromInstruction(Insn, 6, 1)) 5479 inc = 2; 5480 break; 5481 } 5482 5483 if (Rm != 0xF) { // Writeback 5484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5485 return MCDisassembler::Fail; 5486 } 5487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 Inst.addOperand(MCOperand::createImm(align)); 5490 if (Rm != 0xF) { 5491 if (Rm != 0xD) { 5492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5493 return MCDisassembler::Fail; 5494 } else 5495 Inst.addOperand(MCOperand::createReg(0)); 5496 } 5497 5498 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5499 return MCDisassembler::Fail; 5500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5501 return MCDisassembler::Fail; 5502 Inst.addOperand(MCOperand::createImm(index)); 5503 5504 return S; 5505 } 5506 5507 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5508 const MCDisassembler *Decoder) { 5509 DecodeStatus S = MCDisassembler::Success; 5510 5511 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5512 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5513 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5514 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5515 unsigned size = fieldFromInstruction(Insn, 10, 2); 5516 5517 unsigned align = 0; 5518 unsigned index = 0; 5519 unsigned inc = 1; 5520 switch (size) { 5521 default: 5522 return MCDisassembler::Fail; 5523 case 0: 5524 if (fieldFromInstruction(Insn, 4, 1)) 5525 return MCDisassembler::Fail; // UNDEFINED 5526 index = fieldFromInstruction(Insn, 5, 3); 5527 break; 5528 case 1: 5529 if (fieldFromInstruction(Insn, 4, 1)) 5530 return MCDisassembler::Fail; // UNDEFINED 5531 index = fieldFromInstruction(Insn, 6, 2); 5532 if (fieldFromInstruction(Insn, 5, 1)) 5533 inc = 2; 5534 break; 5535 case 2: 5536 if (fieldFromInstruction(Insn, 4, 2)) 5537 return MCDisassembler::Fail; // UNDEFINED 5538 index = fieldFromInstruction(Insn, 7, 1); 5539 if (fieldFromInstruction(Insn, 6, 1)) 5540 inc = 2; 5541 break; 5542 } 5543 5544 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5545 return MCDisassembler::Fail; 5546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5547 return MCDisassembler::Fail; 5548 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5549 return MCDisassembler::Fail; 5550 5551 if (Rm != 0xF) { // Writeback 5552 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5553 return MCDisassembler::Fail; 5554 } 5555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5556 return MCDisassembler::Fail; 5557 Inst.addOperand(MCOperand::createImm(align)); 5558 if (Rm != 0xF) { 5559 if (Rm != 0xD) { 5560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5561 return MCDisassembler::Fail; 5562 } else 5563 Inst.addOperand(MCOperand::createReg(0)); 5564 } 5565 5566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5567 return MCDisassembler::Fail; 5568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5569 return MCDisassembler::Fail; 5570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 Inst.addOperand(MCOperand::createImm(index)); 5573 5574 return S; 5575 } 5576 5577 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5578 const MCDisassembler *Decoder) { 5579 DecodeStatus S = MCDisassembler::Success; 5580 5581 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5582 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5583 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5584 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5585 unsigned size = fieldFromInstruction(Insn, 10, 2); 5586 5587 unsigned align = 0; 5588 unsigned index = 0; 5589 unsigned inc = 1; 5590 switch (size) { 5591 default: 5592 return MCDisassembler::Fail; 5593 case 0: 5594 if (fieldFromInstruction(Insn, 4, 1)) 5595 return MCDisassembler::Fail; // UNDEFINED 5596 index = fieldFromInstruction(Insn, 5, 3); 5597 break; 5598 case 1: 5599 if (fieldFromInstruction(Insn, 4, 1)) 5600 return MCDisassembler::Fail; // UNDEFINED 5601 index = fieldFromInstruction(Insn, 6, 2); 5602 if (fieldFromInstruction(Insn, 5, 1)) 5603 inc = 2; 5604 break; 5605 case 2: 5606 if (fieldFromInstruction(Insn, 4, 2)) 5607 return MCDisassembler::Fail; // UNDEFINED 5608 index = fieldFromInstruction(Insn, 7, 1); 5609 if (fieldFromInstruction(Insn, 6, 1)) 5610 inc = 2; 5611 break; 5612 } 5613 5614 if (Rm != 0xF) { // Writeback 5615 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5616 return MCDisassembler::Fail; 5617 } 5618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5619 return MCDisassembler::Fail; 5620 Inst.addOperand(MCOperand::createImm(align)); 5621 if (Rm != 0xF) { 5622 if (Rm != 0xD) { 5623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5624 return MCDisassembler::Fail; 5625 } else 5626 Inst.addOperand(MCOperand::createReg(0)); 5627 } 5628 5629 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5630 return MCDisassembler::Fail; 5631 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5632 return MCDisassembler::Fail; 5633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5634 return MCDisassembler::Fail; 5635 Inst.addOperand(MCOperand::createImm(index)); 5636 5637 return S; 5638 } 5639 5640 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5641 const MCDisassembler *Decoder) { 5642 DecodeStatus S = MCDisassembler::Success; 5643 5644 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5645 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5646 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5647 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5648 unsigned size = fieldFromInstruction(Insn, 10, 2); 5649 5650 unsigned align = 0; 5651 unsigned index = 0; 5652 unsigned inc = 1; 5653 switch (size) { 5654 default: 5655 return MCDisassembler::Fail; 5656 case 0: 5657 if (fieldFromInstruction(Insn, 4, 1)) 5658 align = 4; 5659 index = fieldFromInstruction(Insn, 5, 3); 5660 break; 5661 case 1: 5662 if (fieldFromInstruction(Insn, 4, 1)) 5663 align = 8; 5664 index = fieldFromInstruction(Insn, 6, 2); 5665 if (fieldFromInstruction(Insn, 5, 1)) 5666 inc = 2; 5667 break; 5668 case 2: 5669 switch (fieldFromInstruction(Insn, 4, 2)) { 5670 case 0: 5671 align = 0; break; 5672 case 3: 5673 return MCDisassembler::Fail; 5674 default: 5675 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5676 } 5677 5678 index = fieldFromInstruction(Insn, 7, 1); 5679 if (fieldFromInstruction(Insn, 6, 1)) 5680 inc = 2; 5681 break; 5682 } 5683 5684 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5685 return MCDisassembler::Fail; 5686 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5687 return MCDisassembler::Fail; 5688 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5689 return MCDisassembler::Fail; 5690 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5691 return MCDisassembler::Fail; 5692 5693 if (Rm != 0xF) { // Writeback 5694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5695 return MCDisassembler::Fail; 5696 } 5697 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5698 return MCDisassembler::Fail; 5699 Inst.addOperand(MCOperand::createImm(align)); 5700 if (Rm != 0xF) { 5701 if (Rm != 0xD) { 5702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5703 return MCDisassembler::Fail; 5704 } else 5705 Inst.addOperand(MCOperand::createReg(0)); 5706 } 5707 5708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5709 return MCDisassembler::Fail; 5710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5711 return MCDisassembler::Fail; 5712 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5713 return MCDisassembler::Fail; 5714 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5715 return MCDisassembler::Fail; 5716 Inst.addOperand(MCOperand::createImm(index)); 5717 5718 return S; 5719 } 5720 5721 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5722 const MCDisassembler *Decoder) { 5723 DecodeStatus S = MCDisassembler::Success; 5724 5725 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5726 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5727 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5728 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5729 unsigned size = fieldFromInstruction(Insn, 10, 2); 5730 5731 unsigned align = 0; 5732 unsigned index = 0; 5733 unsigned inc = 1; 5734 switch (size) { 5735 default: 5736 return MCDisassembler::Fail; 5737 case 0: 5738 if (fieldFromInstruction(Insn, 4, 1)) 5739 align = 4; 5740 index = fieldFromInstruction(Insn, 5, 3); 5741 break; 5742 case 1: 5743 if (fieldFromInstruction(Insn, 4, 1)) 5744 align = 8; 5745 index = fieldFromInstruction(Insn, 6, 2); 5746 if (fieldFromInstruction(Insn, 5, 1)) 5747 inc = 2; 5748 break; 5749 case 2: 5750 switch (fieldFromInstruction(Insn, 4, 2)) { 5751 case 0: 5752 align = 0; break; 5753 case 3: 5754 return MCDisassembler::Fail; 5755 default: 5756 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5757 } 5758 5759 index = fieldFromInstruction(Insn, 7, 1); 5760 if (fieldFromInstruction(Insn, 6, 1)) 5761 inc = 2; 5762 break; 5763 } 5764 5765 if (Rm != 0xF) { // Writeback 5766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5767 return MCDisassembler::Fail; 5768 } 5769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5770 return MCDisassembler::Fail; 5771 Inst.addOperand(MCOperand::createImm(align)); 5772 if (Rm != 0xF) { 5773 if (Rm != 0xD) { 5774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5775 return MCDisassembler::Fail; 5776 } else 5777 Inst.addOperand(MCOperand::createReg(0)); 5778 } 5779 5780 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5781 return MCDisassembler::Fail; 5782 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5783 return MCDisassembler::Fail; 5784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5785 return MCDisassembler::Fail; 5786 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5787 return MCDisassembler::Fail; 5788 Inst.addOperand(MCOperand::createImm(index)); 5789 5790 return S; 5791 } 5792 5793 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5794 const MCDisassembler *Decoder) { 5795 DecodeStatus S = MCDisassembler::Success; 5796 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5797 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5798 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5799 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5800 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5801 5802 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5803 S = MCDisassembler::SoftFail; 5804 5805 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5806 return MCDisassembler::Fail; 5807 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5808 return MCDisassembler::Fail; 5809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5810 return MCDisassembler::Fail; 5811 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5812 return MCDisassembler::Fail; 5813 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5814 return MCDisassembler::Fail; 5815 5816 return S; 5817 } 5818 5819 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5820 const MCDisassembler *Decoder) { 5821 DecodeStatus S = MCDisassembler::Success; 5822 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5823 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5824 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5825 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5826 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5827 5828 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5829 S = MCDisassembler::SoftFail; 5830 5831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5832 return MCDisassembler::Fail; 5833 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5834 return MCDisassembler::Fail; 5835 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5836 return MCDisassembler::Fail; 5837 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5838 return MCDisassembler::Fail; 5839 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5840 return MCDisassembler::Fail; 5841 5842 return S; 5843 } 5844 5845 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5846 const MCDisassembler *Decoder) { 5847 DecodeStatus S = MCDisassembler::Success; 5848 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5849 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5850 5851 if (pred == 0xF) { 5852 pred = 0xE; 5853 S = MCDisassembler::SoftFail; 5854 } 5855 5856 if (mask == 0x0) 5857 return MCDisassembler::Fail; 5858 5859 // IT masks are encoded as a sequence of replacement low-order bits 5860 // for the condition code. So if the low bit of the starting 5861 // condition code is 1, then we have to flip all the bits above the 5862 // terminating bit (which is the lowest 1 bit). 5863 if (pred & 1) { 5864 unsigned LowBit = mask & -mask; 5865 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5866 mask ^= BitsAboveLowBit; 5867 } 5868 5869 Inst.addOperand(MCOperand::createImm(pred)); 5870 Inst.addOperand(MCOperand::createImm(mask)); 5871 return S; 5872 } 5873 5874 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5875 uint64_t Address, 5876 const MCDisassembler *Decoder) { 5877 DecodeStatus S = MCDisassembler::Success; 5878 5879 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5880 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5881 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5882 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5883 unsigned W = fieldFromInstruction(Insn, 21, 1); 5884 unsigned U = fieldFromInstruction(Insn, 23, 1); 5885 unsigned P = fieldFromInstruction(Insn, 24, 1); 5886 bool writeback = (W == 1) | (P == 0); 5887 5888 addr |= (U << 8) | (Rn << 9); 5889 5890 if (writeback && (Rn == Rt || Rn == Rt2)) 5891 Check(S, MCDisassembler::SoftFail); 5892 if (Rt == Rt2) 5893 Check(S, MCDisassembler::SoftFail); 5894 5895 // Rt 5896 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5897 return MCDisassembler::Fail; 5898 // Rt2 5899 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5900 return MCDisassembler::Fail; 5901 // Writeback operand 5902 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5903 return MCDisassembler::Fail; 5904 // addr 5905 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5906 return MCDisassembler::Fail; 5907 5908 return S; 5909 } 5910 5911 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5912 uint64_t Address, 5913 const MCDisassembler *Decoder) { 5914 DecodeStatus S = MCDisassembler::Success; 5915 5916 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5917 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5918 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5919 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5920 unsigned W = fieldFromInstruction(Insn, 21, 1); 5921 unsigned U = fieldFromInstruction(Insn, 23, 1); 5922 unsigned P = fieldFromInstruction(Insn, 24, 1); 5923 bool writeback = (W == 1) | (P == 0); 5924 5925 addr |= (U << 8) | (Rn << 9); 5926 5927 if (writeback && (Rn == Rt || Rn == Rt2)) 5928 Check(S, MCDisassembler::SoftFail); 5929 5930 // Writeback operand 5931 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5932 return MCDisassembler::Fail; 5933 // Rt 5934 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5935 return MCDisassembler::Fail; 5936 // Rt2 5937 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5938 return MCDisassembler::Fail; 5939 // addr 5940 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5941 return MCDisassembler::Fail; 5942 5943 return S; 5944 } 5945 5946 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5947 const MCDisassembler *Decoder) { 5948 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5949 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5950 if (sign1 != sign2) return MCDisassembler::Fail; 5951 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5952 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5953 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5954 5955 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5956 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5957 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5958 // If sign, then it is decreasing the address. 5959 if (sign1) { 5960 // Following ARMv7 Architecture Manual, when the offset 5961 // is zero, it is decoded as a subw, not as a adr.w 5962 if (!Val) { 5963 Inst.setOpcode(ARM::t2SUBri12); 5964 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5965 } else 5966 Val = -Val; 5967 } 5968 Inst.addOperand(MCOperand::createImm(Val)); 5969 return S; 5970 } 5971 5972 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5973 uint64_t Address, 5974 const MCDisassembler *Decoder) { 5975 DecodeStatus S = MCDisassembler::Success; 5976 5977 // Shift of "asr #32" is not allowed in Thumb2 mode. 5978 if (Val == 0x20) S = MCDisassembler::Fail; 5979 Inst.addOperand(MCOperand::createImm(Val)); 5980 return S; 5981 } 5982 5983 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5984 const MCDisassembler *Decoder) { 5985 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5986 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5987 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5988 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5989 5990 if (pred == 0xF) 5991 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5992 5993 DecodeStatus S = MCDisassembler::Success; 5994 5995 if (Rt == Rn || Rn == Rt2) 5996 S = MCDisassembler::SoftFail; 5997 5998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5999 return MCDisassembler::Fail; 6000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6001 return MCDisassembler::Fail; 6002 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6003 return MCDisassembler::Fail; 6004 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6005 return MCDisassembler::Fail; 6006 6007 return S; 6008 } 6009 6010 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6011 const MCDisassembler *Decoder) { 6012 const FeatureBitset &featureBits = 6013 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6014 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6015 6016 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6017 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6018 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6019 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6020 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6021 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6022 unsigned op = fieldFromInstruction(Insn, 5, 1); 6023 6024 DecodeStatus S = MCDisassembler::Success; 6025 6026 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6027 if (!(imm & 0x38)) { 6028 if (cmode == 0xF) { 6029 if (op == 1) return MCDisassembler::Fail; 6030 Inst.setOpcode(ARM::VMOVv2f32); 6031 } 6032 if (hasFullFP16) { 6033 if (cmode == 0xE) { 6034 if (op == 1) { 6035 Inst.setOpcode(ARM::VMOVv1i64); 6036 } else { 6037 Inst.setOpcode(ARM::VMOVv8i8); 6038 } 6039 } 6040 if (cmode == 0xD) { 6041 if (op == 1) { 6042 Inst.setOpcode(ARM::VMVNv2i32); 6043 } else { 6044 Inst.setOpcode(ARM::VMOVv2i32); 6045 } 6046 } 6047 if (cmode == 0xC) { 6048 if (op == 1) { 6049 Inst.setOpcode(ARM::VMVNv2i32); 6050 } else { 6051 Inst.setOpcode(ARM::VMOVv2i32); 6052 } 6053 } 6054 } 6055 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6056 } 6057 6058 if (!(imm & 0x20)) return MCDisassembler::Fail; 6059 6060 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6061 return MCDisassembler::Fail; 6062 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6063 return MCDisassembler::Fail; 6064 Inst.addOperand(MCOperand::createImm(64 - imm)); 6065 6066 return S; 6067 } 6068 6069 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6070 const MCDisassembler *Decoder) { 6071 const FeatureBitset &featureBits = 6072 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6073 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6074 6075 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6076 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6077 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6078 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6079 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6080 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6081 unsigned op = fieldFromInstruction(Insn, 5, 1); 6082 6083 DecodeStatus S = MCDisassembler::Success; 6084 6085 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6086 if (!(imm & 0x38)) { 6087 if (cmode == 0xF) { 6088 if (op == 1) return MCDisassembler::Fail; 6089 Inst.setOpcode(ARM::VMOVv4f32); 6090 } 6091 if (hasFullFP16) { 6092 if (cmode == 0xE) { 6093 if (op == 1) { 6094 Inst.setOpcode(ARM::VMOVv2i64); 6095 } else { 6096 Inst.setOpcode(ARM::VMOVv16i8); 6097 } 6098 } 6099 if (cmode == 0xD) { 6100 if (op == 1) { 6101 Inst.setOpcode(ARM::VMVNv4i32); 6102 } else { 6103 Inst.setOpcode(ARM::VMOVv4i32); 6104 } 6105 } 6106 if (cmode == 0xC) { 6107 if (op == 1) { 6108 Inst.setOpcode(ARM::VMVNv4i32); 6109 } else { 6110 Inst.setOpcode(ARM::VMOVv4i32); 6111 } 6112 } 6113 } 6114 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6115 } 6116 6117 if (!(imm & 0x20)) return MCDisassembler::Fail; 6118 6119 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6120 return MCDisassembler::Fail; 6121 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6122 return MCDisassembler::Fail; 6123 Inst.addOperand(MCOperand::createImm(64 - imm)); 6124 6125 return S; 6126 } 6127 6128 static DecodeStatus 6129 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6130 uint64_t Address, 6131 const MCDisassembler *Decoder) { 6132 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6133 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6134 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6135 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6136 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6137 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6138 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6139 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6140 6141 DecodeStatus S = MCDisassembler::Success; 6142 6143 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6144 6145 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6146 return MCDisassembler::Fail; 6147 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6148 return MCDisassembler::Fail; 6149 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6150 return MCDisassembler::Fail; 6151 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6152 return MCDisassembler::Fail; 6153 // The lane index does not have any bits in the encoding, because it can only 6154 // be 0. 6155 Inst.addOperand(MCOperand::createImm(0)); 6156 Inst.addOperand(MCOperand::createImm(rotate)); 6157 6158 return S; 6159 } 6160 6161 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6162 const MCDisassembler *Decoder) { 6163 DecodeStatus S = MCDisassembler::Success; 6164 6165 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6166 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6167 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6168 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6169 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6170 6171 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6172 S = MCDisassembler::SoftFail; 6173 6174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6175 return MCDisassembler::Fail; 6176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6177 return MCDisassembler::Fail; 6178 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6179 return MCDisassembler::Fail; 6180 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6181 return MCDisassembler::Fail; 6182 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6183 return MCDisassembler::Fail; 6184 6185 return S; 6186 } 6187 6188 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6189 uint64_t Address, 6190 const MCDisassembler *Decoder) { 6191 DecodeStatus S = MCDisassembler::Success; 6192 6193 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6194 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6195 unsigned cop = fieldFromInstruction(Val, 8, 4); 6196 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6197 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6198 6199 if ((cop & ~0x1) == 0xa) 6200 return MCDisassembler::Fail; 6201 6202 if (Rt == Rt2) 6203 S = MCDisassembler::SoftFail; 6204 6205 // We have to check if the instruction is MRRC2 6206 // or MCRR2 when constructing the operands for 6207 // Inst. Reason is because MRRC2 stores to two 6208 // registers so it's tablegen desc has has two 6209 // outputs whereas MCRR doesn't store to any 6210 // registers so all of it's operands are listed 6211 // as inputs, therefore the operand order for 6212 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6213 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6214 6215 if (Inst.getOpcode() == ARM::MRRC2) { 6216 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6217 return MCDisassembler::Fail; 6218 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6219 return MCDisassembler::Fail; 6220 } 6221 Inst.addOperand(MCOperand::createImm(cop)); 6222 Inst.addOperand(MCOperand::createImm(opc1)); 6223 if (Inst.getOpcode() == ARM::MCRR2) { 6224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6225 return MCDisassembler::Fail; 6226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6227 return MCDisassembler::Fail; 6228 } 6229 Inst.addOperand(MCOperand::createImm(CRm)); 6230 6231 return S; 6232 } 6233 6234 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6235 uint64_t Address, 6236 const MCDisassembler *Decoder) { 6237 const FeatureBitset &featureBits = 6238 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6239 DecodeStatus S = MCDisassembler::Success; 6240 6241 // Add explicit operand for the destination sysreg, for cases where 6242 // we have to model it for code generation purposes. 6243 switch (Inst.getOpcode()) { 6244 case ARM::VMSR_FPSCR_NZCVQC: 6245 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6246 break; 6247 case ARM::VMSR_P0: 6248 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6249 break; 6250 } 6251 6252 if (Inst.getOpcode() != ARM::FMSTAT) { 6253 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6254 6255 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6256 if (Rt == 13 || Rt == 15) 6257 S = MCDisassembler::SoftFail; 6258 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6259 } else 6260 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6261 } 6262 6263 // Add explicit operand for the source sysreg, similarly to above. 6264 switch (Inst.getOpcode()) { 6265 case ARM::VMRS_FPSCR_NZCVQC: 6266 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6267 break; 6268 case ARM::VMRS_P0: 6269 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6270 break; 6271 } 6272 6273 if (featureBits[ARM::ModeThumb]) { 6274 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6275 Inst.addOperand(MCOperand::createReg(0)); 6276 } else { 6277 unsigned pred = fieldFromInstruction(Val, 28, 4); 6278 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6279 return MCDisassembler::Fail; 6280 } 6281 6282 return S; 6283 } 6284 6285 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6286 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6287 uint64_t Address, 6288 const MCDisassembler *Decoder) { 6289 DecodeStatus S = MCDisassembler::Success; 6290 if (Val == 0 && !zeroPermitted) 6291 S = MCDisassembler::Fail; 6292 6293 uint64_t DecVal; 6294 if (isSigned) 6295 DecVal = SignExtend32<size + 1>(Val << 1); 6296 else 6297 DecVal = (Val << 1); 6298 6299 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6300 Decoder)) 6301 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6302 return S; 6303 } 6304 6305 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6306 uint64_t Address, 6307 const MCDisassembler *Decoder) { 6308 6309 uint64_t LocImm = Inst.getOperand(0).getImm(); 6310 Val = LocImm + (2 << Val); 6311 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6312 Decoder)) 6313 Inst.addOperand(MCOperand::createImm(Val)); 6314 return MCDisassembler::Success; 6315 } 6316 6317 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6318 uint64_t Address, 6319 const MCDisassembler *Decoder) { 6320 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6321 return MCDisassembler::Fail; 6322 Inst.addOperand(MCOperand::createImm(Val)); 6323 return MCDisassembler::Success; 6324 } 6325 6326 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6327 const MCDisassembler *Decoder) { 6328 DecodeStatus S = MCDisassembler::Success; 6329 6330 if (Inst.getOpcode() == ARM::MVE_LCTP) 6331 return S; 6332 6333 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6334 fieldFromInstruction(Insn, 1, 10) << 1; 6335 switch (Inst.getOpcode()) { 6336 case ARM::t2LEUpdate: 6337 case ARM::MVE_LETP: 6338 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6339 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6340 LLVM_FALLTHROUGH; 6341 case ARM::t2LE: 6342 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6343 Inst, Imm, Address, Decoder))) 6344 return MCDisassembler::Fail; 6345 break; 6346 case ARM::t2WLS: 6347 case ARM::MVE_WLSTP_8: 6348 case ARM::MVE_WLSTP_16: 6349 case ARM::MVE_WLSTP_32: 6350 case ARM::MVE_WLSTP_64: 6351 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6352 if (!Check(S, 6353 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6354 Address, Decoder)) || 6355 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6356 Inst, Imm, Address, Decoder))) 6357 return MCDisassembler::Fail; 6358 break; 6359 case ARM::t2DLS: 6360 case ARM::MVE_DLSTP_8: 6361 case ARM::MVE_DLSTP_16: 6362 case ARM::MVE_DLSTP_32: 6363 case ARM::MVE_DLSTP_64: 6364 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6365 if (Rn == 0xF) { 6366 // Enforce all the rest of the instruction bits in LCTP, which 6367 // won't have been reliably checked based on LCTP's own tablegen 6368 // record, because we came to this decode by a roundabout route. 6369 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6370 if ((Insn & ~SBZMask) != CanonicalLCTP) 6371 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6372 if (Insn != CanonicalLCTP) 6373 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6374 6375 Inst.setOpcode(ARM::MVE_LCTP); 6376 } else { 6377 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6378 if (!Check(S, DecoderGPRRegisterClass(Inst, 6379 fieldFromInstruction(Insn, 16, 4), 6380 Address, Decoder))) 6381 return MCDisassembler::Fail; 6382 } 6383 break; 6384 } 6385 return S; 6386 } 6387 6388 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6389 uint64_t Address, 6390 const MCDisassembler *Decoder) { 6391 DecodeStatus S = MCDisassembler::Success; 6392 6393 if (Val == 0) 6394 Val = 32; 6395 6396 Inst.addOperand(MCOperand::createImm(Val)); 6397 6398 return S; 6399 } 6400 6401 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6402 uint64_t Address, 6403 const MCDisassembler *Decoder) { 6404 if ((RegNo) + 1 > 11) 6405 return MCDisassembler::Fail; 6406 6407 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6408 Inst.addOperand(MCOperand::createReg(Register)); 6409 return MCDisassembler::Success; 6410 } 6411 6412 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6413 uint64_t Address, 6414 const MCDisassembler *Decoder) { 6415 if ((RegNo) > 14) 6416 return MCDisassembler::Fail; 6417 6418 unsigned Register = GPRDecoderTable[(RegNo)]; 6419 Inst.addOperand(MCOperand::createReg(Register)); 6420 return MCDisassembler::Success; 6421 } 6422 6423 static DecodeStatus 6424 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6425 uint64_t Address, 6426 const MCDisassembler *Decoder) { 6427 if (RegNo == 15) { 6428 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6429 return MCDisassembler::Success; 6430 } 6431 6432 unsigned Register = GPRDecoderTable[RegNo]; 6433 Inst.addOperand(MCOperand::createReg(Register)); 6434 6435 if (RegNo == 13) 6436 return MCDisassembler::SoftFail; 6437 6438 return MCDisassembler::Success; 6439 } 6440 6441 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6442 const MCDisassembler *Decoder) { 6443 DecodeStatus S = MCDisassembler::Success; 6444 6445 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6446 Inst.addOperand(MCOperand::createReg(0)); 6447 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6448 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6449 (fieldFromInstruction(Insn, 12, 4) << 8) | 6450 (fieldFromInstruction(Insn, 22, 1) << 12); 6451 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6452 return MCDisassembler::Fail; 6453 } 6454 } else { 6455 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6456 (fieldFromInstruction(Insn, 22, 1) << 8) | 6457 (fieldFromInstruction(Insn, 12, 4) << 9); 6458 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6459 return MCDisassembler::Fail; 6460 } 6461 } 6462 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6463 6464 return S; 6465 } 6466 6467 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6468 uint64_t Address, 6469 const MCDisassembler *Decoder) { 6470 if (RegNo > 7) 6471 return MCDisassembler::Fail; 6472 6473 unsigned Register = QPRDecoderTable[RegNo]; 6474 Inst.addOperand(MCOperand::createReg(Register)); 6475 return MCDisassembler::Success; 6476 } 6477 6478 static const uint16_t QQPRDecoderTable[] = { 6479 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6480 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6481 }; 6482 6483 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6484 uint64_t Address, 6485 const MCDisassembler *Decoder) { 6486 if (RegNo > 6) 6487 return MCDisassembler::Fail; 6488 6489 unsigned Register = QQPRDecoderTable[RegNo]; 6490 Inst.addOperand(MCOperand::createReg(Register)); 6491 return MCDisassembler::Success; 6492 } 6493 6494 static const uint16_t QQQQPRDecoderTable[] = { 6495 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6496 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6497 }; 6498 6499 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6500 uint64_t Address, 6501 const MCDisassembler *Decoder) { 6502 if (RegNo > 4) 6503 return MCDisassembler::Fail; 6504 6505 unsigned Register = QQQQPRDecoderTable[RegNo]; 6506 Inst.addOperand(MCOperand::createReg(Register)); 6507 return MCDisassembler::Success; 6508 } 6509 6510 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6511 uint64_t Address, 6512 const MCDisassembler *Decoder) { 6513 DecodeStatus S = MCDisassembler::Success; 6514 6515 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6516 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6517 // 't' as 0 and finish with a 1. 6518 unsigned Imm = 0; 6519 // We always start with a 't'. 6520 unsigned CurBit = 0; 6521 for (int i = 3; i >= 0; --i) { 6522 // If the bit we are looking at is not the same as last one, invert the 6523 // CurBit, if it is the same leave it as is. 6524 CurBit ^= (Val >> i) & 1U; 6525 6526 // Encode the CurBit at the right place in the immediate. 6527 Imm |= (CurBit << i); 6528 6529 // If we are done, finish the encoding with a 1. 6530 if ((Val & ~(~0U << i)) == 0) { 6531 Imm |= 1U << i; 6532 break; 6533 } 6534 } 6535 6536 Inst.addOperand(MCOperand::createImm(Imm)); 6537 6538 return S; 6539 } 6540 6541 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6542 uint64_t Address, 6543 const MCDisassembler *Decoder) { 6544 // The vpred_r operand type includes an MQPR register field derived 6545 // from the encoding. But we don't actually want to add an operand 6546 // to the MCInst at this stage, because AddThumbPredicate will do it 6547 // later, and will infer the register number from the TIED_TO 6548 // constraint. So this is a deliberately empty decoder method that 6549 // will inhibit the auto-generated disassembly code from adding an 6550 // operand at all. 6551 return MCDisassembler::Success; 6552 } 6553 6554 static DecodeStatus 6555 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6556 const MCDisassembler *Decoder) { 6557 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6558 return MCDisassembler::Success; 6559 } 6560 6561 static DecodeStatus 6562 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6563 const MCDisassembler *Decoder) { 6564 unsigned Code; 6565 switch (Val & 0x3) { 6566 case 0: 6567 Code = ARMCC::GE; 6568 break; 6569 case 1: 6570 Code = ARMCC::LT; 6571 break; 6572 case 2: 6573 Code = ARMCC::GT; 6574 break; 6575 case 3: 6576 Code = ARMCC::LE; 6577 break; 6578 } 6579 Inst.addOperand(MCOperand::createImm(Code)); 6580 return MCDisassembler::Success; 6581 } 6582 6583 static DecodeStatus 6584 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6585 const MCDisassembler *Decoder) { 6586 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6587 return MCDisassembler::Success; 6588 } 6589 6590 static DecodeStatus 6591 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6592 const MCDisassembler *Decoder) { 6593 unsigned Code; 6594 switch (Val) { 6595 default: 6596 return MCDisassembler::Fail; 6597 case 0: 6598 Code = ARMCC::EQ; 6599 break; 6600 case 1: 6601 Code = ARMCC::NE; 6602 break; 6603 case 4: 6604 Code = ARMCC::GE; 6605 break; 6606 case 5: 6607 Code = ARMCC::LT; 6608 break; 6609 case 6: 6610 Code = ARMCC::GT; 6611 break; 6612 case 7: 6613 Code = ARMCC::LE; 6614 break; 6615 } 6616 6617 Inst.addOperand(MCOperand::createImm(Code)); 6618 return MCDisassembler::Success; 6619 } 6620 6621 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6622 uint64_t Address, 6623 const MCDisassembler *Decoder) { 6624 DecodeStatus S = MCDisassembler::Success; 6625 6626 unsigned DecodedVal = 64 - Val; 6627 6628 switch (Inst.getOpcode()) { 6629 case ARM::MVE_VCVTf16s16_fix: 6630 case ARM::MVE_VCVTs16f16_fix: 6631 case ARM::MVE_VCVTf16u16_fix: 6632 case ARM::MVE_VCVTu16f16_fix: 6633 if (DecodedVal > 16) 6634 return MCDisassembler::Fail; 6635 break; 6636 case ARM::MVE_VCVTf32s32_fix: 6637 case ARM::MVE_VCVTs32f32_fix: 6638 case ARM::MVE_VCVTf32u32_fix: 6639 case ARM::MVE_VCVTu32f32_fix: 6640 if (DecodedVal > 32) 6641 return MCDisassembler::Fail; 6642 break; 6643 } 6644 6645 Inst.addOperand(MCOperand::createImm(64 - Val)); 6646 6647 return S; 6648 } 6649 6650 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6651 switch (Opcode) { 6652 case ARM::VSTR_P0_off: 6653 case ARM::VSTR_P0_pre: 6654 case ARM::VSTR_P0_post: 6655 case ARM::VLDR_P0_off: 6656 case ARM::VLDR_P0_pre: 6657 case ARM::VLDR_P0_post: 6658 return ARM::P0; 6659 default: 6660 return 0; 6661 } 6662 } 6663 6664 template <bool Writeback> 6665 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6666 uint64_t Address, 6667 const MCDisassembler *Decoder) { 6668 switch (Inst.getOpcode()) { 6669 case ARM::VSTR_FPSCR_pre: 6670 case ARM::VSTR_FPSCR_NZCVQC_pre: 6671 case ARM::VLDR_FPSCR_pre: 6672 case ARM::VLDR_FPSCR_NZCVQC_pre: 6673 case ARM::VSTR_FPSCR_off: 6674 case ARM::VSTR_FPSCR_NZCVQC_off: 6675 case ARM::VLDR_FPSCR_off: 6676 case ARM::VLDR_FPSCR_NZCVQC_off: 6677 case ARM::VSTR_FPSCR_post: 6678 case ARM::VSTR_FPSCR_NZCVQC_post: 6679 case ARM::VLDR_FPSCR_post: 6680 case ARM::VLDR_FPSCR_NZCVQC_post: 6681 const FeatureBitset &featureBits = 6682 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6683 6684 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6685 return MCDisassembler::Fail; 6686 } 6687 6688 DecodeStatus S = MCDisassembler::Success; 6689 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6690 Inst.addOperand(MCOperand::createReg(Sysreg)); 6691 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6692 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6693 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6694 6695 if (Writeback) { 6696 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6697 return MCDisassembler::Fail; 6698 } 6699 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6700 return MCDisassembler::Fail; 6701 6702 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6703 Inst.addOperand(MCOperand::createReg(0)); 6704 6705 return S; 6706 } 6707 6708 static inline DecodeStatus 6709 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6710 const MCDisassembler *Decoder, unsigned Rn, 6711 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6712 DecodeStatus S = MCDisassembler::Success; 6713 6714 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6715 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6716 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6717 6718 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6719 return MCDisassembler::Fail; 6720 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6721 return MCDisassembler::Fail; 6722 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6723 return MCDisassembler::Fail; 6724 6725 return S; 6726 } 6727 6728 template <int shift> 6729 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6730 uint64_t Address, 6731 const MCDisassembler *Decoder) { 6732 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6733 fieldFromInstruction(Val, 16, 3), 6734 DecodetGPRRegisterClass, 6735 DecodeTAddrModeImm7<shift>); 6736 } 6737 6738 template <int shift> 6739 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6740 uint64_t Address, 6741 const MCDisassembler *Decoder) { 6742 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6743 fieldFromInstruction(Val, 16, 4), 6744 DecoderGPRRegisterClass, 6745 DecodeT2AddrModeImm7<shift,1>); 6746 } 6747 6748 template <int shift> 6749 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6750 uint64_t Address, 6751 const MCDisassembler *Decoder) { 6752 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6753 fieldFromInstruction(Val, 17, 3), 6754 DecodeMQPRRegisterClass, 6755 DecodeMveAddrModeQ<shift>); 6756 } 6757 6758 template <unsigned MinLog, unsigned MaxLog> 6759 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6760 uint64_t Address, 6761 const MCDisassembler *Decoder) { 6762 DecodeStatus S = MCDisassembler::Success; 6763 6764 if (Val < MinLog || Val > MaxLog) 6765 return MCDisassembler::Fail; 6766 6767 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6768 return S; 6769 } 6770 6771 template <unsigned start> 6772 static DecodeStatus 6773 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6774 const MCDisassembler *Decoder) { 6775 DecodeStatus S = MCDisassembler::Success; 6776 6777 Inst.addOperand(MCOperand::createImm(start + Val)); 6778 6779 return S; 6780 } 6781 6782 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6783 uint64_t Address, 6784 const MCDisassembler *Decoder) { 6785 DecodeStatus S = MCDisassembler::Success; 6786 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6787 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6788 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6789 fieldFromInstruction(Insn, 13, 3)); 6790 unsigned index = fieldFromInstruction(Insn, 4, 1); 6791 6792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6793 return MCDisassembler::Fail; 6794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6795 return MCDisassembler::Fail; 6796 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6797 return MCDisassembler::Fail; 6798 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6799 return MCDisassembler::Fail; 6800 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6801 return MCDisassembler::Fail; 6802 6803 return S; 6804 } 6805 6806 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6807 uint64_t Address, 6808 const MCDisassembler *Decoder) { 6809 DecodeStatus S = MCDisassembler::Success; 6810 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6811 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6812 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6813 fieldFromInstruction(Insn, 13, 3)); 6814 unsigned index = fieldFromInstruction(Insn, 4, 1); 6815 6816 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6817 return MCDisassembler::Fail; 6818 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6819 return MCDisassembler::Fail; 6820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6821 return MCDisassembler::Fail; 6822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6823 return MCDisassembler::Fail; 6824 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6825 return MCDisassembler::Fail; 6826 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6827 return MCDisassembler::Fail; 6828 6829 return S; 6830 } 6831 6832 static DecodeStatus 6833 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6834 const MCDisassembler *Decoder) { 6835 DecodeStatus S = MCDisassembler::Success; 6836 6837 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6838 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6839 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6840 6841 if (RdaHi == 14) { 6842 // This value of RdaHi (really indicating pc, because RdaHi has to 6843 // be an odd-numbered register, so the low bit will be set by the 6844 // decode function below) indicates that we must decode as SQRSHR 6845 // or UQRSHL, which both have a single Rda register field with all 6846 // four bits. 6847 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6848 6849 switch (Inst.getOpcode()) { 6850 case ARM::MVE_ASRLr: 6851 case ARM::MVE_SQRSHRL: 6852 Inst.setOpcode(ARM::MVE_SQRSHR); 6853 break; 6854 case ARM::MVE_LSLLr: 6855 case ARM::MVE_UQRSHLL: 6856 Inst.setOpcode(ARM::MVE_UQRSHL); 6857 break; 6858 default: 6859 llvm_unreachable("Unexpected starting opcode!"); 6860 } 6861 6862 // Rda as output parameter 6863 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6864 return MCDisassembler::Fail; 6865 6866 // Rda again as input parameter 6867 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6868 return MCDisassembler::Fail; 6869 6870 // Rm, the amount to shift by 6871 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6872 return MCDisassembler::Fail; 6873 6874 if (fieldFromInstruction (Insn, 6, 3) != 4) 6875 return MCDisassembler::SoftFail; 6876 6877 if (Rda == Rm) 6878 return MCDisassembler::SoftFail; 6879 6880 return S; 6881 } 6882 6883 // Otherwise, we decode as whichever opcode our caller has already 6884 // put into Inst. Those all look the same: 6885 6886 // RdaLo,RdaHi as output parameters 6887 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6888 return MCDisassembler::Fail; 6889 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6890 return MCDisassembler::Fail; 6891 6892 // RdaLo,RdaHi again as input parameters 6893 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6894 return MCDisassembler::Fail; 6895 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6896 return MCDisassembler::Fail; 6897 6898 // Rm, the amount to shift by 6899 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6900 return MCDisassembler::Fail; 6901 6902 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6903 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6904 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6905 // Saturate, the bit position for saturation 6906 Inst.addOperand(MCOperand::createImm(Saturate)); 6907 } 6908 6909 return S; 6910 } 6911 6912 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6913 uint64_t Address, 6914 const MCDisassembler *Decoder) { 6915 DecodeStatus S = MCDisassembler::Success; 6916 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6917 fieldFromInstruction(Insn, 13, 3)); 6918 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6919 fieldFromInstruction(Insn, 1, 3)); 6920 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6921 6922 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6923 return MCDisassembler::Fail; 6924 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6925 return MCDisassembler::Fail; 6926 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6927 return MCDisassembler::Fail; 6928 6929 return S; 6930 } 6931 6932 template <bool scalar, OperandDecoder predicate_decoder> 6933 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6934 const MCDisassembler *Decoder) { 6935 DecodeStatus S = MCDisassembler::Success; 6936 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6937 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6938 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6939 return MCDisassembler::Fail; 6940 6941 unsigned fc; 6942 6943 if (scalar) { 6944 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6945 fieldFromInstruction(Insn, 7, 1) | 6946 fieldFromInstruction(Insn, 5, 1) << 1; 6947 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6948 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6949 return MCDisassembler::Fail; 6950 } else { 6951 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6952 fieldFromInstruction(Insn, 7, 1) | 6953 fieldFromInstruction(Insn, 0, 1) << 1; 6954 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6955 fieldFromInstruction(Insn, 1, 3); 6956 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6957 return MCDisassembler::Fail; 6958 } 6959 6960 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6961 return MCDisassembler::Fail; 6962 6963 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6964 Inst.addOperand(MCOperand::createReg(0)); 6965 Inst.addOperand(MCOperand::createImm(0)); 6966 6967 return S; 6968 } 6969 6970 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6971 const MCDisassembler *Decoder) { 6972 DecodeStatus S = MCDisassembler::Success; 6973 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6974 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6975 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6976 return MCDisassembler::Fail; 6977 return S; 6978 } 6979 6980 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6981 uint64_t Address, 6982 const MCDisassembler *Decoder) { 6983 DecodeStatus S = MCDisassembler::Success; 6984 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6985 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6986 return S; 6987 } 6988 6989 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6990 uint64_t Address, 6991 const MCDisassembler *Decoder) { 6992 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6993 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6994 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6995 fieldFromInstruction(Insn, 12, 3) << 8 | 6996 fieldFromInstruction(Insn, 0, 8); 6997 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6998 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6999 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7000 unsigned S = fieldFromInstruction(Insn, 20, 1); 7001 if (sign1 != sign2) 7002 return MCDisassembler::Fail; 7003 7004 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7005 DecodeStatus DS = MCDisassembler::Success; 7006 if ((!Check(DS, 7007 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7008 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7009 return MCDisassembler::Fail; 7010 if (TypeT3) { 7011 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7012 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7013 } else { 7014 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7015 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7016 return MCDisassembler::Fail; 7017 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7018 return MCDisassembler::Fail; 7019 } 7020 7021 return DS; 7022 } 7023