xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (revision c7a063741720ef81d4caa4613242579d12f1d605)
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
10 #include "MCTargetDesc/ARMAddressingModes.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "TargetInfo/ARMTargetInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
17 #include "llvm/MC/MCFixedLenDisassembler.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/SubtargetFeature.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37 
38 namespace {
39 
40   // Handles the condition code status of instructions in IT blocks
41   class ITStatus
42   {
43     public:
44       // Returns the condition code for instruction in IT block
45       unsigned getITCC() {
46         unsigned CC = ARMCC::AL;
47         if (instrInITBlock())
48           CC = ITStates.back();
49         return CC;
50       }
51 
52       // Advances the IT block state to the next T or E
53       void advanceITState() {
54         ITStates.pop_back();
55       }
56 
57       // Returns true if the current instruction is in an IT block
58       bool instrInITBlock() {
59         return !ITStates.empty();
60       }
61 
62       // Returns true if current instruction is the last instruction in an IT block
63       bool instrLastInITBlock() {
64         return ITStates.size() == 1;
65       }
66 
67       // Called when decoding an IT instruction. Sets the IT state for
68       // the following instructions that for the IT block. Firstcond
69       // corresponds to the field in the IT instruction encoding; Mask
70       // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71       void setITState(char Firstcond, char Mask) {
72         // (3 - the number of trailing zeros) is the number of then / else.
73         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75         assert(NumTZ <= 3 && "Invalid IT mask!");
76         // push condition codes onto the stack the correct order for the pops
77         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78           unsigned Else = (Mask >> Pos) & 1;
79           ITStates.push_back(CCBits ^ Else);
80         }
81         ITStates.push_back(CCBits);
82       }
83 
84     private:
85       std::vector<unsigned char> ITStates;
86   };
87 
88   class VPTStatus
89   {
90     public:
91       unsigned getVPTPred() {
92         unsigned Pred = ARMVCC::None;
93         if (instrInVPTBlock())
94           Pred = VPTStates.back();
95         return Pred;
96       }
97 
98       void advanceVPTState() {
99         VPTStates.pop_back();
100       }
101 
102       bool instrInVPTBlock() {
103         return !VPTStates.empty();
104       }
105 
106       bool instrLastInVPTBlock() {
107         return VPTStates.size() == 1;
108       }
109 
110       void setVPTState(char Mask) {
111         // (3 - the number of trailing zeros) is the number of then / else.
112         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113         assert(NumTZ <= 3 && "Invalid VPT mask!");
114         // push predicates onto the stack the correct order for the pops
115         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116           bool T = ((Mask >> Pos) & 1) == 0;
117           if (T)
118             VPTStates.push_back(ARMVCC::Then);
119           else
120             VPTStates.push_back(ARMVCC::Else);
121         }
122         VPTStates.push_back(ARMVCC::Then);
123       }
124 
125     private:
126       SmallVector<unsigned char, 4> VPTStates;
127   };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133     MCDisassembler(STI, Ctx) {
134   }
135 
136   ~ARMDisassembler() override = default;
137 
138   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
139                               ArrayRef<uint8_t> Bytes, uint64_t Address,
140                               raw_ostream &CStream) const override;
141 
142 private:
143   DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144                                  ArrayRef<uint8_t> Bytes, uint64_t Address,
145                                  raw_ostream &CStream) const;
146 
147   DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148                                    ArrayRef<uint8_t> Bytes, uint64_t Address,
149                                    raw_ostream &CStream) const;
150 
151   mutable ITStatus ITBlock;
152   mutable VPTStatus VPTBlock;
153 
154   DecodeStatus AddThumbPredicate(MCInst&) const;
155   void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156 };
157 
158 } // end anonymous namespace
159 
160 static bool Check(DecodeStatus &Out, DecodeStatus In) {
161   switch (In) {
162     case MCDisassembler::Success:
163       // Out stays the same.
164       return true;
165     case MCDisassembler::SoftFail:
166       Out = In;
167       return true;
168     case MCDisassembler::Fail:
169       Out = In;
170       return false;
171   }
172   llvm_unreachable("Invalid DecodeStatus!");
173 }
174 
175 // Forward declare these because the autogenerated code will reference them.
176 // Definitions are further down.
177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
178                                    uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
180                                    uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
182                                    uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
184                                    uint64_t Address, const void *Decoder);
185 static DecodeStatus
186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
187                                         uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
189                                                uint64_t Address,
190                                                const void *Decoder);
191 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
192                                                uint64_t Address,
193                                                const void *Decoder);
194 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
195                                                unsigned RegNo, uint64_t Address,
196                                                const void *Decoder);
197 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
198                                                unsigned RegNo, uint64_t Address,
199                                                const void *Decoder);
200 static DecodeStatus DecodeGPRwithZRnospRegisterClass(
201     MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
203                                    uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
205                                    uint64_t Address, const void *Decoder);
206 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
207                                    uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
209                                    uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
211                                    uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
213                                              uint64_t Address,
214                                              const void *Decoder);
215 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
216                                    uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
218                                    uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
220                                    uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
222                                    uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
224                                    uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
226                                                 unsigned RegNo,
227                                                 uint64_t Address,
228                                                 const void *Decoder);
229 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
230                                    uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
232                                    uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
234                                              uint64_t Address,
235                                              const void *Decoder);
236 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
237                                                uint64_t Address,
238                                                const void *Decoder);
239 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
240                                    uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
242                                unsigned RegNo, uint64_t Address,
243                                const void *Decoder);
244 
245 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
246                                uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
248                                uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
250                                uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
252                                uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
254                                uint64_t Address, const void *Decoder);
255 
256 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
257                                uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
259                                uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
261                                                   unsigned Insn,
262                                                   uint64_t Address,
263                                                   const void *Decoder);
264 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
265                                uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
267                                uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
269                                uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
271                                uint64_t Address, const void *Decoder);
272 
273 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
274                                                   unsigned Insn,
275                                                   uint64_t Adddress,
276                                                   const void *Decoder);
277 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
278                                uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
280                                uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
282                                uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
284                                uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
286                                uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
288                                uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
290                                uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
292                                uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
294                                                  uint64_t Address,
295                                                  const void *Decoder);
296 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
297                                uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
299                                uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
301                                uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
303                                uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
305                                uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
307                                uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
309                                uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
311                                uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
313                                uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
315                                uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
317                                uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
319                                uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
321                                uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
323                                uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
325                                uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
327                                uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
329                                uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
331                                uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
333                                uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
335                                uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
337                                uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
339                                uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
341                                uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
343                                uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
345                                uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
347                                uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
349                                uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
351                                uint64_t Address, const void *Decoder);
352 template<int shift>
353 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
354                                uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
356                                uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
358                                uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
360                                uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
362                                uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
364                                uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
366                                uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
368                                uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
370                                uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
372                                uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
374                                uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
376                                uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
378                                uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
380                                uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
382                                uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
384                                uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
386                                uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
388                                uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
390                                uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
392                                uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
394                                uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
396                                uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
398                                uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
400                                 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
402                                 uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
404                                          uint64_t Address, const void *Decoder);
405 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
406                                                        unsigned Val,
407                                                        uint64_t Address,
408                                                        const void *Decoder);
409 
410 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
411                                uint64_t Address, const void *Decoder);
412 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
413                                uint64_t Address, const void *Decoder);
414 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
415                                uint64_t Address, const void *Decoder);
416 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
417                                uint64_t Address, const void *Decoder);
418 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
419                                uint64_t Address, const void *Decoder);
420 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
421                                uint64_t Address, const void *Decoder);
422 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
423                                uint64_t Address, const void *Decoder);
424 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
425                                uint64_t Address, const void *Decoder);
426 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
427                                uint64_t Address, const void *Decoder);
428 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
429                                uint64_t Address, const void *Decoder);
430 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
431                                uint64_t Address, const void* Decoder);
432 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
433                                uint64_t Address, const void* Decoder);
434 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
435                                uint64_t Address, const void* Decoder);
436 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
437                                uint64_t Address, const void* Decoder);
438 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
439                                uint64_t Address, const void *Decoder);
440 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
441                                uint64_t Address, const void *Decoder);
442 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
443                                uint64_t Address, const void *Decoder);
444 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
445                                            uint64_t Address,
446                                            const void *Decoder);
447 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
448                                uint64_t Address, const void *Decoder);
449 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
450                                uint64_t Address, const void *Decoder);
451 template<int shift>
452 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
453                                uint64_t Address, const void *Decoder);
454 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
455                                uint64_t Address, const void *Decoder);
456 template<int shift>
457 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
458                                uint64_t Address, const void *Decoder);
459 template<int shift, int WriteBack>
460 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
461                                uint64_t Address, const void *Decoder);
462 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
463                                uint64_t Address, const void *Decoder);
464 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
465                                 uint64_t Address, const void *Decoder);
466 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
467                                 uint64_t Address, const void *Decoder);
468 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
469                                 uint64_t Address, const void *Decoder);
470 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
471                                 uint64_t Address, const void *Decoder);
472 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
473                                 uint64_t Address, const void *Decoder);
474 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
475                                 uint64_t Address, const void *Decoder);
476 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
477                                 uint64_t Address, const void *Decoder);
478 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
479                                 uint64_t Address, const void *Decoder);
480 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
481                                 uint64_t Address, const void *Decoder);
482 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
483                                 uint64_t Address, const void *Decoder);
484 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
485                                 uint64_t Address, const void *Decoder);
486 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
487                                uint64_t Address, const void *Decoder);
488 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
489                                uint64_t Address, const void *Decoder);
490 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
491                                 uint64_t Address, const void *Decoder);
492 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
493                                 uint64_t Address, const void *Decoder);
494 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
495                                 uint64_t Address, const void *Decoder);
496 
497 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
498                                 uint64_t Address, const void *Decoder);
499 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
500                                             uint64_t Address, const void *Decoder);
501 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
502                                          uint64_t Address, const void *Decoder);
503 
504 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
505 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
506                                          uint64_t Address, const void *Decoder);
507 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
508                                                uint64_t Address,
509                                                const void *Decoder);
510 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
511                                           uint64_t Address,
512                                           const void *Decoder);
513 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
514                                  const void *Decoder);
515 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
516                                            uint64_t Address,
517                                            const void *Decoder);
518 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
519                                   const void *Decoder);
520 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
521                                          uint64_t Address, const void *Decoder);
522 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
523                                         uint64_t Address, const void *Decoder);
524 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
525                                                      uint64_t Address,
526                                                      const void *Decoder);
527 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
528                                                      uint64_t Address,
529                                                      const void *Decoder);
530 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
531                                                      uint64_t Address,
532                                                      const void *Decoder);
533 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
534                                                        unsigned Val,
535                                                        uint64_t Address,
536                                                        const void *Decoder);
537 template<bool Writeback>
538 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
539                                           uint64_t Address,
540                                           const void *Decoder);
541 template<int shift>
542 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
543                                         uint64_t Address, const void *Decoder);
544 template<int shift>
545 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
546                                         uint64_t Address, const void *Decoder);
547 template<int shift>
548 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
549                                         uint64_t Address, const void *Decoder);
550 template<unsigned MinLog, unsigned MaxLog>
551 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
552                                           uint64_t Address,
553                                           const void *Decoder);
554 template<unsigned start>
555 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
556                                                     uint64_t Address,
557                                                     const void *Decoder);
558 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
559                                          uint64_t Address,
560                                          const void *Decoder);
561 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
562                                          uint64_t Address,
563                                          const void *Decoder);
564 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
565                                       uint64_t Address, const void *Decoder);
566 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
567                                     uint64_t Address, const void *Decoder);
568 template<bool scalar, OperandDecoder predicate_decoder>
569 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
570                                   uint64_t Address, const void *Decoder);
571 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
572                                   uint64_t Address, const void *Decoder);
573 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
574                                    uint64_t Address, const void *Decoder);
575 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
576                                                   uint64_t Address,
577                                                   const void *Decoder);
578 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
579                                         uint64_t Address, const void *Decoder);
580 
581 #include "ARMGenDisassemblerTables.inc"
582 
583 static MCDisassembler *createARMDisassembler(const Target &T,
584                                              const MCSubtargetInfo &STI,
585                                              MCContext &Ctx) {
586   return new ARMDisassembler(STI, Ctx);
587 }
588 
589 // Post-decoding checks
590 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
591                                             uint64_t Address, raw_ostream &CS,
592                                             uint32_t Insn,
593                                             DecodeStatus Result) {
594   switch (MI.getOpcode()) {
595     case ARM::HVC: {
596       // HVC is undefined if condition = 0xf otherwise upredictable
597       // if condition != 0xe
598       uint32_t Cond = (Insn >> 28) & 0xF;
599       if (Cond == 0xF)
600         return MCDisassembler::Fail;
601       if (Cond != 0xE)
602         return MCDisassembler::SoftFail;
603       return Result;
604     }
605     case ARM::t2ADDri:
606     case ARM::t2ADDri12:
607     case ARM::t2ADDrr:
608     case ARM::t2ADDrs:
609     case ARM::t2SUBri:
610     case ARM::t2SUBri12:
611     case ARM::t2SUBrr:
612     case ARM::t2SUBrs:
613       if (MI.getOperand(0).getReg() == ARM::SP &&
614           MI.getOperand(1).getReg() != ARM::SP)
615         return MCDisassembler::SoftFail;
616       return Result;
617     default: return Result;
618   }
619 }
620 
621 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
622                                              ArrayRef<uint8_t> Bytes,
623                                              uint64_t Address,
624                                              raw_ostream &CS) const {
625   if (STI.getFeatureBits()[ARM::ModeThumb])
626     return getThumbInstruction(MI, Size, Bytes, Address, CS);
627   return getARMInstruction(MI, Size, Bytes, Address, CS);
628 }
629 
630 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
631                                                 ArrayRef<uint8_t> Bytes,
632                                                 uint64_t Address,
633                                                 raw_ostream &CS) const {
634   CommentStream = &CS;
635 
636   assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
637          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
638          "mode!");
639 
640   // We want to read exactly 4 bytes of data.
641   if (Bytes.size() < 4) {
642     Size = 0;
643     return MCDisassembler::Fail;
644   }
645 
646   // Encoded as a small-endian 32-bit word in the stream.
647   uint32_t Insn =
648       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
649 
650   // Calling the auto-generated decoder function.
651   DecodeStatus Result =
652       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
653   if (Result != MCDisassembler::Fail) {
654     Size = 4;
655     return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
656   }
657 
658   struct DecodeTable {
659     const uint8_t *P;
660     bool DecodePred;
661   };
662 
663   const DecodeTable Tables[] = {
664       {DecoderTableVFP32, false},      {DecoderTableVFPV832, false},
665       {DecoderTableNEONData32, true},  {DecoderTableNEONLoadStore32, true},
666       {DecoderTableNEONDup32, true},   {DecoderTablev8NEON32, false},
667       {DecoderTablev8Crypto32, false},
668   };
669 
670   for (auto Table : Tables) {
671     Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
672     if (Result != MCDisassembler::Fail) {
673       Size = 4;
674       // Add a fake predicate operand, because we share these instruction
675       // definitions with Thumb2 where these instructions are predicable.
676       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
677         return MCDisassembler::Fail;
678       return Result;
679     }
680   }
681 
682   Result =
683       decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
684   if (Result != MCDisassembler::Fail) {
685     Size = 4;
686     return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
687   }
688 
689   Size = 4;
690   return MCDisassembler::Fail;
691 }
692 
693 namespace llvm {
694 
695 extern const MCInstrDesc ARMInsts[];
696 
697 } // end namespace llvm
698 
699 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
700 /// immediate Value in the MCInst.  The immediate Value has had any PC
701 /// adjustment made by the caller.  If the instruction is a branch instruction
702 /// then isBranch is true, else false.  If the getOpInfo() function was set as
703 /// part of the setupForSymbolicDisassembly() call then that function is called
704 /// to get any symbolic information at the Address for this instruction.  If
705 /// that returns non-zero then the symbolic information it returns is used to
706 /// create an MCExpr and that is added as an operand to the MCInst.  If
707 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
708 /// Value is done and if a symbol is found an MCExpr is created with that, else
709 /// an MCExpr with Value is created.  This function returns true if it adds an
710 /// operand to the MCInst and false otherwise.
711 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
712                                      bool isBranch, uint64_t InstSize,
713                                      MCInst &MI, const void *Decoder) {
714   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
715   // FIXME: Does it make sense for value to be negative?
716   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
717                                        /* Offset */ 0, InstSize);
718 }
719 
720 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
721 /// referenced by a load instruction with the base register that is the Pc.
722 /// These can often be values in a literal pool near the Address of the
723 /// instruction.  The Address of the instruction and its immediate Value are
724 /// used as a possible literal pool entry.  The SymbolLookUp call back will
725 /// return the name of a symbol referenced by the literal pool's entry if
726 /// the referenced address is that of a symbol.  Or it will return a pointer to
727 /// a literal 'C' string if the referenced address of the literal pool's entry
728 /// is an address into a section with 'C' string literals.
729 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
730                                             const void *Decoder) {
731   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
732   Dis->tryAddingPcLoadReferenceComment(Value, Address);
733 }
734 
735 // Thumb1 instructions don't have explicit S bits.  Rather, they
736 // implicitly set CPSR.  Since it's not represented in the encoding, the
737 // auto-generated decoder won't inject the CPSR operand.  We need to fix
738 // that as a post-pass.
739 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
740   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
741   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
742   MCInst::iterator I = MI.begin();
743   for (unsigned i = 0; i < NumOps; ++i, ++I) {
744     if (I == MI.end()) break;
745     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
746       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
747       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
748       return;
749     }
750   }
751 
752   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
753 }
754 
755 static bool isVectorPredicable(unsigned Opcode) {
756   const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
757   unsigned short NumOps = ARMInsts[Opcode].NumOperands;
758   for (unsigned i = 0; i < NumOps; ++i) {
759     if (ARM::isVpred(OpInfo[i].OperandType))
760       return true;
761   }
762   return false;
763 }
764 
765 // Most Thumb instructions don't have explicit predicates in the
766 // encoding, but rather get their predicates from IT context.  We need
767 // to fix up the predicate operands using this context information as a
768 // post-pass.
769 MCDisassembler::DecodeStatus
770 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
771   MCDisassembler::DecodeStatus S = Success;
772 
773   const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
774 
775   // A few instructions actually have predicates encoded in them.  Don't
776   // try to overwrite it if we're seeing one of those.
777   switch (MI.getOpcode()) {
778     case ARM::tBcc:
779     case ARM::t2Bcc:
780     case ARM::tCBZ:
781     case ARM::tCBNZ:
782     case ARM::tCPS:
783     case ARM::t2CPS3p:
784     case ARM::t2CPS2p:
785     case ARM::t2CPS1p:
786     case ARM::t2CSEL:
787     case ARM::t2CSINC:
788     case ARM::t2CSINV:
789     case ARM::t2CSNEG:
790     case ARM::tMOVSr:
791     case ARM::tSETEND:
792       // Some instructions (mostly conditional branches) are not
793       // allowed in IT blocks.
794       if (ITBlock.instrInITBlock())
795         S = SoftFail;
796       else
797         return Success;
798       break;
799     case ARM::t2HINT:
800       if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
801         S = SoftFail;
802       break;
803     case ARM::tB:
804     case ARM::t2B:
805     case ARM::t2TBB:
806     case ARM::t2TBH:
807       // Some instructions (mostly unconditional branches) can
808       // only appears at the end of, or outside of, an IT.
809       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
810         S = SoftFail;
811       break;
812     default:
813       break;
814   }
815 
816   // Warn on non-VPT predicable instruction in a VPT block and a VPT
817   // predicable instruction in an IT block
818   if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
819        (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
820     S = SoftFail;
821 
822   // If we're in an IT/VPT block, base the predicate on that.  Otherwise,
823   // assume a predicate of AL.
824   unsigned CC = ARMCC::AL;
825   unsigned VCC = ARMVCC::None;
826   if (ITBlock.instrInITBlock()) {
827     CC = ITBlock.getITCC();
828     ITBlock.advanceITState();
829   } else if (VPTBlock.instrInVPTBlock()) {
830     VCC = VPTBlock.getVPTPred();
831     VPTBlock.advanceVPTState();
832   }
833 
834   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
835   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
836 
837   MCInst::iterator CCI = MI.begin();
838   for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
839     if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
840   }
841 
842   if (ARMInsts[MI.getOpcode()].isPredicable()) {
843     CCI = MI.insert(CCI, MCOperand::createImm(CC));
844     ++CCI;
845     if (CC == ARMCC::AL)
846       MI.insert(CCI, MCOperand::createReg(0));
847     else
848       MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
849   } else if (CC != ARMCC::AL) {
850     Check(S, SoftFail);
851   }
852 
853   MCInst::iterator VCCI = MI.begin();
854   unsigned VCCPos;
855   for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
856     if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
857   }
858 
859   if (isVectorPredicable(MI.getOpcode())) {
860     VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
861     ++VCCI;
862     if (VCC == ARMVCC::None)
863       VCCI = MI.insert(VCCI, MCOperand::createReg(0));
864     else
865       VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0));
866     ++VCCI;
867     VCCI = MI.insert(VCCI, MCOperand::createReg(0));
868     ++VCCI;
869     if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
870       int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
871         VCCPos + 3, MCOI::TIED_TO);
872       assert(TiedOp >= 0 &&
873              "Inactive register in vpred_r is not tied to an output!");
874       // Copy the operand to ensure it's not invalidated when MI grows.
875       MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp)));
876     }
877   } else if (VCC != ARMVCC::None) {
878     Check(S, SoftFail);
879   }
880 
881   return S;
882 }
883 
884 // Thumb VFP instructions are a special case.  Because we share their
885 // encodings between ARM and Thumb modes, and they are predicable in ARM
886 // mode, the auto-generated decoder will give them an (incorrect)
887 // predicate operand.  We need to rewrite these operands based on the IT
888 // context as a post-pass.
889 void ARMDisassembler::UpdateThumbVFPPredicate(
890   DecodeStatus &S, MCInst &MI) const {
891   unsigned CC;
892   CC = ITBlock.getITCC();
893   if (CC == 0xF)
894     CC = ARMCC::AL;
895   if (ITBlock.instrInITBlock())
896     ITBlock.advanceITState();
897   else if (VPTBlock.instrInVPTBlock()) {
898     CC = VPTBlock.getVPTPred();
899     VPTBlock.advanceVPTState();
900   }
901 
902   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
903   MCInst::iterator I = MI.begin();
904   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
905   for (unsigned i = 0; i < NumOps; ++i, ++I) {
906     if (OpInfo[i].isPredicate() ) {
907       if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
908         Check(S, SoftFail);
909       I->setImm(CC);
910       ++I;
911       if (CC == ARMCC::AL)
912         I->setReg(0);
913       else
914         I->setReg(ARM::CPSR);
915       return;
916     }
917   }
918 }
919 
920 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
921                                                   ArrayRef<uint8_t> Bytes,
922                                                   uint64_t Address,
923                                                   raw_ostream &CS) const {
924   CommentStream = &CS;
925 
926   assert(STI.getFeatureBits()[ARM::ModeThumb] &&
927          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
928 
929   // We want to read exactly 2 bytes of data.
930   if (Bytes.size() < 2) {
931     Size = 0;
932     return MCDisassembler::Fail;
933   }
934 
935   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
936   DecodeStatus Result =
937       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
938   if (Result != MCDisassembler::Fail) {
939     Size = 2;
940     Check(Result, AddThumbPredicate(MI));
941     return Result;
942   }
943 
944   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
945                              STI);
946   if (Result) {
947     Size = 2;
948     bool InITBlock = ITBlock.instrInITBlock();
949     Check(Result, AddThumbPredicate(MI));
950     AddThumb1SBit(MI, InITBlock);
951     return Result;
952   }
953 
954   Result =
955       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
956   if (Result != MCDisassembler::Fail) {
957     Size = 2;
958 
959     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
960     // the Thumb predicate.
961     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
962       Result = MCDisassembler::SoftFail;
963 
964     Check(Result, AddThumbPredicate(MI));
965 
966     // If we find an IT instruction, we need to parse its condition
967     // code and mask operands so that we can apply them correctly
968     // to the subsequent instructions.
969     if (MI.getOpcode() == ARM::t2IT) {
970       unsigned Firstcond = MI.getOperand(0).getImm();
971       unsigned Mask = MI.getOperand(1).getImm();
972       ITBlock.setITState(Firstcond, Mask);
973 
974       // An IT instruction that would give a 'NV' predicate is unpredictable.
975       if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
976         CS << "unpredictable IT predicate sequence";
977     }
978 
979     return Result;
980   }
981 
982   // We want to read exactly 4 bytes of data.
983   if (Bytes.size() < 4) {
984     Size = 0;
985     return MCDisassembler::Fail;
986   }
987 
988   uint32_t Insn32 =
989       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
990 
991   Result =
992       decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
993   if (Result != MCDisassembler::Fail) {
994     Size = 4;
995 
996     // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
997     // the VPT predicate.
998     if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
999       Result = MCDisassembler::SoftFail;
1000 
1001     Check(Result, AddThumbPredicate(MI));
1002 
1003     if (isVPTOpcode(MI.getOpcode())) {
1004       unsigned Mask = MI.getOperand(0).getImm();
1005       VPTBlock.setVPTState(Mask);
1006     }
1007 
1008     return Result;
1009   }
1010 
1011   Result =
1012       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1013   if (Result != MCDisassembler::Fail) {
1014     Size = 4;
1015     bool InITBlock = ITBlock.instrInITBlock();
1016     Check(Result, AddThumbPredicate(MI));
1017     AddThumb1SBit(MI, InITBlock);
1018     return Result;
1019   }
1020 
1021   Result =
1022       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1023   if (Result != MCDisassembler::Fail) {
1024     Size = 4;
1025     Check(Result, AddThumbPredicate(MI));
1026     return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1027   }
1028 
1029   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1030     Result =
1031         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1032     if (Result != MCDisassembler::Fail) {
1033       Size = 4;
1034       UpdateThumbVFPPredicate(Result, MI);
1035       return Result;
1036     }
1037   }
1038 
1039   Result =
1040       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1041   if (Result != MCDisassembler::Fail) {
1042     Size = 4;
1043     return Result;
1044   }
1045 
1046   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1047     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1048                                STI);
1049     if (Result != MCDisassembler::Fail) {
1050       Size = 4;
1051       Check(Result, AddThumbPredicate(MI));
1052       return Result;
1053     }
1054   }
1055 
1056   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1057     uint32_t NEONLdStInsn = Insn32;
1058     NEONLdStInsn &= 0xF0FFFFFF;
1059     NEONLdStInsn |= 0x04000000;
1060     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1061                                Address, this, STI);
1062     if (Result != MCDisassembler::Fail) {
1063       Size = 4;
1064       Check(Result, AddThumbPredicate(MI));
1065       return Result;
1066     }
1067   }
1068 
1069   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1070     uint32_t NEONDataInsn = Insn32;
1071     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1072     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1073     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1074     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1075                                Address, this, STI);
1076     if (Result != MCDisassembler::Fail) {
1077       Size = 4;
1078       Check(Result, AddThumbPredicate(MI));
1079       return Result;
1080     }
1081 
1082     uint32_t NEONCryptoInsn = Insn32;
1083     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1084     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1085     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1086     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1087                                Address, this, STI);
1088     if (Result != MCDisassembler::Fail) {
1089       Size = 4;
1090       return Result;
1091     }
1092 
1093     uint32_t NEONv8Insn = Insn32;
1094     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1095     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1096                                this, STI);
1097     if (Result != MCDisassembler::Fail) {
1098       Size = 4;
1099       return Result;
1100     }
1101   }
1102 
1103   uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1104   const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1105                                     ? DecoderTableThumb2CDE32
1106                                     : DecoderTableThumb2CoProc32;
1107   Result =
1108       decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1109   if (Result != MCDisassembler::Fail) {
1110     Size = 4;
1111     Check(Result, AddThumbPredicate(MI));
1112     return Result;
1113   }
1114 
1115   Size = 0;
1116   return MCDisassembler::Fail;
1117 }
1118 
1119 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() {
1120   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
1121                                          createARMDisassembler);
1122   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
1123                                          createARMDisassembler);
1124   TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
1125                                          createARMDisassembler);
1126   TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
1127                                          createARMDisassembler);
1128 }
1129 
1130 static const uint16_t GPRDecoderTable[] = {
1131   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1132   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1133   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1134   ARM::R12, ARM::SP, ARM::LR, ARM::PC
1135 };
1136 
1137 static const uint16_t CLRMGPRDecoderTable[] = {
1138   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1139   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1140   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1141   ARM::R12, 0, ARM::LR, ARM::APSR
1142 };
1143 
1144 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1145                                    uint64_t Address, const void *Decoder) {
1146   if (RegNo > 15)
1147     return MCDisassembler::Fail;
1148 
1149   unsigned Register = GPRDecoderTable[RegNo];
1150   Inst.addOperand(MCOperand::createReg(Register));
1151   return MCDisassembler::Success;
1152 }
1153 
1154 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1155                                                uint64_t Address,
1156                                                const void *Decoder) {
1157   if (RegNo > 15)
1158     return MCDisassembler::Fail;
1159 
1160   unsigned Register = CLRMGPRDecoderTable[RegNo];
1161   if (Register == 0)
1162     return MCDisassembler::Fail;
1163 
1164   Inst.addOperand(MCOperand::createReg(Register));
1165   return MCDisassembler::Success;
1166 }
1167 
1168 static DecodeStatus
1169 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1170                            uint64_t Address, const void *Decoder) {
1171   DecodeStatus S = MCDisassembler::Success;
1172 
1173   if (RegNo == 15)
1174     S = MCDisassembler::SoftFail;
1175 
1176   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1177 
1178   return S;
1179 }
1180 
1181 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1182                                                uint64_t Address,
1183                                                const void *Decoder) {
1184   DecodeStatus S = MCDisassembler::Success;
1185 
1186   if (RegNo == 13)
1187     S = MCDisassembler::SoftFail;
1188 
1189   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1190 
1191   return S;
1192 }
1193 
1194 static DecodeStatus
1195 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
1196                                uint64_t Address, const void *Decoder) {
1197   DecodeStatus S = MCDisassembler::Success;
1198 
1199   if (RegNo == 15)
1200   {
1201     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1202     return MCDisassembler::Success;
1203   }
1204 
1205   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1206   return S;
1207 }
1208 
1209 static DecodeStatus
1210 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1211                              uint64_t Address, const void *Decoder) {
1212   DecodeStatus S = MCDisassembler::Success;
1213 
1214   if (RegNo == 15)
1215   {
1216     Inst.addOperand(MCOperand::createReg(ARM::ZR));
1217     return MCDisassembler::Success;
1218   }
1219 
1220   if (RegNo == 13)
1221     Check(S, MCDisassembler::SoftFail);
1222 
1223   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1224   return S;
1225 }
1226 
1227 static DecodeStatus
1228 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1229                                  uint64_t Address, const void *Decoder) {
1230   DecodeStatus S = MCDisassembler::Success;
1231   if (RegNo == 13)
1232     return MCDisassembler::Fail;
1233   Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1234   return S;
1235 }
1236 
1237 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1238                                    uint64_t Address, const void *Decoder) {
1239   if (RegNo > 7)
1240     return MCDisassembler::Fail;
1241   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1242 }
1243 
1244 static const uint16_t GPRPairDecoderTable[] = {
1245   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
1246   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1247 };
1248 
1249 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1250                                    uint64_t Address, const void *Decoder) {
1251   DecodeStatus S = MCDisassembler::Success;
1252 
1253   // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1254   // rather than SoftFail as there is no GPRPair table entry for index 7.
1255   if (RegNo > 13)
1256     return MCDisassembler::Fail;
1257 
1258   if (RegNo & 1)
1259      S = MCDisassembler::SoftFail;
1260 
1261   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1262   Inst.addOperand(MCOperand::createReg(RegisterPair));
1263   return S;
1264 }
1265 
1266 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
1267                                    uint64_t Address, const void *Decoder) {
1268   if (RegNo > 13)
1269     return MCDisassembler::Fail;
1270 
1271   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1272   Inst.addOperand(MCOperand::createReg(RegisterPair));
1273 
1274   if ((RegNo & 1) || RegNo > 10)
1275      return MCDisassembler::SoftFail;
1276   return MCDisassembler::Success;
1277 }
1278 
1279 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1280                                              uint64_t Address,
1281                                              const void *Decoder) {
1282   if (RegNo != 13)
1283     return MCDisassembler::Fail;
1284 
1285   unsigned Register = GPRDecoderTable[RegNo];
1286   Inst.addOperand(MCOperand::createReg(Register));
1287   return MCDisassembler::Success;
1288 }
1289 
1290 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1291                                    uint64_t Address, const void *Decoder) {
1292   unsigned Register = 0;
1293   switch (RegNo) {
1294     case 0:
1295       Register = ARM::R0;
1296       break;
1297     case 1:
1298       Register = ARM::R1;
1299       break;
1300     case 2:
1301       Register = ARM::R2;
1302       break;
1303     case 3:
1304       Register = ARM::R3;
1305       break;
1306     case 9:
1307       Register = ARM::R9;
1308       break;
1309     case 12:
1310       Register = ARM::R12;
1311       break;
1312     default:
1313       return MCDisassembler::Fail;
1314     }
1315 
1316   Inst.addOperand(MCOperand::createReg(Register));
1317   return MCDisassembler::Success;
1318 }
1319 
1320 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1321                                    uint64_t Address, const void *Decoder) {
1322   DecodeStatus S = MCDisassembler::Success;
1323 
1324   const FeatureBitset &featureBits =
1325     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1326 
1327   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1328     S = MCDisassembler::SoftFail;
1329 
1330   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1331   return S;
1332 }
1333 
1334 static const uint16_t SPRDecoderTable[] = {
1335      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
1336      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
1337      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
1338     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1339     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1340     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1341     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1342     ARM::S28, ARM::S29, ARM::S30, ARM::S31
1343 };
1344 
1345 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1346                                    uint64_t Address, const void *Decoder) {
1347   if (RegNo > 31)
1348     return MCDisassembler::Fail;
1349 
1350   unsigned Register = SPRDecoderTable[RegNo];
1351   Inst.addOperand(MCOperand::createReg(Register));
1352   return MCDisassembler::Success;
1353 }
1354 
1355 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1356                                    uint64_t Address, const void *Decoder) {
1357   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1358 }
1359 
1360 static const uint16_t DPRDecoderTable[] = {
1361      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
1362      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
1363      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
1364     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1365     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1366     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1367     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1368     ARM::D28, ARM::D29, ARM::D30, ARM::D31
1369 };
1370 
1371 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1372                                    uint64_t Address, const void *Decoder) {
1373   const FeatureBitset &featureBits =
1374     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1375 
1376   bool hasD32 = featureBits[ARM::FeatureD32];
1377 
1378   if (RegNo > 31 || (!hasD32 && RegNo > 15))
1379     return MCDisassembler::Fail;
1380 
1381   unsigned Register = DPRDecoderTable[RegNo];
1382   Inst.addOperand(MCOperand::createReg(Register));
1383   return MCDisassembler::Success;
1384 }
1385 
1386 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1387                                    uint64_t Address, const void *Decoder) {
1388   if (RegNo > 7)
1389     return MCDisassembler::Fail;
1390   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1391 }
1392 
1393 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1394                                    uint64_t Address, const void *Decoder) {
1395   if (RegNo > 15)
1396     return MCDisassembler::Fail;
1397   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1398 }
1399 
1400 static DecodeStatus
1401 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1402                             uint64_t Address, const void *Decoder) {
1403   if (RegNo > 15)
1404     return MCDisassembler::Fail;
1405   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1406 }
1407 
1408 static const uint16_t QPRDecoderTable[] = {
1409      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
1410      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
1411      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
1412     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1413 };
1414 
1415 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1416                                    uint64_t Address, const void *Decoder) {
1417   if (RegNo > 31 || (RegNo & 1) != 0)
1418     return MCDisassembler::Fail;
1419   RegNo >>= 1;
1420 
1421   unsigned Register = QPRDecoderTable[RegNo];
1422   Inst.addOperand(MCOperand::createReg(Register));
1423   return MCDisassembler::Success;
1424 }
1425 
1426 static const uint16_t DPairDecoderTable[] = {
1427   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
1428   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
1429   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
1430   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1431   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1432   ARM::Q15
1433 };
1434 
1435 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1436                                    uint64_t Address, const void *Decoder) {
1437   if (RegNo > 30)
1438     return MCDisassembler::Fail;
1439 
1440   unsigned Register = DPairDecoderTable[RegNo];
1441   Inst.addOperand(MCOperand::createReg(Register));
1442   return MCDisassembler::Success;
1443 }
1444 
1445 static const uint16_t DPairSpacedDecoderTable[] = {
1446   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
1447   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
1448   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
1449   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1450   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1451   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1452   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1453   ARM::D28_D30, ARM::D29_D31
1454 };
1455 
1456 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1457                                                    unsigned RegNo,
1458                                                    uint64_t Address,
1459                                                    const void *Decoder) {
1460   if (RegNo > 29)
1461     return MCDisassembler::Fail;
1462 
1463   unsigned Register = DPairSpacedDecoderTable[RegNo];
1464   Inst.addOperand(MCOperand::createReg(Register));
1465   return MCDisassembler::Success;
1466 }
1467 
1468 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1469                                uint64_t Address, const void *Decoder) {
1470   DecodeStatus S = MCDisassembler::Success;
1471   if (Val == 0xF) return MCDisassembler::Fail;
1472   // AL predicate is not allowed on Thumb1 branches.
1473   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1474     return MCDisassembler::Fail;
1475   if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1476     Check(S, MCDisassembler::SoftFail);
1477   Inst.addOperand(MCOperand::createImm(Val));
1478   if (Val == ARMCC::AL) {
1479     Inst.addOperand(MCOperand::createReg(0));
1480   } else
1481     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1482   return S;
1483 }
1484 
1485 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1486                                uint64_t Address, const void *Decoder) {
1487   if (Val)
1488     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1489   else
1490     Inst.addOperand(MCOperand::createReg(0));
1491   return MCDisassembler::Success;
1492 }
1493 
1494 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1495                                uint64_t Address, const void *Decoder) {
1496   DecodeStatus S = MCDisassembler::Success;
1497 
1498   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1499   unsigned type = fieldFromInstruction(Val, 5, 2);
1500   unsigned imm = fieldFromInstruction(Val, 7, 5);
1501 
1502   // Register-immediate
1503   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1504     return MCDisassembler::Fail;
1505 
1506   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1507   switch (type) {
1508     case 0:
1509       Shift = ARM_AM::lsl;
1510       break;
1511     case 1:
1512       Shift = ARM_AM::lsr;
1513       break;
1514     case 2:
1515       Shift = ARM_AM::asr;
1516       break;
1517     case 3:
1518       Shift = ARM_AM::ror;
1519       break;
1520   }
1521 
1522   if (Shift == ARM_AM::ror && imm == 0)
1523     Shift = ARM_AM::rrx;
1524 
1525   unsigned Op = Shift | (imm << 3);
1526   Inst.addOperand(MCOperand::createImm(Op));
1527 
1528   return S;
1529 }
1530 
1531 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1532                                uint64_t Address, const void *Decoder) {
1533   DecodeStatus S = MCDisassembler::Success;
1534 
1535   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1536   unsigned type = fieldFromInstruction(Val, 5, 2);
1537   unsigned Rs = fieldFromInstruction(Val, 8, 4);
1538 
1539   // Register-register
1540   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1541     return MCDisassembler::Fail;
1542   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1543     return MCDisassembler::Fail;
1544 
1545   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1546   switch (type) {
1547     case 0:
1548       Shift = ARM_AM::lsl;
1549       break;
1550     case 1:
1551       Shift = ARM_AM::lsr;
1552       break;
1553     case 2:
1554       Shift = ARM_AM::asr;
1555       break;
1556     case 3:
1557       Shift = ARM_AM::ror;
1558       break;
1559   }
1560 
1561   Inst.addOperand(MCOperand::createImm(Shift));
1562 
1563   return S;
1564 }
1565 
1566 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1567                                  uint64_t Address, const void *Decoder) {
1568   DecodeStatus S = MCDisassembler::Success;
1569 
1570   bool NeedDisjointWriteback = false;
1571   unsigned WritebackReg = 0;
1572   bool CLRM = false;
1573   switch (Inst.getOpcode()) {
1574   default:
1575     break;
1576   case ARM::LDMIA_UPD:
1577   case ARM::LDMDB_UPD:
1578   case ARM::LDMIB_UPD:
1579   case ARM::LDMDA_UPD:
1580   case ARM::t2LDMIA_UPD:
1581   case ARM::t2LDMDB_UPD:
1582   case ARM::t2STMIA_UPD:
1583   case ARM::t2STMDB_UPD:
1584     NeedDisjointWriteback = true;
1585     WritebackReg = Inst.getOperand(0).getReg();
1586     break;
1587   case ARM::t2CLRM:
1588     CLRM = true;
1589     break;
1590   }
1591 
1592   // Empty register lists are not allowed.
1593   if (Val == 0) return MCDisassembler::Fail;
1594   for (unsigned i = 0; i < 16; ++i) {
1595     if (Val & (1 << i)) {
1596       if (CLRM) {
1597         if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1598           return MCDisassembler::Fail;
1599         }
1600       } else {
1601         if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1602           return MCDisassembler::Fail;
1603         // Writeback not allowed if Rn is in the target list.
1604         if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1605           Check(S, MCDisassembler::SoftFail);
1606       }
1607     }
1608   }
1609 
1610   return S;
1611 }
1612 
1613 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1614                                  uint64_t Address, const void *Decoder) {
1615   DecodeStatus S = MCDisassembler::Success;
1616 
1617   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1618   unsigned regs = fieldFromInstruction(Val, 0, 8);
1619 
1620   // In case of unpredictable encoding, tweak the operands.
1621   if (regs == 0 || (Vd + regs) > 32) {
1622     regs = Vd + regs > 32 ? 32 - Vd : regs;
1623     regs = std::max( 1u, regs);
1624     S = MCDisassembler::SoftFail;
1625   }
1626 
1627   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1628     return MCDisassembler::Fail;
1629   for (unsigned i = 0; i < (regs - 1); ++i) {
1630     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1631       return MCDisassembler::Fail;
1632   }
1633 
1634   return S;
1635 }
1636 
1637 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1638                                  uint64_t Address, const void *Decoder) {
1639   DecodeStatus S = MCDisassembler::Success;
1640 
1641   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1642   unsigned regs = fieldFromInstruction(Val, 1, 7);
1643 
1644   // In case of unpredictable encoding, tweak the operands.
1645   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1646     regs = Vd + regs > 32 ? 32 - Vd : regs;
1647     regs = std::max( 1u, regs);
1648     regs = std::min(16u, regs);
1649     S = MCDisassembler::SoftFail;
1650   }
1651 
1652   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1653       return MCDisassembler::Fail;
1654   for (unsigned i = 0; i < (regs - 1); ++i) {
1655     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1656       return MCDisassembler::Fail;
1657   }
1658 
1659   return S;
1660 }
1661 
1662 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1663                                       uint64_t Address, const void *Decoder) {
1664   // This operand encodes a mask of contiguous zeros between a specified MSB
1665   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1666   // the mask of all bits LSB-and-lower, and then xor them to create
1667   // the mask of that's all ones on [msb, lsb].  Finally we not it to
1668   // create the final mask.
1669   unsigned msb = fieldFromInstruction(Val, 5, 5);
1670   unsigned lsb = fieldFromInstruction(Val, 0, 5);
1671 
1672   DecodeStatus S = MCDisassembler::Success;
1673   if (lsb > msb) {
1674     Check(S, MCDisassembler::SoftFail);
1675     // The check above will cause the warning for the "potentially undefined
1676     // instruction encoding" but we can't build a bad MCOperand value here
1677     // with a lsb > msb or else printing the MCInst will cause a crash.
1678     lsb = msb;
1679   }
1680 
1681   uint32_t msb_mask = 0xFFFFFFFF;
1682   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1683   uint32_t lsb_mask = (1U << lsb) - 1;
1684 
1685   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1686   return S;
1687 }
1688 
1689 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1690                                   uint64_t Address, const void *Decoder) {
1691   DecodeStatus S = MCDisassembler::Success;
1692 
1693   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1694   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1695   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1696   unsigned imm = fieldFromInstruction(Insn, 0, 8);
1697   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1698   unsigned U = fieldFromInstruction(Insn, 23, 1);
1699   const FeatureBitset &featureBits =
1700     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1701 
1702   switch (Inst.getOpcode()) {
1703     case ARM::LDC_OFFSET:
1704     case ARM::LDC_PRE:
1705     case ARM::LDC_POST:
1706     case ARM::LDC_OPTION:
1707     case ARM::LDCL_OFFSET:
1708     case ARM::LDCL_PRE:
1709     case ARM::LDCL_POST:
1710     case ARM::LDCL_OPTION:
1711     case ARM::STC_OFFSET:
1712     case ARM::STC_PRE:
1713     case ARM::STC_POST:
1714     case ARM::STC_OPTION:
1715     case ARM::STCL_OFFSET:
1716     case ARM::STCL_PRE:
1717     case ARM::STCL_POST:
1718     case ARM::STCL_OPTION:
1719     case ARM::t2LDC_OFFSET:
1720     case ARM::t2LDC_PRE:
1721     case ARM::t2LDC_POST:
1722     case ARM::t2LDC_OPTION:
1723     case ARM::t2LDCL_OFFSET:
1724     case ARM::t2LDCL_PRE:
1725     case ARM::t2LDCL_POST:
1726     case ARM::t2LDCL_OPTION:
1727     case ARM::t2STC_OFFSET:
1728     case ARM::t2STC_PRE:
1729     case ARM::t2STC_POST:
1730     case ARM::t2STC_OPTION:
1731     case ARM::t2STCL_OFFSET:
1732     case ARM::t2STCL_PRE:
1733     case ARM::t2STCL_POST:
1734     case ARM::t2STCL_OPTION:
1735     case ARM::t2LDC2_OFFSET:
1736     case ARM::t2LDC2L_OFFSET:
1737     case ARM::t2LDC2_PRE:
1738     case ARM::t2LDC2L_PRE:
1739     case ARM::t2STC2_OFFSET:
1740     case ARM::t2STC2L_OFFSET:
1741     case ARM::t2STC2_PRE:
1742     case ARM::t2STC2L_PRE:
1743     case ARM::LDC2_OFFSET:
1744     case ARM::LDC2L_OFFSET:
1745     case ARM::LDC2_PRE:
1746     case ARM::LDC2L_PRE:
1747     case ARM::STC2_OFFSET:
1748     case ARM::STC2L_OFFSET:
1749     case ARM::STC2_PRE:
1750     case ARM::STC2L_PRE:
1751     case ARM::t2LDC2_OPTION:
1752     case ARM::t2STC2_OPTION:
1753     case ARM::t2LDC2_POST:
1754     case ARM::t2LDC2L_POST:
1755     case ARM::t2STC2_POST:
1756     case ARM::t2STC2L_POST:
1757     case ARM::LDC2_POST:
1758     case ARM::LDC2L_POST:
1759     case ARM::STC2_POST:
1760     case ARM::STC2L_POST:
1761       if (coproc == 0xA || coproc == 0xB ||
1762           (featureBits[ARM::HasV8_1MMainlineOps] &&
1763            (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1764             coproc == 0xE || coproc == 0xF)))
1765         return MCDisassembler::Fail;
1766       break;
1767     default:
1768       break;
1769   }
1770 
1771   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1772     return MCDisassembler::Fail;
1773 
1774   Inst.addOperand(MCOperand::createImm(coproc));
1775   Inst.addOperand(MCOperand::createImm(CRd));
1776   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1777     return MCDisassembler::Fail;
1778 
1779   switch (Inst.getOpcode()) {
1780     case ARM::t2LDC2_OFFSET:
1781     case ARM::t2LDC2L_OFFSET:
1782     case ARM::t2LDC2_PRE:
1783     case ARM::t2LDC2L_PRE:
1784     case ARM::t2STC2_OFFSET:
1785     case ARM::t2STC2L_OFFSET:
1786     case ARM::t2STC2_PRE:
1787     case ARM::t2STC2L_PRE:
1788     case ARM::LDC2_OFFSET:
1789     case ARM::LDC2L_OFFSET:
1790     case ARM::LDC2_PRE:
1791     case ARM::LDC2L_PRE:
1792     case ARM::STC2_OFFSET:
1793     case ARM::STC2L_OFFSET:
1794     case ARM::STC2_PRE:
1795     case ARM::STC2L_PRE:
1796     case ARM::t2LDC_OFFSET:
1797     case ARM::t2LDCL_OFFSET:
1798     case ARM::t2LDC_PRE:
1799     case ARM::t2LDCL_PRE:
1800     case ARM::t2STC_OFFSET:
1801     case ARM::t2STCL_OFFSET:
1802     case ARM::t2STC_PRE:
1803     case ARM::t2STCL_PRE:
1804     case ARM::LDC_OFFSET:
1805     case ARM::LDCL_OFFSET:
1806     case ARM::LDC_PRE:
1807     case ARM::LDCL_PRE:
1808     case ARM::STC_OFFSET:
1809     case ARM::STCL_OFFSET:
1810     case ARM::STC_PRE:
1811     case ARM::STCL_PRE:
1812       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1813       Inst.addOperand(MCOperand::createImm(imm));
1814       break;
1815     case ARM::t2LDC2_POST:
1816     case ARM::t2LDC2L_POST:
1817     case ARM::t2STC2_POST:
1818     case ARM::t2STC2L_POST:
1819     case ARM::LDC2_POST:
1820     case ARM::LDC2L_POST:
1821     case ARM::STC2_POST:
1822     case ARM::STC2L_POST:
1823     case ARM::t2LDC_POST:
1824     case ARM::t2LDCL_POST:
1825     case ARM::t2STC_POST:
1826     case ARM::t2STCL_POST:
1827     case ARM::LDC_POST:
1828     case ARM::LDCL_POST:
1829     case ARM::STC_POST:
1830     case ARM::STCL_POST:
1831       imm |= U << 8;
1832       LLVM_FALLTHROUGH;
1833     default:
1834       // The 'option' variant doesn't encode 'U' in the immediate since
1835       // the immediate is unsigned [0,255].
1836       Inst.addOperand(MCOperand::createImm(imm));
1837       break;
1838   }
1839 
1840   switch (Inst.getOpcode()) {
1841     case ARM::LDC_OFFSET:
1842     case ARM::LDC_PRE:
1843     case ARM::LDC_POST:
1844     case ARM::LDC_OPTION:
1845     case ARM::LDCL_OFFSET:
1846     case ARM::LDCL_PRE:
1847     case ARM::LDCL_POST:
1848     case ARM::LDCL_OPTION:
1849     case ARM::STC_OFFSET:
1850     case ARM::STC_PRE:
1851     case ARM::STC_POST:
1852     case ARM::STC_OPTION:
1853     case ARM::STCL_OFFSET:
1854     case ARM::STCL_PRE:
1855     case ARM::STCL_POST:
1856     case ARM::STCL_OPTION:
1857       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1858         return MCDisassembler::Fail;
1859       break;
1860     default:
1861       break;
1862   }
1863 
1864   return S;
1865 }
1866 
1867 static DecodeStatus
1868 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1869                               uint64_t Address, const void *Decoder) {
1870   DecodeStatus S = MCDisassembler::Success;
1871 
1872   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1873   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1874   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1875   unsigned imm = fieldFromInstruction(Insn, 0, 12);
1876   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1877   unsigned reg = fieldFromInstruction(Insn, 25, 1);
1878   unsigned P = fieldFromInstruction(Insn, 24, 1);
1879   unsigned W = fieldFromInstruction(Insn, 21, 1);
1880 
1881   // On stores, the writeback operand precedes Rt.
1882   switch (Inst.getOpcode()) {
1883     case ARM::STR_POST_IMM:
1884     case ARM::STR_POST_REG:
1885     case ARM::STRB_POST_IMM:
1886     case ARM::STRB_POST_REG:
1887     case ARM::STRT_POST_REG:
1888     case ARM::STRT_POST_IMM:
1889     case ARM::STRBT_POST_REG:
1890     case ARM::STRBT_POST_IMM:
1891       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1892         return MCDisassembler::Fail;
1893       break;
1894     default:
1895       break;
1896   }
1897 
1898   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1899     return MCDisassembler::Fail;
1900 
1901   // On loads, the writeback operand comes after Rt.
1902   switch (Inst.getOpcode()) {
1903     case ARM::LDR_POST_IMM:
1904     case ARM::LDR_POST_REG:
1905     case ARM::LDRB_POST_IMM:
1906     case ARM::LDRB_POST_REG:
1907     case ARM::LDRBT_POST_REG:
1908     case ARM::LDRBT_POST_IMM:
1909     case ARM::LDRT_POST_REG:
1910     case ARM::LDRT_POST_IMM:
1911       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1912         return MCDisassembler::Fail;
1913       break;
1914     default:
1915       break;
1916   }
1917 
1918   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1919     return MCDisassembler::Fail;
1920 
1921   ARM_AM::AddrOpc Op = ARM_AM::add;
1922   if (!fieldFromInstruction(Insn, 23, 1))
1923     Op = ARM_AM::sub;
1924 
1925   bool writeback = (P == 0) || (W == 1);
1926   unsigned idx_mode = 0;
1927   if (P && writeback)
1928     idx_mode = ARMII::IndexModePre;
1929   else if (!P && writeback)
1930     idx_mode = ARMII::IndexModePost;
1931 
1932   if (writeback && (Rn == 15 || Rn == Rt))
1933     S = MCDisassembler::SoftFail; // UNPREDICTABLE
1934 
1935   if (reg) {
1936     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1937       return MCDisassembler::Fail;
1938     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1939     switch( fieldFromInstruction(Insn, 5, 2)) {
1940       case 0:
1941         Opc = ARM_AM::lsl;
1942         break;
1943       case 1:
1944         Opc = ARM_AM::lsr;
1945         break;
1946       case 2:
1947         Opc = ARM_AM::asr;
1948         break;
1949       case 3:
1950         Opc = ARM_AM::ror;
1951         break;
1952       default:
1953         return MCDisassembler::Fail;
1954     }
1955     unsigned amt = fieldFromInstruction(Insn, 7, 5);
1956     if (Opc == ARM_AM::ror && amt == 0)
1957       Opc = ARM_AM::rrx;
1958     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1959 
1960     Inst.addOperand(MCOperand::createImm(imm));
1961   } else {
1962     Inst.addOperand(MCOperand::createReg(0));
1963     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1964     Inst.addOperand(MCOperand::createImm(tmp));
1965   }
1966 
1967   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1968     return MCDisassembler::Fail;
1969 
1970   return S;
1971 }
1972 
1973 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1974                                   uint64_t Address, const void *Decoder) {
1975   DecodeStatus S = MCDisassembler::Success;
1976 
1977   unsigned Rn = fieldFromInstruction(Val, 13, 4);
1978   unsigned Rm = fieldFromInstruction(Val,  0, 4);
1979   unsigned type = fieldFromInstruction(Val, 5, 2);
1980   unsigned imm = fieldFromInstruction(Val, 7, 5);
1981   unsigned U = fieldFromInstruction(Val, 12, 1);
1982 
1983   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1984   switch (type) {
1985     case 0:
1986       ShOp = ARM_AM::lsl;
1987       break;
1988     case 1:
1989       ShOp = ARM_AM::lsr;
1990       break;
1991     case 2:
1992       ShOp = ARM_AM::asr;
1993       break;
1994     case 3:
1995       ShOp = ARM_AM::ror;
1996       break;
1997   }
1998 
1999   if (ShOp == ARM_AM::ror && imm == 0)
2000     ShOp = ARM_AM::rrx;
2001 
2002   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2003     return MCDisassembler::Fail;
2004   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2005     return MCDisassembler::Fail;
2006   unsigned shift;
2007   if (U)
2008     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
2009   else
2010     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
2011   Inst.addOperand(MCOperand::createImm(shift));
2012 
2013   return S;
2014 }
2015 
2016 static DecodeStatus
2017 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
2018                            uint64_t Address, const void *Decoder) {
2019   DecodeStatus S = MCDisassembler::Success;
2020 
2021   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
2022   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2023   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2024   unsigned type = fieldFromInstruction(Insn, 22, 1);
2025   unsigned imm = fieldFromInstruction(Insn, 8, 4);
2026   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2027   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2028   unsigned W = fieldFromInstruction(Insn, 21, 1);
2029   unsigned P = fieldFromInstruction(Insn, 24, 1);
2030   unsigned Rt2 = Rt + 1;
2031 
2032   bool writeback = (W == 1) | (P == 0);
2033 
2034   // For {LD,ST}RD, Rt must be even, else undefined.
2035   switch (Inst.getOpcode()) {
2036     case ARM::STRD:
2037     case ARM::STRD_PRE:
2038     case ARM::STRD_POST:
2039     case ARM::LDRD:
2040     case ARM::LDRD_PRE:
2041     case ARM::LDRD_POST:
2042       if (Rt & 0x1) S = MCDisassembler::SoftFail;
2043       break;
2044     default:
2045       break;
2046   }
2047   switch (Inst.getOpcode()) {
2048     case ARM::STRD:
2049     case ARM::STRD_PRE:
2050     case ARM::STRD_POST:
2051       if (P == 0 && W == 1)
2052         S = MCDisassembler::SoftFail;
2053 
2054       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2055         S = MCDisassembler::SoftFail;
2056       if (type && Rm == 15)
2057         S = MCDisassembler::SoftFail;
2058       if (Rt2 == 15)
2059         S = MCDisassembler::SoftFail;
2060       if (!type && fieldFromInstruction(Insn, 8, 4))
2061         S = MCDisassembler::SoftFail;
2062       break;
2063     case ARM::STRH:
2064     case ARM::STRH_PRE:
2065     case ARM::STRH_POST:
2066       if (Rt == 15)
2067         S = MCDisassembler::SoftFail;
2068       if (writeback && (Rn == 15 || Rn == Rt))
2069         S = MCDisassembler::SoftFail;
2070       if (!type && Rm == 15)
2071         S = MCDisassembler::SoftFail;
2072       break;
2073     case ARM::LDRD:
2074     case ARM::LDRD_PRE:
2075     case ARM::LDRD_POST:
2076       if (type && Rn == 15) {
2077         if (Rt2 == 15)
2078           S = MCDisassembler::SoftFail;
2079         break;
2080       }
2081       if (P == 0 && W == 1)
2082         S = MCDisassembler::SoftFail;
2083       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2084         S = MCDisassembler::SoftFail;
2085       if (!type && writeback && Rn == 15)
2086         S = MCDisassembler::SoftFail;
2087       if (writeback && (Rn == Rt || Rn == Rt2))
2088         S = MCDisassembler::SoftFail;
2089       break;
2090     case ARM::LDRH:
2091     case ARM::LDRH_PRE:
2092     case ARM::LDRH_POST:
2093       if (type && Rn == 15) {
2094         if (Rt == 15)
2095           S = MCDisassembler::SoftFail;
2096         break;
2097       }
2098       if (Rt == 15)
2099         S = MCDisassembler::SoftFail;
2100       if (!type && Rm == 15)
2101         S = MCDisassembler::SoftFail;
2102       if (!type && writeback && (Rn == 15 || Rn == Rt))
2103         S = MCDisassembler::SoftFail;
2104       break;
2105     case ARM::LDRSH:
2106     case ARM::LDRSH_PRE:
2107     case ARM::LDRSH_POST:
2108     case ARM::LDRSB:
2109     case ARM::LDRSB_PRE:
2110     case ARM::LDRSB_POST:
2111       if (type && Rn == 15) {
2112         if (Rt == 15)
2113           S = MCDisassembler::SoftFail;
2114         break;
2115       }
2116       if (type && (Rt == 15 || (writeback && Rn == Rt)))
2117         S = MCDisassembler::SoftFail;
2118       if (!type && (Rt == 15 || Rm == 15))
2119         S = MCDisassembler::SoftFail;
2120       if (!type && writeback && (Rn == 15 || Rn == Rt))
2121         S = MCDisassembler::SoftFail;
2122       break;
2123     default:
2124       break;
2125   }
2126 
2127   if (writeback) { // Writeback
2128     if (P)
2129       U |= ARMII::IndexModePre << 9;
2130     else
2131       U |= ARMII::IndexModePost << 9;
2132 
2133     // On stores, the writeback operand precedes Rt.
2134     switch (Inst.getOpcode()) {
2135     case ARM::STRD:
2136     case ARM::STRD_PRE:
2137     case ARM::STRD_POST:
2138     case ARM::STRH:
2139     case ARM::STRH_PRE:
2140     case ARM::STRH_POST:
2141       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2142         return MCDisassembler::Fail;
2143       break;
2144     default:
2145       break;
2146     }
2147   }
2148 
2149   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2150     return MCDisassembler::Fail;
2151   switch (Inst.getOpcode()) {
2152     case ARM::STRD:
2153     case ARM::STRD_PRE:
2154     case ARM::STRD_POST:
2155     case ARM::LDRD:
2156     case ARM::LDRD_PRE:
2157     case ARM::LDRD_POST:
2158       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2159         return MCDisassembler::Fail;
2160       break;
2161     default:
2162       break;
2163   }
2164 
2165   if (writeback) {
2166     // On loads, the writeback operand comes after Rt.
2167     switch (Inst.getOpcode()) {
2168     case ARM::LDRD:
2169     case ARM::LDRD_PRE:
2170     case ARM::LDRD_POST:
2171     case ARM::LDRH:
2172     case ARM::LDRH_PRE:
2173     case ARM::LDRH_POST:
2174     case ARM::LDRSH:
2175     case ARM::LDRSH_PRE:
2176     case ARM::LDRSH_POST:
2177     case ARM::LDRSB:
2178     case ARM::LDRSB_PRE:
2179     case ARM::LDRSB_POST:
2180     case ARM::LDRHTr:
2181     case ARM::LDRSBTr:
2182       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2183         return MCDisassembler::Fail;
2184       break;
2185     default:
2186       break;
2187     }
2188   }
2189 
2190   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2191     return MCDisassembler::Fail;
2192 
2193   if (type) {
2194     Inst.addOperand(MCOperand::createReg(0));
2195     Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2196   } else {
2197     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2198     return MCDisassembler::Fail;
2199     Inst.addOperand(MCOperand::createImm(U));
2200   }
2201 
2202   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2203     return MCDisassembler::Fail;
2204 
2205   return S;
2206 }
2207 
2208 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2209                                  uint64_t Address, const void *Decoder) {
2210   DecodeStatus S = MCDisassembler::Success;
2211 
2212   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2213   unsigned mode = fieldFromInstruction(Insn, 23, 2);
2214 
2215   switch (mode) {
2216     case 0:
2217       mode = ARM_AM::da;
2218       break;
2219     case 1:
2220       mode = ARM_AM::ia;
2221       break;
2222     case 2:
2223       mode = ARM_AM::db;
2224       break;
2225     case 3:
2226       mode = ARM_AM::ib;
2227       break;
2228   }
2229 
2230   Inst.addOperand(MCOperand::createImm(mode));
2231   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2232     return MCDisassembler::Fail;
2233 
2234   return S;
2235 }
2236 
2237 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2238                                uint64_t Address, const void *Decoder) {
2239   DecodeStatus S = MCDisassembler::Success;
2240 
2241   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2242   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2243   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2244   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2245 
2246   if (pred == 0xF)
2247     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2248 
2249   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2250     return MCDisassembler::Fail;
2251   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2252     return MCDisassembler::Fail;
2253   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2254     return MCDisassembler::Fail;
2255   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2256     return MCDisassembler::Fail;
2257   return S;
2258 }
2259 
2260 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
2261                                   unsigned Insn,
2262                                   uint64_t Address, const void *Decoder) {
2263   DecodeStatus S = MCDisassembler::Success;
2264 
2265   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2266   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2267   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2268 
2269   if (pred == 0xF) {
2270     // Ambiguous with RFE and SRS
2271     switch (Inst.getOpcode()) {
2272       case ARM::LDMDA:
2273         Inst.setOpcode(ARM::RFEDA);
2274         break;
2275       case ARM::LDMDA_UPD:
2276         Inst.setOpcode(ARM::RFEDA_UPD);
2277         break;
2278       case ARM::LDMDB:
2279         Inst.setOpcode(ARM::RFEDB);
2280         break;
2281       case ARM::LDMDB_UPD:
2282         Inst.setOpcode(ARM::RFEDB_UPD);
2283         break;
2284       case ARM::LDMIA:
2285         Inst.setOpcode(ARM::RFEIA);
2286         break;
2287       case ARM::LDMIA_UPD:
2288         Inst.setOpcode(ARM::RFEIA_UPD);
2289         break;
2290       case ARM::LDMIB:
2291         Inst.setOpcode(ARM::RFEIB);
2292         break;
2293       case ARM::LDMIB_UPD:
2294         Inst.setOpcode(ARM::RFEIB_UPD);
2295         break;
2296       case ARM::STMDA:
2297         Inst.setOpcode(ARM::SRSDA);
2298         break;
2299       case ARM::STMDA_UPD:
2300         Inst.setOpcode(ARM::SRSDA_UPD);
2301         break;
2302       case ARM::STMDB:
2303         Inst.setOpcode(ARM::SRSDB);
2304         break;
2305       case ARM::STMDB_UPD:
2306         Inst.setOpcode(ARM::SRSDB_UPD);
2307         break;
2308       case ARM::STMIA:
2309         Inst.setOpcode(ARM::SRSIA);
2310         break;
2311       case ARM::STMIA_UPD:
2312         Inst.setOpcode(ARM::SRSIA_UPD);
2313         break;
2314       case ARM::STMIB:
2315         Inst.setOpcode(ARM::SRSIB);
2316         break;
2317       case ARM::STMIB_UPD:
2318         Inst.setOpcode(ARM::SRSIB_UPD);
2319         break;
2320       default:
2321         return MCDisassembler::Fail;
2322     }
2323 
2324     // For stores (which become SRS's, the only operand is the mode.
2325     if (fieldFromInstruction(Insn, 20, 1) == 0) {
2326       // Check SRS encoding constraints
2327       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2328             fieldFromInstruction(Insn, 20, 1) == 0))
2329         return MCDisassembler::Fail;
2330 
2331       Inst.addOperand(
2332           MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2333       return S;
2334     }
2335 
2336     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2337   }
2338 
2339   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2340     return MCDisassembler::Fail;
2341   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2342     return MCDisassembler::Fail; // Tied
2343   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2344     return MCDisassembler::Fail;
2345   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2346     return MCDisassembler::Fail;
2347 
2348   return S;
2349 }
2350 
2351 // Check for UNPREDICTABLE predicated ESB instruction
2352 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2353                                  uint64_t Address, const void *Decoder) {
2354   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2355   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2356   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2357   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2358 
2359   DecodeStatus S = MCDisassembler::Success;
2360 
2361   Inst.addOperand(MCOperand::createImm(imm8));
2362 
2363   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2364     return MCDisassembler::Fail;
2365 
2366   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2367   // so all predicates should be allowed.
2368   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2369     S = MCDisassembler::SoftFail;
2370 
2371   return S;
2372 }
2373 
2374 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2375                                  uint64_t Address, const void *Decoder) {
2376   unsigned imod = fieldFromInstruction(Insn, 18, 2);
2377   unsigned M = fieldFromInstruction(Insn, 17, 1);
2378   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2379   unsigned mode = fieldFromInstruction(Insn, 0, 5);
2380 
2381   DecodeStatus S = MCDisassembler::Success;
2382 
2383   // This decoder is called from multiple location that do not check
2384   // the full encoding is valid before they do.
2385   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2386       fieldFromInstruction(Insn, 16, 1) != 0 ||
2387       fieldFromInstruction(Insn, 20, 8) != 0x10)
2388     return MCDisassembler::Fail;
2389 
2390   // imod == '01' --> UNPREDICTABLE
2391   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2392   // return failure here.  The '01' imod value is unprintable, so there's
2393   // nothing useful we could do even if we returned UNPREDICTABLE.
2394 
2395   if (imod == 1) return MCDisassembler::Fail;
2396 
2397   if (imod && M) {
2398     Inst.setOpcode(ARM::CPS3p);
2399     Inst.addOperand(MCOperand::createImm(imod));
2400     Inst.addOperand(MCOperand::createImm(iflags));
2401     Inst.addOperand(MCOperand::createImm(mode));
2402   } else if (imod && !M) {
2403     Inst.setOpcode(ARM::CPS2p);
2404     Inst.addOperand(MCOperand::createImm(imod));
2405     Inst.addOperand(MCOperand::createImm(iflags));
2406     if (mode) S = MCDisassembler::SoftFail;
2407   } else if (!imod && M) {
2408     Inst.setOpcode(ARM::CPS1p);
2409     Inst.addOperand(MCOperand::createImm(mode));
2410     if (iflags) S = MCDisassembler::SoftFail;
2411   } else {
2412     // imod == '00' && M == '0' --> UNPREDICTABLE
2413     Inst.setOpcode(ARM::CPS1p);
2414     Inst.addOperand(MCOperand::createImm(mode));
2415     S = MCDisassembler::SoftFail;
2416   }
2417 
2418   return S;
2419 }
2420 
2421 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2422                                  uint64_t Address, const void *Decoder) {
2423   unsigned imod = fieldFromInstruction(Insn, 9, 2);
2424   unsigned M = fieldFromInstruction(Insn, 8, 1);
2425   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2426   unsigned mode = fieldFromInstruction(Insn, 0, 5);
2427 
2428   DecodeStatus S = MCDisassembler::Success;
2429 
2430   // imod == '01' --> UNPREDICTABLE
2431   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2432   // return failure here.  The '01' imod value is unprintable, so there's
2433   // nothing useful we could do even if we returned UNPREDICTABLE.
2434 
2435   if (imod == 1) return MCDisassembler::Fail;
2436 
2437   if (imod && M) {
2438     Inst.setOpcode(ARM::t2CPS3p);
2439     Inst.addOperand(MCOperand::createImm(imod));
2440     Inst.addOperand(MCOperand::createImm(iflags));
2441     Inst.addOperand(MCOperand::createImm(mode));
2442   } else if (imod && !M) {
2443     Inst.setOpcode(ARM::t2CPS2p);
2444     Inst.addOperand(MCOperand::createImm(imod));
2445     Inst.addOperand(MCOperand::createImm(iflags));
2446     if (mode) S = MCDisassembler::SoftFail;
2447   } else if (!imod && M) {
2448     Inst.setOpcode(ARM::t2CPS1p);
2449     Inst.addOperand(MCOperand::createImm(mode));
2450     if (iflags) S = MCDisassembler::SoftFail;
2451   } else {
2452     // imod == '00' && M == '0' --> this is a HINT instruction
2453     int imm = fieldFromInstruction(Insn, 0, 8);
2454     // HINT are defined only for immediate in [0..4]
2455     if(imm > 4) return MCDisassembler::Fail;
2456     Inst.setOpcode(ARM::t2HINT);
2457     Inst.addOperand(MCOperand::createImm(imm));
2458   }
2459 
2460   return S;
2461 }
2462 
2463 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
2464                                                  uint64_t Address,
2465                                                  const void *Decoder) {
2466   unsigned imm = fieldFromInstruction(Insn, 0, 8);
2467 
2468   unsigned Opcode = ARM::t2HINT;
2469 
2470   if (imm == 0x0D) {
2471     Opcode = ARM::t2PACBTI;
2472   } else if (imm == 0x1D) {
2473     Opcode = ARM::t2PAC;
2474   } else if (imm == 0x2D) {
2475     Opcode = ARM::t2AUT;
2476   } else if (imm == 0x0F) {
2477     Opcode = ARM::t2BTI;
2478   }
2479 
2480   Inst.setOpcode(Opcode);
2481   if (Opcode == ARM::t2HINT) {
2482     Inst.addOperand(MCOperand::createImm(imm));
2483   }
2484 
2485   return MCDisassembler::Success;
2486 }
2487 
2488 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2489                                  uint64_t Address, const void *Decoder) {
2490   DecodeStatus S = MCDisassembler::Success;
2491 
2492   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2493   unsigned imm = 0;
2494 
2495   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2496   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2497   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2498   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2499 
2500   if (Inst.getOpcode() == ARM::t2MOVTi16)
2501     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2502       return MCDisassembler::Fail;
2503   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2504     return MCDisassembler::Fail;
2505 
2506   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2507     Inst.addOperand(MCOperand::createImm(imm));
2508 
2509   return S;
2510 }
2511 
2512 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2513                                  uint64_t Address, const void *Decoder) {
2514   DecodeStatus S = MCDisassembler::Success;
2515 
2516   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2517   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2518   unsigned imm = 0;
2519 
2520   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2521   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2522 
2523   if (Inst.getOpcode() == ARM::MOVTi16)
2524     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2525       return MCDisassembler::Fail;
2526 
2527   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2528     return MCDisassembler::Fail;
2529 
2530   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2531     Inst.addOperand(MCOperand::createImm(imm));
2532 
2533   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2534     return MCDisassembler::Fail;
2535 
2536   return S;
2537 }
2538 
2539 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2540                                  uint64_t Address, const void *Decoder) {
2541   DecodeStatus S = MCDisassembler::Success;
2542 
2543   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2544   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2545   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2546   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2547   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2548 
2549   if (pred == 0xF)
2550     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2551 
2552   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2553     return MCDisassembler::Fail;
2554   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2555     return MCDisassembler::Fail;
2556   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2557     return MCDisassembler::Fail;
2558   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2559     return MCDisassembler::Fail;
2560 
2561   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2562     return MCDisassembler::Fail;
2563 
2564   return S;
2565 }
2566 
2567 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2568                                   uint64_t Address, const void *Decoder) {
2569   DecodeStatus S = MCDisassembler::Success;
2570 
2571   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2572   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2573   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2574 
2575   if (Pred == 0xF)
2576     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2577 
2578   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2579     return MCDisassembler::Fail;
2580   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2581     return MCDisassembler::Fail;
2582   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2583     return MCDisassembler::Fail;
2584 
2585   return S;
2586 }
2587 
2588 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2589                                   uint64_t Address, const void *Decoder) {
2590   DecodeStatus S = MCDisassembler::Success;
2591 
2592   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2593 
2594   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2595   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2596 
2597   if (!FeatureBits[ARM::HasV8_1aOps] ||
2598       !FeatureBits[ARM::HasV8Ops])
2599     return MCDisassembler::Fail;
2600 
2601   // Decoder can be called from DecodeTST, which does not check the full
2602   // encoding is valid.
2603   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2604       fieldFromInstruction(Insn, 4,4) != 0)
2605     return MCDisassembler::Fail;
2606   if (fieldFromInstruction(Insn, 10,10) != 0 ||
2607       fieldFromInstruction(Insn, 0,4) != 0)
2608     S = MCDisassembler::SoftFail;
2609 
2610   Inst.setOpcode(ARM::SETPAN);
2611   Inst.addOperand(MCOperand::createImm(Imm));
2612 
2613   return S;
2614 }
2615 
2616 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2617                            uint64_t Address, const void *Decoder) {
2618   DecodeStatus S = MCDisassembler::Success;
2619 
2620   unsigned add = fieldFromInstruction(Val, 12, 1);
2621   unsigned imm = fieldFromInstruction(Val, 0, 12);
2622   unsigned Rn = fieldFromInstruction(Val, 13, 4);
2623 
2624   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2625     return MCDisassembler::Fail;
2626 
2627   if (!add) imm *= -1;
2628   if (imm == 0 && !add) imm = INT32_MIN;
2629   Inst.addOperand(MCOperand::createImm(imm));
2630   if (Rn == 15)
2631     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2632 
2633   return S;
2634 }
2635 
2636 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2637                                    uint64_t Address, const void *Decoder) {
2638   DecodeStatus S = MCDisassembler::Success;
2639 
2640   unsigned Rn = fieldFromInstruction(Val, 9, 4);
2641   // U == 1 to add imm, 0 to subtract it.
2642   unsigned U = fieldFromInstruction(Val, 8, 1);
2643   unsigned imm = fieldFromInstruction(Val, 0, 8);
2644 
2645   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2646     return MCDisassembler::Fail;
2647 
2648   if (U)
2649     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2650   else
2651     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2652 
2653   return S;
2654 }
2655 
2656 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2657                                    uint64_t Address, const void *Decoder) {
2658   DecodeStatus S = MCDisassembler::Success;
2659 
2660   unsigned Rn = fieldFromInstruction(Val, 9, 4);
2661   // U == 1 to add imm, 0 to subtract it.
2662   unsigned U = fieldFromInstruction(Val, 8, 1);
2663   unsigned imm = fieldFromInstruction(Val, 0, 8);
2664 
2665   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2666     return MCDisassembler::Fail;
2667 
2668   if (U)
2669     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2670   else
2671     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2672 
2673   return S;
2674 }
2675 
2676 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2677                                    uint64_t Address, const void *Decoder) {
2678   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2679 }
2680 
2681 static DecodeStatus
2682 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2683                      uint64_t Address, const void *Decoder) {
2684   DecodeStatus Status = MCDisassembler::Success;
2685 
2686   // Note the J1 and J2 values are from the encoded instruction.  So here
2687   // change them to I1 and I2 values via as documented:
2688   // I1 = NOT(J1 EOR S);
2689   // I2 = NOT(J2 EOR S);
2690   // and build the imm32 with one trailing zero as documented:
2691   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2692   unsigned S = fieldFromInstruction(Insn, 26, 1);
2693   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2694   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2695   unsigned I1 = !(J1 ^ S);
2696   unsigned I2 = !(J2 ^ S);
2697   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2698   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2699   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2700   int imm32 = SignExtend32<25>(tmp << 1);
2701   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2702                                 true, 4, Inst, Decoder))
2703     Inst.addOperand(MCOperand::createImm(imm32));
2704 
2705   return Status;
2706 }
2707 
2708 static DecodeStatus
2709 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2710                            uint64_t Address, const void *Decoder) {
2711   DecodeStatus S = MCDisassembler::Success;
2712 
2713   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2714   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2715 
2716   if (pred == 0xF) {
2717     Inst.setOpcode(ARM::BLXi);
2718     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2719     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2720                                   true, 4, Inst, Decoder))
2721     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2722     return S;
2723   }
2724 
2725   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2726                                 true, 4, Inst, Decoder))
2727     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2728 
2729   // We already have BL_pred for BL w/ predicate, no need to add addition
2730   // predicate opreands for BL
2731   if (Inst.getOpcode() != ARM::BL)
2732     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2733       return MCDisassembler::Fail;
2734 
2735   return S;
2736 }
2737 
2738 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2739                                    uint64_t Address, const void *Decoder) {
2740   DecodeStatus S = MCDisassembler::Success;
2741 
2742   unsigned Rm = fieldFromInstruction(Val, 0, 4);
2743   unsigned align = fieldFromInstruction(Val, 4, 2);
2744 
2745   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2746     return MCDisassembler::Fail;
2747   if (!align)
2748     Inst.addOperand(MCOperand::createImm(0));
2749   else
2750     Inst.addOperand(MCOperand::createImm(4 << align));
2751 
2752   return S;
2753 }
2754 
2755 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2756                                    uint64_t Address, const void *Decoder) {
2757   DecodeStatus S = MCDisassembler::Success;
2758 
2759   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2760   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2761   unsigned wb = fieldFromInstruction(Insn, 16, 4);
2762   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2763   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2764   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2765 
2766   // First output register
2767   switch (Inst.getOpcode()) {
2768   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2769   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2770   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2771   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2772   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2773   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2774   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2775   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2776   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2777     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2778       return MCDisassembler::Fail;
2779     break;
2780   case ARM::VLD2b16:
2781   case ARM::VLD2b32:
2782   case ARM::VLD2b8:
2783   case ARM::VLD2b16wb_fixed:
2784   case ARM::VLD2b16wb_register:
2785   case ARM::VLD2b32wb_fixed:
2786   case ARM::VLD2b32wb_register:
2787   case ARM::VLD2b8wb_fixed:
2788   case ARM::VLD2b8wb_register:
2789     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2790       return MCDisassembler::Fail;
2791     break;
2792   default:
2793     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2794       return MCDisassembler::Fail;
2795   }
2796 
2797   // Second output register
2798   switch (Inst.getOpcode()) {
2799     case ARM::VLD3d8:
2800     case ARM::VLD3d16:
2801     case ARM::VLD3d32:
2802     case ARM::VLD3d8_UPD:
2803     case ARM::VLD3d16_UPD:
2804     case ARM::VLD3d32_UPD:
2805     case ARM::VLD4d8:
2806     case ARM::VLD4d16:
2807     case ARM::VLD4d32:
2808     case ARM::VLD4d8_UPD:
2809     case ARM::VLD4d16_UPD:
2810     case ARM::VLD4d32_UPD:
2811       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2812         return MCDisassembler::Fail;
2813       break;
2814     case ARM::VLD3q8:
2815     case ARM::VLD3q16:
2816     case ARM::VLD3q32:
2817     case ARM::VLD3q8_UPD:
2818     case ARM::VLD3q16_UPD:
2819     case ARM::VLD3q32_UPD:
2820     case ARM::VLD4q8:
2821     case ARM::VLD4q16:
2822     case ARM::VLD4q32:
2823     case ARM::VLD4q8_UPD:
2824     case ARM::VLD4q16_UPD:
2825     case ARM::VLD4q32_UPD:
2826       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2827         return MCDisassembler::Fail;
2828       break;
2829     default:
2830       break;
2831   }
2832 
2833   // Third output register
2834   switch(Inst.getOpcode()) {
2835     case ARM::VLD3d8:
2836     case ARM::VLD3d16:
2837     case ARM::VLD3d32:
2838     case ARM::VLD3d8_UPD:
2839     case ARM::VLD3d16_UPD:
2840     case ARM::VLD3d32_UPD:
2841     case ARM::VLD4d8:
2842     case ARM::VLD4d16:
2843     case ARM::VLD4d32:
2844     case ARM::VLD4d8_UPD:
2845     case ARM::VLD4d16_UPD:
2846     case ARM::VLD4d32_UPD:
2847       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2848         return MCDisassembler::Fail;
2849       break;
2850     case ARM::VLD3q8:
2851     case ARM::VLD3q16:
2852     case ARM::VLD3q32:
2853     case ARM::VLD3q8_UPD:
2854     case ARM::VLD3q16_UPD:
2855     case ARM::VLD3q32_UPD:
2856     case ARM::VLD4q8:
2857     case ARM::VLD4q16:
2858     case ARM::VLD4q32:
2859     case ARM::VLD4q8_UPD:
2860     case ARM::VLD4q16_UPD:
2861     case ARM::VLD4q32_UPD:
2862       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2863         return MCDisassembler::Fail;
2864       break;
2865     default:
2866       break;
2867   }
2868 
2869   // Fourth output register
2870   switch (Inst.getOpcode()) {
2871     case ARM::VLD4d8:
2872     case ARM::VLD4d16:
2873     case ARM::VLD4d32:
2874     case ARM::VLD4d8_UPD:
2875     case ARM::VLD4d16_UPD:
2876     case ARM::VLD4d32_UPD:
2877       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2878         return MCDisassembler::Fail;
2879       break;
2880     case ARM::VLD4q8:
2881     case ARM::VLD4q16:
2882     case ARM::VLD4q32:
2883     case ARM::VLD4q8_UPD:
2884     case ARM::VLD4q16_UPD:
2885     case ARM::VLD4q32_UPD:
2886       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2887         return MCDisassembler::Fail;
2888       break;
2889     default:
2890       break;
2891   }
2892 
2893   // Writeback operand
2894   switch (Inst.getOpcode()) {
2895     case ARM::VLD1d8wb_fixed:
2896     case ARM::VLD1d16wb_fixed:
2897     case ARM::VLD1d32wb_fixed:
2898     case ARM::VLD1d64wb_fixed:
2899     case ARM::VLD1d8wb_register:
2900     case ARM::VLD1d16wb_register:
2901     case ARM::VLD1d32wb_register:
2902     case ARM::VLD1d64wb_register:
2903     case ARM::VLD1q8wb_fixed:
2904     case ARM::VLD1q16wb_fixed:
2905     case ARM::VLD1q32wb_fixed:
2906     case ARM::VLD1q64wb_fixed:
2907     case ARM::VLD1q8wb_register:
2908     case ARM::VLD1q16wb_register:
2909     case ARM::VLD1q32wb_register:
2910     case ARM::VLD1q64wb_register:
2911     case ARM::VLD1d8Twb_fixed:
2912     case ARM::VLD1d8Twb_register:
2913     case ARM::VLD1d16Twb_fixed:
2914     case ARM::VLD1d16Twb_register:
2915     case ARM::VLD1d32Twb_fixed:
2916     case ARM::VLD1d32Twb_register:
2917     case ARM::VLD1d64Twb_fixed:
2918     case ARM::VLD1d64Twb_register:
2919     case ARM::VLD1d8Qwb_fixed:
2920     case ARM::VLD1d8Qwb_register:
2921     case ARM::VLD1d16Qwb_fixed:
2922     case ARM::VLD1d16Qwb_register:
2923     case ARM::VLD1d32Qwb_fixed:
2924     case ARM::VLD1d32Qwb_register:
2925     case ARM::VLD1d64Qwb_fixed:
2926     case ARM::VLD1d64Qwb_register:
2927     case ARM::VLD2d8wb_fixed:
2928     case ARM::VLD2d16wb_fixed:
2929     case ARM::VLD2d32wb_fixed:
2930     case ARM::VLD2q8wb_fixed:
2931     case ARM::VLD2q16wb_fixed:
2932     case ARM::VLD2q32wb_fixed:
2933     case ARM::VLD2d8wb_register:
2934     case ARM::VLD2d16wb_register:
2935     case ARM::VLD2d32wb_register:
2936     case ARM::VLD2q8wb_register:
2937     case ARM::VLD2q16wb_register:
2938     case ARM::VLD2q32wb_register:
2939     case ARM::VLD2b8wb_fixed:
2940     case ARM::VLD2b16wb_fixed:
2941     case ARM::VLD2b32wb_fixed:
2942     case ARM::VLD2b8wb_register:
2943     case ARM::VLD2b16wb_register:
2944     case ARM::VLD2b32wb_register:
2945       Inst.addOperand(MCOperand::createImm(0));
2946       break;
2947     case ARM::VLD3d8_UPD:
2948     case ARM::VLD3d16_UPD:
2949     case ARM::VLD3d32_UPD:
2950     case ARM::VLD3q8_UPD:
2951     case ARM::VLD3q16_UPD:
2952     case ARM::VLD3q32_UPD:
2953     case ARM::VLD4d8_UPD:
2954     case ARM::VLD4d16_UPD:
2955     case ARM::VLD4d32_UPD:
2956     case ARM::VLD4q8_UPD:
2957     case ARM::VLD4q16_UPD:
2958     case ARM::VLD4q32_UPD:
2959       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2960         return MCDisassembler::Fail;
2961       break;
2962     default:
2963       break;
2964   }
2965 
2966   // AddrMode6 Base (register+alignment)
2967   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2968     return MCDisassembler::Fail;
2969 
2970   // AddrMode6 Offset (register)
2971   switch (Inst.getOpcode()) {
2972   default:
2973     // The below have been updated to have explicit am6offset split
2974     // between fixed and register offset. For those instructions not
2975     // yet updated, we need to add an additional reg0 operand for the
2976     // fixed variant.
2977     //
2978     // The fixed offset encodes as Rm == 0xd, so we check for that.
2979     if (Rm == 0xd) {
2980       Inst.addOperand(MCOperand::createReg(0));
2981       break;
2982     }
2983     // Fall through to handle the register offset variant.
2984     LLVM_FALLTHROUGH;
2985   case ARM::VLD1d8wb_fixed:
2986   case ARM::VLD1d16wb_fixed:
2987   case ARM::VLD1d32wb_fixed:
2988   case ARM::VLD1d64wb_fixed:
2989   case ARM::VLD1d8Twb_fixed:
2990   case ARM::VLD1d16Twb_fixed:
2991   case ARM::VLD1d32Twb_fixed:
2992   case ARM::VLD1d64Twb_fixed:
2993   case ARM::VLD1d8Qwb_fixed:
2994   case ARM::VLD1d16Qwb_fixed:
2995   case ARM::VLD1d32Qwb_fixed:
2996   case ARM::VLD1d64Qwb_fixed:
2997   case ARM::VLD1d8wb_register:
2998   case ARM::VLD1d16wb_register:
2999   case ARM::VLD1d32wb_register:
3000   case ARM::VLD1d64wb_register:
3001   case ARM::VLD1q8wb_fixed:
3002   case ARM::VLD1q16wb_fixed:
3003   case ARM::VLD1q32wb_fixed:
3004   case ARM::VLD1q64wb_fixed:
3005   case ARM::VLD1q8wb_register:
3006   case ARM::VLD1q16wb_register:
3007   case ARM::VLD1q32wb_register:
3008   case ARM::VLD1q64wb_register:
3009     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3010     // variant encodes Rm == 0xf. Anything else is a register offset post-
3011     // increment and we need to add the register operand to the instruction.
3012     if (Rm != 0xD && Rm != 0xF &&
3013         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3014       return MCDisassembler::Fail;
3015     break;
3016   case ARM::VLD2d8wb_fixed:
3017   case ARM::VLD2d16wb_fixed:
3018   case ARM::VLD2d32wb_fixed:
3019   case ARM::VLD2b8wb_fixed:
3020   case ARM::VLD2b16wb_fixed:
3021   case ARM::VLD2b32wb_fixed:
3022   case ARM::VLD2q8wb_fixed:
3023   case ARM::VLD2q16wb_fixed:
3024   case ARM::VLD2q32wb_fixed:
3025     break;
3026   }
3027 
3028   return S;
3029 }
3030 
3031 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
3032                                    uint64_t Address, const void *Decoder) {
3033   unsigned type = fieldFromInstruction(Insn, 8, 4);
3034   unsigned align = fieldFromInstruction(Insn, 4, 2);
3035   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
3036   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
3037   if (type == 10 && align == 3) return MCDisassembler::Fail;
3038 
3039   unsigned load = fieldFromInstruction(Insn, 21, 1);
3040   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3041               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3042 }
3043 
3044 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
3045                                    uint64_t Address, const void *Decoder) {
3046   unsigned size = fieldFromInstruction(Insn, 6, 2);
3047   if (size == 3) return MCDisassembler::Fail;
3048 
3049   unsigned type = fieldFromInstruction(Insn, 8, 4);
3050   unsigned align = fieldFromInstruction(Insn, 4, 2);
3051   if (type == 8 && align == 3) return MCDisassembler::Fail;
3052   if (type == 9 && align == 3) return MCDisassembler::Fail;
3053 
3054   unsigned load = fieldFromInstruction(Insn, 21, 1);
3055   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3056               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3057 }
3058 
3059 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3060                                    uint64_t Address, const void *Decoder) {
3061   unsigned size = fieldFromInstruction(Insn, 6, 2);
3062   if (size == 3) return MCDisassembler::Fail;
3063 
3064   unsigned align = fieldFromInstruction(Insn, 4, 2);
3065   if (align & 2) return MCDisassembler::Fail;
3066 
3067   unsigned load = fieldFromInstruction(Insn, 21, 1);
3068   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3069               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3070 }
3071 
3072 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3073                                    uint64_t Address, const void *Decoder) {
3074   unsigned size = fieldFromInstruction(Insn, 6, 2);
3075   if (size == 3) return MCDisassembler::Fail;
3076 
3077   unsigned load = fieldFromInstruction(Insn, 21, 1);
3078   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3079               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3080 }
3081 
3082 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3083                                  uint64_t Address, const void *Decoder) {
3084   DecodeStatus S = MCDisassembler::Success;
3085 
3086   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3087   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3088   unsigned wb = fieldFromInstruction(Insn, 16, 4);
3089   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3090   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3091   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3092 
3093   // Writeback Operand
3094   switch (Inst.getOpcode()) {
3095     case ARM::VST1d8wb_fixed:
3096     case ARM::VST1d16wb_fixed:
3097     case ARM::VST1d32wb_fixed:
3098     case ARM::VST1d64wb_fixed:
3099     case ARM::VST1d8wb_register:
3100     case ARM::VST1d16wb_register:
3101     case ARM::VST1d32wb_register:
3102     case ARM::VST1d64wb_register:
3103     case ARM::VST1q8wb_fixed:
3104     case ARM::VST1q16wb_fixed:
3105     case ARM::VST1q32wb_fixed:
3106     case ARM::VST1q64wb_fixed:
3107     case ARM::VST1q8wb_register:
3108     case ARM::VST1q16wb_register:
3109     case ARM::VST1q32wb_register:
3110     case ARM::VST1q64wb_register:
3111     case ARM::VST1d8Twb_fixed:
3112     case ARM::VST1d16Twb_fixed:
3113     case ARM::VST1d32Twb_fixed:
3114     case ARM::VST1d64Twb_fixed:
3115     case ARM::VST1d8Twb_register:
3116     case ARM::VST1d16Twb_register:
3117     case ARM::VST1d32Twb_register:
3118     case ARM::VST1d64Twb_register:
3119     case ARM::VST1d8Qwb_fixed:
3120     case ARM::VST1d16Qwb_fixed:
3121     case ARM::VST1d32Qwb_fixed:
3122     case ARM::VST1d64Qwb_fixed:
3123     case ARM::VST1d8Qwb_register:
3124     case ARM::VST1d16Qwb_register:
3125     case ARM::VST1d32Qwb_register:
3126     case ARM::VST1d64Qwb_register:
3127     case ARM::VST2d8wb_fixed:
3128     case ARM::VST2d16wb_fixed:
3129     case ARM::VST2d32wb_fixed:
3130     case ARM::VST2d8wb_register:
3131     case ARM::VST2d16wb_register:
3132     case ARM::VST2d32wb_register:
3133     case ARM::VST2q8wb_fixed:
3134     case ARM::VST2q16wb_fixed:
3135     case ARM::VST2q32wb_fixed:
3136     case ARM::VST2q8wb_register:
3137     case ARM::VST2q16wb_register:
3138     case ARM::VST2q32wb_register:
3139     case ARM::VST2b8wb_fixed:
3140     case ARM::VST2b16wb_fixed:
3141     case ARM::VST2b32wb_fixed:
3142     case ARM::VST2b8wb_register:
3143     case ARM::VST2b16wb_register:
3144     case ARM::VST2b32wb_register:
3145       if (Rm == 0xF)
3146         return MCDisassembler::Fail;
3147       Inst.addOperand(MCOperand::createImm(0));
3148       break;
3149     case ARM::VST3d8_UPD:
3150     case ARM::VST3d16_UPD:
3151     case ARM::VST3d32_UPD:
3152     case ARM::VST3q8_UPD:
3153     case ARM::VST3q16_UPD:
3154     case ARM::VST3q32_UPD:
3155     case ARM::VST4d8_UPD:
3156     case ARM::VST4d16_UPD:
3157     case ARM::VST4d32_UPD:
3158     case ARM::VST4q8_UPD:
3159     case ARM::VST4q16_UPD:
3160     case ARM::VST4q32_UPD:
3161       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3162         return MCDisassembler::Fail;
3163       break;
3164     default:
3165       break;
3166   }
3167 
3168   // AddrMode6 Base (register+alignment)
3169   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3170     return MCDisassembler::Fail;
3171 
3172   // AddrMode6 Offset (register)
3173   switch (Inst.getOpcode()) {
3174     default:
3175       if (Rm == 0xD)
3176         Inst.addOperand(MCOperand::createReg(0));
3177       else if (Rm != 0xF) {
3178         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3179           return MCDisassembler::Fail;
3180       }
3181       break;
3182     case ARM::VST1d8wb_fixed:
3183     case ARM::VST1d16wb_fixed:
3184     case ARM::VST1d32wb_fixed:
3185     case ARM::VST1d64wb_fixed:
3186     case ARM::VST1q8wb_fixed:
3187     case ARM::VST1q16wb_fixed:
3188     case ARM::VST1q32wb_fixed:
3189     case ARM::VST1q64wb_fixed:
3190     case ARM::VST1d8Twb_fixed:
3191     case ARM::VST1d16Twb_fixed:
3192     case ARM::VST1d32Twb_fixed:
3193     case ARM::VST1d64Twb_fixed:
3194     case ARM::VST1d8Qwb_fixed:
3195     case ARM::VST1d16Qwb_fixed:
3196     case ARM::VST1d32Qwb_fixed:
3197     case ARM::VST1d64Qwb_fixed:
3198     case ARM::VST2d8wb_fixed:
3199     case ARM::VST2d16wb_fixed:
3200     case ARM::VST2d32wb_fixed:
3201     case ARM::VST2q8wb_fixed:
3202     case ARM::VST2q16wb_fixed:
3203     case ARM::VST2q32wb_fixed:
3204     case ARM::VST2b8wb_fixed:
3205     case ARM::VST2b16wb_fixed:
3206     case ARM::VST2b32wb_fixed:
3207       break;
3208   }
3209 
3210   // First input register
3211   switch (Inst.getOpcode()) {
3212   case ARM::VST1q16:
3213   case ARM::VST1q32:
3214   case ARM::VST1q64:
3215   case ARM::VST1q8:
3216   case ARM::VST1q16wb_fixed:
3217   case ARM::VST1q16wb_register:
3218   case ARM::VST1q32wb_fixed:
3219   case ARM::VST1q32wb_register:
3220   case ARM::VST1q64wb_fixed:
3221   case ARM::VST1q64wb_register:
3222   case ARM::VST1q8wb_fixed:
3223   case ARM::VST1q8wb_register:
3224   case ARM::VST2d16:
3225   case ARM::VST2d32:
3226   case ARM::VST2d8:
3227   case ARM::VST2d16wb_fixed:
3228   case ARM::VST2d16wb_register:
3229   case ARM::VST2d32wb_fixed:
3230   case ARM::VST2d32wb_register:
3231   case ARM::VST2d8wb_fixed:
3232   case ARM::VST2d8wb_register:
3233     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3234       return MCDisassembler::Fail;
3235     break;
3236   case ARM::VST2b16:
3237   case ARM::VST2b32:
3238   case ARM::VST2b8:
3239   case ARM::VST2b16wb_fixed:
3240   case ARM::VST2b16wb_register:
3241   case ARM::VST2b32wb_fixed:
3242   case ARM::VST2b32wb_register:
3243   case ARM::VST2b8wb_fixed:
3244   case ARM::VST2b8wb_register:
3245     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3246       return MCDisassembler::Fail;
3247     break;
3248   default:
3249     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3250       return MCDisassembler::Fail;
3251   }
3252 
3253   // Second input register
3254   switch (Inst.getOpcode()) {
3255     case ARM::VST3d8:
3256     case ARM::VST3d16:
3257     case ARM::VST3d32:
3258     case ARM::VST3d8_UPD:
3259     case ARM::VST3d16_UPD:
3260     case ARM::VST3d32_UPD:
3261     case ARM::VST4d8:
3262     case ARM::VST4d16:
3263     case ARM::VST4d32:
3264     case ARM::VST4d8_UPD:
3265     case ARM::VST4d16_UPD:
3266     case ARM::VST4d32_UPD:
3267       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3268         return MCDisassembler::Fail;
3269       break;
3270     case ARM::VST3q8:
3271     case ARM::VST3q16:
3272     case ARM::VST3q32:
3273     case ARM::VST3q8_UPD:
3274     case ARM::VST3q16_UPD:
3275     case ARM::VST3q32_UPD:
3276     case ARM::VST4q8:
3277     case ARM::VST4q16:
3278     case ARM::VST4q32:
3279     case ARM::VST4q8_UPD:
3280     case ARM::VST4q16_UPD:
3281     case ARM::VST4q32_UPD:
3282       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3283         return MCDisassembler::Fail;
3284       break;
3285     default:
3286       break;
3287   }
3288 
3289   // Third input register
3290   switch (Inst.getOpcode()) {
3291     case ARM::VST3d8:
3292     case ARM::VST3d16:
3293     case ARM::VST3d32:
3294     case ARM::VST3d8_UPD:
3295     case ARM::VST3d16_UPD:
3296     case ARM::VST3d32_UPD:
3297     case ARM::VST4d8:
3298     case ARM::VST4d16:
3299     case ARM::VST4d32:
3300     case ARM::VST4d8_UPD:
3301     case ARM::VST4d16_UPD:
3302     case ARM::VST4d32_UPD:
3303       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3304         return MCDisassembler::Fail;
3305       break;
3306     case ARM::VST3q8:
3307     case ARM::VST3q16:
3308     case ARM::VST3q32:
3309     case ARM::VST3q8_UPD:
3310     case ARM::VST3q16_UPD:
3311     case ARM::VST3q32_UPD:
3312     case ARM::VST4q8:
3313     case ARM::VST4q16:
3314     case ARM::VST4q32:
3315     case ARM::VST4q8_UPD:
3316     case ARM::VST4q16_UPD:
3317     case ARM::VST4q32_UPD:
3318       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3319         return MCDisassembler::Fail;
3320       break;
3321     default:
3322       break;
3323   }
3324 
3325   // Fourth input register
3326   switch (Inst.getOpcode()) {
3327     case ARM::VST4d8:
3328     case ARM::VST4d16:
3329     case ARM::VST4d32:
3330     case ARM::VST4d8_UPD:
3331     case ARM::VST4d16_UPD:
3332     case ARM::VST4d32_UPD:
3333       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3334         return MCDisassembler::Fail;
3335       break;
3336     case ARM::VST4q8:
3337     case ARM::VST4q16:
3338     case ARM::VST4q32:
3339     case ARM::VST4q8_UPD:
3340     case ARM::VST4q16_UPD:
3341     case ARM::VST4q32_UPD:
3342       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3343         return MCDisassembler::Fail;
3344       break;
3345     default:
3346       break;
3347   }
3348 
3349   return S;
3350 }
3351 
3352 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3353                                     uint64_t Address, const void *Decoder) {
3354   DecodeStatus S = MCDisassembler::Success;
3355 
3356   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3357   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3358   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3359   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3360   unsigned align = fieldFromInstruction(Insn, 4, 1);
3361   unsigned size = fieldFromInstruction(Insn, 6, 2);
3362 
3363   if (size == 0 && align == 1)
3364     return MCDisassembler::Fail;
3365   align *= (1 << size);
3366 
3367   switch (Inst.getOpcode()) {
3368   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3369   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3370   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3371   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3372     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3373       return MCDisassembler::Fail;
3374     break;
3375   default:
3376     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3377       return MCDisassembler::Fail;
3378     break;
3379   }
3380   if (Rm != 0xF) {
3381     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3382       return MCDisassembler::Fail;
3383   }
3384 
3385   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3386     return MCDisassembler::Fail;
3387   Inst.addOperand(MCOperand::createImm(align));
3388 
3389   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3390   // variant encodes Rm == 0xf. Anything else is a register offset post-
3391   // increment and we need to add the register operand to the instruction.
3392   if (Rm != 0xD && Rm != 0xF &&
3393       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3394     return MCDisassembler::Fail;
3395 
3396   return S;
3397 }
3398 
3399 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3400                                     uint64_t Address, const void *Decoder) {
3401   DecodeStatus S = MCDisassembler::Success;
3402 
3403   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3404   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3405   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3406   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3407   unsigned align = fieldFromInstruction(Insn, 4, 1);
3408   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3409   align *= 2*size;
3410 
3411   switch (Inst.getOpcode()) {
3412   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3413   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3414   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3415   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3416     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3417       return MCDisassembler::Fail;
3418     break;
3419   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3420   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3421   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3422   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3423     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3424       return MCDisassembler::Fail;
3425     break;
3426   default:
3427     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3428       return MCDisassembler::Fail;
3429     break;
3430   }
3431 
3432   if (Rm != 0xF)
3433     Inst.addOperand(MCOperand::createImm(0));
3434 
3435   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3436     return MCDisassembler::Fail;
3437   Inst.addOperand(MCOperand::createImm(align));
3438 
3439   if (Rm != 0xD && Rm != 0xF) {
3440     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3441       return MCDisassembler::Fail;
3442   }
3443 
3444   return S;
3445 }
3446 
3447 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3448                                     uint64_t Address, const void *Decoder) {
3449   DecodeStatus S = MCDisassembler::Success;
3450 
3451   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3452   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3453   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3454   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3455   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3456 
3457   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3458     return MCDisassembler::Fail;
3459   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3460     return MCDisassembler::Fail;
3461   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3462     return MCDisassembler::Fail;
3463   if (Rm != 0xF) {
3464     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3465       return MCDisassembler::Fail;
3466   }
3467 
3468   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3469     return MCDisassembler::Fail;
3470   Inst.addOperand(MCOperand::createImm(0));
3471 
3472   if (Rm == 0xD)
3473     Inst.addOperand(MCOperand::createReg(0));
3474   else if (Rm != 0xF) {
3475     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3476       return MCDisassembler::Fail;
3477   }
3478 
3479   return S;
3480 }
3481 
3482 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3483                                     uint64_t Address, const void *Decoder) {
3484   DecodeStatus S = MCDisassembler::Success;
3485 
3486   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3487   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3488   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3489   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3490   unsigned size = fieldFromInstruction(Insn, 6, 2);
3491   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3492   unsigned align = fieldFromInstruction(Insn, 4, 1);
3493 
3494   if (size == 0x3) {
3495     if (align == 0)
3496       return MCDisassembler::Fail;
3497     align = 16;
3498   } else {
3499     if (size == 2) {
3500       align *= 8;
3501     } else {
3502       size = 1 << size;
3503       align *= 4*size;
3504     }
3505   }
3506 
3507   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3508     return MCDisassembler::Fail;
3509   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3510     return MCDisassembler::Fail;
3511   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3512     return MCDisassembler::Fail;
3513   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3514     return MCDisassembler::Fail;
3515   if (Rm != 0xF) {
3516     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3517       return MCDisassembler::Fail;
3518   }
3519 
3520   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3521     return MCDisassembler::Fail;
3522   Inst.addOperand(MCOperand::createImm(align));
3523 
3524   if (Rm == 0xD)
3525     Inst.addOperand(MCOperand::createReg(0));
3526   else if (Rm != 0xF) {
3527     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3528       return MCDisassembler::Fail;
3529   }
3530 
3531   return S;
3532 }
3533 
3534 static DecodeStatus
3535 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3536                             uint64_t Address, const void *Decoder) {
3537   DecodeStatus S = MCDisassembler::Success;
3538 
3539   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3540   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3541   unsigned imm = fieldFromInstruction(Insn, 0, 4);
3542   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3543   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3544   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3545   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3546   unsigned Q = fieldFromInstruction(Insn, 6, 1);
3547 
3548   if (Q) {
3549     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3550     return MCDisassembler::Fail;
3551   } else {
3552     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3553     return MCDisassembler::Fail;
3554   }
3555 
3556   Inst.addOperand(MCOperand::createImm(imm));
3557 
3558   switch (Inst.getOpcode()) {
3559     case ARM::VORRiv4i16:
3560     case ARM::VORRiv2i32:
3561     case ARM::VBICiv4i16:
3562     case ARM::VBICiv2i32:
3563       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3564         return MCDisassembler::Fail;
3565       break;
3566     case ARM::VORRiv8i16:
3567     case ARM::VORRiv4i32:
3568     case ARM::VBICiv8i16:
3569     case ARM::VBICiv4i32:
3570       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3571         return MCDisassembler::Fail;
3572       break;
3573     default:
3574       break;
3575   }
3576 
3577   return S;
3578 }
3579 
3580 static DecodeStatus
3581 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3582                            uint64_t Address, const void *Decoder) {
3583   DecodeStatus S = MCDisassembler::Success;
3584 
3585   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3586                  fieldFromInstruction(Insn, 13, 3));
3587   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3588   unsigned imm = fieldFromInstruction(Insn, 0, 4);
3589   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3590   imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3591   imm |= cmode                             << 8;
3592   imm |= fieldFromInstruction(Insn, 5, 1)  << 12;
3593 
3594   if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3595     return MCDisassembler::Fail;
3596 
3597   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3598     return MCDisassembler::Fail;
3599 
3600   Inst.addOperand(MCOperand::createImm(imm));
3601 
3602   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3603   Inst.addOperand(MCOperand::createReg(0));
3604   Inst.addOperand(MCOperand::createImm(0));
3605 
3606   return S;
3607 }
3608 
3609 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3610                                uint64_t Address, const void *Decoder) {
3611   DecodeStatus S = MCDisassembler::Success;
3612 
3613   unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3614   Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3615   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3616     return MCDisassembler::Fail;
3617   Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3618 
3619   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3620   Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3621   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3622     return MCDisassembler::Fail;
3623   unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3624   Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3625   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3626     return MCDisassembler::Fail;
3627   if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3628     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3629   Inst.addOperand(MCOperand::createImm(Qd));
3630 
3631   return S;
3632 }
3633 
3634 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3635                                         uint64_t Address, const void *Decoder) {
3636   DecodeStatus S = MCDisassembler::Success;
3637 
3638   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3639   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3640   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3641   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3642   unsigned size = fieldFromInstruction(Insn, 18, 2);
3643 
3644   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3645     return MCDisassembler::Fail;
3646   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3647     return MCDisassembler::Fail;
3648   Inst.addOperand(MCOperand::createImm(8 << size));
3649 
3650   return S;
3651 }
3652 
3653 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3654                                uint64_t Address, const void *Decoder) {
3655   Inst.addOperand(MCOperand::createImm(8 - Val));
3656   return MCDisassembler::Success;
3657 }
3658 
3659 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3660                                uint64_t Address, const void *Decoder) {
3661   Inst.addOperand(MCOperand::createImm(16 - Val));
3662   return MCDisassembler::Success;
3663 }
3664 
3665 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3666                                uint64_t Address, const void *Decoder) {
3667   Inst.addOperand(MCOperand::createImm(32 - Val));
3668   return MCDisassembler::Success;
3669 }
3670 
3671 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3672                                uint64_t Address, const void *Decoder) {
3673   Inst.addOperand(MCOperand::createImm(64 - Val));
3674   return MCDisassembler::Success;
3675 }
3676 
3677 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3678                                uint64_t Address, const void *Decoder) {
3679   DecodeStatus S = MCDisassembler::Success;
3680 
3681   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3682   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3683   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3684   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3685   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3686   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3687   unsigned op = fieldFromInstruction(Insn, 6, 1);
3688 
3689   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3690     return MCDisassembler::Fail;
3691   if (op) {
3692     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3693     return MCDisassembler::Fail; // Writeback
3694   }
3695 
3696   switch (Inst.getOpcode()) {
3697   case ARM::VTBL2:
3698   case ARM::VTBX2:
3699     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3700       return MCDisassembler::Fail;
3701     break;
3702   default:
3703     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3704       return MCDisassembler::Fail;
3705   }
3706 
3707   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3708     return MCDisassembler::Fail;
3709 
3710   return S;
3711 }
3712 
3713 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3714                                      uint64_t Address, const void *Decoder) {
3715   DecodeStatus S = MCDisassembler::Success;
3716 
3717   unsigned dst = fieldFromInstruction(Insn, 8, 3);
3718   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3719 
3720   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3721     return MCDisassembler::Fail;
3722 
3723   switch(Inst.getOpcode()) {
3724     default:
3725       return MCDisassembler::Fail;
3726     case ARM::tADR:
3727       break; // tADR does not explicitly represent the PC as an operand.
3728     case ARM::tADDrSPi:
3729       Inst.addOperand(MCOperand::createReg(ARM::SP));
3730       break;
3731   }
3732 
3733   Inst.addOperand(MCOperand::createImm(imm));
3734   return S;
3735 }
3736 
3737 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3738                                  uint64_t Address, const void *Decoder) {
3739   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3740                                 true, 2, Inst, Decoder))
3741     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3742   return MCDisassembler::Success;
3743 }
3744 
3745 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3746                                  uint64_t Address, const void *Decoder) {
3747   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3748                                 true, 4, Inst, Decoder))
3749     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3750   return MCDisassembler::Success;
3751 }
3752 
3753 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3754                                  uint64_t Address, const void *Decoder) {
3755   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3756                                 true, 2, Inst, Decoder))
3757     Inst.addOperand(MCOperand::createImm(Val << 1));
3758   return MCDisassembler::Success;
3759 }
3760 
3761 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3762                                  uint64_t Address, const void *Decoder) {
3763   DecodeStatus S = MCDisassembler::Success;
3764 
3765   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3766   unsigned Rm = fieldFromInstruction(Val, 3, 3);
3767 
3768   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3769     return MCDisassembler::Fail;
3770   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3771     return MCDisassembler::Fail;
3772 
3773   return S;
3774 }
3775 
3776 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3777                                   uint64_t Address, const void *Decoder) {
3778   DecodeStatus S = MCDisassembler::Success;
3779 
3780   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3781   unsigned imm = fieldFromInstruction(Val, 3, 5);
3782 
3783   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3784     return MCDisassembler::Fail;
3785   Inst.addOperand(MCOperand::createImm(imm));
3786 
3787   return S;
3788 }
3789 
3790 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3791                                   uint64_t Address, const void *Decoder) {
3792   unsigned imm = Val << 2;
3793 
3794   Inst.addOperand(MCOperand::createImm(imm));
3795   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3796 
3797   return MCDisassembler::Success;
3798 }
3799 
3800 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3801                                   uint64_t Address, const void *Decoder) {
3802   Inst.addOperand(MCOperand::createReg(ARM::SP));
3803   Inst.addOperand(MCOperand::createImm(Val));
3804 
3805   return MCDisassembler::Success;
3806 }
3807 
3808 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3809                                   uint64_t Address, const void *Decoder) {
3810   DecodeStatus S = MCDisassembler::Success;
3811 
3812   unsigned Rn = fieldFromInstruction(Val, 6, 4);
3813   unsigned Rm = fieldFromInstruction(Val, 2, 4);
3814   unsigned imm = fieldFromInstruction(Val, 0, 2);
3815 
3816   // Thumb stores cannot use PC as dest register.
3817   switch (Inst.getOpcode()) {
3818   case ARM::t2STRHs:
3819   case ARM::t2STRBs:
3820   case ARM::t2STRs:
3821     if (Rn == 15)
3822       return MCDisassembler::Fail;
3823     break;
3824   default:
3825     break;
3826   }
3827 
3828   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3829     return MCDisassembler::Fail;
3830   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3831     return MCDisassembler::Fail;
3832   Inst.addOperand(MCOperand::createImm(imm));
3833 
3834   return S;
3835 }
3836 
3837 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3838                               uint64_t Address, const void *Decoder) {
3839   DecodeStatus S = MCDisassembler::Success;
3840 
3841   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3842   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3843 
3844   const FeatureBitset &featureBits =
3845     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3846 
3847   bool hasMP = featureBits[ARM::FeatureMP];
3848   bool hasV7Ops = featureBits[ARM::HasV7Ops];
3849 
3850   if (Rn == 15) {
3851     switch (Inst.getOpcode()) {
3852     case ARM::t2LDRBs:
3853       Inst.setOpcode(ARM::t2LDRBpci);
3854       break;
3855     case ARM::t2LDRHs:
3856       Inst.setOpcode(ARM::t2LDRHpci);
3857       break;
3858     case ARM::t2LDRSHs:
3859       Inst.setOpcode(ARM::t2LDRSHpci);
3860       break;
3861     case ARM::t2LDRSBs:
3862       Inst.setOpcode(ARM::t2LDRSBpci);
3863       break;
3864     case ARM::t2LDRs:
3865       Inst.setOpcode(ARM::t2LDRpci);
3866       break;
3867     case ARM::t2PLDs:
3868       Inst.setOpcode(ARM::t2PLDpci);
3869       break;
3870     case ARM::t2PLIs:
3871       Inst.setOpcode(ARM::t2PLIpci);
3872       break;
3873     default:
3874       return MCDisassembler::Fail;
3875     }
3876 
3877     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3878   }
3879 
3880   if (Rt == 15) {
3881     switch (Inst.getOpcode()) {
3882     case ARM::t2LDRSHs:
3883       return MCDisassembler::Fail;
3884     case ARM::t2LDRHs:
3885       Inst.setOpcode(ARM::t2PLDWs);
3886       break;
3887     case ARM::t2LDRSBs:
3888       Inst.setOpcode(ARM::t2PLIs);
3889       break;
3890     default:
3891       break;
3892     }
3893   }
3894 
3895   switch (Inst.getOpcode()) {
3896     case ARM::t2PLDs:
3897       break;
3898     case ARM::t2PLIs:
3899       if (!hasV7Ops)
3900         return MCDisassembler::Fail;
3901       break;
3902     case ARM::t2PLDWs:
3903       if (!hasV7Ops || !hasMP)
3904         return MCDisassembler::Fail;
3905       break;
3906     default:
3907       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3908         return MCDisassembler::Fail;
3909   }
3910 
3911   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3912   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3913   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3914   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3915     return MCDisassembler::Fail;
3916 
3917   return S;
3918 }
3919 
3920 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3921                                 uint64_t Address, const void* Decoder) {
3922   DecodeStatus S = MCDisassembler::Success;
3923 
3924   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3925   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3926   unsigned U = fieldFromInstruction(Insn, 9, 1);
3927   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3928   imm |= (U << 8);
3929   imm |= (Rn << 9);
3930   unsigned add = fieldFromInstruction(Insn, 9, 1);
3931 
3932   const FeatureBitset &featureBits =
3933     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3934 
3935   bool hasMP = featureBits[ARM::FeatureMP];
3936   bool hasV7Ops = featureBits[ARM::HasV7Ops];
3937 
3938   if (Rn == 15) {
3939     switch (Inst.getOpcode()) {
3940     case ARM::t2LDRi8:
3941       Inst.setOpcode(ARM::t2LDRpci);
3942       break;
3943     case ARM::t2LDRBi8:
3944       Inst.setOpcode(ARM::t2LDRBpci);
3945       break;
3946     case ARM::t2LDRSBi8:
3947       Inst.setOpcode(ARM::t2LDRSBpci);
3948       break;
3949     case ARM::t2LDRHi8:
3950       Inst.setOpcode(ARM::t2LDRHpci);
3951       break;
3952     case ARM::t2LDRSHi8:
3953       Inst.setOpcode(ARM::t2LDRSHpci);
3954       break;
3955     case ARM::t2PLDi8:
3956       Inst.setOpcode(ARM::t2PLDpci);
3957       break;
3958     case ARM::t2PLIi8:
3959       Inst.setOpcode(ARM::t2PLIpci);
3960       break;
3961     default:
3962       return MCDisassembler::Fail;
3963     }
3964     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3965   }
3966 
3967   if (Rt == 15) {
3968     switch (Inst.getOpcode()) {
3969     case ARM::t2LDRSHi8:
3970       return MCDisassembler::Fail;
3971     case ARM::t2LDRHi8:
3972       if (!add)
3973         Inst.setOpcode(ARM::t2PLDWi8);
3974       break;
3975     case ARM::t2LDRSBi8:
3976       Inst.setOpcode(ARM::t2PLIi8);
3977       break;
3978     default:
3979       break;
3980     }
3981   }
3982 
3983   switch (Inst.getOpcode()) {
3984   case ARM::t2PLDi8:
3985     break;
3986   case ARM::t2PLIi8:
3987     if (!hasV7Ops)
3988       return MCDisassembler::Fail;
3989     break;
3990   case ARM::t2PLDWi8:
3991       if (!hasV7Ops || !hasMP)
3992         return MCDisassembler::Fail;
3993       break;
3994   default:
3995     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3996       return MCDisassembler::Fail;
3997   }
3998 
3999   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4000     return MCDisassembler::Fail;
4001   return S;
4002 }
4003 
4004 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
4005                                 uint64_t Address, const void* Decoder) {
4006   DecodeStatus S = MCDisassembler::Success;
4007 
4008   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4009   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4010   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4011   imm |= (Rn << 13);
4012 
4013   const FeatureBitset &featureBits =
4014     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4015 
4016   bool hasMP = featureBits[ARM::FeatureMP];
4017   bool hasV7Ops = featureBits[ARM::HasV7Ops];
4018 
4019   if (Rn == 15) {
4020     switch (Inst.getOpcode()) {
4021     case ARM::t2LDRi12:
4022       Inst.setOpcode(ARM::t2LDRpci);
4023       break;
4024     case ARM::t2LDRHi12:
4025       Inst.setOpcode(ARM::t2LDRHpci);
4026       break;
4027     case ARM::t2LDRSHi12:
4028       Inst.setOpcode(ARM::t2LDRSHpci);
4029       break;
4030     case ARM::t2LDRBi12:
4031       Inst.setOpcode(ARM::t2LDRBpci);
4032       break;
4033     case ARM::t2LDRSBi12:
4034       Inst.setOpcode(ARM::t2LDRSBpci);
4035       break;
4036     case ARM::t2PLDi12:
4037       Inst.setOpcode(ARM::t2PLDpci);
4038       break;
4039     case ARM::t2PLIi12:
4040       Inst.setOpcode(ARM::t2PLIpci);
4041       break;
4042     default:
4043       return MCDisassembler::Fail;
4044     }
4045     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4046   }
4047 
4048   if (Rt == 15) {
4049     switch (Inst.getOpcode()) {
4050     case ARM::t2LDRSHi12:
4051       return MCDisassembler::Fail;
4052     case ARM::t2LDRHi12:
4053       Inst.setOpcode(ARM::t2PLDWi12);
4054       break;
4055     case ARM::t2LDRSBi12:
4056       Inst.setOpcode(ARM::t2PLIi12);
4057       break;
4058     default:
4059       break;
4060     }
4061   }
4062 
4063   switch (Inst.getOpcode()) {
4064   case ARM::t2PLDi12:
4065     break;
4066   case ARM::t2PLIi12:
4067     if (!hasV7Ops)
4068       return MCDisassembler::Fail;
4069     break;
4070   case ARM::t2PLDWi12:
4071       if (!hasV7Ops || !hasMP)
4072         return MCDisassembler::Fail;
4073       break;
4074   default:
4075     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4076       return MCDisassembler::Fail;
4077   }
4078 
4079   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4080     return MCDisassembler::Fail;
4081   return S;
4082 }
4083 
4084 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
4085                                 uint64_t Address, const void* Decoder) {
4086   DecodeStatus S = MCDisassembler::Success;
4087 
4088   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4089   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4090   unsigned imm = fieldFromInstruction(Insn, 0, 8);
4091   imm |= (Rn << 9);
4092 
4093   if (Rn == 15) {
4094     switch (Inst.getOpcode()) {
4095     case ARM::t2LDRT:
4096       Inst.setOpcode(ARM::t2LDRpci);
4097       break;
4098     case ARM::t2LDRBT:
4099       Inst.setOpcode(ARM::t2LDRBpci);
4100       break;
4101     case ARM::t2LDRHT:
4102       Inst.setOpcode(ARM::t2LDRHpci);
4103       break;
4104     case ARM::t2LDRSBT:
4105       Inst.setOpcode(ARM::t2LDRSBpci);
4106       break;
4107     case ARM::t2LDRSHT:
4108       Inst.setOpcode(ARM::t2LDRSHpci);
4109       break;
4110     default:
4111       return MCDisassembler::Fail;
4112     }
4113     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4114   }
4115 
4116   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4117     return MCDisassembler::Fail;
4118   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4119     return MCDisassembler::Fail;
4120   return S;
4121 }
4122 
4123 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4124                                 uint64_t Address, const void* Decoder) {
4125   DecodeStatus S = MCDisassembler::Success;
4126 
4127   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4128   unsigned U = fieldFromInstruction(Insn, 23, 1);
4129   int imm = fieldFromInstruction(Insn, 0, 12);
4130 
4131   const FeatureBitset &featureBits =
4132     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4133 
4134   bool hasV7Ops = featureBits[ARM::HasV7Ops];
4135 
4136   if (Rt == 15) {
4137     switch (Inst.getOpcode()) {
4138       case ARM::t2LDRBpci:
4139       case ARM::t2LDRHpci:
4140         Inst.setOpcode(ARM::t2PLDpci);
4141         break;
4142       case ARM::t2LDRSBpci:
4143         Inst.setOpcode(ARM::t2PLIpci);
4144         break;
4145       case ARM::t2LDRSHpci:
4146         return MCDisassembler::Fail;
4147       default:
4148         break;
4149     }
4150   }
4151 
4152   switch(Inst.getOpcode()) {
4153   case ARM::t2PLDpci:
4154     break;
4155   case ARM::t2PLIpci:
4156     if (!hasV7Ops)
4157       return MCDisassembler::Fail;
4158     break;
4159   default:
4160     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4161       return MCDisassembler::Fail;
4162   }
4163 
4164   if (!U) {
4165     // Special case for #-0.
4166     if (imm == 0)
4167       imm = INT32_MIN;
4168     else
4169       imm = -imm;
4170   }
4171   Inst.addOperand(MCOperand::createImm(imm));
4172 
4173   return S;
4174 }
4175 
4176 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4177                            uint64_t Address, const void *Decoder) {
4178   if (Val == 0)
4179     Inst.addOperand(MCOperand::createImm(INT32_MIN));
4180   else {
4181     int imm = Val & 0xFF;
4182 
4183     if (!(Val & 0x100)) imm *= -1;
4184     Inst.addOperand(MCOperand::createImm(imm * 4));
4185   }
4186 
4187   return MCDisassembler::Success;
4188 }
4189 
4190 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4191                                    const void *Decoder) {
4192   if (Val == 0)
4193     Inst.addOperand(MCOperand::createImm(INT32_MIN));
4194   else {
4195     int imm = Val & 0x7F;
4196 
4197     if (!(Val & 0x80))
4198       imm *= -1;
4199     Inst.addOperand(MCOperand::createImm(imm * 4));
4200   }
4201 
4202   return MCDisassembler::Success;
4203 }
4204 
4205 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4206                                    uint64_t Address, const void *Decoder) {
4207   DecodeStatus S = MCDisassembler::Success;
4208 
4209   unsigned Rn = fieldFromInstruction(Val, 9, 4);
4210   unsigned imm = fieldFromInstruction(Val, 0, 9);
4211 
4212   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4213     return MCDisassembler::Fail;
4214   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4215     return MCDisassembler::Fail;
4216 
4217   return S;
4218 }
4219 
4220 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4221                                            uint64_t Address,
4222                                            const void *Decoder) {
4223   DecodeStatus S = MCDisassembler::Success;
4224 
4225   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4226   unsigned imm = fieldFromInstruction(Val, 0, 8);
4227 
4228   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4229     return MCDisassembler::Fail;
4230   if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4231     return MCDisassembler::Fail;
4232 
4233   return S;
4234 }
4235 
4236 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
4237                                    uint64_t Address, const void *Decoder) {
4238   DecodeStatus S = MCDisassembler::Success;
4239 
4240   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4241   unsigned imm = fieldFromInstruction(Val, 0, 8);
4242 
4243   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4244     return MCDisassembler::Fail;
4245 
4246   Inst.addOperand(MCOperand::createImm(imm));
4247 
4248   return S;
4249 }
4250 
4251 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4252                          uint64_t Address, const void *Decoder) {
4253   int imm = Val & 0xFF;
4254   if (Val == 0)
4255     imm = INT32_MIN;
4256   else if (!(Val & 0x100))
4257     imm *= -1;
4258   Inst.addOperand(MCOperand::createImm(imm));
4259 
4260   return MCDisassembler::Success;
4261 }
4262 
4263 template<int shift>
4264 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4265                          uint64_t Address, const void *Decoder) {
4266   int imm = Val & 0x7F;
4267   if (Val == 0)
4268     imm = INT32_MIN;
4269   else if (!(Val & 0x80))
4270     imm *= -1;
4271   if (imm != INT32_MIN)
4272     imm *= (1U << shift);
4273   Inst.addOperand(MCOperand::createImm(imm));
4274 
4275   return MCDisassembler::Success;
4276 }
4277 
4278 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4279                                  uint64_t Address, const void *Decoder) {
4280   DecodeStatus S = MCDisassembler::Success;
4281 
4282   unsigned Rn = fieldFromInstruction(Val, 9, 4);
4283   unsigned imm = fieldFromInstruction(Val, 0, 9);
4284 
4285   // Thumb stores cannot use PC as dest register.
4286   switch (Inst.getOpcode()) {
4287   case ARM::t2STRT:
4288   case ARM::t2STRBT:
4289   case ARM::t2STRHT:
4290   case ARM::t2STRi8:
4291   case ARM::t2STRHi8:
4292   case ARM::t2STRBi8:
4293     if (Rn == 15)
4294       return MCDisassembler::Fail;
4295     break;
4296   default:
4297     break;
4298   }
4299 
4300   // Some instructions always use an additive offset.
4301   switch (Inst.getOpcode()) {
4302     case ARM::t2LDRT:
4303     case ARM::t2LDRBT:
4304     case ARM::t2LDRHT:
4305     case ARM::t2LDRSBT:
4306     case ARM::t2LDRSHT:
4307     case ARM::t2STRT:
4308     case ARM::t2STRBT:
4309     case ARM::t2STRHT:
4310       imm |= 0x100;
4311       break;
4312     default:
4313       break;
4314   }
4315 
4316   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4317     return MCDisassembler::Fail;
4318   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4319     return MCDisassembler::Fail;
4320 
4321   return S;
4322 }
4323 
4324 template<int shift>
4325 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4326                                          uint64_t Address,
4327                                          const void *Decoder) {
4328   DecodeStatus S = MCDisassembler::Success;
4329 
4330   unsigned Rn = fieldFromInstruction(Val, 8, 3);
4331   unsigned imm = fieldFromInstruction(Val, 0, 8);
4332 
4333   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4334     return MCDisassembler::Fail;
4335   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4336     return MCDisassembler::Fail;
4337 
4338   return S;
4339 }
4340 
4341 template<int shift, int WriteBack>
4342 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4343                                          uint64_t Address,
4344                                          const void *Decoder) {
4345   DecodeStatus S = MCDisassembler::Success;
4346 
4347   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4348   unsigned imm = fieldFromInstruction(Val, 0, 8);
4349   if (WriteBack) {
4350     if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4351       return MCDisassembler::Fail;
4352   } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4353     return MCDisassembler::Fail;
4354   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4355     return MCDisassembler::Fail;
4356 
4357   return S;
4358 }
4359 
4360 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4361                                     uint64_t Address, const void *Decoder) {
4362   DecodeStatus S = MCDisassembler::Success;
4363 
4364   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4365   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4366   unsigned addr = fieldFromInstruction(Insn, 0, 8);
4367   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4368   addr |= Rn << 9;
4369   unsigned load = fieldFromInstruction(Insn, 20, 1);
4370 
4371   if (Rn == 15) {
4372     switch (Inst.getOpcode()) {
4373     case ARM::t2LDR_PRE:
4374     case ARM::t2LDR_POST:
4375       Inst.setOpcode(ARM::t2LDRpci);
4376       break;
4377     case ARM::t2LDRB_PRE:
4378     case ARM::t2LDRB_POST:
4379       Inst.setOpcode(ARM::t2LDRBpci);
4380       break;
4381     case ARM::t2LDRH_PRE:
4382     case ARM::t2LDRH_POST:
4383       Inst.setOpcode(ARM::t2LDRHpci);
4384       break;
4385     case ARM::t2LDRSB_PRE:
4386     case ARM::t2LDRSB_POST:
4387       if (Rt == 15)
4388         Inst.setOpcode(ARM::t2PLIpci);
4389       else
4390         Inst.setOpcode(ARM::t2LDRSBpci);
4391       break;
4392     case ARM::t2LDRSH_PRE:
4393     case ARM::t2LDRSH_POST:
4394       Inst.setOpcode(ARM::t2LDRSHpci);
4395       break;
4396     default:
4397       return MCDisassembler::Fail;
4398     }
4399     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4400   }
4401 
4402   if (!load) {
4403     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4404       return MCDisassembler::Fail;
4405   }
4406 
4407   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4408     return MCDisassembler::Fail;
4409 
4410   if (load) {
4411     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4412       return MCDisassembler::Fail;
4413   }
4414 
4415   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4416     return MCDisassembler::Fail;
4417 
4418   return S;
4419 }
4420 
4421 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4422                                   uint64_t Address, const void *Decoder) {
4423   DecodeStatus S = MCDisassembler::Success;
4424 
4425   unsigned Rn = fieldFromInstruction(Val, 13, 4);
4426   unsigned imm = fieldFromInstruction(Val, 0, 12);
4427 
4428   // Thumb stores cannot use PC as dest register.
4429   switch (Inst.getOpcode()) {
4430   case ARM::t2STRi12:
4431   case ARM::t2STRBi12:
4432   case ARM::t2STRHi12:
4433     if (Rn == 15)
4434       return MCDisassembler::Fail;
4435     break;
4436   default:
4437     break;
4438   }
4439 
4440   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4441     return MCDisassembler::Fail;
4442   Inst.addOperand(MCOperand::createImm(imm));
4443 
4444   return S;
4445 }
4446 
4447 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4448                                 uint64_t Address, const void *Decoder) {
4449   unsigned imm = fieldFromInstruction(Insn, 0, 7);
4450 
4451   Inst.addOperand(MCOperand::createReg(ARM::SP));
4452   Inst.addOperand(MCOperand::createReg(ARM::SP));
4453   Inst.addOperand(MCOperand::createImm(imm));
4454 
4455   return MCDisassembler::Success;
4456 }
4457 
4458 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4459                                 uint64_t Address, const void *Decoder) {
4460   DecodeStatus S = MCDisassembler::Success;
4461 
4462   if (Inst.getOpcode() == ARM::tADDrSP) {
4463     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4464     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4465 
4466     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4467     return MCDisassembler::Fail;
4468     Inst.addOperand(MCOperand::createReg(ARM::SP));
4469     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4470     return MCDisassembler::Fail;
4471   } else if (Inst.getOpcode() == ARM::tADDspr) {
4472     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4473 
4474     Inst.addOperand(MCOperand::createReg(ARM::SP));
4475     Inst.addOperand(MCOperand::createReg(ARM::SP));
4476     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4477     return MCDisassembler::Fail;
4478   }
4479 
4480   return S;
4481 }
4482 
4483 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4484                            uint64_t Address, const void *Decoder) {
4485   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4486   unsigned flags = fieldFromInstruction(Insn, 0, 3);
4487 
4488   Inst.addOperand(MCOperand::createImm(imod));
4489   Inst.addOperand(MCOperand::createImm(flags));
4490 
4491   return MCDisassembler::Success;
4492 }
4493 
4494 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4495                              uint64_t Address, const void *Decoder) {
4496   DecodeStatus S = MCDisassembler::Success;
4497   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4498   unsigned add = fieldFromInstruction(Insn, 4, 1);
4499 
4500   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4501     return MCDisassembler::Fail;
4502   Inst.addOperand(MCOperand::createImm(add));
4503 
4504   return S;
4505 }
4506 
4507 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4508                              uint64_t Address, const void *Decoder) {
4509   DecodeStatus S = MCDisassembler::Success;
4510   unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4511   unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4512 
4513   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4514     return MCDisassembler::Fail;
4515   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4516     return MCDisassembler::Fail;
4517 
4518   return S;
4519 }
4520 
4521 template<int shift>
4522 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4523                              uint64_t Address, const void *Decoder) {
4524   DecodeStatus S = MCDisassembler::Success;
4525   unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4526   int imm = fieldFromInstruction(Insn, 0, 7);
4527 
4528   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4529     return MCDisassembler::Fail;
4530 
4531   if(!fieldFromInstruction(Insn, 7, 1)) {
4532     if (imm == 0)
4533       imm = INT32_MIN;                 // indicate -0
4534     else
4535       imm *= -1;
4536   }
4537   if (imm != INT32_MIN)
4538     imm *= (1U << shift);
4539   Inst.addOperand(MCOperand::createImm(imm));
4540 
4541   return S;
4542 }
4543 
4544 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4545                                  uint64_t Address, const void *Decoder) {
4546   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4547   // Note only one trailing zero not two.  Also the J1 and J2 values are from
4548   // the encoded instruction.  So here change to I1 and I2 values via:
4549   // I1 = NOT(J1 EOR S);
4550   // I2 = NOT(J2 EOR S);
4551   // and build the imm32 with two trailing zeros as documented:
4552   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4553   unsigned S = (Val >> 23) & 1;
4554   unsigned J1 = (Val >> 22) & 1;
4555   unsigned J2 = (Val >> 21) & 1;
4556   unsigned I1 = !(J1 ^ S);
4557   unsigned I2 = !(J2 ^ S);
4558   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4559   int imm32 = SignExtend32<25>(tmp << 1);
4560 
4561   if (!tryAddingSymbolicOperand(Address,
4562                                 (Address & ~2u) + imm32 + 4,
4563                                 true, 4, Inst, Decoder))
4564     Inst.addOperand(MCOperand::createImm(imm32));
4565   return MCDisassembler::Success;
4566 }
4567 
4568 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4569                               uint64_t Address, const void *Decoder) {
4570   if (Val == 0xA || Val == 0xB)
4571     return MCDisassembler::Fail;
4572 
4573   const FeatureBitset &featureBits =
4574     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4575 
4576   if (!isValidCoprocessorNumber(Val, featureBits))
4577     return MCDisassembler::Fail;
4578 
4579   Inst.addOperand(MCOperand::createImm(Val));
4580   return MCDisassembler::Success;
4581 }
4582 
4583 static DecodeStatus
4584 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4585                        uint64_t Address, const void *Decoder) {
4586   const FeatureBitset &FeatureBits =
4587     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4588   DecodeStatus S = MCDisassembler::Success;
4589 
4590   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4591   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4592 
4593   if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
4594   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4595     return MCDisassembler::Fail;
4596   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4597     return MCDisassembler::Fail;
4598   return S;
4599 }
4600 
4601 static DecodeStatus
4602 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4603                            uint64_t Address, const void *Decoder) {
4604   DecodeStatus S = MCDisassembler::Success;
4605 
4606   unsigned pred = fieldFromInstruction(Insn, 22, 4);
4607   if (pred == 0xE || pred == 0xF) {
4608     unsigned opc = fieldFromInstruction(Insn, 4, 28);
4609     switch (opc) {
4610       default:
4611         return MCDisassembler::Fail;
4612       case 0xf3bf8f4:
4613         Inst.setOpcode(ARM::t2DSB);
4614         break;
4615       case 0xf3bf8f5:
4616         Inst.setOpcode(ARM::t2DMB);
4617         break;
4618       case 0xf3bf8f6:
4619         Inst.setOpcode(ARM::t2ISB);
4620         break;
4621     }
4622 
4623     unsigned imm = fieldFromInstruction(Insn, 0, 4);
4624     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4625   }
4626 
4627   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4628   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4629   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4630   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4631   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4632 
4633   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4634     return MCDisassembler::Fail;
4635   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4636     return MCDisassembler::Fail;
4637 
4638   return S;
4639 }
4640 
4641 // Decode a shifted immediate operand.  These basically consist
4642 // of an 8-bit value, and a 4-bit directive that specifies either
4643 // a splat operation or a rotation.
4644 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4645                           uint64_t Address, const void *Decoder) {
4646   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4647   if (ctrl == 0) {
4648     unsigned byte = fieldFromInstruction(Val, 8, 2);
4649     unsigned imm = fieldFromInstruction(Val, 0, 8);
4650     switch (byte) {
4651       case 0:
4652         Inst.addOperand(MCOperand::createImm(imm));
4653         break;
4654       case 1:
4655         Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4656         break;
4657       case 2:
4658         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4659         break;
4660       case 3:
4661         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4662                                              (imm << 8)  |  imm));
4663         break;
4664     }
4665   } else {
4666     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4667     unsigned rot = fieldFromInstruction(Val, 7, 5);
4668     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4669     Inst.addOperand(MCOperand::createImm(imm));
4670   }
4671 
4672   return MCDisassembler::Success;
4673 }
4674 
4675 static DecodeStatus
4676 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4677                             uint64_t Address, const void *Decoder) {
4678   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4679                                 true, 2, Inst, Decoder))
4680     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4681   return MCDisassembler::Success;
4682 }
4683 
4684 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4685                                                uint64_t Address,
4686                                                const void *Decoder) {
4687   // Val is passed in as S:J1:J2:imm10:imm11
4688   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
4689   // the encoded instruction.  So here change to I1 and I2 values via:
4690   // I1 = NOT(J1 EOR S);
4691   // I2 = NOT(J2 EOR S);
4692   // and build the imm32 with one trailing zero as documented:
4693   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4694   unsigned S = (Val >> 23) & 1;
4695   unsigned J1 = (Val >> 22) & 1;
4696   unsigned J2 = (Val >> 21) & 1;
4697   unsigned I1 = !(J1 ^ S);
4698   unsigned I2 = !(J2 ^ S);
4699   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4700   int imm32 = SignExtend32<25>(tmp << 1);
4701 
4702   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4703                                 true, 4, Inst, Decoder))
4704     Inst.addOperand(MCOperand::createImm(imm32));
4705   return MCDisassembler::Success;
4706 }
4707 
4708 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4709                                    uint64_t Address, const void *Decoder) {
4710   if (Val & ~0xf)
4711     return MCDisassembler::Fail;
4712 
4713   Inst.addOperand(MCOperand::createImm(Val));
4714   return MCDisassembler::Success;
4715 }
4716 
4717 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4718                                         uint64_t Address, const void *Decoder) {
4719   if (Val & ~0xf)
4720     return MCDisassembler::Fail;
4721 
4722   Inst.addOperand(MCOperand::createImm(Val));
4723   return MCDisassembler::Success;
4724 }
4725 
4726 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4727                           uint64_t Address, const void *Decoder) {
4728   DecodeStatus S = MCDisassembler::Success;
4729   const FeatureBitset &FeatureBits =
4730     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4731 
4732   if (FeatureBits[ARM::FeatureMClass]) {
4733     unsigned ValLow = Val & 0xff;
4734 
4735     // Validate the SYSm value first.
4736     switch (ValLow) {
4737     case  0: // apsr
4738     case  1: // iapsr
4739     case  2: // eapsr
4740     case  3: // xpsr
4741     case  5: // ipsr
4742     case  6: // epsr
4743     case  7: // iepsr
4744     case  8: // msp
4745     case  9: // psp
4746     case 16: // primask
4747     case 20: // control
4748       break;
4749     case 17: // basepri
4750     case 18: // basepri_max
4751     case 19: // faultmask
4752       if (!(FeatureBits[ARM::HasV7Ops]))
4753         // Values basepri, basepri_max and faultmask are only valid for v7m.
4754         return MCDisassembler::Fail;
4755       break;
4756     case 0x8a: // msplim_ns
4757     case 0x8b: // psplim_ns
4758     case 0x91: // basepri_ns
4759     case 0x93: // faultmask_ns
4760       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4761         return MCDisassembler::Fail;
4762       LLVM_FALLTHROUGH;
4763     case 10:   // msplim
4764     case 11:   // psplim
4765     case 0x88: // msp_ns
4766     case 0x89: // psp_ns
4767     case 0x90: // primask_ns
4768     case 0x94: // control_ns
4769     case 0x98: // sp_ns
4770       if (!(FeatureBits[ARM::Feature8MSecExt]))
4771         return MCDisassembler::Fail;
4772       break;
4773     case 0x20: // pac_key_p_0
4774     case 0x21: // pac_key_p_1
4775     case 0x22: // pac_key_p_2
4776     case 0x23: // pac_key_p_3
4777     case 0x24: // pac_key_u_0
4778     case 0x25: // pac_key_u_1
4779     case 0x26: // pac_key_u_2
4780     case 0x27: // pac_key_u_3
4781     case 0xa0: // pac_key_p_0_ns
4782     case 0xa1: // pac_key_p_1_ns
4783     case 0xa2: // pac_key_p_2_ns
4784     case 0xa3: // pac_key_p_3_ns
4785     case 0xa4: // pac_key_u_0_ns
4786     case 0xa5: // pac_key_u_1_ns
4787     case 0xa6: // pac_key_u_2_ns
4788     case 0xa7: // pac_key_u_3_ns
4789       if (!(FeatureBits[ARM::FeaturePACBTI]))
4790         return MCDisassembler::Fail;
4791       break;
4792     default:
4793       // Architecturally defined as unpredictable
4794       S = MCDisassembler::SoftFail;
4795       break;
4796     }
4797 
4798     if (Inst.getOpcode() == ARM::t2MSR_M) {
4799       unsigned Mask = fieldFromInstruction(Val, 10, 2);
4800       if (!(FeatureBits[ARM::HasV7Ops])) {
4801         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4802         // unpredictable.
4803         if (Mask != 2)
4804           S = MCDisassembler::SoftFail;
4805       }
4806       else {
4807         // The ARMv7-M architecture stores an additional 2-bit mask value in
4808         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4809         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4810         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4811         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4812         // only if the processor includes the DSP extension.
4813         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4814             (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4815           S = MCDisassembler::SoftFail;
4816       }
4817     }
4818   } else {
4819     // A/R class
4820     if (Val == 0)
4821       return MCDisassembler::Fail;
4822   }
4823   Inst.addOperand(MCOperand::createImm(Val));
4824   return S;
4825 }
4826 
4827 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4828                                     uint64_t Address, const void *Decoder) {
4829   unsigned R = fieldFromInstruction(Val, 5, 1);
4830   unsigned SysM = fieldFromInstruction(Val, 0, 5);
4831 
4832   // The table of encodings for these banked registers comes from B9.2.3 of the
4833   // ARM ARM. There are patterns, but nothing regular enough to make this logic
4834   // neater. So by fiat, these values are UNPREDICTABLE:
4835   if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4836     return MCDisassembler::Fail;
4837 
4838   Inst.addOperand(MCOperand::createImm(Val));
4839   return MCDisassembler::Success;
4840 }
4841 
4842 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4843                                         uint64_t Address, const void *Decoder) {
4844   DecodeStatus S = MCDisassembler::Success;
4845 
4846   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4847   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4848   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4849 
4850   if (Rn == 0xF)
4851     S = MCDisassembler::SoftFail;
4852 
4853   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4854     return MCDisassembler::Fail;
4855   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4856     return MCDisassembler::Fail;
4857   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4858     return MCDisassembler::Fail;
4859 
4860   return S;
4861 }
4862 
4863 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4864                                          uint64_t Address,
4865                                          const void *Decoder) {
4866   DecodeStatus S = MCDisassembler::Success;
4867 
4868   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4869   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4870   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4871   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4872 
4873   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4874     return MCDisassembler::Fail;
4875 
4876   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4877     S = MCDisassembler::SoftFail;
4878 
4879   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4880     return MCDisassembler::Fail;
4881   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4882     return MCDisassembler::Fail;
4883   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4884     return MCDisassembler::Fail;
4885 
4886   return S;
4887 }
4888 
4889 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4890                             uint64_t Address, const void *Decoder) {
4891   DecodeStatus S = MCDisassembler::Success;
4892 
4893   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4894   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4895   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4896   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4897   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4898   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4899 
4900   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4901 
4902   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4903     return MCDisassembler::Fail;
4904   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4905     return MCDisassembler::Fail;
4906   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4907     return MCDisassembler::Fail;
4908   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4909     return MCDisassembler::Fail;
4910 
4911   return S;
4912 }
4913 
4914 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4915                             uint64_t Address, const void *Decoder) {
4916   DecodeStatus S = MCDisassembler::Success;
4917 
4918   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4919   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4920   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4921   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4922   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4923   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4924   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4925 
4926   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4927   if (Rm == 0xF) S = MCDisassembler::SoftFail;
4928 
4929   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4930     return MCDisassembler::Fail;
4931   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4932     return MCDisassembler::Fail;
4933   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4934     return MCDisassembler::Fail;
4935   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4936     return MCDisassembler::Fail;
4937 
4938   return S;
4939 }
4940 
4941 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4942                             uint64_t Address, const void *Decoder) {
4943   DecodeStatus S = MCDisassembler::Success;
4944 
4945   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4946   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4947   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4948   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4949   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4950   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4951 
4952   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4953 
4954   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4955     return MCDisassembler::Fail;
4956   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4957     return MCDisassembler::Fail;
4958   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4959     return MCDisassembler::Fail;
4960   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4961     return MCDisassembler::Fail;
4962 
4963   return S;
4964 }
4965 
4966 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4967                             uint64_t Address, const void *Decoder) {
4968   DecodeStatus S = MCDisassembler::Success;
4969 
4970   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4971   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4972   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4973   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4974   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4975   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4976 
4977   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4978 
4979   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4980     return MCDisassembler::Fail;
4981   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4982     return MCDisassembler::Fail;
4983   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4984     return MCDisassembler::Fail;
4985   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4986     return MCDisassembler::Fail;
4987 
4988   return S;
4989 }
4990 
4991 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4992                          uint64_t Address, const void *Decoder) {
4993   DecodeStatus S = MCDisassembler::Success;
4994 
4995   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4996   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4997   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4998   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4999   unsigned size = fieldFromInstruction(Insn, 10, 2);
5000 
5001   unsigned align = 0;
5002   unsigned index = 0;
5003   switch (size) {
5004     default:
5005       return MCDisassembler::Fail;
5006     case 0:
5007       if (fieldFromInstruction(Insn, 4, 1))
5008         return MCDisassembler::Fail; // UNDEFINED
5009       index = fieldFromInstruction(Insn, 5, 3);
5010       break;
5011     case 1:
5012       if (fieldFromInstruction(Insn, 5, 1))
5013         return MCDisassembler::Fail; // UNDEFINED
5014       index = fieldFromInstruction(Insn, 6, 2);
5015       if (fieldFromInstruction(Insn, 4, 1))
5016         align = 2;
5017       break;
5018     case 2:
5019       if (fieldFromInstruction(Insn, 6, 1))
5020         return MCDisassembler::Fail; // UNDEFINED
5021       index = fieldFromInstruction(Insn, 7, 1);
5022 
5023       switch (fieldFromInstruction(Insn, 4, 2)) {
5024         case 0 :
5025           align = 0; break;
5026         case 3:
5027           align = 4; break;
5028         default:
5029           return MCDisassembler::Fail;
5030       }
5031       break;
5032   }
5033 
5034   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5035     return MCDisassembler::Fail;
5036   if (Rm != 0xF) { // Writeback
5037     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5038       return MCDisassembler::Fail;
5039   }
5040   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5041     return MCDisassembler::Fail;
5042   Inst.addOperand(MCOperand::createImm(align));
5043   if (Rm != 0xF) {
5044     if (Rm != 0xD) {
5045       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5046         return MCDisassembler::Fail;
5047     } else
5048       Inst.addOperand(MCOperand::createReg(0));
5049   }
5050 
5051   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5052     return MCDisassembler::Fail;
5053   Inst.addOperand(MCOperand::createImm(index));
5054 
5055   return S;
5056 }
5057 
5058 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
5059                          uint64_t Address, const void *Decoder) {
5060   DecodeStatus S = MCDisassembler::Success;
5061 
5062   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5063   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5064   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5065   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5066   unsigned size = fieldFromInstruction(Insn, 10, 2);
5067 
5068   unsigned align = 0;
5069   unsigned index = 0;
5070   switch (size) {
5071     default:
5072       return MCDisassembler::Fail;
5073     case 0:
5074       if (fieldFromInstruction(Insn, 4, 1))
5075         return MCDisassembler::Fail; // UNDEFINED
5076       index = fieldFromInstruction(Insn, 5, 3);
5077       break;
5078     case 1:
5079       if (fieldFromInstruction(Insn, 5, 1))
5080         return MCDisassembler::Fail; // UNDEFINED
5081       index = fieldFromInstruction(Insn, 6, 2);
5082       if (fieldFromInstruction(Insn, 4, 1))
5083         align = 2;
5084       break;
5085     case 2:
5086       if (fieldFromInstruction(Insn, 6, 1))
5087         return MCDisassembler::Fail; // UNDEFINED
5088       index = fieldFromInstruction(Insn, 7, 1);
5089 
5090       switch (fieldFromInstruction(Insn, 4, 2)) {
5091         case 0:
5092           align = 0; break;
5093         case 3:
5094           align = 4; break;
5095         default:
5096           return MCDisassembler::Fail;
5097       }
5098       break;
5099   }
5100 
5101   if (Rm != 0xF) { // Writeback
5102     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5103     return MCDisassembler::Fail;
5104   }
5105   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5106     return MCDisassembler::Fail;
5107   Inst.addOperand(MCOperand::createImm(align));
5108   if (Rm != 0xF) {
5109     if (Rm != 0xD) {
5110       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5111     return MCDisassembler::Fail;
5112     } else
5113       Inst.addOperand(MCOperand::createReg(0));
5114   }
5115 
5116   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5117     return MCDisassembler::Fail;
5118   Inst.addOperand(MCOperand::createImm(index));
5119 
5120   return S;
5121 }
5122 
5123 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
5124                          uint64_t Address, const void *Decoder) {
5125   DecodeStatus S = MCDisassembler::Success;
5126 
5127   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5128   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5129   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5130   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5131   unsigned size = fieldFromInstruction(Insn, 10, 2);
5132 
5133   unsigned align = 0;
5134   unsigned index = 0;
5135   unsigned inc = 1;
5136   switch (size) {
5137     default:
5138       return MCDisassembler::Fail;
5139     case 0:
5140       index = fieldFromInstruction(Insn, 5, 3);
5141       if (fieldFromInstruction(Insn, 4, 1))
5142         align = 2;
5143       break;
5144     case 1:
5145       index = fieldFromInstruction(Insn, 6, 2);
5146       if (fieldFromInstruction(Insn, 4, 1))
5147         align = 4;
5148       if (fieldFromInstruction(Insn, 5, 1))
5149         inc = 2;
5150       break;
5151     case 2:
5152       if (fieldFromInstruction(Insn, 5, 1))
5153         return MCDisassembler::Fail; // UNDEFINED
5154       index = fieldFromInstruction(Insn, 7, 1);
5155       if (fieldFromInstruction(Insn, 4, 1) != 0)
5156         align = 8;
5157       if (fieldFromInstruction(Insn, 6, 1))
5158         inc = 2;
5159       break;
5160   }
5161 
5162   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5163     return MCDisassembler::Fail;
5164   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5165     return MCDisassembler::Fail;
5166   if (Rm != 0xF) { // Writeback
5167     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5168       return MCDisassembler::Fail;
5169   }
5170   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5171     return MCDisassembler::Fail;
5172   Inst.addOperand(MCOperand::createImm(align));
5173   if (Rm != 0xF) {
5174     if (Rm != 0xD) {
5175       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5176         return MCDisassembler::Fail;
5177     } else
5178       Inst.addOperand(MCOperand::createReg(0));
5179   }
5180 
5181   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5182     return MCDisassembler::Fail;
5183   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5184     return MCDisassembler::Fail;
5185   Inst.addOperand(MCOperand::createImm(index));
5186 
5187   return S;
5188 }
5189 
5190 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
5191                          uint64_t Address, const void *Decoder) {
5192   DecodeStatus S = MCDisassembler::Success;
5193 
5194   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5195   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5196   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5197   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5198   unsigned size = fieldFromInstruction(Insn, 10, 2);
5199 
5200   unsigned align = 0;
5201   unsigned index = 0;
5202   unsigned inc = 1;
5203   switch (size) {
5204     default:
5205       return MCDisassembler::Fail;
5206     case 0:
5207       index = fieldFromInstruction(Insn, 5, 3);
5208       if (fieldFromInstruction(Insn, 4, 1))
5209         align = 2;
5210       break;
5211     case 1:
5212       index = fieldFromInstruction(Insn, 6, 2);
5213       if (fieldFromInstruction(Insn, 4, 1))
5214         align = 4;
5215       if (fieldFromInstruction(Insn, 5, 1))
5216         inc = 2;
5217       break;
5218     case 2:
5219       if (fieldFromInstruction(Insn, 5, 1))
5220         return MCDisassembler::Fail; // UNDEFINED
5221       index = fieldFromInstruction(Insn, 7, 1);
5222       if (fieldFromInstruction(Insn, 4, 1) != 0)
5223         align = 8;
5224       if (fieldFromInstruction(Insn, 6, 1))
5225         inc = 2;
5226       break;
5227   }
5228 
5229   if (Rm != 0xF) { // Writeback
5230     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5231       return MCDisassembler::Fail;
5232   }
5233   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5234     return MCDisassembler::Fail;
5235   Inst.addOperand(MCOperand::createImm(align));
5236   if (Rm != 0xF) {
5237     if (Rm != 0xD) {
5238       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5239         return MCDisassembler::Fail;
5240     } else
5241       Inst.addOperand(MCOperand::createReg(0));
5242   }
5243 
5244   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5245     return MCDisassembler::Fail;
5246   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5247     return MCDisassembler::Fail;
5248   Inst.addOperand(MCOperand::createImm(index));
5249 
5250   return S;
5251 }
5252 
5253 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
5254                          uint64_t Address, const void *Decoder) {
5255   DecodeStatus S = MCDisassembler::Success;
5256 
5257   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5258   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5259   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5260   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5261   unsigned size = fieldFromInstruction(Insn, 10, 2);
5262 
5263   unsigned align = 0;
5264   unsigned index = 0;
5265   unsigned inc = 1;
5266   switch (size) {
5267     default:
5268       return MCDisassembler::Fail;
5269     case 0:
5270       if (fieldFromInstruction(Insn, 4, 1))
5271         return MCDisassembler::Fail; // UNDEFINED
5272       index = fieldFromInstruction(Insn, 5, 3);
5273       break;
5274     case 1:
5275       if (fieldFromInstruction(Insn, 4, 1))
5276         return MCDisassembler::Fail; // UNDEFINED
5277       index = fieldFromInstruction(Insn, 6, 2);
5278       if (fieldFromInstruction(Insn, 5, 1))
5279         inc = 2;
5280       break;
5281     case 2:
5282       if (fieldFromInstruction(Insn, 4, 2))
5283         return MCDisassembler::Fail; // UNDEFINED
5284       index = fieldFromInstruction(Insn, 7, 1);
5285       if (fieldFromInstruction(Insn, 6, 1))
5286         inc = 2;
5287       break;
5288   }
5289 
5290   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5291     return MCDisassembler::Fail;
5292   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5293     return MCDisassembler::Fail;
5294   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5295     return MCDisassembler::Fail;
5296 
5297   if (Rm != 0xF) { // Writeback
5298     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5299     return MCDisassembler::Fail;
5300   }
5301   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5302     return MCDisassembler::Fail;
5303   Inst.addOperand(MCOperand::createImm(align));
5304   if (Rm != 0xF) {
5305     if (Rm != 0xD) {
5306       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5307     return MCDisassembler::Fail;
5308     } else
5309       Inst.addOperand(MCOperand::createReg(0));
5310   }
5311 
5312   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5313     return MCDisassembler::Fail;
5314   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5315     return MCDisassembler::Fail;
5316   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5317     return MCDisassembler::Fail;
5318   Inst.addOperand(MCOperand::createImm(index));
5319 
5320   return S;
5321 }
5322 
5323 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
5324                          uint64_t Address, const void *Decoder) {
5325   DecodeStatus S = MCDisassembler::Success;
5326 
5327   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5328   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5329   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5330   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5331   unsigned size = fieldFromInstruction(Insn, 10, 2);
5332 
5333   unsigned align = 0;
5334   unsigned index = 0;
5335   unsigned inc = 1;
5336   switch (size) {
5337     default:
5338       return MCDisassembler::Fail;
5339     case 0:
5340       if (fieldFromInstruction(Insn, 4, 1))
5341         return MCDisassembler::Fail; // UNDEFINED
5342       index = fieldFromInstruction(Insn, 5, 3);
5343       break;
5344     case 1:
5345       if (fieldFromInstruction(Insn, 4, 1))
5346         return MCDisassembler::Fail; // UNDEFINED
5347       index = fieldFromInstruction(Insn, 6, 2);
5348       if (fieldFromInstruction(Insn, 5, 1))
5349         inc = 2;
5350       break;
5351     case 2:
5352       if (fieldFromInstruction(Insn, 4, 2))
5353         return MCDisassembler::Fail; // UNDEFINED
5354       index = fieldFromInstruction(Insn, 7, 1);
5355       if (fieldFromInstruction(Insn, 6, 1))
5356         inc = 2;
5357       break;
5358   }
5359 
5360   if (Rm != 0xF) { // Writeback
5361     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5362     return MCDisassembler::Fail;
5363   }
5364   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5365     return MCDisassembler::Fail;
5366   Inst.addOperand(MCOperand::createImm(align));
5367   if (Rm != 0xF) {
5368     if (Rm != 0xD) {
5369       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5370     return MCDisassembler::Fail;
5371     } else
5372       Inst.addOperand(MCOperand::createReg(0));
5373   }
5374 
5375   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5376     return MCDisassembler::Fail;
5377   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5378     return MCDisassembler::Fail;
5379   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5380     return MCDisassembler::Fail;
5381   Inst.addOperand(MCOperand::createImm(index));
5382 
5383   return S;
5384 }
5385 
5386 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
5387                          uint64_t Address, const void *Decoder) {
5388   DecodeStatus S = MCDisassembler::Success;
5389 
5390   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5391   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5392   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5393   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5394   unsigned size = fieldFromInstruction(Insn, 10, 2);
5395 
5396   unsigned align = 0;
5397   unsigned index = 0;
5398   unsigned inc = 1;
5399   switch (size) {
5400     default:
5401       return MCDisassembler::Fail;
5402     case 0:
5403       if (fieldFromInstruction(Insn, 4, 1))
5404         align = 4;
5405       index = fieldFromInstruction(Insn, 5, 3);
5406       break;
5407     case 1:
5408       if (fieldFromInstruction(Insn, 4, 1))
5409         align = 8;
5410       index = fieldFromInstruction(Insn, 6, 2);
5411       if (fieldFromInstruction(Insn, 5, 1))
5412         inc = 2;
5413       break;
5414     case 2:
5415       switch (fieldFromInstruction(Insn, 4, 2)) {
5416         case 0:
5417           align = 0; break;
5418         case 3:
5419           return MCDisassembler::Fail;
5420         default:
5421           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5422       }
5423 
5424       index = fieldFromInstruction(Insn, 7, 1);
5425       if (fieldFromInstruction(Insn, 6, 1))
5426         inc = 2;
5427       break;
5428   }
5429 
5430   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5431     return MCDisassembler::Fail;
5432   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5433     return MCDisassembler::Fail;
5434   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5435     return MCDisassembler::Fail;
5436   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5437     return MCDisassembler::Fail;
5438 
5439   if (Rm != 0xF) { // Writeback
5440     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5441       return MCDisassembler::Fail;
5442   }
5443   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5444     return MCDisassembler::Fail;
5445   Inst.addOperand(MCOperand::createImm(align));
5446   if (Rm != 0xF) {
5447     if (Rm != 0xD) {
5448       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5449         return MCDisassembler::Fail;
5450     } else
5451       Inst.addOperand(MCOperand::createReg(0));
5452   }
5453 
5454   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5455     return MCDisassembler::Fail;
5456   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5457     return MCDisassembler::Fail;
5458   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5459     return MCDisassembler::Fail;
5460   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5461     return MCDisassembler::Fail;
5462   Inst.addOperand(MCOperand::createImm(index));
5463 
5464   return S;
5465 }
5466 
5467 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
5468                          uint64_t Address, const void *Decoder) {
5469   DecodeStatus S = MCDisassembler::Success;
5470 
5471   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5472   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5473   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5474   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5475   unsigned size = fieldFromInstruction(Insn, 10, 2);
5476 
5477   unsigned align = 0;
5478   unsigned index = 0;
5479   unsigned inc = 1;
5480   switch (size) {
5481     default:
5482       return MCDisassembler::Fail;
5483     case 0:
5484       if (fieldFromInstruction(Insn, 4, 1))
5485         align = 4;
5486       index = fieldFromInstruction(Insn, 5, 3);
5487       break;
5488     case 1:
5489       if (fieldFromInstruction(Insn, 4, 1))
5490         align = 8;
5491       index = fieldFromInstruction(Insn, 6, 2);
5492       if (fieldFromInstruction(Insn, 5, 1))
5493         inc = 2;
5494       break;
5495     case 2:
5496       switch (fieldFromInstruction(Insn, 4, 2)) {
5497         case 0:
5498           align = 0; break;
5499         case 3:
5500           return MCDisassembler::Fail;
5501         default:
5502           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5503       }
5504 
5505       index = fieldFromInstruction(Insn, 7, 1);
5506       if (fieldFromInstruction(Insn, 6, 1))
5507         inc = 2;
5508       break;
5509   }
5510 
5511   if (Rm != 0xF) { // Writeback
5512     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5513     return MCDisassembler::Fail;
5514   }
5515   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5516     return MCDisassembler::Fail;
5517   Inst.addOperand(MCOperand::createImm(align));
5518   if (Rm != 0xF) {
5519     if (Rm != 0xD) {
5520       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5521     return MCDisassembler::Fail;
5522     } else
5523       Inst.addOperand(MCOperand::createReg(0));
5524   }
5525 
5526   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5527     return MCDisassembler::Fail;
5528   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5529     return MCDisassembler::Fail;
5530   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5531     return MCDisassembler::Fail;
5532   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5533     return MCDisassembler::Fail;
5534   Inst.addOperand(MCOperand::createImm(index));
5535 
5536   return S;
5537 }
5538 
5539 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
5540                                   uint64_t Address, const void *Decoder) {
5541   DecodeStatus S = MCDisassembler::Success;
5542   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
5543   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5544   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
5545   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5546   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5547 
5548   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5549     S = MCDisassembler::SoftFail;
5550 
5551   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
5552     return MCDisassembler::Fail;
5553   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5554     return MCDisassembler::Fail;
5555   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
5556     return MCDisassembler::Fail;
5557   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5558     return MCDisassembler::Fail;
5559   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5560     return MCDisassembler::Fail;
5561 
5562   return S;
5563 }
5564 
5565 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
5566                                   uint64_t Address, const void *Decoder) {
5567   DecodeStatus S = MCDisassembler::Success;
5568   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
5569   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5570   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
5571   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5572   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5573 
5574   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5575     S = MCDisassembler::SoftFail;
5576 
5577   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
5578     return MCDisassembler::Fail;
5579   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5580     return MCDisassembler::Fail;
5581   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
5582     return MCDisassembler::Fail;
5583   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5584     return MCDisassembler::Fail;
5585   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5586     return MCDisassembler::Fail;
5587 
5588   return S;
5589 }
5590 
5591 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
5592                              uint64_t Address, const void *Decoder) {
5593   DecodeStatus S = MCDisassembler::Success;
5594   unsigned pred = fieldFromInstruction(Insn, 4, 4);
5595   unsigned mask = fieldFromInstruction(Insn, 0, 4);
5596 
5597   if (pred == 0xF) {
5598     pred = 0xE;
5599     S = MCDisassembler::SoftFail;
5600   }
5601 
5602   if (mask == 0x0)
5603     return MCDisassembler::Fail;
5604 
5605   // IT masks are encoded as a sequence of replacement low-order bits
5606   // for the condition code. So if the low bit of the starting
5607   // condition code is 1, then we have to flip all the bits above the
5608   // terminating bit (which is the lowest 1 bit).
5609   if (pred & 1) {
5610     unsigned LowBit = mask & -mask;
5611     unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5612     mask ^= BitsAboveLowBit;
5613   }
5614 
5615   Inst.addOperand(MCOperand::createImm(pred));
5616   Inst.addOperand(MCOperand::createImm(mask));
5617   return S;
5618 }
5619 
5620 static DecodeStatus
5621 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5622                            uint64_t Address, const void *Decoder) {
5623   DecodeStatus S = MCDisassembler::Success;
5624 
5625   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5626   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5627   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5628   unsigned addr = fieldFromInstruction(Insn, 0, 8);
5629   unsigned W = fieldFromInstruction(Insn, 21, 1);
5630   unsigned U = fieldFromInstruction(Insn, 23, 1);
5631   unsigned P = fieldFromInstruction(Insn, 24, 1);
5632   bool writeback = (W == 1) | (P == 0);
5633 
5634   addr |= (U << 8) | (Rn << 9);
5635 
5636   if (writeback && (Rn == Rt || Rn == Rt2))
5637     Check(S, MCDisassembler::SoftFail);
5638   if (Rt == Rt2)
5639     Check(S, MCDisassembler::SoftFail);
5640 
5641   // Rt
5642   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5643     return MCDisassembler::Fail;
5644   // Rt2
5645   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5646     return MCDisassembler::Fail;
5647   // Writeback operand
5648   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5649     return MCDisassembler::Fail;
5650   // addr
5651   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5652     return MCDisassembler::Fail;
5653 
5654   return S;
5655 }
5656 
5657 static DecodeStatus
5658 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5659                            uint64_t Address, const void *Decoder) {
5660   DecodeStatus S = MCDisassembler::Success;
5661 
5662   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5663   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5664   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5665   unsigned addr = fieldFromInstruction(Insn, 0, 8);
5666   unsigned W = fieldFromInstruction(Insn, 21, 1);
5667   unsigned U = fieldFromInstruction(Insn, 23, 1);
5668   unsigned P = fieldFromInstruction(Insn, 24, 1);
5669   bool writeback = (W == 1) | (P == 0);
5670 
5671   addr |= (U << 8) | (Rn << 9);
5672 
5673   if (writeback && (Rn == Rt || Rn == Rt2))
5674     Check(S, MCDisassembler::SoftFail);
5675 
5676   // Writeback operand
5677   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5678     return MCDisassembler::Fail;
5679   // Rt
5680   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5681     return MCDisassembler::Fail;
5682   // Rt2
5683   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5684     return MCDisassembler::Fail;
5685   // addr
5686   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5687     return MCDisassembler::Fail;
5688 
5689   return S;
5690 }
5691 
5692 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5693                                 uint64_t Address, const void *Decoder) {
5694   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5695   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5696   if (sign1 != sign2) return MCDisassembler::Fail;
5697   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5698   assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5699   DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
5700 
5701   unsigned Val = fieldFromInstruction(Insn, 0, 8);
5702   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5703   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5704   // If sign, then it is decreasing the address.
5705   if (sign1) {
5706     // Following ARMv7 Architecture Manual, when the offset
5707     // is zero, it is decoded as a subw, not as a adr.w
5708     if (!Val) {
5709       Inst.setOpcode(ARM::t2SUBri12);
5710       Inst.addOperand(MCOperand::createReg(ARM::PC));
5711     } else
5712       Val = -Val;
5713   }
5714   Inst.addOperand(MCOperand::createImm(Val));
5715   return S;
5716 }
5717 
5718 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5719                                               uint64_t Address,
5720                                               const void *Decoder) {
5721   DecodeStatus S = MCDisassembler::Success;
5722 
5723   // Shift of "asr #32" is not allowed in Thumb2 mode.
5724   if (Val == 0x20) S = MCDisassembler::Fail;
5725   Inst.addOperand(MCOperand::createImm(Val));
5726   return S;
5727 }
5728 
5729 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5730                                uint64_t Address, const void *Decoder) {
5731   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
5732   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
5733   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
5734   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5735 
5736   if (pred == 0xF)
5737     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5738 
5739   DecodeStatus S = MCDisassembler::Success;
5740 
5741   if (Rt == Rn || Rn == Rt2)
5742     S = MCDisassembler::SoftFail;
5743 
5744   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5745     return MCDisassembler::Fail;
5746   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5747     return MCDisassembler::Fail;
5748   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5749     return MCDisassembler::Fail;
5750   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5751     return MCDisassembler::Fail;
5752 
5753   return S;
5754 }
5755 
5756 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5757                                 uint64_t Address, const void *Decoder) {
5758   const FeatureBitset &featureBits =
5759       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5760   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5761 
5762   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5763   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5764   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5765   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5766   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5767   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5768   unsigned op = fieldFromInstruction(Insn, 5, 1);
5769 
5770   DecodeStatus S = MCDisassembler::Success;
5771 
5772   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5773   if (!(imm & 0x38)) {
5774     if (cmode == 0xF) {
5775       if (op == 1) return MCDisassembler::Fail;
5776       Inst.setOpcode(ARM::VMOVv2f32);
5777     }
5778     if (hasFullFP16) {
5779       if (cmode == 0xE) {
5780         if (op == 1) {
5781           Inst.setOpcode(ARM::VMOVv1i64);
5782         } else {
5783           Inst.setOpcode(ARM::VMOVv8i8);
5784         }
5785       }
5786       if (cmode == 0xD) {
5787         if (op == 1) {
5788           Inst.setOpcode(ARM::VMVNv2i32);
5789         } else {
5790           Inst.setOpcode(ARM::VMOVv2i32);
5791         }
5792       }
5793       if (cmode == 0xC) {
5794         if (op == 1) {
5795           Inst.setOpcode(ARM::VMVNv2i32);
5796         } else {
5797           Inst.setOpcode(ARM::VMOVv2i32);
5798         }
5799       }
5800     }
5801     return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5802   }
5803 
5804   if (!(imm & 0x20)) return MCDisassembler::Fail;
5805 
5806   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5807     return MCDisassembler::Fail;
5808   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5809     return MCDisassembler::Fail;
5810   Inst.addOperand(MCOperand::createImm(64 - imm));
5811 
5812   return S;
5813 }
5814 
5815 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5816                                 uint64_t Address, const void *Decoder) {
5817   const FeatureBitset &featureBits =
5818       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5819   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5820 
5821   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5822   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5823   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5824   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5825   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5826   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5827   unsigned op = fieldFromInstruction(Insn, 5, 1);
5828 
5829   DecodeStatus S = MCDisassembler::Success;
5830 
5831   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5832   if (!(imm & 0x38)) {
5833     if (cmode == 0xF) {
5834       if (op == 1) return MCDisassembler::Fail;
5835       Inst.setOpcode(ARM::VMOVv4f32);
5836     }
5837     if (hasFullFP16) {
5838       if (cmode == 0xE) {
5839         if (op == 1) {
5840           Inst.setOpcode(ARM::VMOVv2i64);
5841         } else {
5842           Inst.setOpcode(ARM::VMOVv16i8);
5843         }
5844       }
5845       if (cmode == 0xD) {
5846         if (op == 1) {
5847           Inst.setOpcode(ARM::VMVNv4i32);
5848         } else {
5849           Inst.setOpcode(ARM::VMOVv4i32);
5850         }
5851       }
5852       if (cmode == 0xC) {
5853         if (op == 1) {
5854           Inst.setOpcode(ARM::VMVNv4i32);
5855         } else {
5856           Inst.setOpcode(ARM::VMOVv4i32);
5857         }
5858       }
5859     }
5860     return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5861   }
5862 
5863   if (!(imm & 0x20)) return MCDisassembler::Fail;
5864 
5865   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5866     return MCDisassembler::Fail;
5867   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5868     return MCDisassembler::Fail;
5869   Inst.addOperand(MCOperand::createImm(64 - imm));
5870 
5871   return S;
5872 }
5873 
5874 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5875                                                        unsigned Insn,
5876                                                        uint64_t Address,
5877                                                        const void *Decoder) {
5878   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5879   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5880   unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5881   Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5882   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5883   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5884   unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5885   unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5886 
5887   DecodeStatus S = MCDisassembler::Success;
5888 
5889   auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5890 
5891   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5892     return MCDisassembler::Fail;
5893   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5894     return MCDisassembler::Fail;
5895   if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5896     return MCDisassembler::Fail;
5897   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5898     return MCDisassembler::Fail;
5899   // The lane index does not have any bits in the encoding, because it can only
5900   // be 0.
5901   Inst.addOperand(MCOperand::createImm(0));
5902   Inst.addOperand(MCOperand::createImm(rotate));
5903 
5904   return S;
5905 }
5906 
5907 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5908                                 uint64_t Address, const void *Decoder) {
5909   DecodeStatus S = MCDisassembler::Success;
5910 
5911   unsigned Rn = fieldFromInstruction(Val, 16, 4);
5912   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5913   unsigned Rm = fieldFromInstruction(Val, 0, 4);
5914   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5915   unsigned Cond = fieldFromInstruction(Val, 28, 4);
5916 
5917   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5918     S = MCDisassembler::SoftFail;
5919 
5920   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5921     return MCDisassembler::Fail;
5922   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5923     return MCDisassembler::Fail;
5924   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5925     return MCDisassembler::Fail;
5926   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5927     return MCDisassembler::Fail;
5928   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5929     return MCDisassembler::Fail;
5930 
5931   return S;
5932 }
5933 
5934 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5935                                             uint64_t Address, const void *Decoder) {
5936   DecodeStatus S = MCDisassembler::Success;
5937 
5938   unsigned CRm = fieldFromInstruction(Val, 0, 4);
5939   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5940   unsigned cop = fieldFromInstruction(Val, 8, 4);
5941   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5942   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5943 
5944   if ((cop & ~0x1) == 0xa)
5945     return MCDisassembler::Fail;
5946 
5947   if (Rt == Rt2)
5948     S = MCDisassembler::SoftFail;
5949 
5950   // We have to check if the instruction is MRRC2
5951   // or MCRR2 when constructing the operands for
5952   // Inst. Reason is because MRRC2 stores to two
5953   // registers so it's tablegen desc has has two
5954   // outputs whereas MCRR doesn't store to any
5955   // registers so all of it's operands are listed
5956   // as inputs, therefore the operand order for
5957   // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5958   // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5959 
5960   if (Inst.getOpcode() == ARM::MRRC2) {
5961     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5962       return MCDisassembler::Fail;
5963     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5964       return MCDisassembler::Fail;
5965   }
5966   Inst.addOperand(MCOperand::createImm(cop));
5967   Inst.addOperand(MCOperand::createImm(opc1));
5968   if (Inst.getOpcode() == ARM::MCRR2) {
5969     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5970       return MCDisassembler::Fail;
5971     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5972       return MCDisassembler::Fail;
5973   }
5974   Inst.addOperand(MCOperand::createImm(CRm));
5975 
5976   return S;
5977 }
5978 
5979 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5980                                          uint64_t Address,
5981                                          const void *Decoder) {
5982   const FeatureBitset &featureBits =
5983       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5984   DecodeStatus S = MCDisassembler::Success;
5985 
5986   // Add explicit operand for the destination sysreg, for cases where
5987   // we have to model it for code generation purposes.
5988   switch (Inst.getOpcode()) {
5989   case ARM::VMSR_FPSCR_NZCVQC:
5990     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5991     break;
5992   case ARM::VMSR_P0:
5993     Inst.addOperand(MCOperand::createReg(ARM::VPR));
5994     break;
5995   }
5996 
5997   if (Inst.getOpcode() != ARM::FMSTAT) {
5998     unsigned Rt = fieldFromInstruction(Val, 12, 4);
5999 
6000     if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
6001       if (Rt == 13 || Rt == 15)
6002         S = MCDisassembler::SoftFail;
6003       Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
6004     } else
6005       Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
6006   }
6007 
6008   // Add explicit operand for the source sysreg, similarly to above.
6009   switch (Inst.getOpcode()) {
6010   case ARM::VMRS_FPSCR_NZCVQC:
6011     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6012     break;
6013   case ARM::VMRS_P0:
6014     Inst.addOperand(MCOperand::createReg(ARM::VPR));
6015     break;
6016   }
6017 
6018   if (featureBits[ARM::ModeThumb]) {
6019     Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6020     Inst.addOperand(MCOperand::createReg(0));
6021   } else {
6022     unsigned pred = fieldFromInstruction(Val, 28, 4);
6023     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6024       return MCDisassembler::Fail;
6025   }
6026 
6027   return S;
6028 }
6029 
6030 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
6031 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
6032                                          uint64_t Address,
6033                                          const void *Decoder) {
6034   DecodeStatus S = MCDisassembler::Success;
6035   if (Val == 0 && !zeroPermitted)
6036     S = MCDisassembler::Fail;
6037 
6038   uint64_t DecVal;
6039   if (isSigned)
6040     DecVal = SignExtend32<size + 1>(Val << 1);
6041   else
6042     DecVal = (Val << 1);
6043 
6044   if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
6045                                 Decoder))
6046     Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
6047   return S;
6048 }
6049 
6050 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
6051                                                uint64_t Address,
6052                                                const void *Decoder) {
6053 
6054   uint64_t LocImm = Inst.getOperand(0).getImm();
6055   Val = LocImm + (2 << Val);
6056   if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
6057                                 Decoder))
6058     Inst.addOperand(MCOperand::createImm(Val));
6059   return MCDisassembler::Success;
6060 }
6061 
6062 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
6063                                           uint64_t Address,
6064                                           const void *Decoder) {
6065   if (Val >= ARMCC::AL)  // also exclude the non-condition NV
6066     return MCDisassembler::Fail;
6067   Inst.addOperand(MCOperand::createImm(Val));
6068   return MCDisassembler::Success;
6069 }
6070 
6071 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
6072                                  const void *Decoder) {
6073   DecodeStatus S = MCDisassembler::Success;
6074 
6075   if (Inst.getOpcode() == ARM::MVE_LCTP)
6076     return S;
6077 
6078   unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
6079                  fieldFromInstruction(Insn, 1, 10) << 1;
6080   switch (Inst.getOpcode()) {
6081   case ARM::t2LEUpdate:
6082   case ARM::MVE_LETP:
6083     Inst.addOperand(MCOperand::createReg(ARM::LR));
6084     Inst.addOperand(MCOperand::createReg(ARM::LR));
6085     LLVM_FALLTHROUGH;
6086   case ARM::t2LE:
6087     if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
6088                    Inst, Imm, Address, Decoder)))
6089       return MCDisassembler::Fail;
6090     break;
6091   case ARM::t2WLS:
6092   case ARM::MVE_WLSTP_8:
6093   case ARM::MVE_WLSTP_16:
6094   case ARM::MVE_WLSTP_32:
6095   case ARM::MVE_WLSTP_64:
6096     Inst.addOperand(MCOperand::createReg(ARM::LR));
6097     if (!Check(S,
6098                DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
6099                                        Address, Decoder)) ||
6100         !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
6101                    Inst, Imm, Address, Decoder)))
6102       return MCDisassembler::Fail;
6103     break;
6104   case ARM::t2DLS:
6105   case ARM::MVE_DLSTP_8:
6106   case ARM::MVE_DLSTP_16:
6107   case ARM::MVE_DLSTP_32:
6108   case ARM::MVE_DLSTP_64:
6109     unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6110     if (Rn == 0xF) {
6111       // Enforce all the rest of the instruction bits in LCTP, which
6112       // won't have been reliably checked based on LCTP's own tablegen
6113       // record, because we came to this decode by a roundabout route.
6114       uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6115       if ((Insn & ~SBZMask) != CanonicalLCTP)
6116         return MCDisassembler::Fail;   // a mandatory bit is wrong: hard fail
6117       if (Insn != CanonicalLCTP)
6118         Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
6119 
6120       Inst.setOpcode(ARM::MVE_LCTP);
6121     } else {
6122       Inst.addOperand(MCOperand::createReg(ARM::LR));
6123       if (!Check(S, DecoderGPRRegisterClass(Inst,
6124                                             fieldFromInstruction(Insn, 16, 4),
6125                                             Address, Decoder)))
6126         return MCDisassembler::Fail;
6127     }
6128     break;
6129   }
6130   return S;
6131 }
6132 
6133 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6134                                            uint64_t Address,
6135                                            const void *Decoder) {
6136   DecodeStatus S = MCDisassembler::Success;
6137 
6138   if (Val == 0)
6139     Val = 32;
6140 
6141   Inst.addOperand(MCOperand::createImm(Val));
6142 
6143   return S;
6144 }
6145 
6146 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6147                                    uint64_t Address, const void *Decoder) {
6148   if ((RegNo) + 1 > 11)
6149     return MCDisassembler::Fail;
6150 
6151   unsigned Register = GPRDecoderTable[(RegNo) + 1];
6152   Inst.addOperand(MCOperand::createReg(Register));
6153   return MCDisassembler::Success;
6154 }
6155 
6156 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6157                                    uint64_t Address, const void *Decoder) {
6158   if ((RegNo) > 14)
6159     return MCDisassembler::Fail;
6160 
6161   unsigned Register = GPRDecoderTable[(RegNo)];
6162   Inst.addOperand(MCOperand::createReg(Register));
6163   return MCDisassembler::Success;
6164 }
6165 
6166 static DecodeStatus
6167 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6168                                         uint64_t Address, const void *Decoder) {
6169   if (RegNo == 15) {
6170     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6171     return MCDisassembler::Success;
6172   }
6173 
6174   unsigned Register = GPRDecoderTable[RegNo];
6175   Inst.addOperand(MCOperand::createReg(Register));
6176 
6177   if (RegNo == 13)
6178     return MCDisassembler::SoftFail;
6179 
6180   return MCDisassembler::Success;
6181 }
6182 
6183 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6184                                   const void *Decoder) {
6185   DecodeStatus S = MCDisassembler::Success;
6186 
6187   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6188   Inst.addOperand(MCOperand::createReg(0));
6189   if (Inst.getOpcode() == ARM::VSCCLRMD) {
6190     unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
6191                        (fieldFromInstruction(Insn, 12, 4) << 8) |
6192                        (fieldFromInstruction(Insn, 22, 1) << 12);
6193     if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
6194       return MCDisassembler::Fail;
6195     }
6196   } else {
6197     unsigned reglist = fieldFromInstruction(Insn, 0, 8) |
6198                        (fieldFromInstruction(Insn, 22, 1) << 8) |
6199                        (fieldFromInstruction(Insn, 12, 4) << 9);
6200     if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
6201       return MCDisassembler::Fail;
6202     }
6203   }
6204   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6205 
6206   return S;
6207 }
6208 
6209 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6210                               uint64_t Address,
6211                               const void *Decoder) {
6212   if (RegNo > 7)
6213     return MCDisassembler::Fail;
6214 
6215   unsigned Register = QPRDecoderTable[RegNo];
6216   Inst.addOperand(MCOperand::createReg(Register));
6217   return MCDisassembler::Success;
6218 }
6219 
6220 static const uint16_t QQPRDecoderTable[] = {
6221      ARM::Q0_Q1,  ARM::Q1_Q2,  ARM::Q2_Q3,  ARM::Q3_Q4,
6222      ARM::Q4_Q5,  ARM::Q5_Q6,  ARM::Q6_Q7
6223 };
6224 
6225 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6226                                              uint64_t Address,
6227                                              const void *Decoder) {
6228   if (RegNo > 6)
6229     return MCDisassembler::Fail;
6230 
6231   unsigned Register = QQPRDecoderTable[RegNo];
6232   Inst.addOperand(MCOperand::createReg(Register));
6233   return MCDisassembler::Success;
6234 }
6235 
6236 static const uint16_t QQQQPRDecoderTable[] = {
6237      ARM::Q0_Q1_Q2_Q3,  ARM::Q1_Q2_Q3_Q4,  ARM::Q2_Q3_Q4_Q5,
6238      ARM::Q3_Q4_Q5_Q6,  ARM::Q4_Q5_Q6_Q7
6239 };
6240 
6241 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6242                                                uint64_t Address,
6243                                                const void *Decoder) {
6244   if (RegNo > 4)
6245     return MCDisassembler::Fail;
6246 
6247   unsigned Register = QQQQPRDecoderTable[RegNo];
6248   Inst.addOperand(MCOperand::createReg(Register));
6249   return MCDisassembler::Success;
6250 }
6251 
6252 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6253                                          uint64_t Address,
6254                                          const void *Decoder) {
6255   DecodeStatus S = MCDisassembler::Success;
6256 
6257   // Parse VPT mask and encode it in the MCInst as an immediate with the same
6258   // format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1 and
6259   // 't' as 0 and finish with a 1.
6260   unsigned Imm = 0;
6261   // We always start with a 't'.
6262   unsigned CurBit = 0;
6263   for (int i = 3; i >= 0; --i) {
6264     // If the bit we are looking at is not the same as last one, invert the
6265     // CurBit, if it is the same leave it as is.
6266     CurBit ^= (Val >> i) & 1U;
6267 
6268     // Encode the CurBit at the right place in the immediate.
6269     Imm |= (CurBit << i);
6270 
6271     // If we are done, finish the encoding with a 1.
6272     if ((Val & ~(~0U << i)) == 0) {
6273       Imm |= 1U << i;
6274       break;
6275     }
6276   }
6277 
6278   Inst.addOperand(MCOperand::createImm(Imm));
6279 
6280   return S;
6281 }
6282 
6283 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6284                                         uint64_t Address, const void *Decoder) {
6285   // The vpred_r operand type includes an MQPR register field derived
6286   // from the encoding. But we don't actually want to add an operand
6287   // to the MCInst at this stage, because AddThumbPredicate will do it
6288   // later, and will infer the register number from the TIED_TO
6289   // constraint. So this is a deliberately empty decoder method that
6290   // will inhibit the auto-generated disassembly code from adding an
6291   // operand at all.
6292   return MCDisassembler::Success;
6293 }
6294 
6295 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
6296                                                       unsigned Val,
6297                                                       uint64_t Address,
6298                                                       const void *Decoder) {
6299   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6300   return MCDisassembler::Success;
6301 }
6302 
6303 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
6304                                                       unsigned Val,
6305                                                       uint64_t Address,
6306                                                       const void *Decoder) {
6307   unsigned Code;
6308   switch (Val & 0x3) {
6309   case 0:
6310     Code = ARMCC::GE;
6311     break;
6312   case 1:
6313     Code = ARMCC::LT;
6314     break;
6315   case 2:
6316     Code = ARMCC::GT;
6317     break;
6318   case 3:
6319     Code = ARMCC::LE;
6320     break;
6321   }
6322   Inst.addOperand(MCOperand::createImm(Code));
6323   return MCDisassembler::Success;
6324 }
6325 
6326 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
6327                                                       unsigned Val,
6328                                                       uint64_t Address,
6329                                                       const void *Decoder) {
6330   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6331   return MCDisassembler::Success;
6332 }
6333 
6334 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
6335                                                      uint64_t Address,
6336                                                      const void *Decoder) {
6337   unsigned Code;
6338   switch (Val) {
6339   default:
6340     return MCDisassembler::Fail;
6341   case 0:
6342     Code = ARMCC::EQ;
6343     break;
6344   case 1:
6345     Code = ARMCC::NE;
6346     break;
6347   case 4:
6348     Code = ARMCC::GE;
6349     break;
6350   case 5:
6351     Code = ARMCC::LT;
6352     break;
6353   case 6:
6354     Code = ARMCC::GT;
6355     break;
6356   case 7:
6357     Code = ARMCC::LE;
6358     break;
6359   }
6360 
6361   Inst.addOperand(MCOperand::createImm(Code));
6362   return MCDisassembler::Success;
6363 }
6364 
6365 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6366                                          uint64_t Address, const void *Decoder) {
6367   DecodeStatus S = MCDisassembler::Success;
6368 
6369   unsigned DecodedVal = 64 - Val;
6370 
6371   switch (Inst.getOpcode()) {
6372   case ARM::MVE_VCVTf16s16_fix:
6373   case ARM::MVE_VCVTs16f16_fix:
6374   case ARM::MVE_VCVTf16u16_fix:
6375   case ARM::MVE_VCVTu16f16_fix:
6376     if (DecodedVal > 16)
6377       return MCDisassembler::Fail;
6378     break;
6379   case ARM::MVE_VCVTf32s32_fix:
6380   case ARM::MVE_VCVTs32f32_fix:
6381   case ARM::MVE_VCVTf32u32_fix:
6382   case ARM::MVE_VCVTu32f32_fix:
6383     if (DecodedVal > 32)
6384       return MCDisassembler::Fail;
6385     break;
6386   }
6387 
6388   Inst.addOperand(MCOperand::createImm(64 - Val));
6389 
6390   return S;
6391 }
6392 
6393 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
6394   switch (Opcode) {
6395   case ARM::VSTR_P0_off:
6396   case ARM::VSTR_P0_pre:
6397   case ARM::VSTR_P0_post:
6398   case ARM::VLDR_P0_off:
6399   case ARM::VLDR_P0_pre:
6400   case ARM::VLDR_P0_post:
6401     return ARM::P0;
6402   default:
6403     return 0;
6404   }
6405 }
6406 
6407 template<bool Writeback>
6408 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6409                                           uint64_t Address,
6410                                           const void *Decoder) {
6411   switch (Inst.getOpcode()) {
6412   case ARM::VSTR_FPSCR_pre:
6413   case ARM::VSTR_FPSCR_NZCVQC_pre:
6414   case ARM::VLDR_FPSCR_pre:
6415   case ARM::VLDR_FPSCR_NZCVQC_pre:
6416   case ARM::VSTR_FPSCR_off:
6417   case ARM::VSTR_FPSCR_NZCVQC_off:
6418   case ARM::VLDR_FPSCR_off:
6419   case ARM::VLDR_FPSCR_NZCVQC_off:
6420   case ARM::VSTR_FPSCR_post:
6421   case ARM::VSTR_FPSCR_NZCVQC_post:
6422   case ARM::VLDR_FPSCR_post:
6423   case ARM::VLDR_FPSCR_NZCVQC_post:
6424     const FeatureBitset &featureBits =
6425         ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6426 
6427     if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6428       return MCDisassembler::Fail;
6429   }
6430 
6431   DecodeStatus S = MCDisassembler::Success;
6432   if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6433     Inst.addOperand(MCOperand::createReg(Sysreg));
6434   unsigned Rn = fieldFromInstruction(Val, 16, 4);
6435   unsigned addr = fieldFromInstruction(Val, 0, 7) |
6436                   (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6437 
6438   if (Writeback) {
6439     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6440       return MCDisassembler::Fail;
6441   }
6442   if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
6443     return MCDisassembler::Fail;
6444 
6445   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6446   Inst.addOperand(MCOperand::createReg(0));
6447 
6448   return S;
6449 }
6450 
6451 static inline DecodeStatus DecodeMVE_MEM_pre(
6452   MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
6453   unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6454   DecodeStatus S = MCDisassembler::Success;
6455 
6456   unsigned Qd = fieldFromInstruction(Val, 13, 3);
6457   unsigned addr = fieldFromInstruction(Val, 0, 7) |
6458                   (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6459 
6460   if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6461     return MCDisassembler::Fail;
6462   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6463     return MCDisassembler::Fail;
6464   if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6465     return MCDisassembler::Fail;
6466 
6467   return S;
6468 }
6469 
6470 template <int shift>
6471 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6472                                         uint64_t Address, const void *Decoder) {
6473   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6474                            fieldFromInstruction(Val, 16, 3),
6475                            DecodetGPRRegisterClass,
6476                            DecodeTAddrModeImm7<shift>);
6477 }
6478 
6479 template <int shift>
6480 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6481                                         uint64_t Address, const void *Decoder) {
6482   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6483                            fieldFromInstruction(Val, 16, 4),
6484                            DecoderGPRRegisterClass,
6485                            DecodeT2AddrModeImm7<shift,1>);
6486 }
6487 
6488 template <int shift>
6489 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6490                                         uint64_t Address, const void *Decoder) {
6491   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6492                            fieldFromInstruction(Val, 17, 3),
6493                            DecodeMQPRRegisterClass,
6494                            DecodeMveAddrModeQ<shift>);
6495 }
6496 
6497 template<unsigned MinLog, unsigned MaxLog>
6498 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6499                                           uint64_t Address,
6500                                           const void *Decoder) {
6501   DecodeStatus S = MCDisassembler::Success;
6502 
6503   if (Val < MinLog || Val > MaxLog)
6504     return MCDisassembler::Fail;
6505 
6506   Inst.addOperand(MCOperand::createImm(1LL << Val));
6507   return S;
6508 }
6509 
6510 template<unsigned start>
6511 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
6512                                                     uint64_t Address,
6513                                                     const void *Decoder) {
6514   DecodeStatus S = MCDisassembler::Success;
6515 
6516   Inst.addOperand(MCOperand::createImm(start + Val));
6517 
6518   return S;
6519 }
6520 
6521 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6522                                          uint64_t Address, const void *Decoder) {
6523   DecodeStatus S = MCDisassembler::Success;
6524   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6525   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6526   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6527                  fieldFromInstruction(Insn, 13, 3));
6528   unsigned index = fieldFromInstruction(Insn, 4, 1);
6529 
6530   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6531     return MCDisassembler::Fail;
6532   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6533     return MCDisassembler::Fail;
6534   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6535     return MCDisassembler::Fail;
6536   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6537     return MCDisassembler::Fail;
6538   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6539     return MCDisassembler::Fail;
6540 
6541   return S;
6542 }
6543 
6544 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6545                                          uint64_t Address, const void *Decoder) {
6546   DecodeStatus S = MCDisassembler::Success;
6547   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6548   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6549   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6550                  fieldFromInstruction(Insn, 13, 3));
6551   unsigned index = fieldFromInstruction(Insn, 4, 1);
6552 
6553   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6554     return MCDisassembler::Fail;
6555   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6556     return MCDisassembler::Fail;
6557   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6558     return MCDisassembler::Fail;
6559   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6560     return MCDisassembler::Fail;
6561   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6562     return MCDisassembler::Fail;
6563   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6564     return MCDisassembler::Fail;
6565 
6566   return S;
6567 }
6568 
6569 static DecodeStatus DecodeMVEOverlappingLongShift(
6570   MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
6571   DecodeStatus S = MCDisassembler::Success;
6572 
6573   unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
6574   unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
6575   unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6576 
6577   if (RdaHi == 14) {
6578     // This value of RdaHi (really indicating pc, because RdaHi has to
6579     // be an odd-numbered register, so the low bit will be set by the
6580     // decode function below) indicates that we must decode as SQRSHR
6581     // or UQRSHL, which both have a single Rda register field with all
6582     // four bits.
6583     unsigned Rda = fieldFromInstruction(Insn, 16, 4);
6584 
6585     switch (Inst.getOpcode()) {
6586       case ARM::MVE_ASRLr:
6587       case ARM::MVE_SQRSHRL:
6588         Inst.setOpcode(ARM::MVE_SQRSHR);
6589         break;
6590       case ARM::MVE_LSLLr:
6591       case ARM::MVE_UQRSHLL:
6592         Inst.setOpcode(ARM::MVE_UQRSHL);
6593         break;
6594       default:
6595         llvm_unreachable("Unexpected starting opcode!");
6596     }
6597 
6598     // Rda as output parameter
6599     if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6600       return MCDisassembler::Fail;
6601 
6602     // Rda again as input parameter
6603     if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6604       return MCDisassembler::Fail;
6605 
6606     // Rm, the amount to shift by
6607     if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6608       return MCDisassembler::Fail;
6609 
6610     if (fieldFromInstruction (Insn, 6, 3) != 4)
6611       return MCDisassembler::SoftFail;
6612 
6613     if (Rda == Rm)
6614       return MCDisassembler::SoftFail;
6615 
6616     return S;
6617   }
6618 
6619   // Otherwise, we decode as whichever opcode our caller has already
6620   // put into Inst. Those all look the same:
6621 
6622   // RdaLo,RdaHi as output parameters
6623   if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6624     return MCDisassembler::Fail;
6625   if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6626     return MCDisassembler::Fail;
6627 
6628   // RdaLo,RdaHi again as input parameters
6629   if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6630     return MCDisassembler::Fail;
6631   if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6632     return MCDisassembler::Fail;
6633 
6634   // Rm, the amount to shift by
6635   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6636     return MCDisassembler::Fail;
6637 
6638   if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6639       Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6640     unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
6641     // Saturate, the bit position for saturation
6642     Inst.addOperand(MCOperand::createImm(Saturate));
6643   }
6644 
6645   return S;
6646 }
6647 
6648 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
6649                                       const void *Decoder) {
6650   DecodeStatus S = MCDisassembler::Success;
6651   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6652                  fieldFromInstruction(Insn, 13, 3));
6653   unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
6654                  fieldFromInstruction(Insn, 1, 3));
6655   unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
6656 
6657   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6658     return MCDisassembler::Fail;
6659   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6660     return MCDisassembler::Fail;
6661   if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6662     return MCDisassembler::Fail;
6663 
6664   return S;
6665 }
6666 
6667 template<bool scalar, OperandDecoder predicate_decoder>
6668 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6669                                   const void *Decoder) {
6670   DecodeStatus S = MCDisassembler::Success;
6671   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6672   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
6673   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6674     return MCDisassembler::Fail;
6675 
6676   unsigned fc;
6677 
6678   if (scalar) {
6679     fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6680          fieldFromInstruction(Insn, 7, 1) |
6681          fieldFromInstruction(Insn, 5, 1) << 1;
6682     unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6683     if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6684       return MCDisassembler::Fail;
6685   } else {
6686     fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6687          fieldFromInstruction(Insn, 7, 1) |
6688          fieldFromInstruction(Insn, 0, 1) << 1;
6689     unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
6690                   fieldFromInstruction(Insn, 1, 3);
6691     if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6692       return MCDisassembler::Fail;
6693   }
6694 
6695   if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
6696     return MCDisassembler::Fail;
6697 
6698   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
6699   Inst.addOperand(MCOperand::createReg(0));
6700   Inst.addOperand(MCOperand::createImm(0));
6701 
6702   return S;
6703 }
6704 
6705 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6706                                   const void *Decoder) {
6707   DecodeStatus S = MCDisassembler::Success;
6708   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6709   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6710   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6711     return MCDisassembler::Fail;
6712   return S;
6713 }
6714 
6715 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
6716                                    const void *Decoder) {
6717   DecodeStatus S = MCDisassembler::Success;
6718   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6719   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6720   return S;
6721 }
6722 
6723 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
6724                                         uint64_t Address, const void *Decoder) {
6725   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
6726   const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6727   const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
6728                          fieldFromInstruction(Insn, 12, 3) << 8 |
6729                          fieldFromInstruction(Insn, 0, 8);
6730   const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
6731   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
6732   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
6733   unsigned S = fieldFromInstruction(Insn, 20, 1);
6734   if (sign1 != sign2)
6735     return MCDisassembler::Fail;
6736 
6737   // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
6738   DecodeStatus DS = MCDisassembler::Success;
6739   if ((!Check(DS,
6740               DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
6741       (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
6742     return MCDisassembler::Fail;
6743   if (TypeT3) {
6744     Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
6745     Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
6746   } else {
6747     Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
6748     if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
6749       return MCDisassembler::Fail;
6750     if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
6751       return MCDisassembler::Fail;
6752   }
6753 
6754   return DS;
6755 }
6756