xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMBaseInstrInfo.h"
10 #include "MCTargetDesc/ARMAddressingModes.h"
11 #include "MCTargetDesc/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMMCTargetDesc.h"
13 #include "TargetInfo/ARMTargetInfo.h"
14 #include "Utils/ARMBaseInfo.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
17 #include "llvm/MC/MCFixedLenDisassembler.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/SubtargetFeature.h"
22 #include "llvm/Support/Compiler.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include <algorithm>
28 #include <cassert>
29 #include <cstdint>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "arm-disassembler"
35 
36 using DecodeStatus = MCDisassembler::DecodeStatus;
37 
38 namespace {
39 
40   // Handles the condition code status of instructions in IT blocks
41   class ITStatus
42   {
43     public:
44       // Returns the condition code for instruction in IT block
45       unsigned getITCC() {
46         unsigned CC = ARMCC::AL;
47         if (instrInITBlock())
48           CC = ITStates.back();
49         return CC;
50       }
51 
52       // Advances the IT block state to the next T or E
53       void advanceITState() {
54         ITStates.pop_back();
55       }
56 
57       // Returns true if the current instruction is in an IT block
58       bool instrInITBlock() {
59         return !ITStates.empty();
60       }
61 
62       // Returns true if current instruction is the last instruction in an IT block
63       bool instrLastInITBlock() {
64         return ITStates.size() == 1;
65       }
66 
67       // Called when decoding an IT instruction. Sets the IT state for
68       // the following instructions that for the IT block. Firstcond
69       // corresponds to the field in the IT instruction encoding; Mask
70       // is in the MCOperand format in which 1 means 'else' and 0 'then'.
71       void setITState(char Firstcond, char Mask) {
72         // (3 - the number of trailing zeros) is the number of then / else.
73         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
74         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
75         assert(NumTZ <= 3 && "Invalid IT mask!");
76         // push condition codes onto the stack the correct order for the pops
77         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
78           unsigned Else = (Mask >> Pos) & 1;
79           ITStates.push_back(CCBits ^ Else);
80         }
81         ITStates.push_back(CCBits);
82       }
83 
84     private:
85       std::vector<unsigned char> ITStates;
86   };
87 
88   class VPTStatus
89   {
90     public:
91       unsigned getVPTPred() {
92         unsigned Pred = ARMVCC::None;
93         if (instrInVPTBlock())
94           Pred = VPTStates.back();
95         return Pred;
96       }
97 
98       void advanceVPTState() {
99         VPTStates.pop_back();
100       }
101 
102       bool instrInVPTBlock() {
103         return !VPTStates.empty();
104       }
105 
106       bool instrLastInVPTBlock() {
107         return VPTStates.size() == 1;
108       }
109 
110       void setVPTState(char Mask) {
111         // (3 - the number of trailing zeros) is the number of then / else.
112         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
113         assert(NumTZ <= 3 && "Invalid VPT mask!");
114         // push predicates onto the stack the correct order for the pops
115         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
116           bool T = ((Mask >> Pos) & 1) == 0;
117           if (T)
118             VPTStates.push_back(ARMVCC::Then);
119           else
120             VPTStates.push_back(ARMVCC::Else);
121         }
122         VPTStates.push_back(ARMVCC::Then);
123       }
124 
125     private:
126       SmallVector<unsigned char, 4> VPTStates;
127   };
128 
129 /// ARM disassembler for all ARM platforms.
130 class ARMDisassembler : public MCDisassembler {
131 public:
132   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
133     MCDisassembler(STI, Ctx) {
134   }
135 
136   ~ARMDisassembler() override = default;
137 
138   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
139                               ArrayRef<uint8_t> Bytes, uint64_t Address,
140                               raw_ostream &CStream) const override;
141 
142 private:
143   DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size,
144                                  ArrayRef<uint8_t> Bytes, uint64_t Address,
145                                  raw_ostream &CStream) const;
146 
147   DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size,
148                                    ArrayRef<uint8_t> Bytes, uint64_t Address,
149                                    raw_ostream &CStream) const;
150 
151   mutable ITStatus ITBlock;
152   mutable VPTStatus VPTBlock;
153 
154   DecodeStatus AddThumbPredicate(MCInst&) const;
155   void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const;
156 };
157 
158 } // end anonymous namespace
159 
160 static bool Check(DecodeStatus &Out, DecodeStatus In) {
161   switch (In) {
162     case MCDisassembler::Success:
163       // Out stays the same.
164       return true;
165     case MCDisassembler::SoftFail:
166       Out = In;
167       return true;
168     case MCDisassembler::Fail:
169       Out = In;
170       return false;
171   }
172   llvm_unreachable("Invalid DecodeStatus!");
173 }
174 
175 // Forward declare these because the autogenerated code will reference them.
176 // Definitions are further down.
177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
178                                    uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
180                                    uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
182                                    uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
184                                    uint64_t Address, const void *Decoder);
185 static DecodeStatus
186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
187                                         uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
189                                                unsigned RegNo, uint64_t Address,
190                                                const void *Decoder);
191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
192                                                unsigned RegNo, uint64_t Address,
193                                                const void *Decoder);
194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
195                                                unsigned RegNo, uint64_t Address,
196                                                const void *Decoder);
197 static DecodeStatus DecodeGPRwithZRnospRegisterClass(
198     MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
200                                    uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
202                                    uint64_t Address, const void *Decoder);
203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
204                                    uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
206                                    uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
208                                    uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
210                                              uint64_t Address,
211                                              const void *Decoder);
212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
213                                    uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
215                                    uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
217                                    uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
219                                    uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
221                                    uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
223                                                 unsigned RegNo,
224                                                 uint64_t Address,
225                                                 const void *Decoder);
226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
227                                    uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
229                                    uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
231                                    uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
233                                    uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
235                                    uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
237                                unsigned RegNo, uint64_t Address,
238                                const void *Decoder);
239 
240 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
241                                uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
243                                uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
245                                uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
247                                uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
249                                uint64_t Address, const void *Decoder);
250 
251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
252                                uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
254                                uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
256                                                   unsigned Insn,
257                                                   uint64_t Address,
258                                                   const void *Decoder);
259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
260                                uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
262                                uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
264                                uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
266                                uint64_t Address, const void *Decoder);
267 
268 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
269                                                   unsigned Insn,
270                                                   uint64_t Adddress,
271                                                   const void *Decoder);
272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
273                                uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
275                                uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
277                                uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
279                                uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
281                                uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
283                                uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
285                                uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
287                                uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
289                                uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
291                                uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
293                                uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
295                                uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
297                                uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
299                                uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
301                                uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
303                                uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
305                                uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
307                                uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
309                                uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
311                                uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
313                                uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
315                                uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
317                                uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
319                                uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
321                                uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val,
323                                uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
325                                uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
327                                uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
329                                uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
331                                uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
333                                uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
335                                uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
337                                uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
339                                uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
341                                uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
343                                uint64_t Address, const void *Decoder);
344 template<int shift>
345 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
346                                uint64_t Address, const void *Decoder);
347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
348                                uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
350                                uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
352                                uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
354                                uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
356                                uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
358                                uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
360                                uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
362                                uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
364                                uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
366                                uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
368                                uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
370                                uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
372                                uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
374                                uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
376                                uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
378                                uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
380                                uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
382                                uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
384                                uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
386                                uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
388                                uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
390                                uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
392                                 uint64_t Address, const void *Decoder);
393 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
394                                 uint64_t Address, const void *Decoder);
395 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
396                                          uint64_t Address, const void *Decoder);
397 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
398                                                        unsigned Val,
399                                                        uint64_t Address,
400                                                        const void *Decoder);
401 
402 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
403                                uint64_t Address, const void *Decoder);
404 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
405                                uint64_t Address, const void *Decoder);
406 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
407                                uint64_t Address, const void *Decoder);
408 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
409                                uint64_t Address, const void *Decoder);
410 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
411                                uint64_t Address, const void *Decoder);
412 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
413                                uint64_t Address, const void *Decoder);
414 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
415                                uint64_t Address, const void *Decoder);
416 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
417                                uint64_t Address, const void *Decoder);
418 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
419                                uint64_t Address, const void *Decoder);
420 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
421                                uint64_t Address, const void *Decoder);
422 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
423                                uint64_t Address, const void* Decoder);
424 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
425                                uint64_t Address, const void* Decoder);
426 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
427                                uint64_t Address, const void* Decoder);
428 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
429                                uint64_t Address, const void* Decoder);
430 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
431                                uint64_t Address, const void *Decoder);
432 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val,
433                                uint64_t Address, const void *Decoder);
434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
435                                uint64_t Address, const void *Decoder);
436 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
437                                            uint64_t Address,
438                                            const void *Decoder);
439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
440                                uint64_t Address, const void *Decoder);
441 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
442                                uint64_t Address, const void *Decoder);
443 template<int shift>
444 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
445                                uint64_t Address, const void *Decoder);
446 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
447                                uint64_t Address, const void *Decoder);
448 template<int shift>
449 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
450                                uint64_t Address, const void *Decoder);
451 template<int shift, int WriteBack>
452 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
453                                uint64_t Address, const void *Decoder);
454 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
455                                uint64_t Address, const void *Decoder);
456 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
457                                 uint64_t Address, const void *Decoder);
458 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
459                                 uint64_t Address, const void *Decoder);
460 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
461                                 uint64_t Address, const void *Decoder);
462 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
463                                 uint64_t Address, const void *Decoder);
464 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
465                                 uint64_t Address, const void *Decoder);
466 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
467                                 uint64_t Address, const void *Decoder);
468 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
469                                 uint64_t Address, const void *Decoder);
470 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
471                                 uint64_t Address, const void *Decoder);
472 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
473                                 uint64_t Address, const void *Decoder);
474 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
475                                 uint64_t Address, const void *Decoder);
476 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
477                                 uint64_t Address, const void *Decoder);
478 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
479                                uint64_t Address, const void *Decoder);
480 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
481                                uint64_t Address, const void *Decoder);
482 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
483                                 uint64_t Address, const void *Decoder);
484 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
485                                 uint64_t Address, const void *Decoder);
486 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
487                                 uint64_t Address, const void *Decoder);
488 
489 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
490                                 uint64_t Address, const void *Decoder);
491 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
492                                             uint64_t Address, const void *Decoder);
493 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
494                                          uint64_t Address, const void *Decoder);
495 
496 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
497 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
498                                          uint64_t Address, const void *Decoder);
499 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
500                                                uint64_t Address,
501                                                const void *Decoder);
502 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
503                                           uint64_t Address,
504                                           const void *Decoder);
505 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
506                                  const void *Decoder);
507 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
508                                            uint64_t Address,
509                                            const void *Decoder);
510 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
511                                   const void *Decoder);
512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
513                                          uint64_t Address, const void *Decoder);
514 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
515                                         uint64_t Address, const void *Decoder);
516 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val,
517                                                      uint64_t Address,
518                                                      const void *Decoder);
519 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val,
520                                                      uint64_t Address,
521                                                      const void *Decoder);
522 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val,
523                                                      uint64_t Address,
524                                                      const void *Decoder);
525 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
526                                                        unsigned Val,
527                                                        uint64_t Address,
528                                                        const void *Decoder);
529 template<bool Writeback>
530 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
531                                           uint64_t Address,
532                                           const void *Decoder);
533 template<int shift>
534 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
535                                         uint64_t Address, const void *Decoder);
536 template<int shift>
537 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
538                                         uint64_t Address, const void *Decoder);
539 template<int shift>
540 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
541                                         uint64_t Address, const void *Decoder);
542 template<unsigned MinLog, unsigned MaxLog>
543 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
544                                           uint64_t Address,
545                                           const void *Decoder);
546 template<unsigned start>
547 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
548                                                     uint64_t Address,
549                                                     const void *Decoder);
550 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
551                                          uint64_t Address,
552                                          const void *Decoder);
553 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
554                                          uint64_t Address,
555                                          const void *Decoder);
556 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
557                                       uint64_t Address, const void *Decoder);
558 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
559                                     uint64_t Address, const void *Decoder);
560 template<bool scalar, OperandDecoder predicate_decoder>
561 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
562                                   uint64_t Address, const void *Decoder);
563 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
564                                   uint64_t Address, const void *Decoder);
565 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
566                                    uint64_t Address, const void *Decoder);
567 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
568                                                   uint64_t Address,
569                                                   const void *Decoder);
570 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
571                                         uint64_t Address, const void *Decoder);
572 
573 #include "ARMGenDisassemblerTables.inc"
574 
575 static MCDisassembler *createARMDisassembler(const Target &T,
576                                              const MCSubtargetInfo &STI,
577                                              MCContext &Ctx) {
578   return new ARMDisassembler(STI, Ctx);
579 }
580 
581 // Post-decoding checks
582 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
583                                             uint64_t Address, raw_ostream &CS,
584                                             uint32_t Insn,
585                                             DecodeStatus Result) {
586   switch (MI.getOpcode()) {
587     case ARM::HVC: {
588       // HVC is undefined if condition = 0xf otherwise upredictable
589       // if condition != 0xe
590       uint32_t Cond = (Insn >> 28) & 0xF;
591       if (Cond == 0xF)
592         return MCDisassembler::Fail;
593       if (Cond != 0xE)
594         return MCDisassembler::SoftFail;
595       return Result;
596     }
597     case ARM::t2ADDri:
598     case ARM::t2ADDri12:
599     case ARM::t2ADDrr:
600     case ARM::t2ADDrs:
601     case ARM::t2SUBri:
602     case ARM::t2SUBri12:
603     case ARM::t2SUBrr:
604     case ARM::t2SUBrs:
605       if (MI.getOperand(0).getReg() == ARM::SP &&
606           MI.getOperand(1).getReg() != ARM::SP)
607         return MCDisassembler::SoftFail;
608       return Result;
609     default: return Result;
610   }
611 }
612 
613 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
614                                              ArrayRef<uint8_t> Bytes,
615                                              uint64_t Address,
616                                              raw_ostream &CS) const {
617   if (STI.getFeatureBits()[ARM::ModeThumb])
618     return getThumbInstruction(MI, Size, Bytes, Address, CS);
619   return getARMInstruction(MI, Size, Bytes, Address, CS);
620 }
621 
622 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
623                                                 ArrayRef<uint8_t> Bytes,
624                                                 uint64_t Address,
625                                                 raw_ostream &CS) const {
626   CommentStream = &CS;
627 
628   assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
629          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
630          "mode!");
631 
632   // We want to read exactly 4 bytes of data.
633   if (Bytes.size() < 4) {
634     Size = 0;
635     return MCDisassembler::Fail;
636   }
637 
638   // Encoded as a small-endian 32-bit word in the stream.
639   uint32_t Insn =
640       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
641 
642   // Calling the auto-generated decoder function.
643   DecodeStatus Result =
644       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
645   if (Result != MCDisassembler::Fail) {
646     Size = 4;
647     return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
648   }
649 
650   struct DecodeTable {
651     const uint8_t *P;
652     bool DecodePred;
653   };
654 
655   const DecodeTable Tables[] = {
656       {DecoderTableVFP32, false},      {DecoderTableVFPV832, false},
657       {DecoderTableNEONData32, true},  {DecoderTableNEONLoadStore32, true},
658       {DecoderTableNEONDup32, true},   {DecoderTablev8NEON32, false},
659       {DecoderTablev8Crypto32, false},
660   };
661 
662   for (auto Table : Tables) {
663     Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
664     if (Result != MCDisassembler::Fail) {
665       Size = 4;
666       // Add a fake predicate operand, because we share these instruction
667       // definitions with Thumb2 where these instructions are predicable.
668       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
669         return MCDisassembler::Fail;
670       return Result;
671     }
672   }
673 
674   Result =
675       decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
676   if (Result != MCDisassembler::Fail) {
677     Size = 4;
678     return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result);
679   }
680 
681   Size = 4;
682   return MCDisassembler::Fail;
683 }
684 
685 namespace llvm {
686 
687 extern const MCInstrDesc ARMInsts[];
688 
689 } // end namespace llvm
690 
691 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
692 /// immediate Value in the MCInst.  The immediate Value has had any PC
693 /// adjustment made by the caller.  If the instruction is a branch instruction
694 /// then isBranch is true, else false.  If the getOpInfo() function was set as
695 /// part of the setupForSymbolicDisassembly() call then that function is called
696 /// to get any symbolic information at the Address for this instruction.  If
697 /// that returns non-zero then the symbolic information it returns is used to
698 /// create an MCExpr and that is added as an operand to the MCInst.  If
699 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
700 /// Value is done and if a symbol is found an MCExpr is created with that, else
701 /// an MCExpr with Value is created.  This function returns true if it adds an
702 /// operand to the MCInst and false otherwise.
703 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
704                                      bool isBranch, uint64_t InstSize,
705                                      MCInst &MI, const void *Decoder) {
706   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
707   // FIXME: Does it make sense for value to be negative?
708   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
709                                        /* Offset */ 0, InstSize);
710 }
711 
712 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
713 /// referenced by a load instruction with the base register that is the Pc.
714 /// These can often be values in a literal pool near the Address of the
715 /// instruction.  The Address of the instruction and its immediate Value are
716 /// used as a possible literal pool entry.  The SymbolLookUp call back will
717 /// return the name of a symbol referenced by the literal pool's entry if
718 /// the referenced address is that of a symbol.  Or it will return a pointer to
719 /// a literal 'C' string if the referenced address of the literal pool's entry
720 /// is an address into a section with 'C' string literals.
721 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
722                                             const void *Decoder) {
723   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
724   Dis->tryAddingPcLoadReferenceComment(Value, Address);
725 }
726 
727 // Thumb1 instructions don't have explicit S bits.  Rather, they
728 // implicitly set CPSR.  Since it's not represented in the encoding, the
729 // auto-generated decoder won't inject the CPSR operand.  We need to fix
730 // that as a post-pass.
731 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
732   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
733   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
734   MCInst::iterator I = MI.begin();
735   for (unsigned i = 0; i < NumOps; ++i, ++I) {
736     if (I == MI.end()) break;
737     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
738       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
739       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
740       return;
741     }
742   }
743 
744   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
745 }
746 
747 static bool isVectorPredicable(unsigned Opcode) {
748   const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
749   unsigned short NumOps = ARMInsts[Opcode].NumOperands;
750   for (unsigned i = 0; i < NumOps; ++i) {
751     if (ARM::isVpred(OpInfo[i].OperandType))
752       return true;
753   }
754   return false;
755 }
756 
757 // Most Thumb instructions don't have explicit predicates in the
758 // encoding, but rather get their predicates from IT context.  We need
759 // to fix up the predicate operands using this context information as a
760 // post-pass.
761 MCDisassembler::DecodeStatus
762 ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
763   MCDisassembler::DecodeStatus S = Success;
764 
765   const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
766 
767   // A few instructions actually have predicates encoded in them.  Don't
768   // try to overwrite it if we're seeing one of those.
769   switch (MI.getOpcode()) {
770     case ARM::tBcc:
771     case ARM::t2Bcc:
772     case ARM::tCBZ:
773     case ARM::tCBNZ:
774     case ARM::tCPS:
775     case ARM::t2CPS3p:
776     case ARM::t2CPS2p:
777     case ARM::t2CPS1p:
778     case ARM::t2CSEL:
779     case ARM::t2CSINC:
780     case ARM::t2CSINV:
781     case ARM::t2CSNEG:
782     case ARM::tMOVSr:
783     case ARM::tSETEND:
784       // Some instructions (mostly conditional branches) are not
785       // allowed in IT blocks.
786       if (ITBlock.instrInITBlock())
787         S = SoftFail;
788       else
789         return Success;
790       break;
791     case ARM::t2HINT:
792       if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
793         S = SoftFail;
794       break;
795     case ARM::tB:
796     case ARM::t2B:
797     case ARM::t2TBB:
798     case ARM::t2TBH:
799       // Some instructions (mostly unconditional branches) can
800       // only appears at the end of, or outside of, an IT.
801       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
802         S = SoftFail;
803       break;
804     default:
805       break;
806   }
807 
808   // Warn on non-VPT predicable instruction in a VPT block and a VPT
809   // predicable instruction in an IT block
810   if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
811        (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
812     S = SoftFail;
813 
814   // If we're in an IT/VPT block, base the predicate on that.  Otherwise,
815   // assume a predicate of AL.
816   unsigned CC = ARMCC::AL;
817   unsigned VCC = ARMVCC::None;
818   if (ITBlock.instrInITBlock()) {
819     CC = ITBlock.getITCC();
820     ITBlock.advanceITState();
821   } else if (VPTBlock.instrInVPTBlock()) {
822     VCC = VPTBlock.getVPTPred();
823     VPTBlock.advanceVPTState();
824   }
825 
826   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
827   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
828 
829   MCInst::iterator CCI = MI.begin();
830   for (unsigned i = 0; i < NumOps; ++i, ++CCI) {
831     if (OpInfo[i].isPredicate() || CCI == MI.end()) break;
832   }
833 
834   if (ARMInsts[MI.getOpcode()].isPredicable()) {
835     CCI = MI.insert(CCI, MCOperand::createImm(CC));
836     ++CCI;
837     if (CC == ARMCC::AL)
838       MI.insert(CCI, MCOperand::createReg(0));
839     else
840       MI.insert(CCI, MCOperand::createReg(ARM::CPSR));
841   } else if (CC != ARMCC::AL) {
842     Check(S, SoftFail);
843   }
844 
845   MCInst::iterator VCCI = MI.begin();
846   unsigned VCCPos;
847   for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) {
848     if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break;
849   }
850 
851   if (isVectorPredicable(MI.getOpcode())) {
852     VCCI = MI.insert(VCCI, MCOperand::createImm(VCC));
853     ++VCCI;
854     if (VCC == ARMVCC::None)
855       MI.insert(VCCI, MCOperand::createReg(0));
856     else
857       MI.insert(VCCI, MCOperand::createReg(ARM::P0));
858     if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) {
859       int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
860         VCCPos + 2, MCOI::TIED_TO);
861       assert(TiedOp >= 0 &&
862              "Inactive register in vpred_r is not tied to an output!");
863       MI.insert(VCCI, MI.getOperand(TiedOp));
864     }
865   } else if (VCC != ARMVCC::None) {
866     Check(S, SoftFail);
867   }
868 
869   return S;
870 }
871 
872 // Thumb VFP instructions are a special case.  Because we share their
873 // encodings between ARM and Thumb modes, and they are predicable in ARM
874 // mode, the auto-generated decoder will give them an (incorrect)
875 // predicate operand.  We need to rewrite these operands based on the IT
876 // context as a post-pass.
877 void ARMDisassembler::UpdateThumbVFPPredicate(
878   DecodeStatus &S, MCInst &MI) const {
879   unsigned CC;
880   CC = ITBlock.getITCC();
881   if (CC == 0xF)
882     CC = ARMCC::AL;
883   if (ITBlock.instrInITBlock())
884     ITBlock.advanceITState();
885   else if (VPTBlock.instrInVPTBlock()) {
886     CC = VPTBlock.getVPTPred();
887     VPTBlock.advanceVPTState();
888   }
889 
890   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
891   MCInst::iterator I = MI.begin();
892   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
893   for (unsigned i = 0; i < NumOps; ++i, ++I) {
894     if (OpInfo[i].isPredicate() ) {
895       if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
896         Check(S, SoftFail);
897       I->setImm(CC);
898       ++I;
899       if (CC == ARMCC::AL)
900         I->setReg(0);
901       else
902         I->setReg(ARM::CPSR);
903       return;
904     }
905   }
906 }
907 
908 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
909                                                   ArrayRef<uint8_t> Bytes,
910                                                   uint64_t Address,
911                                                   raw_ostream &CS) const {
912   CommentStream = &CS;
913 
914   assert(STI.getFeatureBits()[ARM::ModeThumb] &&
915          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
916 
917   // We want to read exactly 2 bytes of data.
918   if (Bytes.size() < 2) {
919     Size = 0;
920     return MCDisassembler::Fail;
921   }
922 
923   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
924   DecodeStatus Result =
925       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
926   if (Result != MCDisassembler::Fail) {
927     Size = 2;
928     Check(Result, AddThumbPredicate(MI));
929     return Result;
930   }
931 
932   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
933                              STI);
934   if (Result) {
935     Size = 2;
936     bool InITBlock = ITBlock.instrInITBlock();
937     Check(Result, AddThumbPredicate(MI));
938     AddThumb1SBit(MI, InITBlock);
939     return Result;
940   }
941 
942   Result =
943       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
944   if (Result != MCDisassembler::Fail) {
945     Size = 2;
946 
947     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
948     // the Thumb predicate.
949     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
950       Result = MCDisassembler::SoftFail;
951 
952     Check(Result, AddThumbPredicate(MI));
953 
954     // If we find an IT instruction, we need to parse its condition
955     // code and mask operands so that we can apply them correctly
956     // to the subsequent instructions.
957     if (MI.getOpcode() == ARM::t2IT) {
958       unsigned Firstcond = MI.getOperand(0).getImm();
959       unsigned Mask = MI.getOperand(1).getImm();
960       ITBlock.setITState(Firstcond, Mask);
961 
962       // An IT instruction that would give a 'NV' predicate is unpredictable.
963       if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
964         CS << "unpredictable IT predicate sequence";
965     }
966 
967     return Result;
968   }
969 
970   // We want to read exactly 4 bytes of data.
971   if (Bytes.size() < 4) {
972     Size = 0;
973     return MCDisassembler::Fail;
974   }
975 
976   uint32_t Insn32 =
977       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
978 
979   Result =
980       decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
981   if (Result != MCDisassembler::Fail) {
982     Size = 4;
983 
984     // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
985     // the VPT predicate.
986     if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
987       Result = MCDisassembler::SoftFail;
988 
989     Check(Result, AddThumbPredicate(MI));
990 
991     if (isVPTOpcode(MI.getOpcode())) {
992       unsigned Mask = MI.getOperand(0).getImm();
993       VPTBlock.setVPTState(Mask);
994     }
995 
996     return Result;
997   }
998 
999   Result =
1000       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1001   if (Result != MCDisassembler::Fail) {
1002     Size = 4;
1003     bool InITBlock = ITBlock.instrInITBlock();
1004     Check(Result, AddThumbPredicate(MI));
1005     AddThumb1SBit(MI, InITBlock);
1006     return Result;
1007   }
1008 
1009   Result =
1010       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1011   if (Result != MCDisassembler::Fail) {
1012     Size = 4;
1013     Check(Result, AddThumbPredicate(MI));
1014     return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result);
1015   }
1016 
1017   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1018     Result =
1019         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1020     if (Result != MCDisassembler::Fail) {
1021       Size = 4;
1022       UpdateThumbVFPPredicate(Result, MI);
1023       return Result;
1024     }
1025   }
1026 
1027   Result =
1028       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1029   if (Result != MCDisassembler::Fail) {
1030     Size = 4;
1031     return Result;
1032   }
1033 
1034   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
1035     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
1036                                STI);
1037     if (Result != MCDisassembler::Fail) {
1038       Size = 4;
1039       Check(Result, AddThumbPredicate(MI));
1040       return Result;
1041     }
1042   }
1043 
1044   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
1045     uint32_t NEONLdStInsn = Insn32;
1046     NEONLdStInsn &= 0xF0FFFFFF;
1047     NEONLdStInsn |= 0x04000000;
1048     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
1049                                Address, this, STI);
1050     if (Result != MCDisassembler::Fail) {
1051       Size = 4;
1052       Check(Result, AddThumbPredicate(MI));
1053       return Result;
1054     }
1055   }
1056 
1057   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
1058     uint32_t NEONDataInsn = Insn32;
1059     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
1060     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1061     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
1062     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
1063                                Address, this, STI);
1064     if (Result != MCDisassembler::Fail) {
1065       Size = 4;
1066       Check(Result, AddThumbPredicate(MI));
1067       return Result;
1068     }
1069 
1070     uint32_t NEONCryptoInsn = Insn32;
1071     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
1072     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
1073     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
1074     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
1075                                Address, this, STI);
1076     if (Result != MCDisassembler::Fail) {
1077       Size = 4;
1078       return Result;
1079     }
1080 
1081     uint32_t NEONv8Insn = Insn32;
1082     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
1083     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
1084                                this, STI);
1085     if (Result != MCDisassembler::Fail) {
1086       Size = 4;
1087       return Result;
1088     }
1089   }
1090 
1091   uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4);
1092   const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI)
1093                                     ? DecoderTableThumb2CDE32
1094                                     : DecoderTableThumb2CoProc32;
1095   Result =
1096       decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI);
1097   if (Result != MCDisassembler::Fail) {
1098     Size = 4;
1099     Check(Result, AddThumbPredicate(MI));
1100     return Result;
1101   }
1102 
1103   Size = 0;
1104   return MCDisassembler::Fail;
1105 }
1106 
1107 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() {
1108   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
1109                                          createARMDisassembler);
1110   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
1111                                          createARMDisassembler);
1112   TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
1113                                          createARMDisassembler);
1114   TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
1115                                          createARMDisassembler);
1116 }
1117 
1118 static const uint16_t GPRDecoderTable[] = {
1119   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1120   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1121   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1122   ARM::R12, ARM::SP, ARM::LR, ARM::PC
1123 };
1124 
1125 static const uint16_t CLRMGPRDecoderTable[] = {
1126   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1127   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1128   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1129   ARM::R12, 0, ARM::LR, ARM::APSR
1130 };
1131 
1132 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1133                                    uint64_t Address, const void *Decoder) {
1134   if (RegNo > 15)
1135     return MCDisassembler::Fail;
1136 
1137   unsigned Register = GPRDecoderTable[RegNo];
1138   Inst.addOperand(MCOperand::createReg(Register));
1139   return MCDisassembler::Success;
1140 }
1141 
1142 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1143                                                uint64_t Address,
1144                                                const void *Decoder) {
1145   if (RegNo > 15)
1146     return MCDisassembler::Fail;
1147 
1148   unsigned Register = CLRMGPRDecoderTable[RegNo];
1149   if (Register == 0)
1150     return MCDisassembler::Fail;
1151 
1152   Inst.addOperand(MCOperand::createReg(Register));
1153   return MCDisassembler::Success;
1154 }
1155 
1156 static DecodeStatus
1157 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1158                            uint64_t Address, const void *Decoder) {
1159   DecodeStatus S = MCDisassembler::Success;
1160 
1161   if (RegNo == 15)
1162     S = MCDisassembler::SoftFail;
1163 
1164   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1165 
1166   return S;
1167 }
1168 
1169 static DecodeStatus
1170 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
1171                                uint64_t Address, const void *Decoder) {
1172   DecodeStatus S = MCDisassembler::Success;
1173 
1174   if (RegNo == 15)
1175   {
1176     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1177     return MCDisassembler::Success;
1178   }
1179 
1180   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1181   return S;
1182 }
1183 
1184 static DecodeStatus
1185 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
1186                              uint64_t Address, const void *Decoder) {
1187   DecodeStatus S = MCDisassembler::Success;
1188 
1189   if (RegNo == 15)
1190   {
1191     Inst.addOperand(MCOperand::createReg(ARM::ZR));
1192     return MCDisassembler::Success;
1193   }
1194 
1195   if (RegNo == 13)
1196     Check(S, MCDisassembler::SoftFail);
1197 
1198   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1199   return S;
1200 }
1201 
1202 static DecodeStatus
1203 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1204                                  uint64_t Address, const void *Decoder) {
1205   DecodeStatus S = MCDisassembler::Success;
1206   if (RegNo == 13)
1207     return MCDisassembler::Fail;
1208   Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1209   return S;
1210 }
1211 
1212 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1213                                    uint64_t Address, const void *Decoder) {
1214   if (RegNo > 7)
1215     return MCDisassembler::Fail;
1216   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1217 }
1218 
1219 static const uint16_t GPRPairDecoderTable[] = {
1220   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
1221   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
1222 };
1223 
1224 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1225                                    uint64_t Address, const void *Decoder) {
1226   DecodeStatus S = MCDisassembler::Success;
1227 
1228   // According to the Arm ARM RegNo = 14 is undefined, but we return fail
1229   // rather than SoftFail as there is no GPRPair table entry for index 7.
1230   if (RegNo > 13)
1231     return MCDisassembler::Fail;
1232 
1233   if (RegNo & 1)
1234      S = MCDisassembler::SoftFail;
1235 
1236   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1237   Inst.addOperand(MCOperand::createReg(RegisterPair));
1238   return S;
1239 }
1240 
1241 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo,
1242                                    uint64_t Address, const void *Decoder) {
1243   if (RegNo > 13)
1244     return MCDisassembler::Fail;
1245 
1246   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
1247   Inst.addOperand(MCOperand::createReg(RegisterPair));
1248 
1249   if ((RegNo & 1) || RegNo > 10)
1250      return MCDisassembler::SoftFail;
1251   return MCDisassembler::Success;
1252 }
1253 
1254 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1255                                              uint64_t Address,
1256                                              const void *Decoder) {
1257   if (RegNo != 13)
1258     return MCDisassembler::Fail;
1259 
1260   unsigned Register = GPRDecoderTable[RegNo];
1261   Inst.addOperand(MCOperand::createReg(Register));
1262   return MCDisassembler::Success;
1263 }
1264 
1265 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1266                                    uint64_t Address, const void *Decoder) {
1267   unsigned Register = 0;
1268   switch (RegNo) {
1269     case 0:
1270       Register = ARM::R0;
1271       break;
1272     case 1:
1273       Register = ARM::R1;
1274       break;
1275     case 2:
1276       Register = ARM::R2;
1277       break;
1278     case 3:
1279       Register = ARM::R3;
1280       break;
1281     case 9:
1282       Register = ARM::R9;
1283       break;
1284     case 12:
1285       Register = ARM::R12;
1286       break;
1287     default:
1288       return MCDisassembler::Fail;
1289     }
1290 
1291   Inst.addOperand(MCOperand::createReg(Register));
1292   return MCDisassembler::Success;
1293 }
1294 
1295 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1296                                    uint64_t Address, const void *Decoder) {
1297   DecodeStatus S = MCDisassembler::Success;
1298 
1299   const FeatureBitset &featureBits =
1300     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1301 
1302   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
1303     S = MCDisassembler::SoftFail;
1304 
1305   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1306   return S;
1307 }
1308 
1309 static const uint16_t SPRDecoderTable[] = {
1310      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
1311      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
1312      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
1313     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1314     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1315     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1316     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1317     ARM::S28, ARM::S29, ARM::S30, ARM::S31
1318 };
1319 
1320 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1321                                    uint64_t Address, const void *Decoder) {
1322   if (RegNo > 31)
1323     return MCDisassembler::Fail;
1324 
1325   unsigned Register = SPRDecoderTable[RegNo];
1326   Inst.addOperand(MCOperand::createReg(Register));
1327   return MCDisassembler::Success;
1328 }
1329 
1330 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1331                                    uint64_t Address, const void *Decoder) {
1332   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1333 }
1334 
1335 static const uint16_t DPRDecoderTable[] = {
1336      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
1337      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
1338      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
1339     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1340     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1341     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1342     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1343     ARM::D28, ARM::D29, ARM::D30, ARM::D31
1344 };
1345 
1346 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1347                                    uint64_t Address, const void *Decoder) {
1348   const FeatureBitset &featureBits =
1349     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1350 
1351   bool hasD32 = featureBits[ARM::FeatureD32];
1352 
1353   if (RegNo > 31 || (!hasD32 && RegNo > 15))
1354     return MCDisassembler::Fail;
1355 
1356   unsigned Register = DPRDecoderTable[RegNo];
1357   Inst.addOperand(MCOperand::createReg(Register));
1358   return MCDisassembler::Success;
1359 }
1360 
1361 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1362                                    uint64_t Address, const void *Decoder) {
1363   if (RegNo > 7)
1364     return MCDisassembler::Fail;
1365   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1366 }
1367 
1368 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1369                                    uint64_t Address, const void *Decoder) {
1370   if (RegNo > 15)
1371     return MCDisassembler::Fail;
1372   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1373 }
1374 
1375 static DecodeStatus
1376 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1377                             uint64_t Address, const void *Decoder) {
1378   if (RegNo > 15)
1379     return MCDisassembler::Fail;
1380   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1381 }
1382 
1383 static const uint16_t QPRDecoderTable[] = {
1384      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
1385      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
1386      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
1387     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1388 };
1389 
1390 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1391                                    uint64_t Address, const void *Decoder) {
1392   if (RegNo > 31 || (RegNo & 1) != 0)
1393     return MCDisassembler::Fail;
1394   RegNo >>= 1;
1395 
1396   unsigned Register = QPRDecoderTable[RegNo];
1397   Inst.addOperand(MCOperand::createReg(Register));
1398   return MCDisassembler::Success;
1399 }
1400 
1401 static const uint16_t DPairDecoderTable[] = {
1402   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
1403   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
1404   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
1405   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1406   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1407   ARM::Q15
1408 };
1409 
1410 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1411                                    uint64_t Address, const void *Decoder) {
1412   if (RegNo > 30)
1413     return MCDisassembler::Fail;
1414 
1415   unsigned Register = DPairDecoderTable[RegNo];
1416   Inst.addOperand(MCOperand::createReg(Register));
1417   return MCDisassembler::Success;
1418 }
1419 
1420 static const uint16_t DPairSpacedDecoderTable[] = {
1421   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
1422   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
1423   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
1424   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1425   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1426   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1427   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1428   ARM::D28_D30, ARM::D29_D31
1429 };
1430 
1431 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1432                                                    unsigned RegNo,
1433                                                    uint64_t Address,
1434                                                    const void *Decoder) {
1435   if (RegNo > 29)
1436     return MCDisassembler::Fail;
1437 
1438   unsigned Register = DPairSpacedDecoderTable[RegNo];
1439   Inst.addOperand(MCOperand::createReg(Register));
1440   return MCDisassembler::Success;
1441 }
1442 
1443 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1444                                uint64_t Address, const void *Decoder) {
1445   DecodeStatus S = MCDisassembler::Success;
1446   if (Val == 0xF) return MCDisassembler::Fail;
1447   // AL predicate is not allowed on Thumb1 branches.
1448   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1449     return MCDisassembler::Fail;
1450   if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1451     Check(S, MCDisassembler::SoftFail);
1452   Inst.addOperand(MCOperand::createImm(Val));
1453   if (Val == ARMCC::AL) {
1454     Inst.addOperand(MCOperand::createReg(0));
1455   } else
1456     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1457   return S;
1458 }
1459 
1460 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1461                                uint64_t Address, const void *Decoder) {
1462   if (Val)
1463     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1464   else
1465     Inst.addOperand(MCOperand::createReg(0));
1466   return MCDisassembler::Success;
1467 }
1468 
1469 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1470                                uint64_t Address, const void *Decoder) {
1471   DecodeStatus S = MCDisassembler::Success;
1472 
1473   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1474   unsigned type = fieldFromInstruction(Val, 5, 2);
1475   unsigned imm = fieldFromInstruction(Val, 7, 5);
1476 
1477   // Register-immediate
1478   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1479     return MCDisassembler::Fail;
1480 
1481   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1482   switch (type) {
1483     case 0:
1484       Shift = ARM_AM::lsl;
1485       break;
1486     case 1:
1487       Shift = ARM_AM::lsr;
1488       break;
1489     case 2:
1490       Shift = ARM_AM::asr;
1491       break;
1492     case 3:
1493       Shift = ARM_AM::ror;
1494       break;
1495   }
1496 
1497   if (Shift == ARM_AM::ror && imm == 0)
1498     Shift = ARM_AM::rrx;
1499 
1500   unsigned Op = Shift | (imm << 3);
1501   Inst.addOperand(MCOperand::createImm(Op));
1502 
1503   return S;
1504 }
1505 
1506 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1507                                uint64_t Address, const void *Decoder) {
1508   DecodeStatus S = MCDisassembler::Success;
1509 
1510   unsigned Rm = fieldFromInstruction(Val, 0, 4);
1511   unsigned type = fieldFromInstruction(Val, 5, 2);
1512   unsigned Rs = fieldFromInstruction(Val, 8, 4);
1513 
1514   // Register-register
1515   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1516     return MCDisassembler::Fail;
1517   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1518     return MCDisassembler::Fail;
1519 
1520   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1521   switch (type) {
1522     case 0:
1523       Shift = ARM_AM::lsl;
1524       break;
1525     case 1:
1526       Shift = ARM_AM::lsr;
1527       break;
1528     case 2:
1529       Shift = ARM_AM::asr;
1530       break;
1531     case 3:
1532       Shift = ARM_AM::ror;
1533       break;
1534   }
1535 
1536   Inst.addOperand(MCOperand::createImm(Shift));
1537 
1538   return S;
1539 }
1540 
1541 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1542                                  uint64_t Address, const void *Decoder) {
1543   DecodeStatus S = MCDisassembler::Success;
1544 
1545   bool NeedDisjointWriteback = false;
1546   unsigned WritebackReg = 0;
1547   bool CLRM = false;
1548   switch (Inst.getOpcode()) {
1549   default:
1550     break;
1551   case ARM::LDMIA_UPD:
1552   case ARM::LDMDB_UPD:
1553   case ARM::LDMIB_UPD:
1554   case ARM::LDMDA_UPD:
1555   case ARM::t2LDMIA_UPD:
1556   case ARM::t2LDMDB_UPD:
1557   case ARM::t2STMIA_UPD:
1558   case ARM::t2STMDB_UPD:
1559     NeedDisjointWriteback = true;
1560     WritebackReg = Inst.getOperand(0).getReg();
1561     break;
1562   case ARM::t2CLRM:
1563     CLRM = true;
1564     break;
1565   }
1566 
1567   // Empty register lists are not allowed.
1568   if (Val == 0) return MCDisassembler::Fail;
1569   for (unsigned i = 0; i < 16; ++i) {
1570     if (Val & (1 << i)) {
1571       if (CLRM) {
1572         if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1573           return MCDisassembler::Fail;
1574         }
1575       } else {
1576         if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1577           return MCDisassembler::Fail;
1578         // Writeback not allowed if Rn is in the target list.
1579         if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1580           Check(S, MCDisassembler::SoftFail);
1581       }
1582     }
1583   }
1584 
1585   return S;
1586 }
1587 
1588 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1589                                  uint64_t Address, const void *Decoder) {
1590   DecodeStatus S = MCDisassembler::Success;
1591 
1592   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1593   unsigned regs = fieldFromInstruction(Val, 0, 8);
1594 
1595   // In case of unpredictable encoding, tweak the operands.
1596   if (regs == 0 || (Vd + regs) > 32) {
1597     regs = Vd + regs > 32 ? 32 - Vd : regs;
1598     regs = std::max( 1u, regs);
1599     S = MCDisassembler::SoftFail;
1600   }
1601 
1602   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1603     return MCDisassembler::Fail;
1604   for (unsigned i = 0; i < (regs - 1); ++i) {
1605     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1606       return MCDisassembler::Fail;
1607   }
1608 
1609   return S;
1610 }
1611 
1612 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1613                                  uint64_t Address, const void *Decoder) {
1614   DecodeStatus S = MCDisassembler::Success;
1615 
1616   unsigned Vd = fieldFromInstruction(Val, 8, 5);
1617   unsigned regs = fieldFromInstruction(Val, 1, 7);
1618 
1619   // In case of unpredictable encoding, tweak the operands.
1620   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1621     regs = Vd + regs > 32 ? 32 - Vd : regs;
1622     regs = std::max( 1u, regs);
1623     regs = std::min(16u, regs);
1624     S = MCDisassembler::SoftFail;
1625   }
1626 
1627   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1628       return MCDisassembler::Fail;
1629   for (unsigned i = 0; i < (regs - 1); ++i) {
1630     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1631       return MCDisassembler::Fail;
1632   }
1633 
1634   return S;
1635 }
1636 
1637 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1638                                       uint64_t Address, const void *Decoder) {
1639   // This operand encodes a mask of contiguous zeros between a specified MSB
1640   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1641   // the mask of all bits LSB-and-lower, and then xor them to create
1642   // the mask of that's all ones on [msb, lsb].  Finally we not it to
1643   // create the final mask.
1644   unsigned msb = fieldFromInstruction(Val, 5, 5);
1645   unsigned lsb = fieldFromInstruction(Val, 0, 5);
1646 
1647   DecodeStatus S = MCDisassembler::Success;
1648   if (lsb > msb) {
1649     Check(S, MCDisassembler::SoftFail);
1650     // The check above will cause the warning for the "potentially undefined
1651     // instruction encoding" but we can't build a bad MCOperand value here
1652     // with a lsb > msb or else printing the MCInst will cause a crash.
1653     lsb = msb;
1654   }
1655 
1656   uint32_t msb_mask = 0xFFFFFFFF;
1657   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1658   uint32_t lsb_mask = (1U << lsb) - 1;
1659 
1660   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1661   return S;
1662 }
1663 
1664 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1665                                   uint64_t Address, const void *Decoder) {
1666   DecodeStatus S = MCDisassembler::Success;
1667 
1668   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1669   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1670   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1671   unsigned imm = fieldFromInstruction(Insn, 0, 8);
1672   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1673   unsigned U = fieldFromInstruction(Insn, 23, 1);
1674   const FeatureBitset &featureBits =
1675     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1676 
1677   switch (Inst.getOpcode()) {
1678     case ARM::LDC_OFFSET:
1679     case ARM::LDC_PRE:
1680     case ARM::LDC_POST:
1681     case ARM::LDC_OPTION:
1682     case ARM::LDCL_OFFSET:
1683     case ARM::LDCL_PRE:
1684     case ARM::LDCL_POST:
1685     case ARM::LDCL_OPTION:
1686     case ARM::STC_OFFSET:
1687     case ARM::STC_PRE:
1688     case ARM::STC_POST:
1689     case ARM::STC_OPTION:
1690     case ARM::STCL_OFFSET:
1691     case ARM::STCL_PRE:
1692     case ARM::STCL_POST:
1693     case ARM::STCL_OPTION:
1694     case ARM::t2LDC_OFFSET:
1695     case ARM::t2LDC_PRE:
1696     case ARM::t2LDC_POST:
1697     case ARM::t2LDC_OPTION:
1698     case ARM::t2LDCL_OFFSET:
1699     case ARM::t2LDCL_PRE:
1700     case ARM::t2LDCL_POST:
1701     case ARM::t2LDCL_OPTION:
1702     case ARM::t2STC_OFFSET:
1703     case ARM::t2STC_PRE:
1704     case ARM::t2STC_POST:
1705     case ARM::t2STC_OPTION:
1706     case ARM::t2STCL_OFFSET:
1707     case ARM::t2STCL_PRE:
1708     case ARM::t2STCL_POST:
1709     case ARM::t2STCL_OPTION:
1710     case ARM::t2LDC2_OFFSET:
1711     case ARM::t2LDC2L_OFFSET:
1712     case ARM::t2LDC2_PRE:
1713     case ARM::t2LDC2L_PRE:
1714     case ARM::t2STC2_OFFSET:
1715     case ARM::t2STC2L_OFFSET:
1716     case ARM::t2STC2_PRE:
1717     case ARM::t2STC2L_PRE:
1718     case ARM::LDC2_OFFSET:
1719     case ARM::LDC2L_OFFSET:
1720     case ARM::LDC2_PRE:
1721     case ARM::LDC2L_PRE:
1722     case ARM::STC2_OFFSET:
1723     case ARM::STC2L_OFFSET:
1724     case ARM::STC2_PRE:
1725     case ARM::STC2L_PRE:
1726     case ARM::t2LDC2_OPTION:
1727     case ARM::t2STC2_OPTION:
1728     case ARM::t2LDC2_POST:
1729     case ARM::t2LDC2L_POST:
1730     case ARM::t2STC2_POST:
1731     case ARM::t2STC2L_POST:
1732     case ARM::LDC2_POST:
1733     case ARM::LDC2L_POST:
1734     case ARM::STC2_POST:
1735     case ARM::STC2L_POST:
1736       if (coproc == 0xA || coproc == 0xB ||
1737           (featureBits[ARM::HasV8_1MMainlineOps] &&
1738            (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB ||
1739             coproc == 0xE || coproc == 0xF)))
1740         return MCDisassembler::Fail;
1741       break;
1742     default:
1743       break;
1744   }
1745 
1746   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1747     return MCDisassembler::Fail;
1748 
1749   Inst.addOperand(MCOperand::createImm(coproc));
1750   Inst.addOperand(MCOperand::createImm(CRd));
1751   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1752     return MCDisassembler::Fail;
1753 
1754   switch (Inst.getOpcode()) {
1755     case ARM::t2LDC2_OFFSET:
1756     case ARM::t2LDC2L_OFFSET:
1757     case ARM::t2LDC2_PRE:
1758     case ARM::t2LDC2L_PRE:
1759     case ARM::t2STC2_OFFSET:
1760     case ARM::t2STC2L_OFFSET:
1761     case ARM::t2STC2_PRE:
1762     case ARM::t2STC2L_PRE:
1763     case ARM::LDC2_OFFSET:
1764     case ARM::LDC2L_OFFSET:
1765     case ARM::LDC2_PRE:
1766     case ARM::LDC2L_PRE:
1767     case ARM::STC2_OFFSET:
1768     case ARM::STC2L_OFFSET:
1769     case ARM::STC2_PRE:
1770     case ARM::STC2L_PRE:
1771     case ARM::t2LDC_OFFSET:
1772     case ARM::t2LDCL_OFFSET:
1773     case ARM::t2LDC_PRE:
1774     case ARM::t2LDCL_PRE:
1775     case ARM::t2STC_OFFSET:
1776     case ARM::t2STCL_OFFSET:
1777     case ARM::t2STC_PRE:
1778     case ARM::t2STCL_PRE:
1779     case ARM::LDC_OFFSET:
1780     case ARM::LDCL_OFFSET:
1781     case ARM::LDC_PRE:
1782     case ARM::LDCL_PRE:
1783     case ARM::STC_OFFSET:
1784     case ARM::STCL_OFFSET:
1785     case ARM::STC_PRE:
1786     case ARM::STCL_PRE:
1787       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1788       Inst.addOperand(MCOperand::createImm(imm));
1789       break;
1790     case ARM::t2LDC2_POST:
1791     case ARM::t2LDC2L_POST:
1792     case ARM::t2STC2_POST:
1793     case ARM::t2STC2L_POST:
1794     case ARM::LDC2_POST:
1795     case ARM::LDC2L_POST:
1796     case ARM::STC2_POST:
1797     case ARM::STC2L_POST:
1798     case ARM::t2LDC_POST:
1799     case ARM::t2LDCL_POST:
1800     case ARM::t2STC_POST:
1801     case ARM::t2STCL_POST:
1802     case ARM::LDC_POST:
1803     case ARM::LDCL_POST:
1804     case ARM::STC_POST:
1805     case ARM::STCL_POST:
1806       imm |= U << 8;
1807       LLVM_FALLTHROUGH;
1808     default:
1809       // The 'option' variant doesn't encode 'U' in the immediate since
1810       // the immediate is unsigned [0,255].
1811       Inst.addOperand(MCOperand::createImm(imm));
1812       break;
1813   }
1814 
1815   switch (Inst.getOpcode()) {
1816     case ARM::LDC_OFFSET:
1817     case ARM::LDC_PRE:
1818     case ARM::LDC_POST:
1819     case ARM::LDC_OPTION:
1820     case ARM::LDCL_OFFSET:
1821     case ARM::LDCL_PRE:
1822     case ARM::LDCL_POST:
1823     case ARM::LDCL_OPTION:
1824     case ARM::STC_OFFSET:
1825     case ARM::STC_PRE:
1826     case ARM::STC_POST:
1827     case ARM::STC_OPTION:
1828     case ARM::STCL_OFFSET:
1829     case ARM::STCL_PRE:
1830     case ARM::STCL_POST:
1831     case ARM::STCL_OPTION:
1832       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1833         return MCDisassembler::Fail;
1834       break;
1835     default:
1836       break;
1837   }
1838 
1839   return S;
1840 }
1841 
1842 static DecodeStatus
1843 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1844                               uint64_t Address, const void *Decoder) {
1845   DecodeStatus S = MCDisassembler::Success;
1846 
1847   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1848   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1849   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1850   unsigned imm = fieldFromInstruction(Insn, 0, 12);
1851   unsigned pred = fieldFromInstruction(Insn, 28, 4);
1852   unsigned reg = fieldFromInstruction(Insn, 25, 1);
1853   unsigned P = fieldFromInstruction(Insn, 24, 1);
1854   unsigned W = fieldFromInstruction(Insn, 21, 1);
1855 
1856   // On stores, the writeback operand precedes Rt.
1857   switch (Inst.getOpcode()) {
1858     case ARM::STR_POST_IMM:
1859     case ARM::STR_POST_REG:
1860     case ARM::STRB_POST_IMM:
1861     case ARM::STRB_POST_REG:
1862     case ARM::STRT_POST_REG:
1863     case ARM::STRT_POST_IMM:
1864     case ARM::STRBT_POST_REG:
1865     case ARM::STRBT_POST_IMM:
1866       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1867         return MCDisassembler::Fail;
1868       break;
1869     default:
1870       break;
1871   }
1872 
1873   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1874     return MCDisassembler::Fail;
1875 
1876   // On loads, the writeback operand comes after Rt.
1877   switch (Inst.getOpcode()) {
1878     case ARM::LDR_POST_IMM:
1879     case ARM::LDR_POST_REG:
1880     case ARM::LDRB_POST_IMM:
1881     case ARM::LDRB_POST_REG:
1882     case ARM::LDRBT_POST_REG:
1883     case ARM::LDRBT_POST_IMM:
1884     case ARM::LDRT_POST_REG:
1885     case ARM::LDRT_POST_IMM:
1886       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887         return MCDisassembler::Fail;
1888       break;
1889     default:
1890       break;
1891   }
1892 
1893   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1894     return MCDisassembler::Fail;
1895 
1896   ARM_AM::AddrOpc Op = ARM_AM::add;
1897   if (!fieldFromInstruction(Insn, 23, 1))
1898     Op = ARM_AM::sub;
1899 
1900   bool writeback = (P == 0) || (W == 1);
1901   unsigned idx_mode = 0;
1902   if (P && writeback)
1903     idx_mode = ARMII::IndexModePre;
1904   else if (!P && writeback)
1905     idx_mode = ARMII::IndexModePost;
1906 
1907   if (writeback && (Rn == 15 || Rn == Rt))
1908     S = MCDisassembler::SoftFail; // UNPREDICTABLE
1909 
1910   if (reg) {
1911     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1912       return MCDisassembler::Fail;
1913     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1914     switch( fieldFromInstruction(Insn, 5, 2)) {
1915       case 0:
1916         Opc = ARM_AM::lsl;
1917         break;
1918       case 1:
1919         Opc = ARM_AM::lsr;
1920         break;
1921       case 2:
1922         Opc = ARM_AM::asr;
1923         break;
1924       case 3:
1925         Opc = ARM_AM::ror;
1926         break;
1927       default:
1928         return MCDisassembler::Fail;
1929     }
1930     unsigned amt = fieldFromInstruction(Insn, 7, 5);
1931     if (Opc == ARM_AM::ror && amt == 0)
1932       Opc = ARM_AM::rrx;
1933     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1934 
1935     Inst.addOperand(MCOperand::createImm(imm));
1936   } else {
1937     Inst.addOperand(MCOperand::createReg(0));
1938     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1939     Inst.addOperand(MCOperand::createImm(tmp));
1940   }
1941 
1942   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1943     return MCDisassembler::Fail;
1944 
1945   return S;
1946 }
1947 
1948 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1949                                   uint64_t Address, const void *Decoder) {
1950   DecodeStatus S = MCDisassembler::Success;
1951 
1952   unsigned Rn = fieldFromInstruction(Val, 13, 4);
1953   unsigned Rm = fieldFromInstruction(Val,  0, 4);
1954   unsigned type = fieldFromInstruction(Val, 5, 2);
1955   unsigned imm = fieldFromInstruction(Val, 7, 5);
1956   unsigned U = fieldFromInstruction(Val, 12, 1);
1957 
1958   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1959   switch (type) {
1960     case 0:
1961       ShOp = ARM_AM::lsl;
1962       break;
1963     case 1:
1964       ShOp = ARM_AM::lsr;
1965       break;
1966     case 2:
1967       ShOp = ARM_AM::asr;
1968       break;
1969     case 3:
1970       ShOp = ARM_AM::ror;
1971       break;
1972   }
1973 
1974   if (ShOp == ARM_AM::ror && imm == 0)
1975     ShOp = ARM_AM::rrx;
1976 
1977   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1978     return MCDisassembler::Fail;
1979   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1980     return MCDisassembler::Fail;
1981   unsigned shift;
1982   if (U)
1983     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1984   else
1985     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1986   Inst.addOperand(MCOperand::createImm(shift));
1987 
1988   return S;
1989 }
1990 
1991 static DecodeStatus
1992 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1993                            uint64_t Address, const void *Decoder) {
1994   DecodeStatus S = MCDisassembler::Success;
1995 
1996   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1997   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1998   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1999   unsigned type = fieldFromInstruction(Insn, 22, 1);
2000   unsigned imm = fieldFromInstruction(Insn, 8, 4);
2001   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
2002   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2003   unsigned W = fieldFromInstruction(Insn, 21, 1);
2004   unsigned P = fieldFromInstruction(Insn, 24, 1);
2005   unsigned Rt2 = Rt + 1;
2006 
2007   bool writeback = (W == 1) | (P == 0);
2008 
2009   // For {LD,ST}RD, Rt must be even, else undefined.
2010   switch (Inst.getOpcode()) {
2011     case ARM::STRD:
2012     case ARM::STRD_PRE:
2013     case ARM::STRD_POST:
2014     case ARM::LDRD:
2015     case ARM::LDRD_PRE:
2016     case ARM::LDRD_POST:
2017       if (Rt & 0x1) S = MCDisassembler::SoftFail;
2018       break;
2019     default:
2020       break;
2021   }
2022   switch (Inst.getOpcode()) {
2023     case ARM::STRD:
2024     case ARM::STRD_PRE:
2025     case ARM::STRD_POST:
2026       if (P == 0 && W == 1)
2027         S = MCDisassembler::SoftFail;
2028 
2029       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2030         S = MCDisassembler::SoftFail;
2031       if (type && Rm == 15)
2032         S = MCDisassembler::SoftFail;
2033       if (Rt2 == 15)
2034         S = MCDisassembler::SoftFail;
2035       if (!type && fieldFromInstruction(Insn, 8, 4))
2036         S = MCDisassembler::SoftFail;
2037       break;
2038     case ARM::STRH:
2039     case ARM::STRH_PRE:
2040     case ARM::STRH_POST:
2041       if (Rt == 15)
2042         S = MCDisassembler::SoftFail;
2043       if (writeback && (Rn == 15 || Rn == Rt))
2044         S = MCDisassembler::SoftFail;
2045       if (!type && Rm == 15)
2046         S = MCDisassembler::SoftFail;
2047       break;
2048     case ARM::LDRD:
2049     case ARM::LDRD_PRE:
2050     case ARM::LDRD_POST:
2051       if (type && Rn == 15) {
2052         if (Rt2 == 15)
2053           S = MCDisassembler::SoftFail;
2054         break;
2055       }
2056       if (P == 0 && W == 1)
2057         S = MCDisassembler::SoftFail;
2058       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2059         S = MCDisassembler::SoftFail;
2060       if (!type && writeback && Rn == 15)
2061         S = MCDisassembler::SoftFail;
2062       if (writeback && (Rn == Rt || Rn == Rt2))
2063         S = MCDisassembler::SoftFail;
2064       break;
2065     case ARM::LDRH:
2066     case ARM::LDRH_PRE:
2067     case ARM::LDRH_POST:
2068       if (type && Rn == 15) {
2069         if (Rt == 15)
2070           S = MCDisassembler::SoftFail;
2071         break;
2072       }
2073       if (Rt == 15)
2074         S = MCDisassembler::SoftFail;
2075       if (!type && Rm == 15)
2076         S = MCDisassembler::SoftFail;
2077       if (!type && writeback && (Rn == 15 || Rn == Rt))
2078         S = MCDisassembler::SoftFail;
2079       break;
2080     case ARM::LDRSH:
2081     case ARM::LDRSH_PRE:
2082     case ARM::LDRSH_POST:
2083     case ARM::LDRSB:
2084     case ARM::LDRSB_PRE:
2085     case ARM::LDRSB_POST:
2086       if (type && Rn == 15) {
2087         if (Rt == 15)
2088           S = MCDisassembler::SoftFail;
2089         break;
2090       }
2091       if (type && (Rt == 15 || (writeback && Rn == Rt)))
2092         S = MCDisassembler::SoftFail;
2093       if (!type && (Rt == 15 || Rm == 15))
2094         S = MCDisassembler::SoftFail;
2095       if (!type && writeback && (Rn == 15 || Rn == Rt))
2096         S = MCDisassembler::SoftFail;
2097       break;
2098     default:
2099       break;
2100   }
2101 
2102   if (writeback) { // Writeback
2103     if (P)
2104       U |= ARMII::IndexModePre << 9;
2105     else
2106       U |= ARMII::IndexModePost << 9;
2107 
2108     // On stores, the writeback operand precedes Rt.
2109     switch (Inst.getOpcode()) {
2110     case ARM::STRD:
2111     case ARM::STRD_PRE:
2112     case ARM::STRD_POST:
2113     case ARM::STRH:
2114     case ARM::STRH_PRE:
2115     case ARM::STRH_POST:
2116       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2117         return MCDisassembler::Fail;
2118       break;
2119     default:
2120       break;
2121     }
2122   }
2123 
2124   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2125     return MCDisassembler::Fail;
2126   switch (Inst.getOpcode()) {
2127     case ARM::STRD:
2128     case ARM::STRD_PRE:
2129     case ARM::STRD_POST:
2130     case ARM::LDRD:
2131     case ARM::LDRD_PRE:
2132     case ARM::LDRD_POST:
2133       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2134         return MCDisassembler::Fail;
2135       break;
2136     default:
2137       break;
2138   }
2139 
2140   if (writeback) {
2141     // On loads, the writeback operand comes after Rt.
2142     switch (Inst.getOpcode()) {
2143     case ARM::LDRD:
2144     case ARM::LDRD_PRE:
2145     case ARM::LDRD_POST:
2146     case ARM::LDRH:
2147     case ARM::LDRH_PRE:
2148     case ARM::LDRH_POST:
2149     case ARM::LDRSH:
2150     case ARM::LDRSH_PRE:
2151     case ARM::LDRSH_POST:
2152     case ARM::LDRSB:
2153     case ARM::LDRSB_PRE:
2154     case ARM::LDRSB_POST:
2155     case ARM::LDRHTr:
2156     case ARM::LDRSBTr:
2157       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2158         return MCDisassembler::Fail;
2159       break;
2160     default:
2161       break;
2162     }
2163   }
2164 
2165   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2166     return MCDisassembler::Fail;
2167 
2168   if (type) {
2169     Inst.addOperand(MCOperand::createReg(0));
2170     Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2171   } else {
2172     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2173     return MCDisassembler::Fail;
2174     Inst.addOperand(MCOperand::createImm(U));
2175   }
2176 
2177   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2178     return MCDisassembler::Fail;
2179 
2180   return S;
2181 }
2182 
2183 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2184                                  uint64_t Address, const void *Decoder) {
2185   DecodeStatus S = MCDisassembler::Success;
2186 
2187   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2188   unsigned mode = fieldFromInstruction(Insn, 23, 2);
2189 
2190   switch (mode) {
2191     case 0:
2192       mode = ARM_AM::da;
2193       break;
2194     case 1:
2195       mode = ARM_AM::ia;
2196       break;
2197     case 2:
2198       mode = ARM_AM::db;
2199       break;
2200     case 3:
2201       mode = ARM_AM::ib;
2202       break;
2203   }
2204 
2205   Inst.addOperand(MCOperand::createImm(mode));
2206   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2207     return MCDisassembler::Fail;
2208 
2209   return S;
2210 }
2211 
2212 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2213                                uint64_t Address, const void *Decoder) {
2214   DecodeStatus S = MCDisassembler::Success;
2215 
2216   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2217   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2218   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2219   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2220 
2221   if (pred == 0xF)
2222     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2223 
2224   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2225     return MCDisassembler::Fail;
2226   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2227     return MCDisassembler::Fail;
2228   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2229     return MCDisassembler::Fail;
2230   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2231     return MCDisassembler::Fail;
2232   return S;
2233 }
2234 
2235 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
2236                                   unsigned Insn,
2237                                   uint64_t Address, const void *Decoder) {
2238   DecodeStatus S = MCDisassembler::Success;
2239 
2240   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2241   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2242   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
2243 
2244   if (pred == 0xF) {
2245     // Ambiguous with RFE and SRS
2246     switch (Inst.getOpcode()) {
2247       case ARM::LDMDA:
2248         Inst.setOpcode(ARM::RFEDA);
2249         break;
2250       case ARM::LDMDA_UPD:
2251         Inst.setOpcode(ARM::RFEDA_UPD);
2252         break;
2253       case ARM::LDMDB:
2254         Inst.setOpcode(ARM::RFEDB);
2255         break;
2256       case ARM::LDMDB_UPD:
2257         Inst.setOpcode(ARM::RFEDB_UPD);
2258         break;
2259       case ARM::LDMIA:
2260         Inst.setOpcode(ARM::RFEIA);
2261         break;
2262       case ARM::LDMIA_UPD:
2263         Inst.setOpcode(ARM::RFEIA_UPD);
2264         break;
2265       case ARM::LDMIB:
2266         Inst.setOpcode(ARM::RFEIB);
2267         break;
2268       case ARM::LDMIB_UPD:
2269         Inst.setOpcode(ARM::RFEIB_UPD);
2270         break;
2271       case ARM::STMDA:
2272         Inst.setOpcode(ARM::SRSDA);
2273         break;
2274       case ARM::STMDA_UPD:
2275         Inst.setOpcode(ARM::SRSDA_UPD);
2276         break;
2277       case ARM::STMDB:
2278         Inst.setOpcode(ARM::SRSDB);
2279         break;
2280       case ARM::STMDB_UPD:
2281         Inst.setOpcode(ARM::SRSDB_UPD);
2282         break;
2283       case ARM::STMIA:
2284         Inst.setOpcode(ARM::SRSIA);
2285         break;
2286       case ARM::STMIA_UPD:
2287         Inst.setOpcode(ARM::SRSIA_UPD);
2288         break;
2289       case ARM::STMIB:
2290         Inst.setOpcode(ARM::SRSIB);
2291         break;
2292       case ARM::STMIB_UPD:
2293         Inst.setOpcode(ARM::SRSIB_UPD);
2294         break;
2295       default:
2296         return MCDisassembler::Fail;
2297     }
2298 
2299     // For stores (which become SRS's, the only operand is the mode.
2300     if (fieldFromInstruction(Insn, 20, 1) == 0) {
2301       // Check SRS encoding constraints
2302       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
2303             fieldFromInstruction(Insn, 20, 1) == 0))
2304         return MCDisassembler::Fail;
2305 
2306       Inst.addOperand(
2307           MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
2308       return S;
2309     }
2310 
2311     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2312   }
2313 
2314   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2315     return MCDisassembler::Fail;
2316   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2317     return MCDisassembler::Fail; // Tied
2318   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2319     return MCDisassembler::Fail;
2320   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2321     return MCDisassembler::Fail;
2322 
2323   return S;
2324 }
2325 
2326 // Check for UNPREDICTABLE predicated ESB instruction
2327 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2328                                  uint64_t Address, const void *Decoder) {
2329   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2330   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
2331   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2332   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2333 
2334   DecodeStatus S = MCDisassembler::Success;
2335 
2336   Inst.addOperand(MCOperand::createImm(imm8));
2337 
2338   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2339     return MCDisassembler::Fail;
2340 
2341   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
2342   // so all predicates should be allowed.
2343   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
2344     S = MCDisassembler::SoftFail;
2345 
2346   return S;
2347 }
2348 
2349 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2350                                  uint64_t Address, const void *Decoder) {
2351   unsigned imod = fieldFromInstruction(Insn, 18, 2);
2352   unsigned M = fieldFromInstruction(Insn, 17, 1);
2353   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
2354   unsigned mode = fieldFromInstruction(Insn, 0, 5);
2355 
2356   DecodeStatus S = MCDisassembler::Success;
2357 
2358   // This decoder is called from multiple location that do not check
2359   // the full encoding is valid before they do.
2360   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
2361       fieldFromInstruction(Insn, 16, 1) != 0 ||
2362       fieldFromInstruction(Insn, 20, 8) != 0x10)
2363     return MCDisassembler::Fail;
2364 
2365   // imod == '01' --> UNPREDICTABLE
2366   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2367   // return failure here.  The '01' imod value is unprintable, so there's
2368   // nothing useful we could do even if we returned UNPREDICTABLE.
2369 
2370   if (imod == 1) return MCDisassembler::Fail;
2371 
2372   if (imod && M) {
2373     Inst.setOpcode(ARM::CPS3p);
2374     Inst.addOperand(MCOperand::createImm(imod));
2375     Inst.addOperand(MCOperand::createImm(iflags));
2376     Inst.addOperand(MCOperand::createImm(mode));
2377   } else if (imod && !M) {
2378     Inst.setOpcode(ARM::CPS2p);
2379     Inst.addOperand(MCOperand::createImm(imod));
2380     Inst.addOperand(MCOperand::createImm(iflags));
2381     if (mode) S = MCDisassembler::SoftFail;
2382   } else if (!imod && M) {
2383     Inst.setOpcode(ARM::CPS1p);
2384     Inst.addOperand(MCOperand::createImm(mode));
2385     if (iflags) S = MCDisassembler::SoftFail;
2386   } else {
2387     // imod == '00' && M == '0' --> UNPREDICTABLE
2388     Inst.setOpcode(ARM::CPS1p);
2389     Inst.addOperand(MCOperand::createImm(mode));
2390     S = MCDisassembler::SoftFail;
2391   }
2392 
2393   return S;
2394 }
2395 
2396 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2397                                  uint64_t Address, const void *Decoder) {
2398   unsigned imod = fieldFromInstruction(Insn, 9, 2);
2399   unsigned M = fieldFromInstruction(Insn, 8, 1);
2400   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2401   unsigned mode = fieldFromInstruction(Insn, 0, 5);
2402 
2403   DecodeStatus S = MCDisassembler::Success;
2404 
2405   // imod == '01' --> UNPREDICTABLE
2406   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2407   // return failure here.  The '01' imod value is unprintable, so there's
2408   // nothing useful we could do even if we returned UNPREDICTABLE.
2409 
2410   if (imod == 1) return MCDisassembler::Fail;
2411 
2412   if (imod && M) {
2413     Inst.setOpcode(ARM::t2CPS3p);
2414     Inst.addOperand(MCOperand::createImm(imod));
2415     Inst.addOperand(MCOperand::createImm(iflags));
2416     Inst.addOperand(MCOperand::createImm(mode));
2417   } else if (imod && !M) {
2418     Inst.setOpcode(ARM::t2CPS2p);
2419     Inst.addOperand(MCOperand::createImm(imod));
2420     Inst.addOperand(MCOperand::createImm(iflags));
2421     if (mode) S = MCDisassembler::SoftFail;
2422   } else if (!imod && M) {
2423     Inst.setOpcode(ARM::t2CPS1p);
2424     Inst.addOperand(MCOperand::createImm(mode));
2425     if (iflags) S = MCDisassembler::SoftFail;
2426   } else {
2427     // imod == '00' && M == '0' --> this is a HINT instruction
2428     int imm = fieldFromInstruction(Insn, 0, 8);
2429     // HINT are defined only for immediate in [0..4]
2430     if(imm > 4) return MCDisassembler::Fail;
2431     Inst.setOpcode(ARM::t2HINT);
2432     Inst.addOperand(MCOperand::createImm(imm));
2433   }
2434 
2435   return S;
2436 }
2437 
2438 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2439                                  uint64_t Address, const void *Decoder) {
2440   DecodeStatus S = MCDisassembler::Success;
2441 
2442   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2443   unsigned imm = 0;
2444 
2445   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2446   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2447   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2448   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2449 
2450   if (Inst.getOpcode() == ARM::t2MOVTi16)
2451     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2452       return MCDisassembler::Fail;
2453   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2454     return MCDisassembler::Fail;
2455 
2456   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2457     Inst.addOperand(MCOperand::createImm(imm));
2458 
2459   return S;
2460 }
2461 
2462 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2463                                  uint64_t Address, const void *Decoder) {
2464   DecodeStatus S = MCDisassembler::Success;
2465 
2466   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2467   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2468   unsigned imm = 0;
2469 
2470   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2471   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2472 
2473   if (Inst.getOpcode() == ARM::MOVTi16)
2474     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2475       return MCDisassembler::Fail;
2476 
2477   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2478     return MCDisassembler::Fail;
2479 
2480   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2481     Inst.addOperand(MCOperand::createImm(imm));
2482 
2483   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2484     return MCDisassembler::Fail;
2485 
2486   return S;
2487 }
2488 
2489 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2490                                  uint64_t Address, const void *Decoder) {
2491   DecodeStatus S = MCDisassembler::Success;
2492 
2493   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2494   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2495   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2496   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2497   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2498 
2499   if (pred == 0xF)
2500     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2501 
2502   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2503     return MCDisassembler::Fail;
2504   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2505     return MCDisassembler::Fail;
2506   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2507     return MCDisassembler::Fail;
2508   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2509     return MCDisassembler::Fail;
2510 
2511   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2512     return MCDisassembler::Fail;
2513 
2514   return S;
2515 }
2516 
2517 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2518                                   uint64_t Address, const void *Decoder) {
2519   DecodeStatus S = MCDisassembler::Success;
2520 
2521   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2522   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2523   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2524 
2525   if (Pred == 0xF)
2526     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2527 
2528   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2529     return MCDisassembler::Fail;
2530   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2531     return MCDisassembler::Fail;
2532   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2533     return MCDisassembler::Fail;
2534 
2535   return S;
2536 }
2537 
2538 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2539                                   uint64_t Address, const void *Decoder) {
2540   DecodeStatus S = MCDisassembler::Success;
2541 
2542   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2543 
2544   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2545   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2546 
2547   if (!FeatureBits[ARM::HasV8_1aOps] ||
2548       !FeatureBits[ARM::HasV8Ops])
2549     return MCDisassembler::Fail;
2550 
2551   // Decoder can be called from DecodeTST, which does not check the full
2552   // encoding is valid.
2553   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2554       fieldFromInstruction(Insn, 4,4) != 0)
2555     return MCDisassembler::Fail;
2556   if (fieldFromInstruction(Insn, 10,10) != 0 ||
2557       fieldFromInstruction(Insn, 0,4) != 0)
2558     S = MCDisassembler::SoftFail;
2559 
2560   Inst.setOpcode(ARM::SETPAN);
2561   Inst.addOperand(MCOperand::createImm(Imm));
2562 
2563   return S;
2564 }
2565 
2566 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2567                            uint64_t Address, const void *Decoder) {
2568   DecodeStatus S = MCDisassembler::Success;
2569 
2570   unsigned add = fieldFromInstruction(Val, 12, 1);
2571   unsigned imm = fieldFromInstruction(Val, 0, 12);
2572   unsigned Rn = fieldFromInstruction(Val, 13, 4);
2573 
2574   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2575     return MCDisassembler::Fail;
2576 
2577   if (!add) imm *= -1;
2578   if (imm == 0 && !add) imm = INT32_MIN;
2579   Inst.addOperand(MCOperand::createImm(imm));
2580   if (Rn == 15)
2581     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2582 
2583   return S;
2584 }
2585 
2586 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2587                                    uint64_t Address, const void *Decoder) {
2588   DecodeStatus S = MCDisassembler::Success;
2589 
2590   unsigned Rn = fieldFromInstruction(Val, 9, 4);
2591   // U == 1 to add imm, 0 to subtract it.
2592   unsigned U = fieldFromInstruction(Val, 8, 1);
2593   unsigned imm = fieldFromInstruction(Val, 0, 8);
2594 
2595   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2596     return MCDisassembler::Fail;
2597 
2598   if (U)
2599     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2600   else
2601     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2602 
2603   return S;
2604 }
2605 
2606 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2607                                    uint64_t Address, const void *Decoder) {
2608   DecodeStatus S = MCDisassembler::Success;
2609 
2610   unsigned Rn = fieldFromInstruction(Val, 9, 4);
2611   // U == 1 to add imm, 0 to subtract it.
2612   unsigned U = fieldFromInstruction(Val, 8, 1);
2613   unsigned imm = fieldFromInstruction(Val, 0, 8);
2614 
2615   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2616     return MCDisassembler::Fail;
2617 
2618   if (U)
2619     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2620   else
2621     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2622 
2623   return S;
2624 }
2625 
2626 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2627                                    uint64_t Address, const void *Decoder) {
2628   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2629 }
2630 
2631 static DecodeStatus
2632 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2633                      uint64_t Address, const void *Decoder) {
2634   DecodeStatus Status = MCDisassembler::Success;
2635 
2636   // Note the J1 and J2 values are from the encoded instruction.  So here
2637   // change them to I1 and I2 values via as documented:
2638   // I1 = NOT(J1 EOR S);
2639   // I2 = NOT(J2 EOR S);
2640   // and build the imm32 with one trailing zero as documented:
2641   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2642   unsigned S = fieldFromInstruction(Insn, 26, 1);
2643   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2644   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2645   unsigned I1 = !(J1 ^ S);
2646   unsigned I2 = !(J2 ^ S);
2647   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2648   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2649   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2650   int imm32 = SignExtend32<25>(tmp << 1);
2651   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2652                                 true, 4, Inst, Decoder))
2653     Inst.addOperand(MCOperand::createImm(imm32));
2654 
2655   return Status;
2656 }
2657 
2658 static DecodeStatus
2659 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2660                            uint64_t Address, const void *Decoder) {
2661   DecodeStatus S = MCDisassembler::Success;
2662 
2663   unsigned pred = fieldFromInstruction(Insn, 28, 4);
2664   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2665 
2666   if (pred == 0xF) {
2667     Inst.setOpcode(ARM::BLXi);
2668     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2669     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2670                                   true, 4, Inst, Decoder))
2671     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2672     return S;
2673   }
2674 
2675   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2676                                 true, 4, Inst, Decoder))
2677     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2678   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2679     return MCDisassembler::Fail;
2680 
2681   return S;
2682 }
2683 
2684 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2685                                    uint64_t Address, const void *Decoder) {
2686   DecodeStatus S = MCDisassembler::Success;
2687 
2688   unsigned Rm = fieldFromInstruction(Val, 0, 4);
2689   unsigned align = fieldFromInstruction(Val, 4, 2);
2690 
2691   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2692     return MCDisassembler::Fail;
2693   if (!align)
2694     Inst.addOperand(MCOperand::createImm(0));
2695   else
2696     Inst.addOperand(MCOperand::createImm(4 << align));
2697 
2698   return S;
2699 }
2700 
2701 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2702                                    uint64_t Address, const void *Decoder) {
2703   DecodeStatus S = MCDisassembler::Success;
2704 
2705   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2706   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2707   unsigned wb = fieldFromInstruction(Insn, 16, 4);
2708   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2709   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2710   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2711 
2712   // First output register
2713   switch (Inst.getOpcode()) {
2714   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2715   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2716   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2717   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2718   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2719   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2720   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2721   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2722   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2723     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2724       return MCDisassembler::Fail;
2725     break;
2726   case ARM::VLD2b16:
2727   case ARM::VLD2b32:
2728   case ARM::VLD2b8:
2729   case ARM::VLD2b16wb_fixed:
2730   case ARM::VLD2b16wb_register:
2731   case ARM::VLD2b32wb_fixed:
2732   case ARM::VLD2b32wb_register:
2733   case ARM::VLD2b8wb_fixed:
2734   case ARM::VLD2b8wb_register:
2735     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2736       return MCDisassembler::Fail;
2737     break;
2738   default:
2739     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2740       return MCDisassembler::Fail;
2741   }
2742 
2743   // Second output register
2744   switch (Inst.getOpcode()) {
2745     case ARM::VLD3d8:
2746     case ARM::VLD3d16:
2747     case ARM::VLD3d32:
2748     case ARM::VLD3d8_UPD:
2749     case ARM::VLD3d16_UPD:
2750     case ARM::VLD3d32_UPD:
2751     case ARM::VLD4d8:
2752     case ARM::VLD4d16:
2753     case ARM::VLD4d32:
2754     case ARM::VLD4d8_UPD:
2755     case ARM::VLD4d16_UPD:
2756     case ARM::VLD4d32_UPD:
2757       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2758         return MCDisassembler::Fail;
2759       break;
2760     case ARM::VLD3q8:
2761     case ARM::VLD3q16:
2762     case ARM::VLD3q32:
2763     case ARM::VLD3q8_UPD:
2764     case ARM::VLD3q16_UPD:
2765     case ARM::VLD3q32_UPD:
2766     case ARM::VLD4q8:
2767     case ARM::VLD4q16:
2768     case ARM::VLD4q32:
2769     case ARM::VLD4q8_UPD:
2770     case ARM::VLD4q16_UPD:
2771     case ARM::VLD4q32_UPD:
2772       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2773         return MCDisassembler::Fail;
2774       break;
2775     default:
2776       break;
2777   }
2778 
2779   // Third output register
2780   switch(Inst.getOpcode()) {
2781     case ARM::VLD3d8:
2782     case ARM::VLD3d16:
2783     case ARM::VLD3d32:
2784     case ARM::VLD3d8_UPD:
2785     case ARM::VLD3d16_UPD:
2786     case ARM::VLD3d32_UPD:
2787     case ARM::VLD4d8:
2788     case ARM::VLD4d16:
2789     case ARM::VLD4d32:
2790     case ARM::VLD4d8_UPD:
2791     case ARM::VLD4d16_UPD:
2792     case ARM::VLD4d32_UPD:
2793       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2794         return MCDisassembler::Fail;
2795       break;
2796     case ARM::VLD3q8:
2797     case ARM::VLD3q16:
2798     case ARM::VLD3q32:
2799     case ARM::VLD3q8_UPD:
2800     case ARM::VLD3q16_UPD:
2801     case ARM::VLD3q32_UPD:
2802     case ARM::VLD4q8:
2803     case ARM::VLD4q16:
2804     case ARM::VLD4q32:
2805     case ARM::VLD4q8_UPD:
2806     case ARM::VLD4q16_UPD:
2807     case ARM::VLD4q32_UPD:
2808       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2809         return MCDisassembler::Fail;
2810       break;
2811     default:
2812       break;
2813   }
2814 
2815   // Fourth output register
2816   switch (Inst.getOpcode()) {
2817     case ARM::VLD4d8:
2818     case ARM::VLD4d16:
2819     case ARM::VLD4d32:
2820     case ARM::VLD4d8_UPD:
2821     case ARM::VLD4d16_UPD:
2822     case ARM::VLD4d32_UPD:
2823       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2824         return MCDisassembler::Fail;
2825       break;
2826     case ARM::VLD4q8:
2827     case ARM::VLD4q16:
2828     case ARM::VLD4q32:
2829     case ARM::VLD4q8_UPD:
2830     case ARM::VLD4q16_UPD:
2831     case ARM::VLD4q32_UPD:
2832       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2833         return MCDisassembler::Fail;
2834       break;
2835     default:
2836       break;
2837   }
2838 
2839   // Writeback operand
2840   switch (Inst.getOpcode()) {
2841     case ARM::VLD1d8wb_fixed:
2842     case ARM::VLD1d16wb_fixed:
2843     case ARM::VLD1d32wb_fixed:
2844     case ARM::VLD1d64wb_fixed:
2845     case ARM::VLD1d8wb_register:
2846     case ARM::VLD1d16wb_register:
2847     case ARM::VLD1d32wb_register:
2848     case ARM::VLD1d64wb_register:
2849     case ARM::VLD1q8wb_fixed:
2850     case ARM::VLD1q16wb_fixed:
2851     case ARM::VLD1q32wb_fixed:
2852     case ARM::VLD1q64wb_fixed:
2853     case ARM::VLD1q8wb_register:
2854     case ARM::VLD1q16wb_register:
2855     case ARM::VLD1q32wb_register:
2856     case ARM::VLD1q64wb_register:
2857     case ARM::VLD1d8Twb_fixed:
2858     case ARM::VLD1d8Twb_register:
2859     case ARM::VLD1d16Twb_fixed:
2860     case ARM::VLD1d16Twb_register:
2861     case ARM::VLD1d32Twb_fixed:
2862     case ARM::VLD1d32Twb_register:
2863     case ARM::VLD1d64Twb_fixed:
2864     case ARM::VLD1d64Twb_register:
2865     case ARM::VLD1d8Qwb_fixed:
2866     case ARM::VLD1d8Qwb_register:
2867     case ARM::VLD1d16Qwb_fixed:
2868     case ARM::VLD1d16Qwb_register:
2869     case ARM::VLD1d32Qwb_fixed:
2870     case ARM::VLD1d32Qwb_register:
2871     case ARM::VLD1d64Qwb_fixed:
2872     case ARM::VLD1d64Qwb_register:
2873     case ARM::VLD2d8wb_fixed:
2874     case ARM::VLD2d16wb_fixed:
2875     case ARM::VLD2d32wb_fixed:
2876     case ARM::VLD2q8wb_fixed:
2877     case ARM::VLD2q16wb_fixed:
2878     case ARM::VLD2q32wb_fixed:
2879     case ARM::VLD2d8wb_register:
2880     case ARM::VLD2d16wb_register:
2881     case ARM::VLD2d32wb_register:
2882     case ARM::VLD2q8wb_register:
2883     case ARM::VLD2q16wb_register:
2884     case ARM::VLD2q32wb_register:
2885     case ARM::VLD2b8wb_fixed:
2886     case ARM::VLD2b16wb_fixed:
2887     case ARM::VLD2b32wb_fixed:
2888     case ARM::VLD2b8wb_register:
2889     case ARM::VLD2b16wb_register:
2890     case ARM::VLD2b32wb_register:
2891       Inst.addOperand(MCOperand::createImm(0));
2892       break;
2893     case ARM::VLD3d8_UPD:
2894     case ARM::VLD3d16_UPD:
2895     case ARM::VLD3d32_UPD:
2896     case ARM::VLD3q8_UPD:
2897     case ARM::VLD3q16_UPD:
2898     case ARM::VLD3q32_UPD:
2899     case ARM::VLD4d8_UPD:
2900     case ARM::VLD4d16_UPD:
2901     case ARM::VLD4d32_UPD:
2902     case ARM::VLD4q8_UPD:
2903     case ARM::VLD4q16_UPD:
2904     case ARM::VLD4q32_UPD:
2905       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2906         return MCDisassembler::Fail;
2907       break;
2908     default:
2909       break;
2910   }
2911 
2912   // AddrMode6 Base (register+alignment)
2913   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2914     return MCDisassembler::Fail;
2915 
2916   // AddrMode6 Offset (register)
2917   switch (Inst.getOpcode()) {
2918   default:
2919     // The below have been updated to have explicit am6offset split
2920     // between fixed and register offset. For those instructions not
2921     // yet updated, we need to add an additional reg0 operand for the
2922     // fixed variant.
2923     //
2924     // The fixed offset encodes as Rm == 0xd, so we check for that.
2925     if (Rm == 0xd) {
2926       Inst.addOperand(MCOperand::createReg(0));
2927       break;
2928     }
2929     // Fall through to handle the register offset variant.
2930     LLVM_FALLTHROUGH;
2931   case ARM::VLD1d8wb_fixed:
2932   case ARM::VLD1d16wb_fixed:
2933   case ARM::VLD1d32wb_fixed:
2934   case ARM::VLD1d64wb_fixed:
2935   case ARM::VLD1d8Twb_fixed:
2936   case ARM::VLD1d16Twb_fixed:
2937   case ARM::VLD1d32Twb_fixed:
2938   case ARM::VLD1d64Twb_fixed:
2939   case ARM::VLD1d8Qwb_fixed:
2940   case ARM::VLD1d16Qwb_fixed:
2941   case ARM::VLD1d32Qwb_fixed:
2942   case ARM::VLD1d64Qwb_fixed:
2943   case ARM::VLD1d8wb_register:
2944   case ARM::VLD1d16wb_register:
2945   case ARM::VLD1d32wb_register:
2946   case ARM::VLD1d64wb_register:
2947   case ARM::VLD1q8wb_fixed:
2948   case ARM::VLD1q16wb_fixed:
2949   case ARM::VLD1q32wb_fixed:
2950   case ARM::VLD1q64wb_fixed:
2951   case ARM::VLD1q8wb_register:
2952   case ARM::VLD1q16wb_register:
2953   case ARM::VLD1q32wb_register:
2954   case ARM::VLD1q64wb_register:
2955     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2956     // variant encodes Rm == 0xf. Anything else is a register offset post-
2957     // increment and we need to add the register operand to the instruction.
2958     if (Rm != 0xD && Rm != 0xF &&
2959         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2960       return MCDisassembler::Fail;
2961     break;
2962   case ARM::VLD2d8wb_fixed:
2963   case ARM::VLD2d16wb_fixed:
2964   case ARM::VLD2d32wb_fixed:
2965   case ARM::VLD2b8wb_fixed:
2966   case ARM::VLD2b16wb_fixed:
2967   case ARM::VLD2b32wb_fixed:
2968   case ARM::VLD2q8wb_fixed:
2969   case ARM::VLD2q16wb_fixed:
2970   case ARM::VLD2q32wb_fixed:
2971     break;
2972   }
2973 
2974   return S;
2975 }
2976 
2977 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2978                                    uint64_t Address, const void *Decoder) {
2979   unsigned type = fieldFromInstruction(Insn, 8, 4);
2980   unsigned align = fieldFromInstruction(Insn, 4, 2);
2981   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2982   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2983   if (type == 10 && align == 3) return MCDisassembler::Fail;
2984 
2985   unsigned load = fieldFromInstruction(Insn, 21, 1);
2986   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2987               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2988 }
2989 
2990 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2991                                    uint64_t Address, const void *Decoder) {
2992   unsigned size = fieldFromInstruction(Insn, 6, 2);
2993   if (size == 3) return MCDisassembler::Fail;
2994 
2995   unsigned type = fieldFromInstruction(Insn, 8, 4);
2996   unsigned align = fieldFromInstruction(Insn, 4, 2);
2997   if (type == 8 && align == 3) return MCDisassembler::Fail;
2998   if (type == 9 && align == 3) return MCDisassembler::Fail;
2999 
3000   unsigned load = fieldFromInstruction(Insn, 21, 1);
3001   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3002               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3003 }
3004 
3005 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3006                                    uint64_t Address, const void *Decoder) {
3007   unsigned size = fieldFromInstruction(Insn, 6, 2);
3008   if (size == 3) return MCDisassembler::Fail;
3009 
3010   unsigned align = fieldFromInstruction(Insn, 4, 2);
3011   if (align & 2) return MCDisassembler::Fail;
3012 
3013   unsigned load = fieldFromInstruction(Insn, 21, 1);
3014   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3015               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3016 }
3017 
3018 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3019                                    uint64_t Address, const void *Decoder) {
3020   unsigned size = fieldFromInstruction(Insn, 6, 2);
3021   if (size == 3) return MCDisassembler::Fail;
3022 
3023   unsigned load = fieldFromInstruction(Insn, 21, 1);
3024   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3025               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3026 }
3027 
3028 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3029                                  uint64_t Address, const void *Decoder) {
3030   DecodeStatus S = MCDisassembler::Success;
3031 
3032   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3033   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3034   unsigned wb = fieldFromInstruction(Insn, 16, 4);
3035   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3036   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
3037   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3038 
3039   // Writeback Operand
3040   switch (Inst.getOpcode()) {
3041     case ARM::VST1d8wb_fixed:
3042     case ARM::VST1d16wb_fixed:
3043     case ARM::VST1d32wb_fixed:
3044     case ARM::VST1d64wb_fixed:
3045     case ARM::VST1d8wb_register:
3046     case ARM::VST1d16wb_register:
3047     case ARM::VST1d32wb_register:
3048     case ARM::VST1d64wb_register:
3049     case ARM::VST1q8wb_fixed:
3050     case ARM::VST1q16wb_fixed:
3051     case ARM::VST1q32wb_fixed:
3052     case ARM::VST1q64wb_fixed:
3053     case ARM::VST1q8wb_register:
3054     case ARM::VST1q16wb_register:
3055     case ARM::VST1q32wb_register:
3056     case ARM::VST1q64wb_register:
3057     case ARM::VST1d8Twb_fixed:
3058     case ARM::VST1d16Twb_fixed:
3059     case ARM::VST1d32Twb_fixed:
3060     case ARM::VST1d64Twb_fixed:
3061     case ARM::VST1d8Twb_register:
3062     case ARM::VST1d16Twb_register:
3063     case ARM::VST1d32Twb_register:
3064     case ARM::VST1d64Twb_register:
3065     case ARM::VST1d8Qwb_fixed:
3066     case ARM::VST1d16Qwb_fixed:
3067     case ARM::VST1d32Qwb_fixed:
3068     case ARM::VST1d64Qwb_fixed:
3069     case ARM::VST1d8Qwb_register:
3070     case ARM::VST1d16Qwb_register:
3071     case ARM::VST1d32Qwb_register:
3072     case ARM::VST1d64Qwb_register:
3073     case ARM::VST2d8wb_fixed:
3074     case ARM::VST2d16wb_fixed:
3075     case ARM::VST2d32wb_fixed:
3076     case ARM::VST2d8wb_register:
3077     case ARM::VST2d16wb_register:
3078     case ARM::VST2d32wb_register:
3079     case ARM::VST2q8wb_fixed:
3080     case ARM::VST2q16wb_fixed:
3081     case ARM::VST2q32wb_fixed:
3082     case ARM::VST2q8wb_register:
3083     case ARM::VST2q16wb_register:
3084     case ARM::VST2q32wb_register:
3085     case ARM::VST2b8wb_fixed:
3086     case ARM::VST2b16wb_fixed:
3087     case ARM::VST2b32wb_fixed:
3088     case ARM::VST2b8wb_register:
3089     case ARM::VST2b16wb_register:
3090     case ARM::VST2b32wb_register:
3091       if (Rm == 0xF)
3092         return MCDisassembler::Fail;
3093       Inst.addOperand(MCOperand::createImm(0));
3094       break;
3095     case ARM::VST3d8_UPD:
3096     case ARM::VST3d16_UPD:
3097     case ARM::VST3d32_UPD:
3098     case ARM::VST3q8_UPD:
3099     case ARM::VST3q16_UPD:
3100     case ARM::VST3q32_UPD:
3101     case ARM::VST4d8_UPD:
3102     case ARM::VST4d16_UPD:
3103     case ARM::VST4d32_UPD:
3104     case ARM::VST4q8_UPD:
3105     case ARM::VST4q16_UPD:
3106     case ARM::VST4q32_UPD:
3107       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3108         return MCDisassembler::Fail;
3109       break;
3110     default:
3111       break;
3112   }
3113 
3114   // AddrMode6 Base (register+alignment)
3115   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3116     return MCDisassembler::Fail;
3117 
3118   // AddrMode6 Offset (register)
3119   switch (Inst.getOpcode()) {
3120     default:
3121       if (Rm == 0xD)
3122         Inst.addOperand(MCOperand::createReg(0));
3123       else if (Rm != 0xF) {
3124         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3125           return MCDisassembler::Fail;
3126       }
3127       break;
3128     case ARM::VST1d8wb_fixed:
3129     case ARM::VST1d16wb_fixed:
3130     case ARM::VST1d32wb_fixed:
3131     case ARM::VST1d64wb_fixed:
3132     case ARM::VST1q8wb_fixed:
3133     case ARM::VST1q16wb_fixed:
3134     case ARM::VST1q32wb_fixed:
3135     case ARM::VST1q64wb_fixed:
3136     case ARM::VST1d8Twb_fixed:
3137     case ARM::VST1d16Twb_fixed:
3138     case ARM::VST1d32Twb_fixed:
3139     case ARM::VST1d64Twb_fixed:
3140     case ARM::VST1d8Qwb_fixed:
3141     case ARM::VST1d16Qwb_fixed:
3142     case ARM::VST1d32Qwb_fixed:
3143     case ARM::VST1d64Qwb_fixed:
3144     case ARM::VST2d8wb_fixed:
3145     case ARM::VST2d16wb_fixed:
3146     case ARM::VST2d32wb_fixed:
3147     case ARM::VST2q8wb_fixed:
3148     case ARM::VST2q16wb_fixed:
3149     case ARM::VST2q32wb_fixed:
3150     case ARM::VST2b8wb_fixed:
3151     case ARM::VST2b16wb_fixed:
3152     case ARM::VST2b32wb_fixed:
3153       break;
3154   }
3155 
3156   // First input register
3157   switch (Inst.getOpcode()) {
3158   case ARM::VST1q16:
3159   case ARM::VST1q32:
3160   case ARM::VST1q64:
3161   case ARM::VST1q8:
3162   case ARM::VST1q16wb_fixed:
3163   case ARM::VST1q16wb_register:
3164   case ARM::VST1q32wb_fixed:
3165   case ARM::VST1q32wb_register:
3166   case ARM::VST1q64wb_fixed:
3167   case ARM::VST1q64wb_register:
3168   case ARM::VST1q8wb_fixed:
3169   case ARM::VST1q8wb_register:
3170   case ARM::VST2d16:
3171   case ARM::VST2d32:
3172   case ARM::VST2d8:
3173   case ARM::VST2d16wb_fixed:
3174   case ARM::VST2d16wb_register:
3175   case ARM::VST2d32wb_fixed:
3176   case ARM::VST2d32wb_register:
3177   case ARM::VST2d8wb_fixed:
3178   case ARM::VST2d8wb_register:
3179     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3180       return MCDisassembler::Fail;
3181     break;
3182   case ARM::VST2b16:
3183   case ARM::VST2b32:
3184   case ARM::VST2b8:
3185   case ARM::VST2b16wb_fixed:
3186   case ARM::VST2b16wb_register:
3187   case ARM::VST2b32wb_fixed:
3188   case ARM::VST2b32wb_register:
3189   case ARM::VST2b8wb_fixed:
3190   case ARM::VST2b8wb_register:
3191     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3192       return MCDisassembler::Fail;
3193     break;
3194   default:
3195     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3196       return MCDisassembler::Fail;
3197   }
3198 
3199   // Second input register
3200   switch (Inst.getOpcode()) {
3201     case ARM::VST3d8:
3202     case ARM::VST3d16:
3203     case ARM::VST3d32:
3204     case ARM::VST3d8_UPD:
3205     case ARM::VST3d16_UPD:
3206     case ARM::VST3d32_UPD:
3207     case ARM::VST4d8:
3208     case ARM::VST4d16:
3209     case ARM::VST4d32:
3210     case ARM::VST4d8_UPD:
3211     case ARM::VST4d16_UPD:
3212     case ARM::VST4d32_UPD:
3213       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3214         return MCDisassembler::Fail;
3215       break;
3216     case ARM::VST3q8:
3217     case ARM::VST3q16:
3218     case ARM::VST3q32:
3219     case ARM::VST3q8_UPD:
3220     case ARM::VST3q16_UPD:
3221     case ARM::VST3q32_UPD:
3222     case ARM::VST4q8:
3223     case ARM::VST4q16:
3224     case ARM::VST4q32:
3225     case ARM::VST4q8_UPD:
3226     case ARM::VST4q16_UPD:
3227     case ARM::VST4q32_UPD:
3228       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3229         return MCDisassembler::Fail;
3230       break;
3231     default:
3232       break;
3233   }
3234 
3235   // Third input register
3236   switch (Inst.getOpcode()) {
3237     case ARM::VST3d8:
3238     case ARM::VST3d16:
3239     case ARM::VST3d32:
3240     case ARM::VST3d8_UPD:
3241     case ARM::VST3d16_UPD:
3242     case ARM::VST3d32_UPD:
3243     case ARM::VST4d8:
3244     case ARM::VST4d16:
3245     case ARM::VST4d32:
3246     case ARM::VST4d8_UPD:
3247     case ARM::VST4d16_UPD:
3248     case ARM::VST4d32_UPD:
3249       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3250         return MCDisassembler::Fail;
3251       break;
3252     case ARM::VST3q8:
3253     case ARM::VST3q16:
3254     case ARM::VST3q32:
3255     case ARM::VST3q8_UPD:
3256     case ARM::VST3q16_UPD:
3257     case ARM::VST3q32_UPD:
3258     case ARM::VST4q8:
3259     case ARM::VST4q16:
3260     case ARM::VST4q32:
3261     case ARM::VST4q8_UPD:
3262     case ARM::VST4q16_UPD:
3263     case ARM::VST4q32_UPD:
3264       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3265         return MCDisassembler::Fail;
3266       break;
3267     default:
3268       break;
3269   }
3270 
3271   // Fourth input register
3272   switch (Inst.getOpcode()) {
3273     case ARM::VST4d8:
3274     case ARM::VST4d16:
3275     case ARM::VST4d32:
3276     case ARM::VST4d8_UPD:
3277     case ARM::VST4d16_UPD:
3278     case ARM::VST4d32_UPD:
3279       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3280         return MCDisassembler::Fail;
3281       break;
3282     case ARM::VST4q8:
3283     case ARM::VST4q16:
3284     case ARM::VST4q32:
3285     case ARM::VST4q8_UPD:
3286     case ARM::VST4q16_UPD:
3287     case ARM::VST4q32_UPD:
3288       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3289         return MCDisassembler::Fail;
3290       break;
3291     default:
3292       break;
3293   }
3294 
3295   return S;
3296 }
3297 
3298 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3299                                     uint64_t Address, const void *Decoder) {
3300   DecodeStatus S = MCDisassembler::Success;
3301 
3302   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3303   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3304   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3305   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3306   unsigned align = fieldFromInstruction(Insn, 4, 1);
3307   unsigned size = fieldFromInstruction(Insn, 6, 2);
3308 
3309   if (size == 0 && align == 1)
3310     return MCDisassembler::Fail;
3311   align *= (1 << size);
3312 
3313   switch (Inst.getOpcode()) {
3314   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
3315   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
3316   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
3317   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
3318     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3319       return MCDisassembler::Fail;
3320     break;
3321   default:
3322     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3323       return MCDisassembler::Fail;
3324     break;
3325   }
3326   if (Rm != 0xF) {
3327     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3328       return MCDisassembler::Fail;
3329   }
3330 
3331   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332     return MCDisassembler::Fail;
3333   Inst.addOperand(MCOperand::createImm(align));
3334 
3335   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
3336   // variant encodes Rm == 0xf. Anything else is a register offset post-
3337   // increment and we need to add the register operand to the instruction.
3338   if (Rm != 0xD && Rm != 0xF &&
3339       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3340     return MCDisassembler::Fail;
3341 
3342   return S;
3343 }
3344 
3345 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3346                                     uint64_t Address, const void *Decoder) {
3347   DecodeStatus S = MCDisassembler::Success;
3348 
3349   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3350   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3351   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3352   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3353   unsigned align = fieldFromInstruction(Insn, 4, 1);
3354   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
3355   align *= 2*size;
3356 
3357   switch (Inst.getOpcode()) {
3358   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
3359   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
3360   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
3361   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
3362     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3363       return MCDisassembler::Fail;
3364     break;
3365   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
3366   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
3367   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
3368   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
3369     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3370       return MCDisassembler::Fail;
3371     break;
3372   default:
3373     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3374       return MCDisassembler::Fail;
3375     break;
3376   }
3377 
3378   if (Rm != 0xF)
3379     Inst.addOperand(MCOperand::createImm(0));
3380 
3381   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3382     return MCDisassembler::Fail;
3383   Inst.addOperand(MCOperand::createImm(align));
3384 
3385   if (Rm != 0xD && Rm != 0xF) {
3386     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3387       return MCDisassembler::Fail;
3388   }
3389 
3390   return S;
3391 }
3392 
3393 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3394                                     uint64_t Address, const void *Decoder) {
3395   DecodeStatus S = MCDisassembler::Success;
3396 
3397   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3398   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3399   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3400   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3401   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3402 
3403   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3404     return MCDisassembler::Fail;
3405   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3406     return MCDisassembler::Fail;
3407   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3408     return MCDisassembler::Fail;
3409   if (Rm != 0xF) {
3410     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3411       return MCDisassembler::Fail;
3412   }
3413 
3414   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3415     return MCDisassembler::Fail;
3416   Inst.addOperand(MCOperand::createImm(0));
3417 
3418   if (Rm == 0xD)
3419     Inst.addOperand(MCOperand::createReg(0));
3420   else if (Rm != 0xF) {
3421     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3422       return MCDisassembler::Fail;
3423   }
3424 
3425   return S;
3426 }
3427 
3428 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3429                                     uint64_t Address, const void *Decoder) {
3430   DecodeStatus S = MCDisassembler::Success;
3431 
3432   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3433   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3434   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3435   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3436   unsigned size = fieldFromInstruction(Insn, 6, 2);
3437   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3438   unsigned align = fieldFromInstruction(Insn, 4, 1);
3439 
3440   if (size == 0x3) {
3441     if (align == 0)
3442       return MCDisassembler::Fail;
3443     align = 16;
3444   } else {
3445     if (size == 2) {
3446       align *= 8;
3447     } else {
3448       size = 1 << size;
3449       align *= 4*size;
3450     }
3451   }
3452 
3453   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3454     return MCDisassembler::Fail;
3455   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3456     return MCDisassembler::Fail;
3457   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3458     return MCDisassembler::Fail;
3459   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3460     return MCDisassembler::Fail;
3461   if (Rm != 0xF) {
3462     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3463       return MCDisassembler::Fail;
3464   }
3465 
3466   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3467     return MCDisassembler::Fail;
3468   Inst.addOperand(MCOperand::createImm(align));
3469 
3470   if (Rm == 0xD)
3471     Inst.addOperand(MCOperand::createReg(0));
3472   else if (Rm != 0xF) {
3473     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3474       return MCDisassembler::Fail;
3475   }
3476 
3477   return S;
3478 }
3479 
3480 static DecodeStatus
3481 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3482                             uint64_t Address, const void *Decoder) {
3483   DecodeStatus S = MCDisassembler::Success;
3484 
3485   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3486   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3487   unsigned imm = fieldFromInstruction(Insn, 0, 4);
3488   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3489   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3490   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3491   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3492   unsigned Q = fieldFromInstruction(Insn, 6, 1);
3493 
3494   if (Q) {
3495     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3496     return MCDisassembler::Fail;
3497   } else {
3498     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3499     return MCDisassembler::Fail;
3500   }
3501 
3502   Inst.addOperand(MCOperand::createImm(imm));
3503 
3504   switch (Inst.getOpcode()) {
3505     case ARM::VORRiv4i16:
3506     case ARM::VORRiv2i32:
3507     case ARM::VBICiv4i16:
3508     case ARM::VBICiv2i32:
3509       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3510         return MCDisassembler::Fail;
3511       break;
3512     case ARM::VORRiv8i16:
3513     case ARM::VORRiv4i32:
3514     case ARM::VBICiv8i16:
3515     case ARM::VBICiv4i32:
3516       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3517         return MCDisassembler::Fail;
3518       break;
3519     default:
3520       break;
3521   }
3522 
3523   return S;
3524 }
3525 
3526 static DecodeStatus
3527 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3528                            uint64_t Address, const void *Decoder) {
3529   DecodeStatus S = MCDisassembler::Success;
3530 
3531   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
3532                  fieldFromInstruction(Insn, 13, 3));
3533   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
3534   unsigned imm = fieldFromInstruction(Insn, 0, 4);
3535   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3536   imm |= fieldFromInstruction(Insn, 28, 1) << 7;
3537   imm |= cmode                             << 8;
3538   imm |= fieldFromInstruction(Insn, 5, 1)  << 12;
3539 
3540   if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3541     return MCDisassembler::Fail;
3542 
3543   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3544     return MCDisassembler::Fail;
3545 
3546   Inst.addOperand(MCOperand::createImm(imm));
3547 
3548   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3549   Inst.addOperand(MCOperand::createReg(0));
3550   Inst.addOperand(MCOperand::createImm(0));
3551 
3552   return S;
3553 }
3554 
3555 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3556                                uint64_t Address, const void *Decoder) {
3557   DecodeStatus S = MCDisassembler::Success;
3558 
3559   unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3560   Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3561   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3562     return MCDisassembler::Fail;
3563   Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3564 
3565   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3566   Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3567   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3568     return MCDisassembler::Fail;
3569   unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3570   Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3571   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3572     return MCDisassembler::Fail;
3573   if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3574     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3575   Inst.addOperand(MCOperand::createImm(Qd));
3576 
3577   return S;
3578 }
3579 
3580 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3581                                         uint64_t Address, const void *Decoder) {
3582   DecodeStatus S = MCDisassembler::Success;
3583 
3584   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3585   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3586   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3587   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3588   unsigned size = fieldFromInstruction(Insn, 18, 2);
3589 
3590   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3591     return MCDisassembler::Fail;
3592   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3593     return MCDisassembler::Fail;
3594   Inst.addOperand(MCOperand::createImm(8 << size));
3595 
3596   return S;
3597 }
3598 
3599 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3600                                uint64_t Address, const void *Decoder) {
3601   Inst.addOperand(MCOperand::createImm(8 - Val));
3602   return MCDisassembler::Success;
3603 }
3604 
3605 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3606                                uint64_t Address, const void *Decoder) {
3607   Inst.addOperand(MCOperand::createImm(16 - Val));
3608   return MCDisassembler::Success;
3609 }
3610 
3611 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3612                                uint64_t Address, const void *Decoder) {
3613   Inst.addOperand(MCOperand::createImm(32 - Val));
3614   return MCDisassembler::Success;
3615 }
3616 
3617 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3618                                uint64_t Address, const void *Decoder) {
3619   Inst.addOperand(MCOperand::createImm(64 - Val));
3620   return MCDisassembler::Success;
3621 }
3622 
3623 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3624                                uint64_t Address, const void *Decoder) {
3625   DecodeStatus S = MCDisassembler::Success;
3626 
3627   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3628   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3629   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3630   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3631   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3632   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3633   unsigned op = fieldFromInstruction(Insn, 6, 1);
3634 
3635   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3636     return MCDisassembler::Fail;
3637   if (op) {
3638     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3639     return MCDisassembler::Fail; // Writeback
3640   }
3641 
3642   switch (Inst.getOpcode()) {
3643   case ARM::VTBL2:
3644   case ARM::VTBX2:
3645     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3646       return MCDisassembler::Fail;
3647     break;
3648   default:
3649     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3650       return MCDisassembler::Fail;
3651   }
3652 
3653   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3654     return MCDisassembler::Fail;
3655 
3656   return S;
3657 }
3658 
3659 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3660                                      uint64_t Address, const void *Decoder) {
3661   DecodeStatus S = MCDisassembler::Success;
3662 
3663   unsigned dst = fieldFromInstruction(Insn, 8, 3);
3664   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3665 
3666   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3667     return MCDisassembler::Fail;
3668 
3669   switch(Inst.getOpcode()) {
3670     default:
3671       return MCDisassembler::Fail;
3672     case ARM::tADR:
3673       break; // tADR does not explicitly represent the PC as an operand.
3674     case ARM::tADDrSPi:
3675       Inst.addOperand(MCOperand::createReg(ARM::SP));
3676       break;
3677   }
3678 
3679   Inst.addOperand(MCOperand::createImm(imm));
3680   return S;
3681 }
3682 
3683 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3684                                  uint64_t Address, const void *Decoder) {
3685   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3686                                 true, 2, Inst, Decoder))
3687     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3688   return MCDisassembler::Success;
3689 }
3690 
3691 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3692                                  uint64_t Address, const void *Decoder) {
3693   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3694                                 true, 4, Inst, Decoder))
3695     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3696   return MCDisassembler::Success;
3697 }
3698 
3699 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3700                                  uint64_t Address, const void *Decoder) {
3701   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3702                                 true, 2, Inst, Decoder))
3703     Inst.addOperand(MCOperand::createImm(Val << 1));
3704   return MCDisassembler::Success;
3705 }
3706 
3707 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3708                                  uint64_t Address, const void *Decoder) {
3709   DecodeStatus S = MCDisassembler::Success;
3710 
3711   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3712   unsigned Rm = fieldFromInstruction(Val, 3, 3);
3713 
3714   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3715     return MCDisassembler::Fail;
3716   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3717     return MCDisassembler::Fail;
3718 
3719   return S;
3720 }
3721 
3722 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3723                                   uint64_t Address, const void *Decoder) {
3724   DecodeStatus S = MCDisassembler::Success;
3725 
3726   unsigned Rn = fieldFromInstruction(Val, 0, 3);
3727   unsigned imm = fieldFromInstruction(Val, 3, 5);
3728 
3729   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3730     return MCDisassembler::Fail;
3731   Inst.addOperand(MCOperand::createImm(imm));
3732 
3733   return S;
3734 }
3735 
3736 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3737                                   uint64_t Address, const void *Decoder) {
3738   unsigned imm = Val << 2;
3739 
3740   Inst.addOperand(MCOperand::createImm(imm));
3741   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3742 
3743   return MCDisassembler::Success;
3744 }
3745 
3746 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3747                                   uint64_t Address, const void *Decoder) {
3748   Inst.addOperand(MCOperand::createReg(ARM::SP));
3749   Inst.addOperand(MCOperand::createImm(Val));
3750 
3751   return MCDisassembler::Success;
3752 }
3753 
3754 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3755                                   uint64_t Address, const void *Decoder) {
3756   DecodeStatus S = MCDisassembler::Success;
3757 
3758   unsigned Rn = fieldFromInstruction(Val, 6, 4);
3759   unsigned Rm = fieldFromInstruction(Val, 2, 4);
3760   unsigned imm = fieldFromInstruction(Val, 0, 2);
3761 
3762   // Thumb stores cannot use PC as dest register.
3763   switch (Inst.getOpcode()) {
3764   case ARM::t2STRHs:
3765   case ARM::t2STRBs:
3766   case ARM::t2STRs:
3767     if (Rn == 15)
3768       return MCDisassembler::Fail;
3769     break;
3770   default:
3771     break;
3772   }
3773 
3774   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3775     return MCDisassembler::Fail;
3776   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3777     return MCDisassembler::Fail;
3778   Inst.addOperand(MCOperand::createImm(imm));
3779 
3780   return S;
3781 }
3782 
3783 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3784                               uint64_t Address, const void *Decoder) {
3785   DecodeStatus S = MCDisassembler::Success;
3786 
3787   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3788   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3789 
3790   const FeatureBitset &featureBits =
3791     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3792 
3793   bool hasMP = featureBits[ARM::FeatureMP];
3794   bool hasV7Ops = featureBits[ARM::HasV7Ops];
3795 
3796   if (Rn == 15) {
3797     switch (Inst.getOpcode()) {
3798     case ARM::t2LDRBs:
3799       Inst.setOpcode(ARM::t2LDRBpci);
3800       break;
3801     case ARM::t2LDRHs:
3802       Inst.setOpcode(ARM::t2LDRHpci);
3803       break;
3804     case ARM::t2LDRSHs:
3805       Inst.setOpcode(ARM::t2LDRSHpci);
3806       break;
3807     case ARM::t2LDRSBs:
3808       Inst.setOpcode(ARM::t2LDRSBpci);
3809       break;
3810     case ARM::t2LDRs:
3811       Inst.setOpcode(ARM::t2LDRpci);
3812       break;
3813     case ARM::t2PLDs:
3814       Inst.setOpcode(ARM::t2PLDpci);
3815       break;
3816     case ARM::t2PLIs:
3817       Inst.setOpcode(ARM::t2PLIpci);
3818       break;
3819     default:
3820       return MCDisassembler::Fail;
3821     }
3822 
3823     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3824   }
3825 
3826   if (Rt == 15) {
3827     switch (Inst.getOpcode()) {
3828     case ARM::t2LDRSHs:
3829       return MCDisassembler::Fail;
3830     case ARM::t2LDRHs:
3831       Inst.setOpcode(ARM::t2PLDWs);
3832       break;
3833     case ARM::t2LDRSBs:
3834       Inst.setOpcode(ARM::t2PLIs);
3835       break;
3836     default:
3837       break;
3838     }
3839   }
3840 
3841   switch (Inst.getOpcode()) {
3842     case ARM::t2PLDs:
3843       break;
3844     case ARM::t2PLIs:
3845       if (!hasV7Ops)
3846         return MCDisassembler::Fail;
3847       break;
3848     case ARM::t2PLDWs:
3849       if (!hasV7Ops || !hasMP)
3850         return MCDisassembler::Fail;
3851       break;
3852     default:
3853       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3854         return MCDisassembler::Fail;
3855   }
3856 
3857   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3858   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3859   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3860   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3861     return MCDisassembler::Fail;
3862 
3863   return S;
3864 }
3865 
3866 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3867                                 uint64_t Address, const void* Decoder) {
3868   DecodeStatus S = MCDisassembler::Success;
3869 
3870   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3871   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3872   unsigned U = fieldFromInstruction(Insn, 9, 1);
3873   unsigned imm = fieldFromInstruction(Insn, 0, 8);
3874   imm |= (U << 8);
3875   imm |= (Rn << 9);
3876   unsigned add = fieldFromInstruction(Insn, 9, 1);
3877 
3878   const FeatureBitset &featureBits =
3879     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3880 
3881   bool hasMP = featureBits[ARM::FeatureMP];
3882   bool hasV7Ops = featureBits[ARM::HasV7Ops];
3883 
3884   if (Rn == 15) {
3885     switch (Inst.getOpcode()) {
3886     case ARM::t2LDRi8:
3887       Inst.setOpcode(ARM::t2LDRpci);
3888       break;
3889     case ARM::t2LDRBi8:
3890       Inst.setOpcode(ARM::t2LDRBpci);
3891       break;
3892     case ARM::t2LDRSBi8:
3893       Inst.setOpcode(ARM::t2LDRSBpci);
3894       break;
3895     case ARM::t2LDRHi8:
3896       Inst.setOpcode(ARM::t2LDRHpci);
3897       break;
3898     case ARM::t2LDRSHi8:
3899       Inst.setOpcode(ARM::t2LDRSHpci);
3900       break;
3901     case ARM::t2PLDi8:
3902       Inst.setOpcode(ARM::t2PLDpci);
3903       break;
3904     case ARM::t2PLIi8:
3905       Inst.setOpcode(ARM::t2PLIpci);
3906       break;
3907     default:
3908       return MCDisassembler::Fail;
3909     }
3910     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3911   }
3912 
3913   if (Rt == 15) {
3914     switch (Inst.getOpcode()) {
3915     case ARM::t2LDRSHi8:
3916       return MCDisassembler::Fail;
3917     case ARM::t2LDRHi8:
3918       if (!add)
3919         Inst.setOpcode(ARM::t2PLDWi8);
3920       break;
3921     case ARM::t2LDRSBi8:
3922       Inst.setOpcode(ARM::t2PLIi8);
3923       break;
3924     default:
3925       break;
3926     }
3927   }
3928 
3929   switch (Inst.getOpcode()) {
3930   case ARM::t2PLDi8:
3931     break;
3932   case ARM::t2PLIi8:
3933     if (!hasV7Ops)
3934       return MCDisassembler::Fail;
3935     break;
3936   case ARM::t2PLDWi8:
3937       if (!hasV7Ops || !hasMP)
3938         return MCDisassembler::Fail;
3939       break;
3940   default:
3941     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3942       return MCDisassembler::Fail;
3943   }
3944 
3945   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3946     return MCDisassembler::Fail;
3947   return S;
3948 }
3949 
3950 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3951                                 uint64_t Address, const void* Decoder) {
3952   DecodeStatus S = MCDisassembler::Success;
3953 
3954   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3955   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3956   unsigned imm = fieldFromInstruction(Insn, 0, 12);
3957   imm |= (Rn << 13);
3958 
3959   const FeatureBitset &featureBits =
3960     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3961 
3962   bool hasMP = featureBits[ARM::FeatureMP];
3963   bool hasV7Ops = featureBits[ARM::HasV7Ops];
3964 
3965   if (Rn == 15) {
3966     switch (Inst.getOpcode()) {
3967     case ARM::t2LDRi12:
3968       Inst.setOpcode(ARM::t2LDRpci);
3969       break;
3970     case ARM::t2LDRHi12:
3971       Inst.setOpcode(ARM::t2LDRHpci);
3972       break;
3973     case ARM::t2LDRSHi12:
3974       Inst.setOpcode(ARM::t2LDRSHpci);
3975       break;
3976     case ARM::t2LDRBi12:
3977       Inst.setOpcode(ARM::t2LDRBpci);
3978       break;
3979     case ARM::t2LDRSBi12:
3980       Inst.setOpcode(ARM::t2LDRSBpci);
3981       break;
3982     case ARM::t2PLDi12:
3983       Inst.setOpcode(ARM::t2PLDpci);
3984       break;
3985     case ARM::t2PLIi12:
3986       Inst.setOpcode(ARM::t2PLIpci);
3987       break;
3988     default:
3989       return MCDisassembler::Fail;
3990     }
3991     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3992   }
3993 
3994   if (Rt == 15) {
3995     switch (Inst.getOpcode()) {
3996     case ARM::t2LDRSHi12:
3997       return MCDisassembler::Fail;
3998     case ARM::t2LDRHi12:
3999       Inst.setOpcode(ARM::t2PLDWi12);
4000       break;
4001     case ARM::t2LDRSBi12:
4002       Inst.setOpcode(ARM::t2PLIi12);
4003       break;
4004     default:
4005       break;
4006     }
4007   }
4008 
4009   switch (Inst.getOpcode()) {
4010   case ARM::t2PLDi12:
4011     break;
4012   case ARM::t2PLIi12:
4013     if (!hasV7Ops)
4014       return MCDisassembler::Fail;
4015     break;
4016   case ARM::t2PLDWi12:
4017       if (!hasV7Ops || !hasMP)
4018         return MCDisassembler::Fail;
4019       break;
4020   default:
4021     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4022       return MCDisassembler::Fail;
4023   }
4024 
4025   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4026     return MCDisassembler::Fail;
4027   return S;
4028 }
4029 
4030 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
4031                                 uint64_t Address, const void* Decoder) {
4032   DecodeStatus S = MCDisassembler::Success;
4033 
4034   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4035   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4036   unsigned imm = fieldFromInstruction(Insn, 0, 8);
4037   imm |= (Rn << 9);
4038 
4039   if (Rn == 15) {
4040     switch (Inst.getOpcode()) {
4041     case ARM::t2LDRT:
4042       Inst.setOpcode(ARM::t2LDRpci);
4043       break;
4044     case ARM::t2LDRBT:
4045       Inst.setOpcode(ARM::t2LDRBpci);
4046       break;
4047     case ARM::t2LDRHT:
4048       Inst.setOpcode(ARM::t2LDRHpci);
4049       break;
4050     case ARM::t2LDRSBT:
4051       Inst.setOpcode(ARM::t2LDRSBpci);
4052       break;
4053     case ARM::t2LDRSHT:
4054       Inst.setOpcode(ARM::t2LDRSHpci);
4055       break;
4056     default:
4057       return MCDisassembler::Fail;
4058     }
4059     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4060   }
4061 
4062   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4063     return MCDisassembler::Fail;
4064   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4065     return MCDisassembler::Fail;
4066   return S;
4067 }
4068 
4069 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4070                                 uint64_t Address, const void* Decoder) {
4071   DecodeStatus S = MCDisassembler::Success;
4072 
4073   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4074   unsigned U = fieldFromInstruction(Insn, 23, 1);
4075   int imm = fieldFromInstruction(Insn, 0, 12);
4076 
4077   const FeatureBitset &featureBits =
4078     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4079 
4080   bool hasV7Ops = featureBits[ARM::HasV7Ops];
4081 
4082   if (Rt == 15) {
4083     switch (Inst.getOpcode()) {
4084       case ARM::t2LDRBpci:
4085       case ARM::t2LDRHpci:
4086         Inst.setOpcode(ARM::t2PLDpci);
4087         break;
4088       case ARM::t2LDRSBpci:
4089         Inst.setOpcode(ARM::t2PLIpci);
4090         break;
4091       case ARM::t2LDRSHpci:
4092         return MCDisassembler::Fail;
4093       default:
4094         break;
4095     }
4096   }
4097 
4098   switch(Inst.getOpcode()) {
4099   case ARM::t2PLDpci:
4100     break;
4101   case ARM::t2PLIpci:
4102     if (!hasV7Ops)
4103       return MCDisassembler::Fail;
4104     break;
4105   default:
4106     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4107       return MCDisassembler::Fail;
4108   }
4109 
4110   if (!U) {
4111     // Special case for #-0.
4112     if (imm == 0)
4113       imm = INT32_MIN;
4114     else
4115       imm = -imm;
4116   }
4117   Inst.addOperand(MCOperand::createImm(imm));
4118 
4119   return S;
4120 }
4121 
4122 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
4123                            uint64_t Address, const void *Decoder) {
4124   if (Val == 0)
4125     Inst.addOperand(MCOperand::createImm(INT32_MIN));
4126   else {
4127     int imm = Val & 0xFF;
4128 
4129     if (!(Val & 0x100)) imm *= -1;
4130     Inst.addOperand(MCOperand::createImm(imm * 4));
4131   }
4132 
4133   return MCDisassembler::Success;
4134 }
4135 
4136 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4137                                    const void *Decoder) {
4138   if (Val == 0)
4139     Inst.addOperand(MCOperand::createImm(INT32_MIN));
4140   else {
4141     int imm = Val & 0x7F;
4142 
4143     if (!(Val & 0x80))
4144       imm *= -1;
4145     Inst.addOperand(MCOperand::createImm(imm * 4));
4146   }
4147 
4148   return MCDisassembler::Success;
4149 }
4150 
4151 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4152                                    uint64_t Address, const void *Decoder) {
4153   DecodeStatus S = MCDisassembler::Success;
4154 
4155   unsigned Rn = fieldFromInstruction(Val, 9, 4);
4156   unsigned imm = fieldFromInstruction(Val, 0, 9);
4157 
4158   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4159     return MCDisassembler::Fail;
4160   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4161     return MCDisassembler::Fail;
4162 
4163   return S;
4164 }
4165 
4166 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4167                                            uint64_t Address,
4168                                            const void *Decoder) {
4169   DecodeStatus S = MCDisassembler::Success;
4170 
4171   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4172   unsigned imm = fieldFromInstruction(Val, 0, 8);
4173 
4174   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4175     return MCDisassembler::Fail;
4176   if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4177     return MCDisassembler::Fail;
4178 
4179   return S;
4180 }
4181 
4182 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
4183                                    uint64_t Address, const void *Decoder) {
4184   DecodeStatus S = MCDisassembler::Success;
4185 
4186   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4187   unsigned imm = fieldFromInstruction(Val, 0, 8);
4188 
4189   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4190     return MCDisassembler::Fail;
4191 
4192   Inst.addOperand(MCOperand::createImm(imm));
4193 
4194   return S;
4195 }
4196 
4197 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
4198                          uint64_t Address, const void *Decoder) {
4199   int imm = Val & 0xFF;
4200   if (Val == 0)
4201     imm = INT32_MIN;
4202   else if (!(Val & 0x100))
4203     imm *= -1;
4204   Inst.addOperand(MCOperand::createImm(imm));
4205 
4206   return MCDisassembler::Success;
4207 }
4208 
4209 template<int shift>
4210 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4211                          uint64_t Address, const void *Decoder) {
4212   int imm = Val & 0x7F;
4213   if (Val == 0)
4214     imm = INT32_MIN;
4215   else if (!(Val & 0x80))
4216     imm *= -1;
4217   if (imm != INT32_MIN)
4218     imm *= (1U << shift);
4219   Inst.addOperand(MCOperand::createImm(imm));
4220 
4221   return MCDisassembler::Success;
4222 }
4223 
4224 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4225                                  uint64_t Address, const void *Decoder) {
4226   DecodeStatus S = MCDisassembler::Success;
4227 
4228   unsigned Rn = fieldFromInstruction(Val, 9, 4);
4229   unsigned imm = fieldFromInstruction(Val, 0, 9);
4230 
4231   // Thumb stores cannot use PC as dest register.
4232   switch (Inst.getOpcode()) {
4233   case ARM::t2STRT:
4234   case ARM::t2STRBT:
4235   case ARM::t2STRHT:
4236   case ARM::t2STRi8:
4237   case ARM::t2STRHi8:
4238   case ARM::t2STRBi8:
4239     if (Rn == 15)
4240       return MCDisassembler::Fail;
4241     break;
4242   default:
4243     break;
4244   }
4245 
4246   // Some instructions always use an additive offset.
4247   switch (Inst.getOpcode()) {
4248     case ARM::t2LDRT:
4249     case ARM::t2LDRBT:
4250     case ARM::t2LDRHT:
4251     case ARM::t2LDRSBT:
4252     case ARM::t2LDRSHT:
4253     case ARM::t2STRT:
4254     case ARM::t2STRBT:
4255     case ARM::t2STRHT:
4256       imm |= 0x100;
4257       break;
4258     default:
4259       break;
4260   }
4261 
4262   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4263     return MCDisassembler::Fail;
4264   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4265     return MCDisassembler::Fail;
4266 
4267   return S;
4268 }
4269 
4270 template<int shift>
4271 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4272                                          uint64_t Address,
4273                                          const void *Decoder) {
4274   DecodeStatus S = MCDisassembler::Success;
4275 
4276   unsigned Rn = fieldFromInstruction(Val, 8, 3);
4277   unsigned imm = fieldFromInstruction(Val, 0, 8);
4278 
4279   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4280     return MCDisassembler::Fail;
4281   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4282     return MCDisassembler::Fail;
4283 
4284   return S;
4285 }
4286 
4287 template<int shift, int WriteBack>
4288 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4289                                          uint64_t Address,
4290                                          const void *Decoder) {
4291   DecodeStatus S = MCDisassembler::Success;
4292 
4293   unsigned Rn = fieldFromInstruction(Val, 8, 4);
4294   unsigned imm = fieldFromInstruction(Val, 0, 8);
4295   if (WriteBack) {
4296     if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4297       return MCDisassembler::Fail;
4298   } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4299     return MCDisassembler::Fail;
4300   if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4301     return MCDisassembler::Fail;
4302 
4303   return S;
4304 }
4305 
4306 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4307                                     uint64_t Address, const void *Decoder) {
4308   DecodeStatus S = MCDisassembler::Success;
4309 
4310   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4311   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4312   unsigned addr = fieldFromInstruction(Insn, 0, 8);
4313   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
4314   addr |= Rn << 9;
4315   unsigned load = fieldFromInstruction(Insn, 20, 1);
4316 
4317   if (Rn == 15) {
4318     switch (Inst.getOpcode()) {
4319     case ARM::t2LDR_PRE:
4320     case ARM::t2LDR_POST:
4321       Inst.setOpcode(ARM::t2LDRpci);
4322       break;
4323     case ARM::t2LDRB_PRE:
4324     case ARM::t2LDRB_POST:
4325       Inst.setOpcode(ARM::t2LDRBpci);
4326       break;
4327     case ARM::t2LDRH_PRE:
4328     case ARM::t2LDRH_POST:
4329       Inst.setOpcode(ARM::t2LDRHpci);
4330       break;
4331     case ARM::t2LDRSB_PRE:
4332     case ARM::t2LDRSB_POST:
4333       if (Rt == 15)
4334         Inst.setOpcode(ARM::t2PLIpci);
4335       else
4336         Inst.setOpcode(ARM::t2LDRSBpci);
4337       break;
4338     case ARM::t2LDRSH_PRE:
4339     case ARM::t2LDRSH_POST:
4340       Inst.setOpcode(ARM::t2LDRSHpci);
4341       break;
4342     default:
4343       return MCDisassembler::Fail;
4344     }
4345     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4346   }
4347 
4348   if (!load) {
4349     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4350       return MCDisassembler::Fail;
4351   }
4352 
4353   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4354     return MCDisassembler::Fail;
4355 
4356   if (load) {
4357     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4358       return MCDisassembler::Fail;
4359   }
4360 
4361   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4362     return MCDisassembler::Fail;
4363 
4364   return S;
4365 }
4366 
4367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4368                                   uint64_t Address, const void *Decoder) {
4369   DecodeStatus S = MCDisassembler::Success;
4370 
4371   unsigned Rn = fieldFromInstruction(Val, 13, 4);
4372   unsigned imm = fieldFromInstruction(Val, 0, 12);
4373 
4374   // Thumb stores cannot use PC as dest register.
4375   switch (Inst.getOpcode()) {
4376   case ARM::t2STRi12:
4377   case ARM::t2STRBi12:
4378   case ARM::t2STRHi12:
4379     if (Rn == 15)
4380       return MCDisassembler::Fail;
4381     break;
4382   default:
4383     break;
4384   }
4385 
4386   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4387     return MCDisassembler::Fail;
4388   Inst.addOperand(MCOperand::createImm(imm));
4389 
4390   return S;
4391 }
4392 
4393 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4394                                 uint64_t Address, const void *Decoder) {
4395   unsigned imm = fieldFromInstruction(Insn, 0, 7);
4396 
4397   Inst.addOperand(MCOperand::createReg(ARM::SP));
4398   Inst.addOperand(MCOperand::createReg(ARM::SP));
4399   Inst.addOperand(MCOperand::createImm(imm));
4400 
4401   return MCDisassembler::Success;
4402 }
4403 
4404 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4405                                 uint64_t Address, const void *Decoder) {
4406   DecodeStatus S = MCDisassembler::Success;
4407 
4408   if (Inst.getOpcode() == ARM::tADDrSP) {
4409     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
4410     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
4411 
4412     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4413     return MCDisassembler::Fail;
4414     Inst.addOperand(MCOperand::createReg(ARM::SP));
4415     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4416     return MCDisassembler::Fail;
4417   } else if (Inst.getOpcode() == ARM::tADDspr) {
4418     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
4419 
4420     Inst.addOperand(MCOperand::createReg(ARM::SP));
4421     Inst.addOperand(MCOperand::createReg(ARM::SP));
4422     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4423     return MCDisassembler::Fail;
4424   }
4425 
4426   return S;
4427 }
4428 
4429 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4430                            uint64_t Address, const void *Decoder) {
4431   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
4432   unsigned flags = fieldFromInstruction(Insn, 0, 3);
4433 
4434   Inst.addOperand(MCOperand::createImm(imod));
4435   Inst.addOperand(MCOperand::createImm(flags));
4436 
4437   return MCDisassembler::Success;
4438 }
4439 
4440 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4441                              uint64_t Address, const void *Decoder) {
4442   DecodeStatus S = MCDisassembler::Success;
4443   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4444   unsigned add = fieldFromInstruction(Insn, 4, 1);
4445 
4446   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4447     return MCDisassembler::Fail;
4448   Inst.addOperand(MCOperand::createImm(add));
4449 
4450   return S;
4451 }
4452 
4453 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4454                              uint64_t Address, const void *Decoder) {
4455   DecodeStatus S = MCDisassembler::Success;
4456   unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4457   unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4458 
4459   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4460     return MCDisassembler::Fail;
4461   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4462     return MCDisassembler::Fail;
4463 
4464   return S;
4465 }
4466 
4467 template<int shift>
4468 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4469                              uint64_t Address, const void *Decoder) {
4470   DecodeStatus S = MCDisassembler::Success;
4471   unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4472   int imm = fieldFromInstruction(Insn, 0, 7);
4473 
4474   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4475     return MCDisassembler::Fail;
4476 
4477   if(!fieldFromInstruction(Insn, 7, 1)) {
4478     if (imm == 0)
4479       imm = INT32_MIN;                 // indicate -0
4480     else
4481       imm *= -1;
4482   }
4483   if (imm != INT32_MIN)
4484     imm *= (1U << shift);
4485   Inst.addOperand(MCOperand::createImm(imm));
4486 
4487   return S;
4488 }
4489 
4490 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4491                                  uint64_t Address, const void *Decoder) {
4492   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
4493   // Note only one trailing zero not two.  Also the J1 and J2 values are from
4494   // the encoded instruction.  So here change to I1 and I2 values via:
4495   // I1 = NOT(J1 EOR S);
4496   // I2 = NOT(J2 EOR S);
4497   // and build the imm32 with two trailing zeros as documented:
4498   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
4499   unsigned S = (Val >> 23) & 1;
4500   unsigned J1 = (Val >> 22) & 1;
4501   unsigned J2 = (Val >> 21) & 1;
4502   unsigned I1 = !(J1 ^ S);
4503   unsigned I2 = !(J2 ^ S);
4504   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4505   int imm32 = SignExtend32<25>(tmp << 1);
4506 
4507   if (!tryAddingSymbolicOperand(Address,
4508                                 (Address & ~2u) + imm32 + 4,
4509                                 true, 4, Inst, Decoder))
4510     Inst.addOperand(MCOperand::createImm(imm32));
4511   return MCDisassembler::Success;
4512 }
4513 
4514 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4515                               uint64_t Address, const void *Decoder) {
4516   if (Val == 0xA || Val == 0xB)
4517     return MCDisassembler::Fail;
4518 
4519   const FeatureBitset &featureBits =
4520     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4521 
4522   if (!isValidCoprocessorNumber(Val, featureBits))
4523     return MCDisassembler::Fail;
4524 
4525   Inst.addOperand(MCOperand::createImm(Val));
4526   return MCDisassembler::Success;
4527 }
4528 
4529 static DecodeStatus
4530 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4531                        uint64_t Address, const void *Decoder) {
4532   DecodeStatus S = MCDisassembler::Success;
4533 
4534   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4535   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4536 
4537   if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
4538   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4539     return MCDisassembler::Fail;
4540   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4541     return MCDisassembler::Fail;
4542   return S;
4543 }
4544 
4545 static DecodeStatus
4546 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4547                            uint64_t Address, const void *Decoder) {
4548   DecodeStatus S = MCDisassembler::Success;
4549 
4550   unsigned pred = fieldFromInstruction(Insn, 22, 4);
4551   if (pred == 0xE || pred == 0xF) {
4552     unsigned opc = fieldFromInstruction(Insn, 4, 28);
4553     switch (opc) {
4554       default:
4555         return MCDisassembler::Fail;
4556       case 0xf3bf8f4:
4557         Inst.setOpcode(ARM::t2DSB);
4558         break;
4559       case 0xf3bf8f5:
4560         Inst.setOpcode(ARM::t2DMB);
4561         break;
4562       case 0xf3bf8f6:
4563         Inst.setOpcode(ARM::t2ISB);
4564         break;
4565     }
4566 
4567     unsigned imm = fieldFromInstruction(Insn, 0, 4);
4568     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4569   }
4570 
4571   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4572   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4573   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4574   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4575   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4576 
4577   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4578     return MCDisassembler::Fail;
4579   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4580     return MCDisassembler::Fail;
4581 
4582   return S;
4583 }
4584 
4585 // Decode a shifted immediate operand.  These basically consist
4586 // of an 8-bit value, and a 4-bit directive that specifies either
4587 // a splat operation or a rotation.
4588 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4589                           uint64_t Address, const void *Decoder) {
4590   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4591   if (ctrl == 0) {
4592     unsigned byte = fieldFromInstruction(Val, 8, 2);
4593     unsigned imm = fieldFromInstruction(Val, 0, 8);
4594     switch (byte) {
4595       case 0:
4596         Inst.addOperand(MCOperand::createImm(imm));
4597         break;
4598       case 1:
4599         Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4600         break;
4601       case 2:
4602         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4603         break;
4604       case 3:
4605         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4606                                              (imm << 8)  |  imm));
4607         break;
4608     }
4609   } else {
4610     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4611     unsigned rot = fieldFromInstruction(Val, 7, 5);
4612     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4613     Inst.addOperand(MCOperand::createImm(imm));
4614   }
4615 
4616   return MCDisassembler::Success;
4617 }
4618 
4619 static DecodeStatus
4620 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4621                             uint64_t Address, const void *Decoder) {
4622   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4623                                 true, 2, Inst, Decoder))
4624     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4625   return MCDisassembler::Success;
4626 }
4627 
4628 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4629                                                uint64_t Address,
4630                                                const void *Decoder) {
4631   // Val is passed in as S:J1:J2:imm10:imm11
4632   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
4633   // the encoded instruction.  So here change to I1 and I2 values via:
4634   // I1 = NOT(J1 EOR S);
4635   // I2 = NOT(J2 EOR S);
4636   // and build the imm32 with one trailing zero as documented:
4637   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4638   unsigned S = (Val >> 23) & 1;
4639   unsigned J1 = (Val >> 22) & 1;
4640   unsigned J2 = (Val >> 21) & 1;
4641   unsigned I1 = !(J1 ^ S);
4642   unsigned I2 = !(J2 ^ S);
4643   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4644   int imm32 = SignExtend32<25>(tmp << 1);
4645 
4646   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4647                                 true, 4, Inst, Decoder))
4648     Inst.addOperand(MCOperand::createImm(imm32));
4649   return MCDisassembler::Success;
4650 }
4651 
4652 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4653                                    uint64_t Address, const void *Decoder) {
4654   if (Val & ~0xf)
4655     return MCDisassembler::Fail;
4656 
4657   Inst.addOperand(MCOperand::createImm(Val));
4658   return MCDisassembler::Success;
4659 }
4660 
4661 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4662                                         uint64_t Address, const void *Decoder) {
4663   if (Val & ~0xf)
4664     return MCDisassembler::Fail;
4665 
4666   Inst.addOperand(MCOperand::createImm(Val));
4667   return MCDisassembler::Success;
4668 }
4669 
4670 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4671                           uint64_t Address, const void *Decoder) {
4672   DecodeStatus S = MCDisassembler::Success;
4673   const FeatureBitset &FeatureBits =
4674     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4675 
4676   if (FeatureBits[ARM::FeatureMClass]) {
4677     unsigned ValLow = Val & 0xff;
4678 
4679     // Validate the SYSm value first.
4680     switch (ValLow) {
4681     case  0: // apsr
4682     case  1: // iapsr
4683     case  2: // eapsr
4684     case  3: // xpsr
4685     case  5: // ipsr
4686     case  6: // epsr
4687     case  7: // iepsr
4688     case  8: // msp
4689     case  9: // psp
4690     case 16: // primask
4691     case 20: // control
4692       break;
4693     case 17: // basepri
4694     case 18: // basepri_max
4695     case 19: // faultmask
4696       if (!(FeatureBits[ARM::HasV7Ops]))
4697         // Values basepri, basepri_max and faultmask are only valid for v7m.
4698         return MCDisassembler::Fail;
4699       break;
4700     case 0x8a: // msplim_ns
4701     case 0x8b: // psplim_ns
4702     case 0x91: // basepri_ns
4703     case 0x93: // faultmask_ns
4704       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4705         return MCDisassembler::Fail;
4706       LLVM_FALLTHROUGH;
4707     case 10:   // msplim
4708     case 11:   // psplim
4709     case 0x88: // msp_ns
4710     case 0x89: // psp_ns
4711     case 0x90: // primask_ns
4712     case 0x94: // control_ns
4713     case 0x98: // sp_ns
4714       if (!(FeatureBits[ARM::Feature8MSecExt]))
4715         return MCDisassembler::Fail;
4716       break;
4717     default:
4718       // Architecturally defined as unpredictable
4719       S = MCDisassembler::SoftFail;
4720       break;
4721     }
4722 
4723     if (Inst.getOpcode() == ARM::t2MSR_M) {
4724       unsigned Mask = fieldFromInstruction(Val, 10, 2);
4725       if (!(FeatureBits[ARM::HasV7Ops])) {
4726         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4727         // unpredictable.
4728         if (Mask != 2)
4729           S = MCDisassembler::SoftFail;
4730       }
4731       else {
4732         // The ARMv7-M architecture stores an additional 2-bit mask value in
4733         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4734         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4735         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4736         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4737         // only if the processor includes the DSP extension.
4738         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4739             (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4740           S = MCDisassembler::SoftFail;
4741       }
4742     }
4743   } else {
4744     // A/R class
4745     if (Val == 0)
4746       return MCDisassembler::Fail;
4747   }
4748   Inst.addOperand(MCOperand::createImm(Val));
4749   return S;
4750 }
4751 
4752 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4753                                     uint64_t Address, const void *Decoder) {
4754   unsigned R = fieldFromInstruction(Val, 5, 1);
4755   unsigned SysM = fieldFromInstruction(Val, 0, 5);
4756 
4757   // The table of encodings for these banked registers comes from B9.2.3 of the
4758   // ARM ARM. There are patterns, but nothing regular enough to make this logic
4759   // neater. So by fiat, these values are UNPREDICTABLE:
4760   if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
4761     return MCDisassembler::Fail;
4762 
4763   Inst.addOperand(MCOperand::createImm(Val));
4764   return MCDisassembler::Success;
4765 }
4766 
4767 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4768                                         uint64_t Address, const void *Decoder) {
4769   DecodeStatus S = MCDisassembler::Success;
4770 
4771   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4772   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4773   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4774 
4775   if (Rn == 0xF)
4776     S = MCDisassembler::SoftFail;
4777 
4778   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4779     return MCDisassembler::Fail;
4780   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4781     return MCDisassembler::Fail;
4782   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4783     return MCDisassembler::Fail;
4784 
4785   return S;
4786 }
4787 
4788 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4789                                          uint64_t Address,
4790                                          const void *Decoder) {
4791   DecodeStatus S = MCDisassembler::Success;
4792 
4793   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4794   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4795   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4796   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4797 
4798   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4799     return MCDisassembler::Fail;
4800 
4801   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4802     S = MCDisassembler::SoftFail;
4803 
4804   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4805     return MCDisassembler::Fail;
4806   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4807     return MCDisassembler::Fail;
4808   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4809     return MCDisassembler::Fail;
4810 
4811   return S;
4812 }
4813 
4814 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4815                             uint64_t Address, const void *Decoder) {
4816   DecodeStatus S = MCDisassembler::Success;
4817 
4818   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4819   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4820   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4821   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4822   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4823   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4824 
4825   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4826 
4827   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4828     return MCDisassembler::Fail;
4829   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4830     return MCDisassembler::Fail;
4831   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4832     return MCDisassembler::Fail;
4833   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4834     return MCDisassembler::Fail;
4835 
4836   return S;
4837 }
4838 
4839 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4840                             uint64_t Address, const void *Decoder) {
4841   DecodeStatus S = MCDisassembler::Success;
4842 
4843   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4844   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4845   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4846   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4847   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4848   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4849   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4850 
4851   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4852   if (Rm == 0xF) S = MCDisassembler::SoftFail;
4853 
4854   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4855     return MCDisassembler::Fail;
4856   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4857     return MCDisassembler::Fail;
4858   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4859     return MCDisassembler::Fail;
4860   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4861     return MCDisassembler::Fail;
4862 
4863   return S;
4864 }
4865 
4866 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4867                             uint64_t Address, const void *Decoder) {
4868   DecodeStatus S = MCDisassembler::Success;
4869 
4870   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4871   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4872   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4873   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4874   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4875   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4876 
4877   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4878 
4879   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4880     return MCDisassembler::Fail;
4881   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4882     return MCDisassembler::Fail;
4883   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4884     return MCDisassembler::Fail;
4885   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4886     return MCDisassembler::Fail;
4887 
4888   return S;
4889 }
4890 
4891 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4892                             uint64_t Address, const void *Decoder) {
4893   DecodeStatus S = MCDisassembler::Success;
4894 
4895   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4896   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4897   unsigned imm = fieldFromInstruction(Insn, 0, 12);
4898   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4899   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4900   unsigned pred = fieldFromInstruction(Insn, 28, 4);
4901 
4902   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4903 
4904   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4905     return MCDisassembler::Fail;
4906   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4907     return MCDisassembler::Fail;
4908   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4909     return MCDisassembler::Fail;
4910   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4911     return MCDisassembler::Fail;
4912 
4913   return S;
4914 }
4915 
4916 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4917                          uint64_t Address, const void *Decoder) {
4918   DecodeStatus S = MCDisassembler::Success;
4919 
4920   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4921   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4922   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4923   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4924   unsigned size = fieldFromInstruction(Insn, 10, 2);
4925 
4926   unsigned align = 0;
4927   unsigned index = 0;
4928   switch (size) {
4929     default:
4930       return MCDisassembler::Fail;
4931     case 0:
4932       if (fieldFromInstruction(Insn, 4, 1))
4933         return MCDisassembler::Fail; // UNDEFINED
4934       index = fieldFromInstruction(Insn, 5, 3);
4935       break;
4936     case 1:
4937       if (fieldFromInstruction(Insn, 5, 1))
4938         return MCDisassembler::Fail; // UNDEFINED
4939       index = fieldFromInstruction(Insn, 6, 2);
4940       if (fieldFromInstruction(Insn, 4, 1))
4941         align = 2;
4942       break;
4943     case 2:
4944       if (fieldFromInstruction(Insn, 6, 1))
4945         return MCDisassembler::Fail; // UNDEFINED
4946       index = fieldFromInstruction(Insn, 7, 1);
4947 
4948       switch (fieldFromInstruction(Insn, 4, 2)) {
4949         case 0 :
4950           align = 0; break;
4951         case 3:
4952           align = 4; break;
4953         default:
4954           return MCDisassembler::Fail;
4955       }
4956       break;
4957   }
4958 
4959   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4960     return MCDisassembler::Fail;
4961   if (Rm != 0xF) { // Writeback
4962     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4963       return MCDisassembler::Fail;
4964   }
4965   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4966     return MCDisassembler::Fail;
4967   Inst.addOperand(MCOperand::createImm(align));
4968   if (Rm != 0xF) {
4969     if (Rm != 0xD) {
4970       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4971         return MCDisassembler::Fail;
4972     } else
4973       Inst.addOperand(MCOperand::createReg(0));
4974   }
4975 
4976   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4977     return MCDisassembler::Fail;
4978   Inst.addOperand(MCOperand::createImm(index));
4979 
4980   return S;
4981 }
4982 
4983 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4984                          uint64_t Address, const void *Decoder) {
4985   DecodeStatus S = MCDisassembler::Success;
4986 
4987   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4988   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4989   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4990   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4991   unsigned size = fieldFromInstruction(Insn, 10, 2);
4992 
4993   unsigned align = 0;
4994   unsigned index = 0;
4995   switch (size) {
4996     default:
4997       return MCDisassembler::Fail;
4998     case 0:
4999       if (fieldFromInstruction(Insn, 4, 1))
5000         return MCDisassembler::Fail; // UNDEFINED
5001       index = fieldFromInstruction(Insn, 5, 3);
5002       break;
5003     case 1:
5004       if (fieldFromInstruction(Insn, 5, 1))
5005         return MCDisassembler::Fail; // UNDEFINED
5006       index = fieldFromInstruction(Insn, 6, 2);
5007       if (fieldFromInstruction(Insn, 4, 1))
5008         align = 2;
5009       break;
5010     case 2:
5011       if (fieldFromInstruction(Insn, 6, 1))
5012         return MCDisassembler::Fail; // UNDEFINED
5013       index = fieldFromInstruction(Insn, 7, 1);
5014 
5015       switch (fieldFromInstruction(Insn, 4, 2)) {
5016         case 0:
5017           align = 0; break;
5018         case 3:
5019           align = 4; break;
5020         default:
5021           return MCDisassembler::Fail;
5022       }
5023       break;
5024   }
5025 
5026   if (Rm != 0xF) { // Writeback
5027     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5028     return MCDisassembler::Fail;
5029   }
5030   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5031     return MCDisassembler::Fail;
5032   Inst.addOperand(MCOperand::createImm(align));
5033   if (Rm != 0xF) {
5034     if (Rm != 0xD) {
5035       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5036     return MCDisassembler::Fail;
5037     } else
5038       Inst.addOperand(MCOperand::createReg(0));
5039   }
5040 
5041   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5042     return MCDisassembler::Fail;
5043   Inst.addOperand(MCOperand::createImm(index));
5044 
5045   return S;
5046 }
5047 
5048 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
5049                          uint64_t Address, const void *Decoder) {
5050   DecodeStatus S = MCDisassembler::Success;
5051 
5052   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5053   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5054   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5055   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5056   unsigned size = fieldFromInstruction(Insn, 10, 2);
5057 
5058   unsigned align = 0;
5059   unsigned index = 0;
5060   unsigned inc = 1;
5061   switch (size) {
5062     default:
5063       return MCDisassembler::Fail;
5064     case 0:
5065       index = fieldFromInstruction(Insn, 5, 3);
5066       if (fieldFromInstruction(Insn, 4, 1))
5067         align = 2;
5068       break;
5069     case 1:
5070       index = fieldFromInstruction(Insn, 6, 2);
5071       if (fieldFromInstruction(Insn, 4, 1))
5072         align = 4;
5073       if (fieldFromInstruction(Insn, 5, 1))
5074         inc = 2;
5075       break;
5076     case 2:
5077       if (fieldFromInstruction(Insn, 5, 1))
5078         return MCDisassembler::Fail; // UNDEFINED
5079       index = fieldFromInstruction(Insn, 7, 1);
5080       if (fieldFromInstruction(Insn, 4, 1) != 0)
5081         align = 8;
5082       if (fieldFromInstruction(Insn, 6, 1))
5083         inc = 2;
5084       break;
5085   }
5086 
5087   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5088     return MCDisassembler::Fail;
5089   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5090     return MCDisassembler::Fail;
5091   if (Rm != 0xF) { // Writeback
5092     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5093       return MCDisassembler::Fail;
5094   }
5095   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5096     return MCDisassembler::Fail;
5097   Inst.addOperand(MCOperand::createImm(align));
5098   if (Rm != 0xF) {
5099     if (Rm != 0xD) {
5100       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5101         return MCDisassembler::Fail;
5102     } else
5103       Inst.addOperand(MCOperand::createReg(0));
5104   }
5105 
5106   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5107     return MCDisassembler::Fail;
5108   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5109     return MCDisassembler::Fail;
5110   Inst.addOperand(MCOperand::createImm(index));
5111 
5112   return S;
5113 }
5114 
5115 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
5116                          uint64_t Address, const void *Decoder) {
5117   DecodeStatus S = MCDisassembler::Success;
5118 
5119   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5120   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5121   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5122   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5123   unsigned size = fieldFromInstruction(Insn, 10, 2);
5124 
5125   unsigned align = 0;
5126   unsigned index = 0;
5127   unsigned inc = 1;
5128   switch (size) {
5129     default:
5130       return MCDisassembler::Fail;
5131     case 0:
5132       index = fieldFromInstruction(Insn, 5, 3);
5133       if (fieldFromInstruction(Insn, 4, 1))
5134         align = 2;
5135       break;
5136     case 1:
5137       index = fieldFromInstruction(Insn, 6, 2);
5138       if (fieldFromInstruction(Insn, 4, 1))
5139         align = 4;
5140       if (fieldFromInstruction(Insn, 5, 1))
5141         inc = 2;
5142       break;
5143     case 2:
5144       if (fieldFromInstruction(Insn, 5, 1))
5145         return MCDisassembler::Fail; // UNDEFINED
5146       index = fieldFromInstruction(Insn, 7, 1);
5147       if (fieldFromInstruction(Insn, 4, 1) != 0)
5148         align = 8;
5149       if (fieldFromInstruction(Insn, 6, 1))
5150         inc = 2;
5151       break;
5152   }
5153 
5154   if (Rm != 0xF) { // Writeback
5155     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5156       return MCDisassembler::Fail;
5157   }
5158   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5159     return MCDisassembler::Fail;
5160   Inst.addOperand(MCOperand::createImm(align));
5161   if (Rm != 0xF) {
5162     if (Rm != 0xD) {
5163       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5164         return MCDisassembler::Fail;
5165     } else
5166       Inst.addOperand(MCOperand::createReg(0));
5167   }
5168 
5169   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5170     return MCDisassembler::Fail;
5171   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5172     return MCDisassembler::Fail;
5173   Inst.addOperand(MCOperand::createImm(index));
5174 
5175   return S;
5176 }
5177 
5178 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
5179                          uint64_t Address, const void *Decoder) {
5180   DecodeStatus S = MCDisassembler::Success;
5181 
5182   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5183   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5184   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5185   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5186   unsigned size = fieldFromInstruction(Insn, 10, 2);
5187 
5188   unsigned align = 0;
5189   unsigned index = 0;
5190   unsigned inc = 1;
5191   switch (size) {
5192     default:
5193       return MCDisassembler::Fail;
5194     case 0:
5195       if (fieldFromInstruction(Insn, 4, 1))
5196         return MCDisassembler::Fail; // UNDEFINED
5197       index = fieldFromInstruction(Insn, 5, 3);
5198       break;
5199     case 1:
5200       if (fieldFromInstruction(Insn, 4, 1))
5201         return MCDisassembler::Fail; // UNDEFINED
5202       index = fieldFromInstruction(Insn, 6, 2);
5203       if (fieldFromInstruction(Insn, 5, 1))
5204         inc = 2;
5205       break;
5206     case 2:
5207       if (fieldFromInstruction(Insn, 4, 2))
5208         return MCDisassembler::Fail; // UNDEFINED
5209       index = fieldFromInstruction(Insn, 7, 1);
5210       if (fieldFromInstruction(Insn, 6, 1))
5211         inc = 2;
5212       break;
5213   }
5214 
5215   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5216     return MCDisassembler::Fail;
5217   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5218     return MCDisassembler::Fail;
5219   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5220     return MCDisassembler::Fail;
5221 
5222   if (Rm != 0xF) { // Writeback
5223     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5224     return MCDisassembler::Fail;
5225   }
5226   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5227     return MCDisassembler::Fail;
5228   Inst.addOperand(MCOperand::createImm(align));
5229   if (Rm != 0xF) {
5230     if (Rm != 0xD) {
5231       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5232     return MCDisassembler::Fail;
5233     } else
5234       Inst.addOperand(MCOperand::createReg(0));
5235   }
5236 
5237   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5238     return MCDisassembler::Fail;
5239   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5240     return MCDisassembler::Fail;
5241   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5242     return MCDisassembler::Fail;
5243   Inst.addOperand(MCOperand::createImm(index));
5244 
5245   return S;
5246 }
5247 
5248 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
5249                          uint64_t Address, const void *Decoder) {
5250   DecodeStatus S = MCDisassembler::Success;
5251 
5252   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5253   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5254   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5255   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5256   unsigned size = fieldFromInstruction(Insn, 10, 2);
5257 
5258   unsigned align = 0;
5259   unsigned index = 0;
5260   unsigned inc = 1;
5261   switch (size) {
5262     default:
5263       return MCDisassembler::Fail;
5264     case 0:
5265       if (fieldFromInstruction(Insn, 4, 1))
5266         return MCDisassembler::Fail; // UNDEFINED
5267       index = fieldFromInstruction(Insn, 5, 3);
5268       break;
5269     case 1:
5270       if (fieldFromInstruction(Insn, 4, 1))
5271         return MCDisassembler::Fail; // UNDEFINED
5272       index = fieldFromInstruction(Insn, 6, 2);
5273       if (fieldFromInstruction(Insn, 5, 1))
5274         inc = 2;
5275       break;
5276     case 2:
5277       if (fieldFromInstruction(Insn, 4, 2))
5278         return MCDisassembler::Fail; // UNDEFINED
5279       index = fieldFromInstruction(Insn, 7, 1);
5280       if (fieldFromInstruction(Insn, 6, 1))
5281         inc = 2;
5282       break;
5283   }
5284 
5285   if (Rm != 0xF) { // Writeback
5286     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5287     return MCDisassembler::Fail;
5288   }
5289   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5290     return MCDisassembler::Fail;
5291   Inst.addOperand(MCOperand::createImm(align));
5292   if (Rm != 0xF) {
5293     if (Rm != 0xD) {
5294       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5295     return MCDisassembler::Fail;
5296     } else
5297       Inst.addOperand(MCOperand::createReg(0));
5298   }
5299 
5300   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5301     return MCDisassembler::Fail;
5302   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5303     return MCDisassembler::Fail;
5304   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5305     return MCDisassembler::Fail;
5306   Inst.addOperand(MCOperand::createImm(index));
5307 
5308   return S;
5309 }
5310 
5311 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
5312                          uint64_t Address, const void *Decoder) {
5313   DecodeStatus S = MCDisassembler::Success;
5314 
5315   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5316   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5317   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5318   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5319   unsigned size = fieldFromInstruction(Insn, 10, 2);
5320 
5321   unsigned align = 0;
5322   unsigned index = 0;
5323   unsigned inc = 1;
5324   switch (size) {
5325     default:
5326       return MCDisassembler::Fail;
5327     case 0:
5328       if (fieldFromInstruction(Insn, 4, 1))
5329         align = 4;
5330       index = fieldFromInstruction(Insn, 5, 3);
5331       break;
5332     case 1:
5333       if (fieldFromInstruction(Insn, 4, 1))
5334         align = 8;
5335       index = fieldFromInstruction(Insn, 6, 2);
5336       if (fieldFromInstruction(Insn, 5, 1))
5337         inc = 2;
5338       break;
5339     case 2:
5340       switch (fieldFromInstruction(Insn, 4, 2)) {
5341         case 0:
5342           align = 0; break;
5343         case 3:
5344           return MCDisassembler::Fail;
5345         default:
5346           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5347       }
5348 
5349       index = fieldFromInstruction(Insn, 7, 1);
5350       if (fieldFromInstruction(Insn, 6, 1))
5351         inc = 2;
5352       break;
5353   }
5354 
5355   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5356     return MCDisassembler::Fail;
5357   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5358     return MCDisassembler::Fail;
5359   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5360     return MCDisassembler::Fail;
5361   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5362     return MCDisassembler::Fail;
5363 
5364   if (Rm != 0xF) { // Writeback
5365     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5366       return MCDisassembler::Fail;
5367   }
5368   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5369     return MCDisassembler::Fail;
5370   Inst.addOperand(MCOperand::createImm(align));
5371   if (Rm != 0xF) {
5372     if (Rm != 0xD) {
5373       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5374         return MCDisassembler::Fail;
5375     } else
5376       Inst.addOperand(MCOperand::createReg(0));
5377   }
5378 
5379   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5380     return MCDisassembler::Fail;
5381   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5382     return MCDisassembler::Fail;
5383   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5384     return MCDisassembler::Fail;
5385   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5386     return MCDisassembler::Fail;
5387   Inst.addOperand(MCOperand::createImm(index));
5388 
5389   return S;
5390 }
5391 
5392 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
5393                          uint64_t Address, const void *Decoder) {
5394   DecodeStatus S = MCDisassembler::Success;
5395 
5396   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5397   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
5398   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
5399   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
5400   unsigned size = fieldFromInstruction(Insn, 10, 2);
5401 
5402   unsigned align = 0;
5403   unsigned index = 0;
5404   unsigned inc = 1;
5405   switch (size) {
5406     default:
5407       return MCDisassembler::Fail;
5408     case 0:
5409       if (fieldFromInstruction(Insn, 4, 1))
5410         align = 4;
5411       index = fieldFromInstruction(Insn, 5, 3);
5412       break;
5413     case 1:
5414       if (fieldFromInstruction(Insn, 4, 1))
5415         align = 8;
5416       index = fieldFromInstruction(Insn, 6, 2);
5417       if (fieldFromInstruction(Insn, 5, 1))
5418         inc = 2;
5419       break;
5420     case 2:
5421       switch (fieldFromInstruction(Insn, 4, 2)) {
5422         case 0:
5423           align = 0; break;
5424         case 3:
5425           return MCDisassembler::Fail;
5426         default:
5427           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
5428       }
5429 
5430       index = fieldFromInstruction(Insn, 7, 1);
5431       if (fieldFromInstruction(Insn, 6, 1))
5432         inc = 2;
5433       break;
5434   }
5435 
5436   if (Rm != 0xF) { // Writeback
5437     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5438     return MCDisassembler::Fail;
5439   }
5440   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5441     return MCDisassembler::Fail;
5442   Inst.addOperand(MCOperand::createImm(align));
5443   if (Rm != 0xF) {
5444     if (Rm != 0xD) {
5445       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5446     return MCDisassembler::Fail;
5447     } else
5448       Inst.addOperand(MCOperand::createReg(0));
5449   }
5450 
5451   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5452     return MCDisassembler::Fail;
5453   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5454     return MCDisassembler::Fail;
5455   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5456     return MCDisassembler::Fail;
5457   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5458     return MCDisassembler::Fail;
5459   Inst.addOperand(MCOperand::createImm(index));
5460 
5461   return S;
5462 }
5463 
5464 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
5465                                   uint64_t Address, const void *Decoder) {
5466   DecodeStatus S = MCDisassembler::Success;
5467   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
5468   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5469   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
5470   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5471   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5472 
5473   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5474     S = MCDisassembler::SoftFail;
5475 
5476   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
5477     return MCDisassembler::Fail;
5478   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5479     return MCDisassembler::Fail;
5480   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
5481     return MCDisassembler::Fail;
5482   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5483     return MCDisassembler::Fail;
5484   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5485     return MCDisassembler::Fail;
5486 
5487   return S;
5488 }
5489 
5490 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
5491                                   uint64_t Address, const void *Decoder) {
5492   DecodeStatus S = MCDisassembler::Success;
5493   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
5494   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
5495   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
5496   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5497   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
5498 
5499   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5500     S = MCDisassembler::SoftFail;
5501 
5502   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
5503     return MCDisassembler::Fail;
5504   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5505     return MCDisassembler::Fail;
5506   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
5507     return MCDisassembler::Fail;
5508   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5509     return MCDisassembler::Fail;
5510   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5511     return MCDisassembler::Fail;
5512 
5513   return S;
5514 }
5515 
5516 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
5517                              uint64_t Address, const void *Decoder) {
5518   DecodeStatus S = MCDisassembler::Success;
5519   unsigned pred = fieldFromInstruction(Insn, 4, 4);
5520   unsigned mask = fieldFromInstruction(Insn, 0, 4);
5521 
5522   if (pred == 0xF) {
5523     pred = 0xE;
5524     S = MCDisassembler::SoftFail;
5525   }
5526 
5527   if (mask == 0x0)
5528     return MCDisassembler::Fail;
5529 
5530   // IT masks are encoded as a sequence of replacement low-order bits
5531   // for the condition code. So if the low bit of the starting
5532   // condition code is 1, then we have to flip all the bits above the
5533   // terminating bit (which is the lowest 1 bit).
5534   if (pred & 1) {
5535     unsigned LowBit = mask & -mask;
5536     unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
5537     mask ^= BitsAboveLowBit;
5538   }
5539 
5540   Inst.addOperand(MCOperand::createImm(pred));
5541   Inst.addOperand(MCOperand::createImm(mask));
5542   return S;
5543 }
5544 
5545 static DecodeStatus
5546 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5547                            uint64_t Address, const void *Decoder) {
5548   DecodeStatus S = MCDisassembler::Success;
5549 
5550   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5551   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5552   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5553   unsigned addr = fieldFromInstruction(Insn, 0, 8);
5554   unsigned W = fieldFromInstruction(Insn, 21, 1);
5555   unsigned U = fieldFromInstruction(Insn, 23, 1);
5556   unsigned P = fieldFromInstruction(Insn, 24, 1);
5557   bool writeback = (W == 1) | (P == 0);
5558 
5559   addr |= (U << 8) | (Rn << 9);
5560 
5561   if (writeback && (Rn == Rt || Rn == Rt2))
5562     Check(S, MCDisassembler::SoftFail);
5563   if (Rt == Rt2)
5564     Check(S, MCDisassembler::SoftFail);
5565 
5566   // Rt
5567   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5568     return MCDisassembler::Fail;
5569   // Rt2
5570   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5571     return MCDisassembler::Fail;
5572   // Writeback operand
5573   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5574     return MCDisassembler::Fail;
5575   // addr
5576   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5577     return MCDisassembler::Fail;
5578 
5579   return S;
5580 }
5581 
5582 static DecodeStatus
5583 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5584                            uint64_t Address, const void *Decoder) {
5585   DecodeStatus S = MCDisassembler::Success;
5586 
5587   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5588   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5589   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5590   unsigned addr = fieldFromInstruction(Insn, 0, 8);
5591   unsigned W = fieldFromInstruction(Insn, 21, 1);
5592   unsigned U = fieldFromInstruction(Insn, 23, 1);
5593   unsigned P = fieldFromInstruction(Insn, 24, 1);
5594   bool writeback = (W == 1) | (P == 0);
5595 
5596   addr |= (U << 8) | (Rn << 9);
5597 
5598   if (writeback && (Rn == Rt || Rn == Rt2))
5599     Check(S, MCDisassembler::SoftFail);
5600 
5601   // Writeback operand
5602   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5603     return MCDisassembler::Fail;
5604   // Rt
5605   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5606     return MCDisassembler::Fail;
5607   // Rt2
5608   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5609     return MCDisassembler::Fail;
5610   // addr
5611   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5612     return MCDisassembler::Fail;
5613 
5614   return S;
5615 }
5616 
5617 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5618                                 uint64_t Address, const void *Decoder) {
5619   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5620   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5621   if (sign1 != sign2) return MCDisassembler::Fail;
5622   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
5623   assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5624   DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
5625 
5626   unsigned Val = fieldFromInstruction(Insn, 0, 8);
5627   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5628   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5629   // If sign, then it is decreasing the address.
5630   if (sign1) {
5631     // Following ARMv7 Architecture Manual, when the offset
5632     // is zero, it is decoded as a subw, not as a adr.w
5633     if (!Val) {
5634       Inst.setOpcode(ARM::t2SUBri12);
5635       Inst.addOperand(MCOperand::createReg(ARM::PC));
5636     } else
5637       Val = -Val;
5638   }
5639   Inst.addOperand(MCOperand::createImm(Val));
5640   return S;
5641 }
5642 
5643 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5644                                               uint64_t Address,
5645                                               const void *Decoder) {
5646   DecodeStatus S = MCDisassembler::Success;
5647 
5648   // Shift of "asr #32" is not allowed in Thumb2 mode.
5649   if (Val == 0x20) S = MCDisassembler::Fail;
5650   Inst.addOperand(MCOperand::createImm(Val));
5651   return S;
5652 }
5653 
5654 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5655                                uint64_t Address, const void *Decoder) {
5656   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
5657   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
5658   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
5659   unsigned pred = fieldFromInstruction(Insn, 28, 4);
5660 
5661   if (pred == 0xF)
5662     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5663 
5664   DecodeStatus S = MCDisassembler::Success;
5665 
5666   if (Rt == Rn || Rn == Rt2)
5667     S = MCDisassembler::SoftFail;
5668 
5669   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5670     return MCDisassembler::Fail;
5671   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5672     return MCDisassembler::Fail;
5673   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5674     return MCDisassembler::Fail;
5675   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5676     return MCDisassembler::Fail;
5677 
5678   return S;
5679 }
5680 
5681 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5682                                 uint64_t Address, const void *Decoder) {
5683   const FeatureBitset &featureBits =
5684       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5685   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5686 
5687   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5688   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5689   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5690   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5691   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5692   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5693   unsigned op = fieldFromInstruction(Insn, 5, 1);
5694 
5695   DecodeStatus S = MCDisassembler::Success;
5696 
5697   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5698   if (!(imm & 0x38)) {
5699     if (cmode == 0xF) {
5700       if (op == 1) return MCDisassembler::Fail;
5701       Inst.setOpcode(ARM::VMOVv2f32);
5702     }
5703     if (hasFullFP16) {
5704       if (cmode == 0xE) {
5705         if (op == 1) {
5706           Inst.setOpcode(ARM::VMOVv1i64);
5707         } else {
5708           Inst.setOpcode(ARM::VMOVv8i8);
5709         }
5710       }
5711       if (cmode == 0xD) {
5712         if (op == 1) {
5713           Inst.setOpcode(ARM::VMVNv2i32);
5714         } else {
5715           Inst.setOpcode(ARM::VMOVv2i32);
5716         }
5717       }
5718       if (cmode == 0xC) {
5719         if (op == 1) {
5720           Inst.setOpcode(ARM::VMVNv2i32);
5721         } else {
5722           Inst.setOpcode(ARM::VMOVv2i32);
5723         }
5724       }
5725     }
5726     return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5727   }
5728 
5729   if (!(imm & 0x20)) return MCDisassembler::Fail;
5730 
5731   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5732     return MCDisassembler::Fail;
5733   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5734     return MCDisassembler::Fail;
5735   Inst.addOperand(MCOperand::createImm(64 - imm));
5736 
5737   return S;
5738 }
5739 
5740 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5741                                 uint64_t Address, const void *Decoder) {
5742   const FeatureBitset &featureBits =
5743       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5744   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5745 
5746   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5747   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5748   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5749   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5750   unsigned imm = fieldFromInstruction(Insn, 16, 6);
5751   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5752   unsigned op = fieldFromInstruction(Insn, 5, 1);
5753 
5754   DecodeStatus S = MCDisassembler::Success;
5755 
5756   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5757   if (!(imm & 0x38)) {
5758     if (cmode == 0xF) {
5759       if (op == 1) return MCDisassembler::Fail;
5760       Inst.setOpcode(ARM::VMOVv4f32);
5761     }
5762     if (hasFullFP16) {
5763       if (cmode == 0xE) {
5764         if (op == 1) {
5765           Inst.setOpcode(ARM::VMOVv2i64);
5766         } else {
5767           Inst.setOpcode(ARM::VMOVv16i8);
5768         }
5769       }
5770       if (cmode == 0xD) {
5771         if (op == 1) {
5772           Inst.setOpcode(ARM::VMVNv4i32);
5773         } else {
5774           Inst.setOpcode(ARM::VMOVv4i32);
5775         }
5776       }
5777       if (cmode == 0xC) {
5778         if (op == 1) {
5779           Inst.setOpcode(ARM::VMVNv4i32);
5780         } else {
5781           Inst.setOpcode(ARM::VMOVv4i32);
5782         }
5783       }
5784     }
5785     return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
5786   }
5787 
5788   if (!(imm & 0x20)) return MCDisassembler::Fail;
5789 
5790   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5791     return MCDisassembler::Fail;
5792   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5793     return MCDisassembler::Fail;
5794   Inst.addOperand(MCOperand::createImm(64 - imm));
5795 
5796   return S;
5797 }
5798 
5799 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
5800                                                        unsigned Insn,
5801                                                        uint64_t Address,
5802                                                        const void *Decoder) {
5803   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5804   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5805   unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
5806   Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
5807   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5808   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5809   unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
5810   unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
5811 
5812   DecodeStatus S = MCDisassembler::Success;
5813 
5814   auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
5815 
5816   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5817     return MCDisassembler::Fail;
5818   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
5819     return MCDisassembler::Fail;
5820   if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
5821     return MCDisassembler::Fail;
5822   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5823     return MCDisassembler::Fail;
5824   // The lane index does not have any bits in the encoding, because it can only
5825   // be 0.
5826   Inst.addOperand(MCOperand::createImm(0));
5827   Inst.addOperand(MCOperand::createImm(rotate));
5828 
5829   return S;
5830 }
5831 
5832 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5833                                 uint64_t Address, const void *Decoder) {
5834   DecodeStatus S = MCDisassembler::Success;
5835 
5836   unsigned Rn = fieldFromInstruction(Val, 16, 4);
5837   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5838   unsigned Rm = fieldFromInstruction(Val, 0, 4);
5839   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5840   unsigned Cond = fieldFromInstruction(Val, 28, 4);
5841 
5842   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5843     S = MCDisassembler::SoftFail;
5844 
5845   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5846     return MCDisassembler::Fail;
5847   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5848     return MCDisassembler::Fail;
5849   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5850     return MCDisassembler::Fail;
5851   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5852     return MCDisassembler::Fail;
5853   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5854     return MCDisassembler::Fail;
5855 
5856   return S;
5857 }
5858 
5859 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
5860                                             uint64_t Address, const void *Decoder) {
5861   DecodeStatus S = MCDisassembler::Success;
5862 
5863   unsigned CRm = fieldFromInstruction(Val, 0, 4);
5864   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5865   unsigned cop = fieldFromInstruction(Val, 8, 4);
5866   unsigned Rt = fieldFromInstruction(Val, 12, 4);
5867   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5868 
5869   if ((cop & ~0x1) == 0xa)
5870     return MCDisassembler::Fail;
5871 
5872   if (Rt == Rt2)
5873     S = MCDisassembler::SoftFail;
5874 
5875   // We have to check if the instruction is MRRC2
5876   // or MCRR2 when constructing the operands for
5877   // Inst. Reason is because MRRC2 stores to two
5878   // registers so it's tablegen desc has has two
5879   // outputs whereas MCRR doesn't store to any
5880   // registers so all of it's operands are listed
5881   // as inputs, therefore the operand order for
5882   // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
5883   // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
5884 
5885   if (Inst.getOpcode() == ARM::MRRC2) {
5886     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5887       return MCDisassembler::Fail;
5888     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5889       return MCDisassembler::Fail;
5890   }
5891   Inst.addOperand(MCOperand::createImm(cop));
5892   Inst.addOperand(MCOperand::createImm(opc1));
5893   if (Inst.getOpcode() == ARM::MCRR2) {
5894     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5895       return MCDisassembler::Fail;
5896     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5897       return MCDisassembler::Fail;
5898   }
5899   Inst.addOperand(MCOperand::createImm(CRm));
5900 
5901   return S;
5902 }
5903 
5904 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
5905                                          uint64_t Address,
5906                                          const void *Decoder) {
5907   const FeatureBitset &featureBits =
5908       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5909   DecodeStatus S = MCDisassembler::Success;
5910 
5911   // Add explicit operand for the destination sysreg, for cases where
5912   // we have to model it for code generation purposes.
5913   switch (Inst.getOpcode()) {
5914   case ARM::VMSR_FPSCR_NZCVQC:
5915     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5916     break;
5917   case ARM::VMSR_P0:
5918     Inst.addOperand(MCOperand::createReg(ARM::VPR));
5919     break;
5920   }
5921 
5922   if (Inst.getOpcode() != ARM::FMSTAT) {
5923     unsigned Rt = fieldFromInstruction(Val, 12, 4);
5924 
5925     if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
5926       if (Rt == 13 || Rt == 15)
5927         S = MCDisassembler::SoftFail;
5928       Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
5929     } else
5930       Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
5931   }
5932 
5933   // Add explicit operand for the source sysreg, similarly to above.
5934   switch (Inst.getOpcode()) {
5935   case ARM::VMRS_FPSCR_NZCVQC:
5936     Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
5937     break;
5938   case ARM::VMRS_P0:
5939     Inst.addOperand(MCOperand::createReg(ARM::VPR));
5940     break;
5941   }
5942 
5943   if (featureBits[ARM::ModeThumb]) {
5944     Inst.addOperand(MCOperand::createImm(ARMCC::AL));
5945     Inst.addOperand(MCOperand::createReg(0));
5946   } else {
5947     unsigned pred = fieldFromInstruction(Val, 28, 4);
5948     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5949       return MCDisassembler::Fail;
5950   }
5951 
5952   return S;
5953 }
5954 
5955 template <bool isSigned, bool isNeg, bool zeroPermitted, int size>
5956 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
5957                                          uint64_t Address,
5958                                          const void *Decoder) {
5959   DecodeStatus S = MCDisassembler::Success;
5960   if (Val == 0 && !zeroPermitted)
5961     S = MCDisassembler::Fail;
5962 
5963   uint64_t DecVal;
5964   if (isSigned)
5965     DecVal = SignExtend32<size + 1>(Val << 1);
5966   else
5967     DecVal = (Val << 1);
5968 
5969   if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
5970                                 Decoder))
5971     Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
5972   return S;
5973 }
5974 
5975 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
5976                                                uint64_t Address,
5977                                                const void *Decoder) {
5978 
5979   uint64_t LocImm = Inst.getOperand(0).getImm();
5980   Val = LocImm + (2 << Val);
5981   if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
5982                                 Decoder))
5983     Inst.addOperand(MCOperand::createImm(Val));
5984   return MCDisassembler::Success;
5985 }
5986 
5987 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
5988                                           uint64_t Address,
5989                                           const void *Decoder) {
5990   if (Val >= ARMCC::AL)  // also exclude the non-condition NV
5991     return MCDisassembler::Fail;
5992   Inst.addOperand(MCOperand::createImm(Val));
5993   return MCDisassembler::Success;
5994 }
5995 
5996 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
5997                                  const void *Decoder) {
5998   DecodeStatus S = MCDisassembler::Success;
5999 
6000   if (Inst.getOpcode() == ARM::MVE_LCTP)
6001     return S;
6002 
6003   unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
6004                  fieldFromInstruction(Insn, 1, 10) << 1;
6005   switch (Inst.getOpcode()) {
6006   case ARM::t2LEUpdate:
6007   case ARM::MVE_LETP:
6008     Inst.addOperand(MCOperand::createReg(ARM::LR));
6009     Inst.addOperand(MCOperand::createReg(ARM::LR));
6010     LLVM_FALLTHROUGH;
6011   case ARM::t2LE:
6012     if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>(
6013                    Inst, Imm, Address, Decoder)))
6014       return MCDisassembler::Fail;
6015     break;
6016   case ARM::t2WLS:
6017   case ARM::MVE_WLSTP_8:
6018   case ARM::MVE_WLSTP_16:
6019   case ARM::MVE_WLSTP_32:
6020   case ARM::MVE_WLSTP_64:
6021     Inst.addOperand(MCOperand::createReg(ARM::LR));
6022     if (!Check(S,
6023                DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
6024                                        Address, Decoder)) ||
6025         !Check(S, DecodeBFLabelOperand<false, false, true, 11>(
6026                    Inst, Imm, Address, Decoder)))
6027       return MCDisassembler::Fail;
6028     break;
6029   case ARM::t2DLS:
6030   case ARM::MVE_DLSTP_8:
6031   case ARM::MVE_DLSTP_16:
6032   case ARM::MVE_DLSTP_32:
6033   case ARM::MVE_DLSTP_64:
6034     unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6035     if (Rn == 0xF) {
6036       // Enforce all the rest of the instruction bits in LCTP, which
6037       // won't have been reliably checked based on LCTP's own tablegen
6038       // record, because we came to this decode by a roundabout route.
6039       uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
6040       if ((Insn & ~SBZMask) != CanonicalLCTP)
6041         return MCDisassembler::Fail;   // a mandatory bit is wrong: hard fail
6042       if (Insn != CanonicalLCTP)
6043         Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
6044 
6045       Inst.setOpcode(ARM::MVE_LCTP);
6046     } else {
6047       Inst.addOperand(MCOperand::createReg(ARM::LR));
6048       if (!Check(S, DecoderGPRRegisterClass(Inst,
6049                                             fieldFromInstruction(Insn, 16, 4),
6050                                             Address, Decoder)))
6051         return MCDisassembler::Fail;
6052     }
6053     break;
6054   }
6055   return S;
6056 }
6057 
6058 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6059                                            uint64_t Address,
6060                                            const void *Decoder) {
6061   DecodeStatus S = MCDisassembler::Success;
6062 
6063   if (Val == 0)
6064     Val = 32;
6065 
6066   Inst.addOperand(MCOperand::createImm(Val));
6067 
6068   return S;
6069 }
6070 
6071 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6072                                    uint64_t Address, const void *Decoder) {
6073   if ((RegNo) + 1 > 11)
6074     return MCDisassembler::Fail;
6075 
6076   unsigned Register = GPRDecoderTable[(RegNo) + 1];
6077   Inst.addOperand(MCOperand::createReg(Register));
6078   return MCDisassembler::Success;
6079 }
6080 
6081 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6082                                    uint64_t Address, const void *Decoder) {
6083   if ((RegNo) > 14)
6084     return MCDisassembler::Fail;
6085 
6086   unsigned Register = GPRDecoderTable[(RegNo)];
6087   Inst.addOperand(MCOperand::createReg(Register));
6088   return MCDisassembler::Success;
6089 }
6090 
6091 static DecodeStatus
6092 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6093                                         uint64_t Address, const void *Decoder) {
6094   if (RegNo == 15) {
6095     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6096     return MCDisassembler::Success;
6097   }
6098 
6099   unsigned Register = GPRDecoderTable[RegNo];
6100   Inst.addOperand(MCOperand::createReg(Register));
6101 
6102   if (RegNo == 13)
6103     return MCDisassembler::SoftFail;
6104 
6105   return MCDisassembler::Success;
6106 }
6107 
6108 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6109                                   const void *Decoder) {
6110   DecodeStatus S = MCDisassembler::Success;
6111 
6112   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6113   Inst.addOperand(MCOperand::createReg(0));
6114   if (Inst.getOpcode() == ARM::VSCCLRMD) {
6115     unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) |
6116                        (fieldFromInstruction(Insn, 12, 4) << 8) |
6117                        (fieldFromInstruction(Insn, 22, 1) << 12);
6118     if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
6119       return MCDisassembler::Fail;
6120     }
6121   } else {
6122     unsigned reglist = fieldFromInstruction(Insn, 0, 8) |
6123                        (fieldFromInstruction(Insn, 22, 1) << 8) |
6124                        (fieldFromInstruction(Insn, 12, 4) << 9);
6125     if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
6126       return MCDisassembler::Fail;
6127     }
6128   }
6129   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6130 
6131   return S;
6132 }
6133 
6134 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6135                               uint64_t Address,
6136                               const void *Decoder) {
6137   if (RegNo > 7)
6138     return MCDisassembler::Fail;
6139 
6140   unsigned Register = QPRDecoderTable[RegNo];
6141   Inst.addOperand(MCOperand::createReg(Register));
6142   return MCDisassembler::Success;
6143 }
6144 
6145 static const uint16_t QQPRDecoderTable[] = {
6146      ARM::Q0_Q1,  ARM::Q1_Q2,  ARM::Q2_Q3,  ARM::Q3_Q4,
6147      ARM::Q4_Q5,  ARM::Q5_Q6,  ARM::Q6_Q7
6148 };
6149 
6150 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6151                               uint64_t Address,
6152                               const void *Decoder) {
6153   if (RegNo > 6)
6154     return MCDisassembler::Fail;
6155 
6156   unsigned Register = QQPRDecoderTable[RegNo];
6157   Inst.addOperand(MCOperand::createReg(Register));
6158   return MCDisassembler::Success;
6159 }
6160 
6161 static const uint16_t QQQQPRDecoderTable[] = {
6162      ARM::Q0_Q1_Q2_Q3,  ARM::Q1_Q2_Q3_Q4,  ARM::Q2_Q3_Q4_Q5,
6163      ARM::Q3_Q4_Q5_Q6,  ARM::Q4_Q5_Q6_Q7
6164 };
6165 
6166 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6167                               uint64_t Address,
6168                               const void *Decoder) {
6169   if (RegNo > 4)
6170     return MCDisassembler::Fail;
6171 
6172   unsigned Register = QQQQPRDecoderTable[RegNo];
6173   Inst.addOperand(MCOperand::createReg(Register));
6174   return MCDisassembler::Success;
6175 }
6176 
6177 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6178                                          uint64_t Address,
6179                                          const void *Decoder) {
6180   DecodeStatus S = MCDisassembler::Success;
6181 
6182   // Parse VPT mask and encode it in the MCInst as an immediate with the same
6183   // format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1 and
6184   // 't' as 0 and finish with a 1.
6185   unsigned Imm = 0;
6186   // We always start with a 't'.
6187   unsigned CurBit = 0;
6188   for (int i = 3; i >= 0; --i) {
6189     // If the bit we are looking at is not the same as last one, invert the
6190     // CurBit, if it is the same leave it as is.
6191     CurBit ^= (Val >> i) & 1U;
6192 
6193     // Encode the CurBit at the right place in the immediate.
6194     Imm |= (CurBit << i);
6195 
6196     // If we are done, finish the encoding with a 1.
6197     if ((Val & ~(~0U << i)) == 0) {
6198       Imm |= 1U << i;
6199       break;
6200     }
6201   }
6202 
6203   Inst.addOperand(MCOperand::createImm(Imm));
6204 
6205   return S;
6206 }
6207 
6208 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6209                                         uint64_t Address, const void *Decoder) {
6210   // The vpred_r operand type includes an MQPR register field derived
6211   // from the encoding. But we don't actually want to add an operand
6212   // to the MCInst at this stage, because AddThumbPredicate will do it
6213   // later, and will infer the register number from the TIED_TO
6214   // constraint. So this is a deliberately empty decoder method that
6215   // will inhibit the auto-generated disassembly code from adding an
6216   // operand at all.
6217   return MCDisassembler::Success;
6218 }
6219 
6220 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst,
6221                                                       unsigned Val,
6222                                                       uint64_t Address,
6223                                                       const void *Decoder) {
6224   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6225   return MCDisassembler::Success;
6226 }
6227 
6228 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst,
6229                                                       unsigned Val,
6230                                                       uint64_t Address,
6231                                                       const void *Decoder) {
6232   unsigned Code;
6233   switch (Val & 0x3) {
6234   case 0:
6235     Code = ARMCC::GE;
6236     break;
6237   case 1:
6238     Code = ARMCC::LT;
6239     break;
6240   case 2:
6241     Code = ARMCC::GT;
6242     break;
6243   case 3:
6244     Code = ARMCC::LE;
6245     break;
6246   }
6247   Inst.addOperand(MCOperand::createImm(Code));
6248   return MCDisassembler::Success;
6249 }
6250 
6251 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst,
6252                                                       unsigned Val,
6253                                                       uint64_t Address,
6254                                                       const void *Decoder) {
6255   Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6256   return MCDisassembler::Success;
6257 }
6258 
6259 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val,
6260                                                      uint64_t Address,
6261                                                      const void *Decoder) {
6262   unsigned Code;
6263   switch (Val) {
6264   default:
6265     return MCDisassembler::Fail;
6266   case 0:
6267     Code = ARMCC::EQ;
6268     break;
6269   case 1:
6270     Code = ARMCC::NE;
6271     break;
6272   case 4:
6273     Code = ARMCC::GE;
6274     break;
6275   case 5:
6276     Code = ARMCC::LT;
6277     break;
6278   case 6:
6279     Code = ARMCC::GT;
6280     break;
6281   case 7:
6282     Code = ARMCC::LE;
6283     break;
6284   }
6285 
6286   Inst.addOperand(MCOperand::createImm(Code));
6287   return MCDisassembler::Success;
6288 }
6289 
6290 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6291                                          uint64_t Address, const void *Decoder) {
6292   DecodeStatus S = MCDisassembler::Success;
6293 
6294   unsigned DecodedVal = 64 - Val;
6295 
6296   switch (Inst.getOpcode()) {
6297   case ARM::MVE_VCVTf16s16_fix:
6298   case ARM::MVE_VCVTs16f16_fix:
6299   case ARM::MVE_VCVTf16u16_fix:
6300   case ARM::MVE_VCVTu16f16_fix:
6301     if (DecodedVal > 16)
6302       return MCDisassembler::Fail;
6303     break;
6304   case ARM::MVE_VCVTf32s32_fix:
6305   case ARM::MVE_VCVTs32f32_fix:
6306   case ARM::MVE_VCVTf32u32_fix:
6307   case ARM::MVE_VCVTu32f32_fix:
6308     if (DecodedVal > 32)
6309       return MCDisassembler::Fail;
6310     break;
6311   }
6312 
6313   Inst.addOperand(MCOperand::createImm(64 - Val));
6314 
6315   return S;
6316 }
6317 
6318 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
6319   switch (Opcode) {
6320   case ARM::VSTR_P0_off:
6321   case ARM::VSTR_P0_pre:
6322   case ARM::VSTR_P0_post:
6323   case ARM::VLDR_P0_off:
6324   case ARM::VLDR_P0_pre:
6325   case ARM::VLDR_P0_post:
6326     return ARM::P0;
6327   default:
6328     return 0;
6329   }
6330 }
6331 
6332 template<bool Writeback>
6333 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6334                                           uint64_t Address,
6335                                           const void *Decoder) {
6336   switch (Inst.getOpcode()) {
6337   case ARM::VSTR_FPSCR_pre:
6338   case ARM::VSTR_FPSCR_NZCVQC_pre:
6339   case ARM::VLDR_FPSCR_pre:
6340   case ARM::VLDR_FPSCR_NZCVQC_pre:
6341   case ARM::VSTR_FPSCR_off:
6342   case ARM::VSTR_FPSCR_NZCVQC_off:
6343   case ARM::VLDR_FPSCR_off:
6344   case ARM::VLDR_FPSCR_NZCVQC_off:
6345   case ARM::VSTR_FPSCR_post:
6346   case ARM::VSTR_FPSCR_NZCVQC_post:
6347   case ARM::VLDR_FPSCR_post:
6348   case ARM::VLDR_FPSCR_NZCVQC_post:
6349     const FeatureBitset &featureBits =
6350         ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
6351 
6352     if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2])
6353       return MCDisassembler::Fail;
6354   }
6355 
6356   DecodeStatus S = MCDisassembler::Success;
6357   if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6358     Inst.addOperand(MCOperand::createReg(Sysreg));
6359   unsigned Rn = fieldFromInstruction(Val, 16, 4);
6360   unsigned addr = fieldFromInstruction(Val, 0, 7) |
6361                   (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6362 
6363   if (Writeback) {
6364     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6365       return MCDisassembler::Fail;
6366   }
6367   if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
6368     return MCDisassembler::Fail;
6369 
6370   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6371   Inst.addOperand(MCOperand::createReg(0));
6372 
6373   return S;
6374 }
6375 
6376 static inline DecodeStatus DecodeMVE_MEM_pre(
6377   MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
6378   unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6379   DecodeStatus S = MCDisassembler::Success;
6380 
6381   unsigned Qd = fieldFromInstruction(Val, 13, 3);
6382   unsigned addr = fieldFromInstruction(Val, 0, 7) |
6383                   (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6384 
6385   if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6386     return MCDisassembler::Fail;
6387   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6388     return MCDisassembler::Fail;
6389   if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6390     return MCDisassembler::Fail;
6391 
6392   return S;
6393 }
6394 
6395 template <int shift>
6396 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6397                                         uint64_t Address, const void *Decoder) {
6398   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6399                            fieldFromInstruction(Val, 16, 3),
6400                            DecodetGPRRegisterClass,
6401                            DecodeTAddrModeImm7<shift>);
6402 }
6403 
6404 template <int shift>
6405 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6406                                         uint64_t Address, const void *Decoder) {
6407   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6408                            fieldFromInstruction(Val, 16, 4),
6409                            DecoderGPRRegisterClass,
6410                            DecodeT2AddrModeImm7<shift,1>);
6411 }
6412 
6413 template <int shift>
6414 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6415                                         uint64_t Address, const void *Decoder) {
6416   return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6417                            fieldFromInstruction(Val, 17, 3),
6418                            DecodeMQPRRegisterClass,
6419                            DecodeMveAddrModeQ<shift>);
6420 }
6421 
6422 template<unsigned MinLog, unsigned MaxLog>
6423 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6424                                           uint64_t Address,
6425                                           const void *Decoder) {
6426   DecodeStatus S = MCDisassembler::Success;
6427 
6428   if (Val < MinLog || Val > MaxLog)
6429     return MCDisassembler::Fail;
6430 
6431   Inst.addOperand(MCOperand::createImm(1LL << Val));
6432   return S;
6433 }
6434 
6435 template<unsigned start>
6436 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val,
6437                                                     uint64_t Address,
6438                                                     const void *Decoder) {
6439   DecodeStatus S = MCDisassembler::Success;
6440 
6441   Inst.addOperand(MCOperand::createImm(start + Val));
6442 
6443   return S;
6444 }
6445 
6446 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6447                                          uint64_t Address, const void *Decoder) {
6448   DecodeStatus S = MCDisassembler::Success;
6449   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6450   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6451   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6452                  fieldFromInstruction(Insn, 13, 3));
6453   unsigned index = fieldFromInstruction(Insn, 4, 1);
6454 
6455   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6456     return MCDisassembler::Fail;
6457   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6458     return MCDisassembler::Fail;
6459   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6460     return MCDisassembler::Fail;
6461   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6462     return MCDisassembler::Fail;
6463   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6464     return MCDisassembler::Fail;
6465 
6466   return S;
6467 }
6468 
6469 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6470                                          uint64_t Address, const void *Decoder) {
6471   DecodeStatus S = MCDisassembler::Success;
6472   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
6473   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
6474   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6475                  fieldFromInstruction(Insn, 13, 3));
6476   unsigned index = fieldFromInstruction(Insn, 4, 1);
6477 
6478   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6479     return MCDisassembler::Fail;
6480   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6481     return MCDisassembler::Fail;
6482   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6483     return MCDisassembler::Fail;
6484   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6485     return MCDisassembler::Fail;
6486   if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6487     return MCDisassembler::Fail;
6488   if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6489     return MCDisassembler::Fail;
6490 
6491   return S;
6492 }
6493 
6494 static DecodeStatus DecodeMVEOverlappingLongShift(
6495   MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) {
6496   DecodeStatus S = MCDisassembler::Success;
6497 
6498   unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1;
6499   unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1;
6500   unsigned Rm = fieldFromInstruction(Insn, 12, 4);
6501 
6502   if (RdaHi == 14) {
6503     // This value of RdaHi (really indicating pc, because RdaHi has to
6504     // be an odd-numbered register, so the low bit will be set by the
6505     // decode function below) indicates that we must decode as SQRSHR
6506     // or UQRSHL, which both have a single Rda register field with all
6507     // four bits.
6508     unsigned Rda = fieldFromInstruction(Insn, 16, 4);
6509 
6510     switch (Inst.getOpcode()) {
6511       case ARM::MVE_ASRLr:
6512       case ARM::MVE_SQRSHRL:
6513         Inst.setOpcode(ARM::MVE_SQRSHR);
6514         break;
6515       case ARM::MVE_LSLLr:
6516       case ARM::MVE_UQRSHLL:
6517         Inst.setOpcode(ARM::MVE_UQRSHL);
6518         break;
6519       default:
6520         llvm_unreachable("Unexpected starting opcode!");
6521     }
6522 
6523     // Rda as output parameter
6524     if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6525       return MCDisassembler::Fail;
6526 
6527     // Rda again as input parameter
6528     if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6529       return MCDisassembler::Fail;
6530 
6531     // Rm, the amount to shift by
6532     if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6533       return MCDisassembler::Fail;
6534 
6535     if (fieldFromInstruction (Insn, 6, 3) != 4)
6536       return MCDisassembler::SoftFail;
6537 
6538     if (Rda == Rm)
6539       return MCDisassembler::SoftFail;
6540 
6541     return S;
6542   }
6543 
6544   // Otherwise, we decode as whichever opcode our caller has already
6545   // put into Inst. Those all look the same:
6546 
6547   // RdaLo,RdaHi as output parameters
6548   if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6549     return MCDisassembler::Fail;
6550   if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6551     return MCDisassembler::Fail;
6552 
6553   // RdaLo,RdaHi again as input parameters
6554   if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6555     return MCDisassembler::Fail;
6556   if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6557     return MCDisassembler::Fail;
6558 
6559   // Rm, the amount to shift by
6560   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6561     return MCDisassembler::Fail;
6562 
6563   if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6564       Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6565     unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
6566     // Saturate, the bit position for saturation
6567     Inst.addOperand(MCOperand::createImm(Saturate));
6568   }
6569 
6570   return S;
6571 }
6572 
6573 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
6574                                       const void *Decoder) {
6575   DecodeStatus S = MCDisassembler::Success;
6576   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6577                  fieldFromInstruction(Insn, 13, 3));
6578   unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
6579                  fieldFromInstruction(Insn, 1, 3));
6580   unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
6581 
6582   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6583     return MCDisassembler::Fail;
6584   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6585     return MCDisassembler::Fail;
6586   if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6587     return MCDisassembler::Fail;
6588 
6589   return S;
6590 }
6591 
6592 template<bool scalar, OperandDecoder predicate_decoder>
6593 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6594                                   const void *Decoder) {
6595   DecodeStatus S = MCDisassembler::Success;
6596   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6597   unsigned Qn = fieldFromInstruction(Insn, 17, 3);
6598   if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6599     return MCDisassembler::Fail;
6600 
6601   unsigned fc;
6602 
6603   if (scalar) {
6604     fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6605          fieldFromInstruction(Insn, 7, 1) |
6606          fieldFromInstruction(Insn, 5, 1) << 1;
6607     unsigned Rm = fieldFromInstruction(Insn, 0, 4);
6608     if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6609       return MCDisassembler::Fail;
6610   } else {
6611     fc = fieldFromInstruction(Insn, 12, 1) << 2 |
6612          fieldFromInstruction(Insn, 7, 1) |
6613          fieldFromInstruction(Insn, 0, 1) << 1;
6614     unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 |
6615                   fieldFromInstruction(Insn, 1, 3);
6616     if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6617       return MCDisassembler::Fail;
6618   }
6619 
6620   if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
6621     return MCDisassembler::Fail;
6622 
6623   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
6624   Inst.addOperand(MCOperand::createReg(0));
6625   Inst.addOperand(MCOperand::createImm(0));
6626 
6627   return S;
6628 }
6629 
6630 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
6631                                   const void *Decoder) {
6632   DecodeStatus S = MCDisassembler::Success;
6633   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6634   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6635   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
6636     return MCDisassembler::Fail;
6637   return S;
6638 }
6639 
6640 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address,
6641                                    const void *Decoder) {
6642   DecodeStatus S = MCDisassembler::Success;
6643   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6644   Inst.addOperand(MCOperand::createReg(ARM::VPR));
6645   return S;
6646 }
6647 
6648 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
6649                                         uint64_t Address, const void *Decoder) {
6650   const unsigned Rd = fieldFromInstruction(Insn, 8, 4);
6651   const unsigned Rn = fieldFromInstruction(Insn, 16, 4);
6652   const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 |
6653                          fieldFromInstruction(Insn, 12, 3) << 8 |
6654                          fieldFromInstruction(Insn, 0, 8);
6655   const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1);
6656   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
6657   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
6658   unsigned S = fieldFromInstruction(Insn, 20, 1);
6659   if (sign1 != sign2)
6660     return MCDisassembler::Fail;
6661 
6662   // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
6663   DecodeStatus DS = MCDisassembler::Success;
6664   if ((!Check(DS,
6665               DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
6666       (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
6667     return MCDisassembler::Fail;
6668   if (TypeT3) {
6669     Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
6670     S = 0;
6671     Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
6672   } else {
6673     Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
6674     if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
6675       return MCDisassembler::Fail;
6676   }
6677   if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
6678     return MCDisassembler::Fail;
6679 
6680   Inst.addOperand(MCOperand::createReg(0)); // pred
6681 
6682   return DS;
6683 }
6684