1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &VStream, 141 raw_ostream &CStream) const override; 142 143 private: 144 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 145 ArrayRef<uint8_t> Bytes, uint64_t Address, 146 raw_ostream &VStream, 147 raw_ostream &CStream) const; 148 149 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 150 ArrayRef<uint8_t> Bytes, uint64_t Address, 151 raw_ostream &VStream, 152 raw_ostream &CStream) const; 153 154 mutable ITStatus ITBlock; 155 mutable VPTStatus VPTBlock; 156 157 DecodeStatus AddThumbPredicate(MCInst&) const; 158 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 159 }; 160 161 } // end anonymous namespace 162 163 static bool Check(DecodeStatus &Out, DecodeStatus In) { 164 switch (In) { 165 case MCDisassembler::Success: 166 // Out stays the same. 167 return true; 168 case MCDisassembler::SoftFail: 169 Out = In; 170 return true; 171 case MCDisassembler::Fail: 172 Out = In; 173 return false; 174 } 175 llvm_unreachable("Invalid DecodeStatus!"); 176 } 177 178 // Forward declare these because the autogenerated code will reference them. 179 // Definitions are further down. 180 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 181 uint64_t Address, const void *Decoder); 182 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, const void *Decoder); 184 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 185 uint64_t Address, const void *Decoder); 186 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 218 unsigned RegNo, 219 uint64_t Address, 220 const void *Decoder); 221 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 232 unsigned RegNo, uint64_t Address, 233 const void *Decoder); 234 235 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 246 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 249 uint64_t Address, const void *Decoder); 250 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 251 unsigned Insn, 252 uint64_t Address, 253 const void *Decoder); 254 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 255 uint64_t Address, const void *Decoder); 256 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 257 uint64_t Address, const void *Decoder); 258 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 259 uint64_t Address, const void *Decoder); 260 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 261 uint64_t Address, const void *Decoder); 262 263 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 264 unsigned Insn, 265 uint64_t Adddress, 266 const void *Decoder); 267 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 312 uint64_t Address, const void *Decoder); 313 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 314 uint64_t Address, const void *Decoder); 315 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void *Decoder); 337 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void *Decoder); 339 template<int shift> 340 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 345 uint64_t Address, const void *Decoder); 346 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 347 uint64_t Address, const void *Decoder); 348 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 349 uint64_t Address, const void *Decoder); 350 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 351 uint64_t Address, const void *Decoder); 352 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 353 uint64_t Address, const void *Decoder); 354 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 355 uint64_t Address, const void *Decoder); 356 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 357 uint64_t Address, const void *Decoder); 358 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 359 uint64_t Address, const void *Decoder); 360 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 361 uint64_t Address, const void *Decoder); 362 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 363 uint64_t Address, const void *Decoder); 364 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 365 uint64_t Address, const void *Decoder); 366 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 367 uint64_t Address, const void *Decoder); 368 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 369 uint64_t Address, const void *Decoder); 370 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 371 uint64_t Address, const void *Decoder); 372 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 373 uint64_t Address, const void *Decoder); 374 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 375 uint64_t Address, const void *Decoder); 376 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 377 uint64_t Address, const void *Decoder); 378 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 379 uint64_t Address, const void *Decoder); 380 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 381 uint64_t Address, const void *Decoder); 382 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 383 uint64_t Address, const void *Decoder); 384 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 385 uint64_t Address, const void *Decoder); 386 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 387 uint64_t Address, const void *Decoder); 388 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 391 uint64_t Address, const void *Decoder); 392 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 393 unsigned Val, 394 uint64_t Address, 395 const void *Decoder); 396 397 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 398 uint64_t Address, const void *Decoder); 399 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 400 uint64_t Address, const void *Decoder); 401 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 402 uint64_t Address, const void *Decoder); 403 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 404 uint64_t Address, const void *Decoder); 405 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 406 uint64_t Address, const void *Decoder); 407 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 408 uint64_t Address, const void *Decoder); 409 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 410 uint64_t Address, const void *Decoder); 411 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 412 uint64_t Address, const void *Decoder); 413 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 414 uint64_t Address, const void *Decoder); 415 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 416 uint64_t Address, const void *Decoder); 417 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 418 uint64_t Address, const void* Decoder); 419 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 420 uint64_t Address, const void* Decoder); 421 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 422 uint64_t Address, const void* Decoder); 423 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 424 uint64_t Address, const void* Decoder); 425 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 426 uint64_t Address, const void *Decoder); 427 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 428 uint64_t Address, const void *Decoder); 429 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 430 uint64_t Address, const void *Decoder); 431 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 432 uint64_t Address, 433 const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 437 uint64_t Address, const void *Decoder); 438 template<int shift> 439 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift> 444 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 template<int shift, int WriteBack> 447 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 448 uint64_t Address, const void *Decoder); 449 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 450 uint64_t Address, const void *Decoder); 451 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 452 uint64_t Address, const void *Decoder); 453 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 454 uint64_t Address, const void *Decoder); 455 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 456 uint64_t Address, const void *Decoder); 457 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 458 uint64_t Address, const void *Decoder); 459 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 460 uint64_t Address, const void *Decoder); 461 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 462 uint64_t Address, const void *Decoder); 463 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 464 uint64_t Address, const void *Decoder); 465 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 466 uint64_t Address, const void *Decoder); 467 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 468 uint64_t Address, const void *Decoder); 469 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 470 uint64_t Address, const void *Decoder); 471 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 472 uint64_t Address, const void *Decoder); 473 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 474 uint64_t Address, const void *Decoder); 475 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 476 uint64_t Address, const void *Decoder); 477 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 478 uint64_t Address, const void *Decoder); 479 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 480 uint64_t Address, const void *Decoder); 481 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 482 uint64_t Address, const void *Decoder); 483 484 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 489 uint64_t Address, const void *Decoder); 490 491 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 492 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 493 uint64_t Address, const void *Decoder); 494 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 495 uint64_t Address, 496 const void *Decoder); 497 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 498 uint64_t Address, 499 const void *Decoder); 500 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, const void *Decoder); 509 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 510 uint64_t Address, const void *Decoder); 511 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const void *Decoder); 514 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const void *Decoder); 517 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 518 uint64_t Address, 519 const void *Decoder); 520 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 521 unsigned Val, 522 uint64_t Address, 523 const void *Decoder); 524 template<bool Writeback> 525 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const void *Decoder); 528 template<int shift> 529 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 530 uint64_t Address, const void *Decoder); 531 template<int shift> 532 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 533 uint64_t Address, const void *Decoder); 534 template<int shift> 535 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 536 uint64_t Address, const void *Decoder); 537 template<unsigned MinLog, unsigned MaxLog> 538 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const void *Decoder); 541 template <int shift> 542 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 543 uint64_t Address, 544 const void *Decoder); 545 template<unsigned start> 546 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const void *Decoder); 549 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 550 uint64_t Address, 551 const void *Decoder); 552 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 553 uint64_t Address, 554 const void *Decoder); 555 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 556 uint64_t Address, const void *Decoder); 557 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 558 uint64_t Address, const void *Decoder); 559 template<bool scalar, OperandDecoder predicate_decoder> 560 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 561 uint64_t Address, const void *Decoder); 562 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 563 uint64_t Address, const void *Decoder); 564 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 565 uint64_t Address, const void *Decoder); 566 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const void *Decoder); 569 #include "ARMGenDisassemblerTables.inc" 570 571 static MCDisassembler *createARMDisassembler(const Target &T, 572 const MCSubtargetInfo &STI, 573 MCContext &Ctx) { 574 return new ARMDisassembler(STI, Ctx); 575 } 576 577 // Post-decoding checks 578 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 579 uint64_t Address, raw_ostream &OS, 580 raw_ostream &CS, 581 uint32_t Insn, 582 DecodeStatus Result) { 583 switch (MI.getOpcode()) { 584 case ARM::HVC: { 585 // HVC is undefined if condition = 0xf otherwise upredictable 586 // if condition != 0xe 587 uint32_t Cond = (Insn >> 28) & 0xF; 588 if (Cond == 0xF) 589 return MCDisassembler::Fail; 590 if (Cond != 0xE) 591 return MCDisassembler::SoftFail; 592 return Result; 593 } 594 case ARM::t2ADDri: 595 case ARM::t2ADDri12: 596 case ARM::t2ADDrr: 597 case ARM::t2ADDrs: 598 case ARM::t2SUBri: 599 case ARM::t2SUBri12: 600 case ARM::t2SUBrr: 601 case ARM::t2SUBrs: 602 if (MI.getOperand(0).getReg() == ARM::SP && 603 MI.getOperand(1).getReg() != ARM::SP) 604 return MCDisassembler::SoftFail; 605 return Result; 606 default: return Result; 607 } 608 } 609 610 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 611 ArrayRef<uint8_t> Bytes, 612 uint64_t Address, raw_ostream &OS, 613 raw_ostream &CS) const { 614 if (STI.getFeatureBits()[ARM::ModeThumb]) 615 return getThumbInstruction(MI, Size, Bytes, Address, OS, CS); 616 return getARMInstruction(MI, Size, Bytes, Address, OS, CS); 617 } 618 619 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 620 ArrayRef<uint8_t> Bytes, 621 uint64_t Address, 622 raw_ostream &OS, 623 raw_ostream &CS) const { 624 CommentStream = &CS; 625 626 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 627 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 628 "mode!"); 629 630 // We want to read exactly 4 bytes of data. 631 if (Bytes.size() < 4) { 632 Size = 0; 633 return MCDisassembler::Fail; 634 } 635 636 // Encoded as a small-endian 32-bit word in the stream. 637 uint32_t Insn = 638 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 639 640 // Calling the auto-generated decoder function. 641 DecodeStatus Result = 642 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 643 if (Result != MCDisassembler::Fail) { 644 Size = 4; 645 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 646 } 647 648 struct DecodeTable { 649 const uint8_t *P; 650 bool DecodePred; 651 }; 652 653 const DecodeTable Tables[] = { 654 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 655 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 656 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 657 {DecoderTablev8Crypto32, false}, 658 }; 659 660 for (auto Table : Tables) { 661 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 662 if (Result != MCDisassembler::Fail) { 663 Size = 4; 664 // Add a fake predicate operand, because we share these instruction 665 // definitions with Thumb2 where these instructions are predicable. 666 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 667 return MCDisassembler::Fail; 668 return Result; 669 } 670 } 671 672 Result = 673 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 674 if (Result != MCDisassembler::Fail) { 675 Size = 4; 676 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 677 } 678 679 Size = 4; 680 return MCDisassembler::Fail; 681 } 682 683 namespace llvm { 684 685 extern const MCInstrDesc ARMInsts[]; 686 687 } // end namespace llvm 688 689 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 690 /// immediate Value in the MCInst. The immediate Value has had any PC 691 /// adjustment made by the caller. If the instruction is a branch instruction 692 /// then isBranch is true, else false. If the getOpInfo() function was set as 693 /// part of the setupForSymbolicDisassembly() call then that function is called 694 /// to get any symbolic information at the Address for this instruction. If 695 /// that returns non-zero then the symbolic information it returns is used to 696 /// create an MCExpr and that is added as an operand to the MCInst. If 697 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 698 /// Value is done and if a symbol is found an MCExpr is created with that, else 699 /// an MCExpr with Value is created. This function returns true if it adds an 700 /// operand to the MCInst and false otherwise. 701 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 702 bool isBranch, uint64_t InstSize, 703 MCInst &MI, const void *Decoder) { 704 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 705 // FIXME: Does it make sense for value to be negative? 706 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 707 /* Offset */ 0, InstSize); 708 } 709 710 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 711 /// referenced by a load instruction with the base register that is the Pc. 712 /// These can often be values in a literal pool near the Address of the 713 /// instruction. The Address of the instruction and its immediate Value are 714 /// used as a possible literal pool entry. The SymbolLookUp call back will 715 /// return the name of a symbol referenced by the literal pool's entry if 716 /// the referenced address is that of a symbol. Or it will return a pointer to 717 /// a literal 'C' string if the referenced address of the literal pool's entry 718 /// is an address into a section with 'C' string literals. 719 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 720 const void *Decoder) { 721 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 722 Dis->tryAddingPcLoadReferenceComment(Value, Address); 723 } 724 725 // Thumb1 instructions don't have explicit S bits. Rather, they 726 // implicitly set CPSR. Since it's not represented in the encoding, the 727 // auto-generated decoder won't inject the CPSR operand. We need to fix 728 // that as a post-pass. 729 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 730 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 731 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 732 MCInst::iterator I = MI.begin(); 733 for (unsigned i = 0; i < NumOps; ++i, ++I) { 734 if (I == MI.end()) break; 735 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 736 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 737 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 738 return; 739 } 740 } 741 742 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 743 } 744 745 static bool isVectorPredicable(unsigned Opcode) { 746 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 747 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 748 for (unsigned i = 0; i < NumOps; ++i) { 749 if (ARM::isVpred(OpInfo[i].OperandType)) 750 return true; 751 } 752 return false; 753 } 754 755 // Most Thumb instructions don't have explicit predicates in the 756 // encoding, but rather get their predicates from IT context. We need 757 // to fix up the predicate operands using this context information as a 758 // post-pass. 759 MCDisassembler::DecodeStatus 760 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 761 MCDisassembler::DecodeStatus S = Success; 762 763 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 764 765 // A few instructions actually have predicates encoded in them. Don't 766 // try to overwrite it if we're seeing one of those. 767 switch (MI.getOpcode()) { 768 case ARM::tBcc: 769 case ARM::t2Bcc: 770 case ARM::tCBZ: 771 case ARM::tCBNZ: 772 case ARM::tCPS: 773 case ARM::t2CPS3p: 774 case ARM::t2CPS2p: 775 case ARM::t2CPS1p: 776 case ARM::t2CSEL: 777 case ARM::t2CSINC: 778 case ARM::t2CSINV: 779 case ARM::t2CSNEG: 780 case ARM::tMOVSr: 781 case ARM::tSETEND: 782 // Some instructions (mostly conditional branches) are not 783 // allowed in IT blocks. 784 if (ITBlock.instrInITBlock()) 785 S = SoftFail; 786 else 787 return Success; 788 break; 789 case ARM::t2HINT: 790 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 791 S = SoftFail; 792 break; 793 case ARM::tB: 794 case ARM::t2B: 795 case ARM::t2TBB: 796 case ARM::t2TBH: 797 // Some instructions (mostly unconditional branches) can 798 // only appears at the end of, or outside of, an IT. 799 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 800 S = SoftFail; 801 break; 802 default: 803 break; 804 } 805 806 // Warn on non-VPT predicable instruction in a VPT block and a VPT 807 // predicable instruction in an IT block 808 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 809 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 810 S = SoftFail; 811 812 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 813 // assume a predicate of AL. 814 unsigned CC = ARMCC::AL; 815 unsigned VCC = ARMVCC::None; 816 if (ITBlock.instrInITBlock()) { 817 CC = ITBlock.getITCC(); 818 ITBlock.advanceITState(); 819 } else if (VPTBlock.instrInVPTBlock()) { 820 VCC = VPTBlock.getVPTPred(); 821 VPTBlock.advanceVPTState(); 822 } 823 824 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 825 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 826 827 MCInst::iterator CCI = MI.begin(); 828 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 829 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 830 } 831 832 if (ARMInsts[MI.getOpcode()].isPredicable()) { 833 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 834 ++CCI; 835 if (CC == ARMCC::AL) 836 MI.insert(CCI, MCOperand::createReg(0)); 837 else 838 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 839 } else if (CC != ARMCC::AL) { 840 Check(S, SoftFail); 841 } 842 843 MCInst::iterator VCCI = MI.begin(); 844 unsigned VCCPos; 845 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 846 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 847 } 848 849 if (isVectorPredicable(MI.getOpcode())) { 850 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 851 ++VCCI; 852 if (VCC == ARMVCC::None) 853 MI.insert(VCCI, MCOperand::createReg(0)); 854 else 855 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 856 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 857 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 858 VCCPos + 2, MCOI::TIED_TO); 859 assert(TiedOp >= 0 && 860 "Inactive register in vpred_r is not tied to an output!"); 861 MI.insert(VCCI, MI.getOperand(TiedOp)); 862 } 863 } else if (VCC != ARMVCC::None) { 864 Check(S, SoftFail); 865 } 866 867 return S; 868 } 869 870 // Thumb VFP instructions are a special case. Because we share their 871 // encodings between ARM and Thumb modes, and they are predicable in ARM 872 // mode, the auto-generated decoder will give them an (incorrect) 873 // predicate operand. We need to rewrite these operands based on the IT 874 // context as a post-pass. 875 void ARMDisassembler::UpdateThumbVFPPredicate( 876 DecodeStatus &S, MCInst &MI) const { 877 unsigned CC; 878 CC = ITBlock.getITCC(); 879 if (CC == 0xF) 880 CC = ARMCC::AL; 881 if (ITBlock.instrInITBlock()) 882 ITBlock.advanceITState(); 883 else if (VPTBlock.instrInVPTBlock()) { 884 CC = VPTBlock.getVPTPred(); 885 VPTBlock.advanceVPTState(); 886 } 887 888 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 889 MCInst::iterator I = MI.begin(); 890 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 891 for (unsigned i = 0; i < NumOps; ++i, ++I) { 892 if (OpInfo[i].isPredicate() ) { 893 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 894 Check(S, SoftFail); 895 I->setImm(CC); 896 ++I; 897 if (CC == ARMCC::AL) 898 I->setReg(0); 899 else 900 I->setReg(ARM::CPSR); 901 return; 902 } 903 } 904 } 905 906 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 907 ArrayRef<uint8_t> Bytes, 908 uint64_t Address, 909 raw_ostream &OS, 910 raw_ostream &CS) const { 911 CommentStream = &CS; 912 913 assert(STI.getFeatureBits()[ARM::ModeThumb] && 914 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 915 916 // We want to read exactly 2 bytes of data. 917 if (Bytes.size() < 2) { 918 Size = 0; 919 return MCDisassembler::Fail; 920 } 921 922 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 923 DecodeStatus Result = 924 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 925 if (Result != MCDisassembler::Fail) { 926 Size = 2; 927 Check(Result, AddThumbPredicate(MI)); 928 return Result; 929 } 930 931 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 932 STI); 933 if (Result) { 934 Size = 2; 935 bool InITBlock = ITBlock.instrInITBlock(); 936 Check(Result, AddThumbPredicate(MI)); 937 AddThumb1SBit(MI, InITBlock); 938 return Result; 939 } 940 941 Result = 942 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 943 if (Result != MCDisassembler::Fail) { 944 Size = 2; 945 946 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 947 // the Thumb predicate. 948 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 949 Result = MCDisassembler::SoftFail; 950 951 Check(Result, AddThumbPredicate(MI)); 952 953 // If we find an IT instruction, we need to parse its condition 954 // code and mask operands so that we can apply them correctly 955 // to the subsequent instructions. 956 if (MI.getOpcode() == ARM::t2IT) { 957 unsigned Firstcond = MI.getOperand(0).getImm(); 958 unsigned Mask = MI.getOperand(1).getImm(); 959 ITBlock.setITState(Firstcond, Mask); 960 961 // An IT instruction that would give a 'NV' predicate is unpredictable. 962 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 963 CS << "unpredictable IT predicate sequence"; 964 } 965 966 return Result; 967 } 968 969 // We want to read exactly 4 bytes of data. 970 if (Bytes.size() < 4) { 971 Size = 0; 972 return MCDisassembler::Fail; 973 } 974 975 uint32_t Insn32 = 976 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 977 978 Result = 979 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 980 if (Result != MCDisassembler::Fail) { 981 Size = 4; 982 983 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 984 // the VPT predicate. 985 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 986 Result = MCDisassembler::SoftFail; 987 988 Check(Result, AddThumbPredicate(MI)); 989 990 if (isVPTOpcode(MI.getOpcode())) { 991 unsigned Mask = MI.getOperand(0).getImm(); 992 VPTBlock.setVPTState(Mask); 993 } 994 995 return Result; 996 } 997 998 Result = 999 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1000 if (Result != MCDisassembler::Fail) { 1001 Size = 4; 1002 bool InITBlock = ITBlock.instrInITBlock(); 1003 Check(Result, AddThumbPredicate(MI)); 1004 AddThumb1SBit(MI, InITBlock); 1005 return Result; 1006 } 1007 1008 Result = 1009 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1010 if (Result != MCDisassembler::Fail) { 1011 Size = 4; 1012 Check(Result, AddThumbPredicate(MI)); 1013 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn32, Result); 1014 } 1015 1016 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1017 Result = 1018 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1019 if (Result != MCDisassembler::Fail) { 1020 Size = 4; 1021 UpdateThumbVFPPredicate(Result, MI); 1022 return Result; 1023 } 1024 } 1025 1026 Result = 1027 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1028 if (Result != MCDisassembler::Fail) { 1029 Size = 4; 1030 return Result; 1031 } 1032 1033 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1034 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1035 STI); 1036 if (Result != MCDisassembler::Fail) { 1037 Size = 4; 1038 Check(Result, AddThumbPredicate(MI)); 1039 return Result; 1040 } 1041 } 1042 1043 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1044 uint32_t NEONLdStInsn = Insn32; 1045 NEONLdStInsn &= 0xF0FFFFFF; 1046 NEONLdStInsn |= 0x04000000; 1047 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1048 Address, this, STI); 1049 if (Result != MCDisassembler::Fail) { 1050 Size = 4; 1051 Check(Result, AddThumbPredicate(MI)); 1052 return Result; 1053 } 1054 } 1055 1056 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1057 uint32_t NEONDataInsn = Insn32; 1058 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1059 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1060 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1061 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1062 Address, this, STI); 1063 if (Result != MCDisassembler::Fail) { 1064 Size = 4; 1065 Check(Result, AddThumbPredicate(MI)); 1066 return Result; 1067 } 1068 1069 uint32_t NEONCryptoInsn = Insn32; 1070 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1071 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1072 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1073 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1074 Address, this, STI); 1075 if (Result != MCDisassembler::Fail) { 1076 Size = 4; 1077 return Result; 1078 } 1079 1080 uint32_t NEONv8Insn = Insn32; 1081 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1082 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1083 this, STI); 1084 if (Result != MCDisassembler::Fail) { 1085 Size = 4; 1086 return Result; 1087 } 1088 } 1089 1090 Result = 1091 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI); 1092 if (Result != MCDisassembler::Fail) { 1093 Size = 4; 1094 Check(Result, AddThumbPredicate(MI)); 1095 return Result; 1096 } 1097 1098 Size = 0; 1099 return MCDisassembler::Fail; 1100 } 1101 1102 extern "C" void LLVMInitializeARMDisassembler() { 1103 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1104 createARMDisassembler); 1105 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1106 createARMDisassembler); 1107 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1108 createARMDisassembler); 1109 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1110 createARMDisassembler); 1111 } 1112 1113 static const uint16_t GPRDecoderTable[] = { 1114 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1115 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1116 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1118 }; 1119 1120 static const uint16_t CLRMGPRDecoderTable[] = { 1121 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1122 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1123 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1124 ARM::R12, 0, ARM::LR, ARM::APSR 1125 }; 1126 1127 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1128 uint64_t Address, const void *Decoder) { 1129 if (RegNo > 15) 1130 return MCDisassembler::Fail; 1131 1132 unsigned Register = GPRDecoderTable[RegNo]; 1133 Inst.addOperand(MCOperand::createReg(Register)); 1134 return MCDisassembler::Success; 1135 } 1136 1137 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1138 uint64_t Address, 1139 const void *Decoder) { 1140 if (RegNo > 15) 1141 return MCDisassembler::Fail; 1142 1143 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1144 if (Register == 0) 1145 return MCDisassembler::Fail; 1146 1147 Inst.addOperand(MCOperand::createReg(Register)); 1148 return MCDisassembler::Success; 1149 } 1150 1151 static DecodeStatus 1152 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1153 uint64_t Address, const void *Decoder) { 1154 DecodeStatus S = MCDisassembler::Success; 1155 1156 if (RegNo == 15) 1157 S = MCDisassembler::SoftFail; 1158 1159 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1160 1161 return S; 1162 } 1163 1164 static DecodeStatus 1165 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1166 uint64_t Address, const void *Decoder) { 1167 DecodeStatus S = MCDisassembler::Success; 1168 1169 if (RegNo == 15) 1170 { 1171 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1172 return MCDisassembler::Success; 1173 } 1174 1175 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1176 return S; 1177 } 1178 1179 static DecodeStatus 1180 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1181 uint64_t Address, const void *Decoder) { 1182 DecodeStatus S = MCDisassembler::Success; 1183 1184 if (RegNo == 15) 1185 { 1186 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1187 return MCDisassembler::Success; 1188 } 1189 1190 if (RegNo == 13) 1191 Check(S, MCDisassembler::SoftFail); 1192 1193 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1194 return S; 1195 } 1196 1197 static DecodeStatus 1198 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1199 uint64_t Address, const void *Decoder) { 1200 DecodeStatus S = MCDisassembler::Success; 1201 if (RegNo == 13) 1202 return MCDisassembler::Fail; 1203 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1204 return S; 1205 } 1206 1207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1208 uint64_t Address, const void *Decoder) { 1209 if (RegNo > 7) 1210 return MCDisassembler::Fail; 1211 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1212 } 1213 1214 static const uint16_t GPRPairDecoderTable[] = { 1215 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1216 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1217 }; 1218 1219 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1220 uint64_t Address, const void *Decoder) { 1221 DecodeStatus S = MCDisassembler::Success; 1222 1223 if (RegNo > 13) 1224 return MCDisassembler::Fail; 1225 1226 if ((RegNo & 1) || RegNo == 0xe) 1227 S = MCDisassembler::SoftFail; 1228 1229 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1230 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1231 return S; 1232 } 1233 1234 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1235 uint64_t Address, const void *Decoder) { 1236 unsigned Register = 0; 1237 switch (RegNo) { 1238 case 0: 1239 Register = ARM::R0; 1240 break; 1241 case 1: 1242 Register = ARM::R1; 1243 break; 1244 case 2: 1245 Register = ARM::R2; 1246 break; 1247 case 3: 1248 Register = ARM::R3; 1249 break; 1250 case 9: 1251 Register = ARM::R9; 1252 break; 1253 case 12: 1254 Register = ARM::R12; 1255 break; 1256 default: 1257 return MCDisassembler::Fail; 1258 } 1259 1260 Inst.addOperand(MCOperand::createReg(Register)); 1261 return MCDisassembler::Success; 1262 } 1263 1264 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1265 uint64_t Address, const void *Decoder) { 1266 DecodeStatus S = MCDisassembler::Success; 1267 1268 const FeatureBitset &featureBits = 1269 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1270 1271 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1272 S = MCDisassembler::SoftFail; 1273 1274 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1275 return S; 1276 } 1277 1278 static const uint16_t SPRDecoderTable[] = { 1279 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1280 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1281 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1282 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1283 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1284 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1285 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1286 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1287 }; 1288 1289 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1290 uint64_t Address, const void *Decoder) { 1291 if (RegNo > 31) 1292 return MCDisassembler::Fail; 1293 1294 unsigned Register = SPRDecoderTable[RegNo]; 1295 Inst.addOperand(MCOperand::createReg(Register)); 1296 return MCDisassembler::Success; 1297 } 1298 1299 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1300 uint64_t Address, const void *Decoder) { 1301 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1302 } 1303 1304 static const uint16_t DPRDecoderTable[] = { 1305 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1306 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1307 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1308 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1309 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1310 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1311 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1312 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1313 }; 1314 1315 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1316 uint64_t Address, const void *Decoder) { 1317 const FeatureBitset &featureBits = 1318 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1319 1320 bool hasD32 = featureBits[ARM::FeatureD32]; 1321 1322 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1323 return MCDisassembler::Fail; 1324 1325 unsigned Register = DPRDecoderTable[RegNo]; 1326 Inst.addOperand(MCOperand::createReg(Register)); 1327 return MCDisassembler::Success; 1328 } 1329 1330 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1331 uint64_t Address, const void *Decoder) { 1332 if (RegNo > 7) 1333 return MCDisassembler::Fail; 1334 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1335 } 1336 1337 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1338 uint64_t Address, const void *Decoder) { 1339 if (RegNo > 15) 1340 return MCDisassembler::Fail; 1341 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1342 } 1343 1344 static DecodeStatus 1345 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1346 uint64_t Address, const void *Decoder) { 1347 if (RegNo > 15) 1348 return MCDisassembler::Fail; 1349 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1350 } 1351 1352 static const uint16_t QPRDecoderTable[] = { 1353 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1354 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1355 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1356 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1357 }; 1358 1359 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1360 uint64_t Address, const void *Decoder) { 1361 if (RegNo > 31 || (RegNo & 1) != 0) 1362 return MCDisassembler::Fail; 1363 RegNo >>= 1; 1364 1365 unsigned Register = QPRDecoderTable[RegNo]; 1366 Inst.addOperand(MCOperand::createReg(Register)); 1367 return MCDisassembler::Success; 1368 } 1369 1370 static const uint16_t DPairDecoderTable[] = { 1371 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1372 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1373 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1374 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1375 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1376 ARM::Q15 1377 }; 1378 1379 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1380 uint64_t Address, const void *Decoder) { 1381 if (RegNo > 30) 1382 return MCDisassembler::Fail; 1383 1384 unsigned Register = DPairDecoderTable[RegNo]; 1385 Inst.addOperand(MCOperand::createReg(Register)); 1386 return MCDisassembler::Success; 1387 } 1388 1389 static const uint16_t DPairSpacedDecoderTable[] = { 1390 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1391 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1392 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1393 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1394 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1395 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1396 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1397 ARM::D28_D30, ARM::D29_D31 1398 }; 1399 1400 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1401 unsigned RegNo, 1402 uint64_t Address, 1403 const void *Decoder) { 1404 if (RegNo > 29) 1405 return MCDisassembler::Fail; 1406 1407 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1408 Inst.addOperand(MCOperand::createReg(Register)); 1409 return MCDisassembler::Success; 1410 } 1411 1412 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1413 uint64_t Address, const void *Decoder) { 1414 DecodeStatus S = MCDisassembler::Success; 1415 if (Val == 0xF) return MCDisassembler::Fail; 1416 // AL predicate is not allowed on Thumb1 branches. 1417 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1418 return MCDisassembler::Fail; 1419 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1420 Check(S, MCDisassembler::SoftFail); 1421 Inst.addOperand(MCOperand::createImm(Val)); 1422 if (Val == ARMCC::AL) { 1423 Inst.addOperand(MCOperand::createReg(0)); 1424 } else 1425 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1426 return S; 1427 } 1428 1429 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1430 uint64_t Address, const void *Decoder) { 1431 if (Val) 1432 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1433 else 1434 Inst.addOperand(MCOperand::createReg(0)); 1435 return MCDisassembler::Success; 1436 } 1437 1438 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1439 uint64_t Address, const void *Decoder) { 1440 DecodeStatus S = MCDisassembler::Success; 1441 1442 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1443 unsigned type = fieldFromInstruction(Val, 5, 2); 1444 unsigned imm = fieldFromInstruction(Val, 7, 5); 1445 1446 // Register-immediate 1447 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1448 return MCDisassembler::Fail; 1449 1450 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1451 switch (type) { 1452 case 0: 1453 Shift = ARM_AM::lsl; 1454 break; 1455 case 1: 1456 Shift = ARM_AM::lsr; 1457 break; 1458 case 2: 1459 Shift = ARM_AM::asr; 1460 break; 1461 case 3: 1462 Shift = ARM_AM::ror; 1463 break; 1464 } 1465 1466 if (Shift == ARM_AM::ror && imm == 0) 1467 Shift = ARM_AM::rrx; 1468 1469 unsigned Op = Shift | (imm << 3); 1470 Inst.addOperand(MCOperand::createImm(Op)); 1471 1472 return S; 1473 } 1474 1475 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1476 uint64_t Address, const void *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1480 unsigned type = fieldFromInstruction(Val, 5, 2); 1481 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1482 1483 // Register-register 1484 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1485 return MCDisassembler::Fail; 1486 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1487 return MCDisassembler::Fail; 1488 1489 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1490 switch (type) { 1491 case 0: 1492 Shift = ARM_AM::lsl; 1493 break; 1494 case 1: 1495 Shift = ARM_AM::lsr; 1496 break; 1497 case 2: 1498 Shift = ARM_AM::asr; 1499 break; 1500 case 3: 1501 Shift = ARM_AM::ror; 1502 break; 1503 } 1504 1505 Inst.addOperand(MCOperand::createImm(Shift)); 1506 1507 return S; 1508 } 1509 1510 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1511 uint64_t Address, const void *Decoder) { 1512 DecodeStatus S = MCDisassembler::Success; 1513 1514 bool NeedDisjointWriteback = false; 1515 unsigned WritebackReg = 0; 1516 bool CLRM = false; 1517 switch (Inst.getOpcode()) { 1518 default: 1519 break; 1520 case ARM::LDMIA_UPD: 1521 case ARM::LDMDB_UPD: 1522 case ARM::LDMIB_UPD: 1523 case ARM::LDMDA_UPD: 1524 case ARM::t2LDMIA_UPD: 1525 case ARM::t2LDMDB_UPD: 1526 case ARM::t2STMIA_UPD: 1527 case ARM::t2STMDB_UPD: 1528 NeedDisjointWriteback = true; 1529 WritebackReg = Inst.getOperand(0).getReg(); 1530 break; 1531 case ARM::t2CLRM: 1532 CLRM = true; 1533 break; 1534 } 1535 1536 // Empty register lists are not allowed. 1537 if (Val == 0) return MCDisassembler::Fail; 1538 for (unsigned i = 0; i < 16; ++i) { 1539 if (Val & (1 << i)) { 1540 if (CLRM) { 1541 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1542 return MCDisassembler::Fail; 1543 } 1544 } else { 1545 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1546 return MCDisassembler::Fail; 1547 // Writeback not allowed if Rn is in the target list. 1548 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1549 Check(S, MCDisassembler::SoftFail); 1550 } 1551 } 1552 } 1553 1554 return S; 1555 } 1556 1557 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1558 uint64_t Address, const void *Decoder) { 1559 DecodeStatus S = MCDisassembler::Success; 1560 1561 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1562 unsigned regs = fieldFromInstruction(Val, 0, 8); 1563 1564 // In case of unpredictable encoding, tweak the operands. 1565 if (regs == 0 || (Vd + regs) > 32) { 1566 regs = Vd + regs > 32 ? 32 - Vd : regs; 1567 regs = std::max( 1u, regs); 1568 S = MCDisassembler::SoftFail; 1569 } 1570 1571 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1572 return MCDisassembler::Fail; 1573 for (unsigned i = 0; i < (regs - 1); ++i) { 1574 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1575 return MCDisassembler::Fail; 1576 } 1577 1578 return S; 1579 } 1580 1581 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1582 uint64_t Address, const void *Decoder) { 1583 DecodeStatus S = MCDisassembler::Success; 1584 1585 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1586 unsigned regs = fieldFromInstruction(Val, 1, 7); 1587 1588 // In case of unpredictable encoding, tweak the operands. 1589 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1590 regs = Vd + regs > 32 ? 32 - Vd : regs; 1591 regs = std::max( 1u, regs); 1592 regs = std::min(16u, regs); 1593 S = MCDisassembler::SoftFail; 1594 } 1595 1596 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1597 return MCDisassembler::Fail; 1598 for (unsigned i = 0; i < (regs - 1); ++i) { 1599 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1600 return MCDisassembler::Fail; 1601 } 1602 1603 return S; 1604 } 1605 1606 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1607 uint64_t Address, const void *Decoder) { 1608 // This operand encodes a mask of contiguous zeros between a specified MSB 1609 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1610 // the mask of all bits LSB-and-lower, and then xor them to create 1611 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1612 // create the final mask. 1613 unsigned msb = fieldFromInstruction(Val, 5, 5); 1614 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1615 1616 DecodeStatus S = MCDisassembler::Success; 1617 if (lsb > msb) { 1618 Check(S, MCDisassembler::SoftFail); 1619 // The check above will cause the warning for the "potentially undefined 1620 // instruction encoding" but we can't build a bad MCOperand value here 1621 // with a lsb > msb or else printing the MCInst will cause a crash. 1622 lsb = msb; 1623 } 1624 1625 uint32_t msb_mask = 0xFFFFFFFF; 1626 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1627 uint32_t lsb_mask = (1U << lsb) - 1; 1628 1629 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1630 return S; 1631 } 1632 1633 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1634 uint64_t Address, const void *Decoder) { 1635 DecodeStatus S = MCDisassembler::Success; 1636 1637 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1638 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1639 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1640 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1641 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1642 unsigned U = fieldFromInstruction(Insn, 23, 1); 1643 const FeatureBitset &featureBits = 1644 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1645 1646 switch (Inst.getOpcode()) { 1647 case ARM::LDC_OFFSET: 1648 case ARM::LDC_PRE: 1649 case ARM::LDC_POST: 1650 case ARM::LDC_OPTION: 1651 case ARM::LDCL_OFFSET: 1652 case ARM::LDCL_PRE: 1653 case ARM::LDCL_POST: 1654 case ARM::LDCL_OPTION: 1655 case ARM::STC_OFFSET: 1656 case ARM::STC_PRE: 1657 case ARM::STC_POST: 1658 case ARM::STC_OPTION: 1659 case ARM::STCL_OFFSET: 1660 case ARM::STCL_PRE: 1661 case ARM::STCL_POST: 1662 case ARM::STCL_OPTION: 1663 case ARM::t2LDC_OFFSET: 1664 case ARM::t2LDC_PRE: 1665 case ARM::t2LDC_POST: 1666 case ARM::t2LDC_OPTION: 1667 case ARM::t2LDCL_OFFSET: 1668 case ARM::t2LDCL_PRE: 1669 case ARM::t2LDCL_POST: 1670 case ARM::t2LDCL_OPTION: 1671 case ARM::t2STC_OFFSET: 1672 case ARM::t2STC_PRE: 1673 case ARM::t2STC_POST: 1674 case ARM::t2STC_OPTION: 1675 case ARM::t2STCL_OFFSET: 1676 case ARM::t2STCL_PRE: 1677 case ARM::t2STCL_POST: 1678 case ARM::t2STCL_OPTION: 1679 case ARM::t2LDC2_OFFSET: 1680 case ARM::t2LDC2L_OFFSET: 1681 case ARM::t2LDC2_PRE: 1682 case ARM::t2LDC2L_PRE: 1683 case ARM::t2STC2_OFFSET: 1684 case ARM::t2STC2L_OFFSET: 1685 case ARM::t2STC2_PRE: 1686 case ARM::t2STC2L_PRE: 1687 case ARM::LDC2_OFFSET: 1688 case ARM::LDC2L_OFFSET: 1689 case ARM::LDC2_PRE: 1690 case ARM::LDC2L_PRE: 1691 case ARM::STC2_OFFSET: 1692 case ARM::STC2L_OFFSET: 1693 case ARM::STC2_PRE: 1694 case ARM::STC2L_PRE: 1695 case ARM::t2LDC2_OPTION: 1696 case ARM::t2STC2_OPTION: 1697 case ARM::t2LDC2_POST: 1698 case ARM::t2LDC2L_POST: 1699 case ARM::t2STC2_POST: 1700 case ARM::t2STC2L_POST: 1701 case ARM::LDC2_POST: 1702 case ARM::LDC2L_POST: 1703 case ARM::STC2_POST: 1704 case ARM::STC2L_POST: 1705 if (coproc == 0xA || coproc == 0xB || 1706 (featureBits[ARM::HasV8_1MMainlineOps] && 1707 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1708 coproc == 0xE || coproc == 0xF))) 1709 return MCDisassembler::Fail; 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1716 return MCDisassembler::Fail; 1717 1718 Inst.addOperand(MCOperand::createImm(coproc)); 1719 Inst.addOperand(MCOperand::createImm(CRd)); 1720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1721 return MCDisassembler::Fail; 1722 1723 switch (Inst.getOpcode()) { 1724 case ARM::t2LDC2_OFFSET: 1725 case ARM::t2LDC2L_OFFSET: 1726 case ARM::t2LDC2_PRE: 1727 case ARM::t2LDC2L_PRE: 1728 case ARM::t2STC2_OFFSET: 1729 case ARM::t2STC2L_OFFSET: 1730 case ARM::t2STC2_PRE: 1731 case ARM::t2STC2L_PRE: 1732 case ARM::LDC2_OFFSET: 1733 case ARM::LDC2L_OFFSET: 1734 case ARM::LDC2_PRE: 1735 case ARM::LDC2L_PRE: 1736 case ARM::STC2_OFFSET: 1737 case ARM::STC2L_OFFSET: 1738 case ARM::STC2_PRE: 1739 case ARM::STC2L_PRE: 1740 case ARM::t2LDC_OFFSET: 1741 case ARM::t2LDCL_OFFSET: 1742 case ARM::t2LDC_PRE: 1743 case ARM::t2LDCL_PRE: 1744 case ARM::t2STC_OFFSET: 1745 case ARM::t2STCL_OFFSET: 1746 case ARM::t2STC_PRE: 1747 case ARM::t2STCL_PRE: 1748 case ARM::LDC_OFFSET: 1749 case ARM::LDCL_OFFSET: 1750 case ARM::LDC_PRE: 1751 case ARM::LDCL_PRE: 1752 case ARM::STC_OFFSET: 1753 case ARM::STCL_OFFSET: 1754 case ARM::STC_PRE: 1755 case ARM::STCL_PRE: 1756 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1757 Inst.addOperand(MCOperand::createImm(imm)); 1758 break; 1759 case ARM::t2LDC2_POST: 1760 case ARM::t2LDC2L_POST: 1761 case ARM::t2STC2_POST: 1762 case ARM::t2STC2L_POST: 1763 case ARM::LDC2_POST: 1764 case ARM::LDC2L_POST: 1765 case ARM::STC2_POST: 1766 case ARM::STC2L_POST: 1767 case ARM::t2LDC_POST: 1768 case ARM::t2LDCL_POST: 1769 case ARM::t2STC_POST: 1770 case ARM::t2STCL_POST: 1771 case ARM::LDC_POST: 1772 case ARM::LDCL_POST: 1773 case ARM::STC_POST: 1774 case ARM::STCL_POST: 1775 imm |= U << 8; 1776 LLVM_FALLTHROUGH; 1777 default: 1778 // The 'option' variant doesn't encode 'U' in the immediate since 1779 // the immediate is unsigned [0,255]. 1780 Inst.addOperand(MCOperand::createImm(imm)); 1781 break; 1782 } 1783 1784 switch (Inst.getOpcode()) { 1785 case ARM::LDC_OFFSET: 1786 case ARM::LDC_PRE: 1787 case ARM::LDC_POST: 1788 case ARM::LDC_OPTION: 1789 case ARM::LDCL_OFFSET: 1790 case ARM::LDCL_PRE: 1791 case ARM::LDCL_POST: 1792 case ARM::LDCL_OPTION: 1793 case ARM::STC_OFFSET: 1794 case ARM::STC_PRE: 1795 case ARM::STC_POST: 1796 case ARM::STC_OPTION: 1797 case ARM::STCL_OFFSET: 1798 case ARM::STCL_PRE: 1799 case ARM::STCL_POST: 1800 case ARM::STCL_OPTION: 1801 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1802 return MCDisassembler::Fail; 1803 break; 1804 default: 1805 break; 1806 } 1807 1808 return S; 1809 } 1810 1811 static DecodeStatus 1812 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1813 uint64_t Address, const void *Decoder) { 1814 DecodeStatus S = MCDisassembler::Success; 1815 1816 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1817 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1818 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1819 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1820 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1821 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1822 unsigned P = fieldFromInstruction(Insn, 24, 1); 1823 unsigned W = fieldFromInstruction(Insn, 21, 1); 1824 1825 // On stores, the writeback operand precedes Rt. 1826 switch (Inst.getOpcode()) { 1827 case ARM::STR_POST_IMM: 1828 case ARM::STR_POST_REG: 1829 case ARM::STRB_POST_IMM: 1830 case ARM::STRB_POST_REG: 1831 case ARM::STRT_POST_REG: 1832 case ARM::STRT_POST_IMM: 1833 case ARM::STRBT_POST_REG: 1834 case ARM::STRBT_POST_IMM: 1835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1836 return MCDisassembler::Fail; 1837 break; 1838 default: 1839 break; 1840 } 1841 1842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1843 return MCDisassembler::Fail; 1844 1845 // On loads, the writeback operand comes after Rt. 1846 switch (Inst.getOpcode()) { 1847 case ARM::LDR_POST_IMM: 1848 case ARM::LDR_POST_REG: 1849 case ARM::LDRB_POST_IMM: 1850 case ARM::LDRB_POST_REG: 1851 case ARM::LDRBT_POST_REG: 1852 case ARM::LDRBT_POST_IMM: 1853 case ARM::LDRT_POST_REG: 1854 case ARM::LDRT_POST_IMM: 1855 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1856 return MCDisassembler::Fail; 1857 break; 1858 default: 1859 break; 1860 } 1861 1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1863 return MCDisassembler::Fail; 1864 1865 ARM_AM::AddrOpc Op = ARM_AM::add; 1866 if (!fieldFromInstruction(Insn, 23, 1)) 1867 Op = ARM_AM::sub; 1868 1869 bool writeback = (P == 0) || (W == 1); 1870 unsigned idx_mode = 0; 1871 if (P && writeback) 1872 idx_mode = ARMII::IndexModePre; 1873 else if (!P && writeback) 1874 idx_mode = ARMII::IndexModePost; 1875 1876 if (writeback && (Rn == 15 || Rn == Rt)) 1877 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1878 1879 if (reg) { 1880 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1881 return MCDisassembler::Fail; 1882 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1883 switch( fieldFromInstruction(Insn, 5, 2)) { 1884 case 0: 1885 Opc = ARM_AM::lsl; 1886 break; 1887 case 1: 1888 Opc = ARM_AM::lsr; 1889 break; 1890 case 2: 1891 Opc = ARM_AM::asr; 1892 break; 1893 case 3: 1894 Opc = ARM_AM::ror; 1895 break; 1896 default: 1897 return MCDisassembler::Fail; 1898 } 1899 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1900 if (Opc == ARM_AM::ror && amt == 0) 1901 Opc = ARM_AM::rrx; 1902 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1903 1904 Inst.addOperand(MCOperand::createImm(imm)); 1905 } else { 1906 Inst.addOperand(MCOperand::createReg(0)); 1907 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1908 Inst.addOperand(MCOperand::createImm(tmp)); 1909 } 1910 1911 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1912 return MCDisassembler::Fail; 1913 1914 return S; 1915 } 1916 1917 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1918 uint64_t Address, const void *Decoder) { 1919 DecodeStatus S = MCDisassembler::Success; 1920 1921 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1922 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1923 unsigned type = fieldFromInstruction(Val, 5, 2); 1924 unsigned imm = fieldFromInstruction(Val, 7, 5); 1925 unsigned U = fieldFromInstruction(Val, 12, 1); 1926 1927 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1928 switch (type) { 1929 case 0: 1930 ShOp = ARM_AM::lsl; 1931 break; 1932 case 1: 1933 ShOp = ARM_AM::lsr; 1934 break; 1935 case 2: 1936 ShOp = ARM_AM::asr; 1937 break; 1938 case 3: 1939 ShOp = ARM_AM::ror; 1940 break; 1941 } 1942 1943 if (ShOp == ARM_AM::ror && imm == 0) 1944 ShOp = ARM_AM::rrx; 1945 1946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 unsigned shift; 1951 if (U) 1952 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1953 else 1954 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1955 Inst.addOperand(MCOperand::createImm(shift)); 1956 1957 return S; 1958 } 1959 1960 static DecodeStatus 1961 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1962 uint64_t Address, const void *Decoder) { 1963 DecodeStatus S = MCDisassembler::Success; 1964 1965 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1966 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1967 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1968 unsigned type = fieldFromInstruction(Insn, 22, 1); 1969 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1970 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1971 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1972 unsigned W = fieldFromInstruction(Insn, 21, 1); 1973 unsigned P = fieldFromInstruction(Insn, 24, 1); 1974 unsigned Rt2 = Rt + 1; 1975 1976 bool writeback = (W == 1) | (P == 0); 1977 1978 // For {LD,ST}RD, Rt must be even, else undefined. 1979 switch (Inst.getOpcode()) { 1980 case ARM::STRD: 1981 case ARM::STRD_PRE: 1982 case ARM::STRD_POST: 1983 case ARM::LDRD: 1984 case ARM::LDRD_PRE: 1985 case ARM::LDRD_POST: 1986 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1987 break; 1988 default: 1989 break; 1990 } 1991 switch (Inst.getOpcode()) { 1992 case ARM::STRD: 1993 case ARM::STRD_PRE: 1994 case ARM::STRD_POST: 1995 if (P == 0 && W == 1) 1996 S = MCDisassembler::SoftFail; 1997 1998 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1999 S = MCDisassembler::SoftFail; 2000 if (type && Rm == 15) 2001 S = MCDisassembler::SoftFail; 2002 if (Rt2 == 15) 2003 S = MCDisassembler::SoftFail; 2004 if (!type && fieldFromInstruction(Insn, 8, 4)) 2005 S = MCDisassembler::SoftFail; 2006 break; 2007 case ARM::STRH: 2008 case ARM::STRH_PRE: 2009 case ARM::STRH_POST: 2010 if (Rt == 15) 2011 S = MCDisassembler::SoftFail; 2012 if (writeback && (Rn == 15 || Rn == Rt)) 2013 S = MCDisassembler::SoftFail; 2014 if (!type && Rm == 15) 2015 S = MCDisassembler::SoftFail; 2016 break; 2017 case ARM::LDRD: 2018 case ARM::LDRD_PRE: 2019 case ARM::LDRD_POST: 2020 if (type && Rn == 15) { 2021 if (Rt2 == 15) 2022 S = MCDisassembler::SoftFail; 2023 break; 2024 } 2025 if (P == 0 && W == 1) 2026 S = MCDisassembler::SoftFail; 2027 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2028 S = MCDisassembler::SoftFail; 2029 if (!type && writeback && Rn == 15) 2030 S = MCDisassembler::SoftFail; 2031 if (writeback && (Rn == Rt || Rn == Rt2)) 2032 S = MCDisassembler::SoftFail; 2033 break; 2034 case ARM::LDRH: 2035 case ARM::LDRH_PRE: 2036 case ARM::LDRH_POST: 2037 if (type && Rn == 15) { 2038 if (Rt == 15) 2039 S = MCDisassembler::SoftFail; 2040 break; 2041 } 2042 if (Rt == 15) 2043 S = MCDisassembler::SoftFail; 2044 if (!type && Rm == 15) 2045 S = MCDisassembler::SoftFail; 2046 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2047 S = MCDisassembler::SoftFail; 2048 break; 2049 case ARM::LDRSH: 2050 case ARM::LDRSH_PRE: 2051 case ARM::LDRSH_POST: 2052 case ARM::LDRSB: 2053 case ARM::LDRSB_PRE: 2054 case ARM::LDRSB_POST: 2055 if (type && Rn == 15) { 2056 if (Rt == 15) 2057 S = MCDisassembler::SoftFail; 2058 break; 2059 } 2060 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2061 S = MCDisassembler::SoftFail; 2062 if (!type && (Rt == 15 || Rm == 15)) 2063 S = MCDisassembler::SoftFail; 2064 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2065 S = MCDisassembler::SoftFail; 2066 break; 2067 default: 2068 break; 2069 } 2070 2071 if (writeback) { // Writeback 2072 if (P) 2073 U |= ARMII::IndexModePre << 9; 2074 else 2075 U |= ARMII::IndexModePost << 9; 2076 2077 // On stores, the writeback operand precedes Rt. 2078 switch (Inst.getOpcode()) { 2079 case ARM::STRD: 2080 case ARM::STRD_PRE: 2081 case ARM::STRD_POST: 2082 case ARM::STRH: 2083 case ARM::STRH_PRE: 2084 case ARM::STRH_POST: 2085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2086 return MCDisassembler::Fail; 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2094 return MCDisassembler::Fail; 2095 switch (Inst.getOpcode()) { 2096 case ARM::STRD: 2097 case ARM::STRD_PRE: 2098 case ARM::STRD_POST: 2099 case ARM::LDRD: 2100 case ARM::LDRD_PRE: 2101 case ARM::LDRD_POST: 2102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2103 return MCDisassembler::Fail; 2104 break; 2105 default: 2106 break; 2107 } 2108 2109 if (writeback) { 2110 // On loads, the writeback operand comes after Rt. 2111 switch (Inst.getOpcode()) { 2112 case ARM::LDRD: 2113 case ARM::LDRD_PRE: 2114 case ARM::LDRD_POST: 2115 case ARM::LDRH: 2116 case ARM::LDRH_PRE: 2117 case ARM::LDRH_POST: 2118 case ARM::LDRSH: 2119 case ARM::LDRSH_PRE: 2120 case ARM::LDRSH_POST: 2121 case ARM::LDRSB: 2122 case ARM::LDRSB_PRE: 2123 case ARM::LDRSB_POST: 2124 case ARM::LDRHTr: 2125 case ARM::LDRSBTr: 2126 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2127 return MCDisassembler::Fail; 2128 break; 2129 default: 2130 break; 2131 } 2132 } 2133 2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 2137 if (type) { 2138 Inst.addOperand(MCOperand::createReg(0)); 2139 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2140 } else { 2141 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2142 return MCDisassembler::Fail; 2143 Inst.addOperand(MCOperand::createImm(U)); 2144 } 2145 2146 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2147 return MCDisassembler::Fail; 2148 2149 return S; 2150 } 2151 2152 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2153 uint64_t Address, const void *Decoder) { 2154 DecodeStatus S = MCDisassembler::Success; 2155 2156 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2157 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2158 2159 switch (mode) { 2160 case 0: 2161 mode = ARM_AM::da; 2162 break; 2163 case 1: 2164 mode = ARM_AM::ia; 2165 break; 2166 case 2: 2167 mode = ARM_AM::db; 2168 break; 2169 case 3: 2170 mode = ARM_AM::ib; 2171 break; 2172 } 2173 2174 Inst.addOperand(MCOperand::createImm(mode)); 2175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 2178 return S; 2179 } 2180 2181 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2182 uint64_t Address, const void *Decoder) { 2183 DecodeStatus S = MCDisassembler::Success; 2184 2185 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2186 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2187 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2188 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2189 2190 if (pred == 0xF) 2191 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2192 2193 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2194 return MCDisassembler::Fail; 2195 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2196 return MCDisassembler::Fail; 2197 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2198 return MCDisassembler::Fail; 2199 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2200 return MCDisassembler::Fail; 2201 return S; 2202 } 2203 2204 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2205 unsigned Insn, 2206 uint64_t Address, const void *Decoder) { 2207 DecodeStatus S = MCDisassembler::Success; 2208 2209 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2210 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2211 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2212 2213 if (pred == 0xF) { 2214 // Ambiguous with RFE and SRS 2215 switch (Inst.getOpcode()) { 2216 case ARM::LDMDA: 2217 Inst.setOpcode(ARM::RFEDA); 2218 break; 2219 case ARM::LDMDA_UPD: 2220 Inst.setOpcode(ARM::RFEDA_UPD); 2221 break; 2222 case ARM::LDMDB: 2223 Inst.setOpcode(ARM::RFEDB); 2224 break; 2225 case ARM::LDMDB_UPD: 2226 Inst.setOpcode(ARM::RFEDB_UPD); 2227 break; 2228 case ARM::LDMIA: 2229 Inst.setOpcode(ARM::RFEIA); 2230 break; 2231 case ARM::LDMIA_UPD: 2232 Inst.setOpcode(ARM::RFEIA_UPD); 2233 break; 2234 case ARM::LDMIB: 2235 Inst.setOpcode(ARM::RFEIB); 2236 break; 2237 case ARM::LDMIB_UPD: 2238 Inst.setOpcode(ARM::RFEIB_UPD); 2239 break; 2240 case ARM::STMDA: 2241 Inst.setOpcode(ARM::SRSDA); 2242 break; 2243 case ARM::STMDA_UPD: 2244 Inst.setOpcode(ARM::SRSDA_UPD); 2245 break; 2246 case ARM::STMDB: 2247 Inst.setOpcode(ARM::SRSDB); 2248 break; 2249 case ARM::STMDB_UPD: 2250 Inst.setOpcode(ARM::SRSDB_UPD); 2251 break; 2252 case ARM::STMIA: 2253 Inst.setOpcode(ARM::SRSIA); 2254 break; 2255 case ARM::STMIA_UPD: 2256 Inst.setOpcode(ARM::SRSIA_UPD); 2257 break; 2258 case ARM::STMIB: 2259 Inst.setOpcode(ARM::SRSIB); 2260 break; 2261 case ARM::STMIB_UPD: 2262 Inst.setOpcode(ARM::SRSIB_UPD); 2263 break; 2264 default: 2265 return MCDisassembler::Fail; 2266 } 2267 2268 // For stores (which become SRS's, the only operand is the mode. 2269 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2270 // Check SRS encoding constraints 2271 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2272 fieldFromInstruction(Insn, 20, 1) == 0)) 2273 return MCDisassembler::Fail; 2274 2275 Inst.addOperand( 2276 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2277 return S; 2278 } 2279 2280 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2281 } 2282 2283 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2284 return MCDisassembler::Fail; 2285 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2286 return MCDisassembler::Fail; // Tied 2287 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2288 return MCDisassembler::Fail; 2289 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2290 return MCDisassembler::Fail; 2291 2292 return S; 2293 } 2294 2295 // Check for UNPREDICTABLE predicated ESB instruction 2296 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2297 uint64_t Address, const void *Decoder) { 2298 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2299 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2300 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2301 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2302 2303 DecodeStatus S = MCDisassembler::Success; 2304 2305 Inst.addOperand(MCOperand::createImm(imm8)); 2306 2307 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2308 return MCDisassembler::Fail; 2309 2310 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2311 // so all predicates should be allowed. 2312 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2313 S = MCDisassembler::SoftFail; 2314 2315 return S; 2316 } 2317 2318 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2319 uint64_t Address, const void *Decoder) { 2320 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2321 unsigned M = fieldFromInstruction(Insn, 17, 1); 2322 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2323 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2324 2325 DecodeStatus S = MCDisassembler::Success; 2326 2327 // This decoder is called from multiple location that do not check 2328 // the full encoding is valid before they do. 2329 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2330 fieldFromInstruction(Insn, 16, 1) != 0 || 2331 fieldFromInstruction(Insn, 20, 8) != 0x10) 2332 return MCDisassembler::Fail; 2333 2334 // imod == '01' --> UNPREDICTABLE 2335 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2336 // return failure here. The '01' imod value is unprintable, so there's 2337 // nothing useful we could do even if we returned UNPREDICTABLE. 2338 2339 if (imod == 1) return MCDisassembler::Fail; 2340 2341 if (imod && M) { 2342 Inst.setOpcode(ARM::CPS3p); 2343 Inst.addOperand(MCOperand::createImm(imod)); 2344 Inst.addOperand(MCOperand::createImm(iflags)); 2345 Inst.addOperand(MCOperand::createImm(mode)); 2346 } else if (imod && !M) { 2347 Inst.setOpcode(ARM::CPS2p); 2348 Inst.addOperand(MCOperand::createImm(imod)); 2349 Inst.addOperand(MCOperand::createImm(iflags)); 2350 if (mode) S = MCDisassembler::SoftFail; 2351 } else if (!imod && M) { 2352 Inst.setOpcode(ARM::CPS1p); 2353 Inst.addOperand(MCOperand::createImm(mode)); 2354 if (iflags) S = MCDisassembler::SoftFail; 2355 } else { 2356 // imod == '00' && M == '0' --> UNPREDICTABLE 2357 Inst.setOpcode(ARM::CPS1p); 2358 Inst.addOperand(MCOperand::createImm(mode)); 2359 S = MCDisassembler::SoftFail; 2360 } 2361 2362 return S; 2363 } 2364 2365 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2366 uint64_t Address, const void *Decoder) { 2367 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2368 unsigned M = fieldFromInstruction(Insn, 8, 1); 2369 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2370 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2371 2372 DecodeStatus S = MCDisassembler::Success; 2373 2374 // imod == '01' --> UNPREDICTABLE 2375 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2376 // return failure here. The '01' imod value is unprintable, so there's 2377 // nothing useful we could do even if we returned UNPREDICTABLE. 2378 2379 if (imod == 1) return MCDisassembler::Fail; 2380 2381 if (imod && M) { 2382 Inst.setOpcode(ARM::t2CPS3p); 2383 Inst.addOperand(MCOperand::createImm(imod)); 2384 Inst.addOperand(MCOperand::createImm(iflags)); 2385 Inst.addOperand(MCOperand::createImm(mode)); 2386 } else if (imod && !M) { 2387 Inst.setOpcode(ARM::t2CPS2p); 2388 Inst.addOperand(MCOperand::createImm(imod)); 2389 Inst.addOperand(MCOperand::createImm(iflags)); 2390 if (mode) S = MCDisassembler::SoftFail; 2391 } else if (!imod && M) { 2392 Inst.setOpcode(ARM::t2CPS1p); 2393 Inst.addOperand(MCOperand::createImm(mode)); 2394 if (iflags) S = MCDisassembler::SoftFail; 2395 } else { 2396 // imod == '00' && M == '0' --> this is a HINT instruction 2397 int imm = fieldFromInstruction(Insn, 0, 8); 2398 // HINT are defined only for immediate in [0..4] 2399 if(imm > 4) return MCDisassembler::Fail; 2400 Inst.setOpcode(ARM::t2HINT); 2401 Inst.addOperand(MCOperand::createImm(imm)); 2402 } 2403 2404 return S; 2405 } 2406 2407 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2408 uint64_t Address, const void *Decoder) { 2409 DecodeStatus S = MCDisassembler::Success; 2410 2411 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2412 unsigned imm = 0; 2413 2414 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2415 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2416 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2417 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2418 2419 if (Inst.getOpcode() == ARM::t2MOVTi16) 2420 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2421 return MCDisassembler::Fail; 2422 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2423 return MCDisassembler::Fail; 2424 2425 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2426 Inst.addOperand(MCOperand::createImm(imm)); 2427 2428 return S; 2429 } 2430 2431 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2432 uint64_t Address, const void *Decoder) { 2433 DecodeStatus S = MCDisassembler::Success; 2434 2435 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2436 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2437 unsigned imm = 0; 2438 2439 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2440 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2441 2442 if (Inst.getOpcode() == ARM::MOVTi16) 2443 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 2446 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2447 return MCDisassembler::Fail; 2448 2449 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2450 Inst.addOperand(MCOperand::createImm(imm)); 2451 2452 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2453 return MCDisassembler::Fail; 2454 2455 return S; 2456 } 2457 2458 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2459 uint64_t Address, const void *Decoder) { 2460 DecodeStatus S = MCDisassembler::Success; 2461 2462 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2463 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2464 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2465 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2466 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2467 2468 if (pred == 0xF) 2469 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2470 2471 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2472 return MCDisassembler::Fail; 2473 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2474 return MCDisassembler::Fail; 2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2478 return MCDisassembler::Fail; 2479 2480 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2481 return MCDisassembler::Fail; 2482 2483 return S; 2484 } 2485 2486 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2487 uint64_t Address, const void *Decoder) { 2488 DecodeStatus S = MCDisassembler::Success; 2489 2490 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2491 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2492 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2493 2494 if (Pred == 0xF) 2495 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2496 2497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2498 return MCDisassembler::Fail; 2499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2500 return MCDisassembler::Fail; 2501 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2502 return MCDisassembler::Fail; 2503 2504 return S; 2505 } 2506 2507 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2508 uint64_t Address, const void *Decoder) { 2509 DecodeStatus S = MCDisassembler::Success; 2510 2511 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2512 2513 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2514 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2515 2516 if (!FeatureBits[ARM::HasV8_1aOps] || 2517 !FeatureBits[ARM::HasV8Ops]) 2518 return MCDisassembler::Fail; 2519 2520 // Decoder can be called from DecodeTST, which does not check the full 2521 // encoding is valid. 2522 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2523 fieldFromInstruction(Insn, 4,4) != 0) 2524 return MCDisassembler::Fail; 2525 if (fieldFromInstruction(Insn, 10,10) != 0 || 2526 fieldFromInstruction(Insn, 0,4) != 0) 2527 S = MCDisassembler::SoftFail; 2528 2529 Inst.setOpcode(ARM::SETPAN); 2530 Inst.addOperand(MCOperand::createImm(Imm)); 2531 2532 return S; 2533 } 2534 2535 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2536 uint64_t Address, const void *Decoder) { 2537 DecodeStatus S = MCDisassembler::Success; 2538 2539 unsigned add = fieldFromInstruction(Val, 12, 1); 2540 unsigned imm = fieldFromInstruction(Val, 0, 12); 2541 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2542 2543 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2544 return MCDisassembler::Fail; 2545 2546 if (!add) imm *= -1; 2547 if (imm == 0 && !add) imm = INT32_MIN; 2548 Inst.addOperand(MCOperand::createImm(imm)); 2549 if (Rn == 15) 2550 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2551 2552 return S; 2553 } 2554 2555 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2556 uint64_t Address, const void *Decoder) { 2557 DecodeStatus S = MCDisassembler::Success; 2558 2559 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2560 // U == 1 to add imm, 0 to subtract it. 2561 unsigned U = fieldFromInstruction(Val, 8, 1); 2562 unsigned imm = fieldFromInstruction(Val, 0, 8); 2563 2564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2565 return MCDisassembler::Fail; 2566 2567 if (U) 2568 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2569 else 2570 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2571 2572 return S; 2573 } 2574 2575 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2576 uint64_t Address, const void *Decoder) { 2577 DecodeStatus S = MCDisassembler::Success; 2578 2579 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2580 // U == 1 to add imm, 0 to subtract it. 2581 unsigned U = fieldFromInstruction(Val, 8, 1); 2582 unsigned imm = fieldFromInstruction(Val, 0, 8); 2583 2584 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2585 return MCDisassembler::Fail; 2586 2587 if (U) 2588 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2589 else 2590 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2591 2592 return S; 2593 } 2594 2595 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2596 uint64_t Address, const void *Decoder) { 2597 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2598 } 2599 2600 static DecodeStatus 2601 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2602 uint64_t Address, const void *Decoder) { 2603 DecodeStatus Status = MCDisassembler::Success; 2604 2605 // Note the J1 and J2 values are from the encoded instruction. So here 2606 // change them to I1 and I2 values via as documented: 2607 // I1 = NOT(J1 EOR S); 2608 // I2 = NOT(J2 EOR S); 2609 // and build the imm32 with one trailing zero as documented: 2610 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2611 unsigned S = fieldFromInstruction(Insn, 26, 1); 2612 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2613 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2614 unsigned I1 = !(J1 ^ S); 2615 unsigned I2 = !(J2 ^ S); 2616 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2617 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2618 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2619 int imm32 = SignExtend32<25>(tmp << 1); 2620 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2621 true, 4, Inst, Decoder)) 2622 Inst.addOperand(MCOperand::createImm(imm32)); 2623 2624 return Status; 2625 } 2626 2627 static DecodeStatus 2628 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2629 uint64_t Address, const void *Decoder) { 2630 DecodeStatus S = MCDisassembler::Success; 2631 2632 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2633 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2634 2635 if (pred == 0xF) { 2636 Inst.setOpcode(ARM::BLXi); 2637 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2638 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2639 true, 4, Inst, Decoder)) 2640 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2641 return S; 2642 } 2643 2644 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2645 true, 4, Inst, Decoder)) 2646 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2647 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2648 return MCDisassembler::Fail; 2649 2650 return S; 2651 } 2652 2653 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2654 uint64_t Address, const void *Decoder) { 2655 DecodeStatus S = MCDisassembler::Success; 2656 2657 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2658 unsigned align = fieldFromInstruction(Val, 4, 2); 2659 2660 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2661 return MCDisassembler::Fail; 2662 if (!align) 2663 Inst.addOperand(MCOperand::createImm(0)); 2664 else 2665 Inst.addOperand(MCOperand::createImm(4 << align)); 2666 2667 return S; 2668 } 2669 2670 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2671 uint64_t Address, const void *Decoder) { 2672 DecodeStatus S = MCDisassembler::Success; 2673 2674 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2675 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2676 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2677 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2678 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2679 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2680 2681 // First output register 2682 switch (Inst.getOpcode()) { 2683 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2684 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2685 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2686 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2687 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2688 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2689 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2690 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2691 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2692 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 break; 2695 case ARM::VLD2b16: 2696 case ARM::VLD2b32: 2697 case ARM::VLD2b8: 2698 case ARM::VLD2b16wb_fixed: 2699 case ARM::VLD2b16wb_register: 2700 case ARM::VLD2b32wb_fixed: 2701 case ARM::VLD2b32wb_register: 2702 case ARM::VLD2b8wb_fixed: 2703 case ARM::VLD2b8wb_register: 2704 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2705 return MCDisassembler::Fail; 2706 break; 2707 default: 2708 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2709 return MCDisassembler::Fail; 2710 } 2711 2712 // Second output register 2713 switch (Inst.getOpcode()) { 2714 case ARM::VLD3d8: 2715 case ARM::VLD3d16: 2716 case ARM::VLD3d32: 2717 case ARM::VLD3d8_UPD: 2718 case ARM::VLD3d16_UPD: 2719 case ARM::VLD3d32_UPD: 2720 case ARM::VLD4d8: 2721 case ARM::VLD4d16: 2722 case ARM::VLD4d32: 2723 case ARM::VLD4d8_UPD: 2724 case ARM::VLD4d16_UPD: 2725 case ARM::VLD4d32_UPD: 2726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 break; 2729 case ARM::VLD3q8: 2730 case ARM::VLD3q16: 2731 case ARM::VLD3q32: 2732 case ARM::VLD3q8_UPD: 2733 case ARM::VLD3q16_UPD: 2734 case ARM::VLD3q32_UPD: 2735 case ARM::VLD4q8: 2736 case ARM::VLD4q16: 2737 case ARM::VLD4q32: 2738 case ARM::VLD4q8_UPD: 2739 case ARM::VLD4q16_UPD: 2740 case ARM::VLD4q32_UPD: 2741 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2742 return MCDisassembler::Fail; 2743 break; 2744 default: 2745 break; 2746 } 2747 2748 // Third output register 2749 switch(Inst.getOpcode()) { 2750 case ARM::VLD3d8: 2751 case ARM::VLD3d16: 2752 case ARM::VLD3d32: 2753 case ARM::VLD3d8_UPD: 2754 case ARM::VLD3d16_UPD: 2755 case ARM::VLD3d32_UPD: 2756 case ARM::VLD4d8: 2757 case ARM::VLD4d16: 2758 case ARM::VLD4d32: 2759 case ARM::VLD4d8_UPD: 2760 case ARM::VLD4d16_UPD: 2761 case ARM::VLD4d32_UPD: 2762 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2763 return MCDisassembler::Fail; 2764 break; 2765 case ARM::VLD3q8: 2766 case ARM::VLD3q16: 2767 case ARM::VLD3q32: 2768 case ARM::VLD3q8_UPD: 2769 case ARM::VLD3q16_UPD: 2770 case ARM::VLD3q32_UPD: 2771 case ARM::VLD4q8: 2772 case ARM::VLD4q16: 2773 case ARM::VLD4q32: 2774 case ARM::VLD4q8_UPD: 2775 case ARM::VLD4q16_UPD: 2776 case ARM::VLD4q32_UPD: 2777 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2778 return MCDisassembler::Fail; 2779 break; 2780 default: 2781 break; 2782 } 2783 2784 // Fourth output register 2785 switch (Inst.getOpcode()) { 2786 case ARM::VLD4d8: 2787 case ARM::VLD4d16: 2788 case ARM::VLD4d32: 2789 case ARM::VLD4d8_UPD: 2790 case ARM::VLD4d16_UPD: 2791 case ARM::VLD4d32_UPD: 2792 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2793 return MCDisassembler::Fail; 2794 break; 2795 case ARM::VLD4q8: 2796 case ARM::VLD4q16: 2797 case ARM::VLD4q32: 2798 case ARM::VLD4q8_UPD: 2799 case ARM::VLD4q16_UPD: 2800 case ARM::VLD4q32_UPD: 2801 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2802 return MCDisassembler::Fail; 2803 break; 2804 default: 2805 break; 2806 } 2807 2808 // Writeback operand 2809 switch (Inst.getOpcode()) { 2810 case ARM::VLD1d8wb_fixed: 2811 case ARM::VLD1d16wb_fixed: 2812 case ARM::VLD1d32wb_fixed: 2813 case ARM::VLD1d64wb_fixed: 2814 case ARM::VLD1d8wb_register: 2815 case ARM::VLD1d16wb_register: 2816 case ARM::VLD1d32wb_register: 2817 case ARM::VLD1d64wb_register: 2818 case ARM::VLD1q8wb_fixed: 2819 case ARM::VLD1q16wb_fixed: 2820 case ARM::VLD1q32wb_fixed: 2821 case ARM::VLD1q64wb_fixed: 2822 case ARM::VLD1q8wb_register: 2823 case ARM::VLD1q16wb_register: 2824 case ARM::VLD1q32wb_register: 2825 case ARM::VLD1q64wb_register: 2826 case ARM::VLD1d8Twb_fixed: 2827 case ARM::VLD1d8Twb_register: 2828 case ARM::VLD1d16Twb_fixed: 2829 case ARM::VLD1d16Twb_register: 2830 case ARM::VLD1d32Twb_fixed: 2831 case ARM::VLD1d32Twb_register: 2832 case ARM::VLD1d64Twb_fixed: 2833 case ARM::VLD1d64Twb_register: 2834 case ARM::VLD1d8Qwb_fixed: 2835 case ARM::VLD1d8Qwb_register: 2836 case ARM::VLD1d16Qwb_fixed: 2837 case ARM::VLD1d16Qwb_register: 2838 case ARM::VLD1d32Qwb_fixed: 2839 case ARM::VLD1d32Qwb_register: 2840 case ARM::VLD1d64Qwb_fixed: 2841 case ARM::VLD1d64Qwb_register: 2842 case ARM::VLD2d8wb_fixed: 2843 case ARM::VLD2d16wb_fixed: 2844 case ARM::VLD2d32wb_fixed: 2845 case ARM::VLD2q8wb_fixed: 2846 case ARM::VLD2q16wb_fixed: 2847 case ARM::VLD2q32wb_fixed: 2848 case ARM::VLD2d8wb_register: 2849 case ARM::VLD2d16wb_register: 2850 case ARM::VLD2d32wb_register: 2851 case ARM::VLD2q8wb_register: 2852 case ARM::VLD2q16wb_register: 2853 case ARM::VLD2q32wb_register: 2854 case ARM::VLD2b8wb_fixed: 2855 case ARM::VLD2b16wb_fixed: 2856 case ARM::VLD2b32wb_fixed: 2857 case ARM::VLD2b8wb_register: 2858 case ARM::VLD2b16wb_register: 2859 case ARM::VLD2b32wb_register: 2860 Inst.addOperand(MCOperand::createImm(0)); 2861 break; 2862 case ARM::VLD3d8_UPD: 2863 case ARM::VLD3d16_UPD: 2864 case ARM::VLD3d32_UPD: 2865 case ARM::VLD3q8_UPD: 2866 case ARM::VLD3q16_UPD: 2867 case ARM::VLD3q32_UPD: 2868 case ARM::VLD4d8_UPD: 2869 case ARM::VLD4d16_UPD: 2870 case ARM::VLD4d32_UPD: 2871 case ARM::VLD4q8_UPD: 2872 case ARM::VLD4q16_UPD: 2873 case ARM::VLD4q32_UPD: 2874 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 break; 2877 default: 2878 break; 2879 } 2880 2881 // AddrMode6 Base (register+alignment) 2882 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2883 return MCDisassembler::Fail; 2884 2885 // AddrMode6 Offset (register) 2886 switch (Inst.getOpcode()) { 2887 default: 2888 // The below have been updated to have explicit am6offset split 2889 // between fixed and register offset. For those instructions not 2890 // yet updated, we need to add an additional reg0 operand for the 2891 // fixed variant. 2892 // 2893 // The fixed offset encodes as Rm == 0xd, so we check for that. 2894 if (Rm == 0xd) { 2895 Inst.addOperand(MCOperand::createReg(0)); 2896 break; 2897 } 2898 // Fall through to handle the register offset variant. 2899 LLVM_FALLTHROUGH; 2900 case ARM::VLD1d8wb_fixed: 2901 case ARM::VLD1d16wb_fixed: 2902 case ARM::VLD1d32wb_fixed: 2903 case ARM::VLD1d64wb_fixed: 2904 case ARM::VLD1d8Twb_fixed: 2905 case ARM::VLD1d16Twb_fixed: 2906 case ARM::VLD1d32Twb_fixed: 2907 case ARM::VLD1d64Twb_fixed: 2908 case ARM::VLD1d8Qwb_fixed: 2909 case ARM::VLD1d16Qwb_fixed: 2910 case ARM::VLD1d32Qwb_fixed: 2911 case ARM::VLD1d64Qwb_fixed: 2912 case ARM::VLD1d8wb_register: 2913 case ARM::VLD1d16wb_register: 2914 case ARM::VLD1d32wb_register: 2915 case ARM::VLD1d64wb_register: 2916 case ARM::VLD1q8wb_fixed: 2917 case ARM::VLD1q16wb_fixed: 2918 case ARM::VLD1q32wb_fixed: 2919 case ARM::VLD1q64wb_fixed: 2920 case ARM::VLD1q8wb_register: 2921 case ARM::VLD1q16wb_register: 2922 case ARM::VLD1q32wb_register: 2923 case ARM::VLD1q64wb_register: 2924 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2925 // variant encodes Rm == 0xf. Anything else is a register offset post- 2926 // increment and we need to add the register operand to the instruction. 2927 if (Rm != 0xD && Rm != 0xF && 2928 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2929 return MCDisassembler::Fail; 2930 break; 2931 case ARM::VLD2d8wb_fixed: 2932 case ARM::VLD2d16wb_fixed: 2933 case ARM::VLD2d32wb_fixed: 2934 case ARM::VLD2b8wb_fixed: 2935 case ARM::VLD2b16wb_fixed: 2936 case ARM::VLD2b32wb_fixed: 2937 case ARM::VLD2q8wb_fixed: 2938 case ARM::VLD2q16wb_fixed: 2939 case ARM::VLD2q32wb_fixed: 2940 break; 2941 } 2942 2943 return S; 2944 } 2945 2946 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2947 uint64_t Address, const void *Decoder) { 2948 unsigned type = fieldFromInstruction(Insn, 8, 4); 2949 unsigned align = fieldFromInstruction(Insn, 4, 2); 2950 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2951 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2952 if (type == 10 && align == 3) return MCDisassembler::Fail; 2953 2954 unsigned load = fieldFromInstruction(Insn, 21, 1); 2955 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2956 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2957 } 2958 2959 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2960 uint64_t Address, const void *Decoder) { 2961 unsigned size = fieldFromInstruction(Insn, 6, 2); 2962 if (size == 3) return MCDisassembler::Fail; 2963 2964 unsigned type = fieldFromInstruction(Insn, 8, 4); 2965 unsigned align = fieldFromInstruction(Insn, 4, 2); 2966 if (type == 8 && align == 3) return MCDisassembler::Fail; 2967 if (type == 9 && align == 3) return MCDisassembler::Fail; 2968 2969 unsigned load = fieldFromInstruction(Insn, 21, 1); 2970 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2971 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2972 } 2973 2974 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2975 uint64_t Address, const void *Decoder) { 2976 unsigned size = fieldFromInstruction(Insn, 6, 2); 2977 if (size == 3) return MCDisassembler::Fail; 2978 2979 unsigned align = fieldFromInstruction(Insn, 4, 2); 2980 if (align & 2) return MCDisassembler::Fail; 2981 2982 unsigned load = fieldFromInstruction(Insn, 21, 1); 2983 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2984 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2985 } 2986 2987 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2988 uint64_t Address, const void *Decoder) { 2989 unsigned size = fieldFromInstruction(Insn, 6, 2); 2990 if (size == 3) return MCDisassembler::Fail; 2991 2992 unsigned load = fieldFromInstruction(Insn, 21, 1); 2993 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2994 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2995 } 2996 2997 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2998 uint64_t Address, const void *Decoder) { 2999 DecodeStatus S = MCDisassembler::Success; 3000 3001 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3003 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3004 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3005 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3006 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3007 3008 // Writeback Operand 3009 switch (Inst.getOpcode()) { 3010 case ARM::VST1d8wb_fixed: 3011 case ARM::VST1d16wb_fixed: 3012 case ARM::VST1d32wb_fixed: 3013 case ARM::VST1d64wb_fixed: 3014 case ARM::VST1d8wb_register: 3015 case ARM::VST1d16wb_register: 3016 case ARM::VST1d32wb_register: 3017 case ARM::VST1d64wb_register: 3018 case ARM::VST1q8wb_fixed: 3019 case ARM::VST1q16wb_fixed: 3020 case ARM::VST1q32wb_fixed: 3021 case ARM::VST1q64wb_fixed: 3022 case ARM::VST1q8wb_register: 3023 case ARM::VST1q16wb_register: 3024 case ARM::VST1q32wb_register: 3025 case ARM::VST1q64wb_register: 3026 case ARM::VST1d8Twb_fixed: 3027 case ARM::VST1d16Twb_fixed: 3028 case ARM::VST1d32Twb_fixed: 3029 case ARM::VST1d64Twb_fixed: 3030 case ARM::VST1d8Twb_register: 3031 case ARM::VST1d16Twb_register: 3032 case ARM::VST1d32Twb_register: 3033 case ARM::VST1d64Twb_register: 3034 case ARM::VST1d8Qwb_fixed: 3035 case ARM::VST1d16Qwb_fixed: 3036 case ARM::VST1d32Qwb_fixed: 3037 case ARM::VST1d64Qwb_fixed: 3038 case ARM::VST1d8Qwb_register: 3039 case ARM::VST1d16Qwb_register: 3040 case ARM::VST1d32Qwb_register: 3041 case ARM::VST1d64Qwb_register: 3042 case ARM::VST2d8wb_fixed: 3043 case ARM::VST2d16wb_fixed: 3044 case ARM::VST2d32wb_fixed: 3045 case ARM::VST2d8wb_register: 3046 case ARM::VST2d16wb_register: 3047 case ARM::VST2d32wb_register: 3048 case ARM::VST2q8wb_fixed: 3049 case ARM::VST2q16wb_fixed: 3050 case ARM::VST2q32wb_fixed: 3051 case ARM::VST2q8wb_register: 3052 case ARM::VST2q16wb_register: 3053 case ARM::VST2q32wb_register: 3054 case ARM::VST2b8wb_fixed: 3055 case ARM::VST2b16wb_fixed: 3056 case ARM::VST2b32wb_fixed: 3057 case ARM::VST2b8wb_register: 3058 case ARM::VST2b16wb_register: 3059 case ARM::VST2b32wb_register: 3060 if (Rm == 0xF) 3061 return MCDisassembler::Fail; 3062 Inst.addOperand(MCOperand::createImm(0)); 3063 break; 3064 case ARM::VST3d8_UPD: 3065 case ARM::VST3d16_UPD: 3066 case ARM::VST3d32_UPD: 3067 case ARM::VST3q8_UPD: 3068 case ARM::VST3q16_UPD: 3069 case ARM::VST3q32_UPD: 3070 case ARM::VST4d8_UPD: 3071 case ARM::VST4d16_UPD: 3072 case ARM::VST4d32_UPD: 3073 case ARM::VST4q8_UPD: 3074 case ARM::VST4q16_UPD: 3075 case ARM::VST4q32_UPD: 3076 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3077 return MCDisassembler::Fail; 3078 break; 3079 default: 3080 break; 3081 } 3082 3083 // AddrMode6 Base (register+alignment) 3084 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3085 return MCDisassembler::Fail; 3086 3087 // AddrMode6 Offset (register) 3088 switch (Inst.getOpcode()) { 3089 default: 3090 if (Rm == 0xD) 3091 Inst.addOperand(MCOperand::createReg(0)); 3092 else if (Rm != 0xF) { 3093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3094 return MCDisassembler::Fail; 3095 } 3096 break; 3097 case ARM::VST1d8wb_fixed: 3098 case ARM::VST1d16wb_fixed: 3099 case ARM::VST1d32wb_fixed: 3100 case ARM::VST1d64wb_fixed: 3101 case ARM::VST1q8wb_fixed: 3102 case ARM::VST1q16wb_fixed: 3103 case ARM::VST1q32wb_fixed: 3104 case ARM::VST1q64wb_fixed: 3105 case ARM::VST1d8Twb_fixed: 3106 case ARM::VST1d16Twb_fixed: 3107 case ARM::VST1d32Twb_fixed: 3108 case ARM::VST1d64Twb_fixed: 3109 case ARM::VST1d8Qwb_fixed: 3110 case ARM::VST1d16Qwb_fixed: 3111 case ARM::VST1d32Qwb_fixed: 3112 case ARM::VST1d64Qwb_fixed: 3113 case ARM::VST2d8wb_fixed: 3114 case ARM::VST2d16wb_fixed: 3115 case ARM::VST2d32wb_fixed: 3116 case ARM::VST2q8wb_fixed: 3117 case ARM::VST2q16wb_fixed: 3118 case ARM::VST2q32wb_fixed: 3119 case ARM::VST2b8wb_fixed: 3120 case ARM::VST2b16wb_fixed: 3121 case ARM::VST2b32wb_fixed: 3122 break; 3123 } 3124 3125 // First input register 3126 switch (Inst.getOpcode()) { 3127 case ARM::VST1q16: 3128 case ARM::VST1q32: 3129 case ARM::VST1q64: 3130 case ARM::VST1q8: 3131 case ARM::VST1q16wb_fixed: 3132 case ARM::VST1q16wb_register: 3133 case ARM::VST1q32wb_fixed: 3134 case ARM::VST1q32wb_register: 3135 case ARM::VST1q64wb_fixed: 3136 case ARM::VST1q64wb_register: 3137 case ARM::VST1q8wb_fixed: 3138 case ARM::VST1q8wb_register: 3139 case ARM::VST2d16: 3140 case ARM::VST2d32: 3141 case ARM::VST2d8: 3142 case ARM::VST2d16wb_fixed: 3143 case ARM::VST2d16wb_register: 3144 case ARM::VST2d32wb_fixed: 3145 case ARM::VST2d32wb_register: 3146 case ARM::VST2d8wb_fixed: 3147 case ARM::VST2d8wb_register: 3148 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3149 return MCDisassembler::Fail; 3150 break; 3151 case ARM::VST2b16: 3152 case ARM::VST2b32: 3153 case ARM::VST2b8: 3154 case ARM::VST2b16wb_fixed: 3155 case ARM::VST2b16wb_register: 3156 case ARM::VST2b32wb_fixed: 3157 case ARM::VST2b32wb_register: 3158 case ARM::VST2b8wb_fixed: 3159 case ARM::VST2b8wb_register: 3160 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3161 return MCDisassembler::Fail; 3162 break; 3163 default: 3164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3165 return MCDisassembler::Fail; 3166 } 3167 3168 // Second input register 3169 switch (Inst.getOpcode()) { 3170 case ARM::VST3d8: 3171 case ARM::VST3d16: 3172 case ARM::VST3d32: 3173 case ARM::VST3d8_UPD: 3174 case ARM::VST3d16_UPD: 3175 case ARM::VST3d32_UPD: 3176 case ARM::VST4d8: 3177 case ARM::VST4d16: 3178 case ARM::VST4d32: 3179 case ARM::VST4d8_UPD: 3180 case ARM::VST4d16_UPD: 3181 case ARM::VST4d32_UPD: 3182 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3183 return MCDisassembler::Fail; 3184 break; 3185 case ARM::VST3q8: 3186 case ARM::VST3q16: 3187 case ARM::VST3q32: 3188 case ARM::VST3q8_UPD: 3189 case ARM::VST3q16_UPD: 3190 case ARM::VST3q32_UPD: 3191 case ARM::VST4q8: 3192 case ARM::VST4q16: 3193 case ARM::VST4q32: 3194 case ARM::VST4q8_UPD: 3195 case ARM::VST4q16_UPD: 3196 case ARM::VST4q32_UPD: 3197 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 break; 3200 default: 3201 break; 3202 } 3203 3204 // Third input register 3205 switch (Inst.getOpcode()) { 3206 case ARM::VST3d8: 3207 case ARM::VST3d16: 3208 case ARM::VST3d32: 3209 case ARM::VST3d8_UPD: 3210 case ARM::VST3d16_UPD: 3211 case ARM::VST3d32_UPD: 3212 case ARM::VST4d8: 3213 case ARM::VST4d16: 3214 case ARM::VST4d32: 3215 case ARM::VST4d8_UPD: 3216 case ARM::VST4d16_UPD: 3217 case ARM::VST4d32_UPD: 3218 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3219 return MCDisassembler::Fail; 3220 break; 3221 case ARM::VST3q8: 3222 case ARM::VST3q16: 3223 case ARM::VST3q32: 3224 case ARM::VST3q8_UPD: 3225 case ARM::VST3q16_UPD: 3226 case ARM::VST3q32_UPD: 3227 case ARM::VST4q8: 3228 case ARM::VST4q16: 3229 case ARM::VST4q32: 3230 case ARM::VST4q8_UPD: 3231 case ARM::VST4q16_UPD: 3232 case ARM::VST4q32_UPD: 3233 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3234 return MCDisassembler::Fail; 3235 break; 3236 default: 3237 break; 3238 } 3239 3240 // Fourth input register 3241 switch (Inst.getOpcode()) { 3242 case ARM::VST4d8: 3243 case ARM::VST4d16: 3244 case ARM::VST4d32: 3245 case ARM::VST4d8_UPD: 3246 case ARM::VST4d16_UPD: 3247 case ARM::VST4d32_UPD: 3248 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3249 return MCDisassembler::Fail; 3250 break; 3251 case ARM::VST4q8: 3252 case ARM::VST4q16: 3253 case ARM::VST4q32: 3254 case ARM::VST4q8_UPD: 3255 case ARM::VST4q16_UPD: 3256 case ARM::VST4q32_UPD: 3257 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3258 return MCDisassembler::Fail; 3259 break; 3260 default: 3261 break; 3262 } 3263 3264 return S; 3265 } 3266 3267 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3268 uint64_t Address, const void *Decoder) { 3269 DecodeStatus S = MCDisassembler::Success; 3270 3271 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3272 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3273 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3274 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3275 unsigned align = fieldFromInstruction(Insn, 4, 1); 3276 unsigned size = fieldFromInstruction(Insn, 6, 2); 3277 3278 if (size == 0 && align == 1) 3279 return MCDisassembler::Fail; 3280 align *= (1 << size); 3281 3282 switch (Inst.getOpcode()) { 3283 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3284 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3285 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3286 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3287 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3288 return MCDisassembler::Fail; 3289 break; 3290 default: 3291 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3292 return MCDisassembler::Fail; 3293 break; 3294 } 3295 if (Rm != 0xF) { 3296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3297 return MCDisassembler::Fail; 3298 } 3299 3300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3301 return MCDisassembler::Fail; 3302 Inst.addOperand(MCOperand::createImm(align)); 3303 3304 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3305 // variant encodes Rm == 0xf. Anything else is a register offset post- 3306 // increment and we need to add the register operand to the instruction. 3307 if (Rm != 0xD && Rm != 0xF && 3308 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3309 return MCDisassembler::Fail; 3310 3311 return S; 3312 } 3313 3314 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3315 uint64_t Address, const void *Decoder) { 3316 DecodeStatus S = MCDisassembler::Success; 3317 3318 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3319 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3320 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3321 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3322 unsigned align = fieldFromInstruction(Insn, 4, 1); 3323 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3324 align *= 2*size; 3325 3326 switch (Inst.getOpcode()) { 3327 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3328 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3329 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3330 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3331 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 break; 3334 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3335 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3336 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3337 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3338 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 break; 3341 default: 3342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3343 return MCDisassembler::Fail; 3344 break; 3345 } 3346 3347 if (Rm != 0xF) 3348 Inst.addOperand(MCOperand::createImm(0)); 3349 3350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3351 return MCDisassembler::Fail; 3352 Inst.addOperand(MCOperand::createImm(align)); 3353 3354 if (Rm != 0xD && Rm != 0xF) { 3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3356 return MCDisassembler::Fail; 3357 } 3358 3359 return S; 3360 } 3361 3362 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3363 uint64_t Address, const void *Decoder) { 3364 DecodeStatus S = MCDisassembler::Success; 3365 3366 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3367 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3368 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3369 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3370 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3371 3372 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3373 return MCDisassembler::Fail; 3374 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3377 return MCDisassembler::Fail; 3378 if (Rm != 0xF) { 3379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3380 return MCDisassembler::Fail; 3381 } 3382 3383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3384 return MCDisassembler::Fail; 3385 Inst.addOperand(MCOperand::createImm(0)); 3386 3387 if (Rm == 0xD) 3388 Inst.addOperand(MCOperand::createReg(0)); 3389 else if (Rm != 0xF) { 3390 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3391 return MCDisassembler::Fail; 3392 } 3393 3394 return S; 3395 } 3396 3397 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3398 uint64_t Address, const void *Decoder) { 3399 DecodeStatus S = MCDisassembler::Success; 3400 3401 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3402 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3403 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3404 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3405 unsigned size = fieldFromInstruction(Insn, 6, 2); 3406 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3407 unsigned align = fieldFromInstruction(Insn, 4, 1); 3408 3409 if (size == 0x3) { 3410 if (align == 0) 3411 return MCDisassembler::Fail; 3412 align = 16; 3413 } else { 3414 if (size == 2) { 3415 align *= 8; 3416 } else { 3417 size = 1 << size; 3418 align *= 4*size; 3419 } 3420 } 3421 3422 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3425 return MCDisassembler::Fail; 3426 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3427 return MCDisassembler::Fail; 3428 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3429 return MCDisassembler::Fail; 3430 if (Rm != 0xF) { 3431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3432 return MCDisassembler::Fail; 3433 } 3434 3435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3436 return MCDisassembler::Fail; 3437 Inst.addOperand(MCOperand::createImm(align)); 3438 3439 if (Rm == 0xD) 3440 Inst.addOperand(MCOperand::createReg(0)); 3441 else if (Rm != 0xF) { 3442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3443 return MCDisassembler::Fail; 3444 } 3445 3446 return S; 3447 } 3448 3449 static DecodeStatus 3450 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3451 uint64_t Address, const void *Decoder) { 3452 DecodeStatus S = MCDisassembler::Success; 3453 3454 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3455 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3456 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3457 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3458 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3459 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3460 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3461 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3462 3463 if (Q) { 3464 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3465 return MCDisassembler::Fail; 3466 } else { 3467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 } 3470 3471 Inst.addOperand(MCOperand::createImm(imm)); 3472 3473 switch (Inst.getOpcode()) { 3474 case ARM::VORRiv4i16: 3475 case ARM::VORRiv2i32: 3476 case ARM::VBICiv4i16: 3477 case ARM::VBICiv2i32: 3478 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3479 return MCDisassembler::Fail; 3480 break; 3481 case ARM::VORRiv8i16: 3482 case ARM::VORRiv4i32: 3483 case ARM::VBICiv8i16: 3484 case ARM::VBICiv4i32: 3485 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3486 return MCDisassembler::Fail; 3487 break; 3488 default: 3489 break; 3490 } 3491 3492 return S; 3493 } 3494 3495 static DecodeStatus 3496 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3497 uint64_t Address, const void *Decoder) { 3498 DecodeStatus S = MCDisassembler::Success; 3499 3500 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3501 fieldFromInstruction(Insn, 13, 3)); 3502 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3503 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3504 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3505 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3506 imm |= cmode << 8; 3507 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3508 3509 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3510 return MCDisassembler::Fail; 3511 3512 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3513 return MCDisassembler::Fail; 3514 3515 Inst.addOperand(MCOperand::createImm(imm)); 3516 3517 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3518 Inst.addOperand(MCOperand::createReg(0)); 3519 Inst.addOperand(MCOperand::createImm(0)); 3520 3521 return S; 3522 } 3523 3524 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3525 uint64_t Address, const void *Decoder) { 3526 DecodeStatus S = MCDisassembler::Success; 3527 3528 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3529 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3530 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3531 return MCDisassembler::Fail; 3532 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3533 3534 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3535 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3536 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3537 return MCDisassembler::Fail; 3538 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3539 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3540 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3543 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3544 Inst.addOperand(MCOperand::createImm(Qd)); 3545 3546 return S; 3547 } 3548 3549 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3550 uint64_t Address, const void *Decoder) { 3551 DecodeStatus S = MCDisassembler::Success; 3552 3553 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3554 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3555 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3556 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3557 unsigned size = fieldFromInstruction(Insn, 18, 2); 3558 3559 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3560 return MCDisassembler::Fail; 3561 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3562 return MCDisassembler::Fail; 3563 Inst.addOperand(MCOperand::createImm(8 << size)); 3564 3565 return S; 3566 } 3567 3568 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3569 uint64_t Address, const void *Decoder) { 3570 Inst.addOperand(MCOperand::createImm(8 - Val)); 3571 return MCDisassembler::Success; 3572 } 3573 3574 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3575 uint64_t Address, const void *Decoder) { 3576 Inst.addOperand(MCOperand::createImm(16 - Val)); 3577 return MCDisassembler::Success; 3578 } 3579 3580 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3581 uint64_t Address, const void *Decoder) { 3582 Inst.addOperand(MCOperand::createImm(32 - Val)); 3583 return MCDisassembler::Success; 3584 } 3585 3586 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3587 uint64_t Address, const void *Decoder) { 3588 Inst.addOperand(MCOperand::createImm(64 - Val)); 3589 return MCDisassembler::Success; 3590 } 3591 3592 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3593 uint64_t Address, const void *Decoder) { 3594 DecodeStatus S = MCDisassembler::Success; 3595 3596 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3597 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3598 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3599 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3600 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3601 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3602 unsigned op = fieldFromInstruction(Insn, 6, 1); 3603 3604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3605 return MCDisassembler::Fail; 3606 if (op) { 3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3608 return MCDisassembler::Fail; // Writeback 3609 } 3610 3611 switch (Inst.getOpcode()) { 3612 case ARM::VTBL2: 3613 case ARM::VTBX2: 3614 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3615 return MCDisassembler::Fail; 3616 break; 3617 default: 3618 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 } 3621 3622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3623 return MCDisassembler::Fail; 3624 3625 return S; 3626 } 3627 3628 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3629 uint64_t Address, const void *Decoder) { 3630 DecodeStatus S = MCDisassembler::Success; 3631 3632 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3633 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3634 3635 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3636 return MCDisassembler::Fail; 3637 3638 switch(Inst.getOpcode()) { 3639 default: 3640 return MCDisassembler::Fail; 3641 case ARM::tADR: 3642 break; // tADR does not explicitly represent the PC as an operand. 3643 case ARM::tADDrSPi: 3644 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3645 break; 3646 } 3647 3648 Inst.addOperand(MCOperand::createImm(imm)); 3649 return S; 3650 } 3651 3652 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3653 uint64_t Address, const void *Decoder) { 3654 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3655 true, 2, Inst, Decoder)) 3656 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3657 return MCDisassembler::Success; 3658 } 3659 3660 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3661 uint64_t Address, const void *Decoder) { 3662 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3663 true, 4, Inst, Decoder)) 3664 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3665 return MCDisassembler::Success; 3666 } 3667 3668 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3669 uint64_t Address, const void *Decoder) { 3670 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3671 true, 2, Inst, Decoder)) 3672 Inst.addOperand(MCOperand::createImm(Val << 1)); 3673 return MCDisassembler::Success; 3674 } 3675 3676 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3677 uint64_t Address, const void *Decoder) { 3678 DecodeStatus S = MCDisassembler::Success; 3679 3680 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3681 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3682 3683 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3684 return MCDisassembler::Fail; 3685 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3686 return MCDisassembler::Fail; 3687 3688 return S; 3689 } 3690 3691 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3692 uint64_t Address, const void *Decoder) { 3693 DecodeStatus S = MCDisassembler::Success; 3694 3695 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3696 unsigned imm = fieldFromInstruction(Val, 3, 5); 3697 3698 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3699 return MCDisassembler::Fail; 3700 Inst.addOperand(MCOperand::createImm(imm)); 3701 3702 return S; 3703 } 3704 3705 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3706 uint64_t Address, const void *Decoder) { 3707 unsigned imm = Val << 2; 3708 3709 Inst.addOperand(MCOperand::createImm(imm)); 3710 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3711 3712 return MCDisassembler::Success; 3713 } 3714 3715 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3716 uint64_t Address, const void *Decoder) { 3717 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3718 Inst.addOperand(MCOperand::createImm(Val)); 3719 3720 return MCDisassembler::Success; 3721 } 3722 3723 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3724 uint64_t Address, const void *Decoder) { 3725 DecodeStatus S = MCDisassembler::Success; 3726 3727 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3728 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3729 unsigned imm = fieldFromInstruction(Val, 0, 2); 3730 3731 // Thumb stores cannot use PC as dest register. 3732 switch (Inst.getOpcode()) { 3733 case ARM::t2STRHs: 3734 case ARM::t2STRBs: 3735 case ARM::t2STRs: 3736 if (Rn == 15) 3737 return MCDisassembler::Fail; 3738 break; 3739 default: 3740 break; 3741 } 3742 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3746 return MCDisassembler::Fail; 3747 Inst.addOperand(MCOperand::createImm(imm)); 3748 3749 return S; 3750 } 3751 3752 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3753 uint64_t Address, const void *Decoder) { 3754 DecodeStatus S = MCDisassembler::Success; 3755 3756 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3757 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3758 3759 const FeatureBitset &featureBits = 3760 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3761 3762 bool hasMP = featureBits[ARM::FeatureMP]; 3763 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3764 3765 if (Rn == 15) { 3766 switch (Inst.getOpcode()) { 3767 case ARM::t2LDRBs: 3768 Inst.setOpcode(ARM::t2LDRBpci); 3769 break; 3770 case ARM::t2LDRHs: 3771 Inst.setOpcode(ARM::t2LDRHpci); 3772 break; 3773 case ARM::t2LDRSHs: 3774 Inst.setOpcode(ARM::t2LDRSHpci); 3775 break; 3776 case ARM::t2LDRSBs: 3777 Inst.setOpcode(ARM::t2LDRSBpci); 3778 break; 3779 case ARM::t2LDRs: 3780 Inst.setOpcode(ARM::t2LDRpci); 3781 break; 3782 case ARM::t2PLDs: 3783 Inst.setOpcode(ARM::t2PLDpci); 3784 break; 3785 case ARM::t2PLIs: 3786 Inst.setOpcode(ARM::t2PLIpci); 3787 break; 3788 default: 3789 return MCDisassembler::Fail; 3790 } 3791 3792 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3793 } 3794 3795 if (Rt == 15) { 3796 switch (Inst.getOpcode()) { 3797 case ARM::t2LDRSHs: 3798 return MCDisassembler::Fail; 3799 case ARM::t2LDRHs: 3800 Inst.setOpcode(ARM::t2PLDWs); 3801 break; 3802 case ARM::t2LDRSBs: 3803 Inst.setOpcode(ARM::t2PLIs); 3804 break; 3805 default: 3806 break; 3807 } 3808 } 3809 3810 switch (Inst.getOpcode()) { 3811 case ARM::t2PLDs: 3812 break; 3813 case ARM::t2PLIs: 3814 if (!hasV7Ops) 3815 return MCDisassembler::Fail; 3816 break; 3817 case ARM::t2PLDWs: 3818 if (!hasV7Ops || !hasMP) 3819 return MCDisassembler::Fail; 3820 break; 3821 default: 3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3823 return MCDisassembler::Fail; 3824 } 3825 3826 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3827 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3828 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3829 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3830 return MCDisassembler::Fail; 3831 3832 return S; 3833 } 3834 3835 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3836 uint64_t Address, const void* Decoder) { 3837 DecodeStatus S = MCDisassembler::Success; 3838 3839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3840 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3841 unsigned U = fieldFromInstruction(Insn, 9, 1); 3842 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3843 imm |= (U << 8); 3844 imm |= (Rn << 9); 3845 unsigned add = fieldFromInstruction(Insn, 9, 1); 3846 3847 const FeatureBitset &featureBits = 3848 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3849 3850 bool hasMP = featureBits[ARM::FeatureMP]; 3851 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3852 3853 if (Rn == 15) { 3854 switch (Inst.getOpcode()) { 3855 case ARM::t2LDRi8: 3856 Inst.setOpcode(ARM::t2LDRpci); 3857 break; 3858 case ARM::t2LDRBi8: 3859 Inst.setOpcode(ARM::t2LDRBpci); 3860 break; 3861 case ARM::t2LDRSBi8: 3862 Inst.setOpcode(ARM::t2LDRSBpci); 3863 break; 3864 case ARM::t2LDRHi8: 3865 Inst.setOpcode(ARM::t2LDRHpci); 3866 break; 3867 case ARM::t2LDRSHi8: 3868 Inst.setOpcode(ARM::t2LDRSHpci); 3869 break; 3870 case ARM::t2PLDi8: 3871 Inst.setOpcode(ARM::t2PLDpci); 3872 break; 3873 case ARM::t2PLIi8: 3874 Inst.setOpcode(ARM::t2PLIpci); 3875 break; 3876 default: 3877 return MCDisassembler::Fail; 3878 } 3879 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3880 } 3881 3882 if (Rt == 15) { 3883 switch (Inst.getOpcode()) { 3884 case ARM::t2LDRSHi8: 3885 return MCDisassembler::Fail; 3886 case ARM::t2LDRHi8: 3887 if (!add) 3888 Inst.setOpcode(ARM::t2PLDWi8); 3889 break; 3890 case ARM::t2LDRSBi8: 3891 Inst.setOpcode(ARM::t2PLIi8); 3892 break; 3893 default: 3894 break; 3895 } 3896 } 3897 3898 switch (Inst.getOpcode()) { 3899 case ARM::t2PLDi8: 3900 break; 3901 case ARM::t2PLIi8: 3902 if (!hasV7Ops) 3903 return MCDisassembler::Fail; 3904 break; 3905 case ARM::t2PLDWi8: 3906 if (!hasV7Ops || !hasMP) 3907 return MCDisassembler::Fail; 3908 break; 3909 default: 3910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3911 return MCDisassembler::Fail; 3912 } 3913 3914 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3915 return MCDisassembler::Fail; 3916 return S; 3917 } 3918 3919 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3920 uint64_t Address, const void* Decoder) { 3921 DecodeStatus S = MCDisassembler::Success; 3922 3923 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3924 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3925 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3926 imm |= (Rn << 13); 3927 3928 const FeatureBitset &featureBits = 3929 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3930 3931 bool hasMP = featureBits[ARM::FeatureMP]; 3932 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3933 3934 if (Rn == 15) { 3935 switch (Inst.getOpcode()) { 3936 case ARM::t2LDRi12: 3937 Inst.setOpcode(ARM::t2LDRpci); 3938 break; 3939 case ARM::t2LDRHi12: 3940 Inst.setOpcode(ARM::t2LDRHpci); 3941 break; 3942 case ARM::t2LDRSHi12: 3943 Inst.setOpcode(ARM::t2LDRSHpci); 3944 break; 3945 case ARM::t2LDRBi12: 3946 Inst.setOpcode(ARM::t2LDRBpci); 3947 break; 3948 case ARM::t2LDRSBi12: 3949 Inst.setOpcode(ARM::t2LDRSBpci); 3950 break; 3951 case ARM::t2PLDi12: 3952 Inst.setOpcode(ARM::t2PLDpci); 3953 break; 3954 case ARM::t2PLIi12: 3955 Inst.setOpcode(ARM::t2PLIpci); 3956 break; 3957 default: 3958 return MCDisassembler::Fail; 3959 } 3960 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3961 } 3962 3963 if (Rt == 15) { 3964 switch (Inst.getOpcode()) { 3965 case ARM::t2LDRSHi12: 3966 return MCDisassembler::Fail; 3967 case ARM::t2LDRHi12: 3968 Inst.setOpcode(ARM::t2PLDWi12); 3969 break; 3970 case ARM::t2LDRSBi12: 3971 Inst.setOpcode(ARM::t2PLIi12); 3972 break; 3973 default: 3974 break; 3975 } 3976 } 3977 3978 switch (Inst.getOpcode()) { 3979 case ARM::t2PLDi12: 3980 break; 3981 case ARM::t2PLIi12: 3982 if (!hasV7Ops) 3983 return MCDisassembler::Fail; 3984 break; 3985 case ARM::t2PLDWi12: 3986 if (!hasV7Ops || !hasMP) 3987 return MCDisassembler::Fail; 3988 break; 3989 default: 3990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3991 return MCDisassembler::Fail; 3992 } 3993 3994 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 return S; 3997 } 3998 3999 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4000 uint64_t Address, const void* Decoder) { 4001 DecodeStatus S = MCDisassembler::Success; 4002 4003 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4004 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4005 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4006 imm |= (Rn << 9); 4007 4008 if (Rn == 15) { 4009 switch (Inst.getOpcode()) { 4010 case ARM::t2LDRT: 4011 Inst.setOpcode(ARM::t2LDRpci); 4012 break; 4013 case ARM::t2LDRBT: 4014 Inst.setOpcode(ARM::t2LDRBpci); 4015 break; 4016 case ARM::t2LDRHT: 4017 Inst.setOpcode(ARM::t2LDRHpci); 4018 break; 4019 case ARM::t2LDRSBT: 4020 Inst.setOpcode(ARM::t2LDRSBpci); 4021 break; 4022 case ARM::t2LDRSHT: 4023 Inst.setOpcode(ARM::t2LDRSHpci); 4024 break; 4025 default: 4026 return MCDisassembler::Fail; 4027 } 4028 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4029 } 4030 4031 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4032 return MCDisassembler::Fail; 4033 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4034 return MCDisassembler::Fail; 4035 return S; 4036 } 4037 4038 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4039 uint64_t Address, const void* Decoder) { 4040 DecodeStatus S = MCDisassembler::Success; 4041 4042 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4043 unsigned U = fieldFromInstruction(Insn, 23, 1); 4044 int imm = fieldFromInstruction(Insn, 0, 12); 4045 4046 const FeatureBitset &featureBits = 4047 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4048 4049 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4050 4051 if (Rt == 15) { 4052 switch (Inst.getOpcode()) { 4053 case ARM::t2LDRBpci: 4054 case ARM::t2LDRHpci: 4055 Inst.setOpcode(ARM::t2PLDpci); 4056 break; 4057 case ARM::t2LDRSBpci: 4058 Inst.setOpcode(ARM::t2PLIpci); 4059 break; 4060 case ARM::t2LDRSHpci: 4061 return MCDisassembler::Fail; 4062 default: 4063 break; 4064 } 4065 } 4066 4067 switch(Inst.getOpcode()) { 4068 case ARM::t2PLDpci: 4069 break; 4070 case ARM::t2PLIpci: 4071 if (!hasV7Ops) 4072 return MCDisassembler::Fail; 4073 break; 4074 default: 4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4076 return MCDisassembler::Fail; 4077 } 4078 4079 if (!U) { 4080 // Special case for #-0. 4081 if (imm == 0) 4082 imm = INT32_MIN; 4083 else 4084 imm = -imm; 4085 } 4086 Inst.addOperand(MCOperand::createImm(imm)); 4087 4088 return S; 4089 } 4090 4091 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4092 uint64_t Address, const void *Decoder) { 4093 if (Val == 0) 4094 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4095 else { 4096 int imm = Val & 0xFF; 4097 4098 if (!(Val & 0x100)) imm *= -1; 4099 Inst.addOperand(MCOperand::createImm(imm * 4)); 4100 } 4101 4102 return MCDisassembler::Success; 4103 } 4104 4105 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4106 const void *Decoder) { 4107 if (Val == 0) 4108 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4109 else { 4110 int imm = Val & 0x7F; 4111 4112 if (!(Val & 0x80)) 4113 imm *= -1; 4114 Inst.addOperand(MCOperand::createImm(imm * 4)); 4115 } 4116 4117 return MCDisassembler::Success; 4118 } 4119 4120 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4121 uint64_t Address, const void *Decoder) { 4122 DecodeStatus S = MCDisassembler::Success; 4123 4124 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4125 unsigned imm = fieldFromInstruction(Val, 0, 9); 4126 4127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4128 return MCDisassembler::Fail; 4129 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4130 return MCDisassembler::Fail; 4131 4132 return S; 4133 } 4134 4135 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4136 uint64_t Address, 4137 const void *Decoder) { 4138 DecodeStatus S = MCDisassembler::Success; 4139 4140 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4141 unsigned imm = fieldFromInstruction(Val, 0, 8); 4142 4143 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4146 return MCDisassembler::Fail; 4147 4148 return S; 4149 } 4150 4151 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4152 uint64_t Address, const void *Decoder) { 4153 DecodeStatus S = MCDisassembler::Success; 4154 4155 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4156 unsigned imm = fieldFromInstruction(Val, 0, 8); 4157 4158 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4159 return MCDisassembler::Fail; 4160 4161 Inst.addOperand(MCOperand::createImm(imm)); 4162 4163 return S; 4164 } 4165 4166 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4167 uint64_t Address, const void *Decoder) { 4168 int imm = Val & 0xFF; 4169 if (Val == 0) 4170 imm = INT32_MIN; 4171 else if (!(Val & 0x100)) 4172 imm *= -1; 4173 Inst.addOperand(MCOperand::createImm(imm)); 4174 4175 return MCDisassembler::Success; 4176 } 4177 4178 template<int shift> 4179 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4180 uint64_t Address, const void *Decoder) { 4181 int imm = Val & 0x7F; 4182 if (Val == 0) 4183 imm = INT32_MIN; 4184 else if (!(Val & 0x80)) 4185 imm *= -1; 4186 if (imm != INT32_MIN) 4187 imm *= (1U << shift); 4188 Inst.addOperand(MCOperand::createImm(imm)); 4189 4190 return MCDisassembler::Success; 4191 } 4192 4193 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4194 uint64_t Address, const void *Decoder) { 4195 DecodeStatus S = MCDisassembler::Success; 4196 4197 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4198 unsigned imm = fieldFromInstruction(Val, 0, 9); 4199 4200 // Thumb stores cannot use PC as dest register. 4201 switch (Inst.getOpcode()) { 4202 case ARM::t2STRT: 4203 case ARM::t2STRBT: 4204 case ARM::t2STRHT: 4205 case ARM::t2STRi8: 4206 case ARM::t2STRHi8: 4207 case ARM::t2STRBi8: 4208 if (Rn == 15) 4209 return MCDisassembler::Fail; 4210 break; 4211 default: 4212 break; 4213 } 4214 4215 // Some instructions always use an additive offset. 4216 switch (Inst.getOpcode()) { 4217 case ARM::t2LDRT: 4218 case ARM::t2LDRBT: 4219 case ARM::t2LDRHT: 4220 case ARM::t2LDRSBT: 4221 case ARM::t2LDRSHT: 4222 case ARM::t2STRT: 4223 case ARM::t2STRBT: 4224 case ARM::t2STRHT: 4225 imm |= 0x100; 4226 break; 4227 default: 4228 break; 4229 } 4230 4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4232 return MCDisassembler::Fail; 4233 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4234 return MCDisassembler::Fail; 4235 4236 return S; 4237 } 4238 4239 template<int shift> 4240 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4241 uint64_t Address, 4242 const void *Decoder) { 4243 DecodeStatus S = MCDisassembler::Success; 4244 4245 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4246 unsigned imm = fieldFromInstruction(Val, 0, 8); 4247 4248 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4249 return MCDisassembler::Fail; 4250 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4251 return MCDisassembler::Fail; 4252 4253 return S; 4254 } 4255 4256 template<int shift, int WriteBack> 4257 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4258 uint64_t Address, 4259 const void *Decoder) { 4260 DecodeStatus S = MCDisassembler::Success; 4261 4262 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4263 unsigned imm = fieldFromInstruction(Val, 0, 8); 4264 if (WriteBack) { 4265 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4268 return MCDisassembler::Fail; 4269 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4270 return MCDisassembler::Fail; 4271 4272 return S; 4273 } 4274 4275 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4276 uint64_t Address, const void *Decoder) { 4277 DecodeStatus S = MCDisassembler::Success; 4278 4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4280 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4281 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4282 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4283 addr |= Rn << 9; 4284 unsigned load = fieldFromInstruction(Insn, 20, 1); 4285 4286 if (Rn == 15) { 4287 switch (Inst.getOpcode()) { 4288 case ARM::t2LDR_PRE: 4289 case ARM::t2LDR_POST: 4290 Inst.setOpcode(ARM::t2LDRpci); 4291 break; 4292 case ARM::t2LDRB_PRE: 4293 case ARM::t2LDRB_POST: 4294 Inst.setOpcode(ARM::t2LDRBpci); 4295 break; 4296 case ARM::t2LDRH_PRE: 4297 case ARM::t2LDRH_POST: 4298 Inst.setOpcode(ARM::t2LDRHpci); 4299 break; 4300 case ARM::t2LDRSB_PRE: 4301 case ARM::t2LDRSB_POST: 4302 if (Rt == 15) 4303 Inst.setOpcode(ARM::t2PLIpci); 4304 else 4305 Inst.setOpcode(ARM::t2LDRSBpci); 4306 break; 4307 case ARM::t2LDRSH_PRE: 4308 case ARM::t2LDRSH_POST: 4309 Inst.setOpcode(ARM::t2LDRSHpci); 4310 break; 4311 default: 4312 return MCDisassembler::Fail; 4313 } 4314 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4315 } 4316 4317 if (!load) { 4318 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4319 return MCDisassembler::Fail; 4320 } 4321 4322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4323 return MCDisassembler::Fail; 4324 4325 if (load) { 4326 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4327 return MCDisassembler::Fail; 4328 } 4329 4330 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4331 return MCDisassembler::Fail; 4332 4333 return S; 4334 } 4335 4336 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4337 uint64_t Address, const void *Decoder) { 4338 DecodeStatus S = MCDisassembler::Success; 4339 4340 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4341 unsigned imm = fieldFromInstruction(Val, 0, 12); 4342 4343 // Thumb stores cannot use PC as dest register. 4344 switch (Inst.getOpcode()) { 4345 case ARM::t2STRi12: 4346 case ARM::t2STRBi12: 4347 case ARM::t2STRHi12: 4348 if (Rn == 15) 4349 return MCDisassembler::Fail; 4350 break; 4351 default: 4352 break; 4353 } 4354 4355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4356 return MCDisassembler::Fail; 4357 Inst.addOperand(MCOperand::createImm(imm)); 4358 4359 return S; 4360 } 4361 4362 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4363 uint64_t Address, const void *Decoder) { 4364 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4365 4366 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4367 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4368 Inst.addOperand(MCOperand::createImm(imm)); 4369 4370 return MCDisassembler::Success; 4371 } 4372 4373 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4374 uint64_t Address, const void *Decoder) { 4375 DecodeStatus S = MCDisassembler::Success; 4376 4377 if (Inst.getOpcode() == ARM::tADDrSP) { 4378 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4379 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4380 4381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4382 return MCDisassembler::Fail; 4383 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 } else if (Inst.getOpcode() == ARM::tADDspr) { 4387 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4388 4389 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4390 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4392 return MCDisassembler::Fail; 4393 } 4394 4395 return S; 4396 } 4397 4398 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4399 uint64_t Address, const void *Decoder) { 4400 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4401 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4402 4403 Inst.addOperand(MCOperand::createImm(imod)); 4404 Inst.addOperand(MCOperand::createImm(flags)); 4405 4406 return MCDisassembler::Success; 4407 } 4408 4409 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4410 uint64_t Address, const void *Decoder) { 4411 DecodeStatus S = MCDisassembler::Success; 4412 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4413 unsigned add = fieldFromInstruction(Insn, 4, 1); 4414 4415 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4416 return MCDisassembler::Fail; 4417 Inst.addOperand(MCOperand::createImm(add)); 4418 4419 return S; 4420 } 4421 4422 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4423 uint64_t Address, const void *Decoder) { 4424 DecodeStatus S = MCDisassembler::Success; 4425 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4426 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4427 4428 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4429 return MCDisassembler::Fail; 4430 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4431 return MCDisassembler::Fail; 4432 4433 return S; 4434 } 4435 4436 template<int shift> 4437 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4438 uint64_t Address, const void *Decoder) { 4439 DecodeStatus S = MCDisassembler::Success; 4440 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4441 int imm = fieldFromInstruction(Insn, 0, 7); 4442 4443 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4444 return MCDisassembler::Fail; 4445 4446 if(!fieldFromInstruction(Insn, 7, 1)) { 4447 if (imm == 0) 4448 imm = INT32_MIN; // indicate -0 4449 else 4450 imm *= -1; 4451 } 4452 if (imm != INT32_MIN) 4453 imm *= (1U << shift); 4454 Inst.addOperand(MCOperand::createImm(imm)); 4455 4456 return S; 4457 } 4458 4459 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4460 uint64_t Address, const void *Decoder) { 4461 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4462 // Note only one trailing zero not two. Also the J1 and J2 values are from 4463 // the encoded instruction. So here change to I1 and I2 values via: 4464 // I1 = NOT(J1 EOR S); 4465 // I2 = NOT(J2 EOR S); 4466 // and build the imm32 with two trailing zeros as documented: 4467 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4468 unsigned S = (Val >> 23) & 1; 4469 unsigned J1 = (Val >> 22) & 1; 4470 unsigned J2 = (Val >> 21) & 1; 4471 unsigned I1 = !(J1 ^ S); 4472 unsigned I2 = !(J2 ^ S); 4473 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4474 int imm32 = SignExtend32<25>(tmp << 1); 4475 4476 if (!tryAddingSymbolicOperand(Address, 4477 (Address & ~2u) + imm32 + 4, 4478 true, 4, Inst, Decoder)) 4479 Inst.addOperand(MCOperand::createImm(imm32)); 4480 return MCDisassembler::Success; 4481 } 4482 4483 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4484 uint64_t Address, const void *Decoder) { 4485 if (Val == 0xA || Val == 0xB) 4486 return MCDisassembler::Fail; 4487 4488 const FeatureBitset &featureBits = 4489 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4490 4491 if (!isValidCoprocessorNumber(Val, featureBits)) 4492 return MCDisassembler::Fail; 4493 4494 Inst.addOperand(MCOperand::createImm(Val)); 4495 return MCDisassembler::Success; 4496 } 4497 4498 static DecodeStatus 4499 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4500 uint64_t Address, const void *Decoder) { 4501 DecodeStatus S = MCDisassembler::Success; 4502 4503 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4504 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4505 4506 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 4507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4510 return MCDisassembler::Fail; 4511 return S; 4512 } 4513 4514 static DecodeStatus 4515 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4516 uint64_t Address, const void *Decoder) { 4517 DecodeStatus S = MCDisassembler::Success; 4518 4519 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4520 if (pred == 0xE || pred == 0xF) { 4521 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4522 switch (opc) { 4523 default: 4524 return MCDisassembler::Fail; 4525 case 0xf3bf8f4: 4526 Inst.setOpcode(ARM::t2DSB); 4527 break; 4528 case 0xf3bf8f5: 4529 Inst.setOpcode(ARM::t2DMB); 4530 break; 4531 case 0xf3bf8f6: 4532 Inst.setOpcode(ARM::t2ISB); 4533 break; 4534 } 4535 4536 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4537 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4538 } 4539 4540 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4541 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4542 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4543 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4544 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4545 4546 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4547 return MCDisassembler::Fail; 4548 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4549 return MCDisassembler::Fail; 4550 4551 return S; 4552 } 4553 4554 // Decode a shifted immediate operand. These basically consist 4555 // of an 8-bit value, and a 4-bit directive that specifies either 4556 // a splat operation or a rotation. 4557 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4558 uint64_t Address, const void *Decoder) { 4559 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4560 if (ctrl == 0) { 4561 unsigned byte = fieldFromInstruction(Val, 8, 2); 4562 unsigned imm = fieldFromInstruction(Val, 0, 8); 4563 switch (byte) { 4564 case 0: 4565 Inst.addOperand(MCOperand::createImm(imm)); 4566 break; 4567 case 1: 4568 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4569 break; 4570 case 2: 4571 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4572 break; 4573 case 3: 4574 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4575 (imm << 8) | imm)); 4576 break; 4577 } 4578 } else { 4579 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4580 unsigned rot = fieldFromInstruction(Val, 7, 5); 4581 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4582 Inst.addOperand(MCOperand::createImm(imm)); 4583 } 4584 4585 return MCDisassembler::Success; 4586 } 4587 4588 static DecodeStatus 4589 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4590 uint64_t Address, const void *Decoder) { 4591 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4592 true, 2, Inst, Decoder)) 4593 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4594 return MCDisassembler::Success; 4595 } 4596 4597 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4598 uint64_t Address, 4599 const void *Decoder) { 4600 // Val is passed in as S:J1:J2:imm10:imm11 4601 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4602 // the encoded instruction. So here change to I1 and I2 values via: 4603 // I1 = NOT(J1 EOR S); 4604 // I2 = NOT(J2 EOR S); 4605 // and build the imm32 with one trailing zero as documented: 4606 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4607 unsigned S = (Val >> 23) & 1; 4608 unsigned J1 = (Val >> 22) & 1; 4609 unsigned J2 = (Val >> 21) & 1; 4610 unsigned I1 = !(J1 ^ S); 4611 unsigned I2 = !(J2 ^ S); 4612 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4613 int imm32 = SignExtend32<25>(tmp << 1); 4614 4615 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4616 true, 4, Inst, Decoder)) 4617 Inst.addOperand(MCOperand::createImm(imm32)); 4618 return MCDisassembler::Success; 4619 } 4620 4621 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4622 uint64_t Address, const void *Decoder) { 4623 if (Val & ~0xf) 4624 return MCDisassembler::Fail; 4625 4626 Inst.addOperand(MCOperand::createImm(Val)); 4627 return MCDisassembler::Success; 4628 } 4629 4630 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4631 uint64_t Address, const void *Decoder) { 4632 if (Val & ~0xf) 4633 return MCDisassembler::Fail; 4634 4635 Inst.addOperand(MCOperand::createImm(Val)); 4636 return MCDisassembler::Success; 4637 } 4638 4639 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4640 uint64_t Address, const void *Decoder) { 4641 DecodeStatus S = MCDisassembler::Success; 4642 const FeatureBitset &FeatureBits = 4643 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4644 4645 if (FeatureBits[ARM::FeatureMClass]) { 4646 unsigned ValLow = Val & 0xff; 4647 4648 // Validate the SYSm value first. 4649 switch (ValLow) { 4650 case 0: // apsr 4651 case 1: // iapsr 4652 case 2: // eapsr 4653 case 3: // xpsr 4654 case 5: // ipsr 4655 case 6: // epsr 4656 case 7: // iepsr 4657 case 8: // msp 4658 case 9: // psp 4659 case 16: // primask 4660 case 20: // control 4661 break; 4662 case 17: // basepri 4663 case 18: // basepri_max 4664 case 19: // faultmask 4665 if (!(FeatureBits[ARM::HasV7Ops])) 4666 // Values basepri, basepri_max and faultmask are only valid for v7m. 4667 return MCDisassembler::Fail; 4668 break; 4669 case 0x8a: // msplim_ns 4670 case 0x8b: // psplim_ns 4671 case 0x91: // basepri_ns 4672 case 0x93: // faultmask_ns 4673 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4674 return MCDisassembler::Fail; 4675 LLVM_FALLTHROUGH; 4676 case 10: // msplim 4677 case 11: // psplim 4678 case 0x88: // msp_ns 4679 case 0x89: // psp_ns 4680 case 0x90: // primask_ns 4681 case 0x94: // control_ns 4682 case 0x98: // sp_ns 4683 if (!(FeatureBits[ARM::Feature8MSecExt])) 4684 return MCDisassembler::Fail; 4685 break; 4686 default: 4687 // Architecturally defined as unpredictable 4688 S = MCDisassembler::SoftFail; 4689 break; 4690 } 4691 4692 if (Inst.getOpcode() == ARM::t2MSR_M) { 4693 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4694 if (!(FeatureBits[ARM::HasV7Ops])) { 4695 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4696 // unpredictable. 4697 if (Mask != 2) 4698 S = MCDisassembler::SoftFail; 4699 } 4700 else { 4701 // The ARMv7-M architecture stores an additional 2-bit mask value in 4702 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4703 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4704 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4705 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4706 // only if the processor includes the DSP extension. 4707 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4708 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4709 S = MCDisassembler::SoftFail; 4710 } 4711 } 4712 } else { 4713 // A/R class 4714 if (Val == 0) 4715 return MCDisassembler::Fail; 4716 } 4717 Inst.addOperand(MCOperand::createImm(Val)); 4718 return S; 4719 } 4720 4721 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4722 uint64_t Address, const void *Decoder) { 4723 unsigned R = fieldFromInstruction(Val, 5, 1); 4724 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4725 4726 // The table of encodings for these banked registers comes from B9.2.3 of the 4727 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4728 // neater. So by fiat, these values are UNPREDICTABLE: 4729 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4730 return MCDisassembler::Fail; 4731 4732 Inst.addOperand(MCOperand::createImm(Val)); 4733 return MCDisassembler::Success; 4734 } 4735 4736 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4737 uint64_t Address, const void *Decoder) { 4738 DecodeStatus S = MCDisassembler::Success; 4739 4740 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4741 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4742 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4743 4744 if (Rn == 0xF) 4745 S = MCDisassembler::SoftFail; 4746 4747 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4748 return MCDisassembler::Fail; 4749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4750 return MCDisassembler::Fail; 4751 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4752 return MCDisassembler::Fail; 4753 4754 return S; 4755 } 4756 4757 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4758 uint64_t Address, 4759 const void *Decoder) { 4760 DecodeStatus S = MCDisassembler::Success; 4761 4762 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4763 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4764 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4765 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4766 4767 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4768 return MCDisassembler::Fail; 4769 4770 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4771 S = MCDisassembler::SoftFail; 4772 4773 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4774 return MCDisassembler::Fail; 4775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4776 return MCDisassembler::Fail; 4777 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4778 return MCDisassembler::Fail; 4779 4780 return S; 4781 } 4782 4783 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4784 uint64_t Address, const void *Decoder) { 4785 DecodeStatus S = MCDisassembler::Success; 4786 4787 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4788 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4789 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4790 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4791 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4792 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4793 4794 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4795 4796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4797 return MCDisassembler::Fail; 4798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4799 return MCDisassembler::Fail; 4800 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4801 return MCDisassembler::Fail; 4802 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4803 return MCDisassembler::Fail; 4804 4805 return S; 4806 } 4807 4808 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4809 uint64_t Address, const void *Decoder) { 4810 DecodeStatus S = MCDisassembler::Success; 4811 4812 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4813 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4814 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4815 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4816 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4817 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4818 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4819 4820 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4821 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4822 4823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4824 return MCDisassembler::Fail; 4825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4826 return MCDisassembler::Fail; 4827 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4828 return MCDisassembler::Fail; 4829 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4830 return MCDisassembler::Fail; 4831 4832 return S; 4833 } 4834 4835 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4836 uint64_t Address, const void *Decoder) { 4837 DecodeStatus S = MCDisassembler::Success; 4838 4839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4840 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4841 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4842 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4843 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4844 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4845 4846 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4847 4848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 4857 return S; 4858 } 4859 4860 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4861 uint64_t Address, const void *Decoder) { 4862 DecodeStatus S = MCDisassembler::Success; 4863 4864 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4865 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4866 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4867 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4868 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4870 4871 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4872 4873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4874 return MCDisassembler::Fail; 4875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4876 return MCDisassembler::Fail; 4877 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4878 return MCDisassembler::Fail; 4879 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4880 return MCDisassembler::Fail; 4881 4882 return S; 4883 } 4884 4885 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4886 uint64_t Address, const void *Decoder) { 4887 DecodeStatus S = MCDisassembler::Success; 4888 4889 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4890 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4891 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4892 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4893 unsigned size = fieldFromInstruction(Insn, 10, 2); 4894 4895 unsigned align = 0; 4896 unsigned index = 0; 4897 switch (size) { 4898 default: 4899 return MCDisassembler::Fail; 4900 case 0: 4901 if (fieldFromInstruction(Insn, 4, 1)) 4902 return MCDisassembler::Fail; // UNDEFINED 4903 index = fieldFromInstruction(Insn, 5, 3); 4904 break; 4905 case 1: 4906 if (fieldFromInstruction(Insn, 5, 1)) 4907 return MCDisassembler::Fail; // UNDEFINED 4908 index = fieldFromInstruction(Insn, 6, 2); 4909 if (fieldFromInstruction(Insn, 4, 1)) 4910 align = 2; 4911 break; 4912 case 2: 4913 if (fieldFromInstruction(Insn, 6, 1)) 4914 return MCDisassembler::Fail; // UNDEFINED 4915 index = fieldFromInstruction(Insn, 7, 1); 4916 4917 switch (fieldFromInstruction(Insn, 4, 2)) { 4918 case 0 : 4919 align = 0; break; 4920 case 3: 4921 align = 4; break; 4922 default: 4923 return MCDisassembler::Fail; 4924 } 4925 break; 4926 } 4927 4928 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4929 return MCDisassembler::Fail; 4930 if (Rm != 0xF) { // Writeback 4931 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4932 return MCDisassembler::Fail; 4933 } 4934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4935 return MCDisassembler::Fail; 4936 Inst.addOperand(MCOperand::createImm(align)); 4937 if (Rm != 0xF) { 4938 if (Rm != 0xD) { 4939 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4940 return MCDisassembler::Fail; 4941 } else 4942 Inst.addOperand(MCOperand::createReg(0)); 4943 } 4944 4945 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4946 return MCDisassembler::Fail; 4947 Inst.addOperand(MCOperand::createImm(index)); 4948 4949 return S; 4950 } 4951 4952 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4953 uint64_t Address, const void *Decoder) { 4954 DecodeStatus S = MCDisassembler::Success; 4955 4956 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4957 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4958 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4959 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4960 unsigned size = fieldFromInstruction(Insn, 10, 2); 4961 4962 unsigned align = 0; 4963 unsigned index = 0; 4964 switch (size) { 4965 default: 4966 return MCDisassembler::Fail; 4967 case 0: 4968 if (fieldFromInstruction(Insn, 4, 1)) 4969 return MCDisassembler::Fail; // UNDEFINED 4970 index = fieldFromInstruction(Insn, 5, 3); 4971 break; 4972 case 1: 4973 if (fieldFromInstruction(Insn, 5, 1)) 4974 return MCDisassembler::Fail; // UNDEFINED 4975 index = fieldFromInstruction(Insn, 6, 2); 4976 if (fieldFromInstruction(Insn, 4, 1)) 4977 align = 2; 4978 break; 4979 case 2: 4980 if (fieldFromInstruction(Insn, 6, 1)) 4981 return MCDisassembler::Fail; // UNDEFINED 4982 index = fieldFromInstruction(Insn, 7, 1); 4983 4984 switch (fieldFromInstruction(Insn, 4, 2)) { 4985 case 0: 4986 align = 0; break; 4987 case 3: 4988 align = 4; break; 4989 default: 4990 return MCDisassembler::Fail; 4991 } 4992 break; 4993 } 4994 4995 if (Rm != 0xF) { // Writeback 4996 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 } 4999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5000 return MCDisassembler::Fail; 5001 Inst.addOperand(MCOperand::createImm(align)); 5002 if (Rm != 0xF) { 5003 if (Rm != 0xD) { 5004 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5005 return MCDisassembler::Fail; 5006 } else 5007 Inst.addOperand(MCOperand::createReg(0)); 5008 } 5009 5010 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5011 return MCDisassembler::Fail; 5012 Inst.addOperand(MCOperand::createImm(index)); 5013 5014 return S; 5015 } 5016 5017 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5018 uint64_t Address, const void *Decoder) { 5019 DecodeStatus S = MCDisassembler::Success; 5020 5021 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5022 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5023 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5024 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5025 unsigned size = fieldFromInstruction(Insn, 10, 2); 5026 5027 unsigned align = 0; 5028 unsigned index = 0; 5029 unsigned inc = 1; 5030 switch (size) { 5031 default: 5032 return MCDisassembler::Fail; 5033 case 0: 5034 index = fieldFromInstruction(Insn, 5, 3); 5035 if (fieldFromInstruction(Insn, 4, 1)) 5036 align = 2; 5037 break; 5038 case 1: 5039 index = fieldFromInstruction(Insn, 6, 2); 5040 if (fieldFromInstruction(Insn, 4, 1)) 5041 align = 4; 5042 if (fieldFromInstruction(Insn, 5, 1)) 5043 inc = 2; 5044 break; 5045 case 2: 5046 if (fieldFromInstruction(Insn, 5, 1)) 5047 return MCDisassembler::Fail; // UNDEFINED 5048 index = fieldFromInstruction(Insn, 7, 1); 5049 if (fieldFromInstruction(Insn, 4, 1) != 0) 5050 align = 8; 5051 if (fieldFromInstruction(Insn, 6, 1)) 5052 inc = 2; 5053 break; 5054 } 5055 5056 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5057 return MCDisassembler::Fail; 5058 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5059 return MCDisassembler::Fail; 5060 if (Rm != 0xF) { // Writeback 5061 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5062 return MCDisassembler::Fail; 5063 } 5064 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5065 return MCDisassembler::Fail; 5066 Inst.addOperand(MCOperand::createImm(align)); 5067 if (Rm != 0xF) { 5068 if (Rm != 0xD) { 5069 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5070 return MCDisassembler::Fail; 5071 } else 5072 Inst.addOperand(MCOperand::createReg(0)); 5073 } 5074 5075 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5076 return MCDisassembler::Fail; 5077 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5078 return MCDisassembler::Fail; 5079 Inst.addOperand(MCOperand::createImm(index)); 5080 5081 return S; 5082 } 5083 5084 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5085 uint64_t Address, const void *Decoder) { 5086 DecodeStatus S = MCDisassembler::Success; 5087 5088 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5089 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5090 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5091 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5092 unsigned size = fieldFromInstruction(Insn, 10, 2); 5093 5094 unsigned align = 0; 5095 unsigned index = 0; 5096 unsigned inc = 1; 5097 switch (size) { 5098 default: 5099 return MCDisassembler::Fail; 5100 case 0: 5101 index = fieldFromInstruction(Insn, 5, 3); 5102 if (fieldFromInstruction(Insn, 4, 1)) 5103 align = 2; 5104 break; 5105 case 1: 5106 index = fieldFromInstruction(Insn, 6, 2); 5107 if (fieldFromInstruction(Insn, 4, 1)) 5108 align = 4; 5109 if (fieldFromInstruction(Insn, 5, 1)) 5110 inc = 2; 5111 break; 5112 case 2: 5113 if (fieldFromInstruction(Insn, 5, 1)) 5114 return MCDisassembler::Fail; // UNDEFINED 5115 index = fieldFromInstruction(Insn, 7, 1); 5116 if (fieldFromInstruction(Insn, 4, 1) != 0) 5117 align = 8; 5118 if (fieldFromInstruction(Insn, 6, 1)) 5119 inc = 2; 5120 break; 5121 } 5122 5123 if (Rm != 0xF) { // Writeback 5124 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5125 return MCDisassembler::Fail; 5126 } 5127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5128 return MCDisassembler::Fail; 5129 Inst.addOperand(MCOperand::createImm(align)); 5130 if (Rm != 0xF) { 5131 if (Rm != 0xD) { 5132 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 } else 5135 Inst.addOperand(MCOperand::createReg(0)); 5136 } 5137 5138 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5139 return MCDisassembler::Fail; 5140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5141 return MCDisassembler::Fail; 5142 Inst.addOperand(MCOperand::createImm(index)); 5143 5144 return S; 5145 } 5146 5147 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5148 uint64_t Address, const void *Decoder) { 5149 DecodeStatus S = MCDisassembler::Success; 5150 5151 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5152 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5153 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5154 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5155 unsigned size = fieldFromInstruction(Insn, 10, 2); 5156 5157 unsigned align = 0; 5158 unsigned index = 0; 5159 unsigned inc = 1; 5160 switch (size) { 5161 default: 5162 return MCDisassembler::Fail; 5163 case 0: 5164 if (fieldFromInstruction(Insn, 4, 1)) 5165 return MCDisassembler::Fail; // UNDEFINED 5166 index = fieldFromInstruction(Insn, 5, 3); 5167 break; 5168 case 1: 5169 if (fieldFromInstruction(Insn, 4, 1)) 5170 return MCDisassembler::Fail; // UNDEFINED 5171 index = fieldFromInstruction(Insn, 6, 2); 5172 if (fieldFromInstruction(Insn, 5, 1)) 5173 inc = 2; 5174 break; 5175 case 2: 5176 if (fieldFromInstruction(Insn, 4, 2)) 5177 return MCDisassembler::Fail; // UNDEFINED 5178 index = fieldFromInstruction(Insn, 7, 1); 5179 if (fieldFromInstruction(Insn, 6, 1)) 5180 inc = 2; 5181 break; 5182 } 5183 5184 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5185 return MCDisassembler::Fail; 5186 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5187 return MCDisassembler::Fail; 5188 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5189 return MCDisassembler::Fail; 5190 5191 if (Rm != 0xF) { // Writeback 5192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5193 return MCDisassembler::Fail; 5194 } 5195 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5196 return MCDisassembler::Fail; 5197 Inst.addOperand(MCOperand::createImm(align)); 5198 if (Rm != 0xF) { 5199 if (Rm != 0xD) { 5200 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5201 return MCDisassembler::Fail; 5202 } else 5203 Inst.addOperand(MCOperand::createReg(0)); 5204 } 5205 5206 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 Inst.addOperand(MCOperand::createImm(index)); 5213 5214 return S; 5215 } 5216 5217 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5218 uint64_t Address, const void *Decoder) { 5219 DecodeStatus S = MCDisassembler::Success; 5220 5221 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5222 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5223 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5224 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5225 unsigned size = fieldFromInstruction(Insn, 10, 2); 5226 5227 unsigned align = 0; 5228 unsigned index = 0; 5229 unsigned inc = 1; 5230 switch (size) { 5231 default: 5232 return MCDisassembler::Fail; 5233 case 0: 5234 if (fieldFromInstruction(Insn, 4, 1)) 5235 return MCDisassembler::Fail; // UNDEFINED 5236 index = fieldFromInstruction(Insn, 5, 3); 5237 break; 5238 case 1: 5239 if (fieldFromInstruction(Insn, 4, 1)) 5240 return MCDisassembler::Fail; // UNDEFINED 5241 index = fieldFromInstruction(Insn, 6, 2); 5242 if (fieldFromInstruction(Insn, 5, 1)) 5243 inc = 2; 5244 break; 5245 case 2: 5246 if (fieldFromInstruction(Insn, 4, 2)) 5247 return MCDisassembler::Fail; // UNDEFINED 5248 index = fieldFromInstruction(Insn, 7, 1); 5249 if (fieldFromInstruction(Insn, 6, 1)) 5250 inc = 2; 5251 break; 5252 } 5253 5254 if (Rm != 0xF) { // Writeback 5255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5256 return MCDisassembler::Fail; 5257 } 5258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5259 return MCDisassembler::Fail; 5260 Inst.addOperand(MCOperand::createImm(align)); 5261 if (Rm != 0xF) { 5262 if (Rm != 0xD) { 5263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5264 return MCDisassembler::Fail; 5265 } else 5266 Inst.addOperand(MCOperand::createReg(0)); 5267 } 5268 5269 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5270 return MCDisassembler::Fail; 5271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5272 return MCDisassembler::Fail; 5273 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5274 return MCDisassembler::Fail; 5275 Inst.addOperand(MCOperand::createImm(index)); 5276 5277 return S; 5278 } 5279 5280 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5281 uint64_t Address, const void *Decoder) { 5282 DecodeStatus S = MCDisassembler::Success; 5283 5284 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5285 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5286 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5287 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5288 unsigned size = fieldFromInstruction(Insn, 10, 2); 5289 5290 unsigned align = 0; 5291 unsigned index = 0; 5292 unsigned inc = 1; 5293 switch (size) { 5294 default: 5295 return MCDisassembler::Fail; 5296 case 0: 5297 if (fieldFromInstruction(Insn, 4, 1)) 5298 align = 4; 5299 index = fieldFromInstruction(Insn, 5, 3); 5300 break; 5301 case 1: 5302 if (fieldFromInstruction(Insn, 4, 1)) 5303 align = 8; 5304 index = fieldFromInstruction(Insn, 6, 2); 5305 if (fieldFromInstruction(Insn, 5, 1)) 5306 inc = 2; 5307 break; 5308 case 2: 5309 switch (fieldFromInstruction(Insn, 4, 2)) { 5310 case 0: 5311 align = 0; break; 5312 case 3: 5313 return MCDisassembler::Fail; 5314 default: 5315 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5316 } 5317 5318 index = fieldFromInstruction(Insn, 7, 1); 5319 if (fieldFromInstruction(Insn, 6, 1)) 5320 inc = 2; 5321 break; 5322 } 5323 5324 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5325 return MCDisassembler::Fail; 5326 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5327 return MCDisassembler::Fail; 5328 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5329 return MCDisassembler::Fail; 5330 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5331 return MCDisassembler::Fail; 5332 5333 if (Rm != 0xF) { // Writeback 5334 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5335 return MCDisassembler::Fail; 5336 } 5337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5338 return MCDisassembler::Fail; 5339 Inst.addOperand(MCOperand::createImm(align)); 5340 if (Rm != 0xF) { 5341 if (Rm != 0xD) { 5342 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5343 return MCDisassembler::Fail; 5344 } else 5345 Inst.addOperand(MCOperand::createReg(0)); 5346 } 5347 5348 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5349 return MCDisassembler::Fail; 5350 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5351 return MCDisassembler::Fail; 5352 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5353 return MCDisassembler::Fail; 5354 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5355 return MCDisassembler::Fail; 5356 Inst.addOperand(MCOperand::createImm(index)); 5357 5358 return S; 5359 } 5360 5361 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5362 uint64_t Address, const void *Decoder) { 5363 DecodeStatus S = MCDisassembler::Success; 5364 5365 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5366 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5367 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5368 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5369 unsigned size = fieldFromInstruction(Insn, 10, 2); 5370 5371 unsigned align = 0; 5372 unsigned index = 0; 5373 unsigned inc = 1; 5374 switch (size) { 5375 default: 5376 return MCDisassembler::Fail; 5377 case 0: 5378 if (fieldFromInstruction(Insn, 4, 1)) 5379 align = 4; 5380 index = fieldFromInstruction(Insn, 5, 3); 5381 break; 5382 case 1: 5383 if (fieldFromInstruction(Insn, 4, 1)) 5384 align = 8; 5385 index = fieldFromInstruction(Insn, 6, 2); 5386 if (fieldFromInstruction(Insn, 5, 1)) 5387 inc = 2; 5388 break; 5389 case 2: 5390 switch (fieldFromInstruction(Insn, 4, 2)) { 5391 case 0: 5392 align = 0; break; 5393 case 3: 5394 return MCDisassembler::Fail; 5395 default: 5396 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5397 } 5398 5399 index = fieldFromInstruction(Insn, 7, 1); 5400 if (fieldFromInstruction(Insn, 6, 1)) 5401 inc = 2; 5402 break; 5403 } 5404 5405 if (Rm != 0xF) { // Writeback 5406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5407 return MCDisassembler::Fail; 5408 } 5409 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5410 return MCDisassembler::Fail; 5411 Inst.addOperand(MCOperand::createImm(align)); 5412 if (Rm != 0xF) { 5413 if (Rm != 0xD) { 5414 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5415 return MCDisassembler::Fail; 5416 } else 5417 Inst.addOperand(MCOperand::createReg(0)); 5418 } 5419 5420 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5423 return MCDisassembler::Fail; 5424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5425 return MCDisassembler::Fail; 5426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5427 return MCDisassembler::Fail; 5428 Inst.addOperand(MCOperand::createImm(index)); 5429 5430 return S; 5431 } 5432 5433 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5434 uint64_t Address, const void *Decoder) { 5435 DecodeStatus S = MCDisassembler::Success; 5436 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5437 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5438 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5439 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5440 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5441 5442 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5443 S = MCDisassembler::SoftFail; 5444 5445 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5446 return MCDisassembler::Fail; 5447 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5448 return MCDisassembler::Fail; 5449 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5450 return MCDisassembler::Fail; 5451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5452 return MCDisassembler::Fail; 5453 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5454 return MCDisassembler::Fail; 5455 5456 return S; 5457 } 5458 5459 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5460 uint64_t Address, const void *Decoder) { 5461 DecodeStatus S = MCDisassembler::Success; 5462 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5463 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5464 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5465 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5466 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5467 5468 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5469 S = MCDisassembler::SoftFail; 5470 5471 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5472 return MCDisassembler::Fail; 5473 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5474 return MCDisassembler::Fail; 5475 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5476 return MCDisassembler::Fail; 5477 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5478 return MCDisassembler::Fail; 5479 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5480 return MCDisassembler::Fail; 5481 5482 return S; 5483 } 5484 5485 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5486 uint64_t Address, const void *Decoder) { 5487 DecodeStatus S = MCDisassembler::Success; 5488 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5489 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5490 5491 if (pred == 0xF) { 5492 pred = 0xE; 5493 S = MCDisassembler::SoftFail; 5494 } 5495 5496 if (mask == 0x0) 5497 return MCDisassembler::Fail; 5498 5499 // IT masks are encoded as a sequence of replacement low-order bits 5500 // for the condition code. So if the low bit of the starting 5501 // condition code is 1, then we have to flip all the bits above the 5502 // terminating bit (which is the lowest 1 bit). 5503 if (pred & 1) { 5504 unsigned LowBit = mask & -mask; 5505 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5506 mask ^= BitsAboveLowBit; 5507 } 5508 5509 Inst.addOperand(MCOperand::createImm(pred)); 5510 Inst.addOperand(MCOperand::createImm(mask)); 5511 return S; 5512 } 5513 5514 static DecodeStatus 5515 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5516 uint64_t Address, const void *Decoder) { 5517 DecodeStatus S = MCDisassembler::Success; 5518 5519 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5520 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5521 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5522 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5523 unsigned W = fieldFromInstruction(Insn, 21, 1); 5524 unsigned U = fieldFromInstruction(Insn, 23, 1); 5525 unsigned P = fieldFromInstruction(Insn, 24, 1); 5526 bool writeback = (W == 1) | (P == 0); 5527 5528 addr |= (U << 8) | (Rn << 9); 5529 5530 if (writeback && (Rn == Rt || Rn == Rt2)) 5531 Check(S, MCDisassembler::SoftFail); 5532 if (Rt == Rt2) 5533 Check(S, MCDisassembler::SoftFail); 5534 5535 // Rt 5536 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5537 return MCDisassembler::Fail; 5538 // Rt2 5539 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5540 return MCDisassembler::Fail; 5541 // Writeback operand 5542 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5543 return MCDisassembler::Fail; 5544 // addr 5545 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5546 return MCDisassembler::Fail; 5547 5548 return S; 5549 } 5550 5551 static DecodeStatus 5552 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5553 uint64_t Address, const void *Decoder) { 5554 DecodeStatus S = MCDisassembler::Success; 5555 5556 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5557 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5558 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5559 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5560 unsigned W = fieldFromInstruction(Insn, 21, 1); 5561 unsigned U = fieldFromInstruction(Insn, 23, 1); 5562 unsigned P = fieldFromInstruction(Insn, 24, 1); 5563 bool writeback = (W == 1) | (P == 0); 5564 5565 addr |= (U << 8) | (Rn << 9); 5566 5567 if (writeback && (Rn == Rt || Rn == Rt2)) 5568 Check(S, MCDisassembler::SoftFail); 5569 5570 // Writeback operand 5571 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5572 return MCDisassembler::Fail; 5573 // Rt 5574 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5575 return MCDisassembler::Fail; 5576 // Rt2 5577 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5578 return MCDisassembler::Fail; 5579 // addr 5580 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5581 return MCDisassembler::Fail; 5582 5583 return S; 5584 } 5585 5586 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5587 uint64_t Address, const void *Decoder) { 5588 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5589 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5590 if (sign1 != sign2) return MCDisassembler::Fail; 5591 5592 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5593 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5594 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5595 Val |= sign1 << 12; 5596 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); 5597 5598 return MCDisassembler::Success; 5599 } 5600 5601 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5602 uint64_t Address, 5603 const void *Decoder) { 5604 DecodeStatus S = MCDisassembler::Success; 5605 5606 // Shift of "asr #32" is not allowed in Thumb2 mode. 5607 if (Val == 0x20) S = MCDisassembler::Fail; 5608 Inst.addOperand(MCOperand::createImm(Val)); 5609 return S; 5610 } 5611 5612 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5613 uint64_t Address, const void *Decoder) { 5614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5615 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5616 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5617 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5618 5619 if (pred == 0xF) 5620 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5621 5622 DecodeStatus S = MCDisassembler::Success; 5623 5624 if (Rt == Rn || Rn == Rt2) 5625 S = MCDisassembler::SoftFail; 5626 5627 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5628 return MCDisassembler::Fail; 5629 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5630 return MCDisassembler::Fail; 5631 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5632 return MCDisassembler::Fail; 5633 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5634 return MCDisassembler::Fail; 5635 5636 return S; 5637 } 5638 5639 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5640 uint64_t Address, const void *Decoder) { 5641 const FeatureBitset &featureBits = 5642 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5643 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5644 5645 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5646 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5647 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5648 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5649 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5650 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5651 unsigned op = fieldFromInstruction(Insn, 5, 1); 5652 5653 DecodeStatus S = MCDisassembler::Success; 5654 5655 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5656 if (!(imm & 0x38)) { 5657 if (cmode == 0xF) { 5658 if (op == 1) return MCDisassembler::Fail; 5659 Inst.setOpcode(ARM::VMOVv2f32); 5660 } 5661 if (hasFullFP16) { 5662 if (cmode == 0xE) { 5663 if (op == 1) { 5664 Inst.setOpcode(ARM::VMOVv1i64); 5665 } else { 5666 Inst.setOpcode(ARM::VMOVv8i8); 5667 } 5668 } 5669 if (cmode == 0xD) { 5670 if (op == 1) { 5671 Inst.setOpcode(ARM::VMVNv2i32); 5672 } else { 5673 Inst.setOpcode(ARM::VMOVv2i32); 5674 } 5675 } 5676 if (cmode == 0xC) { 5677 if (op == 1) { 5678 Inst.setOpcode(ARM::VMVNv2i32); 5679 } else { 5680 Inst.setOpcode(ARM::VMOVv2i32); 5681 } 5682 } 5683 } 5684 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5685 } 5686 5687 if (!(imm & 0x20)) return MCDisassembler::Fail; 5688 5689 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5692 return MCDisassembler::Fail; 5693 Inst.addOperand(MCOperand::createImm(64 - imm)); 5694 5695 return S; 5696 } 5697 5698 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5699 uint64_t Address, const void *Decoder) { 5700 const FeatureBitset &featureBits = 5701 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5702 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5703 5704 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5705 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5706 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5707 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5708 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5709 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5710 unsigned op = fieldFromInstruction(Insn, 5, 1); 5711 5712 DecodeStatus S = MCDisassembler::Success; 5713 5714 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5715 if (!(imm & 0x38)) { 5716 if (cmode == 0xF) { 5717 if (op == 1) return MCDisassembler::Fail; 5718 Inst.setOpcode(ARM::VMOVv4f32); 5719 } 5720 if (hasFullFP16) { 5721 if (cmode == 0xE) { 5722 if (op == 1) { 5723 Inst.setOpcode(ARM::VMOVv2i64); 5724 } else { 5725 Inst.setOpcode(ARM::VMOVv16i8); 5726 } 5727 } 5728 if (cmode == 0xD) { 5729 if (op == 1) { 5730 Inst.setOpcode(ARM::VMVNv4i32); 5731 } else { 5732 Inst.setOpcode(ARM::VMOVv4i32); 5733 } 5734 } 5735 if (cmode == 0xC) { 5736 if (op == 1) { 5737 Inst.setOpcode(ARM::VMVNv4i32); 5738 } else { 5739 Inst.setOpcode(ARM::VMOVv4i32); 5740 } 5741 } 5742 } 5743 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5744 } 5745 5746 if (!(imm & 0x20)) return MCDisassembler::Fail; 5747 5748 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5749 return MCDisassembler::Fail; 5750 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5751 return MCDisassembler::Fail; 5752 Inst.addOperand(MCOperand::createImm(64 - imm)); 5753 5754 return S; 5755 } 5756 5757 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5758 unsigned Insn, 5759 uint64_t Address, 5760 const void *Decoder) { 5761 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5762 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5763 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5764 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5765 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5766 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5767 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5768 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5769 5770 DecodeStatus S = MCDisassembler::Success; 5771 5772 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5773 5774 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5775 return MCDisassembler::Fail; 5776 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5777 return MCDisassembler::Fail; 5778 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5779 return MCDisassembler::Fail; 5780 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5781 return MCDisassembler::Fail; 5782 // The lane index does not have any bits in the encoding, because it can only 5783 // be 0. 5784 Inst.addOperand(MCOperand::createImm(0)); 5785 Inst.addOperand(MCOperand::createImm(rotate)); 5786 5787 return S; 5788 } 5789 5790 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5791 uint64_t Address, const void *Decoder) { 5792 DecodeStatus S = MCDisassembler::Success; 5793 5794 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5795 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5796 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5797 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5798 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5799 5800 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5801 S = MCDisassembler::SoftFail; 5802 5803 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5804 return MCDisassembler::Fail; 5805 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5806 return MCDisassembler::Fail; 5807 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5808 return MCDisassembler::Fail; 5809 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5810 return MCDisassembler::Fail; 5811 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5812 return MCDisassembler::Fail; 5813 5814 return S; 5815 } 5816 5817 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5818 uint64_t Address, const void *Decoder) { 5819 DecodeStatus S = MCDisassembler::Success; 5820 5821 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5822 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5823 unsigned cop = fieldFromInstruction(Val, 8, 4); 5824 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5825 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5826 5827 if ((cop & ~0x1) == 0xa) 5828 return MCDisassembler::Fail; 5829 5830 if (Rt == Rt2) 5831 S = MCDisassembler::SoftFail; 5832 5833 // We have to check if the instruction is MRRC2 5834 // or MCRR2 when constructing the operands for 5835 // Inst. Reason is because MRRC2 stores to two 5836 // registers so it's tablegen desc has has two 5837 // outputs whereas MCRR doesn't store to any 5838 // registers so all of it's operands are listed 5839 // as inputs, therefore the operand order for 5840 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5841 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5842 5843 if (Inst.getOpcode() == ARM::MRRC2) { 5844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5845 return MCDisassembler::Fail; 5846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5847 return MCDisassembler::Fail; 5848 } 5849 Inst.addOperand(MCOperand::createImm(cop)); 5850 Inst.addOperand(MCOperand::createImm(opc1)); 5851 if (Inst.getOpcode() == ARM::MCRR2) { 5852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5853 return MCDisassembler::Fail; 5854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5855 return MCDisassembler::Fail; 5856 } 5857 Inst.addOperand(MCOperand::createImm(CRm)); 5858 5859 return S; 5860 } 5861 5862 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5863 uint64_t Address, 5864 const void *Decoder) { 5865 const FeatureBitset &featureBits = 5866 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5867 DecodeStatus S = MCDisassembler::Success; 5868 5869 // Add explicit operand for the destination sysreg, for cases where 5870 // we have to model it for code generation purposes. 5871 switch (Inst.getOpcode()) { 5872 case ARM::VMSR_FPSCR_NZCVQC: 5873 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5874 break; 5875 case ARM::VMSR_P0: 5876 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5877 break; 5878 } 5879 5880 if (Inst.getOpcode() != ARM::FMSTAT) { 5881 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5882 5883 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5884 if (Rt == 13 || Rt == 15) 5885 S = MCDisassembler::SoftFail; 5886 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5887 } else 5888 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5889 } 5890 5891 // Add explicit operand for the source sysreg, similarly to above. 5892 switch (Inst.getOpcode()) { 5893 case ARM::VMRS_FPSCR_NZCVQC: 5894 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5895 break; 5896 case ARM::VMRS_P0: 5897 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5898 break; 5899 } 5900 5901 if (featureBits[ARM::ModeThumb]) { 5902 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5903 Inst.addOperand(MCOperand::createReg(0)); 5904 } else { 5905 unsigned pred = fieldFromInstruction(Val, 28, 4); 5906 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5907 return MCDisassembler::Fail; 5908 } 5909 5910 return S; 5911 } 5912 5913 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5914 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5915 uint64_t Address, 5916 const void *Decoder) { 5917 DecodeStatus S = MCDisassembler::Success; 5918 if (Val == 0 && !zeroPermitted) 5919 S = MCDisassembler::Fail; 5920 5921 uint64_t DecVal; 5922 if (isSigned) 5923 DecVal = SignExtend32<size + 1>(Val << 1); 5924 else 5925 DecVal = (Val << 1); 5926 5927 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5928 Decoder)) 5929 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5930 return S; 5931 } 5932 5933 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5934 uint64_t Address, 5935 const void *Decoder) { 5936 5937 uint64_t LocImm = Inst.getOperand(0).getImm(); 5938 Val = LocImm + (2 << Val); 5939 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5940 Decoder)) 5941 Inst.addOperand(MCOperand::createImm(Val)); 5942 return MCDisassembler::Success; 5943 } 5944 5945 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5946 uint64_t Address, 5947 const void *Decoder) { 5948 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5949 return MCDisassembler::Fail; 5950 Inst.addOperand(MCOperand::createImm(Val)); 5951 return MCDisassembler::Success; 5952 } 5953 5954 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 5955 const void *Decoder) { 5956 DecodeStatus S = MCDisassembler::Success; 5957 5958 if (Inst.getOpcode() == ARM::MVE_LCTP) 5959 return S; 5960 5961 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 5962 fieldFromInstruction(Insn, 1, 10) << 1; 5963 switch (Inst.getOpcode()) { 5964 case ARM::t2LEUpdate: 5965 case ARM::MVE_LETP: 5966 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5967 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5968 LLVM_FALLTHROUGH; 5969 case ARM::t2LE: 5970 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 5971 Inst, Imm, Address, Decoder))) 5972 return MCDisassembler::Fail; 5973 break; 5974 case ARM::t2WLS: 5975 case ARM::MVE_WLSTP_8: 5976 case ARM::MVE_WLSTP_16: 5977 case ARM::MVE_WLSTP_32: 5978 case ARM::MVE_WLSTP_64: 5979 Inst.addOperand(MCOperand::createReg(ARM::LR)); 5980 if (!Check(S, 5981 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 5982 Address, Decoder)) || 5983 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 5984 Inst, Imm, Address, Decoder))) 5985 return MCDisassembler::Fail; 5986 break; 5987 case ARM::t2DLS: 5988 case ARM::MVE_DLSTP_8: 5989 case ARM::MVE_DLSTP_16: 5990 case ARM::MVE_DLSTP_32: 5991 case ARM::MVE_DLSTP_64: 5992 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5993 if (Rn == 0xF) { 5994 // Enforce all the rest of the instruction bits in LCTP, which 5995 // won't have been reliably checked based on LCTP's own tablegen 5996 // record, because we came to this decode by a roundabout route. 5997 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 5998 if ((Insn & ~SBZMask) != CanonicalLCTP) 5999 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6000 if (Insn != CanonicalLCTP) 6001 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6002 6003 Inst.setOpcode(ARM::MVE_LCTP); 6004 } else { 6005 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6006 if (!Check(S, DecoderGPRRegisterClass(Inst, 6007 fieldFromInstruction(Insn, 16, 4), 6008 Address, Decoder))) 6009 return MCDisassembler::Fail; 6010 } 6011 break; 6012 } 6013 return S; 6014 } 6015 6016 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6017 uint64_t Address, 6018 const void *Decoder) { 6019 DecodeStatus S = MCDisassembler::Success; 6020 6021 if (Val == 0) 6022 Val = 32; 6023 6024 Inst.addOperand(MCOperand::createImm(Val)); 6025 6026 return S; 6027 } 6028 6029 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6030 uint64_t Address, const void *Decoder) { 6031 if ((RegNo) + 1 > 11) 6032 return MCDisassembler::Fail; 6033 6034 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6035 Inst.addOperand(MCOperand::createReg(Register)); 6036 return MCDisassembler::Success; 6037 } 6038 6039 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6040 uint64_t Address, const void *Decoder) { 6041 if ((RegNo) > 14) 6042 return MCDisassembler::Fail; 6043 6044 unsigned Register = GPRDecoderTable[(RegNo)]; 6045 Inst.addOperand(MCOperand::createReg(Register)); 6046 return MCDisassembler::Success; 6047 } 6048 6049 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6050 const void *Decoder) { 6051 DecodeStatus S = MCDisassembler::Success; 6052 6053 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6054 Inst.addOperand(MCOperand::createReg(0)); 6055 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6056 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6057 (fieldFromInstruction(Insn, 12, 4) << 8) | 6058 (fieldFromInstruction(Insn, 22, 1) << 12); 6059 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6060 return MCDisassembler::Fail; 6061 } 6062 } else { 6063 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6064 (fieldFromInstruction(Insn, 22, 1) << 8) | 6065 (fieldFromInstruction(Insn, 12, 4) << 9); 6066 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6067 return MCDisassembler::Fail; 6068 } 6069 } 6070 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6071 6072 return S; 6073 } 6074 6075 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6076 uint64_t Address, 6077 const void *Decoder) { 6078 if (RegNo > 7) 6079 return MCDisassembler::Fail; 6080 6081 unsigned Register = QPRDecoderTable[RegNo]; 6082 Inst.addOperand(MCOperand::createReg(Register)); 6083 return MCDisassembler::Success; 6084 } 6085 6086 static const uint16_t QQPRDecoderTable[] = { 6087 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6088 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6089 }; 6090 6091 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6092 uint64_t Address, 6093 const void *Decoder) { 6094 if (RegNo > 6) 6095 return MCDisassembler::Fail; 6096 6097 unsigned Register = QQPRDecoderTable[RegNo]; 6098 Inst.addOperand(MCOperand::createReg(Register)); 6099 return MCDisassembler::Success; 6100 } 6101 6102 static const uint16_t QQQQPRDecoderTable[] = { 6103 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6104 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6105 }; 6106 6107 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6108 uint64_t Address, 6109 const void *Decoder) { 6110 if (RegNo > 4) 6111 return MCDisassembler::Fail; 6112 6113 unsigned Register = QQQQPRDecoderTable[RegNo]; 6114 Inst.addOperand(MCOperand::createReg(Register)); 6115 return MCDisassembler::Success; 6116 } 6117 6118 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6119 uint64_t Address, 6120 const void *Decoder) { 6121 DecodeStatus S = MCDisassembler::Success; 6122 6123 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6124 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6125 // 't' as 0 and finish with a 1. 6126 unsigned Imm = 0; 6127 // We always start with a 't'. 6128 unsigned CurBit = 0; 6129 for (int i = 3; i >= 0; --i) { 6130 // If the bit we are looking at is not the same as last one, invert the 6131 // CurBit, if it is the same leave it as is. 6132 CurBit ^= (Val >> i) & 1U; 6133 6134 // Encode the CurBit at the right place in the immediate. 6135 Imm |= (CurBit << i); 6136 6137 // If we are done, finish the encoding with a 1. 6138 if ((Val & ~(~0U << i)) == 0) { 6139 Imm |= 1U << i; 6140 break; 6141 } 6142 } 6143 6144 Inst.addOperand(MCOperand::createImm(Imm)); 6145 6146 return S; 6147 } 6148 6149 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6150 uint64_t Address, const void *Decoder) { 6151 // The vpred_r operand type includes an MQPR register field derived 6152 // from the encoding. But we don't actually want to add an operand 6153 // to the MCInst at this stage, because AddThumbPredicate will do it 6154 // later, and will infer the register number from the TIED_TO 6155 // constraint. So this is a deliberately empty decoder method that 6156 // will inhibit the auto-generated disassembly code from adding an 6157 // operand at all. 6158 return MCDisassembler::Success; 6159 } 6160 6161 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6162 unsigned Val, 6163 uint64_t Address, 6164 const void *Decoder) { 6165 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6166 return MCDisassembler::Success; 6167 } 6168 6169 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6170 unsigned Val, 6171 uint64_t Address, 6172 const void *Decoder) { 6173 unsigned Code; 6174 switch (Val & 0x3) { 6175 case 0: 6176 Code = ARMCC::GE; 6177 break; 6178 case 1: 6179 Code = ARMCC::LT; 6180 break; 6181 case 2: 6182 Code = ARMCC::GT; 6183 break; 6184 case 3: 6185 Code = ARMCC::LE; 6186 break; 6187 } 6188 Inst.addOperand(MCOperand::createImm(Code)); 6189 return MCDisassembler::Success; 6190 } 6191 6192 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6193 unsigned Val, 6194 uint64_t Address, 6195 const void *Decoder) { 6196 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6197 return MCDisassembler::Success; 6198 } 6199 6200 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6201 uint64_t Address, 6202 const void *Decoder) { 6203 unsigned Code; 6204 switch (Val) { 6205 default: 6206 return MCDisassembler::Fail; 6207 case 0: 6208 Code = ARMCC::EQ; 6209 break; 6210 case 1: 6211 Code = ARMCC::NE; 6212 break; 6213 case 4: 6214 Code = ARMCC::GE; 6215 break; 6216 case 5: 6217 Code = ARMCC::LT; 6218 break; 6219 case 6: 6220 Code = ARMCC::GT; 6221 break; 6222 case 7: 6223 Code = ARMCC::LE; 6224 break; 6225 } 6226 6227 Inst.addOperand(MCOperand::createImm(Code)); 6228 return MCDisassembler::Success; 6229 } 6230 6231 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6232 uint64_t Address, const void *Decoder) { 6233 DecodeStatus S = MCDisassembler::Success; 6234 6235 unsigned DecodedVal = 64 - Val; 6236 6237 switch (Inst.getOpcode()) { 6238 case ARM::MVE_VCVTf16s16_fix: 6239 case ARM::MVE_VCVTs16f16_fix: 6240 case ARM::MVE_VCVTf16u16_fix: 6241 case ARM::MVE_VCVTu16f16_fix: 6242 if (DecodedVal > 16) 6243 return MCDisassembler::Fail; 6244 break; 6245 case ARM::MVE_VCVTf32s32_fix: 6246 case ARM::MVE_VCVTs32f32_fix: 6247 case ARM::MVE_VCVTf32u32_fix: 6248 case ARM::MVE_VCVTu32f32_fix: 6249 if (DecodedVal > 32) 6250 return MCDisassembler::Fail; 6251 break; 6252 } 6253 6254 Inst.addOperand(MCOperand::createImm(64 - Val)); 6255 6256 return S; 6257 } 6258 6259 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6260 switch (Opcode) { 6261 case ARM::VSTR_P0_off: 6262 case ARM::VSTR_P0_pre: 6263 case ARM::VSTR_P0_post: 6264 case ARM::VLDR_P0_off: 6265 case ARM::VLDR_P0_pre: 6266 case ARM::VLDR_P0_post: 6267 return ARM::P0; 6268 default: 6269 return 0; 6270 } 6271 } 6272 6273 template<bool Writeback> 6274 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6275 uint64_t Address, 6276 const void *Decoder) { 6277 switch (Inst.getOpcode()) { 6278 case ARM::VSTR_FPSCR_pre: 6279 case ARM::VSTR_FPSCR_NZCVQC_pre: 6280 case ARM::VLDR_FPSCR_pre: 6281 case ARM::VLDR_FPSCR_NZCVQC_pre: 6282 case ARM::VSTR_FPSCR_off: 6283 case ARM::VSTR_FPSCR_NZCVQC_off: 6284 case ARM::VLDR_FPSCR_off: 6285 case ARM::VLDR_FPSCR_NZCVQC_off: 6286 case ARM::VSTR_FPSCR_post: 6287 case ARM::VSTR_FPSCR_NZCVQC_post: 6288 case ARM::VLDR_FPSCR_post: 6289 case ARM::VLDR_FPSCR_NZCVQC_post: 6290 const FeatureBitset &featureBits = 6291 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6292 6293 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6294 return MCDisassembler::Fail; 6295 } 6296 6297 DecodeStatus S = MCDisassembler::Success; 6298 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6299 Inst.addOperand(MCOperand::createReg(Sysreg)); 6300 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6301 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6302 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6303 6304 if (Writeback) { 6305 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6306 return MCDisassembler::Fail; 6307 } 6308 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6309 return MCDisassembler::Fail; 6310 6311 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6312 Inst.addOperand(MCOperand::createReg(0)); 6313 6314 return S; 6315 } 6316 6317 static inline DecodeStatus DecodeMVE_MEM_pre( 6318 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6319 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6320 DecodeStatus S = MCDisassembler::Success; 6321 6322 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6323 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6324 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6325 6326 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6327 return MCDisassembler::Fail; 6328 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6329 return MCDisassembler::Fail; 6330 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6331 return MCDisassembler::Fail; 6332 6333 return S; 6334 } 6335 6336 template <int shift> 6337 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6338 uint64_t Address, const void *Decoder) { 6339 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6340 fieldFromInstruction(Val, 16, 3), 6341 DecodetGPRRegisterClass, 6342 DecodeTAddrModeImm7<shift>); 6343 } 6344 6345 template <int shift> 6346 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6347 uint64_t Address, const void *Decoder) { 6348 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6349 fieldFromInstruction(Val, 16, 4), 6350 DecoderGPRRegisterClass, 6351 DecodeT2AddrModeImm7<shift,1>); 6352 } 6353 6354 template <int shift> 6355 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6356 uint64_t Address, const void *Decoder) { 6357 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6358 fieldFromInstruction(Val, 17, 3), 6359 DecodeMQPRRegisterClass, 6360 DecodeMveAddrModeQ<shift>); 6361 } 6362 6363 template<unsigned MinLog, unsigned MaxLog> 6364 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6365 uint64_t Address, 6366 const void *Decoder) { 6367 DecodeStatus S = MCDisassembler::Success; 6368 6369 if (Val < MinLog || Val > MaxLog) 6370 return MCDisassembler::Fail; 6371 6372 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6373 return S; 6374 } 6375 6376 template <int shift> 6377 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, 6378 uint64_t Address, 6379 const void *Decoder) { 6380 Val <<= shift; 6381 6382 Inst.addOperand(MCOperand::createImm(Val)); 6383 return MCDisassembler::Success; 6384 } 6385 6386 template<unsigned start> 6387 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6388 uint64_t Address, 6389 const void *Decoder) { 6390 DecodeStatus S = MCDisassembler::Success; 6391 6392 Inst.addOperand(MCOperand::createImm(start + Val)); 6393 6394 return S; 6395 } 6396 6397 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6398 uint64_t Address, const void *Decoder) { 6399 DecodeStatus S = MCDisassembler::Success; 6400 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6401 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6402 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6403 fieldFromInstruction(Insn, 13, 3)); 6404 unsigned index = fieldFromInstruction(Insn, 4, 1); 6405 6406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6407 return MCDisassembler::Fail; 6408 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6409 return MCDisassembler::Fail; 6410 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6411 return MCDisassembler::Fail; 6412 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6413 return MCDisassembler::Fail; 6414 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6415 return MCDisassembler::Fail; 6416 6417 return S; 6418 } 6419 6420 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6421 uint64_t Address, const void *Decoder) { 6422 DecodeStatus S = MCDisassembler::Success; 6423 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6424 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6425 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6426 fieldFromInstruction(Insn, 13, 3)); 6427 unsigned index = fieldFromInstruction(Insn, 4, 1); 6428 6429 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6430 return MCDisassembler::Fail; 6431 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6432 return MCDisassembler::Fail; 6433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6434 return MCDisassembler::Fail; 6435 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6436 return MCDisassembler::Fail; 6437 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6438 return MCDisassembler::Fail; 6439 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6440 return MCDisassembler::Fail; 6441 6442 return S; 6443 } 6444 6445 static DecodeStatus DecodeMVEOverlappingLongShift( 6446 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6447 DecodeStatus S = MCDisassembler::Success; 6448 6449 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6450 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6451 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6452 6453 if (RdaHi == 14) { 6454 // This value of RdaHi (really indicating pc, because RdaHi has to 6455 // be an odd-numbered register, so the low bit will be set by the 6456 // decode function below) indicates that we must decode as SQRSHR 6457 // or UQRSHL, which both have a single Rda register field with all 6458 // four bits. 6459 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6460 6461 switch (Inst.getOpcode()) { 6462 case ARM::MVE_ASRLr: 6463 case ARM::MVE_SQRSHRL: 6464 Inst.setOpcode(ARM::MVE_SQRSHR); 6465 break; 6466 case ARM::MVE_LSLLr: 6467 case ARM::MVE_UQRSHLL: 6468 Inst.setOpcode(ARM::MVE_UQRSHL); 6469 break; 6470 default: 6471 llvm_unreachable("Unexpected starting opcode!"); 6472 } 6473 6474 // Rda as output parameter 6475 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6476 return MCDisassembler::Fail; 6477 6478 // Rda again as input parameter 6479 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6480 return MCDisassembler::Fail; 6481 6482 // Rm, the amount to shift by 6483 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6484 return MCDisassembler::Fail; 6485 6486 if (fieldFromInstruction (Insn, 6, 3) != 4) 6487 return MCDisassembler::SoftFail; 6488 6489 if (Rda == Rm) 6490 return MCDisassembler::SoftFail; 6491 6492 return S; 6493 } 6494 6495 // Otherwise, we decode as whichever opcode our caller has already 6496 // put into Inst. Those all look the same: 6497 6498 // RdaLo,RdaHi as output parameters 6499 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6500 return MCDisassembler::Fail; 6501 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6502 return MCDisassembler::Fail; 6503 6504 // RdaLo,RdaHi again as input parameters 6505 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6506 return MCDisassembler::Fail; 6507 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6508 return MCDisassembler::Fail; 6509 6510 // Rm, the amount to shift by 6511 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6512 return MCDisassembler::Fail; 6513 6514 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6515 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6516 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6517 // Saturate, the bit position for saturation 6518 Inst.addOperand(MCOperand::createImm(Saturate)); 6519 } 6520 6521 return S; 6522 } 6523 6524 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6525 const void *Decoder) { 6526 DecodeStatus S = MCDisassembler::Success; 6527 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6528 fieldFromInstruction(Insn, 13, 3)); 6529 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6530 fieldFromInstruction(Insn, 1, 3)); 6531 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6532 6533 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6534 return MCDisassembler::Fail; 6535 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6536 return MCDisassembler::Fail; 6537 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6538 return MCDisassembler::Fail; 6539 6540 return S; 6541 } 6542 6543 template<bool scalar, OperandDecoder predicate_decoder> 6544 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6545 const void *Decoder) { 6546 DecodeStatus S = MCDisassembler::Success; 6547 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6548 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6549 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6550 return MCDisassembler::Fail; 6551 6552 unsigned fc; 6553 6554 if (scalar) { 6555 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6556 fieldFromInstruction(Insn, 7, 1) | 6557 fieldFromInstruction(Insn, 5, 1) << 1; 6558 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6559 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6560 return MCDisassembler::Fail; 6561 } else { 6562 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6563 fieldFromInstruction(Insn, 7, 1) | 6564 fieldFromInstruction(Insn, 0, 1) << 1; 6565 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6566 fieldFromInstruction(Insn, 1, 3); 6567 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6568 return MCDisassembler::Fail; 6569 } 6570 6571 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6572 return MCDisassembler::Fail; 6573 6574 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6575 Inst.addOperand(MCOperand::createReg(0)); 6576 Inst.addOperand(MCOperand::createImm(0)); 6577 6578 return S; 6579 } 6580 6581 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6582 const void *Decoder) { 6583 DecodeStatus S = MCDisassembler::Success; 6584 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6585 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6586 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6587 return MCDisassembler::Fail; 6588 return S; 6589 } 6590 6591 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6592 const void *Decoder) { 6593 DecodeStatus S = MCDisassembler::Success; 6594 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6595 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6596 return S; 6597 } 6598