1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARMBaseInstrInfo.h" 10 #include "MCTargetDesc/ARMAddressingModes.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMMCTargetDesc.h" 13 #include "TargetInfo/ARMTargetInfo.h" 14 #include "Utils/ARMBaseInfo.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 17 #include "llvm/MC/MCFixedLenDisassembler.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/SubtargetFeature.h" 22 #include "llvm/Support/Compiler.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <cstdint> 30 #include <vector> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "arm-disassembler" 35 36 using DecodeStatus = MCDisassembler::DecodeStatus; 37 38 namespace { 39 40 // Handles the condition code status of instructions in IT blocks 41 class ITStatus 42 { 43 public: 44 // Returns the condition code for instruction in IT block 45 unsigned getITCC() { 46 unsigned CC = ARMCC::AL; 47 if (instrInITBlock()) 48 CC = ITStates.back(); 49 return CC; 50 } 51 52 // Advances the IT block state to the next T or E 53 void advanceITState() { 54 ITStates.pop_back(); 55 } 56 57 // Returns true if the current instruction is in an IT block 58 bool instrInITBlock() { 59 return !ITStates.empty(); 60 } 61 62 // Returns true if current instruction is the last instruction in an IT block 63 bool instrLastInITBlock() { 64 return ITStates.size() == 1; 65 } 66 67 // Called when decoding an IT instruction. Sets the IT state for 68 // the following instructions that for the IT block. Firstcond 69 // corresponds to the field in the IT instruction encoding; Mask 70 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 71 void setITState(char Firstcond, char Mask) { 72 // (3 - the number of trailing zeros) is the number of then / else. 73 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 74 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 75 assert(NumTZ <= 3 && "Invalid IT mask!"); 76 // push condition codes onto the stack the correct order for the pops 77 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 78 unsigned Else = (Mask >> Pos) & 1; 79 ITStates.push_back(CCBits ^ Else); 80 } 81 ITStates.push_back(CCBits); 82 } 83 84 private: 85 std::vector<unsigned char> ITStates; 86 }; 87 88 class VPTStatus 89 { 90 public: 91 unsigned getVPTPred() { 92 unsigned Pred = ARMVCC::None; 93 if (instrInVPTBlock()) 94 Pred = VPTStates.back(); 95 return Pred; 96 } 97 98 void advanceVPTState() { 99 VPTStates.pop_back(); 100 } 101 102 bool instrInVPTBlock() { 103 return !VPTStates.empty(); 104 } 105 106 bool instrLastInVPTBlock() { 107 return VPTStates.size() == 1; 108 } 109 110 void setVPTState(char Mask) { 111 // (3 - the number of trailing zeros) is the number of then / else. 112 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 113 assert(NumTZ <= 3 && "Invalid VPT mask!"); 114 // push predicates onto the stack the correct order for the pops 115 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 116 bool T = ((Mask >> Pos) & 1) == 0; 117 if (T) 118 VPTStates.push_back(ARMVCC::Then); 119 else 120 VPTStates.push_back(ARMVCC::Else); 121 } 122 VPTStates.push_back(ARMVCC::Then); 123 } 124 125 private: 126 SmallVector<unsigned char, 4> VPTStates; 127 }; 128 129 /// ARM disassembler for all ARM platforms. 130 class ARMDisassembler : public MCDisassembler { 131 public: 132 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 133 MCDisassembler(STI, Ctx) { 134 } 135 136 ~ARMDisassembler() override = default; 137 138 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 139 ArrayRef<uint8_t> Bytes, uint64_t Address, 140 raw_ostream &CStream) const override; 141 142 private: 143 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 144 ArrayRef<uint8_t> Bytes, uint64_t Address, 145 raw_ostream &CStream) const; 146 147 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 148 ArrayRef<uint8_t> Bytes, uint64_t Address, 149 raw_ostream &CStream) const; 150 151 mutable ITStatus ITBlock; 152 mutable VPTStatus VPTBlock; 153 154 DecodeStatus AddThumbPredicate(MCInst&) const; 155 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 156 }; 157 158 } // end anonymous namespace 159 160 static bool Check(DecodeStatus &Out, DecodeStatus In) { 161 switch (In) { 162 case MCDisassembler::Success: 163 // Out stays the same. 164 return true; 165 case MCDisassembler::SoftFail: 166 Out = In; 167 return true; 168 case MCDisassembler::Fail: 169 Out = In; 170 return false; 171 } 172 llvm_unreachable("Invalid DecodeStatus!"); 173 } 174 175 // Forward declare these because the autogenerated code will reference them. 176 // Definitions are further down. 177 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 184 uint64_t Address, const void *Decoder); 185 static DecodeStatus 186 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 189 unsigned RegNo, uint64_t Address, 190 const void *Decoder); 191 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 192 unsigned RegNo, uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, 195 unsigned RegNo, uint64_t Address, 196 const void *Decoder); 197 static DecodeStatus DecodeGPRwithZRnospRegisterClass( 198 MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); 199 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 200 uint64_t Address, const void *Decoder); 201 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, const void *Decoder); 203 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 204 uint64_t Address, const void *Decoder); 205 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 206 uint64_t Address, const void *Decoder); 207 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 210 uint64_t Address, 211 const void *Decoder); 212 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 213 uint64_t Address, const void *Decoder); 214 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 215 uint64_t Address, const void *Decoder); 216 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, const void *Decoder); 218 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 219 uint64_t Address, const void *Decoder); 220 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 221 uint64_t Address, const void *Decoder); 222 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 223 unsigned RegNo, 224 uint64_t Address, 225 const void *Decoder); 226 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 227 uint64_t Address, const void *Decoder); 228 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, const void *Decoder); 230 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 231 uint64_t Address, const void *Decoder); 232 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 233 uint64_t Address, const void *Decoder); 234 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, const void *Decoder); 236 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 237 unsigned RegNo, uint64_t Address, 238 const void *Decoder); 239 240 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 241 uint64_t Address, const void *Decoder); 242 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 243 uint64_t Address, const void *Decoder); 244 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 245 uint64_t Address, const void *Decoder); 246 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 247 uint64_t Address, const void *Decoder); 248 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 249 uint64_t Address, const void *Decoder); 250 251 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 256 unsigned Insn, 257 uint64_t Address, 258 const void *Decoder); 259 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 268 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 269 unsigned Insn, 270 uint64_t Adddress, 271 const void *Decoder); 272 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 273 uint64_t Address, const void *Decoder); 274 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 275 uint64_t Address, const void *Decoder); 276 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 277 uint64_t Address, const void *Decoder); 278 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 279 uint64_t Address, const void *Decoder); 280 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 281 uint64_t Address, const void *Decoder); 282 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 283 uint64_t Address, const void *Decoder); 284 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 285 uint64_t Address, const void *Decoder); 286 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 287 uint64_t Address, const void *Decoder); 288 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 289 uint64_t Address, const void *Decoder); 290 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 309 uint64_t Address, const void *Decoder); 310 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 311 uint64_t Address, const void *Decoder); 312 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 313 uint64_t Address, const void *Decoder); 314 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 315 uint64_t Address, const void *Decoder); 316 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 317 uint64_t Address, const void *Decoder); 318 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 319 uint64_t Address, const void *Decoder); 320 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 321 uint64_t Address, const void *Decoder); 322 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst,unsigned Val, 323 uint64_t Address, const void *Decoder); 324 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val, 325 uint64_t Address, const void *Decoder); 326 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 327 uint64_t Address, const void *Decoder); 328 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 329 uint64_t Address, const void *Decoder); 330 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 331 uint64_t Address, const void *Decoder); 332 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 333 uint64_t Address, const void *Decoder); 334 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 335 uint64_t Address, const void *Decoder); 336 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 337 uint64_t Address, const void *Decoder); 338 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 339 uint64_t Address, const void *Decoder); 340 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 341 uint64_t Address, const void *Decoder); 342 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 343 uint64_t Address, const void *Decoder); 344 template<int shift> 345 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 386 uint64_t Address, const void *Decoder); 387 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 388 uint64_t Address, const void *Decoder); 389 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 390 uint64_t Address, const void *Decoder); 391 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 392 uint64_t Address, const void *Decoder); 393 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 394 uint64_t Address, const void *Decoder); 395 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 396 uint64_t Address, const void *Decoder); 397 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 398 unsigned Val, 399 uint64_t Address, 400 const void *Decoder); 401 402 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 403 uint64_t Address, const void *Decoder); 404 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 405 uint64_t Address, const void *Decoder); 406 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 407 uint64_t Address, const void *Decoder); 408 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 409 uint64_t Address, const void *Decoder); 410 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 411 uint64_t Address, const void *Decoder); 412 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 413 uint64_t Address, const void *Decoder); 414 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 415 uint64_t Address, const void *Decoder); 416 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 417 uint64_t Address, const void *Decoder); 418 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 419 uint64_t Address, const void *Decoder); 420 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 421 uint64_t Address, const void *Decoder); 422 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 423 uint64_t Address, const void* Decoder); 424 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 425 uint64_t Address, const void* Decoder); 426 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 427 uint64_t Address, const void* Decoder); 428 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 429 uint64_t Address, const void* Decoder); 430 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 431 uint64_t Address, const void *Decoder); 432 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, 433 uint64_t Address, const void *Decoder); 434 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 435 uint64_t Address, const void *Decoder); 436 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 437 uint64_t Address, 438 const void *Decoder); 439 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 440 uint64_t Address, const void *Decoder); 441 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 442 uint64_t Address, const void *Decoder); 443 template<int shift> 444 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 445 uint64_t Address, const void *Decoder); 446 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 447 uint64_t Address, const void *Decoder); 448 template<int shift> 449 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 450 uint64_t Address, const void *Decoder); 451 template<int shift, int WriteBack> 452 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 453 uint64_t Address, const void *Decoder); 454 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 455 uint64_t Address, const void *Decoder); 456 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 457 uint64_t Address, const void *Decoder); 458 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 459 uint64_t Address, const void *Decoder); 460 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 461 uint64_t Address, const void *Decoder); 462 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 463 uint64_t Address, const void *Decoder); 464 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 465 uint64_t Address, const void *Decoder); 466 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 467 uint64_t Address, const void *Decoder); 468 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 469 uint64_t Address, const void *Decoder); 470 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 471 uint64_t Address, const void *Decoder); 472 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 473 uint64_t Address, const void *Decoder); 474 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 475 uint64_t Address, const void *Decoder); 476 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 477 uint64_t Address, const void *Decoder); 478 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 479 uint64_t Address, const void *Decoder); 480 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 481 uint64_t Address, const void *Decoder); 482 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 483 uint64_t Address, const void *Decoder); 484 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 485 uint64_t Address, const void *Decoder); 486 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 487 uint64_t Address, const void *Decoder); 488 489 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 490 uint64_t Address, const void *Decoder); 491 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 492 uint64_t Address, const void *Decoder); 493 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 494 uint64_t Address, const void *Decoder); 495 496 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 497 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 498 uint64_t Address, const void *Decoder); 499 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 500 uint64_t Address, 501 const void *Decoder); 502 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const void *Decoder); 505 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 506 const void *Decoder); 507 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 508 uint64_t Address, 509 const void *Decoder); 510 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 511 const void *Decoder); 512 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 513 uint64_t Address, const void *Decoder); 514 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 515 uint64_t Address, const void *Decoder); 516 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, 517 uint64_t Address, 518 const void *Decoder); 519 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, 520 uint64_t Address, 521 const void *Decoder); 522 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, 523 uint64_t Address, 524 const void *Decoder); 525 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, 526 unsigned Val, 527 uint64_t Address, 528 const void *Decoder); 529 template<bool Writeback> 530 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 531 uint64_t Address, 532 const void *Decoder); 533 template<int shift> 534 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 535 uint64_t Address, const void *Decoder); 536 template<int shift> 537 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 538 uint64_t Address, const void *Decoder); 539 template<int shift> 540 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 541 uint64_t Address, const void *Decoder); 542 template<unsigned MinLog, unsigned MaxLog> 543 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 544 uint64_t Address, 545 const void *Decoder); 546 template<unsigned start> 547 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 548 uint64_t Address, 549 const void *Decoder); 550 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 551 uint64_t Address, 552 const void *Decoder); 553 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 554 uint64_t Address, 555 const void *Decoder); 556 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 557 uint64_t Address, const void *Decoder); 558 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 559 uint64_t Address, const void *Decoder); 560 template<bool scalar, OperandDecoder predicate_decoder> 561 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, 562 uint64_t Address, const void *Decoder); 563 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, 564 uint64_t Address, const void *Decoder); 565 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 566 uint64_t Address, const void *Decoder); 567 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, 568 uint64_t Address, 569 const void *Decoder); 570 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 571 uint64_t Address, const void *Decoder); 572 573 #include "ARMGenDisassemblerTables.inc" 574 575 static MCDisassembler *createARMDisassembler(const Target &T, 576 const MCSubtargetInfo &STI, 577 MCContext &Ctx) { 578 return new ARMDisassembler(STI, Ctx); 579 } 580 581 // Post-decoding checks 582 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 583 uint64_t Address, raw_ostream &CS, 584 uint32_t Insn, 585 DecodeStatus Result) { 586 switch (MI.getOpcode()) { 587 case ARM::HVC: { 588 // HVC is undefined if condition = 0xf otherwise upredictable 589 // if condition != 0xe 590 uint32_t Cond = (Insn >> 28) & 0xF; 591 if (Cond == 0xF) 592 return MCDisassembler::Fail; 593 if (Cond != 0xE) 594 return MCDisassembler::SoftFail; 595 return Result; 596 } 597 case ARM::t2ADDri: 598 case ARM::t2ADDri12: 599 case ARM::t2ADDrr: 600 case ARM::t2ADDrs: 601 case ARM::t2SUBri: 602 case ARM::t2SUBri12: 603 case ARM::t2SUBrr: 604 case ARM::t2SUBrs: 605 if (MI.getOperand(0).getReg() == ARM::SP && 606 MI.getOperand(1).getReg() != ARM::SP) 607 return MCDisassembler::SoftFail; 608 return Result; 609 default: return Result; 610 } 611 } 612 613 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 614 ArrayRef<uint8_t> Bytes, 615 uint64_t Address, 616 raw_ostream &CS) const { 617 if (STI.getFeatureBits()[ARM::ModeThumb]) 618 return getThumbInstruction(MI, Size, Bytes, Address, CS); 619 return getARMInstruction(MI, Size, Bytes, Address, CS); 620 } 621 622 DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 623 ArrayRef<uint8_t> Bytes, 624 uint64_t Address, 625 raw_ostream &CS) const { 626 CommentStream = &CS; 627 628 assert(!STI.getFeatureBits()[ARM::ModeThumb] && 629 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 630 "mode!"); 631 632 // We want to read exactly 4 bytes of data. 633 if (Bytes.size() < 4) { 634 Size = 0; 635 return MCDisassembler::Fail; 636 } 637 638 // Encoded as a small-endian 32-bit word in the stream. 639 uint32_t Insn = 640 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 641 642 // Calling the auto-generated decoder function. 643 DecodeStatus Result = 644 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 645 if (Result != MCDisassembler::Fail) { 646 Size = 4; 647 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 648 } 649 650 struct DecodeTable { 651 const uint8_t *P; 652 bool DecodePred; 653 }; 654 655 const DecodeTable Tables[] = { 656 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 657 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 658 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 659 {DecoderTablev8Crypto32, false}, 660 }; 661 662 for (auto Table : Tables) { 663 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 664 if (Result != MCDisassembler::Fail) { 665 Size = 4; 666 // Add a fake predicate operand, because we share these instruction 667 // definitions with Thumb2 where these instructions are predicable. 668 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 669 return MCDisassembler::Fail; 670 return Result; 671 } 672 } 673 674 Result = 675 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 676 if (Result != MCDisassembler::Fail) { 677 Size = 4; 678 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 679 } 680 681 Size = 4; 682 return MCDisassembler::Fail; 683 } 684 685 namespace llvm { 686 687 extern const MCInstrDesc ARMInsts[]; 688 689 } // end namespace llvm 690 691 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 692 /// immediate Value in the MCInst. The immediate Value has had any PC 693 /// adjustment made by the caller. If the instruction is a branch instruction 694 /// then isBranch is true, else false. If the getOpInfo() function was set as 695 /// part of the setupForSymbolicDisassembly() call then that function is called 696 /// to get any symbolic information at the Address for this instruction. If 697 /// that returns non-zero then the symbolic information it returns is used to 698 /// create an MCExpr and that is added as an operand to the MCInst. If 699 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 700 /// Value is done and if a symbol is found an MCExpr is created with that, else 701 /// an MCExpr with Value is created. This function returns true if it adds an 702 /// operand to the MCInst and false otherwise. 703 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 704 bool isBranch, uint64_t InstSize, 705 MCInst &MI, const void *Decoder) { 706 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 707 // FIXME: Does it make sense for value to be negative? 708 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 709 /* Offset */ 0, InstSize); 710 } 711 712 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 713 /// referenced by a load instruction with the base register that is the Pc. 714 /// These can often be values in a literal pool near the Address of the 715 /// instruction. The Address of the instruction and its immediate Value are 716 /// used as a possible literal pool entry. The SymbolLookUp call back will 717 /// return the name of a symbol referenced by the literal pool's entry if 718 /// the referenced address is that of a symbol. Or it will return a pointer to 719 /// a literal 'C' string if the referenced address of the literal pool's entry 720 /// is an address into a section with 'C' string literals. 721 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 722 const void *Decoder) { 723 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 724 Dis->tryAddingPcLoadReferenceComment(Value, Address); 725 } 726 727 // Thumb1 instructions don't have explicit S bits. Rather, they 728 // implicitly set CPSR. Since it's not represented in the encoding, the 729 // auto-generated decoder won't inject the CPSR operand. We need to fix 730 // that as a post-pass. 731 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 732 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 733 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 734 MCInst::iterator I = MI.begin(); 735 for (unsigned i = 0; i < NumOps; ++i, ++I) { 736 if (I == MI.end()) break; 737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 738 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 740 return; 741 } 742 } 743 744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 745 } 746 747 static bool isVectorPredicable(unsigned Opcode) { 748 const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; 749 unsigned short NumOps = ARMInsts[Opcode].NumOperands; 750 for (unsigned i = 0; i < NumOps; ++i) { 751 if (ARM::isVpred(OpInfo[i].OperandType)) 752 return true; 753 } 754 return false; 755 } 756 757 // Most Thumb instructions don't have explicit predicates in the 758 // encoding, but rather get their predicates from IT context. We need 759 // to fix up the predicate operands using this context information as a 760 // post-pass. 761 MCDisassembler::DecodeStatus 762 ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 763 MCDisassembler::DecodeStatus S = Success; 764 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 766 767 // A few instructions actually have predicates encoded in them. Don't 768 // try to overwrite it if we're seeing one of those. 769 switch (MI.getOpcode()) { 770 case ARM::tBcc: 771 case ARM::t2Bcc: 772 case ARM::tCBZ: 773 case ARM::tCBNZ: 774 case ARM::tCPS: 775 case ARM::t2CPS3p: 776 case ARM::t2CPS2p: 777 case ARM::t2CPS1p: 778 case ARM::t2CSEL: 779 case ARM::t2CSINC: 780 case ARM::t2CSINV: 781 case ARM::t2CSNEG: 782 case ARM::tMOVSr: 783 case ARM::tSETEND: 784 // Some instructions (mostly conditional branches) are not 785 // allowed in IT blocks. 786 if (ITBlock.instrInITBlock()) 787 S = SoftFail; 788 else 789 return Success; 790 break; 791 case ARM::t2HINT: 792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 793 S = SoftFail; 794 break; 795 case ARM::tB: 796 case ARM::t2B: 797 case ARM::t2TBB: 798 case ARM::t2TBH: 799 // Some instructions (mostly unconditional branches) can 800 // only appears at the end of, or outside of, an IT. 801 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 802 S = SoftFail; 803 break; 804 default: 805 break; 806 } 807 808 // Warn on non-VPT predicable instruction in a VPT block and a VPT 809 // predicable instruction in an IT block 810 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) || 811 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock())) 812 S = SoftFail; 813 814 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 815 // assume a predicate of AL. 816 unsigned CC = ARMCC::AL; 817 unsigned VCC = ARMVCC::None; 818 if (ITBlock.instrInITBlock()) { 819 CC = ITBlock.getITCC(); 820 ITBlock.advanceITState(); 821 } else if (VPTBlock.instrInVPTBlock()) { 822 VCC = VPTBlock.getVPTPred(); 823 VPTBlock.advanceVPTState(); 824 } 825 826 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 827 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 828 829 MCInst::iterator CCI = MI.begin(); 830 for (unsigned i = 0; i < NumOps; ++i, ++CCI) { 831 if (OpInfo[i].isPredicate() || CCI == MI.end()) break; 832 } 833 834 if (ARMInsts[MI.getOpcode()].isPredicable()) { 835 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 836 ++CCI; 837 if (CC == ARMCC::AL) 838 MI.insert(CCI, MCOperand::createReg(0)); 839 else 840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 841 } else if (CC != ARMCC::AL) { 842 Check(S, SoftFail); 843 } 844 845 MCInst::iterator VCCI = MI.begin(); 846 unsigned VCCPos; 847 for (VCCPos = 0; VCCPos < NumOps; ++VCCPos, ++VCCI) { 848 if (ARM::isVpred(OpInfo[VCCPos].OperandType) || VCCI == MI.end()) break; 849 } 850 851 if (isVectorPredicable(MI.getOpcode())) { 852 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 853 ++VCCI; 854 if (VCC == ARMVCC::None) 855 MI.insert(VCCI, MCOperand::createReg(0)); 856 else 857 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 858 if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 859 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( 860 VCCPos + 2, MCOI::TIED_TO); 861 assert(TiedOp >= 0 && 862 "Inactive register in vpred_r is not tied to an output!"); 863 // Copy the operand to ensure it's not invalidated when MI grows. 864 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 865 } 866 } else if (VCC != ARMVCC::None) { 867 Check(S, SoftFail); 868 } 869 870 return S; 871 } 872 873 // Thumb VFP instructions are a special case. Because we share their 874 // encodings between ARM and Thumb modes, and they are predicable in ARM 875 // mode, the auto-generated decoder will give them an (incorrect) 876 // predicate operand. We need to rewrite these operands based on the IT 877 // context as a post-pass. 878 void ARMDisassembler::UpdateThumbVFPPredicate( 879 DecodeStatus &S, MCInst &MI) const { 880 unsigned CC; 881 CC = ITBlock.getITCC(); 882 if (CC == 0xF) 883 CC = ARMCC::AL; 884 if (ITBlock.instrInITBlock()) 885 ITBlock.advanceITState(); 886 else if (VPTBlock.instrInVPTBlock()) { 887 CC = VPTBlock.getVPTPred(); 888 VPTBlock.advanceVPTState(); 889 } 890 891 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 892 MCInst::iterator I = MI.begin(); 893 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 894 for (unsigned i = 0; i < NumOps; ++i, ++I) { 895 if (OpInfo[i].isPredicate() ) { 896 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable()) 897 Check(S, SoftFail); 898 I->setImm(CC); 899 ++I; 900 if (CC == ARMCC::AL) 901 I->setReg(0); 902 else 903 I->setReg(ARM::CPSR); 904 return; 905 } 906 } 907 } 908 909 DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 910 ArrayRef<uint8_t> Bytes, 911 uint64_t Address, 912 raw_ostream &CS) const { 913 CommentStream = &CS; 914 915 assert(STI.getFeatureBits()[ARM::ModeThumb] && 916 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 917 918 // We want to read exactly 2 bytes of data. 919 if (Bytes.size() < 2) { 920 Size = 0; 921 return MCDisassembler::Fail; 922 } 923 924 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 925 DecodeStatus Result = 926 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 927 if (Result != MCDisassembler::Fail) { 928 Size = 2; 929 Check(Result, AddThumbPredicate(MI)); 930 return Result; 931 } 932 933 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 934 STI); 935 if (Result) { 936 Size = 2; 937 bool InITBlock = ITBlock.instrInITBlock(); 938 Check(Result, AddThumbPredicate(MI)); 939 AddThumb1SBit(MI, InITBlock); 940 return Result; 941 } 942 943 Result = 944 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 945 if (Result != MCDisassembler::Fail) { 946 Size = 2; 947 948 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 949 // the Thumb predicate. 950 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 951 Result = MCDisassembler::SoftFail; 952 953 Check(Result, AddThumbPredicate(MI)); 954 955 // If we find an IT instruction, we need to parse its condition 956 // code and mask operands so that we can apply them correctly 957 // to the subsequent instructions. 958 if (MI.getOpcode() == ARM::t2IT) { 959 unsigned Firstcond = MI.getOperand(0).getImm(); 960 unsigned Mask = MI.getOperand(1).getImm(); 961 ITBlock.setITState(Firstcond, Mask); 962 963 // An IT instruction that would give a 'NV' predicate is unpredictable. 964 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 965 CS << "unpredictable IT predicate sequence"; 966 } 967 968 return Result; 969 } 970 971 // We want to read exactly 4 bytes of data. 972 if (Bytes.size() < 4) { 973 Size = 0; 974 return MCDisassembler::Fail; 975 } 976 977 uint32_t Insn32 = 978 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 979 980 Result = 981 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 982 if (Result != MCDisassembler::Fail) { 983 Size = 4; 984 985 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 986 // the VPT predicate. 987 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 988 Result = MCDisassembler::SoftFail; 989 990 Check(Result, AddThumbPredicate(MI)); 991 992 if (isVPTOpcode(MI.getOpcode())) { 993 unsigned Mask = MI.getOperand(0).getImm(); 994 VPTBlock.setVPTState(Mask); 995 } 996 997 return Result; 998 } 999 1000 Result = 1001 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1002 if (Result != MCDisassembler::Fail) { 1003 Size = 4; 1004 bool InITBlock = ITBlock.instrInITBlock(); 1005 Check(Result, AddThumbPredicate(MI)); 1006 AddThumb1SBit(MI, InITBlock); 1007 return Result; 1008 } 1009 1010 Result = 1011 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1012 if (Result != MCDisassembler::Fail) { 1013 Size = 4; 1014 Check(Result, AddThumbPredicate(MI)); 1015 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1016 } 1017 1018 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1019 Result = 1020 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1021 if (Result != MCDisassembler::Fail) { 1022 Size = 4; 1023 UpdateThumbVFPPredicate(Result, MI); 1024 return Result; 1025 } 1026 } 1027 1028 Result = 1029 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1030 if (Result != MCDisassembler::Fail) { 1031 Size = 4; 1032 return Result; 1033 } 1034 1035 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1036 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1037 STI); 1038 if (Result != MCDisassembler::Fail) { 1039 Size = 4; 1040 Check(Result, AddThumbPredicate(MI)); 1041 return Result; 1042 } 1043 } 1044 1045 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1046 uint32_t NEONLdStInsn = Insn32; 1047 NEONLdStInsn &= 0xF0FFFFFF; 1048 NEONLdStInsn |= 0x04000000; 1049 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1050 Address, this, STI); 1051 if (Result != MCDisassembler::Fail) { 1052 Size = 4; 1053 Check(Result, AddThumbPredicate(MI)); 1054 return Result; 1055 } 1056 } 1057 1058 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1059 uint32_t NEONDataInsn = Insn32; 1060 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1061 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1062 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1063 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1064 Address, this, STI); 1065 if (Result != MCDisassembler::Fail) { 1066 Size = 4; 1067 Check(Result, AddThumbPredicate(MI)); 1068 return Result; 1069 } 1070 1071 uint32_t NEONCryptoInsn = Insn32; 1072 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1073 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1074 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1075 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1076 Address, this, STI); 1077 if (Result != MCDisassembler::Fail) { 1078 Size = 4; 1079 return Result; 1080 } 1081 1082 uint32_t NEONv8Insn = Insn32; 1083 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1084 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1085 this, STI); 1086 if (Result != MCDisassembler::Fail) { 1087 Size = 4; 1088 return Result; 1089 } 1090 } 1091 1092 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1093 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1094 ? DecoderTableThumb2CDE32 1095 : DecoderTableThumb2CoProc32; 1096 Result = 1097 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1098 if (Result != MCDisassembler::Fail) { 1099 Size = 4; 1100 Check(Result, AddThumbPredicate(MI)); 1101 return Result; 1102 } 1103 1104 Size = 0; 1105 return MCDisassembler::Fail; 1106 } 1107 1108 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1109 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1110 createARMDisassembler); 1111 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1112 createARMDisassembler); 1113 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1114 createARMDisassembler); 1115 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1116 createARMDisassembler); 1117 } 1118 1119 static const uint16_t GPRDecoderTable[] = { 1120 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1121 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1122 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1123 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1124 }; 1125 1126 static const uint16_t CLRMGPRDecoderTable[] = { 1127 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1128 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1129 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1130 ARM::R12, 0, ARM::LR, ARM::APSR 1131 }; 1132 1133 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1134 uint64_t Address, const void *Decoder) { 1135 if (RegNo > 15) 1136 return MCDisassembler::Fail; 1137 1138 unsigned Register = GPRDecoderTable[RegNo]; 1139 Inst.addOperand(MCOperand::createReg(Register)); 1140 return MCDisassembler::Success; 1141 } 1142 1143 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1144 uint64_t Address, 1145 const void *Decoder) { 1146 if (RegNo > 15) 1147 return MCDisassembler::Fail; 1148 1149 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1150 if (Register == 0) 1151 return MCDisassembler::Fail; 1152 1153 Inst.addOperand(MCOperand::createReg(Register)); 1154 return MCDisassembler::Success; 1155 } 1156 1157 static DecodeStatus 1158 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1159 uint64_t Address, const void *Decoder) { 1160 DecodeStatus S = MCDisassembler::Success; 1161 1162 if (RegNo == 15) 1163 S = MCDisassembler::SoftFail; 1164 1165 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1166 1167 return S; 1168 } 1169 1170 static DecodeStatus 1171 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 1172 uint64_t Address, const void *Decoder) { 1173 DecodeStatus S = MCDisassembler::Success; 1174 1175 if (RegNo == 15) 1176 { 1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1178 return MCDisassembler::Success; 1179 } 1180 1181 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1182 return S; 1183 } 1184 1185 static DecodeStatus 1186 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 1187 uint64_t Address, const void *Decoder) { 1188 DecodeStatus S = MCDisassembler::Success; 1189 1190 if (RegNo == 15) 1191 { 1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1193 return MCDisassembler::Success; 1194 } 1195 1196 if (RegNo == 13) 1197 Check(S, MCDisassembler::SoftFail); 1198 1199 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1200 return S; 1201 } 1202 1203 static DecodeStatus 1204 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1205 uint64_t Address, const void *Decoder) { 1206 DecodeStatus S = MCDisassembler::Success; 1207 if (RegNo == 13) 1208 return MCDisassembler::Fail; 1209 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1210 return S; 1211 } 1212 1213 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1214 uint64_t Address, const void *Decoder) { 1215 if (RegNo > 7) 1216 return MCDisassembler::Fail; 1217 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1218 } 1219 1220 static const uint16_t GPRPairDecoderTable[] = { 1221 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1222 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1223 }; 1224 1225 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1226 uint64_t Address, const void *Decoder) { 1227 DecodeStatus S = MCDisassembler::Success; 1228 1229 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1230 // rather than SoftFail as there is no GPRPair table entry for index 7. 1231 if (RegNo > 13) 1232 return MCDisassembler::Fail; 1233 1234 if (RegNo & 1) 1235 S = MCDisassembler::SoftFail; 1236 1237 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1238 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1239 return S; 1240 } 1241 1242 static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, 1243 uint64_t Address, const void *Decoder) { 1244 if (RegNo > 13) 1245 return MCDisassembler::Fail; 1246 1247 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1248 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1249 1250 if ((RegNo & 1) || RegNo > 10) 1251 return MCDisassembler::SoftFail; 1252 return MCDisassembler::Success; 1253 } 1254 1255 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1256 uint64_t Address, 1257 const void *Decoder) { 1258 if (RegNo != 13) 1259 return MCDisassembler::Fail; 1260 1261 unsigned Register = GPRDecoderTable[RegNo]; 1262 Inst.addOperand(MCOperand::createReg(Register)); 1263 return MCDisassembler::Success; 1264 } 1265 1266 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1267 uint64_t Address, const void *Decoder) { 1268 unsigned Register = 0; 1269 switch (RegNo) { 1270 case 0: 1271 Register = ARM::R0; 1272 break; 1273 case 1: 1274 Register = ARM::R1; 1275 break; 1276 case 2: 1277 Register = ARM::R2; 1278 break; 1279 case 3: 1280 Register = ARM::R3; 1281 break; 1282 case 9: 1283 Register = ARM::R9; 1284 break; 1285 case 12: 1286 Register = ARM::R12; 1287 break; 1288 default: 1289 return MCDisassembler::Fail; 1290 } 1291 1292 Inst.addOperand(MCOperand::createReg(Register)); 1293 return MCDisassembler::Success; 1294 } 1295 1296 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1297 uint64_t Address, const void *Decoder) { 1298 DecodeStatus S = MCDisassembler::Success; 1299 1300 const FeatureBitset &featureBits = 1301 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1302 1303 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1304 S = MCDisassembler::SoftFail; 1305 1306 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1307 return S; 1308 } 1309 1310 static const uint16_t SPRDecoderTable[] = { 1311 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1312 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1313 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1314 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1315 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1316 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1317 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1318 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1319 }; 1320 1321 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1322 uint64_t Address, const void *Decoder) { 1323 if (RegNo > 31) 1324 return MCDisassembler::Fail; 1325 1326 unsigned Register = SPRDecoderTable[RegNo]; 1327 Inst.addOperand(MCOperand::createReg(Register)); 1328 return MCDisassembler::Success; 1329 } 1330 1331 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1332 uint64_t Address, const void *Decoder) { 1333 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1334 } 1335 1336 static const uint16_t DPRDecoderTable[] = { 1337 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1338 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1339 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1340 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1341 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1342 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1343 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1344 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1345 }; 1346 1347 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1348 uint64_t Address, const void *Decoder) { 1349 const FeatureBitset &featureBits = 1350 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1351 1352 bool hasD32 = featureBits[ARM::FeatureD32]; 1353 1354 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1355 return MCDisassembler::Fail; 1356 1357 unsigned Register = DPRDecoderTable[RegNo]; 1358 Inst.addOperand(MCOperand::createReg(Register)); 1359 return MCDisassembler::Success; 1360 } 1361 1362 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1363 uint64_t Address, const void *Decoder) { 1364 if (RegNo > 7) 1365 return MCDisassembler::Fail; 1366 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1367 } 1368 1369 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1370 uint64_t Address, const void *Decoder) { 1371 if (RegNo > 15) 1372 return MCDisassembler::Fail; 1373 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1374 } 1375 1376 static DecodeStatus 1377 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1378 uint64_t Address, const void *Decoder) { 1379 if (RegNo > 15) 1380 return MCDisassembler::Fail; 1381 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1382 } 1383 1384 static const uint16_t QPRDecoderTable[] = { 1385 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1386 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1387 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1388 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1389 }; 1390 1391 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1392 uint64_t Address, const void *Decoder) { 1393 if (RegNo > 31 || (RegNo & 1) != 0) 1394 return MCDisassembler::Fail; 1395 RegNo >>= 1; 1396 1397 unsigned Register = QPRDecoderTable[RegNo]; 1398 Inst.addOperand(MCOperand::createReg(Register)); 1399 return MCDisassembler::Success; 1400 } 1401 1402 static const uint16_t DPairDecoderTable[] = { 1403 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1404 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1405 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1406 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1407 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1408 ARM::Q15 1409 }; 1410 1411 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1412 uint64_t Address, const void *Decoder) { 1413 if (RegNo > 30) 1414 return MCDisassembler::Fail; 1415 1416 unsigned Register = DPairDecoderTable[RegNo]; 1417 Inst.addOperand(MCOperand::createReg(Register)); 1418 return MCDisassembler::Success; 1419 } 1420 1421 static const uint16_t DPairSpacedDecoderTable[] = { 1422 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1423 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1424 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1425 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1426 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1427 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1428 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1429 ARM::D28_D30, ARM::D29_D31 1430 }; 1431 1432 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1433 unsigned RegNo, 1434 uint64_t Address, 1435 const void *Decoder) { 1436 if (RegNo > 29) 1437 return MCDisassembler::Fail; 1438 1439 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1440 Inst.addOperand(MCOperand::createReg(Register)); 1441 return MCDisassembler::Success; 1442 } 1443 1444 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1445 uint64_t Address, const void *Decoder) { 1446 DecodeStatus S = MCDisassembler::Success; 1447 if (Val == 0xF) return MCDisassembler::Fail; 1448 // AL predicate is not allowed on Thumb1 branches. 1449 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1450 return MCDisassembler::Fail; 1451 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable()) 1452 Check(S, MCDisassembler::SoftFail); 1453 Inst.addOperand(MCOperand::createImm(Val)); 1454 if (Val == ARMCC::AL) { 1455 Inst.addOperand(MCOperand::createReg(0)); 1456 } else 1457 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1458 return S; 1459 } 1460 1461 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1462 uint64_t Address, const void *Decoder) { 1463 if (Val) 1464 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1465 else 1466 Inst.addOperand(MCOperand::createReg(0)); 1467 return MCDisassembler::Success; 1468 } 1469 1470 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1471 uint64_t Address, const void *Decoder) { 1472 DecodeStatus S = MCDisassembler::Success; 1473 1474 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1475 unsigned type = fieldFromInstruction(Val, 5, 2); 1476 unsigned imm = fieldFromInstruction(Val, 7, 5); 1477 1478 // Register-immediate 1479 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1480 return MCDisassembler::Fail; 1481 1482 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1483 switch (type) { 1484 case 0: 1485 Shift = ARM_AM::lsl; 1486 break; 1487 case 1: 1488 Shift = ARM_AM::lsr; 1489 break; 1490 case 2: 1491 Shift = ARM_AM::asr; 1492 break; 1493 case 3: 1494 Shift = ARM_AM::ror; 1495 break; 1496 } 1497 1498 if (Shift == ARM_AM::ror && imm == 0) 1499 Shift = ARM_AM::rrx; 1500 1501 unsigned Op = Shift | (imm << 3); 1502 Inst.addOperand(MCOperand::createImm(Op)); 1503 1504 return S; 1505 } 1506 1507 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1508 uint64_t Address, const void *Decoder) { 1509 DecodeStatus S = MCDisassembler::Success; 1510 1511 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1512 unsigned type = fieldFromInstruction(Val, 5, 2); 1513 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1514 1515 // Register-register 1516 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1517 return MCDisassembler::Fail; 1518 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1519 return MCDisassembler::Fail; 1520 1521 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1522 switch (type) { 1523 case 0: 1524 Shift = ARM_AM::lsl; 1525 break; 1526 case 1: 1527 Shift = ARM_AM::lsr; 1528 break; 1529 case 2: 1530 Shift = ARM_AM::asr; 1531 break; 1532 case 3: 1533 Shift = ARM_AM::ror; 1534 break; 1535 } 1536 1537 Inst.addOperand(MCOperand::createImm(Shift)); 1538 1539 return S; 1540 } 1541 1542 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1543 uint64_t Address, const void *Decoder) { 1544 DecodeStatus S = MCDisassembler::Success; 1545 1546 bool NeedDisjointWriteback = false; 1547 unsigned WritebackReg = 0; 1548 bool CLRM = false; 1549 switch (Inst.getOpcode()) { 1550 default: 1551 break; 1552 case ARM::LDMIA_UPD: 1553 case ARM::LDMDB_UPD: 1554 case ARM::LDMIB_UPD: 1555 case ARM::LDMDA_UPD: 1556 case ARM::t2LDMIA_UPD: 1557 case ARM::t2LDMDB_UPD: 1558 case ARM::t2STMIA_UPD: 1559 case ARM::t2STMDB_UPD: 1560 NeedDisjointWriteback = true; 1561 WritebackReg = Inst.getOperand(0).getReg(); 1562 break; 1563 case ARM::t2CLRM: 1564 CLRM = true; 1565 break; 1566 } 1567 1568 // Empty register lists are not allowed. 1569 if (Val == 0) return MCDisassembler::Fail; 1570 for (unsigned i = 0; i < 16; ++i) { 1571 if (Val & (1 << i)) { 1572 if (CLRM) { 1573 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1574 return MCDisassembler::Fail; 1575 } 1576 } else { 1577 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1578 return MCDisassembler::Fail; 1579 // Writeback not allowed if Rn is in the target list. 1580 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1581 Check(S, MCDisassembler::SoftFail); 1582 } 1583 } 1584 } 1585 1586 return S; 1587 } 1588 1589 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1590 uint64_t Address, const void *Decoder) { 1591 DecodeStatus S = MCDisassembler::Success; 1592 1593 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1594 unsigned regs = fieldFromInstruction(Val, 0, 8); 1595 1596 // In case of unpredictable encoding, tweak the operands. 1597 if (regs == 0 || (Vd + regs) > 32) { 1598 regs = Vd + regs > 32 ? 32 - Vd : regs; 1599 regs = std::max( 1u, regs); 1600 S = MCDisassembler::SoftFail; 1601 } 1602 1603 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1604 return MCDisassembler::Fail; 1605 for (unsigned i = 0; i < (regs - 1); ++i) { 1606 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1607 return MCDisassembler::Fail; 1608 } 1609 1610 return S; 1611 } 1612 1613 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1614 uint64_t Address, const void *Decoder) { 1615 DecodeStatus S = MCDisassembler::Success; 1616 1617 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1618 unsigned regs = fieldFromInstruction(Val, 1, 7); 1619 1620 // In case of unpredictable encoding, tweak the operands. 1621 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1622 regs = Vd + regs > 32 ? 32 - Vd : regs; 1623 regs = std::max( 1u, regs); 1624 regs = std::min(16u, regs); 1625 S = MCDisassembler::SoftFail; 1626 } 1627 1628 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1629 return MCDisassembler::Fail; 1630 for (unsigned i = 0; i < (regs - 1); ++i) { 1631 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1632 return MCDisassembler::Fail; 1633 } 1634 1635 return S; 1636 } 1637 1638 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1639 uint64_t Address, const void *Decoder) { 1640 // This operand encodes a mask of contiguous zeros between a specified MSB 1641 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1642 // the mask of all bits LSB-and-lower, and then xor them to create 1643 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1644 // create the final mask. 1645 unsigned msb = fieldFromInstruction(Val, 5, 5); 1646 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1647 1648 DecodeStatus S = MCDisassembler::Success; 1649 if (lsb > msb) { 1650 Check(S, MCDisassembler::SoftFail); 1651 // The check above will cause the warning for the "potentially undefined 1652 // instruction encoding" but we can't build a bad MCOperand value here 1653 // with a lsb > msb or else printing the MCInst will cause a crash. 1654 lsb = msb; 1655 } 1656 1657 uint32_t msb_mask = 0xFFFFFFFF; 1658 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1659 uint32_t lsb_mask = (1U << lsb) - 1; 1660 1661 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1662 return S; 1663 } 1664 1665 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1666 uint64_t Address, const void *Decoder) { 1667 DecodeStatus S = MCDisassembler::Success; 1668 1669 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1670 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1671 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1672 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1674 unsigned U = fieldFromInstruction(Insn, 23, 1); 1675 const FeatureBitset &featureBits = 1676 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1677 1678 switch (Inst.getOpcode()) { 1679 case ARM::LDC_OFFSET: 1680 case ARM::LDC_PRE: 1681 case ARM::LDC_POST: 1682 case ARM::LDC_OPTION: 1683 case ARM::LDCL_OFFSET: 1684 case ARM::LDCL_PRE: 1685 case ARM::LDCL_POST: 1686 case ARM::LDCL_OPTION: 1687 case ARM::STC_OFFSET: 1688 case ARM::STC_PRE: 1689 case ARM::STC_POST: 1690 case ARM::STC_OPTION: 1691 case ARM::STCL_OFFSET: 1692 case ARM::STCL_PRE: 1693 case ARM::STCL_POST: 1694 case ARM::STCL_OPTION: 1695 case ARM::t2LDC_OFFSET: 1696 case ARM::t2LDC_PRE: 1697 case ARM::t2LDC_POST: 1698 case ARM::t2LDC_OPTION: 1699 case ARM::t2LDCL_OFFSET: 1700 case ARM::t2LDCL_PRE: 1701 case ARM::t2LDCL_POST: 1702 case ARM::t2LDCL_OPTION: 1703 case ARM::t2STC_OFFSET: 1704 case ARM::t2STC_PRE: 1705 case ARM::t2STC_POST: 1706 case ARM::t2STC_OPTION: 1707 case ARM::t2STCL_OFFSET: 1708 case ARM::t2STCL_PRE: 1709 case ARM::t2STCL_POST: 1710 case ARM::t2STCL_OPTION: 1711 case ARM::t2LDC2_OFFSET: 1712 case ARM::t2LDC2L_OFFSET: 1713 case ARM::t2LDC2_PRE: 1714 case ARM::t2LDC2L_PRE: 1715 case ARM::t2STC2_OFFSET: 1716 case ARM::t2STC2L_OFFSET: 1717 case ARM::t2STC2_PRE: 1718 case ARM::t2STC2L_PRE: 1719 case ARM::LDC2_OFFSET: 1720 case ARM::LDC2L_OFFSET: 1721 case ARM::LDC2_PRE: 1722 case ARM::LDC2L_PRE: 1723 case ARM::STC2_OFFSET: 1724 case ARM::STC2L_OFFSET: 1725 case ARM::STC2_PRE: 1726 case ARM::STC2L_PRE: 1727 case ARM::t2LDC2_OPTION: 1728 case ARM::t2STC2_OPTION: 1729 case ARM::t2LDC2_POST: 1730 case ARM::t2LDC2L_POST: 1731 case ARM::t2STC2_POST: 1732 case ARM::t2STC2L_POST: 1733 case ARM::LDC2_POST: 1734 case ARM::LDC2L_POST: 1735 case ARM::STC2_POST: 1736 case ARM::STC2L_POST: 1737 if (coproc == 0xA || coproc == 0xB || 1738 (featureBits[ARM::HasV8_1MMainlineOps] && 1739 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1740 coproc == 0xE || coproc == 0xF))) 1741 return MCDisassembler::Fail; 1742 break; 1743 default: 1744 break; 1745 } 1746 1747 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1748 return MCDisassembler::Fail; 1749 1750 Inst.addOperand(MCOperand::createImm(coproc)); 1751 Inst.addOperand(MCOperand::createImm(CRd)); 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 1755 switch (Inst.getOpcode()) { 1756 case ARM::t2LDC2_OFFSET: 1757 case ARM::t2LDC2L_OFFSET: 1758 case ARM::t2LDC2_PRE: 1759 case ARM::t2LDC2L_PRE: 1760 case ARM::t2STC2_OFFSET: 1761 case ARM::t2STC2L_OFFSET: 1762 case ARM::t2STC2_PRE: 1763 case ARM::t2STC2L_PRE: 1764 case ARM::LDC2_OFFSET: 1765 case ARM::LDC2L_OFFSET: 1766 case ARM::LDC2_PRE: 1767 case ARM::LDC2L_PRE: 1768 case ARM::STC2_OFFSET: 1769 case ARM::STC2L_OFFSET: 1770 case ARM::STC2_PRE: 1771 case ARM::STC2L_PRE: 1772 case ARM::t2LDC_OFFSET: 1773 case ARM::t2LDCL_OFFSET: 1774 case ARM::t2LDC_PRE: 1775 case ARM::t2LDCL_PRE: 1776 case ARM::t2STC_OFFSET: 1777 case ARM::t2STCL_OFFSET: 1778 case ARM::t2STC_PRE: 1779 case ARM::t2STCL_PRE: 1780 case ARM::LDC_OFFSET: 1781 case ARM::LDCL_OFFSET: 1782 case ARM::LDC_PRE: 1783 case ARM::LDCL_PRE: 1784 case ARM::STC_OFFSET: 1785 case ARM::STCL_OFFSET: 1786 case ARM::STC_PRE: 1787 case ARM::STCL_PRE: 1788 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1789 Inst.addOperand(MCOperand::createImm(imm)); 1790 break; 1791 case ARM::t2LDC2_POST: 1792 case ARM::t2LDC2L_POST: 1793 case ARM::t2STC2_POST: 1794 case ARM::t2STC2L_POST: 1795 case ARM::LDC2_POST: 1796 case ARM::LDC2L_POST: 1797 case ARM::STC2_POST: 1798 case ARM::STC2L_POST: 1799 case ARM::t2LDC_POST: 1800 case ARM::t2LDCL_POST: 1801 case ARM::t2STC_POST: 1802 case ARM::t2STCL_POST: 1803 case ARM::LDC_POST: 1804 case ARM::LDCL_POST: 1805 case ARM::STC_POST: 1806 case ARM::STCL_POST: 1807 imm |= U << 8; 1808 LLVM_FALLTHROUGH; 1809 default: 1810 // The 'option' variant doesn't encode 'U' in the immediate since 1811 // the immediate is unsigned [0,255]. 1812 Inst.addOperand(MCOperand::createImm(imm)); 1813 break; 1814 } 1815 1816 switch (Inst.getOpcode()) { 1817 case ARM::LDC_OFFSET: 1818 case ARM::LDC_PRE: 1819 case ARM::LDC_POST: 1820 case ARM::LDC_OPTION: 1821 case ARM::LDCL_OFFSET: 1822 case ARM::LDCL_PRE: 1823 case ARM::LDCL_POST: 1824 case ARM::LDCL_OPTION: 1825 case ARM::STC_OFFSET: 1826 case ARM::STC_PRE: 1827 case ARM::STC_POST: 1828 case ARM::STC_OPTION: 1829 case ARM::STCL_OFFSET: 1830 case ARM::STCL_PRE: 1831 case ARM::STCL_POST: 1832 case ARM::STCL_OPTION: 1833 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1834 return MCDisassembler::Fail; 1835 break; 1836 default: 1837 break; 1838 } 1839 1840 return S; 1841 } 1842 1843 static DecodeStatus 1844 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1845 uint64_t Address, const void *Decoder) { 1846 DecodeStatus S = MCDisassembler::Success; 1847 1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1849 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1851 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1852 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1853 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1854 unsigned P = fieldFromInstruction(Insn, 24, 1); 1855 unsigned W = fieldFromInstruction(Insn, 21, 1); 1856 1857 // On stores, the writeback operand precedes Rt. 1858 switch (Inst.getOpcode()) { 1859 case ARM::STR_POST_IMM: 1860 case ARM::STR_POST_REG: 1861 case ARM::STRB_POST_IMM: 1862 case ARM::STRB_POST_REG: 1863 case ARM::STRT_POST_REG: 1864 case ARM::STRT_POST_IMM: 1865 case ARM::STRBT_POST_REG: 1866 case ARM::STRBT_POST_IMM: 1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1868 return MCDisassembler::Fail; 1869 break; 1870 default: 1871 break; 1872 } 1873 1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1875 return MCDisassembler::Fail; 1876 1877 // On loads, the writeback operand comes after Rt. 1878 switch (Inst.getOpcode()) { 1879 case ARM::LDR_POST_IMM: 1880 case ARM::LDR_POST_REG: 1881 case ARM::LDRB_POST_IMM: 1882 case ARM::LDRB_POST_REG: 1883 case ARM::LDRBT_POST_REG: 1884 case ARM::LDRBT_POST_IMM: 1885 case ARM::LDRT_POST_REG: 1886 case ARM::LDRT_POST_IMM: 1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1888 return MCDisassembler::Fail; 1889 break; 1890 default: 1891 break; 1892 } 1893 1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1895 return MCDisassembler::Fail; 1896 1897 ARM_AM::AddrOpc Op = ARM_AM::add; 1898 if (!fieldFromInstruction(Insn, 23, 1)) 1899 Op = ARM_AM::sub; 1900 1901 bool writeback = (P == 0) || (W == 1); 1902 unsigned idx_mode = 0; 1903 if (P && writeback) 1904 idx_mode = ARMII::IndexModePre; 1905 else if (!P && writeback) 1906 idx_mode = ARMII::IndexModePost; 1907 1908 if (writeback && (Rn == 15 || Rn == Rt)) 1909 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1910 1911 if (reg) { 1912 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1913 return MCDisassembler::Fail; 1914 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1915 switch( fieldFromInstruction(Insn, 5, 2)) { 1916 case 0: 1917 Opc = ARM_AM::lsl; 1918 break; 1919 case 1: 1920 Opc = ARM_AM::lsr; 1921 break; 1922 case 2: 1923 Opc = ARM_AM::asr; 1924 break; 1925 case 3: 1926 Opc = ARM_AM::ror; 1927 break; 1928 default: 1929 return MCDisassembler::Fail; 1930 } 1931 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1932 if (Opc == ARM_AM::ror && amt == 0) 1933 Opc = ARM_AM::rrx; 1934 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1935 1936 Inst.addOperand(MCOperand::createImm(imm)); 1937 } else { 1938 Inst.addOperand(MCOperand::createReg(0)); 1939 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1940 Inst.addOperand(MCOperand::createImm(tmp)); 1941 } 1942 1943 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1944 return MCDisassembler::Fail; 1945 1946 return S; 1947 } 1948 1949 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1950 uint64_t Address, const void *Decoder) { 1951 DecodeStatus S = MCDisassembler::Success; 1952 1953 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1954 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1955 unsigned type = fieldFromInstruction(Val, 5, 2); 1956 unsigned imm = fieldFromInstruction(Val, 7, 5); 1957 unsigned U = fieldFromInstruction(Val, 12, 1); 1958 1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1960 switch (type) { 1961 case 0: 1962 ShOp = ARM_AM::lsl; 1963 break; 1964 case 1: 1965 ShOp = ARM_AM::lsr; 1966 break; 1967 case 2: 1968 ShOp = ARM_AM::asr; 1969 break; 1970 case 3: 1971 ShOp = ARM_AM::ror; 1972 break; 1973 } 1974 1975 if (ShOp == ARM_AM::ror && imm == 0) 1976 ShOp = ARM_AM::rrx; 1977 1978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1979 return MCDisassembler::Fail; 1980 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1981 return MCDisassembler::Fail; 1982 unsigned shift; 1983 if (U) 1984 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1985 else 1986 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1987 Inst.addOperand(MCOperand::createImm(shift)); 1988 1989 return S; 1990 } 1991 1992 static DecodeStatus 1993 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1994 uint64_t Address, const void *Decoder) { 1995 DecodeStatus S = MCDisassembler::Success; 1996 1997 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1998 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1999 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2000 unsigned type = fieldFromInstruction(Insn, 22, 1); 2001 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2002 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2003 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2004 unsigned W = fieldFromInstruction(Insn, 21, 1); 2005 unsigned P = fieldFromInstruction(Insn, 24, 1); 2006 unsigned Rt2 = Rt + 1; 2007 2008 bool writeback = (W == 1) | (P == 0); 2009 2010 // For {LD,ST}RD, Rt must be even, else undefined. 2011 switch (Inst.getOpcode()) { 2012 case ARM::STRD: 2013 case ARM::STRD_PRE: 2014 case ARM::STRD_POST: 2015 case ARM::LDRD: 2016 case ARM::LDRD_PRE: 2017 case ARM::LDRD_POST: 2018 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2019 break; 2020 default: 2021 break; 2022 } 2023 switch (Inst.getOpcode()) { 2024 case ARM::STRD: 2025 case ARM::STRD_PRE: 2026 case ARM::STRD_POST: 2027 if (P == 0 && W == 1) 2028 S = MCDisassembler::SoftFail; 2029 2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2031 S = MCDisassembler::SoftFail; 2032 if (type && Rm == 15) 2033 S = MCDisassembler::SoftFail; 2034 if (Rt2 == 15) 2035 S = MCDisassembler::SoftFail; 2036 if (!type && fieldFromInstruction(Insn, 8, 4)) 2037 S = MCDisassembler::SoftFail; 2038 break; 2039 case ARM::STRH: 2040 case ARM::STRH_PRE: 2041 case ARM::STRH_POST: 2042 if (Rt == 15) 2043 S = MCDisassembler::SoftFail; 2044 if (writeback && (Rn == 15 || Rn == Rt)) 2045 S = MCDisassembler::SoftFail; 2046 if (!type && Rm == 15) 2047 S = MCDisassembler::SoftFail; 2048 break; 2049 case ARM::LDRD: 2050 case ARM::LDRD_PRE: 2051 case ARM::LDRD_POST: 2052 if (type && Rn == 15) { 2053 if (Rt2 == 15) 2054 S = MCDisassembler::SoftFail; 2055 break; 2056 } 2057 if (P == 0 && W == 1) 2058 S = MCDisassembler::SoftFail; 2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2060 S = MCDisassembler::SoftFail; 2061 if (!type && writeback && Rn == 15) 2062 S = MCDisassembler::SoftFail; 2063 if (writeback && (Rn == Rt || Rn == Rt2)) 2064 S = MCDisassembler::SoftFail; 2065 break; 2066 case ARM::LDRH: 2067 case ARM::LDRH_PRE: 2068 case ARM::LDRH_POST: 2069 if (type && Rn == 15) { 2070 if (Rt == 15) 2071 S = MCDisassembler::SoftFail; 2072 break; 2073 } 2074 if (Rt == 15) 2075 S = MCDisassembler::SoftFail; 2076 if (!type && Rm == 15) 2077 S = MCDisassembler::SoftFail; 2078 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2079 S = MCDisassembler::SoftFail; 2080 break; 2081 case ARM::LDRSH: 2082 case ARM::LDRSH_PRE: 2083 case ARM::LDRSH_POST: 2084 case ARM::LDRSB: 2085 case ARM::LDRSB_PRE: 2086 case ARM::LDRSB_POST: 2087 if (type && Rn == 15) { 2088 if (Rt == 15) 2089 S = MCDisassembler::SoftFail; 2090 break; 2091 } 2092 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2093 S = MCDisassembler::SoftFail; 2094 if (!type && (Rt == 15 || Rm == 15)) 2095 S = MCDisassembler::SoftFail; 2096 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2097 S = MCDisassembler::SoftFail; 2098 break; 2099 default: 2100 break; 2101 } 2102 2103 if (writeback) { // Writeback 2104 if (P) 2105 U |= ARMII::IndexModePre << 9; 2106 else 2107 U |= ARMII::IndexModePost << 9; 2108 2109 // On stores, the writeback operand precedes Rt. 2110 switch (Inst.getOpcode()) { 2111 case ARM::STRD: 2112 case ARM::STRD_PRE: 2113 case ARM::STRD_POST: 2114 case ARM::STRH: 2115 case ARM::STRH_PRE: 2116 case ARM::STRH_POST: 2117 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2118 return MCDisassembler::Fail; 2119 break; 2120 default: 2121 break; 2122 } 2123 } 2124 2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2126 return MCDisassembler::Fail; 2127 switch (Inst.getOpcode()) { 2128 case ARM::STRD: 2129 case ARM::STRD_PRE: 2130 case ARM::STRD_POST: 2131 case ARM::LDRD: 2132 case ARM::LDRD_PRE: 2133 case ARM::LDRD_POST: 2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2135 return MCDisassembler::Fail; 2136 break; 2137 default: 2138 break; 2139 } 2140 2141 if (writeback) { 2142 // On loads, the writeback operand comes after Rt. 2143 switch (Inst.getOpcode()) { 2144 case ARM::LDRD: 2145 case ARM::LDRD_PRE: 2146 case ARM::LDRD_POST: 2147 case ARM::LDRH: 2148 case ARM::LDRH_PRE: 2149 case ARM::LDRH_POST: 2150 case ARM::LDRSH: 2151 case ARM::LDRSH_PRE: 2152 case ARM::LDRSH_POST: 2153 case ARM::LDRSB: 2154 case ARM::LDRSB_PRE: 2155 case ARM::LDRSB_POST: 2156 case ARM::LDRHTr: 2157 case ARM::LDRSBTr: 2158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2159 return MCDisassembler::Fail; 2160 break; 2161 default: 2162 break; 2163 } 2164 } 2165 2166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2167 return MCDisassembler::Fail; 2168 2169 if (type) { 2170 Inst.addOperand(MCOperand::createReg(0)); 2171 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2172 } else { 2173 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2174 return MCDisassembler::Fail; 2175 Inst.addOperand(MCOperand::createImm(U)); 2176 } 2177 2178 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2179 return MCDisassembler::Fail; 2180 2181 return S; 2182 } 2183 2184 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2185 uint64_t Address, const void *Decoder) { 2186 DecodeStatus S = MCDisassembler::Success; 2187 2188 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2189 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2190 2191 switch (mode) { 2192 case 0: 2193 mode = ARM_AM::da; 2194 break; 2195 case 1: 2196 mode = ARM_AM::ia; 2197 break; 2198 case 2: 2199 mode = ARM_AM::db; 2200 break; 2201 case 3: 2202 mode = ARM_AM::ib; 2203 break; 2204 } 2205 2206 Inst.addOperand(MCOperand::createImm(mode)); 2207 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2208 return MCDisassembler::Fail; 2209 2210 return S; 2211 } 2212 2213 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2214 uint64_t Address, const void *Decoder) { 2215 DecodeStatus S = MCDisassembler::Success; 2216 2217 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2218 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2219 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2220 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2221 2222 if (pred == 0xF) 2223 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2224 2225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2226 return MCDisassembler::Fail; 2227 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2230 return MCDisassembler::Fail; 2231 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2232 return MCDisassembler::Fail; 2233 return S; 2234 } 2235 2236 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 2237 unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 DecodeStatus S = MCDisassembler::Success; 2240 2241 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2242 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2243 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2244 2245 if (pred == 0xF) { 2246 // Ambiguous with RFE and SRS 2247 switch (Inst.getOpcode()) { 2248 case ARM::LDMDA: 2249 Inst.setOpcode(ARM::RFEDA); 2250 break; 2251 case ARM::LDMDA_UPD: 2252 Inst.setOpcode(ARM::RFEDA_UPD); 2253 break; 2254 case ARM::LDMDB: 2255 Inst.setOpcode(ARM::RFEDB); 2256 break; 2257 case ARM::LDMDB_UPD: 2258 Inst.setOpcode(ARM::RFEDB_UPD); 2259 break; 2260 case ARM::LDMIA: 2261 Inst.setOpcode(ARM::RFEIA); 2262 break; 2263 case ARM::LDMIA_UPD: 2264 Inst.setOpcode(ARM::RFEIA_UPD); 2265 break; 2266 case ARM::LDMIB: 2267 Inst.setOpcode(ARM::RFEIB); 2268 break; 2269 case ARM::LDMIB_UPD: 2270 Inst.setOpcode(ARM::RFEIB_UPD); 2271 break; 2272 case ARM::STMDA: 2273 Inst.setOpcode(ARM::SRSDA); 2274 break; 2275 case ARM::STMDA_UPD: 2276 Inst.setOpcode(ARM::SRSDA_UPD); 2277 break; 2278 case ARM::STMDB: 2279 Inst.setOpcode(ARM::SRSDB); 2280 break; 2281 case ARM::STMDB_UPD: 2282 Inst.setOpcode(ARM::SRSDB_UPD); 2283 break; 2284 case ARM::STMIA: 2285 Inst.setOpcode(ARM::SRSIA); 2286 break; 2287 case ARM::STMIA_UPD: 2288 Inst.setOpcode(ARM::SRSIA_UPD); 2289 break; 2290 case ARM::STMIB: 2291 Inst.setOpcode(ARM::SRSIB); 2292 break; 2293 case ARM::STMIB_UPD: 2294 Inst.setOpcode(ARM::SRSIB_UPD); 2295 break; 2296 default: 2297 return MCDisassembler::Fail; 2298 } 2299 2300 // For stores (which become SRS's, the only operand is the mode. 2301 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2302 // Check SRS encoding constraints 2303 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2304 fieldFromInstruction(Insn, 20, 1) == 0)) 2305 return MCDisassembler::Fail; 2306 2307 Inst.addOperand( 2308 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2309 return S; 2310 } 2311 2312 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2313 } 2314 2315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2316 return MCDisassembler::Fail; 2317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2318 return MCDisassembler::Fail; // Tied 2319 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2320 return MCDisassembler::Fail; 2321 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2322 return MCDisassembler::Fail; 2323 2324 return S; 2325 } 2326 2327 // Check for UNPREDICTABLE predicated ESB instruction 2328 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2329 uint64_t Address, const void *Decoder) { 2330 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2331 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2332 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2333 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2334 2335 DecodeStatus S = MCDisassembler::Success; 2336 2337 Inst.addOperand(MCOperand::createImm(imm8)); 2338 2339 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2340 return MCDisassembler::Fail; 2341 2342 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2343 // so all predicates should be allowed. 2344 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2345 S = MCDisassembler::SoftFail; 2346 2347 return S; 2348 } 2349 2350 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2351 uint64_t Address, const void *Decoder) { 2352 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2353 unsigned M = fieldFromInstruction(Insn, 17, 1); 2354 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2355 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2356 2357 DecodeStatus S = MCDisassembler::Success; 2358 2359 // This decoder is called from multiple location that do not check 2360 // the full encoding is valid before they do. 2361 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2362 fieldFromInstruction(Insn, 16, 1) != 0 || 2363 fieldFromInstruction(Insn, 20, 8) != 0x10) 2364 return MCDisassembler::Fail; 2365 2366 // imod == '01' --> UNPREDICTABLE 2367 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2368 // return failure here. The '01' imod value is unprintable, so there's 2369 // nothing useful we could do even if we returned UNPREDICTABLE. 2370 2371 if (imod == 1) return MCDisassembler::Fail; 2372 2373 if (imod && M) { 2374 Inst.setOpcode(ARM::CPS3p); 2375 Inst.addOperand(MCOperand::createImm(imod)); 2376 Inst.addOperand(MCOperand::createImm(iflags)); 2377 Inst.addOperand(MCOperand::createImm(mode)); 2378 } else if (imod && !M) { 2379 Inst.setOpcode(ARM::CPS2p); 2380 Inst.addOperand(MCOperand::createImm(imod)); 2381 Inst.addOperand(MCOperand::createImm(iflags)); 2382 if (mode) S = MCDisassembler::SoftFail; 2383 } else if (!imod && M) { 2384 Inst.setOpcode(ARM::CPS1p); 2385 Inst.addOperand(MCOperand::createImm(mode)); 2386 if (iflags) S = MCDisassembler::SoftFail; 2387 } else { 2388 // imod == '00' && M == '0' --> UNPREDICTABLE 2389 Inst.setOpcode(ARM::CPS1p); 2390 Inst.addOperand(MCOperand::createImm(mode)); 2391 S = MCDisassembler::SoftFail; 2392 } 2393 2394 return S; 2395 } 2396 2397 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2398 uint64_t Address, const void *Decoder) { 2399 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2400 unsigned M = fieldFromInstruction(Insn, 8, 1); 2401 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2402 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2403 2404 DecodeStatus S = MCDisassembler::Success; 2405 2406 // imod == '01' --> UNPREDICTABLE 2407 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2408 // return failure here. The '01' imod value is unprintable, so there's 2409 // nothing useful we could do even if we returned UNPREDICTABLE. 2410 2411 if (imod == 1) return MCDisassembler::Fail; 2412 2413 if (imod && M) { 2414 Inst.setOpcode(ARM::t2CPS3p); 2415 Inst.addOperand(MCOperand::createImm(imod)); 2416 Inst.addOperand(MCOperand::createImm(iflags)); 2417 Inst.addOperand(MCOperand::createImm(mode)); 2418 } else if (imod && !M) { 2419 Inst.setOpcode(ARM::t2CPS2p); 2420 Inst.addOperand(MCOperand::createImm(imod)); 2421 Inst.addOperand(MCOperand::createImm(iflags)); 2422 if (mode) S = MCDisassembler::SoftFail; 2423 } else if (!imod && M) { 2424 Inst.setOpcode(ARM::t2CPS1p); 2425 Inst.addOperand(MCOperand::createImm(mode)); 2426 if (iflags) S = MCDisassembler::SoftFail; 2427 } else { 2428 // imod == '00' && M == '0' --> this is a HINT instruction 2429 int imm = fieldFromInstruction(Insn, 0, 8); 2430 // HINT are defined only for immediate in [0..4] 2431 if(imm > 4) return MCDisassembler::Fail; 2432 Inst.setOpcode(ARM::t2HINT); 2433 Inst.addOperand(MCOperand::createImm(imm)); 2434 } 2435 2436 return S; 2437 } 2438 2439 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2440 uint64_t Address, const void *Decoder) { 2441 DecodeStatus S = MCDisassembler::Success; 2442 2443 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2444 unsigned imm = 0; 2445 2446 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2447 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2448 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2449 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2450 2451 if (Inst.getOpcode() == ARM::t2MOVTi16) 2452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2453 return MCDisassembler::Fail; 2454 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2455 return MCDisassembler::Fail; 2456 2457 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2458 Inst.addOperand(MCOperand::createImm(imm)); 2459 2460 return S; 2461 } 2462 2463 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2464 uint64_t Address, const void *Decoder) { 2465 DecodeStatus S = MCDisassembler::Success; 2466 2467 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2468 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2469 unsigned imm = 0; 2470 2471 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2472 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2473 2474 if (Inst.getOpcode() == ARM::MOVTi16) 2475 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2476 return MCDisassembler::Fail; 2477 2478 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2479 return MCDisassembler::Fail; 2480 2481 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2482 Inst.addOperand(MCOperand::createImm(imm)); 2483 2484 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2485 return MCDisassembler::Fail; 2486 2487 return S; 2488 } 2489 2490 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2491 uint64_t Address, const void *Decoder) { 2492 DecodeStatus S = MCDisassembler::Success; 2493 2494 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2495 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2496 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2497 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2498 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2499 2500 if (pred == 0xF) 2501 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2502 2503 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2504 return MCDisassembler::Fail; 2505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2506 return MCDisassembler::Fail; 2507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2508 return MCDisassembler::Fail; 2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2510 return MCDisassembler::Fail; 2511 2512 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2513 return MCDisassembler::Fail; 2514 2515 return S; 2516 } 2517 2518 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2519 uint64_t Address, const void *Decoder) { 2520 DecodeStatus S = MCDisassembler::Success; 2521 2522 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2523 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2524 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2525 2526 if (Pred == 0xF) 2527 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2528 2529 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2530 return MCDisassembler::Fail; 2531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2532 return MCDisassembler::Fail; 2533 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2534 return MCDisassembler::Fail; 2535 2536 return S; 2537 } 2538 2539 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2540 uint64_t Address, const void *Decoder) { 2541 DecodeStatus S = MCDisassembler::Success; 2542 2543 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2544 2545 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2546 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2547 2548 if (!FeatureBits[ARM::HasV8_1aOps] || 2549 !FeatureBits[ARM::HasV8Ops]) 2550 return MCDisassembler::Fail; 2551 2552 // Decoder can be called from DecodeTST, which does not check the full 2553 // encoding is valid. 2554 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2555 fieldFromInstruction(Insn, 4,4) != 0) 2556 return MCDisassembler::Fail; 2557 if (fieldFromInstruction(Insn, 10,10) != 0 || 2558 fieldFromInstruction(Insn, 0,4) != 0) 2559 S = MCDisassembler::SoftFail; 2560 2561 Inst.setOpcode(ARM::SETPAN); 2562 Inst.addOperand(MCOperand::createImm(Imm)); 2563 2564 return S; 2565 } 2566 2567 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2568 uint64_t Address, const void *Decoder) { 2569 DecodeStatus S = MCDisassembler::Success; 2570 2571 unsigned add = fieldFromInstruction(Val, 12, 1); 2572 unsigned imm = fieldFromInstruction(Val, 0, 12); 2573 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2574 2575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2576 return MCDisassembler::Fail; 2577 2578 if (!add) imm *= -1; 2579 if (imm == 0 && !add) imm = INT32_MIN; 2580 Inst.addOperand(MCOperand::createImm(imm)); 2581 if (Rn == 15) 2582 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2583 2584 return S; 2585 } 2586 2587 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2588 uint64_t Address, const void *Decoder) { 2589 DecodeStatus S = MCDisassembler::Success; 2590 2591 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2592 // U == 1 to add imm, 0 to subtract it. 2593 unsigned U = fieldFromInstruction(Val, 8, 1); 2594 unsigned imm = fieldFromInstruction(Val, 0, 8); 2595 2596 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2597 return MCDisassembler::Fail; 2598 2599 if (U) 2600 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2601 else 2602 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2603 2604 return S; 2605 } 2606 2607 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2608 uint64_t Address, const void *Decoder) { 2609 DecodeStatus S = MCDisassembler::Success; 2610 2611 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2612 // U == 1 to add imm, 0 to subtract it. 2613 unsigned U = fieldFromInstruction(Val, 8, 1); 2614 unsigned imm = fieldFromInstruction(Val, 0, 8); 2615 2616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2617 return MCDisassembler::Fail; 2618 2619 if (U) 2620 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2621 else 2622 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2623 2624 return S; 2625 } 2626 2627 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2628 uint64_t Address, const void *Decoder) { 2629 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2630 } 2631 2632 static DecodeStatus 2633 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2634 uint64_t Address, const void *Decoder) { 2635 DecodeStatus Status = MCDisassembler::Success; 2636 2637 // Note the J1 and J2 values are from the encoded instruction. So here 2638 // change them to I1 and I2 values via as documented: 2639 // I1 = NOT(J1 EOR S); 2640 // I2 = NOT(J2 EOR S); 2641 // and build the imm32 with one trailing zero as documented: 2642 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2643 unsigned S = fieldFromInstruction(Insn, 26, 1); 2644 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2645 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2646 unsigned I1 = !(J1 ^ S); 2647 unsigned I2 = !(J2 ^ S); 2648 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2649 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2650 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2651 int imm32 = SignExtend32<25>(tmp << 1); 2652 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2653 true, 4, Inst, Decoder)) 2654 Inst.addOperand(MCOperand::createImm(imm32)); 2655 2656 return Status; 2657 } 2658 2659 static DecodeStatus 2660 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2661 uint64_t Address, const void *Decoder) { 2662 DecodeStatus S = MCDisassembler::Success; 2663 2664 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2665 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2666 2667 if (pred == 0xF) { 2668 Inst.setOpcode(ARM::BLXi); 2669 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2670 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2671 true, 4, Inst, Decoder)) 2672 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2673 return S; 2674 } 2675 2676 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2677 true, 4, Inst, Decoder)) 2678 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2679 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2680 return MCDisassembler::Fail; 2681 2682 return S; 2683 } 2684 2685 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2686 uint64_t Address, const void *Decoder) { 2687 DecodeStatus S = MCDisassembler::Success; 2688 2689 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2690 unsigned align = fieldFromInstruction(Val, 4, 2); 2691 2692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2693 return MCDisassembler::Fail; 2694 if (!align) 2695 Inst.addOperand(MCOperand::createImm(0)); 2696 else 2697 Inst.addOperand(MCOperand::createImm(4 << align)); 2698 2699 return S; 2700 } 2701 2702 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2703 uint64_t Address, const void *Decoder) { 2704 DecodeStatus S = MCDisassembler::Success; 2705 2706 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2707 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2708 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2709 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2710 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2711 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2712 2713 // First output register 2714 switch (Inst.getOpcode()) { 2715 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2716 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2717 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2718 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2719 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2720 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2721 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2722 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2723 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2724 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2725 return MCDisassembler::Fail; 2726 break; 2727 case ARM::VLD2b16: 2728 case ARM::VLD2b32: 2729 case ARM::VLD2b8: 2730 case ARM::VLD2b16wb_fixed: 2731 case ARM::VLD2b16wb_register: 2732 case ARM::VLD2b32wb_fixed: 2733 case ARM::VLD2b32wb_register: 2734 case ARM::VLD2b8wb_fixed: 2735 case ARM::VLD2b8wb_register: 2736 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2737 return MCDisassembler::Fail; 2738 break; 2739 default: 2740 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2741 return MCDisassembler::Fail; 2742 } 2743 2744 // Second output register 2745 switch (Inst.getOpcode()) { 2746 case ARM::VLD3d8: 2747 case ARM::VLD3d16: 2748 case ARM::VLD3d32: 2749 case ARM::VLD3d8_UPD: 2750 case ARM::VLD3d16_UPD: 2751 case ARM::VLD3d32_UPD: 2752 case ARM::VLD4d8: 2753 case ARM::VLD4d16: 2754 case ARM::VLD4d32: 2755 case ARM::VLD4d8_UPD: 2756 case ARM::VLD4d16_UPD: 2757 case ARM::VLD4d32_UPD: 2758 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2759 return MCDisassembler::Fail; 2760 break; 2761 case ARM::VLD3q8: 2762 case ARM::VLD3q16: 2763 case ARM::VLD3q32: 2764 case ARM::VLD3q8_UPD: 2765 case ARM::VLD3q16_UPD: 2766 case ARM::VLD3q32_UPD: 2767 case ARM::VLD4q8: 2768 case ARM::VLD4q16: 2769 case ARM::VLD4q32: 2770 case ARM::VLD4q8_UPD: 2771 case ARM::VLD4q16_UPD: 2772 case ARM::VLD4q32_UPD: 2773 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2774 return MCDisassembler::Fail; 2775 break; 2776 default: 2777 break; 2778 } 2779 2780 // Third output register 2781 switch(Inst.getOpcode()) { 2782 case ARM::VLD3d8: 2783 case ARM::VLD3d16: 2784 case ARM::VLD3d32: 2785 case ARM::VLD3d8_UPD: 2786 case ARM::VLD3d16_UPD: 2787 case ARM::VLD3d32_UPD: 2788 case ARM::VLD4d8: 2789 case ARM::VLD4d16: 2790 case ARM::VLD4d32: 2791 case ARM::VLD4d8_UPD: 2792 case ARM::VLD4d16_UPD: 2793 case ARM::VLD4d32_UPD: 2794 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2795 return MCDisassembler::Fail; 2796 break; 2797 case ARM::VLD3q8: 2798 case ARM::VLD3q16: 2799 case ARM::VLD3q32: 2800 case ARM::VLD3q8_UPD: 2801 case ARM::VLD3q16_UPD: 2802 case ARM::VLD3q32_UPD: 2803 case ARM::VLD4q8: 2804 case ARM::VLD4q16: 2805 case ARM::VLD4q32: 2806 case ARM::VLD4q8_UPD: 2807 case ARM::VLD4q16_UPD: 2808 case ARM::VLD4q32_UPD: 2809 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2810 return MCDisassembler::Fail; 2811 break; 2812 default: 2813 break; 2814 } 2815 2816 // Fourth output register 2817 switch (Inst.getOpcode()) { 2818 case ARM::VLD4d8: 2819 case ARM::VLD4d16: 2820 case ARM::VLD4d32: 2821 case ARM::VLD4d8_UPD: 2822 case ARM::VLD4d16_UPD: 2823 case ARM::VLD4d32_UPD: 2824 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2825 return MCDisassembler::Fail; 2826 break; 2827 case ARM::VLD4q8: 2828 case ARM::VLD4q16: 2829 case ARM::VLD4q32: 2830 case ARM::VLD4q8_UPD: 2831 case ARM::VLD4q16_UPD: 2832 case ARM::VLD4q32_UPD: 2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2834 return MCDisassembler::Fail; 2835 break; 2836 default: 2837 break; 2838 } 2839 2840 // Writeback operand 2841 switch (Inst.getOpcode()) { 2842 case ARM::VLD1d8wb_fixed: 2843 case ARM::VLD1d16wb_fixed: 2844 case ARM::VLD1d32wb_fixed: 2845 case ARM::VLD1d64wb_fixed: 2846 case ARM::VLD1d8wb_register: 2847 case ARM::VLD1d16wb_register: 2848 case ARM::VLD1d32wb_register: 2849 case ARM::VLD1d64wb_register: 2850 case ARM::VLD1q8wb_fixed: 2851 case ARM::VLD1q16wb_fixed: 2852 case ARM::VLD1q32wb_fixed: 2853 case ARM::VLD1q64wb_fixed: 2854 case ARM::VLD1q8wb_register: 2855 case ARM::VLD1q16wb_register: 2856 case ARM::VLD1q32wb_register: 2857 case ARM::VLD1q64wb_register: 2858 case ARM::VLD1d8Twb_fixed: 2859 case ARM::VLD1d8Twb_register: 2860 case ARM::VLD1d16Twb_fixed: 2861 case ARM::VLD1d16Twb_register: 2862 case ARM::VLD1d32Twb_fixed: 2863 case ARM::VLD1d32Twb_register: 2864 case ARM::VLD1d64Twb_fixed: 2865 case ARM::VLD1d64Twb_register: 2866 case ARM::VLD1d8Qwb_fixed: 2867 case ARM::VLD1d8Qwb_register: 2868 case ARM::VLD1d16Qwb_fixed: 2869 case ARM::VLD1d16Qwb_register: 2870 case ARM::VLD1d32Qwb_fixed: 2871 case ARM::VLD1d32Qwb_register: 2872 case ARM::VLD1d64Qwb_fixed: 2873 case ARM::VLD1d64Qwb_register: 2874 case ARM::VLD2d8wb_fixed: 2875 case ARM::VLD2d16wb_fixed: 2876 case ARM::VLD2d32wb_fixed: 2877 case ARM::VLD2q8wb_fixed: 2878 case ARM::VLD2q16wb_fixed: 2879 case ARM::VLD2q32wb_fixed: 2880 case ARM::VLD2d8wb_register: 2881 case ARM::VLD2d16wb_register: 2882 case ARM::VLD2d32wb_register: 2883 case ARM::VLD2q8wb_register: 2884 case ARM::VLD2q16wb_register: 2885 case ARM::VLD2q32wb_register: 2886 case ARM::VLD2b8wb_fixed: 2887 case ARM::VLD2b16wb_fixed: 2888 case ARM::VLD2b32wb_fixed: 2889 case ARM::VLD2b8wb_register: 2890 case ARM::VLD2b16wb_register: 2891 case ARM::VLD2b32wb_register: 2892 Inst.addOperand(MCOperand::createImm(0)); 2893 break; 2894 case ARM::VLD3d8_UPD: 2895 case ARM::VLD3d16_UPD: 2896 case ARM::VLD3d32_UPD: 2897 case ARM::VLD3q8_UPD: 2898 case ARM::VLD3q16_UPD: 2899 case ARM::VLD3q32_UPD: 2900 case ARM::VLD4d8_UPD: 2901 case ARM::VLD4d16_UPD: 2902 case ARM::VLD4d32_UPD: 2903 case ARM::VLD4q8_UPD: 2904 case ARM::VLD4q16_UPD: 2905 case ARM::VLD4q32_UPD: 2906 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2907 return MCDisassembler::Fail; 2908 break; 2909 default: 2910 break; 2911 } 2912 2913 // AddrMode6 Base (register+alignment) 2914 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2915 return MCDisassembler::Fail; 2916 2917 // AddrMode6 Offset (register) 2918 switch (Inst.getOpcode()) { 2919 default: 2920 // The below have been updated to have explicit am6offset split 2921 // between fixed and register offset. For those instructions not 2922 // yet updated, we need to add an additional reg0 operand for the 2923 // fixed variant. 2924 // 2925 // The fixed offset encodes as Rm == 0xd, so we check for that. 2926 if (Rm == 0xd) { 2927 Inst.addOperand(MCOperand::createReg(0)); 2928 break; 2929 } 2930 // Fall through to handle the register offset variant. 2931 LLVM_FALLTHROUGH; 2932 case ARM::VLD1d8wb_fixed: 2933 case ARM::VLD1d16wb_fixed: 2934 case ARM::VLD1d32wb_fixed: 2935 case ARM::VLD1d64wb_fixed: 2936 case ARM::VLD1d8Twb_fixed: 2937 case ARM::VLD1d16Twb_fixed: 2938 case ARM::VLD1d32Twb_fixed: 2939 case ARM::VLD1d64Twb_fixed: 2940 case ARM::VLD1d8Qwb_fixed: 2941 case ARM::VLD1d16Qwb_fixed: 2942 case ARM::VLD1d32Qwb_fixed: 2943 case ARM::VLD1d64Qwb_fixed: 2944 case ARM::VLD1d8wb_register: 2945 case ARM::VLD1d16wb_register: 2946 case ARM::VLD1d32wb_register: 2947 case ARM::VLD1d64wb_register: 2948 case ARM::VLD1q8wb_fixed: 2949 case ARM::VLD1q16wb_fixed: 2950 case ARM::VLD1q32wb_fixed: 2951 case ARM::VLD1q64wb_fixed: 2952 case ARM::VLD1q8wb_register: 2953 case ARM::VLD1q16wb_register: 2954 case ARM::VLD1q32wb_register: 2955 case ARM::VLD1q64wb_register: 2956 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2957 // variant encodes Rm == 0xf. Anything else is a register offset post- 2958 // increment and we need to add the register operand to the instruction. 2959 if (Rm != 0xD && Rm != 0xF && 2960 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2961 return MCDisassembler::Fail; 2962 break; 2963 case ARM::VLD2d8wb_fixed: 2964 case ARM::VLD2d16wb_fixed: 2965 case ARM::VLD2d32wb_fixed: 2966 case ARM::VLD2b8wb_fixed: 2967 case ARM::VLD2b16wb_fixed: 2968 case ARM::VLD2b32wb_fixed: 2969 case ARM::VLD2q8wb_fixed: 2970 case ARM::VLD2q16wb_fixed: 2971 case ARM::VLD2q32wb_fixed: 2972 break; 2973 } 2974 2975 return S; 2976 } 2977 2978 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2979 uint64_t Address, const void *Decoder) { 2980 unsigned type = fieldFromInstruction(Insn, 8, 4); 2981 unsigned align = fieldFromInstruction(Insn, 4, 2); 2982 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2983 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2984 if (type == 10 && align == 3) return MCDisassembler::Fail; 2985 2986 unsigned load = fieldFromInstruction(Insn, 21, 1); 2987 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2988 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2989 } 2990 2991 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2992 uint64_t Address, const void *Decoder) { 2993 unsigned size = fieldFromInstruction(Insn, 6, 2); 2994 if (size == 3) return MCDisassembler::Fail; 2995 2996 unsigned type = fieldFromInstruction(Insn, 8, 4); 2997 unsigned align = fieldFromInstruction(Insn, 4, 2); 2998 if (type == 8 && align == 3) return MCDisassembler::Fail; 2999 if (type == 9 && align == 3) return MCDisassembler::Fail; 3000 3001 unsigned load = fieldFromInstruction(Insn, 21, 1); 3002 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3003 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3004 } 3005 3006 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3007 uint64_t Address, const void *Decoder) { 3008 unsigned size = fieldFromInstruction(Insn, 6, 2); 3009 if (size == 3) return MCDisassembler::Fail; 3010 3011 unsigned align = fieldFromInstruction(Insn, 4, 2); 3012 if (align & 2) return MCDisassembler::Fail; 3013 3014 unsigned load = fieldFromInstruction(Insn, 21, 1); 3015 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3016 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3017 } 3018 3019 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3020 uint64_t Address, const void *Decoder) { 3021 unsigned size = fieldFromInstruction(Insn, 6, 2); 3022 if (size == 3) return MCDisassembler::Fail; 3023 3024 unsigned load = fieldFromInstruction(Insn, 21, 1); 3025 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3026 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3027 } 3028 3029 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3030 uint64_t Address, const void *Decoder) { 3031 DecodeStatus S = MCDisassembler::Success; 3032 3033 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3034 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3035 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3036 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3037 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3038 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3039 3040 // Writeback Operand 3041 switch (Inst.getOpcode()) { 3042 case ARM::VST1d8wb_fixed: 3043 case ARM::VST1d16wb_fixed: 3044 case ARM::VST1d32wb_fixed: 3045 case ARM::VST1d64wb_fixed: 3046 case ARM::VST1d8wb_register: 3047 case ARM::VST1d16wb_register: 3048 case ARM::VST1d32wb_register: 3049 case ARM::VST1d64wb_register: 3050 case ARM::VST1q8wb_fixed: 3051 case ARM::VST1q16wb_fixed: 3052 case ARM::VST1q32wb_fixed: 3053 case ARM::VST1q64wb_fixed: 3054 case ARM::VST1q8wb_register: 3055 case ARM::VST1q16wb_register: 3056 case ARM::VST1q32wb_register: 3057 case ARM::VST1q64wb_register: 3058 case ARM::VST1d8Twb_fixed: 3059 case ARM::VST1d16Twb_fixed: 3060 case ARM::VST1d32Twb_fixed: 3061 case ARM::VST1d64Twb_fixed: 3062 case ARM::VST1d8Twb_register: 3063 case ARM::VST1d16Twb_register: 3064 case ARM::VST1d32Twb_register: 3065 case ARM::VST1d64Twb_register: 3066 case ARM::VST1d8Qwb_fixed: 3067 case ARM::VST1d16Qwb_fixed: 3068 case ARM::VST1d32Qwb_fixed: 3069 case ARM::VST1d64Qwb_fixed: 3070 case ARM::VST1d8Qwb_register: 3071 case ARM::VST1d16Qwb_register: 3072 case ARM::VST1d32Qwb_register: 3073 case ARM::VST1d64Qwb_register: 3074 case ARM::VST2d8wb_fixed: 3075 case ARM::VST2d16wb_fixed: 3076 case ARM::VST2d32wb_fixed: 3077 case ARM::VST2d8wb_register: 3078 case ARM::VST2d16wb_register: 3079 case ARM::VST2d32wb_register: 3080 case ARM::VST2q8wb_fixed: 3081 case ARM::VST2q16wb_fixed: 3082 case ARM::VST2q32wb_fixed: 3083 case ARM::VST2q8wb_register: 3084 case ARM::VST2q16wb_register: 3085 case ARM::VST2q32wb_register: 3086 case ARM::VST2b8wb_fixed: 3087 case ARM::VST2b16wb_fixed: 3088 case ARM::VST2b32wb_fixed: 3089 case ARM::VST2b8wb_register: 3090 case ARM::VST2b16wb_register: 3091 case ARM::VST2b32wb_register: 3092 if (Rm == 0xF) 3093 return MCDisassembler::Fail; 3094 Inst.addOperand(MCOperand::createImm(0)); 3095 break; 3096 case ARM::VST3d8_UPD: 3097 case ARM::VST3d16_UPD: 3098 case ARM::VST3d32_UPD: 3099 case ARM::VST3q8_UPD: 3100 case ARM::VST3q16_UPD: 3101 case ARM::VST3q32_UPD: 3102 case ARM::VST4d8_UPD: 3103 case ARM::VST4d16_UPD: 3104 case ARM::VST4d32_UPD: 3105 case ARM::VST4q8_UPD: 3106 case ARM::VST4q16_UPD: 3107 case ARM::VST4q32_UPD: 3108 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3109 return MCDisassembler::Fail; 3110 break; 3111 default: 3112 break; 3113 } 3114 3115 // AddrMode6 Base (register+alignment) 3116 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 3119 // AddrMode6 Offset (register) 3120 switch (Inst.getOpcode()) { 3121 default: 3122 if (Rm == 0xD) 3123 Inst.addOperand(MCOperand::createReg(0)); 3124 else if (Rm != 0xF) { 3125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3126 return MCDisassembler::Fail; 3127 } 3128 break; 3129 case ARM::VST1d8wb_fixed: 3130 case ARM::VST1d16wb_fixed: 3131 case ARM::VST1d32wb_fixed: 3132 case ARM::VST1d64wb_fixed: 3133 case ARM::VST1q8wb_fixed: 3134 case ARM::VST1q16wb_fixed: 3135 case ARM::VST1q32wb_fixed: 3136 case ARM::VST1q64wb_fixed: 3137 case ARM::VST1d8Twb_fixed: 3138 case ARM::VST1d16Twb_fixed: 3139 case ARM::VST1d32Twb_fixed: 3140 case ARM::VST1d64Twb_fixed: 3141 case ARM::VST1d8Qwb_fixed: 3142 case ARM::VST1d16Qwb_fixed: 3143 case ARM::VST1d32Qwb_fixed: 3144 case ARM::VST1d64Qwb_fixed: 3145 case ARM::VST2d8wb_fixed: 3146 case ARM::VST2d16wb_fixed: 3147 case ARM::VST2d32wb_fixed: 3148 case ARM::VST2q8wb_fixed: 3149 case ARM::VST2q16wb_fixed: 3150 case ARM::VST2q32wb_fixed: 3151 case ARM::VST2b8wb_fixed: 3152 case ARM::VST2b16wb_fixed: 3153 case ARM::VST2b32wb_fixed: 3154 break; 3155 } 3156 3157 // First input register 3158 switch (Inst.getOpcode()) { 3159 case ARM::VST1q16: 3160 case ARM::VST1q32: 3161 case ARM::VST1q64: 3162 case ARM::VST1q8: 3163 case ARM::VST1q16wb_fixed: 3164 case ARM::VST1q16wb_register: 3165 case ARM::VST1q32wb_fixed: 3166 case ARM::VST1q32wb_register: 3167 case ARM::VST1q64wb_fixed: 3168 case ARM::VST1q64wb_register: 3169 case ARM::VST1q8wb_fixed: 3170 case ARM::VST1q8wb_register: 3171 case ARM::VST2d16: 3172 case ARM::VST2d32: 3173 case ARM::VST2d8: 3174 case ARM::VST2d16wb_fixed: 3175 case ARM::VST2d16wb_register: 3176 case ARM::VST2d32wb_fixed: 3177 case ARM::VST2d32wb_register: 3178 case ARM::VST2d8wb_fixed: 3179 case ARM::VST2d8wb_register: 3180 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3181 return MCDisassembler::Fail; 3182 break; 3183 case ARM::VST2b16: 3184 case ARM::VST2b32: 3185 case ARM::VST2b8: 3186 case ARM::VST2b16wb_fixed: 3187 case ARM::VST2b16wb_register: 3188 case ARM::VST2b32wb_fixed: 3189 case ARM::VST2b32wb_register: 3190 case ARM::VST2b8wb_fixed: 3191 case ARM::VST2b8wb_register: 3192 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3193 return MCDisassembler::Fail; 3194 break; 3195 default: 3196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3197 return MCDisassembler::Fail; 3198 } 3199 3200 // Second input register 3201 switch (Inst.getOpcode()) { 3202 case ARM::VST3d8: 3203 case ARM::VST3d16: 3204 case ARM::VST3d32: 3205 case ARM::VST3d8_UPD: 3206 case ARM::VST3d16_UPD: 3207 case ARM::VST3d32_UPD: 3208 case ARM::VST4d8: 3209 case ARM::VST4d16: 3210 case ARM::VST4d32: 3211 case ARM::VST4d8_UPD: 3212 case ARM::VST4d16_UPD: 3213 case ARM::VST4d32_UPD: 3214 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3215 return MCDisassembler::Fail; 3216 break; 3217 case ARM::VST3q8: 3218 case ARM::VST3q16: 3219 case ARM::VST3q32: 3220 case ARM::VST3q8_UPD: 3221 case ARM::VST3q16_UPD: 3222 case ARM::VST3q32_UPD: 3223 case ARM::VST4q8: 3224 case ARM::VST4q16: 3225 case ARM::VST4q32: 3226 case ARM::VST4q8_UPD: 3227 case ARM::VST4q16_UPD: 3228 case ARM::VST4q32_UPD: 3229 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3230 return MCDisassembler::Fail; 3231 break; 3232 default: 3233 break; 3234 } 3235 3236 // Third input register 3237 switch (Inst.getOpcode()) { 3238 case ARM::VST3d8: 3239 case ARM::VST3d16: 3240 case ARM::VST3d32: 3241 case ARM::VST3d8_UPD: 3242 case ARM::VST3d16_UPD: 3243 case ARM::VST3d32_UPD: 3244 case ARM::VST4d8: 3245 case ARM::VST4d16: 3246 case ARM::VST4d32: 3247 case ARM::VST4d8_UPD: 3248 case ARM::VST4d16_UPD: 3249 case ARM::VST4d32_UPD: 3250 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3251 return MCDisassembler::Fail; 3252 break; 3253 case ARM::VST3q8: 3254 case ARM::VST3q16: 3255 case ARM::VST3q32: 3256 case ARM::VST3q8_UPD: 3257 case ARM::VST3q16_UPD: 3258 case ARM::VST3q32_UPD: 3259 case ARM::VST4q8: 3260 case ARM::VST4q16: 3261 case ARM::VST4q32: 3262 case ARM::VST4q8_UPD: 3263 case ARM::VST4q16_UPD: 3264 case ARM::VST4q32_UPD: 3265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3266 return MCDisassembler::Fail; 3267 break; 3268 default: 3269 break; 3270 } 3271 3272 // Fourth input register 3273 switch (Inst.getOpcode()) { 3274 case ARM::VST4d8: 3275 case ARM::VST4d16: 3276 case ARM::VST4d32: 3277 case ARM::VST4d8_UPD: 3278 case ARM::VST4d16_UPD: 3279 case ARM::VST4d32_UPD: 3280 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3281 return MCDisassembler::Fail; 3282 break; 3283 case ARM::VST4q8: 3284 case ARM::VST4q16: 3285 case ARM::VST4q32: 3286 case ARM::VST4q8_UPD: 3287 case ARM::VST4q16_UPD: 3288 case ARM::VST4q32_UPD: 3289 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3290 return MCDisassembler::Fail; 3291 break; 3292 default: 3293 break; 3294 } 3295 3296 return S; 3297 } 3298 3299 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3300 uint64_t Address, const void *Decoder) { 3301 DecodeStatus S = MCDisassembler::Success; 3302 3303 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3305 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3306 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3307 unsigned align = fieldFromInstruction(Insn, 4, 1); 3308 unsigned size = fieldFromInstruction(Insn, 6, 2); 3309 3310 if (size == 0 && align == 1) 3311 return MCDisassembler::Fail; 3312 align *= (1 << size); 3313 3314 switch (Inst.getOpcode()) { 3315 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3316 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3317 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3318 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3319 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3320 return MCDisassembler::Fail; 3321 break; 3322 default: 3323 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3324 return MCDisassembler::Fail; 3325 break; 3326 } 3327 if (Rm != 0xF) { 3328 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3329 return MCDisassembler::Fail; 3330 } 3331 3332 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3333 return MCDisassembler::Fail; 3334 Inst.addOperand(MCOperand::createImm(align)); 3335 3336 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3337 // variant encodes Rm == 0xf. Anything else is a register offset post- 3338 // increment and we need to add the register operand to the instruction. 3339 if (Rm != 0xD && Rm != 0xF && 3340 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3341 return MCDisassembler::Fail; 3342 3343 return S; 3344 } 3345 3346 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3347 uint64_t Address, const void *Decoder) { 3348 DecodeStatus S = MCDisassembler::Success; 3349 3350 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3351 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3352 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3353 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3354 unsigned align = fieldFromInstruction(Insn, 4, 1); 3355 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3356 align *= 2*size; 3357 3358 switch (Inst.getOpcode()) { 3359 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3360 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3361 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3362 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3363 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3364 return MCDisassembler::Fail; 3365 break; 3366 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3367 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3368 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3369 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3370 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3371 return MCDisassembler::Fail; 3372 break; 3373 default: 3374 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3375 return MCDisassembler::Fail; 3376 break; 3377 } 3378 3379 if (Rm != 0xF) 3380 Inst.addOperand(MCOperand::createImm(0)); 3381 3382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3383 return MCDisassembler::Fail; 3384 Inst.addOperand(MCOperand::createImm(align)); 3385 3386 if (Rm != 0xD && Rm != 0xF) { 3387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3388 return MCDisassembler::Fail; 3389 } 3390 3391 return S; 3392 } 3393 3394 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3395 uint64_t Address, const void *Decoder) { 3396 DecodeStatus S = MCDisassembler::Success; 3397 3398 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3399 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3400 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3401 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3402 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3403 3404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3405 return MCDisassembler::Fail; 3406 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3407 return MCDisassembler::Fail; 3408 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3409 return MCDisassembler::Fail; 3410 if (Rm != 0xF) { 3411 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3412 return MCDisassembler::Fail; 3413 } 3414 3415 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3416 return MCDisassembler::Fail; 3417 Inst.addOperand(MCOperand::createImm(0)); 3418 3419 if (Rm == 0xD) 3420 Inst.addOperand(MCOperand::createReg(0)); 3421 else if (Rm != 0xF) { 3422 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 } 3425 3426 return S; 3427 } 3428 3429 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3430 uint64_t Address, const void *Decoder) { 3431 DecodeStatus S = MCDisassembler::Success; 3432 3433 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3434 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3435 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3436 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3437 unsigned size = fieldFromInstruction(Insn, 6, 2); 3438 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3439 unsigned align = fieldFromInstruction(Insn, 4, 1); 3440 3441 if (size == 0x3) { 3442 if (align == 0) 3443 return MCDisassembler::Fail; 3444 align = 16; 3445 } else { 3446 if (size == 2) { 3447 align *= 8; 3448 } else { 3449 size = 1 << size; 3450 align *= 4*size; 3451 } 3452 } 3453 3454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3455 return MCDisassembler::Fail; 3456 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3457 return MCDisassembler::Fail; 3458 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3459 return MCDisassembler::Fail; 3460 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3461 return MCDisassembler::Fail; 3462 if (Rm != 0xF) { 3463 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3464 return MCDisassembler::Fail; 3465 } 3466 3467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3468 return MCDisassembler::Fail; 3469 Inst.addOperand(MCOperand::createImm(align)); 3470 3471 if (Rm == 0xD) 3472 Inst.addOperand(MCOperand::createReg(0)); 3473 else if (Rm != 0xF) { 3474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3475 return MCDisassembler::Fail; 3476 } 3477 3478 return S; 3479 } 3480 3481 static DecodeStatus 3482 DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3483 uint64_t Address, const void *Decoder) { 3484 DecodeStatus S = MCDisassembler::Success; 3485 3486 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3487 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3488 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3489 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3490 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3491 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3492 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3493 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3494 3495 if (Q) { 3496 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3497 return MCDisassembler::Fail; 3498 } else { 3499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3500 return MCDisassembler::Fail; 3501 } 3502 3503 Inst.addOperand(MCOperand::createImm(imm)); 3504 3505 switch (Inst.getOpcode()) { 3506 case ARM::VORRiv4i16: 3507 case ARM::VORRiv2i32: 3508 case ARM::VBICiv4i16: 3509 case ARM::VBICiv2i32: 3510 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3511 return MCDisassembler::Fail; 3512 break; 3513 case ARM::VORRiv8i16: 3514 case ARM::VORRiv4i32: 3515 case ARM::VBICiv8i16: 3516 case ARM::VBICiv4i32: 3517 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3518 return MCDisassembler::Fail; 3519 break; 3520 default: 3521 break; 3522 } 3523 3524 return S; 3525 } 3526 3527 static DecodeStatus 3528 DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3529 uint64_t Address, const void *Decoder) { 3530 DecodeStatus S = MCDisassembler::Success; 3531 3532 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3533 fieldFromInstruction(Insn, 13, 3)); 3534 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3535 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3536 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3537 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3538 imm |= cmode << 8; 3539 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3540 3541 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3542 return MCDisassembler::Fail; 3543 3544 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3545 return MCDisassembler::Fail; 3546 3547 Inst.addOperand(MCOperand::createImm(imm)); 3548 3549 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3550 Inst.addOperand(MCOperand::createReg(0)); 3551 Inst.addOperand(MCOperand::createImm(0)); 3552 3553 return S; 3554 } 3555 3556 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3557 uint64_t Address, const void *Decoder) { 3558 DecodeStatus S = MCDisassembler::Success; 3559 3560 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3561 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3562 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3563 return MCDisassembler::Fail; 3564 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3565 3566 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3567 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3568 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3569 return MCDisassembler::Fail; 3570 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3571 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3572 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3573 return MCDisassembler::Fail; 3574 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3575 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3576 Inst.addOperand(MCOperand::createImm(Qd)); 3577 3578 return S; 3579 } 3580 3581 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3582 uint64_t Address, const void *Decoder) { 3583 DecodeStatus S = MCDisassembler::Success; 3584 3585 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3586 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3587 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3588 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3589 unsigned size = fieldFromInstruction(Insn, 18, 2); 3590 3591 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3592 return MCDisassembler::Fail; 3593 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3594 return MCDisassembler::Fail; 3595 Inst.addOperand(MCOperand::createImm(8 << size)); 3596 3597 return S; 3598 } 3599 3600 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3601 uint64_t Address, const void *Decoder) { 3602 Inst.addOperand(MCOperand::createImm(8 - Val)); 3603 return MCDisassembler::Success; 3604 } 3605 3606 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3607 uint64_t Address, const void *Decoder) { 3608 Inst.addOperand(MCOperand::createImm(16 - Val)); 3609 return MCDisassembler::Success; 3610 } 3611 3612 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3613 uint64_t Address, const void *Decoder) { 3614 Inst.addOperand(MCOperand::createImm(32 - Val)); 3615 return MCDisassembler::Success; 3616 } 3617 3618 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3619 uint64_t Address, const void *Decoder) { 3620 Inst.addOperand(MCOperand::createImm(64 - Val)); 3621 return MCDisassembler::Success; 3622 } 3623 3624 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3625 uint64_t Address, const void *Decoder) { 3626 DecodeStatus S = MCDisassembler::Success; 3627 3628 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3629 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3630 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3631 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3632 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3633 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3634 unsigned op = fieldFromInstruction(Insn, 6, 1); 3635 3636 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3637 return MCDisassembler::Fail; 3638 if (op) { 3639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3640 return MCDisassembler::Fail; // Writeback 3641 } 3642 3643 switch (Inst.getOpcode()) { 3644 case ARM::VTBL2: 3645 case ARM::VTBX2: 3646 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3647 return MCDisassembler::Fail; 3648 break; 3649 default: 3650 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 } 3653 3654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3655 return MCDisassembler::Fail; 3656 3657 return S; 3658 } 3659 3660 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3661 uint64_t Address, const void *Decoder) { 3662 DecodeStatus S = MCDisassembler::Success; 3663 3664 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3665 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3666 3667 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3668 return MCDisassembler::Fail; 3669 3670 switch(Inst.getOpcode()) { 3671 default: 3672 return MCDisassembler::Fail; 3673 case ARM::tADR: 3674 break; // tADR does not explicitly represent the PC as an operand. 3675 case ARM::tADDrSPi: 3676 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3677 break; 3678 } 3679 3680 Inst.addOperand(MCOperand::createImm(imm)); 3681 return S; 3682 } 3683 3684 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3685 uint64_t Address, const void *Decoder) { 3686 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3687 true, 2, Inst, Decoder)) 3688 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3689 return MCDisassembler::Success; 3690 } 3691 3692 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3693 uint64_t Address, const void *Decoder) { 3694 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3695 true, 4, Inst, Decoder)) 3696 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3697 return MCDisassembler::Success; 3698 } 3699 3700 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3701 uint64_t Address, const void *Decoder) { 3702 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3703 true, 2, Inst, Decoder)) 3704 Inst.addOperand(MCOperand::createImm(Val << 1)); 3705 return MCDisassembler::Success; 3706 } 3707 3708 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3709 uint64_t Address, const void *Decoder) { 3710 DecodeStatus S = MCDisassembler::Success; 3711 3712 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3713 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3714 3715 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3716 return MCDisassembler::Fail; 3717 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3718 return MCDisassembler::Fail; 3719 3720 return S; 3721 } 3722 3723 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3724 uint64_t Address, const void *Decoder) { 3725 DecodeStatus S = MCDisassembler::Success; 3726 3727 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3728 unsigned imm = fieldFromInstruction(Val, 3, 5); 3729 3730 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3731 return MCDisassembler::Fail; 3732 Inst.addOperand(MCOperand::createImm(imm)); 3733 3734 return S; 3735 } 3736 3737 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3738 uint64_t Address, const void *Decoder) { 3739 unsigned imm = Val << 2; 3740 3741 Inst.addOperand(MCOperand::createImm(imm)); 3742 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3743 3744 return MCDisassembler::Success; 3745 } 3746 3747 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3748 uint64_t Address, const void *Decoder) { 3749 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3750 Inst.addOperand(MCOperand::createImm(Val)); 3751 3752 return MCDisassembler::Success; 3753 } 3754 3755 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3756 uint64_t Address, const void *Decoder) { 3757 DecodeStatus S = MCDisassembler::Success; 3758 3759 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3760 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3761 unsigned imm = fieldFromInstruction(Val, 0, 2); 3762 3763 // Thumb stores cannot use PC as dest register. 3764 switch (Inst.getOpcode()) { 3765 case ARM::t2STRHs: 3766 case ARM::t2STRBs: 3767 case ARM::t2STRs: 3768 if (Rn == 15) 3769 return MCDisassembler::Fail; 3770 break; 3771 default: 3772 break; 3773 } 3774 3775 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3778 return MCDisassembler::Fail; 3779 Inst.addOperand(MCOperand::createImm(imm)); 3780 3781 return S; 3782 } 3783 3784 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3785 uint64_t Address, const void *Decoder) { 3786 DecodeStatus S = MCDisassembler::Success; 3787 3788 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3789 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3790 3791 const FeatureBitset &featureBits = 3792 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3793 3794 bool hasMP = featureBits[ARM::FeatureMP]; 3795 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3796 3797 if (Rn == 15) { 3798 switch (Inst.getOpcode()) { 3799 case ARM::t2LDRBs: 3800 Inst.setOpcode(ARM::t2LDRBpci); 3801 break; 3802 case ARM::t2LDRHs: 3803 Inst.setOpcode(ARM::t2LDRHpci); 3804 break; 3805 case ARM::t2LDRSHs: 3806 Inst.setOpcode(ARM::t2LDRSHpci); 3807 break; 3808 case ARM::t2LDRSBs: 3809 Inst.setOpcode(ARM::t2LDRSBpci); 3810 break; 3811 case ARM::t2LDRs: 3812 Inst.setOpcode(ARM::t2LDRpci); 3813 break; 3814 case ARM::t2PLDs: 3815 Inst.setOpcode(ARM::t2PLDpci); 3816 break; 3817 case ARM::t2PLIs: 3818 Inst.setOpcode(ARM::t2PLIpci); 3819 break; 3820 default: 3821 return MCDisassembler::Fail; 3822 } 3823 3824 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3825 } 3826 3827 if (Rt == 15) { 3828 switch (Inst.getOpcode()) { 3829 case ARM::t2LDRSHs: 3830 return MCDisassembler::Fail; 3831 case ARM::t2LDRHs: 3832 Inst.setOpcode(ARM::t2PLDWs); 3833 break; 3834 case ARM::t2LDRSBs: 3835 Inst.setOpcode(ARM::t2PLIs); 3836 break; 3837 default: 3838 break; 3839 } 3840 } 3841 3842 switch (Inst.getOpcode()) { 3843 case ARM::t2PLDs: 3844 break; 3845 case ARM::t2PLIs: 3846 if (!hasV7Ops) 3847 return MCDisassembler::Fail; 3848 break; 3849 case ARM::t2PLDWs: 3850 if (!hasV7Ops || !hasMP) 3851 return MCDisassembler::Fail; 3852 break; 3853 default: 3854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3855 return MCDisassembler::Fail; 3856 } 3857 3858 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3859 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3860 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3861 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3862 return MCDisassembler::Fail; 3863 3864 return S; 3865 } 3866 3867 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3868 uint64_t Address, const void* Decoder) { 3869 DecodeStatus S = MCDisassembler::Success; 3870 3871 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3872 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3873 unsigned U = fieldFromInstruction(Insn, 9, 1); 3874 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3875 imm |= (U << 8); 3876 imm |= (Rn << 9); 3877 unsigned add = fieldFromInstruction(Insn, 9, 1); 3878 3879 const FeatureBitset &featureBits = 3880 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3881 3882 bool hasMP = featureBits[ARM::FeatureMP]; 3883 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3884 3885 if (Rn == 15) { 3886 switch (Inst.getOpcode()) { 3887 case ARM::t2LDRi8: 3888 Inst.setOpcode(ARM::t2LDRpci); 3889 break; 3890 case ARM::t2LDRBi8: 3891 Inst.setOpcode(ARM::t2LDRBpci); 3892 break; 3893 case ARM::t2LDRSBi8: 3894 Inst.setOpcode(ARM::t2LDRSBpci); 3895 break; 3896 case ARM::t2LDRHi8: 3897 Inst.setOpcode(ARM::t2LDRHpci); 3898 break; 3899 case ARM::t2LDRSHi8: 3900 Inst.setOpcode(ARM::t2LDRSHpci); 3901 break; 3902 case ARM::t2PLDi8: 3903 Inst.setOpcode(ARM::t2PLDpci); 3904 break; 3905 case ARM::t2PLIi8: 3906 Inst.setOpcode(ARM::t2PLIpci); 3907 break; 3908 default: 3909 return MCDisassembler::Fail; 3910 } 3911 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3912 } 3913 3914 if (Rt == 15) { 3915 switch (Inst.getOpcode()) { 3916 case ARM::t2LDRSHi8: 3917 return MCDisassembler::Fail; 3918 case ARM::t2LDRHi8: 3919 if (!add) 3920 Inst.setOpcode(ARM::t2PLDWi8); 3921 break; 3922 case ARM::t2LDRSBi8: 3923 Inst.setOpcode(ARM::t2PLIi8); 3924 break; 3925 default: 3926 break; 3927 } 3928 } 3929 3930 switch (Inst.getOpcode()) { 3931 case ARM::t2PLDi8: 3932 break; 3933 case ARM::t2PLIi8: 3934 if (!hasV7Ops) 3935 return MCDisassembler::Fail; 3936 break; 3937 case ARM::t2PLDWi8: 3938 if (!hasV7Ops || !hasMP) 3939 return MCDisassembler::Fail; 3940 break; 3941 default: 3942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3943 return MCDisassembler::Fail; 3944 } 3945 3946 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3947 return MCDisassembler::Fail; 3948 return S; 3949 } 3950 3951 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3952 uint64_t Address, const void* Decoder) { 3953 DecodeStatus S = MCDisassembler::Success; 3954 3955 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3956 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3957 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3958 imm |= (Rn << 13); 3959 3960 const FeatureBitset &featureBits = 3961 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 3962 3963 bool hasMP = featureBits[ARM::FeatureMP]; 3964 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 3965 3966 if (Rn == 15) { 3967 switch (Inst.getOpcode()) { 3968 case ARM::t2LDRi12: 3969 Inst.setOpcode(ARM::t2LDRpci); 3970 break; 3971 case ARM::t2LDRHi12: 3972 Inst.setOpcode(ARM::t2LDRHpci); 3973 break; 3974 case ARM::t2LDRSHi12: 3975 Inst.setOpcode(ARM::t2LDRSHpci); 3976 break; 3977 case ARM::t2LDRBi12: 3978 Inst.setOpcode(ARM::t2LDRBpci); 3979 break; 3980 case ARM::t2LDRSBi12: 3981 Inst.setOpcode(ARM::t2LDRSBpci); 3982 break; 3983 case ARM::t2PLDi12: 3984 Inst.setOpcode(ARM::t2PLDpci); 3985 break; 3986 case ARM::t2PLIi12: 3987 Inst.setOpcode(ARM::t2PLIpci); 3988 break; 3989 default: 3990 return MCDisassembler::Fail; 3991 } 3992 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3993 } 3994 3995 if (Rt == 15) { 3996 switch (Inst.getOpcode()) { 3997 case ARM::t2LDRSHi12: 3998 return MCDisassembler::Fail; 3999 case ARM::t2LDRHi12: 4000 Inst.setOpcode(ARM::t2PLDWi12); 4001 break; 4002 case ARM::t2LDRSBi12: 4003 Inst.setOpcode(ARM::t2PLIi12); 4004 break; 4005 default: 4006 break; 4007 } 4008 } 4009 4010 switch (Inst.getOpcode()) { 4011 case ARM::t2PLDi12: 4012 break; 4013 case ARM::t2PLIi12: 4014 if (!hasV7Ops) 4015 return MCDisassembler::Fail; 4016 break; 4017 case ARM::t2PLDWi12: 4018 if (!hasV7Ops || !hasMP) 4019 return MCDisassembler::Fail; 4020 break; 4021 default: 4022 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4023 return MCDisassembler::Fail; 4024 } 4025 4026 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4027 return MCDisassembler::Fail; 4028 return S; 4029 } 4030 4031 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 4032 uint64_t Address, const void* Decoder) { 4033 DecodeStatus S = MCDisassembler::Success; 4034 4035 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4036 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4037 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4038 imm |= (Rn << 9); 4039 4040 if (Rn == 15) { 4041 switch (Inst.getOpcode()) { 4042 case ARM::t2LDRT: 4043 Inst.setOpcode(ARM::t2LDRpci); 4044 break; 4045 case ARM::t2LDRBT: 4046 Inst.setOpcode(ARM::t2LDRBpci); 4047 break; 4048 case ARM::t2LDRHT: 4049 Inst.setOpcode(ARM::t2LDRHpci); 4050 break; 4051 case ARM::t2LDRSBT: 4052 Inst.setOpcode(ARM::t2LDRSBpci); 4053 break; 4054 case ARM::t2LDRSHT: 4055 Inst.setOpcode(ARM::t2LDRSHpci); 4056 break; 4057 default: 4058 return MCDisassembler::Fail; 4059 } 4060 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4061 } 4062 4063 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4064 return MCDisassembler::Fail; 4065 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4066 return MCDisassembler::Fail; 4067 return S; 4068 } 4069 4070 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4071 uint64_t Address, const void* Decoder) { 4072 DecodeStatus S = MCDisassembler::Success; 4073 4074 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4075 unsigned U = fieldFromInstruction(Insn, 23, 1); 4076 int imm = fieldFromInstruction(Insn, 0, 12); 4077 4078 const FeatureBitset &featureBits = 4079 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4080 4081 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4082 4083 if (Rt == 15) { 4084 switch (Inst.getOpcode()) { 4085 case ARM::t2LDRBpci: 4086 case ARM::t2LDRHpci: 4087 Inst.setOpcode(ARM::t2PLDpci); 4088 break; 4089 case ARM::t2LDRSBpci: 4090 Inst.setOpcode(ARM::t2PLIpci); 4091 break; 4092 case ARM::t2LDRSHpci: 4093 return MCDisassembler::Fail; 4094 default: 4095 break; 4096 } 4097 } 4098 4099 switch(Inst.getOpcode()) { 4100 case ARM::t2PLDpci: 4101 break; 4102 case ARM::t2PLIpci: 4103 if (!hasV7Ops) 4104 return MCDisassembler::Fail; 4105 break; 4106 default: 4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4108 return MCDisassembler::Fail; 4109 } 4110 4111 if (!U) { 4112 // Special case for #-0. 4113 if (imm == 0) 4114 imm = INT32_MIN; 4115 else 4116 imm = -imm; 4117 } 4118 Inst.addOperand(MCOperand::createImm(imm)); 4119 4120 return S; 4121 } 4122 4123 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 4124 uint64_t Address, const void *Decoder) { 4125 if (Val == 0) 4126 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4127 else { 4128 int imm = Val & 0xFF; 4129 4130 if (!(Val & 0x100)) imm *= -1; 4131 Inst.addOperand(MCOperand::createImm(imm * 4)); 4132 } 4133 4134 return MCDisassembler::Success; 4135 } 4136 4137 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4138 const void *Decoder) { 4139 if (Val == 0) 4140 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4141 else { 4142 int imm = Val & 0x7F; 4143 4144 if (!(Val & 0x80)) 4145 imm *= -1; 4146 Inst.addOperand(MCOperand::createImm(imm * 4)); 4147 } 4148 4149 return MCDisassembler::Success; 4150 } 4151 4152 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4153 uint64_t Address, const void *Decoder) { 4154 DecodeStatus S = MCDisassembler::Success; 4155 4156 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4157 unsigned imm = fieldFromInstruction(Val, 0, 9); 4158 4159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4160 return MCDisassembler::Fail; 4161 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4162 return MCDisassembler::Fail; 4163 4164 return S; 4165 } 4166 4167 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4168 uint64_t Address, 4169 const void *Decoder) { 4170 DecodeStatus S = MCDisassembler::Success; 4171 4172 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4173 unsigned imm = fieldFromInstruction(Val, 0, 8); 4174 4175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4178 return MCDisassembler::Fail; 4179 4180 return S; 4181 } 4182 4183 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 4184 uint64_t Address, const void *Decoder) { 4185 DecodeStatus S = MCDisassembler::Success; 4186 4187 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4188 unsigned imm = fieldFromInstruction(Val, 0, 8); 4189 4190 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4191 return MCDisassembler::Fail; 4192 4193 Inst.addOperand(MCOperand::createImm(imm)); 4194 4195 return S; 4196 } 4197 4198 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 4199 uint64_t Address, const void *Decoder) { 4200 int imm = Val & 0xFF; 4201 if (Val == 0) 4202 imm = INT32_MIN; 4203 else if (!(Val & 0x100)) 4204 imm *= -1; 4205 Inst.addOperand(MCOperand::createImm(imm)); 4206 4207 return MCDisassembler::Success; 4208 } 4209 4210 template<int shift> 4211 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, 4212 uint64_t Address, const void *Decoder) { 4213 int imm = Val & 0x7F; 4214 if (Val == 0) 4215 imm = INT32_MIN; 4216 else if (!(Val & 0x80)) 4217 imm *= -1; 4218 if (imm != INT32_MIN) 4219 imm *= (1U << shift); 4220 Inst.addOperand(MCOperand::createImm(imm)); 4221 4222 return MCDisassembler::Success; 4223 } 4224 4225 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4226 uint64_t Address, const void *Decoder) { 4227 DecodeStatus S = MCDisassembler::Success; 4228 4229 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4230 unsigned imm = fieldFromInstruction(Val, 0, 9); 4231 4232 // Thumb stores cannot use PC as dest register. 4233 switch (Inst.getOpcode()) { 4234 case ARM::t2STRT: 4235 case ARM::t2STRBT: 4236 case ARM::t2STRHT: 4237 case ARM::t2STRi8: 4238 case ARM::t2STRHi8: 4239 case ARM::t2STRBi8: 4240 if (Rn == 15) 4241 return MCDisassembler::Fail; 4242 break; 4243 default: 4244 break; 4245 } 4246 4247 // Some instructions always use an additive offset. 4248 switch (Inst.getOpcode()) { 4249 case ARM::t2LDRT: 4250 case ARM::t2LDRBT: 4251 case ARM::t2LDRHT: 4252 case ARM::t2LDRSBT: 4253 case ARM::t2LDRSHT: 4254 case ARM::t2STRT: 4255 case ARM::t2STRBT: 4256 case ARM::t2STRHT: 4257 imm |= 0x100; 4258 break; 4259 default: 4260 break; 4261 } 4262 4263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4264 return MCDisassembler::Fail; 4265 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4266 return MCDisassembler::Fail; 4267 4268 return S; 4269 } 4270 4271 template<int shift> 4272 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4273 uint64_t Address, 4274 const void *Decoder) { 4275 DecodeStatus S = MCDisassembler::Success; 4276 4277 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4278 unsigned imm = fieldFromInstruction(Val, 0, 8); 4279 4280 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4281 return MCDisassembler::Fail; 4282 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4283 return MCDisassembler::Fail; 4284 4285 return S; 4286 } 4287 4288 template<int shift, int WriteBack> 4289 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4290 uint64_t Address, 4291 const void *Decoder) { 4292 DecodeStatus S = MCDisassembler::Success; 4293 4294 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4295 unsigned imm = fieldFromInstruction(Val, 0, 8); 4296 if (WriteBack) { 4297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4298 return MCDisassembler::Fail; 4299 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4300 return MCDisassembler::Fail; 4301 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4302 return MCDisassembler::Fail; 4303 4304 return S; 4305 } 4306 4307 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4308 uint64_t Address, const void *Decoder) { 4309 DecodeStatus S = MCDisassembler::Success; 4310 4311 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4312 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4313 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4314 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4315 addr |= Rn << 9; 4316 unsigned load = fieldFromInstruction(Insn, 20, 1); 4317 4318 if (Rn == 15) { 4319 switch (Inst.getOpcode()) { 4320 case ARM::t2LDR_PRE: 4321 case ARM::t2LDR_POST: 4322 Inst.setOpcode(ARM::t2LDRpci); 4323 break; 4324 case ARM::t2LDRB_PRE: 4325 case ARM::t2LDRB_POST: 4326 Inst.setOpcode(ARM::t2LDRBpci); 4327 break; 4328 case ARM::t2LDRH_PRE: 4329 case ARM::t2LDRH_POST: 4330 Inst.setOpcode(ARM::t2LDRHpci); 4331 break; 4332 case ARM::t2LDRSB_PRE: 4333 case ARM::t2LDRSB_POST: 4334 if (Rt == 15) 4335 Inst.setOpcode(ARM::t2PLIpci); 4336 else 4337 Inst.setOpcode(ARM::t2LDRSBpci); 4338 break; 4339 case ARM::t2LDRSH_PRE: 4340 case ARM::t2LDRSH_POST: 4341 Inst.setOpcode(ARM::t2LDRSHpci); 4342 break; 4343 default: 4344 return MCDisassembler::Fail; 4345 } 4346 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4347 } 4348 4349 if (!load) { 4350 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4351 return MCDisassembler::Fail; 4352 } 4353 4354 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4355 return MCDisassembler::Fail; 4356 4357 if (load) { 4358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4359 return MCDisassembler::Fail; 4360 } 4361 4362 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4363 return MCDisassembler::Fail; 4364 4365 return S; 4366 } 4367 4368 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4369 uint64_t Address, const void *Decoder) { 4370 DecodeStatus S = MCDisassembler::Success; 4371 4372 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4373 unsigned imm = fieldFromInstruction(Val, 0, 12); 4374 4375 // Thumb stores cannot use PC as dest register. 4376 switch (Inst.getOpcode()) { 4377 case ARM::t2STRi12: 4378 case ARM::t2STRBi12: 4379 case ARM::t2STRHi12: 4380 if (Rn == 15) 4381 return MCDisassembler::Fail; 4382 break; 4383 default: 4384 break; 4385 } 4386 4387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4388 return MCDisassembler::Fail; 4389 Inst.addOperand(MCOperand::createImm(imm)); 4390 4391 return S; 4392 } 4393 4394 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4395 uint64_t Address, const void *Decoder) { 4396 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4397 4398 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4399 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4400 Inst.addOperand(MCOperand::createImm(imm)); 4401 4402 return MCDisassembler::Success; 4403 } 4404 4405 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4406 uint64_t Address, const void *Decoder) { 4407 DecodeStatus S = MCDisassembler::Success; 4408 4409 if (Inst.getOpcode() == ARM::tADDrSP) { 4410 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4411 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4412 4413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4414 return MCDisassembler::Fail; 4415 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4416 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4417 return MCDisassembler::Fail; 4418 } else if (Inst.getOpcode() == ARM::tADDspr) { 4419 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4420 4421 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4422 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4424 return MCDisassembler::Fail; 4425 } 4426 4427 return S; 4428 } 4429 4430 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4431 uint64_t Address, const void *Decoder) { 4432 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4433 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4434 4435 Inst.addOperand(MCOperand::createImm(imod)); 4436 Inst.addOperand(MCOperand::createImm(flags)); 4437 4438 return MCDisassembler::Success; 4439 } 4440 4441 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4442 uint64_t Address, const void *Decoder) { 4443 DecodeStatus S = MCDisassembler::Success; 4444 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4445 unsigned add = fieldFromInstruction(Insn, 4, 1); 4446 4447 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 Inst.addOperand(MCOperand::createImm(add)); 4450 4451 return S; 4452 } 4453 4454 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4455 uint64_t Address, const void *Decoder) { 4456 DecodeStatus S = MCDisassembler::Success; 4457 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4458 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4459 4460 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4461 return MCDisassembler::Fail; 4462 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4463 return MCDisassembler::Fail; 4464 4465 return S; 4466 } 4467 4468 template<int shift> 4469 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4470 uint64_t Address, const void *Decoder) { 4471 DecodeStatus S = MCDisassembler::Success; 4472 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4473 int imm = fieldFromInstruction(Insn, 0, 7); 4474 4475 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4476 return MCDisassembler::Fail; 4477 4478 if(!fieldFromInstruction(Insn, 7, 1)) { 4479 if (imm == 0) 4480 imm = INT32_MIN; // indicate -0 4481 else 4482 imm *= -1; 4483 } 4484 if (imm != INT32_MIN) 4485 imm *= (1U << shift); 4486 Inst.addOperand(MCOperand::createImm(imm)); 4487 4488 return S; 4489 } 4490 4491 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4492 uint64_t Address, const void *Decoder) { 4493 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4494 // Note only one trailing zero not two. Also the J1 and J2 values are from 4495 // the encoded instruction. So here change to I1 and I2 values via: 4496 // I1 = NOT(J1 EOR S); 4497 // I2 = NOT(J2 EOR S); 4498 // and build the imm32 with two trailing zeros as documented: 4499 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4500 unsigned S = (Val >> 23) & 1; 4501 unsigned J1 = (Val >> 22) & 1; 4502 unsigned J2 = (Val >> 21) & 1; 4503 unsigned I1 = !(J1 ^ S); 4504 unsigned I2 = !(J2 ^ S); 4505 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4506 int imm32 = SignExtend32<25>(tmp << 1); 4507 4508 if (!tryAddingSymbolicOperand(Address, 4509 (Address & ~2u) + imm32 + 4, 4510 true, 4, Inst, Decoder)) 4511 Inst.addOperand(MCOperand::createImm(imm32)); 4512 return MCDisassembler::Success; 4513 } 4514 4515 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4516 uint64_t Address, const void *Decoder) { 4517 if (Val == 0xA || Val == 0xB) 4518 return MCDisassembler::Fail; 4519 4520 const FeatureBitset &featureBits = 4521 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4522 4523 if (!isValidCoprocessorNumber(Val, featureBits)) 4524 return MCDisassembler::Fail; 4525 4526 Inst.addOperand(MCOperand::createImm(Val)); 4527 return MCDisassembler::Success; 4528 } 4529 4530 static DecodeStatus 4531 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4532 uint64_t Address, const void *Decoder) { 4533 const FeatureBitset &FeatureBits = 4534 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4535 DecodeStatus S = MCDisassembler::Success; 4536 4537 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4538 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4539 4540 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4541 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4542 return MCDisassembler::Fail; 4543 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4544 return MCDisassembler::Fail; 4545 return S; 4546 } 4547 4548 static DecodeStatus 4549 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4550 uint64_t Address, const void *Decoder) { 4551 DecodeStatus S = MCDisassembler::Success; 4552 4553 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4554 if (pred == 0xE || pred == 0xF) { 4555 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4556 switch (opc) { 4557 default: 4558 return MCDisassembler::Fail; 4559 case 0xf3bf8f4: 4560 Inst.setOpcode(ARM::t2DSB); 4561 break; 4562 case 0xf3bf8f5: 4563 Inst.setOpcode(ARM::t2DMB); 4564 break; 4565 case 0xf3bf8f6: 4566 Inst.setOpcode(ARM::t2ISB); 4567 break; 4568 } 4569 4570 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4571 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4572 } 4573 4574 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4575 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4576 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4577 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4578 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4579 4580 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4581 return MCDisassembler::Fail; 4582 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 4585 return S; 4586 } 4587 4588 // Decode a shifted immediate operand. These basically consist 4589 // of an 8-bit value, and a 4-bit directive that specifies either 4590 // a splat operation or a rotation. 4591 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 4592 uint64_t Address, const void *Decoder) { 4593 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4594 if (ctrl == 0) { 4595 unsigned byte = fieldFromInstruction(Val, 8, 2); 4596 unsigned imm = fieldFromInstruction(Val, 0, 8); 4597 switch (byte) { 4598 case 0: 4599 Inst.addOperand(MCOperand::createImm(imm)); 4600 break; 4601 case 1: 4602 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4603 break; 4604 case 2: 4605 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4606 break; 4607 case 3: 4608 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4609 (imm << 8) | imm)); 4610 break; 4611 } 4612 } else { 4613 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4614 unsigned rot = fieldFromInstruction(Val, 7, 5); 4615 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 4616 Inst.addOperand(MCOperand::createImm(imm)); 4617 } 4618 4619 return MCDisassembler::Success; 4620 } 4621 4622 static DecodeStatus 4623 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4624 uint64_t Address, const void *Decoder) { 4625 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4626 true, 2, Inst, Decoder)) 4627 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4628 return MCDisassembler::Success; 4629 } 4630 4631 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4632 uint64_t Address, 4633 const void *Decoder) { 4634 // Val is passed in as S:J1:J2:imm10:imm11 4635 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4636 // the encoded instruction. So here change to I1 and I2 values via: 4637 // I1 = NOT(J1 EOR S); 4638 // I2 = NOT(J2 EOR S); 4639 // and build the imm32 with one trailing zero as documented: 4640 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4641 unsigned S = (Val >> 23) & 1; 4642 unsigned J1 = (Val >> 22) & 1; 4643 unsigned J2 = (Val >> 21) & 1; 4644 unsigned I1 = !(J1 ^ S); 4645 unsigned I2 = !(J2 ^ S); 4646 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4647 int imm32 = SignExtend32<25>(tmp << 1); 4648 4649 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4650 true, 4, Inst, Decoder)) 4651 Inst.addOperand(MCOperand::createImm(imm32)); 4652 return MCDisassembler::Success; 4653 } 4654 4655 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4656 uint64_t Address, const void *Decoder) { 4657 if (Val & ~0xf) 4658 return MCDisassembler::Fail; 4659 4660 Inst.addOperand(MCOperand::createImm(Val)); 4661 return MCDisassembler::Success; 4662 } 4663 4664 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4665 uint64_t Address, const void *Decoder) { 4666 if (Val & ~0xf) 4667 return MCDisassembler::Fail; 4668 4669 Inst.addOperand(MCOperand::createImm(Val)); 4670 return MCDisassembler::Success; 4671 } 4672 4673 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4674 uint64_t Address, const void *Decoder) { 4675 DecodeStatus S = MCDisassembler::Success; 4676 const FeatureBitset &FeatureBits = 4677 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4678 4679 if (FeatureBits[ARM::FeatureMClass]) { 4680 unsigned ValLow = Val & 0xff; 4681 4682 // Validate the SYSm value first. 4683 switch (ValLow) { 4684 case 0: // apsr 4685 case 1: // iapsr 4686 case 2: // eapsr 4687 case 3: // xpsr 4688 case 5: // ipsr 4689 case 6: // epsr 4690 case 7: // iepsr 4691 case 8: // msp 4692 case 9: // psp 4693 case 16: // primask 4694 case 20: // control 4695 break; 4696 case 17: // basepri 4697 case 18: // basepri_max 4698 case 19: // faultmask 4699 if (!(FeatureBits[ARM::HasV7Ops])) 4700 // Values basepri, basepri_max and faultmask are only valid for v7m. 4701 return MCDisassembler::Fail; 4702 break; 4703 case 0x8a: // msplim_ns 4704 case 0x8b: // psplim_ns 4705 case 0x91: // basepri_ns 4706 case 0x93: // faultmask_ns 4707 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 4708 return MCDisassembler::Fail; 4709 LLVM_FALLTHROUGH; 4710 case 10: // msplim 4711 case 11: // psplim 4712 case 0x88: // msp_ns 4713 case 0x89: // psp_ns 4714 case 0x90: // primask_ns 4715 case 0x94: // control_ns 4716 case 0x98: // sp_ns 4717 if (!(FeatureBits[ARM::Feature8MSecExt])) 4718 return MCDisassembler::Fail; 4719 break; 4720 default: 4721 // Architecturally defined as unpredictable 4722 S = MCDisassembler::SoftFail; 4723 break; 4724 } 4725 4726 if (Inst.getOpcode() == ARM::t2MSR_M) { 4727 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4728 if (!(FeatureBits[ARM::HasV7Ops])) { 4729 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4730 // unpredictable. 4731 if (Mask != 2) 4732 S = MCDisassembler::SoftFail; 4733 } 4734 else { 4735 // The ARMv7-M architecture stores an additional 2-bit mask value in 4736 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4737 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4738 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4739 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4740 // only if the processor includes the DSP extension. 4741 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4742 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 4743 S = MCDisassembler::SoftFail; 4744 } 4745 } 4746 } else { 4747 // A/R class 4748 if (Val == 0) 4749 return MCDisassembler::Fail; 4750 } 4751 Inst.addOperand(MCOperand::createImm(Val)); 4752 return S; 4753 } 4754 4755 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4756 uint64_t Address, const void *Decoder) { 4757 unsigned R = fieldFromInstruction(Val, 5, 1); 4758 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4759 4760 // The table of encodings for these banked registers comes from B9.2.3 of the 4761 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4762 // neater. So by fiat, these values are UNPREDICTABLE: 4763 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 4764 return MCDisassembler::Fail; 4765 4766 Inst.addOperand(MCOperand::createImm(Val)); 4767 return MCDisassembler::Success; 4768 } 4769 4770 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4771 uint64_t Address, const void *Decoder) { 4772 DecodeStatus S = MCDisassembler::Success; 4773 4774 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4775 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4776 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4777 4778 if (Rn == 0xF) 4779 S = MCDisassembler::SoftFail; 4780 4781 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4782 return MCDisassembler::Fail; 4783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4784 return MCDisassembler::Fail; 4785 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4786 return MCDisassembler::Fail; 4787 4788 return S; 4789 } 4790 4791 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4792 uint64_t Address, 4793 const void *Decoder) { 4794 DecodeStatus S = MCDisassembler::Success; 4795 4796 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4797 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4798 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4799 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4800 4801 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4802 return MCDisassembler::Fail; 4803 4804 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4805 S = MCDisassembler::SoftFail; 4806 4807 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4808 return MCDisassembler::Fail; 4809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4810 return MCDisassembler::Fail; 4811 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4812 return MCDisassembler::Fail; 4813 4814 return S; 4815 } 4816 4817 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4818 uint64_t Address, const void *Decoder) { 4819 DecodeStatus S = MCDisassembler::Success; 4820 4821 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4822 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4823 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4824 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4825 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4826 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4827 4828 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4829 4830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4831 return MCDisassembler::Fail; 4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4833 return MCDisassembler::Fail; 4834 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4835 return MCDisassembler::Fail; 4836 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4837 return MCDisassembler::Fail; 4838 4839 return S; 4840 } 4841 4842 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4843 uint64_t Address, const void *Decoder) { 4844 DecodeStatus S = MCDisassembler::Success; 4845 4846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4847 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4848 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4849 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4850 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4851 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4852 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4853 4854 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4855 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4856 4857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4858 return MCDisassembler::Fail; 4859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4860 return MCDisassembler::Fail; 4861 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4862 return MCDisassembler::Fail; 4863 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4864 return MCDisassembler::Fail; 4865 4866 return S; 4867 } 4868 4869 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4870 uint64_t Address, const void *Decoder) { 4871 DecodeStatus S = MCDisassembler::Success; 4872 4873 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4874 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4875 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4876 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4877 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4878 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4879 4880 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4881 4882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4883 return MCDisassembler::Fail; 4884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4885 return MCDisassembler::Fail; 4886 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4887 return MCDisassembler::Fail; 4888 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4889 return MCDisassembler::Fail; 4890 4891 return S; 4892 } 4893 4894 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4895 uint64_t Address, const void *Decoder) { 4896 DecodeStatus S = MCDisassembler::Success; 4897 4898 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4899 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4900 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4901 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4902 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4903 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4904 4905 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4906 4907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4908 return MCDisassembler::Fail; 4909 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4910 return MCDisassembler::Fail; 4911 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4912 return MCDisassembler::Fail; 4913 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4914 return MCDisassembler::Fail; 4915 4916 return S; 4917 } 4918 4919 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4920 uint64_t Address, const void *Decoder) { 4921 DecodeStatus S = MCDisassembler::Success; 4922 4923 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4924 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4925 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4926 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4927 unsigned size = fieldFromInstruction(Insn, 10, 2); 4928 4929 unsigned align = 0; 4930 unsigned index = 0; 4931 switch (size) { 4932 default: 4933 return MCDisassembler::Fail; 4934 case 0: 4935 if (fieldFromInstruction(Insn, 4, 1)) 4936 return MCDisassembler::Fail; // UNDEFINED 4937 index = fieldFromInstruction(Insn, 5, 3); 4938 break; 4939 case 1: 4940 if (fieldFromInstruction(Insn, 5, 1)) 4941 return MCDisassembler::Fail; // UNDEFINED 4942 index = fieldFromInstruction(Insn, 6, 2); 4943 if (fieldFromInstruction(Insn, 4, 1)) 4944 align = 2; 4945 break; 4946 case 2: 4947 if (fieldFromInstruction(Insn, 6, 1)) 4948 return MCDisassembler::Fail; // UNDEFINED 4949 index = fieldFromInstruction(Insn, 7, 1); 4950 4951 switch (fieldFromInstruction(Insn, 4, 2)) { 4952 case 0 : 4953 align = 0; break; 4954 case 3: 4955 align = 4; break; 4956 default: 4957 return MCDisassembler::Fail; 4958 } 4959 break; 4960 } 4961 4962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4963 return MCDisassembler::Fail; 4964 if (Rm != 0xF) { // Writeback 4965 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4966 return MCDisassembler::Fail; 4967 } 4968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4969 return MCDisassembler::Fail; 4970 Inst.addOperand(MCOperand::createImm(align)); 4971 if (Rm != 0xF) { 4972 if (Rm != 0xD) { 4973 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4974 return MCDisassembler::Fail; 4975 } else 4976 Inst.addOperand(MCOperand::createReg(0)); 4977 } 4978 4979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4980 return MCDisassembler::Fail; 4981 Inst.addOperand(MCOperand::createImm(index)); 4982 4983 return S; 4984 } 4985 4986 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4987 uint64_t Address, const void *Decoder) { 4988 DecodeStatus S = MCDisassembler::Success; 4989 4990 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4991 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4992 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4993 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4994 unsigned size = fieldFromInstruction(Insn, 10, 2); 4995 4996 unsigned align = 0; 4997 unsigned index = 0; 4998 switch (size) { 4999 default: 5000 return MCDisassembler::Fail; 5001 case 0: 5002 if (fieldFromInstruction(Insn, 4, 1)) 5003 return MCDisassembler::Fail; // UNDEFINED 5004 index = fieldFromInstruction(Insn, 5, 3); 5005 break; 5006 case 1: 5007 if (fieldFromInstruction(Insn, 5, 1)) 5008 return MCDisassembler::Fail; // UNDEFINED 5009 index = fieldFromInstruction(Insn, 6, 2); 5010 if (fieldFromInstruction(Insn, 4, 1)) 5011 align = 2; 5012 break; 5013 case 2: 5014 if (fieldFromInstruction(Insn, 6, 1)) 5015 return MCDisassembler::Fail; // UNDEFINED 5016 index = fieldFromInstruction(Insn, 7, 1); 5017 5018 switch (fieldFromInstruction(Insn, 4, 2)) { 5019 case 0: 5020 align = 0; break; 5021 case 3: 5022 align = 4; break; 5023 default: 5024 return MCDisassembler::Fail; 5025 } 5026 break; 5027 } 5028 5029 if (Rm != 0xF) { // Writeback 5030 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5031 return MCDisassembler::Fail; 5032 } 5033 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5034 return MCDisassembler::Fail; 5035 Inst.addOperand(MCOperand::createImm(align)); 5036 if (Rm != 0xF) { 5037 if (Rm != 0xD) { 5038 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5039 return MCDisassembler::Fail; 5040 } else 5041 Inst.addOperand(MCOperand::createReg(0)); 5042 } 5043 5044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5045 return MCDisassembler::Fail; 5046 Inst.addOperand(MCOperand::createImm(index)); 5047 5048 return S; 5049 } 5050 5051 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 5052 uint64_t Address, const void *Decoder) { 5053 DecodeStatus S = MCDisassembler::Success; 5054 5055 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5056 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5057 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5058 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5059 unsigned size = fieldFromInstruction(Insn, 10, 2); 5060 5061 unsigned align = 0; 5062 unsigned index = 0; 5063 unsigned inc = 1; 5064 switch (size) { 5065 default: 5066 return MCDisassembler::Fail; 5067 case 0: 5068 index = fieldFromInstruction(Insn, 5, 3); 5069 if (fieldFromInstruction(Insn, 4, 1)) 5070 align = 2; 5071 break; 5072 case 1: 5073 index = fieldFromInstruction(Insn, 6, 2); 5074 if (fieldFromInstruction(Insn, 4, 1)) 5075 align = 4; 5076 if (fieldFromInstruction(Insn, 5, 1)) 5077 inc = 2; 5078 break; 5079 case 2: 5080 if (fieldFromInstruction(Insn, 5, 1)) 5081 return MCDisassembler::Fail; // UNDEFINED 5082 index = fieldFromInstruction(Insn, 7, 1); 5083 if (fieldFromInstruction(Insn, 4, 1) != 0) 5084 align = 8; 5085 if (fieldFromInstruction(Insn, 6, 1)) 5086 inc = 2; 5087 break; 5088 } 5089 5090 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5091 return MCDisassembler::Fail; 5092 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5093 return MCDisassembler::Fail; 5094 if (Rm != 0xF) { // Writeback 5095 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5096 return MCDisassembler::Fail; 5097 } 5098 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5099 return MCDisassembler::Fail; 5100 Inst.addOperand(MCOperand::createImm(align)); 5101 if (Rm != 0xF) { 5102 if (Rm != 0xD) { 5103 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5104 return MCDisassembler::Fail; 5105 } else 5106 Inst.addOperand(MCOperand::createReg(0)); 5107 } 5108 5109 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5110 return MCDisassembler::Fail; 5111 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5112 return MCDisassembler::Fail; 5113 Inst.addOperand(MCOperand::createImm(index)); 5114 5115 return S; 5116 } 5117 5118 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 5119 uint64_t Address, const void *Decoder) { 5120 DecodeStatus S = MCDisassembler::Success; 5121 5122 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5123 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5124 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5125 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5126 unsigned size = fieldFromInstruction(Insn, 10, 2); 5127 5128 unsigned align = 0; 5129 unsigned index = 0; 5130 unsigned inc = 1; 5131 switch (size) { 5132 default: 5133 return MCDisassembler::Fail; 5134 case 0: 5135 index = fieldFromInstruction(Insn, 5, 3); 5136 if (fieldFromInstruction(Insn, 4, 1)) 5137 align = 2; 5138 break; 5139 case 1: 5140 index = fieldFromInstruction(Insn, 6, 2); 5141 if (fieldFromInstruction(Insn, 4, 1)) 5142 align = 4; 5143 if (fieldFromInstruction(Insn, 5, 1)) 5144 inc = 2; 5145 break; 5146 case 2: 5147 if (fieldFromInstruction(Insn, 5, 1)) 5148 return MCDisassembler::Fail; // UNDEFINED 5149 index = fieldFromInstruction(Insn, 7, 1); 5150 if (fieldFromInstruction(Insn, 4, 1) != 0) 5151 align = 8; 5152 if (fieldFromInstruction(Insn, 6, 1)) 5153 inc = 2; 5154 break; 5155 } 5156 5157 if (Rm != 0xF) { // Writeback 5158 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5159 return MCDisassembler::Fail; 5160 } 5161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5162 return MCDisassembler::Fail; 5163 Inst.addOperand(MCOperand::createImm(align)); 5164 if (Rm != 0xF) { 5165 if (Rm != 0xD) { 5166 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5167 return MCDisassembler::Fail; 5168 } else 5169 Inst.addOperand(MCOperand::createReg(0)); 5170 } 5171 5172 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5173 return MCDisassembler::Fail; 5174 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5175 return MCDisassembler::Fail; 5176 Inst.addOperand(MCOperand::createImm(index)); 5177 5178 return S; 5179 } 5180 5181 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 5182 uint64_t Address, const void *Decoder) { 5183 DecodeStatus S = MCDisassembler::Success; 5184 5185 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5186 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5187 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5188 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5189 unsigned size = fieldFromInstruction(Insn, 10, 2); 5190 5191 unsigned align = 0; 5192 unsigned index = 0; 5193 unsigned inc = 1; 5194 switch (size) { 5195 default: 5196 return MCDisassembler::Fail; 5197 case 0: 5198 if (fieldFromInstruction(Insn, 4, 1)) 5199 return MCDisassembler::Fail; // UNDEFINED 5200 index = fieldFromInstruction(Insn, 5, 3); 5201 break; 5202 case 1: 5203 if (fieldFromInstruction(Insn, 4, 1)) 5204 return MCDisassembler::Fail; // UNDEFINED 5205 index = fieldFromInstruction(Insn, 6, 2); 5206 if (fieldFromInstruction(Insn, 5, 1)) 5207 inc = 2; 5208 break; 5209 case 2: 5210 if (fieldFromInstruction(Insn, 4, 2)) 5211 return MCDisassembler::Fail; // UNDEFINED 5212 index = fieldFromInstruction(Insn, 7, 1); 5213 if (fieldFromInstruction(Insn, 6, 1)) 5214 inc = 2; 5215 break; 5216 } 5217 5218 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5219 return MCDisassembler::Fail; 5220 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5221 return MCDisassembler::Fail; 5222 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5223 return MCDisassembler::Fail; 5224 5225 if (Rm != 0xF) { // Writeback 5226 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5227 return MCDisassembler::Fail; 5228 } 5229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5230 return MCDisassembler::Fail; 5231 Inst.addOperand(MCOperand::createImm(align)); 5232 if (Rm != 0xF) { 5233 if (Rm != 0xD) { 5234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5235 return MCDisassembler::Fail; 5236 } else 5237 Inst.addOperand(MCOperand::createReg(0)); 5238 } 5239 5240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5241 return MCDisassembler::Fail; 5242 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5243 return MCDisassembler::Fail; 5244 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5245 return MCDisassembler::Fail; 5246 Inst.addOperand(MCOperand::createImm(index)); 5247 5248 return S; 5249 } 5250 5251 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 5252 uint64_t Address, const void *Decoder) { 5253 DecodeStatus S = MCDisassembler::Success; 5254 5255 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5256 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5257 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5258 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5259 unsigned size = fieldFromInstruction(Insn, 10, 2); 5260 5261 unsigned align = 0; 5262 unsigned index = 0; 5263 unsigned inc = 1; 5264 switch (size) { 5265 default: 5266 return MCDisassembler::Fail; 5267 case 0: 5268 if (fieldFromInstruction(Insn, 4, 1)) 5269 return MCDisassembler::Fail; // UNDEFINED 5270 index = fieldFromInstruction(Insn, 5, 3); 5271 break; 5272 case 1: 5273 if (fieldFromInstruction(Insn, 4, 1)) 5274 return MCDisassembler::Fail; // UNDEFINED 5275 index = fieldFromInstruction(Insn, 6, 2); 5276 if (fieldFromInstruction(Insn, 5, 1)) 5277 inc = 2; 5278 break; 5279 case 2: 5280 if (fieldFromInstruction(Insn, 4, 2)) 5281 return MCDisassembler::Fail; // UNDEFINED 5282 index = fieldFromInstruction(Insn, 7, 1); 5283 if (fieldFromInstruction(Insn, 6, 1)) 5284 inc = 2; 5285 break; 5286 } 5287 5288 if (Rm != 0xF) { // Writeback 5289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5290 return MCDisassembler::Fail; 5291 } 5292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5293 return MCDisassembler::Fail; 5294 Inst.addOperand(MCOperand::createImm(align)); 5295 if (Rm != 0xF) { 5296 if (Rm != 0xD) { 5297 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5298 return MCDisassembler::Fail; 5299 } else 5300 Inst.addOperand(MCOperand::createReg(0)); 5301 } 5302 5303 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5304 return MCDisassembler::Fail; 5305 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5306 return MCDisassembler::Fail; 5307 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5308 return MCDisassembler::Fail; 5309 Inst.addOperand(MCOperand::createImm(index)); 5310 5311 return S; 5312 } 5313 5314 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 5315 uint64_t Address, const void *Decoder) { 5316 DecodeStatus S = MCDisassembler::Success; 5317 5318 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5319 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5320 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5321 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5322 unsigned size = fieldFromInstruction(Insn, 10, 2); 5323 5324 unsigned align = 0; 5325 unsigned index = 0; 5326 unsigned inc = 1; 5327 switch (size) { 5328 default: 5329 return MCDisassembler::Fail; 5330 case 0: 5331 if (fieldFromInstruction(Insn, 4, 1)) 5332 align = 4; 5333 index = fieldFromInstruction(Insn, 5, 3); 5334 break; 5335 case 1: 5336 if (fieldFromInstruction(Insn, 4, 1)) 5337 align = 8; 5338 index = fieldFromInstruction(Insn, 6, 2); 5339 if (fieldFromInstruction(Insn, 5, 1)) 5340 inc = 2; 5341 break; 5342 case 2: 5343 switch (fieldFromInstruction(Insn, 4, 2)) { 5344 case 0: 5345 align = 0; break; 5346 case 3: 5347 return MCDisassembler::Fail; 5348 default: 5349 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5350 } 5351 5352 index = fieldFromInstruction(Insn, 7, 1); 5353 if (fieldFromInstruction(Insn, 6, 1)) 5354 inc = 2; 5355 break; 5356 } 5357 5358 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5359 return MCDisassembler::Fail; 5360 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5361 return MCDisassembler::Fail; 5362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5363 return MCDisassembler::Fail; 5364 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5365 return MCDisassembler::Fail; 5366 5367 if (Rm != 0xF) { // Writeback 5368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5369 return MCDisassembler::Fail; 5370 } 5371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5372 return MCDisassembler::Fail; 5373 Inst.addOperand(MCOperand::createImm(align)); 5374 if (Rm != 0xF) { 5375 if (Rm != 0xD) { 5376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5377 return MCDisassembler::Fail; 5378 } else 5379 Inst.addOperand(MCOperand::createReg(0)); 5380 } 5381 5382 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5383 return MCDisassembler::Fail; 5384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5385 return MCDisassembler::Fail; 5386 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5387 return MCDisassembler::Fail; 5388 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5389 return MCDisassembler::Fail; 5390 Inst.addOperand(MCOperand::createImm(index)); 5391 5392 return S; 5393 } 5394 5395 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 5396 uint64_t Address, const void *Decoder) { 5397 DecodeStatus S = MCDisassembler::Success; 5398 5399 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5400 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5401 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5402 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5403 unsigned size = fieldFromInstruction(Insn, 10, 2); 5404 5405 unsigned align = 0; 5406 unsigned index = 0; 5407 unsigned inc = 1; 5408 switch (size) { 5409 default: 5410 return MCDisassembler::Fail; 5411 case 0: 5412 if (fieldFromInstruction(Insn, 4, 1)) 5413 align = 4; 5414 index = fieldFromInstruction(Insn, 5, 3); 5415 break; 5416 case 1: 5417 if (fieldFromInstruction(Insn, 4, 1)) 5418 align = 8; 5419 index = fieldFromInstruction(Insn, 6, 2); 5420 if (fieldFromInstruction(Insn, 5, 1)) 5421 inc = 2; 5422 break; 5423 case 2: 5424 switch (fieldFromInstruction(Insn, 4, 2)) { 5425 case 0: 5426 align = 0; break; 5427 case 3: 5428 return MCDisassembler::Fail; 5429 default: 5430 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5431 } 5432 5433 index = fieldFromInstruction(Insn, 7, 1); 5434 if (fieldFromInstruction(Insn, 6, 1)) 5435 inc = 2; 5436 break; 5437 } 5438 5439 if (Rm != 0xF) { // Writeback 5440 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5441 return MCDisassembler::Fail; 5442 } 5443 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5444 return MCDisassembler::Fail; 5445 Inst.addOperand(MCOperand::createImm(align)); 5446 if (Rm != 0xF) { 5447 if (Rm != 0xD) { 5448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5449 return MCDisassembler::Fail; 5450 } else 5451 Inst.addOperand(MCOperand::createReg(0)); 5452 } 5453 5454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5455 return MCDisassembler::Fail; 5456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5457 return MCDisassembler::Fail; 5458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5459 return MCDisassembler::Fail; 5460 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5461 return MCDisassembler::Fail; 5462 Inst.addOperand(MCOperand::createImm(index)); 5463 5464 return S; 5465 } 5466 5467 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 5468 uint64_t Address, const void *Decoder) { 5469 DecodeStatus S = MCDisassembler::Success; 5470 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5471 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5472 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5473 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5474 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5475 5476 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5477 S = MCDisassembler::SoftFail; 5478 5479 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5480 return MCDisassembler::Fail; 5481 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5482 return MCDisassembler::Fail; 5483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5484 return MCDisassembler::Fail; 5485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5486 return MCDisassembler::Fail; 5487 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5488 return MCDisassembler::Fail; 5489 5490 return S; 5491 } 5492 5493 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 5494 uint64_t Address, const void *Decoder) { 5495 DecodeStatus S = MCDisassembler::Success; 5496 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5497 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5498 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5499 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5500 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5501 5502 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5503 S = MCDisassembler::SoftFail; 5504 5505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5506 return MCDisassembler::Fail; 5507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5508 return MCDisassembler::Fail; 5509 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5510 return MCDisassembler::Fail; 5511 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5512 return MCDisassembler::Fail; 5513 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5514 return MCDisassembler::Fail; 5515 5516 return S; 5517 } 5518 5519 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 5520 uint64_t Address, const void *Decoder) { 5521 DecodeStatus S = MCDisassembler::Success; 5522 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5523 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5524 5525 if (pred == 0xF) { 5526 pred = 0xE; 5527 S = MCDisassembler::SoftFail; 5528 } 5529 5530 if (mask == 0x0) 5531 return MCDisassembler::Fail; 5532 5533 // IT masks are encoded as a sequence of replacement low-order bits 5534 // for the condition code. So if the low bit of the starting 5535 // condition code is 1, then we have to flip all the bits above the 5536 // terminating bit (which is the lowest 1 bit). 5537 if (pred & 1) { 5538 unsigned LowBit = mask & -mask; 5539 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5540 mask ^= BitsAboveLowBit; 5541 } 5542 5543 Inst.addOperand(MCOperand::createImm(pred)); 5544 Inst.addOperand(MCOperand::createImm(mask)); 5545 return S; 5546 } 5547 5548 static DecodeStatus 5549 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5550 uint64_t Address, const void *Decoder) { 5551 DecodeStatus S = MCDisassembler::Success; 5552 5553 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5554 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5555 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5556 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5557 unsigned W = fieldFromInstruction(Insn, 21, 1); 5558 unsigned U = fieldFromInstruction(Insn, 23, 1); 5559 unsigned P = fieldFromInstruction(Insn, 24, 1); 5560 bool writeback = (W == 1) | (P == 0); 5561 5562 addr |= (U << 8) | (Rn << 9); 5563 5564 if (writeback && (Rn == Rt || Rn == Rt2)) 5565 Check(S, MCDisassembler::SoftFail); 5566 if (Rt == Rt2) 5567 Check(S, MCDisassembler::SoftFail); 5568 5569 // Rt 5570 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5571 return MCDisassembler::Fail; 5572 // Rt2 5573 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5574 return MCDisassembler::Fail; 5575 // Writeback operand 5576 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5577 return MCDisassembler::Fail; 5578 // addr 5579 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5580 return MCDisassembler::Fail; 5581 5582 return S; 5583 } 5584 5585 static DecodeStatus 5586 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5587 uint64_t Address, const void *Decoder) { 5588 DecodeStatus S = MCDisassembler::Success; 5589 5590 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5591 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5592 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5593 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5594 unsigned W = fieldFromInstruction(Insn, 21, 1); 5595 unsigned U = fieldFromInstruction(Insn, 23, 1); 5596 unsigned P = fieldFromInstruction(Insn, 24, 1); 5597 bool writeback = (W == 1) | (P == 0); 5598 5599 addr |= (U << 8) | (Rn << 9); 5600 5601 if (writeback && (Rn == Rt || Rn == Rt2)) 5602 Check(S, MCDisassembler::SoftFail); 5603 5604 // Writeback operand 5605 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5606 return MCDisassembler::Fail; 5607 // Rt 5608 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5609 return MCDisassembler::Fail; 5610 // Rt2 5611 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5612 return MCDisassembler::Fail; 5613 // addr 5614 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5615 return MCDisassembler::Fail; 5616 5617 return S; 5618 } 5619 5620 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 5621 uint64_t Address, const void *Decoder) { 5622 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5623 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5624 if (sign1 != sign2) return MCDisassembler::Fail; 5625 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5626 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5627 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5628 5629 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5630 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5631 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5632 // If sign, then it is decreasing the address. 5633 if (sign1) { 5634 // Following ARMv7 Architecture Manual, when the offset 5635 // is zero, it is decoded as a subw, not as a adr.w 5636 if (!Val) { 5637 Inst.setOpcode(ARM::t2SUBri12); 5638 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5639 } else 5640 Val = -Val; 5641 } 5642 Inst.addOperand(MCOperand::createImm(Val)); 5643 return S; 5644 } 5645 5646 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5647 uint64_t Address, 5648 const void *Decoder) { 5649 DecodeStatus S = MCDisassembler::Success; 5650 5651 // Shift of "asr #32" is not allowed in Thumb2 mode. 5652 if (Val == 0x20) S = MCDisassembler::Fail; 5653 Inst.addOperand(MCOperand::createImm(Val)); 5654 return S; 5655 } 5656 5657 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 5658 uint64_t Address, const void *Decoder) { 5659 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5660 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5661 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5662 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5663 5664 if (pred == 0xF) 5665 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5666 5667 DecodeStatus S = MCDisassembler::Success; 5668 5669 if (Rt == Rn || Rn == Rt2) 5670 S = MCDisassembler::SoftFail; 5671 5672 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5673 return MCDisassembler::Fail; 5674 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5675 return MCDisassembler::Fail; 5676 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5677 return MCDisassembler::Fail; 5678 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5679 return MCDisassembler::Fail; 5680 5681 return S; 5682 } 5683 5684 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5685 uint64_t Address, const void *Decoder) { 5686 const FeatureBitset &featureBits = 5687 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5688 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5689 5690 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5691 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5692 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5693 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5694 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5695 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5696 unsigned op = fieldFromInstruction(Insn, 5, 1); 5697 5698 DecodeStatus S = MCDisassembler::Success; 5699 5700 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5701 if (!(imm & 0x38)) { 5702 if (cmode == 0xF) { 5703 if (op == 1) return MCDisassembler::Fail; 5704 Inst.setOpcode(ARM::VMOVv2f32); 5705 } 5706 if (hasFullFP16) { 5707 if (cmode == 0xE) { 5708 if (op == 1) { 5709 Inst.setOpcode(ARM::VMOVv1i64); 5710 } else { 5711 Inst.setOpcode(ARM::VMOVv8i8); 5712 } 5713 } 5714 if (cmode == 0xD) { 5715 if (op == 1) { 5716 Inst.setOpcode(ARM::VMVNv2i32); 5717 } else { 5718 Inst.setOpcode(ARM::VMOVv2i32); 5719 } 5720 } 5721 if (cmode == 0xC) { 5722 if (op == 1) { 5723 Inst.setOpcode(ARM::VMVNv2i32); 5724 } else { 5725 Inst.setOpcode(ARM::VMOVv2i32); 5726 } 5727 } 5728 } 5729 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5730 } 5731 5732 if (!(imm & 0x20)) return MCDisassembler::Fail; 5733 5734 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5735 return MCDisassembler::Fail; 5736 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5737 return MCDisassembler::Fail; 5738 Inst.addOperand(MCOperand::createImm(64 - imm)); 5739 5740 return S; 5741 } 5742 5743 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5744 uint64_t Address, const void *Decoder) { 5745 const FeatureBitset &featureBits = 5746 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5747 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 5748 5749 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5750 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5751 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5752 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5753 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5754 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5755 unsigned op = fieldFromInstruction(Insn, 5, 1); 5756 5757 DecodeStatus S = MCDisassembler::Success; 5758 5759 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 5760 if (!(imm & 0x38)) { 5761 if (cmode == 0xF) { 5762 if (op == 1) return MCDisassembler::Fail; 5763 Inst.setOpcode(ARM::VMOVv4f32); 5764 } 5765 if (hasFullFP16) { 5766 if (cmode == 0xE) { 5767 if (op == 1) { 5768 Inst.setOpcode(ARM::VMOVv2i64); 5769 } else { 5770 Inst.setOpcode(ARM::VMOVv16i8); 5771 } 5772 } 5773 if (cmode == 0xD) { 5774 if (op == 1) { 5775 Inst.setOpcode(ARM::VMVNv4i32); 5776 } else { 5777 Inst.setOpcode(ARM::VMOVv4i32); 5778 } 5779 } 5780 if (cmode == 0xC) { 5781 if (op == 1) { 5782 Inst.setOpcode(ARM::VMVNv4i32); 5783 } else { 5784 Inst.setOpcode(ARM::VMOVv4i32); 5785 } 5786 } 5787 } 5788 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 5789 } 5790 5791 if (!(imm & 0x20)) return MCDisassembler::Fail; 5792 5793 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5794 return MCDisassembler::Fail; 5795 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5796 return MCDisassembler::Fail; 5797 Inst.addOperand(MCOperand::createImm(64 - imm)); 5798 5799 return S; 5800 } 5801 5802 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst, 5803 unsigned Insn, 5804 uint64_t Address, 5805 const void *Decoder) { 5806 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5807 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5808 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 5809 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 5810 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5811 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5812 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 5813 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 5814 5815 DecodeStatus S = MCDisassembler::Success; 5816 5817 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 5818 5819 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5820 return MCDisassembler::Fail; 5821 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 5822 return MCDisassembler::Fail; 5823 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 5824 return MCDisassembler::Fail; 5825 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5826 return MCDisassembler::Fail; 5827 // The lane index does not have any bits in the encoding, because it can only 5828 // be 0. 5829 Inst.addOperand(MCOperand::createImm(0)); 5830 Inst.addOperand(MCOperand::createImm(rotate)); 5831 5832 return S; 5833 } 5834 5835 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5836 uint64_t Address, const void *Decoder) { 5837 DecodeStatus S = MCDisassembler::Success; 5838 5839 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5840 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5841 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5842 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5843 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5844 5845 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5846 S = MCDisassembler::SoftFail; 5847 5848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5849 return MCDisassembler::Fail; 5850 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5851 return MCDisassembler::Fail; 5852 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5853 return MCDisassembler::Fail; 5854 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5855 return MCDisassembler::Fail; 5856 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5857 return MCDisassembler::Fail; 5858 5859 return S; 5860 } 5861 5862 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 5863 uint64_t Address, const void *Decoder) { 5864 DecodeStatus S = MCDisassembler::Success; 5865 5866 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5867 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5868 unsigned cop = fieldFromInstruction(Val, 8, 4); 5869 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5870 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5871 5872 if ((cop & ~0x1) == 0xa) 5873 return MCDisassembler::Fail; 5874 5875 if (Rt == Rt2) 5876 S = MCDisassembler::SoftFail; 5877 5878 // We have to check if the instruction is MRRC2 5879 // or MCRR2 when constructing the operands for 5880 // Inst. Reason is because MRRC2 stores to two 5881 // registers so it's tablegen desc has has two 5882 // outputs whereas MCRR doesn't store to any 5883 // registers so all of it's operands are listed 5884 // as inputs, therefore the operand order for 5885 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 5886 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 5887 5888 if (Inst.getOpcode() == ARM::MRRC2) { 5889 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5890 return MCDisassembler::Fail; 5891 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5892 return MCDisassembler::Fail; 5893 } 5894 Inst.addOperand(MCOperand::createImm(cop)); 5895 Inst.addOperand(MCOperand::createImm(opc1)); 5896 if (Inst.getOpcode() == ARM::MCRR2) { 5897 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5898 return MCDisassembler::Fail; 5899 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5900 return MCDisassembler::Fail; 5901 } 5902 Inst.addOperand(MCOperand::createImm(CRm)); 5903 5904 return S; 5905 } 5906 5907 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 5908 uint64_t Address, 5909 const void *Decoder) { 5910 const FeatureBitset &featureBits = 5911 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 5912 DecodeStatus S = MCDisassembler::Success; 5913 5914 // Add explicit operand for the destination sysreg, for cases where 5915 // we have to model it for code generation purposes. 5916 switch (Inst.getOpcode()) { 5917 case ARM::VMSR_FPSCR_NZCVQC: 5918 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5919 break; 5920 case ARM::VMSR_P0: 5921 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5922 break; 5923 } 5924 5925 if (Inst.getOpcode() != ARM::FMSTAT) { 5926 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5927 5928 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 5929 if (Rt == 13 || Rt == 15) 5930 S = MCDisassembler::SoftFail; 5931 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 5932 } else 5933 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 5934 } 5935 5936 // Add explicit operand for the source sysreg, similarly to above. 5937 switch (Inst.getOpcode()) { 5938 case ARM::VMRS_FPSCR_NZCVQC: 5939 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 5940 break; 5941 case ARM::VMRS_P0: 5942 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 5943 break; 5944 } 5945 5946 if (featureBits[ARM::ModeThumb]) { 5947 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 5948 Inst.addOperand(MCOperand::createReg(0)); 5949 } else { 5950 unsigned pred = fieldFromInstruction(Val, 28, 4); 5951 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5952 return MCDisassembler::Fail; 5953 } 5954 5955 return S; 5956 } 5957 5958 template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 5959 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 5960 uint64_t Address, 5961 const void *Decoder) { 5962 DecodeStatus S = MCDisassembler::Success; 5963 if (Val == 0 && !zeroPermitted) 5964 S = MCDisassembler::Fail; 5965 5966 uint64_t DecVal; 5967 if (isSigned) 5968 DecVal = SignExtend32<size + 1>(Val << 1); 5969 else 5970 DecVal = (Val << 1); 5971 5972 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 5973 Decoder)) 5974 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 5975 return S; 5976 } 5977 5978 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 5979 uint64_t Address, 5980 const void *Decoder) { 5981 5982 uint64_t LocImm = Inst.getOperand(0).getImm(); 5983 Val = LocImm + (2 << Val); 5984 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 5985 Decoder)) 5986 Inst.addOperand(MCOperand::createImm(Val)); 5987 return MCDisassembler::Success; 5988 } 5989 5990 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 5991 uint64_t Address, 5992 const void *Decoder) { 5993 if (Val >= ARMCC::AL) // also exclude the non-condition NV 5994 return MCDisassembler::Fail; 5995 Inst.addOperand(MCOperand::createImm(Val)); 5996 return MCDisassembler::Success; 5997 } 5998 5999 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6000 const void *Decoder) { 6001 DecodeStatus S = MCDisassembler::Success; 6002 6003 if (Inst.getOpcode() == ARM::MVE_LCTP) 6004 return S; 6005 6006 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6007 fieldFromInstruction(Insn, 1, 10) << 1; 6008 switch (Inst.getOpcode()) { 6009 case ARM::t2LEUpdate: 6010 case ARM::MVE_LETP: 6011 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6012 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6013 LLVM_FALLTHROUGH; 6014 case ARM::t2LE: 6015 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6016 Inst, Imm, Address, Decoder))) 6017 return MCDisassembler::Fail; 6018 break; 6019 case ARM::t2WLS: 6020 case ARM::MVE_WLSTP_8: 6021 case ARM::MVE_WLSTP_16: 6022 case ARM::MVE_WLSTP_32: 6023 case ARM::MVE_WLSTP_64: 6024 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6025 if (!Check(S, 6026 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6027 Address, Decoder)) || 6028 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6029 Inst, Imm, Address, Decoder))) 6030 return MCDisassembler::Fail; 6031 break; 6032 case ARM::t2DLS: 6033 case ARM::MVE_DLSTP_8: 6034 case ARM::MVE_DLSTP_16: 6035 case ARM::MVE_DLSTP_32: 6036 case ARM::MVE_DLSTP_64: 6037 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6038 if (Rn == 0xF) { 6039 // Enforce all the rest of the instruction bits in LCTP, which 6040 // won't have been reliably checked based on LCTP's own tablegen 6041 // record, because we came to this decode by a roundabout route. 6042 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6043 if ((Insn & ~SBZMask) != CanonicalLCTP) 6044 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6045 if (Insn != CanonicalLCTP) 6046 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6047 6048 Inst.setOpcode(ARM::MVE_LCTP); 6049 } else { 6050 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6051 if (!Check(S, DecoderGPRRegisterClass(Inst, 6052 fieldFromInstruction(Insn, 16, 4), 6053 Address, Decoder))) 6054 return MCDisassembler::Fail; 6055 } 6056 break; 6057 } 6058 return S; 6059 } 6060 6061 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6062 uint64_t Address, 6063 const void *Decoder) { 6064 DecodeStatus S = MCDisassembler::Success; 6065 6066 if (Val == 0) 6067 Val = 32; 6068 6069 Inst.addOperand(MCOperand::createImm(Val)); 6070 6071 return S; 6072 } 6073 6074 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6075 uint64_t Address, const void *Decoder) { 6076 if ((RegNo) + 1 > 11) 6077 return MCDisassembler::Fail; 6078 6079 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6080 Inst.addOperand(MCOperand::createReg(Register)); 6081 return MCDisassembler::Success; 6082 } 6083 6084 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6085 uint64_t Address, const void *Decoder) { 6086 if ((RegNo) > 14) 6087 return MCDisassembler::Fail; 6088 6089 unsigned Register = GPRDecoderTable[(RegNo)]; 6090 Inst.addOperand(MCOperand::createReg(Register)); 6091 return MCDisassembler::Success; 6092 } 6093 6094 static DecodeStatus 6095 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6096 uint64_t Address, const void *Decoder) { 6097 if (RegNo == 15) { 6098 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6099 return MCDisassembler::Success; 6100 } 6101 6102 unsigned Register = GPRDecoderTable[RegNo]; 6103 Inst.addOperand(MCOperand::createReg(Register)); 6104 6105 if (RegNo == 13) 6106 return MCDisassembler::SoftFail; 6107 6108 return MCDisassembler::Success; 6109 } 6110 6111 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6112 const void *Decoder) { 6113 DecodeStatus S = MCDisassembler::Success; 6114 6115 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6116 Inst.addOperand(MCOperand::createReg(0)); 6117 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6118 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6119 (fieldFromInstruction(Insn, 12, 4) << 8) | 6120 (fieldFromInstruction(Insn, 22, 1) << 12); 6121 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6122 return MCDisassembler::Fail; 6123 } 6124 } else { 6125 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6126 (fieldFromInstruction(Insn, 22, 1) << 8) | 6127 (fieldFromInstruction(Insn, 12, 4) << 9); 6128 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6129 return MCDisassembler::Fail; 6130 } 6131 } 6132 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6133 6134 return S; 6135 } 6136 6137 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6138 uint64_t Address, 6139 const void *Decoder) { 6140 if (RegNo > 7) 6141 return MCDisassembler::Fail; 6142 6143 unsigned Register = QPRDecoderTable[RegNo]; 6144 Inst.addOperand(MCOperand::createReg(Register)); 6145 return MCDisassembler::Success; 6146 } 6147 6148 static const uint16_t QQPRDecoderTable[] = { 6149 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6150 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6151 }; 6152 6153 static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6154 uint64_t Address, 6155 const void *Decoder) { 6156 if (RegNo > 6) 6157 return MCDisassembler::Fail; 6158 6159 unsigned Register = QQPRDecoderTable[RegNo]; 6160 Inst.addOperand(MCOperand::createReg(Register)); 6161 return MCDisassembler::Success; 6162 } 6163 6164 static const uint16_t QQQQPRDecoderTable[] = { 6165 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6166 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6167 }; 6168 6169 static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6170 uint64_t Address, 6171 const void *Decoder) { 6172 if (RegNo > 4) 6173 return MCDisassembler::Fail; 6174 6175 unsigned Register = QQQQPRDecoderTable[RegNo]; 6176 Inst.addOperand(MCOperand::createReg(Register)); 6177 return MCDisassembler::Success; 6178 } 6179 6180 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6181 uint64_t Address, 6182 const void *Decoder) { 6183 DecodeStatus S = MCDisassembler::Success; 6184 6185 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6186 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6187 // 't' as 0 and finish with a 1. 6188 unsigned Imm = 0; 6189 // We always start with a 't'. 6190 unsigned CurBit = 0; 6191 for (int i = 3; i >= 0; --i) { 6192 // If the bit we are looking at is not the same as last one, invert the 6193 // CurBit, if it is the same leave it as is. 6194 CurBit ^= (Val >> i) & 1U; 6195 6196 // Encode the CurBit at the right place in the immediate. 6197 Imm |= (CurBit << i); 6198 6199 // If we are done, finish the encoding with a 1. 6200 if ((Val & ~(~0U << i)) == 0) { 6201 Imm |= 1U << i; 6202 break; 6203 } 6204 } 6205 6206 Inst.addOperand(MCOperand::createImm(Imm)); 6207 6208 return S; 6209 } 6210 6211 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6212 uint64_t Address, const void *Decoder) { 6213 // The vpred_r operand type includes an MQPR register field derived 6214 // from the encoding. But we don't actually want to add an operand 6215 // to the MCInst at this stage, because AddThumbPredicate will do it 6216 // later, and will infer the register number from the TIED_TO 6217 // constraint. So this is a deliberately empty decoder method that 6218 // will inhibit the auto-generated disassembly code from adding an 6219 // operand at all. 6220 return MCDisassembler::Success; 6221 } 6222 6223 static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst &Inst, 6224 unsigned Val, 6225 uint64_t Address, 6226 const void *Decoder) { 6227 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6228 return MCDisassembler::Success; 6229 } 6230 6231 static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst &Inst, 6232 unsigned Val, 6233 uint64_t Address, 6234 const void *Decoder) { 6235 unsigned Code; 6236 switch (Val & 0x3) { 6237 case 0: 6238 Code = ARMCC::GE; 6239 break; 6240 case 1: 6241 Code = ARMCC::LT; 6242 break; 6243 case 2: 6244 Code = ARMCC::GT; 6245 break; 6246 case 3: 6247 Code = ARMCC::LE; 6248 break; 6249 } 6250 Inst.addOperand(MCOperand::createImm(Code)); 6251 return MCDisassembler::Success; 6252 } 6253 6254 static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst &Inst, 6255 unsigned Val, 6256 uint64_t Address, 6257 const void *Decoder) { 6258 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6259 return MCDisassembler::Success; 6260 } 6261 6262 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, 6263 uint64_t Address, 6264 const void *Decoder) { 6265 unsigned Code; 6266 switch (Val) { 6267 default: 6268 return MCDisassembler::Fail; 6269 case 0: 6270 Code = ARMCC::EQ; 6271 break; 6272 case 1: 6273 Code = ARMCC::NE; 6274 break; 6275 case 4: 6276 Code = ARMCC::GE; 6277 break; 6278 case 5: 6279 Code = ARMCC::LT; 6280 break; 6281 case 6: 6282 Code = ARMCC::GT; 6283 break; 6284 case 7: 6285 Code = ARMCC::LE; 6286 break; 6287 } 6288 6289 Inst.addOperand(MCOperand::createImm(Code)); 6290 return MCDisassembler::Success; 6291 } 6292 6293 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6294 uint64_t Address, const void *Decoder) { 6295 DecodeStatus S = MCDisassembler::Success; 6296 6297 unsigned DecodedVal = 64 - Val; 6298 6299 switch (Inst.getOpcode()) { 6300 case ARM::MVE_VCVTf16s16_fix: 6301 case ARM::MVE_VCVTs16f16_fix: 6302 case ARM::MVE_VCVTf16u16_fix: 6303 case ARM::MVE_VCVTu16f16_fix: 6304 if (DecodedVal > 16) 6305 return MCDisassembler::Fail; 6306 break; 6307 case ARM::MVE_VCVTf32s32_fix: 6308 case ARM::MVE_VCVTs32f32_fix: 6309 case ARM::MVE_VCVTf32u32_fix: 6310 case ARM::MVE_VCVTu32f32_fix: 6311 if (DecodedVal > 32) 6312 return MCDisassembler::Fail; 6313 break; 6314 } 6315 6316 Inst.addOperand(MCOperand::createImm(64 - Val)); 6317 6318 return S; 6319 } 6320 6321 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6322 switch (Opcode) { 6323 case ARM::VSTR_P0_off: 6324 case ARM::VSTR_P0_pre: 6325 case ARM::VSTR_P0_post: 6326 case ARM::VLDR_P0_off: 6327 case ARM::VLDR_P0_pre: 6328 case ARM::VLDR_P0_post: 6329 return ARM::P0; 6330 default: 6331 return 0; 6332 } 6333 } 6334 6335 template<bool Writeback> 6336 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6337 uint64_t Address, 6338 const void *Decoder) { 6339 switch (Inst.getOpcode()) { 6340 case ARM::VSTR_FPSCR_pre: 6341 case ARM::VSTR_FPSCR_NZCVQC_pre: 6342 case ARM::VLDR_FPSCR_pre: 6343 case ARM::VLDR_FPSCR_NZCVQC_pre: 6344 case ARM::VSTR_FPSCR_off: 6345 case ARM::VSTR_FPSCR_NZCVQC_off: 6346 case ARM::VLDR_FPSCR_off: 6347 case ARM::VLDR_FPSCR_NZCVQC_off: 6348 case ARM::VSTR_FPSCR_post: 6349 case ARM::VSTR_FPSCR_NZCVQC_post: 6350 case ARM::VLDR_FPSCR_post: 6351 case ARM::VLDR_FPSCR_NZCVQC_post: 6352 const FeatureBitset &featureBits = 6353 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6354 6355 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6356 return MCDisassembler::Fail; 6357 } 6358 6359 DecodeStatus S = MCDisassembler::Success; 6360 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6361 Inst.addOperand(MCOperand::createReg(Sysreg)); 6362 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6363 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6364 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6365 6366 if (Writeback) { 6367 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6368 return MCDisassembler::Fail; 6369 } 6370 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6371 return MCDisassembler::Fail; 6372 6373 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6374 Inst.addOperand(MCOperand::createReg(0)); 6375 6376 return S; 6377 } 6378 6379 static inline DecodeStatus DecodeMVE_MEM_pre( 6380 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder, 6381 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6382 DecodeStatus S = MCDisassembler::Success; 6383 6384 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6385 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6386 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6387 6388 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6389 return MCDisassembler::Fail; 6390 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6391 return MCDisassembler::Fail; 6392 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6393 return MCDisassembler::Fail; 6394 6395 return S; 6396 } 6397 6398 template <int shift> 6399 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6400 uint64_t Address, const void *Decoder) { 6401 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6402 fieldFromInstruction(Val, 16, 3), 6403 DecodetGPRRegisterClass, 6404 DecodeTAddrModeImm7<shift>); 6405 } 6406 6407 template <int shift> 6408 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6409 uint64_t Address, const void *Decoder) { 6410 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6411 fieldFromInstruction(Val, 16, 4), 6412 DecoderGPRRegisterClass, 6413 DecodeT2AddrModeImm7<shift,1>); 6414 } 6415 6416 template <int shift> 6417 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6418 uint64_t Address, const void *Decoder) { 6419 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6420 fieldFromInstruction(Val, 17, 3), 6421 DecodeMQPRRegisterClass, 6422 DecodeMveAddrModeQ<shift>); 6423 } 6424 6425 template<unsigned MinLog, unsigned MaxLog> 6426 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6427 uint64_t Address, 6428 const void *Decoder) { 6429 DecodeStatus S = MCDisassembler::Success; 6430 6431 if (Val < MinLog || Val > MaxLog) 6432 return MCDisassembler::Fail; 6433 6434 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6435 return S; 6436 } 6437 6438 template<unsigned start> 6439 static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, 6440 uint64_t Address, 6441 const void *Decoder) { 6442 DecodeStatus S = MCDisassembler::Success; 6443 6444 Inst.addOperand(MCOperand::createImm(start + Val)); 6445 6446 return S; 6447 } 6448 6449 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6450 uint64_t Address, const void *Decoder) { 6451 DecodeStatus S = MCDisassembler::Success; 6452 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6453 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6454 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6455 fieldFromInstruction(Insn, 13, 3)); 6456 unsigned index = fieldFromInstruction(Insn, 4, 1); 6457 6458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6459 return MCDisassembler::Fail; 6460 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6461 return MCDisassembler::Fail; 6462 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6463 return MCDisassembler::Fail; 6464 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6465 return MCDisassembler::Fail; 6466 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6467 return MCDisassembler::Fail; 6468 6469 return S; 6470 } 6471 6472 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6473 uint64_t Address, const void *Decoder) { 6474 DecodeStatus S = MCDisassembler::Success; 6475 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6476 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6477 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6478 fieldFromInstruction(Insn, 13, 3)); 6479 unsigned index = fieldFromInstruction(Insn, 4, 1); 6480 6481 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6482 return MCDisassembler::Fail; 6483 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6484 return MCDisassembler::Fail; 6485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6486 return MCDisassembler::Fail; 6487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6488 return MCDisassembler::Fail; 6489 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6490 return MCDisassembler::Fail; 6491 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6492 return MCDisassembler::Fail; 6493 6494 return S; 6495 } 6496 6497 static DecodeStatus DecodeMVEOverlappingLongShift( 6498 MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { 6499 DecodeStatus S = MCDisassembler::Success; 6500 6501 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6502 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6503 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6504 6505 if (RdaHi == 14) { 6506 // This value of RdaHi (really indicating pc, because RdaHi has to 6507 // be an odd-numbered register, so the low bit will be set by the 6508 // decode function below) indicates that we must decode as SQRSHR 6509 // or UQRSHL, which both have a single Rda register field with all 6510 // four bits. 6511 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6512 6513 switch (Inst.getOpcode()) { 6514 case ARM::MVE_ASRLr: 6515 case ARM::MVE_SQRSHRL: 6516 Inst.setOpcode(ARM::MVE_SQRSHR); 6517 break; 6518 case ARM::MVE_LSLLr: 6519 case ARM::MVE_UQRSHLL: 6520 Inst.setOpcode(ARM::MVE_UQRSHL); 6521 break; 6522 default: 6523 llvm_unreachable("Unexpected starting opcode!"); 6524 } 6525 6526 // Rda as output parameter 6527 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6528 return MCDisassembler::Fail; 6529 6530 // Rda again as input parameter 6531 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6532 return MCDisassembler::Fail; 6533 6534 // Rm, the amount to shift by 6535 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6536 return MCDisassembler::Fail; 6537 6538 if (fieldFromInstruction (Insn, 6, 3) != 4) 6539 return MCDisassembler::SoftFail; 6540 6541 if (Rda == Rm) 6542 return MCDisassembler::SoftFail; 6543 6544 return S; 6545 } 6546 6547 // Otherwise, we decode as whichever opcode our caller has already 6548 // put into Inst. Those all look the same: 6549 6550 // RdaLo,RdaHi as output parameters 6551 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6552 return MCDisassembler::Fail; 6553 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6554 return MCDisassembler::Fail; 6555 6556 // RdaLo,RdaHi again as input parameters 6557 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6558 return MCDisassembler::Fail; 6559 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6560 return MCDisassembler::Fail; 6561 6562 // Rm, the amount to shift by 6563 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6564 return MCDisassembler::Fail; 6565 6566 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6567 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6568 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6569 // Saturate, the bit position for saturation 6570 Inst.addOperand(MCOperand::createImm(Saturate)); 6571 } 6572 6573 return S; 6574 } 6575 6576 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address, 6577 const void *Decoder) { 6578 DecodeStatus S = MCDisassembler::Success; 6579 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6580 fieldFromInstruction(Insn, 13, 3)); 6581 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6582 fieldFromInstruction(Insn, 1, 3)); 6583 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6584 6585 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6586 return MCDisassembler::Fail; 6587 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6588 return MCDisassembler::Fail; 6589 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6590 return MCDisassembler::Fail; 6591 6592 return S; 6593 } 6594 6595 template<bool scalar, OperandDecoder predicate_decoder> 6596 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6597 const void *Decoder) { 6598 DecodeStatus S = MCDisassembler::Success; 6599 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6600 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6601 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6602 return MCDisassembler::Fail; 6603 6604 unsigned fc; 6605 6606 if (scalar) { 6607 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6608 fieldFromInstruction(Insn, 7, 1) | 6609 fieldFromInstruction(Insn, 5, 1) << 1; 6610 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6611 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6612 return MCDisassembler::Fail; 6613 } else { 6614 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6615 fieldFromInstruction(Insn, 7, 1) | 6616 fieldFromInstruction(Insn, 0, 1) << 1; 6617 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6618 fieldFromInstruction(Insn, 1, 3); 6619 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6620 return MCDisassembler::Fail; 6621 } 6622 6623 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6624 return MCDisassembler::Fail; 6625 6626 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6627 Inst.addOperand(MCOperand::createReg(0)); 6628 Inst.addOperand(MCOperand::createImm(0)); 6629 6630 return S; 6631 } 6632 6633 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6634 const void *Decoder) { 6635 DecodeStatus S = MCDisassembler::Success; 6636 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6637 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6638 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6639 return MCDisassembler::Fail; 6640 return S; 6641 } 6642 6643 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, uint64_t Address, 6644 const void *Decoder) { 6645 DecodeStatus S = MCDisassembler::Success; 6646 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6647 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6648 return S; 6649 } 6650 6651 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 6652 uint64_t Address, const void *Decoder) { 6653 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 6654 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6655 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 6656 fieldFromInstruction(Insn, 12, 3) << 8 | 6657 fieldFromInstruction(Insn, 0, 8); 6658 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 6659 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 6660 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 6661 unsigned S = fieldFromInstruction(Insn, 20, 1); 6662 if (sign1 != sign2) 6663 return MCDisassembler::Fail; 6664 6665 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 6666 DecodeStatus DS = MCDisassembler::Success; 6667 if ((!Check(DS, 6668 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 6669 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 6670 return MCDisassembler::Fail; 6671 if (TypeT3) { 6672 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 6673 S = 0; 6674 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 6675 } else { 6676 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 6677 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 6678 return MCDisassembler::Fail; 6679 } 6680 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 6681 return MCDisassembler::Fail; 6682 6683 Inst.addOperand(MCOperand::createReg(0)); // pred 6684 6685 return DS; 6686 } 6687