xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (revision acb1f1269c6f4ff89a0d28ba742f6687e9ef779d)
1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "ARMFeatures.h"
10 #include "ARMBaseInstrInfo.h"
11 #include "Utils/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMBaseInfo.h"
14 #include "MCTargetDesc/ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "MCTargetDesc/ARMMCTargetDesc.h"
17 #include "TargetInfo/ARMTargetInfo.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringMap.h"
25 #include "llvm/ADT/StringSet.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCExpr.h"
32 #include "llvm/MC/MCInst.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/MC/MCInstrInfo.h"
35 #include "llvm/MC/MCObjectFileInfo.h"
36 #include "llvm/MC/MCParser/MCAsmLexer.h"
37 #include "llvm/MC/MCParser/MCAsmParser.h"
38 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
39 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
40 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
41 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
42 #include "llvm/MC/MCRegisterInfo.h"
43 #include "llvm/MC/MCSection.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSubtargetInfo.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/MC/SubtargetFeature.h"
48 #include "llvm/Support/ARMBuildAttributes.h"
49 #include "llvm/Support/ARMEHABI.h"
50 #include "llvm/Support/Casting.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Support/SMLoc.h"
56 #include "llvm/Support/TargetParser.h"
57 #include "llvm/Support/TargetRegistry.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include <algorithm>
60 #include <cassert>
61 #include <cstddef>
62 #include <cstdint>
63 #include <iterator>
64 #include <limits>
65 #include <memory>
66 #include <string>
67 #include <utility>
68 #include <vector>
69 
70 #define DEBUG_TYPE "asm-parser"
71 
72 using namespace llvm;
73 
74 namespace llvm {
75 extern const MCInstrDesc ARMInsts[];
76 } // end namespace llvm
77 
78 namespace {
79 
80 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
81 
82 static cl::opt<ImplicitItModeTy> ImplicitItMode(
83     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
84     cl::desc("Allow conditional instructions outdside of an IT block"),
85     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
86                           "Accept in both ISAs, emit implicit ITs in Thumb"),
87                clEnumValN(ImplicitItModeTy::Never, "never",
88                           "Warn in ARM, reject in Thumb"),
89                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
90                           "Accept in ARM, reject in Thumb"),
91                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
92                           "Warn in ARM, emit implicit ITs in Thumb")));
93 
94 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
95                                         cl::init(false));
96 
97 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
98 
99 static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
100   // Position==0 means we're not in an IT block at all. Position==1
101   // means we want the first state bit, which is always 0 (Then).
102   // Position==2 means we want the second state bit, stored at bit 3
103   // of Mask, and so on downwards. So (5 - Position) will shift the
104   // right bit down to bit 0, including the always-0 bit at bit 4 for
105   // the mandatory initial Then.
106   return (Mask >> (5 - Position) & 1);
107 }
108 
109 class UnwindContext {
110   using Locs = SmallVector<SMLoc, 4>;
111 
112   MCAsmParser &Parser;
113   Locs FnStartLocs;
114   Locs CantUnwindLocs;
115   Locs PersonalityLocs;
116   Locs PersonalityIndexLocs;
117   Locs HandlerDataLocs;
118   int FPReg;
119 
120 public:
121   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
122 
123   bool hasFnStart() const { return !FnStartLocs.empty(); }
124   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
125   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
126 
127   bool hasPersonality() const {
128     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
129   }
130 
131   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
132   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
133   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
134   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
135   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
136 
137   void saveFPReg(int Reg) { FPReg = Reg; }
138   int getFPReg() const { return FPReg; }
139 
140   void emitFnStartLocNotes() const {
141     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
142          FI != FE; ++FI)
143       Parser.Note(*FI, ".fnstart was specified here");
144   }
145 
146   void emitCantUnwindLocNotes() const {
147     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
148                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
149       Parser.Note(*UI, ".cantunwind was specified here");
150   }
151 
152   void emitHandlerDataLocNotes() const {
153     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
154                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
155       Parser.Note(*HI, ".handlerdata was specified here");
156   }
157 
158   void emitPersonalityLocNotes() const {
159     for (Locs::const_iterator PI = PersonalityLocs.begin(),
160                               PE = PersonalityLocs.end(),
161                               PII = PersonalityIndexLocs.begin(),
162                               PIE = PersonalityIndexLocs.end();
163          PI != PE || PII != PIE;) {
164       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
165         Parser.Note(*PI++, ".personality was specified here");
166       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
167         Parser.Note(*PII++, ".personalityindex was specified here");
168       else
169         llvm_unreachable(".personality and .personalityindex cannot be "
170                          "at the same location");
171     }
172   }
173 
174   void reset() {
175     FnStartLocs = Locs();
176     CantUnwindLocs = Locs();
177     PersonalityLocs = Locs();
178     HandlerDataLocs = Locs();
179     PersonalityIndexLocs = Locs();
180     FPReg = ARM::SP;
181   }
182 };
183 
184 // Various sets of ARM instruction mnemonics which are used by the asm parser
185 class ARMMnemonicSets {
186   StringSet<> CDE;
187   StringSet<> CDEWithVPTSuffix;
188 public:
189   ARMMnemonicSets(const MCSubtargetInfo &STI);
190 
191   /// Returns true iff a given mnemonic is a CDE instruction
192   bool isCDEInstr(StringRef Mnemonic) {
193     // Quick check before searching the set
194     if (!Mnemonic.startswith("cx") && !Mnemonic.startswith("vcx"))
195       return false;
196     return CDE.count(Mnemonic);
197   }
198 
199   /// Returns true iff a given mnemonic is a VPT-predicable CDE instruction
200   /// (possibly with a predication suffix "e" or "t")
201   bool isVPTPredicableCDEInstr(StringRef Mnemonic) {
202     if (!Mnemonic.startswith("vcx"))
203       return false;
204     return CDEWithVPTSuffix.count(Mnemonic);
205   }
206 
207   /// Returns true iff a given mnemonic is an IT-predicable CDE instruction
208   /// (possibly with a condition suffix)
209   bool isITPredicableCDEInstr(StringRef Mnemonic) {
210     if (!Mnemonic.startswith("cx"))
211       return false;
212     return Mnemonic.startswith("cx1a") || Mnemonic.startswith("cx1da") ||
213            Mnemonic.startswith("cx2a") || Mnemonic.startswith("cx2da") ||
214            Mnemonic.startswith("cx3a") || Mnemonic.startswith("cx3da");
215   }
216 
217   /// Return true iff a given mnemonic is an integer CDE instruction with
218   /// dual-register destination
219   bool isCDEDualRegInstr(StringRef Mnemonic) {
220     if (!Mnemonic.startswith("cx"))
221       return false;
222     return Mnemonic == "cx1d" || Mnemonic == "cx1da" ||
223            Mnemonic == "cx2d" || Mnemonic == "cx2da" ||
224            Mnemonic == "cx3d" || Mnemonic == "cx3da";
225   }
226 };
227 
228 ARMMnemonicSets::ARMMnemonicSets(const MCSubtargetInfo &STI) {
229   for (StringRef Mnemonic: { "cx1", "cx1a", "cx1d", "cx1da",
230                              "cx2", "cx2a", "cx2d", "cx2da",
231                              "cx3", "cx3a", "cx3d", "cx3da", })
232     CDE.insert(Mnemonic);
233   for (StringRef Mnemonic :
234        {"vcx1", "vcx1a", "vcx2", "vcx2a", "vcx3", "vcx3a"}) {
235     CDE.insert(Mnemonic);
236     CDEWithVPTSuffix.insert(Mnemonic);
237     CDEWithVPTSuffix.insert(std::string(Mnemonic) + "t");
238     CDEWithVPTSuffix.insert(std::string(Mnemonic) + "e");
239   }
240 }
241 
242 class ARMAsmParser : public MCTargetAsmParser {
243   const MCRegisterInfo *MRI;
244   UnwindContext UC;
245   ARMMnemonicSets MS;
246 
247   ARMTargetStreamer &getTargetStreamer() {
248     assert(getParser().getStreamer().getTargetStreamer() &&
249            "do not have a target streamer");
250     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
251     return static_cast<ARMTargetStreamer &>(TS);
252   }
253 
254   // Map of register aliases registers via the .req directive.
255   StringMap<unsigned> RegisterReqs;
256 
257   bool NextSymbolIsThumb;
258 
259   bool useImplicitITThumb() const {
260     return ImplicitItMode == ImplicitItModeTy::Always ||
261            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
262   }
263 
264   bool useImplicitITARM() const {
265     return ImplicitItMode == ImplicitItModeTy::Always ||
266            ImplicitItMode == ImplicitItModeTy::ARMOnly;
267   }
268 
269   struct {
270     ARMCC::CondCodes Cond;    // Condition for IT block.
271     unsigned Mask:4;          // Condition mask for instructions.
272                               // Starting at first 1 (from lsb).
273                               //   '1'  condition as indicated in IT.
274                               //   '0'  inverse of condition (else).
275                               // Count of instructions in IT block is
276                               // 4 - trailingzeroes(mask)
277                               // Note that this does not have the same encoding
278                               // as in the IT instruction, which also depends
279                               // on the low bit of the condition code.
280 
281     unsigned CurPosition;     // Current position in parsing of IT
282                               // block. In range [0,4], with 0 being the IT
283                               // instruction itself. Initialized according to
284                               // count of instructions in block.  ~0U if no
285                               // active IT block.
286 
287     bool IsExplicit;          // true  - The IT instruction was present in the
288                               //         input, we should not modify it.
289                               // false - The IT instruction was added
290                               //         implicitly, we can extend it if that
291                               //         would be legal.
292   } ITState;
293 
294   SmallVector<MCInst, 4> PendingConditionalInsts;
295 
296   void flushPendingInstructions(MCStreamer &Out) override {
297     if (!inImplicitITBlock()) {
298       assert(PendingConditionalInsts.size() == 0);
299       return;
300     }
301 
302     // Emit the IT instruction
303     MCInst ITInst;
304     ITInst.setOpcode(ARM::t2IT);
305     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
306     ITInst.addOperand(MCOperand::createImm(ITState.Mask));
307     Out.emitInstruction(ITInst, getSTI());
308 
309     // Emit the conditonal instructions
310     assert(PendingConditionalInsts.size() <= 4);
311     for (const MCInst &Inst : PendingConditionalInsts) {
312       Out.emitInstruction(Inst, getSTI());
313     }
314     PendingConditionalInsts.clear();
315 
316     // Clear the IT state
317     ITState.Mask = 0;
318     ITState.CurPosition = ~0U;
319   }
320 
321   bool inITBlock() { return ITState.CurPosition != ~0U; }
322   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
323   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
324 
325   bool lastInITBlock() {
326     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
327   }
328 
329   void forwardITPosition() {
330     if (!inITBlock()) return;
331     // Move to the next instruction in the IT block, if there is one. If not,
332     // mark the block as done, except for implicit IT blocks, which we leave
333     // open until we find an instruction that can't be added to it.
334     unsigned TZ = countTrailingZeros(ITState.Mask);
335     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
336       ITState.CurPosition = ~0U; // Done with the IT block after this.
337   }
338 
339   // Rewind the state of the current IT block, removing the last slot from it.
340   void rewindImplicitITPosition() {
341     assert(inImplicitITBlock());
342     assert(ITState.CurPosition > 1);
343     ITState.CurPosition--;
344     unsigned TZ = countTrailingZeros(ITState.Mask);
345     unsigned NewMask = 0;
346     NewMask |= ITState.Mask & (0xC << TZ);
347     NewMask |= 0x2 << TZ;
348     ITState.Mask = NewMask;
349   }
350 
351   // Rewind the state of the current IT block, removing the last slot from it.
352   // If we were at the first slot, this closes the IT block.
353   void discardImplicitITBlock() {
354     assert(inImplicitITBlock());
355     assert(ITState.CurPosition == 1);
356     ITState.CurPosition = ~0U;
357   }
358 
359   // Return the low-subreg of a given Q register.
360   unsigned getDRegFromQReg(unsigned QReg) const {
361     return MRI->getSubReg(QReg, ARM::dsub_0);
362   }
363 
364   // Get the condition code corresponding to the current IT block slot.
365   ARMCC::CondCodes currentITCond() {
366     unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
367     return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
368   }
369 
370   // Invert the condition of the current IT block slot without changing any
371   // other slots in the same block.
372   void invertCurrentITCondition() {
373     if (ITState.CurPosition == 1) {
374       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
375     } else {
376       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
377     }
378   }
379 
380   // Returns true if the current IT block is full (all 4 slots used).
381   bool isITBlockFull() {
382     return inITBlock() && (ITState.Mask & 1);
383   }
384 
385   // Extend the current implicit IT block to have one more slot with the given
386   // condition code.
387   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
388     assert(inImplicitITBlock());
389     assert(!isITBlockFull());
390     assert(Cond == ITState.Cond ||
391            Cond == ARMCC::getOppositeCondition(ITState.Cond));
392     unsigned TZ = countTrailingZeros(ITState.Mask);
393     unsigned NewMask = 0;
394     // Keep any existing condition bits.
395     NewMask |= ITState.Mask & (0xE << TZ);
396     // Insert the new condition bit.
397     NewMask |= (Cond != ITState.Cond) << TZ;
398     // Move the trailing 1 down one bit.
399     NewMask |= 1 << (TZ - 1);
400     ITState.Mask = NewMask;
401   }
402 
403   // Create a new implicit IT block with a dummy condition code.
404   void startImplicitITBlock() {
405     assert(!inITBlock());
406     ITState.Cond = ARMCC::AL;
407     ITState.Mask = 8;
408     ITState.CurPosition = 1;
409     ITState.IsExplicit = false;
410   }
411 
412   // Create a new explicit IT block with the given condition and mask.
413   // The mask should be in the format used in ARMOperand and
414   // MCOperand, with a 1 implying 'e', regardless of the low bit of
415   // the condition.
416   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
417     assert(!inITBlock());
418     ITState.Cond = Cond;
419     ITState.Mask = Mask;
420     ITState.CurPosition = 0;
421     ITState.IsExplicit = true;
422   }
423 
424   struct {
425     unsigned Mask : 4;
426     unsigned CurPosition;
427   } VPTState;
428   bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
429   void forwardVPTPosition() {
430     if (!inVPTBlock()) return;
431     unsigned TZ = countTrailingZeros(VPTState.Mask);
432     if (++VPTState.CurPosition == 5 - TZ)
433       VPTState.CurPosition = ~0U;
434   }
435 
436   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
437     return getParser().Note(L, Msg, Range);
438   }
439 
440   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
441     return getParser().Warning(L, Msg, Range);
442   }
443 
444   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
445     return getParser().Error(L, Msg, Range);
446   }
447 
448   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
449                            unsigned ListNo, bool IsARPop = false);
450   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
451                            unsigned ListNo);
452 
453   int tryParseRegister();
454   bool tryParseRegisterWithWriteBack(OperandVector &);
455   int tryParseShiftRegister(OperandVector &);
456   bool parseRegisterList(OperandVector &, bool EnforceOrder = true);
457   bool parseMemory(OperandVector &);
458   bool parseOperand(OperandVector &, StringRef Mnemonic);
459   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
460   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
461                               unsigned &ShiftAmount);
462   bool parseLiteralValues(unsigned Size, SMLoc L);
463   bool parseDirectiveThumb(SMLoc L);
464   bool parseDirectiveARM(SMLoc L);
465   bool parseDirectiveThumbFunc(SMLoc L);
466   bool parseDirectiveCode(SMLoc L);
467   bool parseDirectiveSyntax(SMLoc L);
468   bool parseDirectiveReq(StringRef Name, SMLoc L);
469   bool parseDirectiveUnreq(SMLoc L);
470   bool parseDirectiveArch(SMLoc L);
471   bool parseDirectiveEabiAttr(SMLoc L);
472   bool parseDirectiveCPU(SMLoc L);
473   bool parseDirectiveFPU(SMLoc L);
474   bool parseDirectiveFnStart(SMLoc L);
475   bool parseDirectiveFnEnd(SMLoc L);
476   bool parseDirectiveCantUnwind(SMLoc L);
477   bool parseDirectivePersonality(SMLoc L);
478   bool parseDirectiveHandlerData(SMLoc L);
479   bool parseDirectiveSetFP(SMLoc L);
480   bool parseDirectivePad(SMLoc L);
481   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
482   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
483   bool parseDirectiveLtorg(SMLoc L);
484   bool parseDirectiveEven(SMLoc L);
485   bool parseDirectivePersonalityIndex(SMLoc L);
486   bool parseDirectiveUnwindRaw(SMLoc L);
487   bool parseDirectiveTLSDescSeq(SMLoc L);
488   bool parseDirectiveMovSP(SMLoc L);
489   bool parseDirectiveObjectArch(SMLoc L);
490   bool parseDirectiveArchExtension(SMLoc L);
491   bool parseDirectiveAlign(SMLoc L);
492   bool parseDirectiveThumbSet(SMLoc L);
493 
494   bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
495   StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
496                           unsigned &PredicationCode,
497                           unsigned &VPTPredicationCode, bool &CarrySetting,
498                           unsigned &ProcessorIMod, StringRef &ITMask);
499   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
500                              StringRef FullInst, bool &CanAcceptCarrySet,
501                              bool &CanAcceptPredicationCode,
502                              bool &CanAcceptVPTPredicationCode);
503 
504   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
505                                      OperandVector &Operands);
506   bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
507 
508   bool isThumb() const {
509     // FIXME: Can tablegen auto-generate this?
510     return getSTI().getFeatureBits()[ARM::ModeThumb];
511   }
512 
513   bool isThumbOne() const {
514     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
515   }
516 
517   bool isThumbTwo() const {
518     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
519   }
520 
521   bool hasThumb() const {
522     return getSTI().getFeatureBits()[ARM::HasV4TOps];
523   }
524 
525   bool hasThumb2() const {
526     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
527   }
528 
529   bool hasV6Ops() const {
530     return getSTI().getFeatureBits()[ARM::HasV6Ops];
531   }
532 
533   bool hasV6T2Ops() const {
534     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
535   }
536 
537   bool hasV6MOps() const {
538     return getSTI().getFeatureBits()[ARM::HasV6MOps];
539   }
540 
541   bool hasV7Ops() const {
542     return getSTI().getFeatureBits()[ARM::HasV7Ops];
543   }
544 
545   bool hasV8Ops() const {
546     return getSTI().getFeatureBits()[ARM::HasV8Ops];
547   }
548 
549   bool hasV8MBaseline() const {
550     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
551   }
552 
553   bool hasV8MMainline() const {
554     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
555   }
556   bool hasV8_1MMainline() const {
557     return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
558   }
559   bool hasMVE() const {
560     return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
561   }
562   bool hasMVEFloat() const {
563     return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
564   }
565   bool hasCDE() const {
566     return getSTI().getFeatureBits()[ARM::HasCDEOps];
567   }
568   bool has8MSecExt() const {
569     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
570   }
571 
572   bool hasARM() const {
573     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
574   }
575 
576   bool hasDSP() const {
577     return getSTI().getFeatureBits()[ARM::FeatureDSP];
578   }
579 
580   bool hasD32() const {
581     return getSTI().getFeatureBits()[ARM::FeatureD32];
582   }
583 
584   bool hasV8_1aOps() const {
585     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
586   }
587 
588   bool hasRAS() const {
589     return getSTI().getFeatureBits()[ARM::FeatureRAS];
590   }
591 
592   void SwitchMode() {
593     MCSubtargetInfo &STI = copySTI();
594     auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
595     setAvailableFeatures(FB);
596   }
597 
598   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
599 
600   bool isMClass() const {
601     return getSTI().getFeatureBits()[ARM::FeatureMClass];
602   }
603 
604   /// @name Auto-generated Match Functions
605   /// {
606 
607 #define GET_ASSEMBLER_HEADER
608 #include "ARMGenAsmMatcher.inc"
609 
610   /// }
611 
612   OperandMatchResultTy parseITCondCode(OperandVector &);
613   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
614   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
615   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
616   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
617   OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
618   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
619   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
620   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
621   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
622   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
623                                    int High);
624   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
625     return parsePKHImm(O, "lsl", 0, 31);
626   }
627   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
628     return parsePKHImm(O, "asr", 1, 32);
629   }
630   OperandMatchResultTy parseSetEndImm(OperandVector &);
631   OperandMatchResultTy parseShifterImm(OperandVector &);
632   OperandMatchResultTy parseRotImm(OperandVector &);
633   OperandMatchResultTy parseModImm(OperandVector &);
634   OperandMatchResultTy parseBitfield(OperandVector &);
635   OperandMatchResultTy parsePostIdxReg(OperandVector &);
636   OperandMatchResultTy parseAM3Offset(OperandVector &);
637   OperandMatchResultTy parseFPImm(OperandVector &);
638   OperandMatchResultTy parseVectorList(OperandVector &);
639   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
640                                        SMLoc &EndLoc);
641 
642   // Asm Match Converter Methods
643   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
644   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
645   void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
646 
647   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
648   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
649   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
650   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
651   bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
652   bool isITBlockTerminator(MCInst &Inst) const;
653   void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
654   bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
655                         bool Load, bool ARMMode, bool Writeback);
656 
657 public:
658   enum ARMMatchResultTy {
659     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
660     Match_RequiresNotITBlock,
661     Match_RequiresV6,
662     Match_RequiresThumb2,
663     Match_RequiresV8,
664     Match_RequiresFlagSetting,
665 #define GET_OPERAND_DIAGNOSTIC_TYPES
666 #include "ARMGenAsmMatcher.inc"
667 
668   };
669 
670   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
671                const MCInstrInfo &MII, const MCTargetOptions &Options)
672     : MCTargetAsmParser(Options, STI, MII), UC(Parser), MS(STI) {
673     MCAsmParserExtension::Initialize(Parser);
674 
675     // Cache the MCRegisterInfo.
676     MRI = getContext().getRegisterInfo();
677 
678     // Initialize the set of available features.
679     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
680 
681     // Add build attributes based on the selected target.
682     if (AddBuildAttributes)
683       getTargetStreamer().emitTargetAttributes(STI);
684 
685     // Not in an ITBlock to start with.
686     ITState.CurPosition = ~0U;
687 
688     VPTState.CurPosition = ~0U;
689 
690     NextSymbolIsThumb = false;
691   }
692 
693   // Implementation of the MCTargetAsmParser interface:
694   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
695   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
696                                         SMLoc &EndLoc) override;
697   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
698                         SMLoc NameLoc, OperandVector &Operands) override;
699   bool ParseDirective(AsmToken DirectiveID) override;
700 
701   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
702                                       unsigned Kind) override;
703   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
704 
705   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
706                                OperandVector &Operands, MCStreamer &Out,
707                                uint64_t &ErrorInfo,
708                                bool MatchingInlineAsm) override;
709   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
710                             SmallVectorImpl<NearMissInfo> &NearMisses,
711                             bool MatchingInlineAsm, bool &EmitInITBlock,
712                             MCStreamer &Out);
713 
714   struct NearMissMessage {
715     SMLoc Loc;
716     SmallString<128> Message;
717   };
718 
719   const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
720 
721   void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
722                         SmallVectorImpl<NearMissMessage> &NearMissesOut,
723                         SMLoc IDLoc, OperandVector &Operands);
724   void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
725                         OperandVector &Operands);
726 
727   void doBeforeLabelEmit(MCSymbol *Symbol) override;
728 
729   void onLabelParsed(MCSymbol *Symbol) override;
730 };
731 
732 /// ARMOperand - Instances of this class represent a parsed ARM machine
733 /// operand.
734 class ARMOperand : public MCParsedAsmOperand {
735   enum KindTy {
736     k_CondCode,
737     k_VPTPred,
738     k_CCOut,
739     k_ITCondMask,
740     k_CoprocNum,
741     k_CoprocReg,
742     k_CoprocOption,
743     k_Immediate,
744     k_MemBarrierOpt,
745     k_InstSyncBarrierOpt,
746     k_TraceSyncBarrierOpt,
747     k_Memory,
748     k_PostIndexRegister,
749     k_MSRMask,
750     k_BankedReg,
751     k_ProcIFlags,
752     k_VectorIndex,
753     k_Register,
754     k_RegisterList,
755     k_RegisterListWithAPSR,
756     k_DPRRegisterList,
757     k_SPRRegisterList,
758     k_FPSRegisterListWithVPR,
759     k_FPDRegisterListWithVPR,
760     k_VectorList,
761     k_VectorListAllLanes,
762     k_VectorListIndexed,
763     k_ShiftedRegister,
764     k_ShiftedImmediate,
765     k_ShifterImmediate,
766     k_RotateImmediate,
767     k_ModifiedImmediate,
768     k_ConstantPoolImmediate,
769     k_BitfieldDescriptor,
770     k_Token,
771   } Kind;
772 
773   SMLoc StartLoc, EndLoc, AlignmentLoc;
774   SmallVector<unsigned, 8> Registers;
775 
776   struct CCOp {
777     ARMCC::CondCodes Val;
778   };
779 
780   struct VCCOp {
781     ARMVCC::VPTCodes Val;
782   };
783 
784   struct CopOp {
785     unsigned Val;
786   };
787 
788   struct CoprocOptionOp {
789     unsigned Val;
790   };
791 
792   struct ITMaskOp {
793     unsigned Mask:4;
794   };
795 
796   struct MBOptOp {
797     ARM_MB::MemBOpt Val;
798   };
799 
800   struct ISBOptOp {
801     ARM_ISB::InstSyncBOpt Val;
802   };
803 
804   struct TSBOptOp {
805     ARM_TSB::TraceSyncBOpt Val;
806   };
807 
808   struct IFlagsOp {
809     ARM_PROC::IFlags Val;
810   };
811 
812   struct MMaskOp {
813     unsigned Val;
814   };
815 
816   struct BankedRegOp {
817     unsigned Val;
818   };
819 
820   struct TokOp {
821     const char *Data;
822     unsigned Length;
823   };
824 
825   struct RegOp {
826     unsigned RegNum;
827   };
828 
829   // A vector register list is a sequential list of 1 to 4 registers.
830   struct VectorListOp {
831     unsigned RegNum;
832     unsigned Count;
833     unsigned LaneIndex;
834     bool isDoubleSpaced;
835   };
836 
837   struct VectorIndexOp {
838     unsigned Val;
839   };
840 
841   struct ImmOp {
842     const MCExpr *Val;
843   };
844 
845   /// Combined record for all forms of ARM address expressions.
846   struct MemoryOp {
847     unsigned BaseRegNum;
848     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
849     // was specified.
850     const MCConstantExpr *OffsetImm;  // Offset immediate value
851     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
852     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
853     unsigned ShiftImm;        // shift for OffsetReg.
854     unsigned Alignment;       // 0 = no alignment specified
855     // n = alignment in bytes (2, 4, 8, 16, or 32)
856     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
857   };
858 
859   struct PostIdxRegOp {
860     unsigned RegNum;
861     bool isAdd;
862     ARM_AM::ShiftOpc ShiftTy;
863     unsigned ShiftImm;
864   };
865 
866   struct ShifterImmOp {
867     bool isASR;
868     unsigned Imm;
869   };
870 
871   struct RegShiftedRegOp {
872     ARM_AM::ShiftOpc ShiftTy;
873     unsigned SrcReg;
874     unsigned ShiftReg;
875     unsigned ShiftImm;
876   };
877 
878   struct RegShiftedImmOp {
879     ARM_AM::ShiftOpc ShiftTy;
880     unsigned SrcReg;
881     unsigned ShiftImm;
882   };
883 
884   struct RotImmOp {
885     unsigned Imm;
886   };
887 
888   struct ModImmOp {
889     unsigned Bits;
890     unsigned Rot;
891   };
892 
893   struct BitfieldOp {
894     unsigned LSB;
895     unsigned Width;
896   };
897 
898   union {
899     struct CCOp CC;
900     struct VCCOp VCC;
901     struct CopOp Cop;
902     struct CoprocOptionOp CoprocOption;
903     struct MBOptOp MBOpt;
904     struct ISBOptOp ISBOpt;
905     struct TSBOptOp TSBOpt;
906     struct ITMaskOp ITMask;
907     struct IFlagsOp IFlags;
908     struct MMaskOp MMask;
909     struct BankedRegOp BankedReg;
910     struct TokOp Tok;
911     struct RegOp Reg;
912     struct VectorListOp VectorList;
913     struct VectorIndexOp VectorIndex;
914     struct ImmOp Imm;
915     struct MemoryOp Memory;
916     struct PostIdxRegOp PostIdxReg;
917     struct ShifterImmOp ShifterImm;
918     struct RegShiftedRegOp RegShiftedReg;
919     struct RegShiftedImmOp RegShiftedImm;
920     struct RotImmOp RotImm;
921     struct ModImmOp ModImm;
922     struct BitfieldOp Bitfield;
923   };
924 
925 public:
926   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
927 
928   /// getStartLoc - Get the location of the first token of this operand.
929   SMLoc getStartLoc() const override { return StartLoc; }
930 
931   /// getEndLoc - Get the location of the last token of this operand.
932   SMLoc getEndLoc() const override { return EndLoc; }
933 
934   /// getLocRange - Get the range between the first and last token of this
935   /// operand.
936   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
937 
938   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
939   SMLoc getAlignmentLoc() const {
940     assert(Kind == k_Memory && "Invalid access!");
941     return AlignmentLoc;
942   }
943 
944   ARMCC::CondCodes getCondCode() const {
945     assert(Kind == k_CondCode && "Invalid access!");
946     return CC.Val;
947   }
948 
949   ARMVCC::VPTCodes getVPTPred() const {
950     assert(isVPTPred() && "Invalid access!");
951     return VCC.Val;
952   }
953 
954   unsigned getCoproc() const {
955     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
956     return Cop.Val;
957   }
958 
959   StringRef getToken() const {
960     assert(Kind == k_Token && "Invalid access!");
961     return StringRef(Tok.Data, Tok.Length);
962   }
963 
964   unsigned getReg() const override {
965     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
966     return Reg.RegNum;
967   }
968 
969   const SmallVectorImpl<unsigned> &getRegList() const {
970     assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
971             Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
972             Kind == k_FPSRegisterListWithVPR ||
973             Kind == k_FPDRegisterListWithVPR) &&
974            "Invalid access!");
975     return Registers;
976   }
977 
978   const MCExpr *getImm() const {
979     assert(isImm() && "Invalid access!");
980     return Imm.Val;
981   }
982 
983   const MCExpr *getConstantPoolImm() const {
984     assert(isConstantPoolImm() && "Invalid access!");
985     return Imm.Val;
986   }
987 
988   unsigned getVectorIndex() const {
989     assert(Kind == k_VectorIndex && "Invalid access!");
990     return VectorIndex.Val;
991   }
992 
993   ARM_MB::MemBOpt getMemBarrierOpt() const {
994     assert(Kind == k_MemBarrierOpt && "Invalid access!");
995     return MBOpt.Val;
996   }
997 
998   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
999     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
1000     return ISBOpt.Val;
1001   }
1002 
1003   ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
1004     assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
1005     return TSBOpt.Val;
1006   }
1007 
1008   ARM_PROC::IFlags getProcIFlags() const {
1009     assert(Kind == k_ProcIFlags && "Invalid access!");
1010     return IFlags.Val;
1011   }
1012 
1013   unsigned getMSRMask() const {
1014     assert(Kind == k_MSRMask && "Invalid access!");
1015     return MMask.Val;
1016   }
1017 
1018   unsigned getBankedReg() const {
1019     assert(Kind == k_BankedReg && "Invalid access!");
1020     return BankedReg.Val;
1021   }
1022 
1023   bool isCoprocNum() const { return Kind == k_CoprocNum; }
1024   bool isCoprocReg() const { return Kind == k_CoprocReg; }
1025   bool isCoprocOption() const { return Kind == k_CoprocOption; }
1026   bool isCondCode() const { return Kind == k_CondCode; }
1027   bool isVPTPred() const { return Kind == k_VPTPred; }
1028   bool isCCOut() const { return Kind == k_CCOut; }
1029   bool isITMask() const { return Kind == k_ITCondMask; }
1030   bool isITCondCode() const { return Kind == k_CondCode; }
1031   bool isImm() const override {
1032     return Kind == k_Immediate;
1033   }
1034 
1035   bool isARMBranchTarget() const {
1036     if (!isImm()) return false;
1037 
1038     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1039       return CE->getValue() % 4 == 0;
1040     return true;
1041   }
1042 
1043 
1044   bool isThumbBranchTarget() const {
1045     if (!isImm()) return false;
1046 
1047     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
1048       return CE->getValue() % 2 == 0;
1049     return true;
1050   }
1051 
1052   // checks whether this operand is an unsigned offset which fits is a field
1053   // of specified width and scaled by a specific number of bits
1054   template<unsigned width, unsigned scale>
1055   bool isUnsignedOffset() const {
1056     if (!isImm()) return false;
1057     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1058     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1059       int64_t Val = CE->getValue();
1060       int64_t Align = 1LL << scale;
1061       int64_t Max = Align * ((1LL << width) - 1);
1062       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
1063     }
1064     return false;
1065   }
1066 
1067   // checks whether this operand is an signed offset which fits is a field
1068   // of specified width and scaled by a specific number of bits
1069   template<unsigned width, unsigned scale>
1070   bool isSignedOffset() const {
1071     if (!isImm()) return false;
1072     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1073     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1074       int64_t Val = CE->getValue();
1075       int64_t Align = 1LL << scale;
1076       int64_t Max = Align * ((1LL << (width-1)) - 1);
1077       int64_t Min = -Align * (1LL << (width-1));
1078       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1079     }
1080     return false;
1081   }
1082 
1083   // checks whether this operand is an offset suitable for the LE /
1084   // LETP instructions in Arm v8.1M
1085   bool isLEOffset() const {
1086     if (!isImm()) return false;
1087     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1088     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1089       int64_t Val = CE->getValue();
1090       return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1091     }
1092     return false;
1093   }
1094 
1095   // checks whether this operand is a memory operand computed as an offset
1096   // applied to PC. the offset may have 8 bits of magnitude and is represented
1097   // with two bits of shift. textually it may be either [pc, #imm], #imm or
1098   // relocable expression...
1099   bool isThumbMemPC() const {
1100     int64_t Val = 0;
1101     if (isImm()) {
1102       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1103       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1104       if (!CE) return false;
1105       Val = CE->getValue();
1106     }
1107     else if (isGPRMem()) {
1108       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1109       if(Memory.BaseRegNum != ARM::PC) return false;
1110       Val = Memory.OffsetImm->getValue();
1111     }
1112     else return false;
1113     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1114   }
1115 
1116   bool isFPImm() const {
1117     if (!isImm()) return false;
1118     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1119     if (!CE) return false;
1120     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1121     return Val != -1;
1122   }
1123 
1124   template<int64_t N, int64_t M>
1125   bool isImmediate() const {
1126     if (!isImm()) return false;
1127     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1128     if (!CE) return false;
1129     int64_t Value = CE->getValue();
1130     return Value >= N && Value <= M;
1131   }
1132 
1133   template<int64_t N, int64_t M>
1134   bool isImmediateS4() const {
1135     if (!isImm()) return false;
1136     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137     if (!CE) return false;
1138     int64_t Value = CE->getValue();
1139     return ((Value & 3) == 0) && Value >= N && Value <= M;
1140   }
1141   template<int64_t N, int64_t M>
1142   bool isImmediateS2() const {
1143     if (!isImm()) return false;
1144     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1145     if (!CE) return false;
1146     int64_t Value = CE->getValue();
1147     return ((Value & 1) == 0) && Value >= N && Value <= M;
1148   }
1149   bool isFBits16() const {
1150     return isImmediate<0, 17>();
1151   }
1152   bool isFBits32() const {
1153     return isImmediate<1, 33>();
1154   }
1155   bool isImm8s4() const {
1156     return isImmediateS4<-1020, 1020>();
1157   }
1158   bool isImm7s4() const {
1159     return isImmediateS4<-508, 508>();
1160   }
1161   bool isImm7Shift0() const {
1162     return isImmediate<-127, 127>();
1163   }
1164   bool isImm7Shift1() const {
1165     return isImmediateS2<-255, 255>();
1166   }
1167   bool isImm7Shift2() const {
1168     return isImmediateS4<-511, 511>();
1169   }
1170   bool isImm7() const {
1171     return isImmediate<-127, 127>();
1172   }
1173   bool isImm0_1020s4() const {
1174     return isImmediateS4<0, 1020>();
1175   }
1176   bool isImm0_508s4() const {
1177     return isImmediateS4<0, 508>();
1178   }
1179   bool isImm0_508s4Neg() const {
1180     if (!isImm()) return false;
1181     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1182     if (!CE) return false;
1183     int64_t Value = -CE->getValue();
1184     // explicitly exclude zero. we want that to use the normal 0_508 version.
1185     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1186   }
1187 
1188   bool isImm0_4095Neg() const {
1189     if (!isImm()) return false;
1190     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191     if (!CE) return false;
1192     // isImm0_4095Neg is used with 32-bit immediates only.
1193     // 32-bit immediates are zero extended to 64-bit when parsed,
1194     // thus simple -CE->getValue() results in a big negative number,
1195     // not a small positive number as intended
1196     if ((CE->getValue() >> 32) > 0) return false;
1197     uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1198     return Value > 0 && Value < 4096;
1199   }
1200 
1201   bool isImm0_7() const {
1202     return isImmediate<0, 7>();
1203   }
1204 
1205   bool isImm1_16() const {
1206     return isImmediate<1, 16>();
1207   }
1208 
1209   bool isImm1_32() const {
1210     return isImmediate<1, 32>();
1211   }
1212 
1213   bool isImm8_255() const {
1214     return isImmediate<8, 255>();
1215   }
1216 
1217   bool isImm256_65535Expr() const {
1218     if (!isImm()) return false;
1219     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1220     // If it's not a constant expression, it'll generate a fixup and be
1221     // handled later.
1222     if (!CE) return true;
1223     int64_t Value = CE->getValue();
1224     return Value >= 256 && Value < 65536;
1225   }
1226 
1227   bool isImm0_65535Expr() const {
1228     if (!isImm()) return false;
1229     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1230     // If it's not a constant expression, it'll generate a fixup and be
1231     // handled later.
1232     if (!CE) return true;
1233     int64_t Value = CE->getValue();
1234     return Value >= 0 && Value < 65536;
1235   }
1236 
1237   bool isImm24bit() const {
1238     return isImmediate<0, 0xffffff + 1>();
1239   }
1240 
1241   bool isImmThumbSR() const {
1242     return isImmediate<1, 33>();
1243   }
1244 
1245   template<int shift>
1246   bool isExpImmValue(uint64_t Value) const {
1247     uint64_t mask = (1 << shift) - 1;
1248     if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1249       return false;
1250     return true;
1251   }
1252 
1253   template<int shift>
1254   bool isExpImm() const {
1255     if (!isImm()) return false;
1256     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1257     if (!CE) return false;
1258 
1259     return isExpImmValue<shift>(CE->getValue());
1260   }
1261 
1262   template<int shift, int size>
1263   bool isInvertedExpImm() const {
1264     if (!isImm()) return false;
1265     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1266     if (!CE) return false;
1267 
1268     uint64_t OriginalValue = CE->getValue();
1269     uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1270     return isExpImmValue<shift>(InvertedValue);
1271   }
1272 
1273   bool isPKHLSLImm() const {
1274     return isImmediate<0, 32>();
1275   }
1276 
1277   bool isPKHASRImm() const {
1278     return isImmediate<0, 33>();
1279   }
1280 
1281   bool isAdrLabel() const {
1282     // If we have an immediate that's not a constant, treat it as a label
1283     // reference needing a fixup.
1284     if (isImm() && !isa<MCConstantExpr>(getImm()))
1285       return true;
1286 
1287     // If it is a constant, it must fit into a modified immediate encoding.
1288     if (!isImm()) return false;
1289     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1290     if (!CE) return false;
1291     int64_t Value = CE->getValue();
1292     return (ARM_AM::getSOImmVal(Value) != -1 ||
1293             ARM_AM::getSOImmVal(-Value) != -1);
1294   }
1295 
1296   bool isT2SOImm() const {
1297     // If we have an immediate that's not a constant, treat it as an expression
1298     // needing a fixup.
1299     if (isImm() && !isa<MCConstantExpr>(getImm())) {
1300       // We want to avoid matching :upper16: and :lower16: as we want these
1301       // expressions to match in isImm0_65535Expr()
1302       const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1303       return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1304                              ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1305     }
1306     if (!isImm()) return false;
1307     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1308     if (!CE) return false;
1309     int64_t Value = CE->getValue();
1310     return ARM_AM::getT2SOImmVal(Value) != -1;
1311   }
1312 
1313   bool isT2SOImmNot() const {
1314     if (!isImm()) return false;
1315     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1316     if (!CE) return false;
1317     int64_t Value = CE->getValue();
1318     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1319       ARM_AM::getT2SOImmVal(~Value) != -1;
1320   }
1321 
1322   bool isT2SOImmNeg() const {
1323     if (!isImm()) return false;
1324     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1325     if (!CE) return false;
1326     int64_t Value = CE->getValue();
1327     // Only use this when not representable as a plain so_imm.
1328     return ARM_AM::getT2SOImmVal(Value) == -1 &&
1329       ARM_AM::getT2SOImmVal(-Value) != -1;
1330   }
1331 
1332   bool isSetEndImm() const {
1333     if (!isImm()) return false;
1334     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1335     if (!CE) return false;
1336     int64_t Value = CE->getValue();
1337     return Value == 1 || Value == 0;
1338   }
1339 
1340   bool isReg() const override { return Kind == k_Register; }
1341   bool isRegList() const { return Kind == k_RegisterList; }
1342   bool isRegListWithAPSR() const {
1343     return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1344   }
1345   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1346   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1347   bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1348   bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1349   bool isToken() const override { return Kind == k_Token; }
1350   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1351   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1352   bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1353   bool isMem() const override {
1354       return isGPRMem() || isMVEMem();
1355   }
1356   bool isMVEMem() const {
1357     if (Kind != k_Memory)
1358       return false;
1359     if (Memory.BaseRegNum &&
1360         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1361         !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1362       return false;
1363     if (Memory.OffsetRegNum &&
1364         !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1365             Memory.OffsetRegNum))
1366       return false;
1367     return true;
1368   }
1369   bool isGPRMem() const {
1370     if (Kind != k_Memory)
1371       return false;
1372     if (Memory.BaseRegNum &&
1373         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1374       return false;
1375     if (Memory.OffsetRegNum &&
1376         !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1377       return false;
1378     return true;
1379   }
1380   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1381   bool isRegShiftedReg() const {
1382     return Kind == k_ShiftedRegister &&
1383            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1384                RegShiftedReg.SrcReg) &&
1385            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1386                RegShiftedReg.ShiftReg);
1387   }
1388   bool isRegShiftedImm() const {
1389     return Kind == k_ShiftedImmediate &&
1390            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1391                RegShiftedImm.SrcReg);
1392   }
1393   bool isRotImm() const { return Kind == k_RotateImmediate; }
1394 
1395   template<unsigned Min, unsigned Max>
1396   bool isPowerTwoInRange() const {
1397     if (!isImm()) return false;
1398     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1399     if (!CE) return false;
1400     int64_t Value = CE->getValue();
1401     return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1402            Value >= Min && Value <= Max;
1403   }
1404   bool isModImm() const { return Kind == k_ModifiedImmediate; }
1405 
1406   bool isModImmNot() const {
1407     if (!isImm()) return false;
1408     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1409     if (!CE) return false;
1410     int64_t Value = CE->getValue();
1411     return ARM_AM::getSOImmVal(~Value) != -1;
1412   }
1413 
1414   bool isModImmNeg() const {
1415     if (!isImm()) return false;
1416     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1417     if (!CE) return false;
1418     int64_t Value = CE->getValue();
1419     return ARM_AM::getSOImmVal(Value) == -1 &&
1420       ARM_AM::getSOImmVal(-Value) != -1;
1421   }
1422 
1423   bool isThumbModImmNeg1_7() const {
1424     if (!isImm()) return false;
1425     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1426     if (!CE) return false;
1427     int32_t Value = -(int32_t)CE->getValue();
1428     return 0 < Value && Value < 8;
1429   }
1430 
1431   bool isThumbModImmNeg8_255() const {
1432     if (!isImm()) return false;
1433     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1434     if (!CE) return false;
1435     int32_t Value = -(int32_t)CE->getValue();
1436     return 7 < Value && Value < 256;
1437   }
1438 
1439   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1440   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1441   bool isPostIdxRegShifted() const {
1442     return Kind == k_PostIndexRegister &&
1443            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1444   }
1445   bool isPostIdxReg() const {
1446     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1447   }
1448   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1449     if (!isGPRMem())
1450       return false;
1451     // No offset of any kind.
1452     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1453      (alignOK || Memory.Alignment == Alignment);
1454   }
1455   bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1456     if (!isGPRMem())
1457       return false;
1458 
1459     if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1460             Memory.BaseRegNum))
1461       return false;
1462 
1463     // No offset of any kind.
1464     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1465      (alignOK || Memory.Alignment == Alignment);
1466   }
1467   bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1468     if (!isGPRMem())
1469       return false;
1470 
1471     if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1472             Memory.BaseRegNum))
1473       return false;
1474 
1475     // No offset of any kind.
1476     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1477      (alignOK || Memory.Alignment == Alignment);
1478   }
1479   bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1480     if (!isGPRMem())
1481       return false;
1482 
1483     if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1484             Memory.BaseRegNum))
1485       return false;
1486 
1487     // No offset of any kind.
1488     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1489      (alignOK || Memory.Alignment == Alignment);
1490   }
1491   bool isMemPCRelImm12() const {
1492     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1493       return false;
1494     // Base register must be PC.
1495     if (Memory.BaseRegNum != ARM::PC)
1496       return false;
1497     // Immediate offset in range [-4095, 4095].
1498     if (!Memory.OffsetImm) return true;
1499     int64_t Val = Memory.OffsetImm->getValue();
1500     return (Val > -4096 && Val < 4096) ||
1501            (Val == std::numeric_limits<int32_t>::min());
1502   }
1503 
1504   bool isAlignedMemory() const {
1505     return isMemNoOffset(true);
1506   }
1507 
1508   bool isAlignedMemoryNone() const {
1509     return isMemNoOffset(false, 0);
1510   }
1511 
1512   bool isDupAlignedMemoryNone() const {
1513     return isMemNoOffset(false, 0);
1514   }
1515 
1516   bool isAlignedMemory16() const {
1517     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1518       return true;
1519     return isMemNoOffset(false, 0);
1520   }
1521 
1522   bool isDupAlignedMemory16() const {
1523     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1524       return true;
1525     return isMemNoOffset(false, 0);
1526   }
1527 
1528   bool isAlignedMemory32() const {
1529     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1530       return true;
1531     return isMemNoOffset(false, 0);
1532   }
1533 
1534   bool isDupAlignedMemory32() const {
1535     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1536       return true;
1537     return isMemNoOffset(false, 0);
1538   }
1539 
1540   bool isAlignedMemory64() const {
1541     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1542       return true;
1543     return isMemNoOffset(false, 0);
1544   }
1545 
1546   bool isDupAlignedMemory64() const {
1547     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1548       return true;
1549     return isMemNoOffset(false, 0);
1550   }
1551 
1552   bool isAlignedMemory64or128() const {
1553     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1554       return true;
1555     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1556       return true;
1557     return isMemNoOffset(false, 0);
1558   }
1559 
1560   bool isDupAlignedMemory64or128() const {
1561     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1562       return true;
1563     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1564       return true;
1565     return isMemNoOffset(false, 0);
1566   }
1567 
1568   bool isAlignedMemory64or128or256() const {
1569     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1570       return true;
1571     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1572       return true;
1573     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1574       return true;
1575     return isMemNoOffset(false, 0);
1576   }
1577 
1578   bool isAddrMode2() const {
1579     if (!isGPRMem() || Memory.Alignment != 0) return false;
1580     // Check for register offset.
1581     if (Memory.OffsetRegNum) return true;
1582     // Immediate offset in range [-4095, 4095].
1583     if (!Memory.OffsetImm) return true;
1584     int64_t Val = Memory.OffsetImm->getValue();
1585     return Val > -4096 && Val < 4096;
1586   }
1587 
1588   bool isAM2OffsetImm() const {
1589     if (!isImm()) return false;
1590     // Immediate offset in range [-4095, 4095].
1591     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1592     if (!CE) return false;
1593     int64_t Val = CE->getValue();
1594     return (Val == std::numeric_limits<int32_t>::min()) ||
1595            (Val > -4096 && Val < 4096);
1596   }
1597 
1598   bool isAddrMode3() const {
1599     // If we have an immediate that's not a constant, treat it as a label
1600     // reference needing a fixup. If it is a constant, it's something else
1601     // and we reject it.
1602     if (isImm() && !isa<MCConstantExpr>(getImm()))
1603       return true;
1604     if (!isGPRMem() || Memory.Alignment != 0) return false;
1605     // No shifts are legal for AM3.
1606     if (Memory.ShiftType != ARM_AM::no_shift) return false;
1607     // Check for register offset.
1608     if (Memory.OffsetRegNum) return true;
1609     // Immediate offset in range [-255, 255].
1610     if (!Memory.OffsetImm) return true;
1611     int64_t Val = Memory.OffsetImm->getValue();
1612     // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1613     // have to check for this too.
1614     return (Val > -256 && Val < 256) ||
1615            Val == std::numeric_limits<int32_t>::min();
1616   }
1617 
1618   bool isAM3Offset() const {
1619     if (isPostIdxReg())
1620       return true;
1621     if (!isImm())
1622       return false;
1623     // Immediate offset in range [-255, 255].
1624     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625     if (!CE) return false;
1626     int64_t Val = CE->getValue();
1627     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1628     return (Val > -256 && Val < 256) ||
1629            Val == std::numeric_limits<int32_t>::min();
1630   }
1631 
1632   bool isAddrMode5() const {
1633     // If we have an immediate that's not a constant, treat it as a label
1634     // reference needing a fixup. If it is a constant, it's something else
1635     // and we reject it.
1636     if (isImm() && !isa<MCConstantExpr>(getImm()))
1637       return true;
1638     if (!isGPRMem() || Memory.Alignment != 0) return false;
1639     // Check for register offset.
1640     if (Memory.OffsetRegNum) return false;
1641     // Immediate offset in range [-1020, 1020] and a multiple of 4.
1642     if (!Memory.OffsetImm) return true;
1643     int64_t Val = Memory.OffsetImm->getValue();
1644     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1645       Val == std::numeric_limits<int32_t>::min();
1646   }
1647 
1648   bool isAddrMode5FP16() const {
1649     // If we have an immediate that's not a constant, treat it as a label
1650     // reference needing a fixup. If it is a constant, it's something else
1651     // and we reject it.
1652     if (isImm() && !isa<MCConstantExpr>(getImm()))
1653       return true;
1654     if (!isGPRMem() || Memory.Alignment != 0) return false;
1655     // Check for register offset.
1656     if (Memory.OffsetRegNum) return false;
1657     // Immediate offset in range [-510, 510] and a multiple of 2.
1658     if (!Memory.OffsetImm) return true;
1659     int64_t Val = Memory.OffsetImm->getValue();
1660     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1661            Val == std::numeric_limits<int32_t>::min();
1662   }
1663 
1664   bool isMemTBB() const {
1665     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1666         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1667       return false;
1668     return true;
1669   }
1670 
1671   bool isMemTBH() const {
1672     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1673         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1674         Memory.Alignment != 0 )
1675       return false;
1676     return true;
1677   }
1678 
1679   bool isMemRegOffset() const {
1680     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1681       return false;
1682     return true;
1683   }
1684 
1685   bool isT2MemRegOffset() const {
1686     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1687         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1688       return false;
1689     // Only lsl #{0, 1, 2, 3} allowed.
1690     if (Memory.ShiftType == ARM_AM::no_shift)
1691       return true;
1692     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1693       return false;
1694     return true;
1695   }
1696 
1697   bool isMemThumbRR() const {
1698     // Thumb reg+reg addressing is simple. Just two registers, a base and
1699     // an offset. No shifts, negations or any other complicating factors.
1700     if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1701         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1702       return false;
1703     return isARMLowRegister(Memory.BaseRegNum) &&
1704       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1705   }
1706 
1707   bool isMemThumbRIs4() const {
1708     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1709         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1710       return false;
1711     // Immediate offset, multiple of 4 in range [0, 124].
1712     if (!Memory.OffsetImm) return true;
1713     int64_t Val = Memory.OffsetImm->getValue();
1714     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1715   }
1716 
1717   bool isMemThumbRIs2() const {
1718     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1719         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1720       return false;
1721     // Immediate offset, multiple of 4 in range [0, 62].
1722     if (!Memory.OffsetImm) return true;
1723     int64_t Val = Memory.OffsetImm->getValue();
1724     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1725   }
1726 
1727   bool isMemThumbRIs1() const {
1728     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1729         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1730       return false;
1731     // Immediate offset in range [0, 31].
1732     if (!Memory.OffsetImm) return true;
1733     int64_t Val = Memory.OffsetImm->getValue();
1734     return Val >= 0 && Val <= 31;
1735   }
1736 
1737   bool isMemThumbSPI() const {
1738     if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1739         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1740       return false;
1741     // Immediate offset, multiple of 4 in range [0, 1020].
1742     if (!Memory.OffsetImm) return true;
1743     int64_t Val = Memory.OffsetImm->getValue();
1744     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1745   }
1746 
1747   bool isMemImm8s4Offset() const {
1748     // If we have an immediate that's not a constant, treat it as a label
1749     // reference needing a fixup. If it is a constant, it's something else
1750     // and we reject it.
1751     if (isImm() && !isa<MCConstantExpr>(getImm()))
1752       return true;
1753     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1754       return false;
1755     // Immediate offset a multiple of 4 in range [-1020, 1020].
1756     if (!Memory.OffsetImm) return true;
1757     int64_t Val = Memory.OffsetImm->getValue();
1758     // Special case, #-0 is std::numeric_limits<int32_t>::min().
1759     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1760            Val == std::numeric_limits<int32_t>::min();
1761   }
1762   bool isMemImm7s4Offset() const {
1763     // If we have an immediate that's not a constant, treat it as a label
1764     // reference needing a fixup. If it is a constant, it's something else
1765     // and we reject it.
1766     if (isImm() && !isa<MCConstantExpr>(getImm()))
1767       return true;
1768     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1769         !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1770             Memory.BaseRegNum))
1771       return false;
1772     // Immediate offset a multiple of 4 in range [-508, 508].
1773     if (!Memory.OffsetImm) return true;
1774     int64_t Val = Memory.OffsetImm->getValue();
1775     // Special case, #-0 is INT32_MIN.
1776     return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1777   }
1778   bool isMemImm0_1020s4Offset() const {
1779     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1780       return false;
1781     // Immediate offset a multiple of 4 in range [0, 1020].
1782     if (!Memory.OffsetImm) return true;
1783     int64_t Val = Memory.OffsetImm->getValue();
1784     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1785   }
1786 
1787   bool isMemImm8Offset() const {
1788     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1789       return false;
1790     // Base reg of PC isn't allowed for these encodings.
1791     if (Memory.BaseRegNum == ARM::PC) return false;
1792     // Immediate offset in range [-255, 255].
1793     if (!Memory.OffsetImm) return true;
1794     int64_t Val = Memory.OffsetImm->getValue();
1795     return (Val == std::numeric_limits<int32_t>::min()) ||
1796            (Val > -256 && Val < 256);
1797   }
1798 
1799   template<unsigned Bits, unsigned RegClassID>
1800   bool isMemImm7ShiftedOffset() const {
1801     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1802         !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1803       return false;
1804 
1805     // Expect an immediate offset equal to an element of the range
1806     // [-127, 127], shifted left by Bits.
1807 
1808     if (!Memory.OffsetImm) return true;
1809     int64_t Val = Memory.OffsetImm->getValue();
1810 
1811     // INT32_MIN is a special-case value (indicating the encoding with
1812     // zero offset and the subtract bit set)
1813     if (Val == INT32_MIN)
1814       return true;
1815 
1816     unsigned Divisor = 1U << Bits;
1817 
1818     // Check that the low bits are zero
1819     if (Val % Divisor != 0)
1820       return false;
1821 
1822     // Check that the remaining offset is within range.
1823     Val /= Divisor;
1824     return (Val >= -127 && Val <= 127);
1825   }
1826 
1827   template <int shift> bool isMemRegRQOffset() const {
1828     if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
1829       return false;
1830 
1831     if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1832             Memory.BaseRegNum))
1833       return false;
1834     if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1835             Memory.OffsetRegNum))
1836       return false;
1837 
1838     if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1839       return false;
1840 
1841     if (shift > 0 &&
1842         (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1843       return false;
1844 
1845     return true;
1846   }
1847 
1848   template <int shift> bool isMemRegQOffset() const {
1849     if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1850       return false;
1851 
1852     if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1853             Memory.BaseRegNum))
1854       return false;
1855 
1856     if(!Memory.OffsetImm) return true;
1857     static_assert(shift < 56,
1858                   "Such that we dont shift by a value higher than 62");
1859     int64_t Val = Memory.OffsetImm->getValue();
1860 
1861     // The value must be a multiple of (1 << shift)
1862     if ((Val & ((1U << shift) - 1)) != 0)
1863       return false;
1864 
1865     // And be in the right range, depending on the amount that it is shifted
1866     // by.  Shift 0, is equal to 7 unsigned bits, the sign bit is set
1867     // separately.
1868     int64_t Range = (1U << (7+shift)) - 1;
1869     return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1870   }
1871 
1872   bool isMemPosImm8Offset() const {
1873     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1874       return false;
1875     // Immediate offset in range [0, 255].
1876     if (!Memory.OffsetImm) return true;
1877     int64_t Val = Memory.OffsetImm->getValue();
1878     return Val >= 0 && Val < 256;
1879   }
1880 
1881   bool isMemNegImm8Offset() const {
1882     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1883       return false;
1884     // Base reg of PC isn't allowed for these encodings.
1885     if (Memory.BaseRegNum == ARM::PC) return false;
1886     // Immediate offset in range [-255, -1].
1887     if (!Memory.OffsetImm) return false;
1888     int64_t Val = Memory.OffsetImm->getValue();
1889     return (Val == std::numeric_limits<int32_t>::min()) ||
1890            (Val > -256 && Val < 0);
1891   }
1892 
1893   bool isMemUImm12Offset() const {
1894     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1895       return false;
1896     // Immediate offset in range [0, 4095].
1897     if (!Memory.OffsetImm) return true;
1898     int64_t Val = Memory.OffsetImm->getValue();
1899     return (Val >= 0 && Val < 4096);
1900   }
1901 
1902   bool isMemImm12Offset() const {
1903     // If we have an immediate that's not a constant, treat it as a label
1904     // reference needing a fixup. If it is a constant, it's something else
1905     // and we reject it.
1906 
1907     if (isImm() && !isa<MCConstantExpr>(getImm()))
1908       return true;
1909 
1910     if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1911       return false;
1912     // Immediate offset in range [-4095, 4095].
1913     if (!Memory.OffsetImm) return true;
1914     int64_t Val = Memory.OffsetImm->getValue();
1915     return (Val > -4096 && Val < 4096) ||
1916            (Val == std::numeric_limits<int32_t>::min());
1917   }
1918 
1919   bool isConstPoolAsmImm() const {
1920     // Delay processing of Constant Pool Immediate, this will turn into
1921     // a constant. Match no other operand
1922     return (isConstantPoolImm());
1923   }
1924 
1925   bool isPostIdxImm8() const {
1926     if (!isImm()) return false;
1927     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928     if (!CE) return false;
1929     int64_t Val = CE->getValue();
1930     return (Val > -256 && Val < 256) ||
1931            (Val == std::numeric_limits<int32_t>::min());
1932   }
1933 
1934   bool isPostIdxImm8s4() const {
1935     if (!isImm()) return false;
1936     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1937     if (!CE) return false;
1938     int64_t Val = CE->getValue();
1939     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1940            (Val == std::numeric_limits<int32_t>::min());
1941   }
1942 
1943   bool isMSRMask() const { return Kind == k_MSRMask; }
1944   bool isBankedReg() const { return Kind == k_BankedReg; }
1945   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1946 
1947   // NEON operands.
1948   bool isSingleSpacedVectorList() const {
1949     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1950   }
1951 
1952   bool isDoubleSpacedVectorList() const {
1953     return Kind == k_VectorList && VectorList.isDoubleSpaced;
1954   }
1955 
1956   bool isVecListOneD() const {
1957     if (!isSingleSpacedVectorList()) return false;
1958     return VectorList.Count == 1;
1959   }
1960 
1961   bool isVecListTwoMQ() const {
1962     return isSingleSpacedVectorList() && VectorList.Count == 2 &&
1963            ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1964                VectorList.RegNum);
1965   }
1966 
1967   bool isVecListDPair() const {
1968     if (!isSingleSpacedVectorList()) return false;
1969     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1970               .contains(VectorList.RegNum));
1971   }
1972 
1973   bool isVecListThreeD() const {
1974     if (!isSingleSpacedVectorList()) return false;
1975     return VectorList.Count == 3;
1976   }
1977 
1978   bool isVecListFourD() const {
1979     if (!isSingleSpacedVectorList()) return false;
1980     return VectorList.Count == 4;
1981   }
1982 
1983   bool isVecListDPairSpaced() const {
1984     if (Kind != k_VectorList) return false;
1985     if (isSingleSpacedVectorList()) return false;
1986     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1987               .contains(VectorList.RegNum));
1988   }
1989 
1990   bool isVecListThreeQ() const {
1991     if (!isDoubleSpacedVectorList()) return false;
1992     return VectorList.Count == 3;
1993   }
1994 
1995   bool isVecListFourQ() const {
1996     if (!isDoubleSpacedVectorList()) return false;
1997     return VectorList.Count == 4;
1998   }
1999 
2000   bool isVecListFourMQ() const {
2001     return isSingleSpacedVectorList() && VectorList.Count == 4 &&
2002            ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
2003                VectorList.RegNum);
2004   }
2005 
2006   bool isSingleSpacedVectorAllLanes() const {
2007     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
2008   }
2009 
2010   bool isDoubleSpacedVectorAllLanes() const {
2011     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
2012   }
2013 
2014   bool isVecListOneDAllLanes() const {
2015     if (!isSingleSpacedVectorAllLanes()) return false;
2016     return VectorList.Count == 1;
2017   }
2018 
2019   bool isVecListDPairAllLanes() const {
2020     if (!isSingleSpacedVectorAllLanes()) return false;
2021     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
2022               .contains(VectorList.RegNum));
2023   }
2024 
2025   bool isVecListDPairSpacedAllLanes() const {
2026     if (!isDoubleSpacedVectorAllLanes()) return false;
2027     return VectorList.Count == 2;
2028   }
2029 
2030   bool isVecListThreeDAllLanes() const {
2031     if (!isSingleSpacedVectorAllLanes()) return false;
2032     return VectorList.Count == 3;
2033   }
2034 
2035   bool isVecListThreeQAllLanes() const {
2036     if (!isDoubleSpacedVectorAllLanes()) return false;
2037     return VectorList.Count == 3;
2038   }
2039 
2040   bool isVecListFourDAllLanes() const {
2041     if (!isSingleSpacedVectorAllLanes()) return false;
2042     return VectorList.Count == 4;
2043   }
2044 
2045   bool isVecListFourQAllLanes() const {
2046     if (!isDoubleSpacedVectorAllLanes()) return false;
2047     return VectorList.Count == 4;
2048   }
2049 
2050   bool isSingleSpacedVectorIndexed() const {
2051     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
2052   }
2053 
2054   bool isDoubleSpacedVectorIndexed() const {
2055     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
2056   }
2057 
2058   bool isVecListOneDByteIndexed() const {
2059     if (!isSingleSpacedVectorIndexed()) return false;
2060     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
2061   }
2062 
2063   bool isVecListOneDHWordIndexed() const {
2064     if (!isSingleSpacedVectorIndexed()) return false;
2065     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2066   }
2067 
2068   bool isVecListOneDWordIndexed() const {
2069     if (!isSingleSpacedVectorIndexed()) return false;
2070     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2071   }
2072 
2073   bool isVecListTwoDByteIndexed() const {
2074     if (!isSingleSpacedVectorIndexed()) return false;
2075     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2076   }
2077 
2078   bool isVecListTwoDHWordIndexed() const {
2079     if (!isSingleSpacedVectorIndexed()) return false;
2080     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2081   }
2082 
2083   bool isVecListTwoQWordIndexed() const {
2084     if (!isDoubleSpacedVectorIndexed()) return false;
2085     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2086   }
2087 
2088   bool isVecListTwoQHWordIndexed() const {
2089     if (!isDoubleSpacedVectorIndexed()) return false;
2090     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2091   }
2092 
2093   bool isVecListTwoDWordIndexed() const {
2094     if (!isSingleSpacedVectorIndexed()) return false;
2095     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2096   }
2097 
2098   bool isVecListThreeDByteIndexed() const {
2099     if (!isSingleSpacedVectorIndexed()) return false;
2100     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2101   }
2102 
2103   bool isVecListThreeDHWordIndexed() const {
2104     if (!isSingleSpacedVectorIndexed()) return false;
2105     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2106   }
2107 
2108   bool isVecListThreeQWordIndexed() const {
2109     if (!isDoubleSpacedVectorIndexed()) return false;
2110     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2111   }
2112 
2113   bool isVecListThreeQHWordIndexed() const {
2114     if (!isDoubleSpacedVectorIndexed()) return false;
2115     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2116   }
2117 
2118   bool isVecListThreeDWordIndexed() const {
2119     if (!isSingleSpacedVectorIndexed()) return false;
2120     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2121   }
2122 
2123   bool isVecListFourDByteIndexed() const {
2124     if (!isSingleSpacedVectorIndexed()) return false;
2125     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2126   }
2127 
2128   bool isVecListFourDHWordIndexed() const {
2129     if (!isSingleSpacedVectorIndexed()) return false;
2130     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2131   }
2132 
2133   bool isVecListFourQWordIndexed() const {
2134     if (!isDoubleSpacedVectorIndexed()) return false;
2135     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2136   }
2137 
2138   bool isVecListFourQHWordIndexed() const {
2139     if (!isDoubleSpacedVectorIndexed()) return false;
2140     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2141   }
2142 
2143   bool isVecListFourDWordIndexed() const {
2144     if (!isSingleSpacedVectorIndexed()) return false;
2145     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2146   }
2147 
2148   bool isVectorIndex() const { return Kind == k_VectorIndex; }
2149 
2150   template <unsigned NumLanes>
2151   bool isVectorIndexInRange() const {
2152     if (Kind != k_VectorIndex) return false;
2153     return VectorIndex.Val < NumLanes;
2154   }
2155 
2156   bool isVectorIndex8()  const { return isVectorIndexInRange<8>(); }
2157   bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2158   bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2159   bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2160 
2161   template<int PermittedValue, int OtherPermittedValue>
2162   bool isMVEPairVectorIndex() const {
2163     if (Kind != k_VectorIndex) return false;
2164     return VectorIndex.Val == PermittedValue ||
2165            VectorIndex.Val == OtherPermittedValue;
2166   }
2167 
2168   bool isNEONi8splat() const {
2169     if (!isImm()) return false;
2170     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2171     // Must be a constant.
2172     if (!CE) return false;
2173     int64_t Value = CE->getValue();
2174     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2175     // value.
2176     return Value >= 0 && Value < 256;
2177   }
2178 
2179   bool isNEONi16splat() const {
2180     if (isNEONByteReplicate(2))
2181       return false; // Leave that for bytes replication and forbid by default.
2182     if (!isImm())
2183       return false;
2184     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2185     // Must be a constant.
2186     if (!CE) return false;
2187     unsigned Value = CE->getValue();
2188     return ARM_AM::isNEONi16splat(Value);
2189   }
2190 
2191   bool isNEONi16splatNot() const {
2192     if (!isImm())
2193       return false;
2194     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2195     // Must be a constant.
2196     if (!CE) return false;
2197     unsigned Value = CE->getValue();
2198     return ARM_AM::isNEONi16splat(~Value & 0xffff);
2199   }
2200 
2201   bool isNEONi32splat() const {
2202     if (isNEONByteReplicate(4))
2203       return false; // Leave that for bytes replication and forbid by default.
2204     if (!isImm())
2205       return false;
2206     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2207     // Must be a constant.
2208     if (!CE) return false;
2209     unsigned Value = CE->getValue();
2210     return ARM_AM::isNEONi32splat(Value);
2211   }
2212 
2213   bool isNEONi32splatNot() const {
2214     if (!isImm())
2215       return false;
2216     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2217     // Must be a constant.
2218     if (!CE) return false;
2219     unsigned Value = CE->getValue();
2220     return ARM_AM::isNEONi32splat(~Value);
2221   }
2222 
2223   static bool isValidNEONi32vmovImm(int64_t Value) {
2224     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2225     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2226     return ((Value & 0xffffffffffffff00) == 0) ||
2227            ((Value & 0xffffffffffff00ff) == 0) ||
2228            ((Value & 0xffffffffff00ffff) == 0) ||
2229            ((Value & 0xffffffff00ffffff) == 0) ||
2230            ((Value & 0xffffffffffff00ff) == 0xff) ||
2231            ((Value & 0xffffffffff00ffff) == 0xffff);
2232   }
2233 
2234   bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2235     assert((Width == 8 || Width == 16 || Width == 32) &&
2236            "Invalid element width");
2237     assert(NumElems * Width <= 64 && "Invalid result width");
2238 
2239     if (!isImm())
2240       return false;
2241     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2242     // Must be a constant.
2243     if (!CE)
2244       return false;
2245     int64_t Value = CE->getValue();
2246     if (!Value)
2247       return false; // Don't bother with zero.
2248     if (Inv)
2249       Value = ~Value;
2250 
2251     uint64_t Mask = (1ull << Width) - 1;
2252     uint64_t Elem = Value & Mask;
2253     if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2254       return false;
2255     if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2256       return false;
2257 
2258     for (unsigned i = 1; i < NumElems; ++i) {
2259       Value >>= Width;
2260       if ((Value & Mask) != Elem)
2261         return false;
2262     }
2263     return true;
2264   }
2265 
2266   bool isNEONByteReplicate(unsigned NumBytes) const {
2267     return isNEONReplicate(8, NumBytes, false);
2268   }
2269 
2270   static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2271     assert((FromW == 8 || FromW == 16 || FromW == 32) &&
2272            "Invalid source width");
2273     assert((ToW == 16 || ToW == 32 || ToW == 64) &&
2274            "Invalid destination width");
2275     assert(FromW < ToW && "ToW is not less than FromW");
2276   }
2277 
2278   template<unsigned FromW, unsigned ToW>
2279   bool isNEONmovReplicate() const {
2280     checkNeonReplicateArgs(FromW, ToW);
2281     if (ToW == 64 && isNEONi64splat())
2282       return false;
2283     return isNEONReplicate(FromW, ToW / FromW, false);
2284   }
2285 
2286   template<unsigned FromW, unsigned ToW>
2287   bool isNEONinvReplicate() const {
2288     checkNeonReplicateArgs(FromW, ToW);
2289     return isNEONReplicate(FromW, ToW / FromW, true);
2290   }
2291 
2292   bool isNEONi32vmov() const {
2293     if (isNEONByteReplicate(4))
2294       return false; // Let it to be classified as byte-replicate case.
2295     if (!isImm())
2296       return false;
2297     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2298     // Must be a constant.
2299     if (!CE)
2300       return false;
2301     return isValidNEONi32vmovImm(CE->getValue());
2302   }
2303 
2304   bool isNEONi32vmovNeg() const {
2305     if (!isImm()) return false;
2306     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2307     // Must be a constant.
2308     if (!CE) return false;
2309     return isValidNEONi32vmovImm(~CE->getValue());
2310   }
2311 
2312   bool isNEONi64splat() const {
2313     if (!isImm()) return false;
2314     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2315     // Must be a constant.
2316     if (!CE) return false;
2317     uint64_t Value = CE->getValue();
2318     // i64 value with each byte being either 0 or 0xff.
2319     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2320       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2321     return true;
2322   }
2323 
2324   template<int64_t Angle, int64_t Remainder>
2325   bool isComplexRotation() const {
2326     if (!isImm()) return false;
2327 
2328     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2329     if (!CE) return false;
2330     uint64_t Value = CE->getValue();
2331 
2332     return (Value % Angle == Remainder && Value <= 270);
2333   }
2334 
2335   bool isMVELongShift() const {
2336     if (!isImm()) return false;
2337     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2338     // Must be a constant.
2339     if (!CE) return false;
2340     uint64_t Value = CE->getValue();
2341     return Value >= 1 && Value <= 32;
2342   }
2343 
2344   bool isMveSaturateOp() const {
2345     if (!isImm()) return false;
2346     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2347     if (!CE) return false;
2348     uint64_t Value = CE->getValue();
2349     return Value == 48 || Value == 64;
2350   }
2351 
2352   bool isITCondCodeNoAL() const {
2353     if (!isITCondCode()) return false;
2354     ARMCC::CondCodes CC = getCondCode();
2355     return CC != ARMCC::AL;
2356   }
2357 
2358   bool isITCondCodeRestrictedI() const {
2359     if (!isITCondCode())
2360       return false;
2361     ARMCC::CondCodes CC = getCondCode();
2362     return CC == ARMCC::EQ || CC == ARMCC::NE;
2363   }
2364 
2365   bool isITCondCodeRestrictedS() const {
2366     if (!isITCondCode())
2367       return false;
2368     ARMCC::CondCodes CC = getCondCode();
2369     return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2370            CC == ARMCC::GE;
2371   }
2372 
2373   bool isITCondCodeRestrictedU() const {
2374     if (!isITCondCode())
2375       return false;
2376     ARMCC::CondCodes CC = getCondCode();
2377     return CC == ARMCC::HS || CC == ARMCC::HI;
2378   }
2379 
2380   bool isITCondCodeRestrictedFP() const {
2381     if (!isITCondCode())
2382       return false;
2383     ARMCC::CondCodes CC = getCondCode();
2384     return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2385            CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2386   }
2387 
2388   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2389     // Add as immediates when possible.  Null MCExpr = 0.
2390     if (!Expr)
2391       Inst.addOperand(MCOperand::createImm(0));
2392     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2393       Inst.addOperand(MCOperand::createImm(CE->getValue()));
2394     else
2395       Inst.addOperand(MCOperand::createExpr(Expr));
2396   }
2397 
2398   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2399     assert(N == 1 && "Invalid number of operands!");
2400     addExpr(Inst, getImm());
2401   }
2402 
2403   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2404     assert(N == 1 && "Invalid number of operands!");
2405     addExpr(Inst, getImm());
2406   }
2407 
2408   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2409     assert(N == 2 && "Invalid number of operands!");
2410     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2411     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2412     Inst.addOperand(MCOperand::createReg(RegNum));
2413   }
2414 
2415   void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2416     assert(N == 2 && "Invalid number of operands!");
2417     Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2418     unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2419     Inst.addOperand(MCOperand::createReg(RegNum));
2420   }
2421 
2422   void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2423     assert(N == 3 && "Invalid number of operands!");
2424     addVPTPredNOperands(Inst, N-1);
2425     unsigned RegNum;
2426     if (getVPTPred() == ARMVCC::None) {
2427       RegNum = 0;
2428     } else {
2429       unsigned NextOpIndex = Inst.getNumOperands();
2430       const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2431       int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2432       assert(TiedOp >= 0 &&
2433              "Inactive register in vpred_r is not tied to an output!");
2434       RegNum = Inst.getOperand(TiedOp).getReg();
2435     }
2436     Inst.addOperand(MCOperand::createReg(RegNum));
2437   }
2438 
2439   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2440     assert(N == 1 && "Invalid number of operands!");
2441     Inst.addOperand(MCOperand::createImm(getCoproc()));
2442   }
2443 
2444   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2445     assert(N == 1 && "Invalid number of operands!");
2446     Inst.addOperand(MCOperand::createImm(getCoproc()));
2447   }
2448 
2449   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2450     assert(N == 1 && "Invalid number of operands!");
2451     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2452   }
2453 
2454   void addITMaskOperands(MCInst &Inst, unsigned N) const {
2455     assert(N == 1 && "Invalid number of operands!");
2456     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2457   }
2458 
2459   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2460     assert(N == 1 && "Invalid number of operands!");
2461     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2462   }
2463 
2464   void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2465     assert(N == 1 && "Invalid number of operands!");
2466     Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
2467   }
2468 
2469   void addCCOutOperands(MCInst &Inst, unsigned N) const {
2470     assert(N == 1 && "Invalid number of operands!");
2471     Inst.addOperand(MCOperand::createReg(getReg()));
2472   }
2473 
2474   void addRegOperands(MCInst &Inst, unsigned N) const {
2475     assert(N == 1 && "Invalid number of operands!");
2476     Inst.addOperand(MCOperand::createReg(getReg()));
2477   }
2478 
2479   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2480     assert(N == 3 && "Invalid number of operands!");
2481     assert(isRegShiftedReg() &&
2482            "addRegShiftedRegOperands() on non-RegShiftedReg!");
2483     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2484     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2485     Inst.addOperand(MCOperand::createImm(
2486       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2487   }
2488 
2489   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2490     assert(N == 2 && "Invalid number of operands!");
2491     assert(isRegShiftedImm() &&
2492            "addRegShiftedImmOperands() on non-RegShiftedImm!");
2493     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2494     // Shift of #32 is encoded as 0 where permitted
2495     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2496     Inst.addOperand(MCOperand::createImm(
2497       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2498   }
2499 
2500   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2501     assert(N == 1 && "Invalid number of operands!");
2502     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2503                                          ShifterImm.Imm));
2504   }
2505 
2506   void addRegListOperands(MCInst &Inst, unsigned N) const {
2507     assert(N == 1 && "Invalid number of operands!");
2508     const SmallVectorImpl<unsigned> &RegList = getRegList();
2509     for (SmallVectorImpl<unsigned>::const_iterator
2510            I = RegList.begin(), E = RegList.end(); I != E; ++I)
2511       Inst.addOperand(MCOperand::createReg(*I));
2512   }
2513 
2514   void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2515     assert(N == 1 && "Invalid number of operands!");
2516     const SmallVectorImpl<unsigned> &RegList = getRegList();
2517     for (SmallVectorImpl<unsigned>::const_iterator
2518            I = RegList.begin(), E = RegList.end(); I != E; ++I)
2519       Inst.addOperand(MCOperand::createReg(*I));
2520   }
2521 
2522   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2523     addRegListOperands(Inst, N);
2524   }
2525 
2526   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2527     addRegListOperands(Inst, N);
2528   }
2529 
2530   void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2531     addRegListOperands(Inst, N);
2532   }
2533 
2534   void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2535     addRegListOperands(Inst, N);
2536   }
2537 
2538   void addRotImmOperands(MCInst &Inst, unsigned N) const {
2539     assert(N == 1 && "Invalid number of operands!");
2540     // Encoded as val>>3. The printer handles display as 8, 16, 24.
2541     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2542   }
2543 
2544   void addModImmOperands(MCInst &Inst, unsigned N) const {
2545     assert(N == 1 && "Invalid number of operands!");
2546 
2547     // Support for fixups (MCFixup)
2548     if (isImm())
2549       return addImmOperands(Inst, N);
2550 
2551     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2552   }
2553 
2554   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2555     assert(N == 1 && "Invalid number of operands!");
2556     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2557     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2558     Inst.addOperand(MCOperand::createImm(Enc));
2559   }
2560 
2561   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2562     assert(N == 1 && "Invalid number of operands!");
2563     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2564     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2565     Inst.addOperand(MCOperand::createImm(Enc));
2566   }
2567 
2568   void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2569     assert(N == 1 && "Invalid number of operands!");
2570     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2571     uint32_t Val = -CE->getValue();
2572     Inst.addOperand(MCOperand::createImm(Val));
2573   }
2574 
2575   void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2576     assert(N == 1 && "Invalid number of operands!");
2577     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2578     uint32_t Val = -CE->getValue();
2579     Inst.addOperand(MCOperand::createImm(Val));
2580   }
2581 
2582   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2583     assert(N == 1 && "Invalid number of operands!");
2584     // Munge the lsb/width into a bitfield mask.
2585     unsigned lsb = Bitfield.LSB;
2586     unsigned width = Bitfield.Width;
2587     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2588     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2589                       (32 - (lsb + width)));
2590     Inst.addOperand(MCOperand::createImm(Mask));
2591   }
2592 
2593   void addImmOperands(MCInst &Inst, unsigned N) const {
2594     assert(N == 1 && "Invalid number of operands!");
2595     addExpr(Inst, getImm());
2596   }
2597 
2598   void addFBits16Operands(MCInst &Inst, unsigned N) const {
2599     assert(N == 1 && "Invalid number of operands!");
2600     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2601     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2602   }
2603 
2604   void addFBits32Operands(MCInst &Inst, unsigned N) const {
2605     assert(N == 1 && "Invalid number of operands!");
2606     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2607     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2608   }
2609 
2610   void addFPImmOperands(MCInst &Inst, unsigned N) const {
2611     assert(N == 1 && "Invalid number of operands!");
2612     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2613     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2614     Inst.addOperand(MCOperand::createImm(Val));
2615   }
2616 
2617   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2618     assert(N == 1 && "Invalid number of operands!");
2619     // FIXME: We really want to scale the value here, but the LDRD/STRD
2620     // instruction don't encode operands that way yet.
2621     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2622     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2623   }
2624 
2625   void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2626     assert(N == 1 && "Invalid number of operands!");
2627     // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2628     // instruction don't encode operands that way yet.
2629     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2630     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2631   }
2632 
2633   void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2634     assert(N == 1 && "Invalid number of operands!");
2635     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2636     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2637   }
2638 
2639   void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2640     assert(N == 1 && "Invalid number of operands!");
2641     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2642     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2643   }
2644 
2645   void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2646     assert(N == 1 && "Invalid number of operands!");
2647     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2648     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2649   }
2650 
2651   void addImm7Operands(MCInst &Inst, unsigned N) const {
2652     assert(N == 1 && "Invalid number of operands!");
2653     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2654     Inst.addOperand(MCOperand::createImm(CE->getValue()));
2655   }
2656 
2657   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2658     assert(N == 1 && "Invalid number of operands!");
2659     // The immediate is scaled by four in the encoding and is stored
2660     // in the MCInst as such. Lop off the low two bits here.
2661     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2662     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2663   }
2664 
2665   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2666     assert(N == 1 && "Invalid number of operands!");
2667     // The immediate is scaled by four in the encoding and is stored
2668     // in the MCInst as such. Lop off the low two bits here.
2669     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2670     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2671   }
2672 
2673   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2674     assert(N == 1 && "Invalid number of operands!");
2675     // The immediate is scaled by four in the encoding and is stored
2676     // in the MCInst as such. Lop off the low two bits here.
2677     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2678     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2679   }
2680 
2681   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2682     assert(N == 1 && "Invalid number of operands!");
2683     // The constant encodes as the immediate-1, and we store in the instruction
2684     // the bits as encoded, so subtract off one here.
2685     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2686     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2687   }
2688 
2689   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2690     assert(N == 1 && "Invalid number of operands!");
2691     // The constant encodes as the immediate-1, and we store in the instruction
2692     // the bits as encoded, so subtract off one here.
2693     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2694     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2695   }
2696 
2697   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2698     assert(N == 1 && "Invalid number of operands!");
2699     // The constant encodes as the immediate, except for 32, which encodes as
2700     // zero.
2701     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2702     unsigned Imm = CE->getValue();
2703     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2704   }
2705 
2706   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2707     assert(N == 1 && "Invalid number of operands!");
2708     // An ASR value of 32 encodes as 0, so that's how we want to add it to
2709     // the instruction as well.
2710     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2711     int Val = CE->getValue();
2712     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2713   }
2714 
2715   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2716     assert(N == 1 && "Invalid number of operands!");
2717     // The operand is actually a t2_so_imm, but we have its bitwise
2718     // negation in the assembly source, so twiddle it here.
2719     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2720     Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2721   }
2722 
2723   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2724     assert(N == 1 && "Invalid number of operands!");
2725     // The operand is actually a t2_so_imm, but we have its
2726     // negation in the assembly source, so twiddle it here.
2727     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2728     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2729   }
2730 
2731   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2732     assert(N == 1 && "Invalid number of operands!");
2733     // The operand is actually an imm0_4095, but we have its
2734     // negation in the assembly source, so twiddle it here.
2735     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2736     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2737   }
2738 
2739   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2740     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2741       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2742       return;
2743     }
2744     const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2745     Inst.addOperand(MCOperand::createExpr(SR));
2746   }
2747 
2748   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2749     assert(N == 1 && "Invalid number of operands!");
2750     if (isImm()) {
2751       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2752       if (CE) {
2753         Inst.addOperand(MCOperand::createImm(CE->getValue()));
2754         return;
2755       }
2756       const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2757       Inst.addOperand(MCOperand::createExpr(SR));
2758       return;
2759     }
2760 
2761     assert(isGPRMem()  && "Unknown value type!");
2762     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2763     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2764   }
2765 
2766   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2767     assert(N == 1 && "Invalid number of operands!");
2768     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2769   }
2770 
2771   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2772     assert(N == 1 && "Invalid number of operands!");
2773     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2774   }
2775 
2776   void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2777     assert(N == 1 && "Invalid number of operands!");
2778     Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2779   }
2780 
2781   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2782     assert(N == 1 && "Invalid number of operands!");
2783     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2784   }
2785 
2786   void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2787     assert(N == 1 && "Invalid number of operands!");
2788     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2789   }
2790 
2791   void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2792     assert(N == 1 && "Invalid number of operands!");
2793     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2794   }
2795 
2796   void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2797     assert(N == 1 && "Invalid number of operands!");
2798     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2799   }
2800 
2801   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2802     assert(N == 1 && "Invalid number of operands!");
2803     int32_t Imm = Memory.OffsetImm->getValue();
2804     Inst.addOperand(MCOperand::createImm(Imm));
2805   }
2806 
2807   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2808     assert(N == 1 && "Invalid number of operands!");
2809     assert(isImm() && "Not an immediate!");
2810 
2811     // If we have an immediate that's not a constant, treat it as a label
2812     // reference needing a fixup.
2813     if (!isa<MCConstantExpr>(getImm())) {
2814       Inst.addOperand(MCOperand::createExpr(getImm()));
2815       return;
2816     }
2817 
2818     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2819     int Val = CE->getValue();
2820     Inst.addOperand(MCOperand::createImm(Val));
2821   }
2822 
2823   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2824     assert(N == 2 && "Invalid number of operands!");
2825     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2826     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2827   }
2828 
2829   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2830     addAlignedMemoryOperands(Inst, N);
2831   }
2832 
2833   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2834     addAlignedMemoryOperands(Inst, N);
2835   }
2836 
2837   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2838     addAlignedMemoryOperands(Inst, N);
2839   }
2840 
2841   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2842     addAlignedMemoryOperands(Inst, N);
2843   }
2844 
2845   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2846     addAlignedMemoryOperands(Inst, N);
2847   }
2848 
2849   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2850     addAlignedMemoryOperands(Inst, N);
2851   }
2852 
2853   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2854     addAlignedMemoryOperands(Inst, N);
2855   }
2856 
2857   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2858     addAlignedMemoryOperands(Inst, N);
2859   }
2860 
2861   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2862     addAlignedMemoryOperands(Inst, N);
2863   }
2864 
2865   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2866     addAlignedMemoryOperands(Inst, N);
2867   }
2868 
2869   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2870     addAlignedMemoryOperands(Inst, N);
2871   }
2872 
2873   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2874     assert(N == 3 && "Invalid number of operands!");
2875     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2876     if (!Memory.OffsetRegNum) {
2877       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2878       // Special case for #-0
2879       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2880       if (Val < 0) Val = -Val;
2881       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2882     } else {
2883       // For register offset, we encode the shift type and negation flag
2884       // here.
2885       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2886                               Memory.ShiftImm, Memory.ShiftType);
2887     }
2888     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2889     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2890     Inst.addOperand(MCOperand::createImm(Val));
2891   }
2892 
2893   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2894     assert(N == 2 && "Invalid number of operands!");
2895     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2896     assert(CE && "non-constant AM2OffsetImm operand!");
2897     int32_t Val = CE->getValue();
2898     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2899     // Special case for #-0
2900     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2901     if (Val < 0) Val = -Val;
2902     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2903     Inst.addOperand(MCOperand::createReg(0));
2904     Inst.addOperand(MCOperand::createImm(Val));
2905   }
2906 
2907   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2908     assert(N == 3 && "Invalid number of operands!");
2909     // If we have an immediate that's not a constant, treat it as a label
2910     // reference needing a fixup. If it is a constant, it's something else
2911     // and we reject it.
2912     if (isImm()) {
2913       Inst.addOperand(MCOperand::createExpr(getImm()));
2914       Inst.addOperand(MCOperand::createReg(0));
2915       Inst.addOperand(MCOperand::createImm(0));
2916       return;
2917     }
2918 
2919     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2920     if (!Memory.OffsetRegNum) {
2921       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2922       // Special case for #-0
2923       if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2924       if (Val < 0) Val = -Val;
2925       Val = ARM_AM::getAM3Opc(AddSub, Val);
2926     } else {
2927       // For register offset, we encode the shift type and negation flag
2928       // here.
2929       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2930     }
2931     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2932     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2933     Inst.addOperand(MCOperand::createImm(Val));
2934   }
2935 
2936   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2937     assert(N == 2 && "Invalid number of operands!");
2938     if (Kind == k_PostIndexRegister) {
2939       int32_t Val =
2940         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2941       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2942       Inst.addOperand(MCOperand::createImm(Val));
2943       return;
2944     }
2945 
2946     // Constant offset.
2947     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2948     int32_t Val = CE->getValue();
2949     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2950     // Special case for #-0
2951     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2952     if (Val < 0) Val = -Val;
2953     Val = ARM_AM::getAM3Opc(AddSub, Val);
2954     Inst.addOperand(MCOperand::createReg(0));
2955     Inst.addOperand(MCOperand::createImm(Val));
2956   }
2957 
2958   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2959     assert(N == 2 && "Invalid number of operands!");
2960     // If we have an immediate that's not a constant, treat it as a label
2961     // reference needing a fixup. If it is a constant, it's something else
2962     // and we reject it.
2963     if (isImm()) {
2964       Inst.addOperand(MCOperand::createExpr(getImm()));
2965       Inst.addOperand(MCOperand::createImm(0));
2966       return;
2967     }
2968 
2969     // The lower two bits are always zero and as such are not encoded.
2970     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2971     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2972     // Special case for #-0
2973     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2974     if (Val < 0) Val = -Val;
2975     Val = ARM_AM::getAM5Opc(AddSub, Val);
2976     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2977     Inst.addOperand(MCOperand::createImm(Val));
2978   }
2979 
2980   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2981     assert(N == 2 && "Invalid number of operands!");
2982     // If we have an immediate that's not a constant, treat it as a label
2983     // reference needing a fixup. If it is a constant, it's something else
2984     // and we reject it.
2985     if (isImm()) {
2986       Inst.addOperand(MCOperand::createExpr(getImm()));
2987       Inst.addOperand(MCOperand::createImm(0));
2988       return;
2989     }
2990 
2991     // The lower bit is always zero and as such is not encoded.
2992     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2993     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2994     // Special case for #-0
2995     if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2996     if (Val < 0) Val = -Val;
2997     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2998     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2999     Inst.addOperand(MCOperand::createImm(Val));
3000   }
3001 
3002   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
3003     assert(N == 2 && "Invalid number of operands!");
3004     // If we have an immediate that's not a constant, treat it as a label
3005     // reference needing a fixup. If it is a constant, it's something else
3006     // and we reject it.
3007     if (isImm()) {
3008       Inst.addOperand(MCOperand::createExpr(getImm()));
3009       Inst.addOperand(MCOperand::createImm(0));
3010       return;
3011     }
3012 
3013     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3014     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3015     Inst.addOperand(MCOperand::createImm(Val));
3016   }
3017 
3018   void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
3019     assert(N == 2 && "Invalid number of operands!");
3020     // If we have an immediate that's not a constant, treat it as a label
3021     // reference needing a fixup. If it is a constant, it's something else
3022     // and we reject it.
3023     if (isImm()) {
3024       Inst.addOperand(MCOperand::createExpr(getImm()));
3025       Inst.addOperand(MCOperand::createImm(0));
3026       return;
3027     }
3028 
3029     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3030     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3031     Inst.addOperand(MCOperand::createImm(Val));
3032   }
3033 
3034   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
3035     assert(N == 2 && "Invalid number of operands!");
3036     // The lower two bits are always zero and as such are not encoded.
3037     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
3038     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3039     Inst.addOperand(MCOperand::createImm(Val));
3040   }
3041 
3042   void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
3043     assert(N == 2 && "Invalid number of operands!");
3044     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3045     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3046     Inst.addOperand(MCOperand::createImm(Val));
3047   }
3048 
3049   void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
3050     assert(N == 2 && "Invalid number of operands!");
3051     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3052     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3053   }
3054 
3055   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3056     assert(N == 2 && "Invalid number of operands!");
3057     // If this is an immediate, it's a label reference.
3058     if (isImm()) {
3059       addExpr(Inst, getImm());
3060       Inst.addOperand(MCOperand::createImm(0));
3061       return;
3062     }
3063 
3064     // Otherwise, it's a normal memory reg+offset.
3065     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3066     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3067     Inst.addOperand(MCOperand::createImm(Val));
3068   }
3069 
3070   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3071     assert(N == 2 && "Invalid number of operands!");
3072     // If this is an immediate, it's a label reference.
3073     if (isImm()) {
3074       addExpr(Inst, getImm());
3075       Inst.addOperand(MCOperand::createImm(0));
3076       return;
3077     }
3078 
3079     // Otherwise, it's a normal memory reg+offset.
3080     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3081     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3082     Inst.addOperand(MCOperand::createImm(Val));
3083   }
3084 
3085   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3086     assert(N == 1 && "Invalid number of operands!");
3087     // This is container for the immediate that we will create the constant
3088     // pool from
3089     addExpr(Inst, getConstantPoolImm());
3090   }
3091 
3092   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3093     assert(N == 2 && "Invalid number of operands!");
3094     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3095     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3096   }
3097 
3098   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3099     assert(N == 2 && "Invalid number of operands!");
3100     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3101     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3102   }
3103 
3104   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3105     assert(N == 3 && "Invalid number of operands!");
3106     unsigned Val =
3107       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3108                         Memory.ShiftImm, Memory.ShiftType);
3109     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3110     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3111     Inst.addOperand(MCOperand::createImm(Val));
3112   }
3113 
3114   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3115     assert(N == 3 && "Invalid number of operands!");
3116     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3117     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3118     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3119   }
3120 
3121   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3122     assert(N == 2 && "Invalid number of operands!");
3123     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3124     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3125   }
3126 
3127   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3128     assert(N == 2 && "Invalid number of operands!");
3129     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3130     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3131     Inst.addOperand(MCOperand::createImm(Val));
3132   }
3133 
3134   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3135     assert(N == 2 && "Invalid number of operands!");
3136     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
3137     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3138     Inst.addOperand(MCOperand::createImm(Val));
3139   }
3140 
3141   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3142     assert(N == 2 && "Invalid number of operands!");
3143     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
3144     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3145     Inst.addOperand(MCOperand::createImm(Val));
3146   }
3147 
3148   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3149     assert(N == 2 && "Invalid number of operands!");
3150     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3151     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3152     Inst.addOperand(MCOperand::createImm(Val));
3153   }
3154 
3155   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3156     assert(N == 1 && "Invalid number of operands!");
3157     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3158     assert(CE && "non-constant post-idx-imm8 operand!");
3159     int Imm = CE->getValue();
3160     bool isAdd = Imm >= 0;
3161     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3162     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3163     Inst.addOperand(MCOperand::createImm(Imm));
3164   }
3165 
3166   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3167     assert(N == 1 && "Invalid number of operands!");
3168     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3169     assert(CE && "non-constant post-idx-imm8s4 operand!");
3170     int Imm = CE->getValue();
3171     bool isAdd = Imm >= 0;
3172     if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3173     // Immediate is scaled by 4.
3174     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3175     Inst.addOperand(MCOperand::createImm(Imm));
3176   }
3177 
3178   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3179     assert(N == 2 && "Invalid number of operands!");
3180     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3181     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3182   }
3183 
3184   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3185     assert(N == 2 && "Invalid number of operands!");
3186     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3187     // The sign, shift type, and shift amount are encoded in a single operand
3188     // using the AM2 encoding helpers.
3189     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3190     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3191                                      PostIdxReg.ShiftTy);
3192     Inst.addOperand(MCOperand::createImm(Imm));
3193   }
3194 
3195   void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3196     assert(N == 1 && "Invalid number of operands!");
3197     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3198     Inst.addOperand(MCOperand::createImm(CE->getValue()));
3199   }
3200 
3201   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3202     assert(N == 1 && "Invalid number of operands!");
3203     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3204   }
3205 
3206   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3207     assert(N == 1 && "Invalid number of operands!");
3208     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3209   }
3210 
3211   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3212     assert(N == 1 && "Invalid number of operands!");
3213     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3214   }
3215 
3216   void addVecListOperands(MCInst &Inst, unsigned N) const {
3217     assert(N == 1 && "Invalid number of operands!");
3218     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3219   }
3220 
3221   void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3222     assert(N == 1 && "Invalid number of operands!");
3223 
3224     // When we come here, the VectorList field will identify a range
3225     // of q-registers by its base register and length, and it will
3226     // have already been error-checked to be the expected length of
3227     // range and contain only q-regs in the range q0-q7. So we can
3228     // count on the base register being in the range q0-q6 (for 2
3229     // regs) or q0-q4 (for 4)
3230     //
3231     // The MVE instructions taking a register range of this kind will
3232     // need an operand in the QQPR or QQQQPR class, representing the
3233     // entire range as a unit. So we must translate into that class,
3234     // by finding the index of the base register in the MQPR reg
3235     // class, and returning the super-register at the corresponding
3236     // index in the target class.
3237 
3238     const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3239     const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
3240       &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
3241       &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
3242 
3243     unsigned I, E = RC_out->getNumRegs();
3244     for (I = 0; I < E; I++)
3245       if (RC_in->getRegister(I) == VectorList.RegNum)
3246         break;
3247     assert(I < E && "Invalid vector list start register!");
3248 
3249     Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3250   }
3251 
3252   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3253     assert(N == 2 && "Invalid number of operands!");
3254     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3255     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3256   }
3257 
3258   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3259     assert(N == 1 && "Invalid number of operands!");
3260     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3261   }
3262 
3263   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3264     assert(N == 1 && "Invalid number of operands!");
3265     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3266   }
3267 
3268   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3269     assert(N == 1 && "Invalid number of operands!");
3270     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3271   }
3272 
3273   void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3274     assert(N == 1 && "Invalid number of operands!");
3275     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3276   }
3277 
3278   void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3279     assert(N == 1 && "Invalid number of operands!");
3280     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3281   }
3282 
3283   void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3284     assert(N == 1 && "Invalid number of operands!");
3285     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3286   }
3287 
3288   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3289     assert(N == 1 && "Invalid number of operands!");
3290     // The immediate encodes the type of constant as well as the value.
3291     // Mask in that this is an i8 splat.
3292     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3293     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3294   }
3295 
3296   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3297     assert(N == 1 && "Invalid number of operands!");
3298     // The immediate encodes the type of constant as well as the value.
3299     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3300     unsigned Value = CE->getValue();
3301     Value = ARM_AM::encodeNEONi16splat(Value);
3302     Inst.addOperand(MCOperand::createImm(Value));
3303   }
3304 
3305   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3306     assert(N == 1 && "Invalid number of operands!");
3307     // The immediate encodes the type of constant as well as the value.
3308     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3309     unsigned Value = CE->getValue();
3310     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3311     Inst.addOperand(MCOperand::createImm(Value));
3312   }
3313 
3314   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3315     assert(N == 1 && "Invalid number of operands!");
3316     // The immediate encodes the type of constant as well as the value.
3317     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3318     unsigned Value = CE->getValue();
3319     Value = ARM_AM::encodeNEONi32splat(Value);
3320     Inst.addOperand(MCOperand::createImm(Value));
3321   }
3322 
3323   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3324     assert(N == 1 && "Invalid number of operands!");
3325     // The immediate encodes the type of constant as well as the value.
3326     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3327     unsigned Value = CE->getValue();
3328     Value = ARM_AM::encodeNEONi32splat(~Value);
3329     Inst.addOperand(MCOperand::createImm(Value));
3330   }
3331 
3332   void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3333     // The immediate encodes the type of constant as well as the value.
3334     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3335     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3336             Inst.getOpcode() == ARM::VMOVv16i8) &&
3337           "All instructions that wants to replicate non-zero byte "
3338           "always must be replaced with VMOVv8i8 or VMOVv16i8.");
3339     unsigned Value = CE->getValue();
3340     if (Inv)
3341       Value = ~Value;
3342     unsigned B = Value & 0xff;
3343     B |= 0xe00; // cmode = 0b1110
3344     Inst.addOperand(MCOperand::createImm(B));
3345   }
3346 
3347   void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3348     assert(N == 1 && "Invalid number of operands!");
3349     addNEONi8ReplicateOperands(Inst, true);
3350   }
3351 
3352   static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3353     if (Value >= 256 && Value <= 0xffff)
3354       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3355     else if (Value > 0xffff && Value <= 0xffffff)
3356       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3357     else if (Value > 0xffffff)
3358       Value = (Value >> 24) | 0x600;
3359     return Value;
3360   }
3361 
3362   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3363     assert(N == 1 && "Invalid number of operands!");
3364     // The immediate encodes the type of constant as well as the value.
3365     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3366     unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3367     Inst.addOperand(MCOperand::createImm(Value));
3368   }
3369 
3370   void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3371     assert(N == 1 && "Invalid number of operands!");
3372     addNEONi8ReplicateOperands(Inst, false);
3373   }
3374 
3375   void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3376     assert(N == 1 && "Invalid number of operands!");
3377     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3378     assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3379             Inst.getOpcode() == ARM::VMOVv8i16 ||
3380             Inst.getOpcode() == ARM::VMVNv4i16 ||
3381             Inst.getOpcode() == ARM::VMVNv8i16) &&
3382           "All instructions that want to replicate non-zero half-word "
3383           "always must be replaced with V{MOV,MVN}v{4,8}i16.");
3384     uint64_t Value = CE->getValue();
3385     unsigned Elem = Value & 0xffff;
3386     if (Elem >= 256)
3387       Elem = (Elem >> 8) | 0x200;
3388     Inst.addOperand(MCOperand::createImm(Elem));
3389   }
3390 
3391   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3392     assert(N == 1 && "Invalid number of operands!");
3393     // The immediate encodes the type of constant as well as the value.
3394     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3395     unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3396     Inst.addOperand(MCOperand::createImm(Value));
3397   }
3398 
3399   void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3400     assert(N == 1 && "Invalid number of operands!");
3401     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3402     assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3403             Inst.getOpcode() == ARM::VMOVv4i32 ||
3404             Inst.getOpcode() == ARM::VMVNv2i32 ||
3405             Inst.getOpcode() == ARM::VMVNv4i32) &&
3406           "All instructions that want to replicate non-zero word "
3407           "always must be replaced with V{MOV,MVN}v{2,4}i32.");
3408     uint64_t Value = CE->getValue();
3409     unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3410     Inst.addOperand(MCOperand::createImm(Elem));
3411   }
3412 
3413   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3414     assert(N == 1 && "Invalid number of operands!");
3415     // The immediate encodes the type of constant as well as the value.
3416     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3417     uint64_t Value = CE->getValue();
3418     unsigned Imm = 0;
3419     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3420       Imm |= (Value & 1) << i;
3421     }
3422     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3423   }
3424 
3425   void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3426     assert(N == 1 && "Invalid number of operands!");
3427     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3428     Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3429   }
3430 
3431   void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3432     assert(N == 1 && "Invalid number of operands!");
3433     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3434     Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3435   }
3436 
3437   void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3438     assert(N == 1 && "Invalid number of operands!");
3439     const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3440     unsigned Imm = CE->getValue();
3441     assert((Imm == 48 || Imm == 64) && "Invalid saturate operand");
3442     Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3443   }
3444 
3445   void print(raw_ostream &OS) const override;
3446 
3447   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3448     auto Op = std::make_unique<ARMOperand>(k_ITCondMask);
3449     Op->ITMask.Mask = Mask;
3450     Op->StartLoc = S;
3451     Op->EndLoc = S;
3452     return Op;
3453   }
3454 
3455   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3456                                                     SMLoc S) {
3457     auto Op = std::make_unique<ARMOperand>(k_CondCode);
3458     Op->CC.Val = CC;
3459     Op->StartLoc = S;
3460     Op->EndLoc = S;
3461     return Op;
3462   }
3463 
3464   static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3465                                                    SMLoc S) {
3466     auto Op = std::make_unique<ARMOperand>(k_VPTPred);
3467     Op->VCC.Val = CC;
3468     Op->StartLoc = S;
3469     Op->EndLoc = S;
3470     return Op;
3471   }
3472 
3473   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3474     auto Op = std::make_unique<ARMOperand>(k_CoprocNum);
3475     Op->Cop.Val = CopVal;
3476     Op->StartLoc = S;
3477     Op->EndLoc = S;
3478     return Op;
3479   }
3480 
3481   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3482     auto Op = std::make_unique<ARMOperand>(k_CoprocReg);
3483     Op->Cop.Val = CopVal;
3484     Op->StartLoc = S;
3485     Op->EndLoc = S;
3486     return Op;
3487   }
3488 
3489   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3490                                                         SMLoc E) {
3491     auto Op = std::make_unique<ARMOperand>(k_CoprocOption);
3492     Op->Cop.Val = Val;
3493     Op->StartLoc = S;
3494     Op->EndLoc = E;
3495     return Op;
3496   }
3497 
3498   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3499     auto Op = std::make_unique<ARMOperand>(k_CCOut);
3500     Op->Reg.RegNum = RegNum;
3501     Op->StartLoc = S;
3502     Op->EndLoc = S;
3503     return Op;
3504   }
3505 
3506   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3507     auto Op = std::make_unique<ARMOperand>(k_Token);
3508     Op->Tok.Data = Str.data();
3509     Op->Tok.Length = Str.size();
3510     Op->StartLoc = S;
3511     Op->EndLoc = S;
3512     return Op;
3513   }
3514 
3515   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3516                                                SMLoc E) {
3517     auto Op = std::make_unique<ARMOperand>(k_Register);
3518     Op->Reg.RegNum = RegNum;
3519     Op->StartLoc = S;
3520     Op->EndLoc = E;
3521     return Op;
3522   }
3523 
3524   static std::unique_ptr<ARMOperand>
3525   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3526                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3527                         SMLoc E) {
3528     auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister);
3529     Op->RegShiftedReg.ShiftTy = ShTy;
3530     Op->RegShiftedReg.SrcReg = SrcReg;
3531     Op->RegShiftedReg.ShiftReg = ShiftReg;
3532     Op->RegShiftedReg.ShiftImm = ShiftImm;
3533     Op->StartLoc = S;
3534     Op->EndLoc = E;
3535     return Op;
3536   }
3537 
3538   static std::unique_ptr<ARMOperand>
3539   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3540                          unsigned ShiftImm, SMLoc S, SMLoc E) {
3541     auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate);
3542     Op->RegShiftedImm.ShiftTy = ShTy;
3543     Op->RegShiftedImm.SrcReg = SrcReg;
3544     Op->RegShiftedImm.ShiftImm = ShiftImm;
3545     Op->StartLoc = S;
3546     Op->EndLoc = E;
3547     return Op;
3548   }
3549 
3550   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3551                                                       SMLoc S, SMLoc E) {
3552     auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate);
3553     Op->ShifterImm.isASR = isASR;
3554     Op->ShifterImm.Imm = Imm;
3555     Op->StartLoc = S;
3556     Op->EndLoc = E;
3557     return Op;
3558   }
3559 
3560   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3561                                                   SMLoc E) {
3562     auto Op = std::make_unique<ARMOperand>(k_RotateImmediate);
3563     Op->RotImm.Imm = Imm;
3564     Op->StartLoc = S;
3565     Op->EndLoc = E;
3566     return Op;
3567   }
3568 
3569   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3570                                                   SMLoc S, SMLoc E) {
3571     auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate);
3572     Op->ModImm.Bits = Bits;
3573     Op->ModImm.Rot = Rot;
3574     Op->StartLoc = S;
3575     Op->EndLoc = E;
3576     return Op;
3577   }
3578 
3579   static std::unique_ptr<ARMOperand>
3580   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3581     auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate);
3582     Op->Imm.Val = Val;
3583     Op->StartLoc = S;
3584     Op->EndLoc = E;
3585     return Op;
3586   }
3587 
3588   static std::unique_ptr<ARMOperand>
3589   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3590     auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor);
3591     Op->Bitfield.LSB = LSB;
3592     Op->Bitfield.Width = Width;
3593     Op->StartLoc = S;
3594     Op->EndLoc = E;
3595     return Op;
3596   }
3597 
3598   static std::unique_ptr<ARMOperand>
3599   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3600                 SMLoc StartLoc, SMLoc EndLoc) {
3601     assert(Regs.size() > 0 && "RegList contains no registers?");
3602     KindTy Kind = k_RegisterList;
3603 
3604     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3605             Regs.front().second)) {
3606       if (Regs.back().second == ARM::VPR)
3607         Kind = k_FPDRegisterListWithVPR;
3608       else
3609         Kind = k_DPRRegisterList;
3610     } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3611                    Regs.front().second)) {
3612       if (Regs.back().second == ARM::VPR)
3613         Kind = k_FPSRegisterListWithVPR;
3614       else
3615         Kind = k_SPRRegisterList;
3616     }
3617 
3618     if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3619       Kind = k_RegisterListWithAPSR;
3620 
3621     assert(llvm::is_sorted(Regs) && "Register list must be sorted by encoding");
3622 
3623     auto Op = std::make_unique<ARMOperand>(Kind);
3624     for (const auto &P : Regs)
3625       Op->Registers.push_back(P.second);
3626 
3627     Op->StartLoc = StartLoc;
3628     Op->EndLoc = EndLoc;
3629     return Op;
3630   }
3631 
3632   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3633                                                       unsigned Count,
3634                                                       bool isDoubleSpaced,
3635                                                       SMLoc S, SMLoc E) {
3636     auto Op = std::make_unique<ARMOperand>(k_VectorList);
3637     Op->VectorList.RegNum = RegNum;
3638     Op->VectorList.Count = Count;
3639     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3640     Op->StartLoc = S;
3641     Op->EndLoc = E;
3642     return Op;
3643   }
3644 
3645   static std::unique_ptr<ARMOperand>
3646   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3647                            SMLoc S, SMLoc E) {
3648     auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes);
3649     Op->VectorList.RegNum = RegNum;
3650     Op->VectorList.Count = Count;
3651     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3652     Op->StartLoc = S;
3653     Op->EndLoc = E;
3654     return Op;
3655   }
3656 
3657   static std::unique_ptr<ARMOperand>
3658   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3659                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
3660     auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed);
3661     Op->VectorList.RegNum = RegNum;
3662     Op->VectorList.Count = Count;
3663     Op->VectorList.LaneIndex = Index;
3664     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3665     Op->StartLoc = S;
3666     Op->EndLoc = E;
3667     return Op;
3668   }
3669 
3670   static std::unique_ptr<ARMOperand>
3671   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3672     auto Op = std::make_unique<ARMOperand>(k_VectorIndex);
3673     Op->VectorIndex.Val = Idx;
3674     Op->StartLoc = S;
3675     Op->EndLoc = E;
3676     return Op;
3677   }
3678 
3679   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3680                                                SMLoc E) {
3681     auto Op = std::make_unique<ARMOperand>(k_Immediate);
3682     Op->Imm.Val = Val;
3683     Op->StartLoc = S;
3684     Op->EndLoc = E;
3685     return Op;
3686   }
3687 
3688   static std::unique_ptr<ARMOperand>
3689   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3690             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3691             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3692             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3693     auto Op = std::make_unique<ARMOperand>(k_Memory);
3694     Op->Memory.BaseRegNum = BaseRegNum;
3695     Op->Memory.OffsetImm = OffsetImm;
3696     Op->Memory.OffsetRegNum = OffsetRegNum;
3697     Op->Memory.ShiftType = ShiftType;
3698     Op->Memory.ShiftImm = ShiftImm;
3699     Op->Memory.Alignment = Alignment;
3700     Op->Memory.isNegative = isNegative;
3701     Op->StartLoc = S;
3702     Op->EndLoc = E;
3703     Op->AlignmentLoc = AlignmentLoc;
3704     return Op;
3705   }
3706 
3707   static std::unique_ptr<ARMOperand>
3708   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3709                    unsigned ShiftImm, SMLoc S, SMLoc E) {
3710     auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister);
3711     Op->PostIdxReg.RegNum = RegNum;
3712     Op->PostIdxReg.isAdd = isAdd;
3713     Op->PostIdxReg.ShiftTy = ShiftTy;
3714     Op->PostIdxReg.ShiftImm = ShiftImm;
3715     Op->StartLoc = S;
3716     Op->EndLoc = E;
3717     return Op;
3718   }
3719 
3720   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3721                                                          SMLoc S) {
3722     auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt);
3723     Op->MBOpt.Val = Opt;
3724     Op->StartLoc = S;
3725     Op->EndLoc = S;
3726     return Op;
3727   }
3728 
3729   static std::unique_ptr<ARMOperand>
3730   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3731     auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3732     Op->ISBOpt.Val = Opt;
3733     Op->StartLoc = S;
3734     Op->EndLoc = S;
3735     return Op;
3736   }
3737 
3738   static std::unique_ptr<ARMOperand>
3739   CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3740     auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3741     Op->TSBOpt.Val = Opt;
3742     Op->StartLoc = S;
3743     Op->EndLoc = S;
3744     return Op;
3745   }
3746 
3747   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3748                                                       SMLoc S) {
3749     auto Op = std::make_unique<ARMOperand>(k_ProcIFlags);
3750     Op->IFlags.Val = IFlags;
3751     Op->StartLoc = S;
3752     Op->EndLoc = S;
3753     return Op;
3754   }
3755 
3756   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3757     auto Op = std::make_unique<ARMOperand>(k_MSRMask);
3758     Op->MMask.Val = MMask;
3759     Op->StartLoc = S;
3760     Op->EndLoc = S;
3761     return Op;
3762   }
3763 
3764   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3765     auto Op = std::make_unique<ARMOperand>(k_BankedReg);
3766     Op->BankedReg.Val = Reg;
3767     Op->StartLoc = S;
3768     Op->EndLoc = S;
3769     return Op;
3770   }
3771 };
3772 
3773 } // end anonymous namespace.
3774 
3775 void ARMOperand::print(raw_ostream &OS) const {
3776   auto RegName = [](unsigned Reg) {
3777     if (Reg)
3778       return ARMInstPrinter::getRegisterName(Reg);
3779     else
3780       return "noreg";
3781   };
3782 
3783   switch (Kind) {
3784   case k_CondCode:
3785     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3786     break;
3787   case k_VPTPred:
3788     OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3789     break;
3790   case k_CCOut:
3791     OS << "<ccout " << RegName(getReg()) << ">";
3792     break;
3793   case k_ITCondMask: {
3794     static const char *const MaskStr[] = {
3795       "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3796       "(tt)",      "(ttet)", "(tte)", "(ttee)",
3797       "(t)",       "(tett)", "(tet)", "(tete)",
3798       "(te)",      "(teet)", "(tee)", "(teee)",
3799     };
3800     assert((ITMask.Mask & 0xf) == ITMask.Mask);
3801     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3802     break;
3803   }
3804   case k_CoprocNum:
3805     OS << "<coprocessor number: " << getCoproc() << ">";
3806     break;
3807   case k_CoprocReg:
3808     OS << "<coprocessor register: " << getCoproc() << ">";
3809     break;
3810   case k_CoprocOption:
3811     OS << "<coprocessor option: " << CoprocOption.Val << ">";
3812     break;
3813   case k_MSRMask:
3814     OS << "<mask: " << getMSRMask() << ">";
3815     break;
3816   case k_BankedReg:
3817     OS << "<banked reg: " << getBankedReg() << ">";
3818     break;
3819   case k_Immediate:
3820     OS << *getImm();
3821     break;
3822   case k_MemBarrierOpt:
3823     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3824     break;
3825   case k_InstSyncBarrierOpt:
3826     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3827     break;
3828   case k_TraceSyncBarrierOpt:
3829     OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3830     break;
3831   case k_Memory:
3832     OS << "<memory";
3833     if (Memory.BaseRegNum)
3834       OS << " base:" << RegName(Memory.BaseRegNum);
3835     if (Memory.OffsetImm)
3836       OS << " offset-imm:" << *Memory.OffsetImm;
3837     if (Memory.OffsetRegNum)
3838       OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3839          << RegName(Memory.OffsetRegNum);
3840     if (Memory.ShiftType != ARM_AM::no_shift) {
3841       OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3842       OS << " shift-imm:" << Memory.ShiftImm;
3843     }
3844     if (Memory.Alignment)
3845       OS << " alignment:" << Memory.Alignment;
3846     OS << ">";
3847     break;
3848   case k_PostIndexRegister:
3849     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3850        << RegName(PostIdxReg.RegNum);
3851     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3852       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3853          << PostIdxReg.ShiftImm;
3854     OS << ">";
3855     break;
3856   case k_ProcIFlags: {
3857     OS << "<ARM_PROC::";
3858     unsigned IFlags = getProcIFlags();
3859     for (int i=2; i >= 0; --i)
3860       if (IFlags & (1 << i))
3861         OS << ARM_PROC::IFlagsToString(1 << i);
3862     OS << ">";
3863     break;
3864   }
3865   case k_Register:
3866     OS << "<register " << RegName(getReg()) << ">";
3867     break;
3868   case k_ShifterImmediate:
3869     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3870        << " #" << ShifterImm.Imm << ">";
3871     break;
3872   case k_ShiftedRegister:
3873     OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3874        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3875        << RegName(RegShiftedReg.ShiftReg) << ">";
3876     break;
3877   case k_ShiftedImmediate:
3878     OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3879        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3880        << RegShiftedImm.ShiftImm << ">";
3881     break;
3882   case k_RotateImmediate:
3883     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3884     break;
3885   case k_ModifiedImmediate:
3886     OS << "<mod_imm #" << ModImm.Bits << ", #"
3887        <<  ModImm.Rot << ")>";
3888     break;
3889   case k_ConstantPoolImmediate:
3890     OS << "<constant_pool_imm #" << *getConstantPoolImm();
3891     break;
3892   case k_BitfieldDescriptor:
3893     OS << "<bitfield " << "lsb: " << Bitfield.LSB
3894        << ", width: " << Bitfield.Width << ">";
3895     break;
3896   case k_RegisterList:
3897   case k_RegisterListWithAPSR:
3898   case k_DPRRegisterList:
3899   case k_SPRRegisterList:
3900   case k_FPSRegisterListWithVPR:
3901   case k_FPDRegisterListWithVPR: {
3902     OS << "<register_list ";
3903 
3904     const SmallVectorImpl<unsigned> &RegList = getRegList();
3905     for (SmallVectorImpl<unsigned>::const_iterator
3906            I = RegList.begin(), E = RegList.end(); I != E; ) {
3907       OS << RegName(*I);
3908       if (++I < E) OS << ", ";
3909     }
3910 
3911     OS << ">";
3912     break;
3913   }
3914   case k_VectorList:
3915     OS << "<vector_list " << VectorList.Count << " * "
3916        << RegName(VectorList.RegNum) << ">";
3917     break;
3918   case k_VectorListAllLanes:
3919     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3920        << RegName(VectorList.RegNum) << ">";
3921     break;
3922   case k_VectorListIndexed:
3923     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3924        << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3925     break;
3926   case k_Token:
3927     OS << "'" << getToken() << "'";
3928     break;
3929   case k_VectorIndex:
3930     OS << "<vectorindex " << getVectorIndex() << ">";
3931     break;
3932   }
3933 }
3934 
3935 /// @name Auto-generated Match Functions
3936 /// {
3937 
3938 static unsigned MatchRegisterName(StringRef Name);
3939 
3940 /// }
3941 
3942 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3943                                  SMLoc &StartLoc, SMLoc &EndLoc) {
3944   const AsmToken &Tok = getParser().getTok();
3945   StartLoc = Tok.getLoc();
3946   EndLoc = Tok.getEndLoc();
3947   RegNo = tryParseRegister();
3948 
3949   return (RegNo == (unsigned)-1);
3950 }
3951 
3952 OperandMatchResultTy ARMAsmParser::tryParseRegister(unsigned &RegNo,
3953                                                     SMLoc &StartLoc,
3954                                                     SMLoc &EndLoc) {
3955   if (ParseRegister(RegNo, StartLoc, EndLoc))
3956     return MatchOperand_NoMatch;
3957   return MatchOperand_Success;
3958 }
3959 
3960 /// Try to parse a register name.  The token must be an Identifier when called,
3961 /// and if it is a register name the token is eaten and the register number is
3962 /// returned.  Otherwise return -1.
3963 int ARMAsmParser::tryParseRegister() {
3964   MCAsmParser &Parser = getParser();
3965   const AsmToken &Tok = Parser.getTok();
3966   if (Tok.isNot(AsmToken::Identifier)) return -1;
3967 
3968   std::string lowerCase = Tok.getString().lower();
3969   unsigned RegNum = MatchRegisterName(lowerCase);
3970   if (!RegNum) {
3971     RegNum = StringSwitch<unsigned>(lowerCase)
3972       .Case("r13", ARM::SP)
3973       .Case("r14", ARM::LR)
3974       .Case("r15", ARM::PC)
3975       .Case("ip", ARM::R12)
3976       // Additional register name aliases for 'gas' compatibility.
3977       .Case("a1", ARM::R0)
3978       .Case("a2", ARM::R1)
3979       .Case("a3", ARM::R2)
3980       .Case("a4", ARM::R3)
3981       .Case("v1", ARM::R4)
3982       .Case("v2", ARM::R5)
3983       .Case("v3", ARM::R6)
3984       .Case("v4", ARM::R7)
3985       .Case("v5", ARM::R8)
3986       .Case("v6", ARM::R9)
3987       .Case("v7", ARM::R10)
3988       .Case("v8", ARM::R11)
3989       .Case("sb", ARM::R9)
3990       .Case("sl", ARM::R10)
3991       .Case("fp", ARM::R11)
3992       .Default(0);
3993   }
3994   if (!RegNum) {
3995     // Check for aliases registered via .req. Canonicalize to lower case.
3996     // That's more consistent since register names are case insensitive, and
3997     // it's how the original entry was passed in from MC/MCParser/AsmParser.
3998     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3999     // If no match, return failure.
4000     if (Entry == RegisterReqs.end())
4001       return -1;
4002     Parser.Lex(); // Eat identifier token.
4003     return Entry->getValue();
4004   }
4005 
4006   // Some FPUs only have 16 D registers, so D16-D31 are invalid
4007   if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
4008     return -1;
4009 
4010   Parser.Lex(); // Eat identifier token.
4011 
4012   return RegNum;
4013 }
4014 
4015 // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
4016 // If a recoverable error occurs, return 1. If an irrecoverable error
4017 // occurs, return -1. An irrecoverable error is one where tokens have been
4018 // consumed in the process of trying to parse the shifter (i.e., when it is
4019 // indeed a shifter operand, but malformed).
4020 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
4021   MCAsmParser &Parser = getParser();
4022   SMLoc S = Parser.getTok().getLoc();
4023   const AsmToken &Tok = Parser.getTok();
4024   if (Tok.isNot(AsmToken::Identifier))
4025     return -1;
4026 
4027   std::string lowerCase = Tok.getString().lower();
4028   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
4029       .Case("asl", ARM_AM::lsl)
4030       .Case("lsl", ARM_AM::lsl)
4031       .Case("lsr", ARM_AM::lsr)
4032       .Case("asr", ARM_AM::asr)
4033       .Case("ror", ARM_AM::ror)
4034       .Case("rrx", ARM_AM::rrx)
4035       .Default(ARM_AM::no_shift);
4036 
4037   if (ShiftTy == ARM_AM::no_shift)
4038     return 1;
4039 
4040   Parser.Lex(); // Eat the operator.
4041 
4042   // The source register for the shift has already been added to the
4043   // operand list, so we need to pop it off and combine it into the shifted
4044   // register operand instead.
4045   std::unique_ptr<ARMOperand> PrevOp(
4046       (ARMOperand *)Operands.pop_back_val().release());
4047   if (!PrevOp->isReg())
4048     return Error(PrevOp->getStartLoc(), "shift must be of a register");
4049   int SrcReg = PrevOp->getReg();
4050 
4051   SMLoc EndLoc;
4052   int64_t Imm = 0;
4053   int ShiftReg = 0;
4054   if (ShiftTy == ARM_AM::rrx) {
4055     // RRX Doesn't have an explicit shift amount. The encoder expects
4056     // the shift register to be the same as the source register. Seems odd,
4057     // but OK.
4058     ShiftReg = SrcReg;
4059   } else {
4060     // Figure out if this is shifted by a constant or a register (for non-RRX).
4061     if (Parser.getTok().is(AsmToken::Hash) ||
4062         Parser.getTok().is(AsmToken::Dollar)) {
4063       Parser.Lex(); // Eat hash.
4064       SMLoc ImmLoc = Parser.getTok().getLoc();
4065       const MCExpr *ShiftExpr = nullptr;
4066       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
4067         Error(ImmLoc, "invalid immediate shift value");
4068         return -1;
4069       }
4070       // The expression must be evaluatable as an immediate.
4071       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4072       if (!CE) {
4073         Error(ImmLoc, "invalid immediate shift value");
4074         return -1;
4075       }
4076       // Range check the immediate.
4077       // lsl, ror: 0 <= imm <= 31
4078       // lsr, asr: 0 <= imm <= 32
4079       Imm = CE->getValue();
4080       if (Imm < 0 ||
4081           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4082           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4083         Error(ImmLoc, "immediate shift value out of range");
4084         return -1;
4085       }
4086       // shift by zero is a nop. Always send it through as lsl.
4087       // ('as' compatibility)
4088       if (Imm == 0)
4089         ShiftTy = ARM_AM::lsl;
4090     } else if (Parser.getTok().is(AsmToken::Identifier)) {
4091       SMLoc L = Parser.getTok().getLoc();
4092       EndLoc = Parser.getTok().getEndLoc();
4093       ShiftReg = tryParseRegister();
4094       if (ShiftReg == -1) {
4095         Error(L, "expected immediate or register in shift operand");
4096         return -1;
4097       }
4098     } else {
4099       Error(Parser.getTok().getLoc(),
4100             "expected immediate or register in shift operand");
4101       return -1;
4102     }
4103   }
4104 
4105   if (ShiftReg && ShiftTy != ARM_AM::rrx)
4106     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4107                                                          ShiftReg, Imm,
4108                                                          S, EndLoc));
4109   else
4110     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4111                                                           S, EndLoc));
4112 
4113   return 0;
4114 }
4115 
4116 /// Try to parse a register name.  The token must be an Identifier when called.
4117 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
4118 /// if there is a "writeback". 'true' if it's not a register.
4119 ///
4120 /// TODO this is likely to change to allow different register types and or to
4121 /// parse for a specific register type.
4122 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4123   MCAsmParser &Parser = getParser();
4124   SMLoc RegStartLoc = Parser.getTok().getLoc();
4125   SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4126   int RegNo = tryParseRegister();
4127   if (RegNo == -1)
4128     return true;
4129 
4130   Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4131 
4132   const AsmToken &ExclaimTok = Parser.getTok();
4133   if (ExclaimTok.is(AsmToken::Exclaim)) {
4134     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4135                                                ExclaimTok.getLoc()));
4136     Parser.Lex(); // Eat exclaim token
4137     return false;
4138   }
4139 
4140   // Also check for an index operand. This is only legal for vector registers,
4141   // but that'll get caught OK in operand matching, so we don't need to
4142   // explicitly filter everything else out here.
4143   if (Parser.getTok().is(AsmToken::LBrac)) {
4144     SMLoc SIdx = Parser.getTok().getLoc();
4145     Parser.Lex(); // Eat left bracket token.
4146 
4147     const MCExpr *ImmVal;
4148     if (getParser().parseExpression(ImmVal))
4149       return true;
4150     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4151     if (!MCE)
4152       return TokError("immediate value expected for vector index");
4153 
4154     if (Parser.getTok().isNot(AsmToken::RBrac))
4155       return Error(Parser.getTok().getLoc(), "']' expected");
4156 
4157     SMLoc E = Parser.getTok().getEndLoc();
4158     Parser.Lex(); // Eat right bracket token.
4159 
4160     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4161                                                      SIdx, E,
4162                                                      getContext()));
4163   }
4164 
4165   return false;
4166 }
4167 
4168 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
4169 /// instruction with a symbolic operand name.
4170 /// We accept "crN" syntax for GAS compatibility.
4171 /// <operand-name> ::= <prefix><number>
4172 /// If CoprocOp is 'c', then:
4173 ///   <prefix> ::= c | cr
4174 /// If CoprocOp is 'p', then :
4175 ///   <prefix> ::= p
4176 /// <number> ::= integer in range [0, 15]
4177 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4178   // Use the same layout as the tablegen'erated register name matcher. Ugly,
4179   // but efficient.
4180   if (Name.size() < 2 || Name[0] != CoprocOp)
4181     return -1;
4182   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4183 
4184   switch (Name.size()) {
4185   default: return -1;
4186   case 1:
4187     switch (Name[0]) {
4188     default:  return -1;
4189     case '0': return 0;
4190     case '1': return 1;
4191     case '2': return 2;
4192     case '3': return 3;
4193     case '4': return 4;
4194     case '5': return 5;
4195     case '6': return 6;
4196     case '7': return 7;
4197     case '8': return 8;
4198     case '9': return 9;
4199     }
4200   case 2:
4201     if (Name[0] != '1')
4202       return -1;
4203     switch (Name[1]) {
4204     default:  return -1;
4205     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4206     // However, old cores (v5/v6) did use them in that way.
4207     case '0': return 10;
4208     case '1': return 11;
4209     case '2': return 12;
4210     case '3': return 13;
4211     case '4': return 14;
4212     case '5': return 15;
4213     }
4214   }
4215 }
4216 
4217 /// parseITCondCode - Try to parse a condition code for an IT instruction.
4218 OperandMatchResultTy
4219 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4220   MCAsmParser &Parser = getParser();
4221   SMLoc S = Parser.getTok().getLoc();
4222   const AsmToken &Tok = Parser.getTok();
4223   if (!Tok.is(AsmToken::Identifier))
4224     return MatchOperand_NoMatch;
4225   unsigned CC = ARMCondCodeFromString(Tok.getString());
4226   if (CC == ~0U)
4227     return MatchOperand_NoMatch;
4228   Parser.Lex(); // Eat the token.
4229 
4230   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4231 
4232   return MatchOperand_Success;
4233 }
4234 
4235 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4236 /// token must be an Identifier when called, and if it is a coprocessor
4237 /// number, the token is eaten and the operand is added to the operand list.
4238 OperandMatchResultTy
4239 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4240   MCAsmParser &Parser = getParser();
4241   SMLoc S = Parser.getTok().getLoc();
4242   const AsmToken &Tok = Parser.getTok();
4243   if (Tok.isNot(AsmToken::Identifier))
4244     return MatchOperand_NoMatch;
4245 
4246   int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4247   if (Num == -1)
4248     return MatchOperand_NoMatch;
4249   if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4250     return MatchOperand_NoMatch;
4251 
4252   Parser.Lex(); // Eat identifier token.
4253   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4254   return MatchOperand_Success;
4255 }
4256 
4257 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4258 /// token must be an Identifier when called, and if it is a coprocessor
4259 /// number, the token is eaten and the operand is added to the operand list.
4260 OperandMatchResultTy
4261 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4262   MCAsmParser &Parser = getParser();
4263   SMLoc S = Parser.getTok().getLoc();
4264   const AsmToken &Tok = Parser.getTok();
4265   if (Tok.isNot(AsmToken::Identifier))
4266     return MatchOperand_NoMatch;
4267 
4268   int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4269   if (Reg == -1)
4270     return MatchOperand_NoMatch;
4271 
4272   Parser.Lex(); // Eat identifier token.
4273   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4274   return MatchOperand_Success;
4275 }
4276 
4277 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4278 /// coproc_option : '{' imm0_255 '}'
4279 OperandMatchResultTy
4280 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4281   MCAsmParser &Parser = getParser();
4282   SMLoc S = Parser.getTok().getLoc();
4283 
4284   // If this isn't a '{', this isn't a coprocessor immediate operand.
4285   if (Parser.getTok().isNot(AsmToken::LCurly))
4286     return MatchOperand_NoMatch;
4287   Parser.Lex(); // Eat the '{'
4288 
4289   const MCExpr *Expr;
4290   SMLoc Loc = Parser.getTok().getLoc();
4291   if (getParser().parseExpression(Expr)) {
4292     Error(Loc, "illegal expression");
4293     return MatchOperand_ParseFail;
4294   }
4295   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4296   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4297     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4298     return MatchOperand_ParseFail;
4299   }
4300   int Val = CE->getValue();
4301 
4302   // Check for and consume the closing '}'
4303   if (Parser.getTok().isNot(AsmToken::RCurly))
4304     return MatchOperand_ParseFail;
4305   SMLoc E = Parser.getTok().getEndLoc();
4306   Parser.Lex(); // Eat the '}'
4307 
4308   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4309   return MatchOperand_Success;
4310 }
4311 
4312 // For register list parsing, we need to map from raw GPR register numbering
4313 // to the enumeration values. The enumeration values aren't sorted by
4314 // register number due to our using "sp", "lr" and "pc" as canonical names.
4315 static unsigned getNextRegister(unsigned Reg) {
4316   // If this is a GPR, we need to do it manually, otherwise we can rely
4317   // on the sort ordering of the enumeration since the other reg-classes
4318   // are sane.
4319   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4320     return Reg + 1;
4321   switch(Reg) {
4322   default: llvm_unreachable("Invalid GPR number!");
4323   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
4324   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
4325   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
4326   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
4327   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
4328   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4329   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
4330   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
4331   }
4332 }
4333 
4334 // Insert an <Encoding, Register> pair in an ordered vector. Return true on
4335 // success, or false, if duplicate encoding found.
4336 static bool
4337 insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4338                    unsigned Enc, unsigned Reg) {
4339   Regs.emplace_back(Enc, Reg);
4340   for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4341     if (J->first == Enc) {
4342       Regs.erase(J.base());
4343       return false;
4344     }
4345     if (J->first < Enc)
4346       break;
4347     std::swap(*I, *J);
4348   }
4349   return true;
4350 }
4351 
4352 /// Parse a register list.
4353 bool ARMAsmParser::parseRegisterList(OperandVector &Operands,
4354                                      bool EnforceOrder) {
4355   MCAsmParser &Parser = getParser();
4356   if (Parser.getTok().isNot(AsmToken::LCurly))
4357     return TokError("Token is not a Left Curly Brace");
4358   SMLoc S = Parser.getTok().getLoc();
4359   Parser.Lex(); // Eat '{' token.
4360   SMLoc RegLoc = Parser.getTok().getLoc();
4361 
4362   // Check the first register in the list to see what register class
4363   // this is a list of.
4364   int Reg = tryParseRegister();
4365   if (Reg == -1)
4366     return Error(RegLoc, "register expected");
4367 
4368   // The reglist instructions have at most 16 registers, so reserve
4369   // space for that many.
4370   int EReg = 0;
4371   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4372 
4373   // Allow Q regs and just interpret them as the two D sub-registers.
4374   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4375     Reg = getDRegFromQReg(Reg);
4376     EReg = MRI->getEncodingValue(Reg);
4377     Registers.emplace_back(EReg, Reg);
4378     ++Reg;
4379   }
4380   const MCRegisterClass *RC;
4381   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4382     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4383   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4384     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4385   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4386     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4387   else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4388     RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4389   else
4390     return Error(RegLoc, "invalid register in register list");
4391 
4392   // Store the register.
4393   EReg = MRI->getEncodingValue(Reg);
4394   Registers.emplace_back(EReg, Reg);
4395 
4396   // This starts immediately after the first register token in the list,
4397   // so we can see either a comma or a minus (range separator) as a legal
4398   // next token.
4399   while (Parser.getTok().is(AsmToken::Comma) ||
4400          Parser.getTok().is(AsmToken::Minus)) {
4401     if (Parser.getTok().is(AsmToken::Minus)) {
4402       Parser.Lex(); // Eat the minus.
4403       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4404       int EndReg = tryParseRegister();
4405       if (EndReg == -1)
4406         return Error(AfterMinusLoc, "register expected");
4407       // Allow Q regs and just interpret them as the two D sub-registers.
4408       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4409         EndReg = getDRegFromQReg(EndReg) + 1;
4410       // If the register is the same as the start reg, there's nothing
4411       // more to do.
4412       if (Reg == EndReg)
4413         continue;
4414       // The register must be in the same register class as the first.
4415       if (!RC->contains(EndReg))
4416         return Error(AfterMinusLoc, "invalid register in register list");
4417       // Ranges must go from low to high.
4418       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4419         return Error(AfterMinusLoc, "bad range in register list");
4420 
4421       // Add all the registers in the range to the register list.
4422       while (Reg != EndReg) {
4423         Reg = getNextRegister(Reg);
4424         EReg = MRI->getEncodingValue(Reg);
4425         if (!insertNoDuplicates(Registers, EReg, Reg)) {
4426           Warning(AfterMinusLoc, StringRef("duplicated register (") +
4427                                      ARMInstPrinter::getRegisterName(Reg) +
4428                                      ") in register list");
4429         }
4430       }
4431       continue;
4432     }
4433     Parser.Lex(); // Eat the comma.
4434     RegLoc = Parser.getTok().getLoc();
4435     int OldReg = Reg;
4436     const AsmToken RegTok = Parser.getTok();
4437     Reg = tryParseRegister();
4438     if (Reg == -1)
4439       return Error(RegLoc, "register expected");
4440     // Allow Q regs and just interpret them as the two D sub-registers.
4441     bool isQReg = false;
4442     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4443       Reg = getDRegFromQReg(Reg);
4444       isQReg = true;
4445     }
4446     if (!RC->contains(Reg) &&
4447         RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4448         ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4449       // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4450       // subset of GPRRegClassId except it contains APSR as well.
4451       RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4452     }
4453     if (Reg == ARM::VPR &&
4454         (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4455          RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4456          RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4457       RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4458       EReg = MRI->getEncodingValue(Reg);
4459       if (!insertNoDuplicates(Registers, EReg, Reg)) {
4460         Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4461                             ") in register list");
4462       }
4463       continue;
4464     }
4465     // The register must be in the same register class as the first.
4466     if (!RC->contains(Reg))
4467       return Error(RegLoc, "invalid register in register list");
4468     // In most cases, the list must be monotonically increasing. An
4469     // exception is CLRM, which is order-independent anyway, so
4470     // there's no potential for confusion if you write clrm {r2,r1}
4471     // instead of clrm {r1,r2}.
4472     if (EnforceOrder &&
4473         MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4474       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4475         Warning(RegLoc, "register list not in ascending order");
4476       else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4477         return Error(RegLoc, "register list not in ascending order");
4478     }
4479     // VFP register lists must also be contiguous.
4480     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4481         RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4482         Reg != OldReg + 1)
4483       return Error(RegLoc, "non-contiguous register range");
4484     EReg = MRI->getEncodingValue(Reg);
4485     if (!insertNoDuplicates(Registers, EReg, Reg)) {
4486       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4487                           ") in register list");
4488     }
4489     if (isQReg) {
4490       EReg = MRI->getEncodingValue(++Reg);
4491       Registers.emplace_back(EReg, Reg);
4492     }
4493   }
4494 
4495   if (Parser.getTok().isNot(AsmToken::RCurly))
4496     return Error(Parser.getTok().getLoc(), "'}' expected");
4497   SMLoc E = Parser.getTok().getEndLoc();
4498   Parser.Lex(); // Eat '}' token.
4499 
4500   // Push the register list operand.
4501   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4502 
4503   // The ARM system instruction variants for LDM/STM have a '^' token here.
4504   if (Parser.getTok().is(AsmToken::Caret)) {
4505     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4506     Parser.Lex(); // Eat '^' token.
4507   }
4508 
4509   return false;
4510 }
4511 
4512 // Helper function to parse the lane index for vector lists.
4513 OperandMatchResultTy ARMAsmParser::
4514 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4515   MCAsmParser &Parser = getParser();
4516   Index = 0; // Always return a defined index value.
4517   if (Parser.getTok().is(AsmToken::LBrac)) {
4518     Parser.Lex(); // Eat the '['.
4519     if (Parser.getTok().is(AsmToken::RBrac)) {
4520       // "Dn[]" is the 'all lanes' syntax.
4521       LaneKind = AllLanes;
4522       EndLoc = Parser.getTok().getEndLoc();
4523       Parser.Lex(); // Eat the ']'.
4524       return MatchOperand_Success;
4525     }
4526 
4527     // There's an optional '#' token here. Normally there wouldn't be, but
4528     // inline assemble puts one in, and it's friendly to accept that.
4529     if (Parser.getTok().is(AsmToken::Hash))
4530       Parser.Lex(); // Eat '#' or '$'.
4531 
4532     const MCExpr *LaneIndex;
4533     SMLoc Loc = Parser.getTok().getLoc();
4534     if (getParser().parseExpression(LaneIndex)) {
4535       Error(Loc, "illegal expression");
4536       return MatchOperand_ParseFail;
4537     }
4538     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4539     if (!CE) {
4540       Error(Loc, "lane index must be empty or an integer");
4541       return MatchOperand_ParseFail;
4542     }
4543     if (Parser.getTok().isNot(AsmToken::RBrac)) {
4544       Error(Parser.getTok().getLoc(), "']' expected");
4545       return MatchOperand_ParseFail;
4546     }
4547     EndLoc = Parser.getTok().getEndLoc();
4548     Parser.Lex(); // Eat the ']'.
4549     int64_t Val = CE->getValue();
4550 
4551     // FIXME: Make this range check context sensitive for .8, .16, .32.
4552     if (Val < 0 || Val > 7) {
4553       Error(Parser.getTok().getLoc(), "lane index out of range");
4554       return MatchOperand_ParseFail;
4555     }
4556     Index = Val;
4557     LaneKind = IndexedLane;
4558     return MatchOperand_Success;
4559   }
4560   LaneKind = NoLanes;
4561   return MatchOperand_Success;
4562 }
4563 
4564 // parse a vector register list
4565 OperandMatchResultTy
4566 ARMAsmParser::parseVectorList(OperandVector &Operands) {
4567   MCAsmParser &Parser = getParser();
4568   VectorLaneTy LaneKind;
4569   unsigned LaneIndex;
4570   SMLoc S = Parser.getTok().getLoc();
4571   // As an extension (to match gas), support a plain D register or Q register
4572   // (without encosing curly braces) as a single or double entry list,
4573   // respectively.
4574   if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4575     SMLoc E = Parser.getTok().getEndLoc();
4576     int Reg = tryParseRegister();
4577     if (Reg == -1)
4578       return MatchOperand_NoMatch;
4579     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4580       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4581       if (Res != MatchOperand_Success)
4582         return Res;
4583       switch (LaneKind) {
4584       case NoLanes:
4585         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4586         break;
4587       case AllLanes:
4588         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4589                                                                 S, E));
4590         break;
4591       case IndexedLane:
4592         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4593                                                                LaneIndex,
4594                                                                false, S, E));
4595         break;
4596       }
4597       return MatchOperand_Success;
4598     }
4599     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4600       Reg = getDRegFromQReg(Reg);
4601       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4602       if (Res != MatchOperand_Success)
4603         return Res;
4604       switch (LaneKind) {
4605       case NoLanes:
4606         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4607                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4608         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4609         break;
4610       case AllLanes:
4611         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4612                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4613         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4614                                                                 S, E));
4615         break;
4616       case IndexedLane:
4617         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4618                                                                LaneIndex,
4619                                                                false, S, E));
4620         break;
4621       }
4622       return MatchOperand_Success;
4623     }
4624     Error(S, "vector register expected");
4625     return MatchOperand_ParseFail;
4626   }
4627 
4628   if (Parser.getTok().isNot(AsmToken::LCurly))
4629     return MatchOperand_NoMatch;
4630 
4631   Parser.Lex(); // Eat '{' token.
4632   SMLoc RegLoc = Parser.getTok().getLoc();
4633 
4634   int Reg = tryParseRegister();
4635   if (Reg == -1) {
4636     Error(RegLoc, "register expected");
4637     return MatchOperand_ParseFail;
4638   }
4639   unsigned Count = 1;
4640   int Spacing = 0;
4641   unsigned FirstReg = Reg;
4642 
4643   if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4644       Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4645       return MatchOperand_ParseFail;
4646   }
4647   // The list is of D registers, but we also allow Q regs and just interpret
4648   // them as the two D sub-registers.
4649   else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4650     FirstReg = Reg = getDRegFromQReg(Reg);
4651     Spacing = 1; // double-spacing requires explicit D registers, otherwise
4652                  // it's ambiguous with four-register single spaced.
4653     ++Reg;
4654     ++Count;
4655   }
4656 
4657   SMLoc E;
4658   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4659     return MatchOperand_ParseFail;
4660 
4661   while (Parser.getTok().is(AsmToken::Comma) ||
4662          Parser.getTok().is(AsmToken::Minus)) {
4663     if (Parser.getTok().is(AsmToken::Minus)) {
4664       if (!Spacing)
4665         Spacing = 1; // Register range implies a single spaced list.
4666       else if (Spacing == 2) {
4667         Error(Parser.getTok().getLoc(),
4668               "sequential registers in double spaced list");
4669         return MatchOperand_ParseFail;
4670       }
4671       Parser.Lex(); // Eat the minus.
4672       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4673       int EndReg = tryParseRegister();
4674       if (EndReg == -1) {
4675         Error(AfterMinusLoc, "register expected");
4676         return MatchOperand_ParseFail;
4677       }
4678       // Allow Q regs and just interpret them as the two D sub-registers.
4679       if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4680         EndReg = getDRegFromQReg(EndReg) + 1;
4681       // If the register is the same as the start reg, there's nothing
4682       // more to do.
4683       if (Reg == EndReg)
4684         continue;
4685       // The register must be in the same register class as the first.
4686       if ((hasMVE() &&
4687            !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4688           (!hasMVE() &&
4689            !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4690         Error(AfterMinusLoc, "invalid register in register list");
4691         return MatchOperand_ParseFail;
4692       }
4693       // Ranges must go from low to high.
4694       if (Reg > EndReg) {
4695         Error(AfterMinusLoc, "bad range in register list");
4696         return MatchOperand_ParseFail;
4697       }
4698       // Parse the lane specifier if present.
4699       VectorLaneTy NextLaneKind;
4700       unsigned NextLaneIndex;
4701       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4702           MatchOperand_Success)
4703         return MatchOperand_ParseFail;
4704       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4705         Error(AfterMinusLoc, "mismatched lane index in register list");
4706         return MatchOperand_ParseFail;
4707       }
4708 
4709       // Add all the registers in the range to the register list.
4710       Count += EndReg - Reg;
4711       Reg = EndReg;
4712       continue;
4713     }
4714     Parser.Lex(); // Eat the comma.
4715     RegLoc = Parser.getTok().getLoc();
4716     int OldReg = Reg;
4717     Reg = tryParseRegister();
4718     if (Reg == -1) {
4719       Error(RegLoc, "register expected");
4720       return MatchOperand_ParseFail;
4721     }
4722 
4723     if (hasMVE()) {
4724       if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4725         Error(RegLoc, "vector register in range Q0-Q7 expected");
4726         return MatchOperand_ParseFail;
4727       }
4728       Spacing = 1;
4729     }
4730     // vector register lists must be contiguous.
4731     // It's OK to use the enumeration values directly here rather, as the
4732     // VFP register classes have the enum sorted properly.
4733     //
4734     // The list is of D registers, but we also allow Q regs and just interpret
4735     // them as the two D sub-registers.
4736     else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4737       if (!Spacing)
4738         Spacing = 1; // Register range implies a single spaced list.
4739       else if (Spacing == 2) {
4740         Error(RegLoc,
4741               "invalid register in double-spaced list (must be 'D' register')");
4742         return MatchOperand_ParseFail;
4743       }
4744       Reg = getDRegFromQReg(Reg);
4745       if (Reg != OldReg + 1) {
4746         Error(RegLoc, "non-contiguous register range");
4747         return MatchOperand_ParseFail;
4748       }
4749       ++Reg;
4750       Count += 2;
4751       // Parse the lane specifier if present.
4752       VectorLaneTy NextLaneKind;
4753       unsigned NextLaneIndex;
4754       SMLoc LaneLoc = Parser.getTok().getLoc();
4755       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4756           MatchOperand_Success)
4757         return MatchOperand_ParseFail;
4758       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4759         Error(LaneLoc, "mismatched lane index in register list");
4760         return MatchOperand_ParseFail;
4761       }
4762       continue;
4763     }
4764     // Normal D register.
4765     // Figure out the register spacing (single or double) of the list if
4766     // we don't know it already.
4767     if (!Spacing)
4768       Spacing = 1 + (Reg == OldReg + 2);
4769 
4770     // Just check that it's contiguous and keep going.
4771     if (Reg != OldReg + Spacing) {
4772       Error(RegLoc, "non-contiguous register range");
4773       return MatchOperand_ParseFail;
4774     }
4775     ++Count;
4776     // Parse the lane specifier if present.
4777     VectorLaneTy NextLaneKind;
4778     unsigned NextLaneIndex;
4779     SMLoc EndLoc = Parser.getTok().getLoc();
4780     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4781       return MatchOperand_ParseFail;
4782     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4783       Error(EndLoc, "mismatched lane index in register list");
4784       return MatchOperand_ParseFail;
4785     }
4786   }
4787 
4788   if (Parser.getTok().isNot(AsmToken::RCurly)) {
4789     Error(Parser.getTok().getLoc(), "'}' expected");
4790     return MatchOperand_ParseFail;
4791   }
4792   E = Parser.getTok().getEndLoc();
4793   Parser.Lex(); // Eat '}' token.
4794 
4795   switch (LaneKind) {
4796   case NoLanes:
4797   case AllLanes: {
4798     // Two-register operands have been converted to the
4799     // composite register classes.
4800     if (Count == 2 && !hasMVE()) {
4801       const MCRegisterClass *RC = (Spacing == 1) ?
4802         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4803         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4804       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4805     }
4806     auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4807                    ARMOperand::CreateVectorListAllLanes);
4808     Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4809     break;
4810   }
4811   case IndexedLane:
4812     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4813                                                            LaneIndex,
4814                                                            (Spacing == 2),
4815                                                            S, E));
4816     break;
4817   }
4818   return MatchOperand_Success;
4819 }
4820 
4821 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4822 OperandMatchResultTy
4823 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4824   MCAsmParser &Parser = getParser();
4825   SMLoc S = Parser.getTok().getLoc();
4826   const AsmToken &Tok = Parser.getTok();
4827   unsigned Opt;
4828 
4829   if (Tok.is(AsmToken::Identifier)) {
4830     StringRef OptStr = Tok.getString();
4831 
4832     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4833       .Case("sy",    ARM_MB::SY)
4834       .Case("st",    ARM_MB::ST)
4835       .Case("ld",    ARM_MB::LD)
4836       .Case("sh",    ARM_MB::ISH)
4837       .Case("ish",   ARM_MB::ISH)
4838       .Case("shst",  ARM_MB::ISHST)
4839       .Case("ishst", ARM_MB::ISHST)
4840       .Case("ishld", ARM_MB::ISHLD)
4841       .Case("nsh",   ARM_MB::NSH)
4842       .Case("un",    ARM_MB::NSH)
4843       .Case("nshst", ARM_MB::NSHST)
4844       .Case("nshld", ARM_MB::NSHLD)
4845       .Case("unst",  ARM_MB::NSHST)
4846       .Case("osh",   ARM_MB::OSH)
4847       .Case("oshst", ARM_MB::OSHST)
4848       .Case("oshld", ARM_MB::OSHLD)
4849       .Default(~0U);
4850 
4851     // ishld, oshld, nshld and ld are only available from ARMv8.
4852     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4853                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4854       Opt = ~0U;
4855 
4856     if (Opt == ~0U)
4857       return MatchOperand_NoMatch;
4858 
4859     Parser.Lex(); // Eat identifier token.
4860   } else if (Tok.is(AsmToken::Hash) ||
4861              Tok.is(AsmToken::Dollar) ||
4862              Tok.is(AsmToken::Integer)) {
4863     if (Parser.getTok().isNot(AsmToken::Integer))
4864       Parser.Lex(); // Eat '#' or '$'.
4865     SMLoc Loc = Parser.getTok().getLoc();
4866 
4867     const MCExpr *MemBarrierID;
4868     if (getParser().parseExpression(MemBarrierID)) {
4869       Error(Loc, "illegal expression");
4870       return MatchOperand_ParseFail;
4871     }
4872 
4873     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4874     if (!CE) {
4875       Error(Loc, "constant expression expected");
4876       return MatchOperand_ParseFail;
4877     }
4878 
4879     int Val = CE->getValue();
4880     if (Val & ~0xf) {
4881       Error(Loc, "immediate value out of range");
4882       return MatchOperand_ParseFail;
4883     }
4884 
4885     Opt = ARM_MB::RESERVED_0 + Val;
4886   } else
4887     return MatchOperand_ParseFail;
4888 
4889   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4890   return MatchOperand_Success;
4891 }
4892 
4893 OperandMatchResultTy
4894 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4895   MCAsmParser &Parser = getParser();
4896   SMLoc S = Parser.getTok().getLoc();
4897   const AsmToken &Tok = Parser.getTok();
4898 
4899   if (Tok.isNot(AsmToken::Identifier))
4900      return MatchOperand_NoMatch;
4901 
4902   if (!Tok.getString().equals_lower("csync"))
4903     return MatchOperand_NoMatch;
4904 
4905   Parser.Lex(); // Eat identifier token.
4906 
4907   Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4908   return MatchOperand_Success;
4909 }
4910 
4911 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4912 OperandMatchResultTy
4913 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4914   MCAsmParser &Parser = getParser();
4915   SMLoc S = Parser.getTok().getLoc();
4916   const AsmToken &Tok = Parser.getTok();
4917   unsigned Opt;
4918 
4919   if (Tok.is(AsmToken::Identifier)) {
4920     StringRef OptStr = Tok.getString();
4921 
4922     if (OptStr.equals_lower("sy"))
4923       Opt = ARM_ISB::SY;
4924     else
4925       return MatchOperand_NoMatch;
4926 
4927     Parser.Lex(); // Eat identifier token.
4928   } else if (Tok.is(AsmToken::Hash) ||
4929              Tok.is(AsmToken::Dollar) ||
4930              Tok.is(AsmToken::Integer)) {
4931     if (Parser.getTok().isNot(AsmToken::Integer))
4932       Parser.Lex(); // Eat '#' or '$'.
4933     SMLoc Loc = Parser.getTok().getLoc();
4934 
4935     const MCExpr *ISBarrierID;
4936     if (getParser().parseExpression(ISBarrierID)) {
4937       Error(Loc, "illegal expression");
4938       return MatchOperand_ParseFail;
4939     }
4940 
4941     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4942     if (!CE) {
4943       Error(Loc, "constant expression expected");
4944       return MatchOperand_ParseFail;
4945     }
4946 
4947     int Val = CE->getValue();
4948     if (Val & ~0xf) {
4949       Error(Loc, "immediate value out of range");
4950       return MatchOperand_ParseFail;
4951     }
4952 
4953     Opt = ARM_ISB::RESERVED_0 + Val;
4954   } else
4955     return MatchOperand_ParseFail;
4956 
4957   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4958           (ARM_ISB::InstSyncBOpt)Opt, S));
4959   return MatchOperand_Success;
4960 }
4961 
4962 
4963 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4964 OperandMatchResultTy
4965 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4966   MCAsmParser &Parser = getParser();
4967   SMLoc S = Parser.getTok().getLoc();
4968   const AsmToken &Tok = Parser.getTok();
4969   if (!Tok.is(AsmToken::Identifier))
4970     return MatchOperand_NoMatch;
4971   StringRef IFlagsStr = Tok.getString();
4972 
4973   // An iflags string of "none" is interpreted to mean that none of the AIF
4974   // bits are set.  Not a terribly useful instruction, but a valid encoding.
4975   unsigned IFlags = 0;
4976   if (IFlagsStr != "none") {
4977         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4978       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4979         .Case("a", ARM_PROC::A)
4980         .Case("i", ARM_PROC::I)
4981         .Case("f", ARM_PROC::F)
4982         .Default(~0U);
4983 
4984       // If some specific iflag is already set, it means that some letter is
4985       // present more than once, this is not acceptable.
4986       if (Flag == ~0U || (IFlags & Flag))
4987         return MatchOperand_NoMatch;
4988 
4989       IFlags |= Flag;
4990     }
4991   }
4992 
4993   Parser.Lex(); // Eat identifier token.
4994   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4995   return MatchOperand_Success;
4996 }
4997 
4998 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4999 OperandMatchResultTy
5000 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
5001   MCAsmParser &Parser = getParser();
5002   SMLoc S = Parser.getTok().getLoc();
5003   const AsmToken &Tok = Parser.getTok();
5004 
5005   if (Tok.is(AsmToken::Integer)) {
5006     int64_t Val = Tok.getIntVal();
5007     if (Val > 255 || Val < 0) {
5008       return MatchOperand_NoMatch;
5009     }
5010     unsigned SYSmvalue = Val & 0xFF;
5011     Parser.Lex();
5012     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5013     return MatchOperand_Success;
5014   }
5015 
5016   if (!Tok.is(AsmToken::Identifier))
5017     return MatchOperand_NoMatch;
5018   StringRef Mask = Tok.getString();
5019 
5020   if (isMClass()) {
5021     auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
5022     if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
5023       return MatchOperand_NoMatch;
5024 
5025     unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
5026 
5027     Parser.Lex(); // Eat identifier token.
5028     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
5029     return MatchOperand_Success;
5030   }
5031 
5032   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5033   size_t Start = 0, Next = Mask.find('_');
5034   StringRef Flags = "";
5035   std::string SpecReg = Mask.slice(Start, Next).lower();
5036   if (Next != StringRef::npos)
5037     Flags = Mask.slice(Next+1, Mask.size());
5038 
5039   // FlagsVal contains the complete mask:
5040   // 3-0: Mask
5041   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5042   unsigned FlagsVal = 0;
5043 
5044   if (SpecReg == "apsr") {
5045     FlagsVal = StringSwitch<unsigned>(Flags)
5046     .Case("nzcvq",  0x8) // same as CPSR_f
5047     .Case("g",      0x4) // same as CPSR_s
5048     .Case("nzcvqg", 0xc) // same as CPSR_fs
5049     .Default(~0U);
5050 
5051     if (FlagsVal == ~0U) {
5052       if (!Flags.empty())
5053         return MatchOperand_NoMatch;
5054       else
5055         FlagsVal = 8; // No flag
5056     }
5057   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
5058     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
5059     if (Flags == "all" || Flags == "")
5060       Flags = "fc";
5061     for (int i = 0, e = Flags.size(); i != e; ++i) {
5062       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
5063       .Case("c", 1)
5064       .Case("x", 2)
5065       .Case("s", 4)
5066       .Case("f", 8)
5067       .Default(~0U);
5068 
5069       // If some specific flag is already set, it means that some letter is
5070       // present more than once, this is not acceptable.
5071       if (Flag == ~0U || (FlagsVal & Flag))
5072         return MatchOperand_NoMatch;
5073       FlagsVal |= Flag;
5074     }
5075   } else // No match for special register.
5076     return MatchOperand_NoMatch;
5077 
5078   // Special register without flags is NOT equivalent to "fc" flags.
5079   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
5080   // two lines would enable gas compatibility at the expense of breaking
5081   // round-tripping.
5082   //
5083   // if (!FlagsVal)
5084   //  FlagsVal = 0x9;
5085 
5086   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5087   if (SpecReg == "spsr")
5088     FlagsVal |= 16;
5089 
5090   Parser.Lex(); // Eat identifier token.
5091   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
5092   return MatchOperand_Success;
5093 }
5094 
5095 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
5096 /// use in the MRS/MSR instructions added to support virtualization.
5097 OperandMatchResultTy
5098 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5099   MCAsmParser &Parser = getParser();
5100   SMLoc S = Parser.getTok().getLoc();
5101   const AsmToken &Tok = Parser.getTok();
5102   if (!Tok.is(AsmToken::Identifier))
5103     return MatchOperand_NoMatch;
5104   StringRef RegName = Tok.getString();
5105 
5106   auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5107   if (!TheReg)
5108     return MatchOperand_NoMatch;
5109   unsigned Encoding = TheReg->Encoding;
5110 
5111   Parser.Lex(); // Eat identifier token.
5112   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5113   return MatchOperand_Success;
5114 }
5115 
5116 OperandMatchResultTy
5117 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5118                           int High) {
5119   MCAsmParser &Parser = getParser();
5120   const AsmToken &Tok = Parser.getTok();
5121   if (Tok.isNot(AsmToken::Identifier)) {
5122     Error(Parser.getTok().getLoc(), Op + " operand expected.");
5123     return MatchOperand_ParseFail;
5124   }
5125   StringRef ShiftName = Tok.getString();
5126   std::string LowerOp = Op.lower();
5127   std::string UpperOp = Op.upper();
5128   if (ShiftName != LowerOp && ShiftName != UpperOp) {
5129     Error(Parser.getTok().getLoc(), Op + " operand expected.");
5130     return MatchOperand_ParseFail;
5131   }
5132   Parser.Lex(); // Eat shift type token.
5133 
5134   // There must be a '#' and a shift amount.
5135   if (Parser.getTok().isNot(AsmToken::Hash) &&
5136       Parser.getTok().isNot(AsmToken::Dollar)) {
5137     Error(Parser.getTok().getLoc(), "'#' expected");
5138     return MatchOperand_ParseFail;
5139   }
5140   Parser.Lex(); // Eat hash token.
5141 
5142   const MCExpr *ShiftAmount;
5143   SMLoc Loc = Parser.getTok().getLoc();
5144   SMLoc EndLoc;
5145   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5146     Error(Loc, "illegal expression");
5147     return MatchOperand_ParseFail;
5148   }
5149   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5150   if (!CE) {
5151     Error(Loc, "constant expression expected");
5152     return MatchOperand_ParseFail;
5153   }
5154   int Val = CE->getValue();
5155   if (Val < Low || Val > High) {
5156     Error(Loc, "immediate value out of range");
5157     return MatchOperand_ParseFail;
5158   }
5159 
5160   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5161 
5162   return MatchOperand_Success;
5163 }
5164 
5165 OperandMatchResultTy
5166 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5167   MCAsmParser &Parser = getParser();
5168   const AsmToken &Tok = Parser.getTok();
5169   SMLoc S = Tok.getLoc();
5170   if (Tok.isNot(AsmToken::Identifier)) {
5171     Error(S, "'be' or 'le' operand expected");
5172     return MatchOperand_ParseFail;
5173   }
5174   int Val = StringSwitch<int>(Tok.getString().lower())
5175     .Case("be", 1)
5176     .Case("le", 0)
5177     .Default(-1);
5178   Parser.Lex(); // Eat the token.
5179 
5180   if (Val == -1) {
5181     Error(S, "'be' or 'le' operand expected");
5182     return MatchOperand_ParseFail;
5183   }
5184   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5185                                                                   getContext()),
5186                                            S, Tok.getEndLoc()));
5187   return MatchOperand_Success;
5188 }
5189 
5190 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5191 /// instructions. Legal values are:
5192 ///     lsl #n  'n' in [0,31]
5193 ///     asr #n  'n' in [1,32]
5194 ///             n == 32 encoded as n == 0.
5195 OperandMatchResultTy
5196 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5197   MCAsmParser &Parser = getParser();
5198   const AsmToken &Tok = Parser.getTok();
5199   SMLoc S = Tok.getLoc();
5200   if (Tok.isNot(AsmToken::Identifier)) {
5201     Error(S, "shift operator 'asr' or 'lsl' expected");
5202     return MatchOperand_ParseFail;
5203   }
5204   StringRef ShiftName = Tok.getString();
5205   bool isASR;
5206   if (ShiftName == "lsl" || ShiftName == "LSL")
5207     isASR = false;
5208   else if (ShiftName == "asr" || ShiftName == "ASR")
5209     isASR = true;
5210   else {
5211     Error(S, "shift operator 'asr' or 'lsl' expected");
5212     return MatchOperand_ParseFail;
5213   }
5214   Parser.Lex(); // Eat the operator.
5215 
5216   // A '#' and a shift amount.
5217   if (Parser.getTok().isNot(AsmToken::Hash) &&
5218       Parser.getTok().isNot(AsmToken::Dollar)) {
5219     Error(Parser.getTok().getLoc(), "'#' expected");
5220     return MatchOperand_ParseFail;
5221   }
5222   Parser.Lex(); // Eat hash token.
5223   SMLoc ExLoc = Parser.getTok().getLoc();
5224 
5225   const MCExpr *ShiftAmount;
5226   SMLoc EndLoc;
5227   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5228     Error(ExLoc, "malformed shift expression");
5229     return MatchOperand_ParseFail;
5230   }
5231   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5232   if (!CE) {
5233     Error(ExLoc, "shift amount must be an immediate");
5234     return MatchOperand_ParseFail;
5235   }
5236 
5237   int64_t Val = CE->getValue();
5238   if (isASR) {
5239     // Shift amount must be in [1,32]
5240     if (Val < 1 || Val > 32) {
5241       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5242       return MatchOperand_ParseFail;
5243     }
5244     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5245     if (isThumb() && Val == 32) {
5246       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5247       return MatchOperand_ParseFail;
5248     }
5249     if (Val == 32) Val = 0;
5250   } else {
5251     // Shift amount must be in [1,32]
5252     if (Val < 0 || Val > 31) {
5253       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5254       return MatchOperand_ParseFail;
5255     }
5256   }
5257 
5258   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5259 
5260   return MatchOperand_Success;
5261 }
5262 
5263 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5264 /// of instructions. Legal values are:
5265 ///     ror #n  'n' in {0, 8, 16, 24}
5266 OperandMatchResultTy
5267 ARMAsmParser::parseRotImm(OperandVector &Operands) {
5268   MCAsmParser &Parser = getParser();
5269   const AsmToken &Tok = Parser.getTok();
5270   SMLoc S = Tok.getLoc();
5271   if (Tok.isNot(AsmToken::Identifier))
5272     return MatchOperand_NoMatch;
5273   StringRef ShiftName = Tok.getString();
5274   if (ShiftName != "ror" && ShiftName != "ROR")
5275     return MatchOperand_NoMatch;
5276   Parser.Lex(); // Eat the operator.
5277 
5278   // A '#' and a rotate amount.
5279   if (Parser.getTok().isNot(AsmToken::Hash) &&
5280       Parser.getTok().isNot(AsmToken::Dollar)) {
5281     Error(Parser.getTok().getLoc(), "'#' expected");
5282     return MatchOperand_ParseFail;
5283   }
5284   Parser.Lex(); // Eat hash token.
5285   SMLoc ExLoc = Parser.getTok().getLoc();
5286 
5287   const MCExpr *ShiftAmount;
5288   SMLoc EndLoc;
5289   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5290     Error(ExLoc, "malformed rotate expression");
5291     return MatchOperand_ParseFail;
5292   }
5293   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5294   if (!CE) {
5295     Error(ExLoc, "rotate amount must be an immediate");
5296     return MatchOperand_ParseFail;
5297   }
5298 
5299   int64_t Val = CE->getValue();
5300   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5301   // normally, zero is represented in asm by omitting the rotate operand
5302   // entirely.
5303   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5304     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5305     return MatchOperand_ParseFail;
5306   }
5307 
5308   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5309 
5310   return MatchOperand_Success;
5311 }
5312 
5313 OperandMatchResultTy
5314 ARMAsmParser::parseModImm(OperandVector &Operands) {
5315   MCAsmParser &Parser = getParser();
5316   MCAsmLexer &Lexer = getLexer();
5317   int64_t Imm1, Imm2;
5318 
5319   SMLoc S = Parser.getTok().getLoc();
5320 
5321   // 1) A mod_imm operand can appear in the place of a register name:
5322   //   add r0, #mod_imm
5323   //   add r0, r0, #mod_imm
5324   // to correctly handle the latter, we bail out as soon as we see an
5325   // identifier.
5326   //
5327   // 2) Similarly, we do not want to parse into complex operands:
5328   //   mov r0, #mod_imm
5329   //   mov r0, :lower16:(_foo)
5330   if (Parser.getTok().is(AsmToken::Identifier) ||
5331       Parser.getTok().is(AsmToken::Colon))
5332     return MatchOperand_NoMatch;
5333 
5334   // Hash (dollar) is optional as per the ARMARM
5335   if (Parser.getTok().is(AsmToken::Hash) ||
5336       Parser.getTok().is(AsmToken::Dollar)) {
5337     // Avoid parsing into complex operands (#:)
5338     if (Lexer.peekTok().is(AsmToken::Colon))
5339       return MatchOperand_NoMatch;
5340 
5341     // Eat the hash (dollar)
5342     Parser.Lex();
5343   }
5344 
5345   SMLoc Sx1, Ex1;
5346   Sx1 = Parser.getTok().getLoc();
5347   const MCExpr *Imm1Exp;
5348   if (getParser().parseExpression(Imm1Exp, Ex1)) {
5349     Error(Sx1, "malformed expression");
5350     return MatchOperand_ParseFail;
5351   }
5352 
5353   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5354 
5355   if (CE) {
5356     // Immediate must fit within 32-bits
5357     Imm1 = CE->getValue();
5358     int Enc = ARM_AM::getSOImmVal(Imm1);
5359     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5360       // We have a match!
5361       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5362                                                   (Enc & 0xF00) >> 7,
5363                                                   Sx1, Ex1));
5364       return MatchOperand_Success;
5365     }
5366 
5367     // We have parsed an immediate which is not for us, fallback to a plain
5368     // immediate. This can happen for instruction aliases. For an example,
5369     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5370     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5371     // instruction with a mod_imm operand. The alias is defined such that the
5372     // parser method is shared, that's why we have to do this here.
5373     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5374       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5375       return MatchOperand_Success;
5376     }
5377   } else {
5378     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5379     // MCFixup). Fallback to a plain immediate.
5380     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5381     return MatchOperand_Success;
5382   }
5383 
5384   // From this point onward, we expect the input to be a (#bits, #rot) pair
5385   if (Parser.getTok().isNot(AsmToken::Comma)) {
5386     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5387     return MatchOperand_ParseFail;
5388   }
5389 
5390   if (Imm1 & ~0xFF) {
5391     Error(Sx1, "immediate operand must a number in the range [0, 255]");
5392     return MatchOperand_ParseFail;
5393   }
5394 
5395   // Eat the comma
5396   Parser.Lex();
5397 
5398   // Repeat for #rot
5399   SMLoc Sx2, Ex2;
5400   Sx2 = Parser.getTok().getLoc();
5401 
5402   // Eat the optional hash (dollar)
5403   if (Parser.getTok().is(AsmToken::Hash) ||
5404       Parser.getTok().is(AsmToken::Dollar))
5405     Parser.Lex();
5406 
5407   const MCExpr *Imm2Exp;
5408   if (getParser().parseExpression(Imm2Exp, Ex2)) {
5409     Error(Sx2, "malformed expression");
5410     return MatchOperand_ParseFail;
5411   }
5412 
5413   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5414 
5415   if (CE) {
5416     Imm2 = CE->getValue();
5417     if (!(Imm2 & ~0x1E)) {
5418       // We have a match!
5419       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5420       return MatchOperand_Success;
5421     }
5422     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5423     return MatchOperand_ParseFail;
5424   } else {
5425     Error(Sx2, "constant expression expected");
5426     return MatchOperand_ParseFail;
5427   }
5428 }
5429 
5430 OperandMatchResultTy
5431 ARMAsmParser::parseBitfield(OperandVector &Operands) {
5432   MCAsmParser &Parser = getParser();
5433   SMLoc S = Parser.getTok().getLoc();
5434   // The bitfield descriptor is really two operands, the LSB and the width.
5435   if (Parser.getTok().isNot(AsmToken::Hash) &&
5436       Parser.getTok().isNot(AsmToken::Dollar)) {
5437     Error(Parser.getTok().getLoc(), "'#' expected");
5438     return MatchOperand_ParseFail;
5439   }
5440   Parser.Lex(); // Eat hash token.
5441 
5442   const MCExpr *LSBExpr;
5443   SMLoc E = Parser.getTok().getLoc();
5444   if (getParser().parseExpression(LSBExpr)) {
5445     Error(E, "malformed immediate expression");
5446     return MatchOperand_ParseFail;
5447   }
5448   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5449   if (!CE) {
5450     Error(E, "'lsb' operand must be an immediate");
5451     return MatchOperand_ParseFail;
5452   }
5453 
5454   int64_t LSB = CE->getValue();
5455   // The LSB must be in the range [0,31]
5456   if (LSB < 0 || LSB > 31) {
5457     Error(E, "'lsb' operand must be in the range [0,31]");
5458     return MatchOperand_ParseFail;
5459   }
5460   E = Parser.getTok().getLoc();
5461 
5462   // Expect another immediate operand.
5463   if (Parser.getTok().isNot(AsmToken::Comma)) {
5464     Error(Parser.getTok().getLoc(), "too few operands");
5465     return MatchOperand_ParseFail;
5466   }
5467   Parser.Lex(); // Eat hash token.
5468   if (Parser.getTok().isNot(AsmToken::Hash) &&
5469       Parser.getTok().isNot(AsmToken::Dollar)) {
5470     Error(Parser.getTok().getLoc(), "'#' expected");
5471     return MatchOperand_ParseFail;
5472   }
5473   Parser.Lex(); // Eat hash token.
5474 
5475   const MCExpr *WidthExpr;
5476   SMLoc EndLoc;
5477   if (getParser().parseExpression(WidthExpr, EndLoc)) {
5478     Error(E, "malformed immediate expression");
5479     return MatchOperand_ParseFail;
5480   }
5481   CE = dyn_cast<MCConstantExpr>(WidthExpr);
5482   if (!CE) {
5483     Error(E, "'width' operand must be an immediate");
5484     return MatchOperand_ParseFail;
5485   }
5486 
5487   int64_t Width = CE->getValue();
5488   // The LSB must be in the range [1,32-lsb]
5489   if (Width < 1 || Width > 32 - LSB) {
5490     Error(E, "'width' operand must be in the range [1,32-lsb]");
5491     return MatchOperand_ParseFail;
5492   }
5493 
5494   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
5495 
5496   return MatchOperand_Success;
5497 }
5498 
5499 OperandMatchResultTy
5500 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5501   // Check for a post-index addressing register operand. Specifically:
5502   // postidx_reg := '+' register {, shift}
5503   //              | '-' register {, shift}
5504   //              | register {, shift}
5505 
5506   // This method must return MatchOperand_NoMatch without consuming any tokens
5507   // in the case where there is no match, as other alternatives take other
5508   // parse methods.
5509   MCAsmParser &Parser = getParser();
5510   AsmToken Tok = Parser.getTok();
5511   SMLoc S = Tok.getLoc();
5512   bool haveEaten = false;
5513   bool isAdd = true;
5514   if (Tok.is(AsmToken::Plus)) {
5515     Parser.Lex(); // Eat the '+' token.
5516     haveEaten = true;
5517   } else if (Tok.is(AsmToken::Minus)) {
5518     Parser.Lex(); // Eat the '-' token.
5519     isAdd = false;
5520     haveEaten = true;
5521   }
5522 
5523   SMLoc E = Parser.getTok().getEndLoc();
5524   int Reg = tryParseRegister();
5525   if (Reg == -1) {
5526     if (!haveEaten)
5527       return MatchOperand_NoMatch;
5528     Error(Parser.getTok().getLoc(), "register expected");
5529     return MatchOperand_ParseFail;
5530   }
5531 
5532   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5533   unsigned ShiftImm = 0;
5534   if (Parser.getTok().is(AsmToken::Comma)) {
5535     Parser.Lex(); // Eat the ','.
5536     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5537       return MatchOperand_ParseFail;
5538 
5539     // FIXME: Only approximates end...may include intervening whitespace.
5540     E = Parser.getTok().getLoc();
5541   }
5542 
5543   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
5544                                                   ShiftImm, S, E));
5545 
5546   return MatchOperand_Success;
5547 }
5548 
5549 OperandMatchResultTy
5550 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5551   // Check for a post-index addressing register operand. Specifically:
5552   // am3offset := '+' register
5553   //              | '-' register
5554   //              | register
5555   //              | # imm
5556   //              | # + imm
5557   //              | # - imm
5558 
5559   // This method must return MatchOperand_NoMatch without consuming any tokens
5560   // in the case where there is no match, as other alternatives take other
5561   // parse methods.
5562   MCAsmParser &Parser = getParser();
5563   AsmToken Tok = Parser.getTok();
5564   SMLoc S = Tok.getLoc();
5565 
5566   // Do immediates first, as we always parse those if we have a '#'.
5567   if (Parser.getTok().is(AsmToken::Hash) ||
5568       Parser.getTok().is(AsmToken::Dollar)) {
5569     Parser.Lex(); // Eat '#' or '$'.
5570     // Explicitly look for a '-', as we need to encode negative zero
5571     // differently.
5572     bool isNegative = Parser.getTok().is(AsmToken::Minus);
5573     const MCExpr *Offset;
5574     SMLoc E;
5575     if (getParser().parseExpression(Offset, E))
5576       return MatchOperand_ParseFail;
5577     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5578     if (!CE) {
5579       Error(S, "constant expression expected");
5580       return MatchOperand_ParseFail;
5581     }
5582     // Negative zero is encoded as the flag value
5583     // std::numeric_limits<int32_t>::min().
5584     int32_t Val = CE->getValue();
5585     if (isNegative && Val == 0)
5586       Val = std::numeric_limits<int32_t>::min();
5587 
5588     Operands.push_back(
5589       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
5590 
5591     return MatchOperand_Success;
5592   }
5593 
5594   bool haveEaten = false;
5595   bool isAdd = true;
5596   if (Tok.is(AsmToken::Plus)) {
5597     Parser.Lex(); // Eat the '+' token.
5598     haveEaten = true;
5599   } else if (Tok.is(AsmToken::Minus)) {
5600     Parser.Lex(); // Eat the '-' token.
5601     isAdd = false;
5602     haveEaten = true;
5603   }
5604 
5605   Tok = Parser.getTok();
5606   int Reg = tryParseRegister();
5607   if (Reg == -1) {
5608     if (!haveEaten)
5609       return MatchOperand_NoMatch;
5610     Error(Tok.getLoc(), "register expected");
5611     return MatchOperand_ParseFail;
5612   }
5613 
5614   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5615                                                   0, S, Tok.getEndLoc()));
5616 
5617   return MatchOperand_Success;
5618 }
5619 
5620 /// Convert parsed operands to MCInst.  Needed here because this instruction
5621 /// only has two register operands, but multiplication is commutative so
5622 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5623 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5624                                     const OperandVector &Operands) {
5625   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
5626   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
5627   // If we have a three-operand form, make sure to set Rn to be the operand
5628   // that isn't the same as Rd.
5629   unsigned RegOp = 4;
5630   if (Operands.size() == 6 &&
5631       ((ARMOperand &)*Operands[4]).getReg() ==
5632           ((ARMOperand &)*Operands[3]).getReg())
5633     RegOp = 5;
5634   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5635   Inst.addOperand(Inst.getOperand(0));
5636   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5637 }
5638 
5639 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5640                                     const OperandVector &Operands) {
5641   int CondOp = -1, ImmOp = -1;
5642   switch(Inst.getOpcode()) {
5643     case ARM::tB:
5644     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
5645 
5646     case ARM::t2B:
5647     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5648 
5649     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
5650   }
5651   // first decide whether or not the branch should be conditional
5652   // by looking at it's location relative to an IT block
5653   if(inITBlock()) {
5654     // inside an IT block we cannot have any conditional branches. any
5655     // such instructions needs to be converted to unconditional form
5656     switch(Inst.getOpcode()) {
5657       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5658       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5659     }
5660   } else {
5661     // outside IT blocks we can only have unconditional branches with AL
5662     // condition code or conditional branches with non-AL condition code
5663     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5664     switch(Inst.getOpcode()) {
5665       case ARM::tB:
5666       case ARM::tBcc:
5667         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5668         break;
5669       case ARM::t2B:
5670       case ARM::t2Bcc:
5671         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5672         break;
5673     }
5674   }
5675 
5676   // now decide on encoding size based on branch target range
5677   switch(Inst.getOpcode()) {
5678     // classify tB as either t2B or t1B based on range of immediate operand
5679     case ARM::tB: {
5680       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5681       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5682         Inst.setOpcode(ARM::t2B);
5683       break;
5684     }
5685     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5686     case ARM::tBcc: {
5687       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5688       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5689         Inst.setOpcode(ARM::t2Bcc);
5690       break;
5691     }
5692   }
5693   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5694   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5695 }
5696 
5697 void ARMAsmParser::cvtMVEVMOVQtoDReg(
5698   MCInst &Inst, const OperandVector &Operands) {
5699 
5700   // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5701   assert(Operands.size() == 8);
5702 
5703   ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
5704   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
5705   ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
5706   ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
5707   // skip second copy of Qd in Operands[6]
5708   ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
5709   ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
5710 }
5711 
5712 /// Parse an ARM memory expression, return false if successful else return true
5713 /// or an error.  The first token must be a '[' when called.
5714 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5715   MCAsmParser &Parser = getParser();
5716   SMLoc S, E;
5717   if (Parser.getTok().isNot(AsmToken::LBrac))
5718     return TokError("Token is not a Left Bracket");
5719   S = Parser.getTok().getLoc();
5720   Parser.Lex(); // Eat left bracket token.
5721 
5722   const AsmToken &BaseRegTok = Parser.getTok();
5723   int BaseRegNum = tryParseRegister();
5724   if (BaseRegNum == -1)
5725     return Error(BaseRegTok.getLoc(), "register expected");
5726 
5727   // The next token must either be a comma, a colon or a closing bracket.
5728   const AsmToken &Tok = Parser.getTok();
5729   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5730       !Tok.is(AsmToken::RBrac))
5731     return Error(Tok.getLoc(), "malformed memory operand");
5732 
5733   if (Tok.is(AsmToken::RBrac)) {
5734     E = Tok.getEndLoc();
5735     Parser.Lex(); // Eat right bracket token.
5736 
5737     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5738                                              ARM_AM::no_shift, 0, 0, false,
5739                                              S, E));
5740 
5741     // If there's a pre-indexing writeback marker, '!', just add it as a token
5742     // operand. It's rather odd, but syntactically valid.
5743     if (Parser.getTok().is(AsmToken::Exclaim)) {
5744       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5745       Parser.Lex(); // Eat the '!'.
5746     }
5747 
5748     return false;
5749   }
5750 
5751   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5752          "Lost colon or comma in memory operand?!");
5753   if (Tok.is(AsmToken::Comma)) {
5754     Parser.Lex(); // Eat the comma.
5755   }
5756 
5757   // If we have a ':', it's an alignment specifier.
5758   if (Parser.getTok().is(AsmToken::Colon)) {
5759     Parser.Lex(); // Eat the ':'.
5760     E = Parser.getTok().getLoc();
5761     SMLoc AlignmentLoc = Tok.getLoc();
5762 
5763     const MCExpr *Expr;
5764     if (getParser().parseExpression(Expr))
5765      return true;
5766 
5767     // The expression has to be a constant. Memory references with relocations
5768     // don't come through here, as they use the <label> forms of the relevant
5769     // instructions.
5770     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5771     if (!CE)
5772       return Error (E, "constant expression expected");
5773 
5774     unsigned Align = 0;
5775     switch (CE->getValue()) {
5776     default:
5777       return Error(E,
5778                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5779     case 16:  Align = 2; break;
5780     case 32:  Align = 4; break;
5781     case 64:  Align = 8; break;
5782     case 128: Align = 16; break;
5783     case 256: Align = 32; break;
5784     }
5785 
5786     // Now we should have the closing ']'
5787     if (Parser.getTok().isNot(AsmToken::RBrac))
5788       return Error(Parser.getTok().getLoc(), "']' expected");
5789     E = Parser.getTok().getEndLoc();
5790     Parser.Lex(); // Eat right bracket token.
5791 
5792     // Don't worry about range checking the value here. That's handled by
5793     // the is*() predicates.
5794     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5795                                              ARM_AM::no_shift, 0, Align,
5796                                              false, S, E, AlignmentLoc));
5797 
5798     // If there's a pre-indexing writeback marker, '!', just add it as a token
5799     // operand.
5800     if (Parser.getTok().is(AsmToken::Exclaim)) {
5801       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5802       Parser.Lex(); // Eat the '!'.
5803     }
5804 
5805     return false;
5806   }
5807 
5808   // If we have a '#' or '$', it's an immediate offset, else assume it's a
5809   // register offset. Be friendly and also accept a plain integer or expression
5810   // (without a leading hash) for gas compatibility.
5811   if (Parser.getTok().is(AsmToken::Hash) ||
5812       Parser.getTok().is(AsmToken::Dollar) ||
5813       Parser.getTok().is(AsmToken::LParen) ||
5814       Parser.getTok().is(AsmToken::Integer)) {
5815     if (Parser.getTok().is(AsmToken::Hash) ||
5816         Parser.getTok().is(AsmToken::Dollar))
5817       Parser.Lex(); // Eat '#' or '$'
5818     E = Parser.getTok().getLoc();
5819 
5820     bool isNegative = getParser().getTok().is(AsmToken::Minus);
5821     const MCExpr *Offset;
5822     if (getParser().parseExpression(Offset))
5823      return true;
5824 
5825     // The expression has to be a constant. Memory references with relocations
5826     // don't come through here, as they use the <label> forms of the relevant
5827     // instructions.
5828     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5829     if (!CE)
5830       return Error (E, "constant expression expected");
5831 
5832     // If the constant was #-0, represent it as
5833     // std::numeric_limits<int32_t>::min().
5834     int32_t Val = CE->getValue();
5835     if (isNegative && Val == 0)
5836       CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5837                                   getContext());
5838 
5839     // Now we should have the closing ']'
5840     if (Parser.getTok().isNot(AsmToken::RBrac))
5841       return Error(Parser.getTok().getLoc(), "']' expected");
5842     E = Parser.getTok().getEndLoc();
5843     Parser.Lex(); // Eat right bracket token.
5844 
5845     // Don't worry about range checking the value here. That's handled by
5846     // the is*() predicates.
5847     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5848                                              ARM_AM::no_shift, 0, 0,
5849                                              false, S, E));
5850 
5851     // If there's a pre-indexing writeback marker, '!', just add it as a token
5852     // operand.
5853     if (Parser.getTok().is(AsmToken::Exclaim)) {
5854       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5855       Parser.Lex(); // Eat the '!'.
5856     }
5857 
5858     return false;
5859   }
5860 
5861   // The register offset is optionally preceded by a '+' or '-'
5862   bool isNegative = false;
5863   if (Parser.getTok().is(AsmToken::Minus)) {
5864     isNegative = true;
5865     Parser.Lex(); // Eat the '-'.
5866   } else if (Parser.getTok().is(AsmToken::Plus)) {
5867     // Nothing to do.
5868     Parser.Lex(); // Eat the '+'.
5869   }
5870 
5871   E = Parser.getTok().getLoc();
5872   int OffsetRegNum = tryParseRegister();
5873   if (OffsetRegNum == -1)
5874     return Error(E, "register expected");
5875 
5876   // If there's a shift operator, handle it.
5877   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5878   unsigned ShiftImm = 0;
5879   if (Parser.getTok().is(AsmToken::Comma)) {
5880     Parser.Lex(); // Eat the ','.
5881     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5882       return true;
5883   }
5884 
5885   // Now we should have the closing ']'
5886   if (Parser.getTok().isNot(AsmToken::RBrac))
5887     return Error(Parser.getTok().getLoc(), "']' expected");
5888   E = Parser.getTok().getEndLoc();
5889   Parser.Lex(); // Eat right bracket token.
5890 
5891   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5892                                            ShiftType, ShiftImm, 0, isNegative,
5893                                            S, E));
5894 
5895   // If there's a pre-indexing writeback marker, '!', just add it as a token
5896   // operand.
5897   if (Parser.getTok().is(AsmToken::Exclaim)) {
5898     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5899     Parser.Lex(); // Eat the '!'.
5900   }
5901 
5902   return false;
5903 }
5904 
5905 /// parseMemRegOffsetShift - one of these two:
5906 ///   ( lsl | lsr | asr | ror ) , # shift_amount
5907 ///   rrx
5908 /// return true if it parses a shift otherwise it returns false.
5909 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5910                                           unsigned &Amount) {
5911   MCAsmParser &Parser = getParser();
5912   SMLoc Loc = Parser.getTok().getLoc();
5913   const AsmToken &Tok = Parser.getTok();
5914   if (Tok.isNot(AsmToken::Identifier))
5915     return Error(Loc, "illegal shift operator");
5916   StringRef ShiftName = Tok.getString();
5917   if (ShiftName == "lsl" || ShiftName == "LSL" ||
5918       ShiftName == "asl" || ShiftName == "ASL")
5919     St = ARM_AM::lsl;
5920   else if (ShiftName == "lsr" || ShiftName == "LSR")
5921     St = ARM_AM::lsr;
5922   else if (ShiftName == "asr" || ShiftName == "ASR")
5923     St = ARM_AM::asr;
5924   else if (ShiftName == "ror" || ShiftName == "ROR")
5925     St = ARM_AM::ror;
5926   else if (ShiftName == "rrx" || ShiftName == "RRX")
5927     St = ARM_AM::rrx;
5928   else if (ShiftName == "uxtw" || ShiftName == "UXTW")
5929     St = ARM_AM::uxtw;
5930   else
5931     return Error(Loc, "illegal shift operator");
5932   Parser.Lex(); // Eat shift type token.
5933 
5934   // rrx stands alone.
5935   Amount = 0;
5936   if (St != ARM_AM::rrx) {
5937     Loc = Parser.getTok().getLoc();
5938     // A '#' and a shift amount.
5939     const AsmToken &HashTok = Parser.getTok();
5940     if (HashTok.isNot(AsmToken::Hash) &&
5941         HashTok.isNot(AsmToken::Dollar))
5942       return Error(HashTok.getLoc(), "'#' expected");
5943     Parser.Lex(); // Eat hash token.
5944 
5945     const MCExpr *Expr;
5946     if (getParser().parseExpression(Expr))
5947       return true;
5948     // Range check the immediate.
5949     // lsl, ror: 0 <= imm <= 31
5950     // lsr, asr: 0 <= imm <= 32
5951     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5952     if (!CE)
5953       return Error(Loc, "shift amount must be an immediate");
5954     int64_t Imm = CE->getValue();
5955     if (Imm < 0 ||
5956         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5957         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5958       return Error(Loc, "immediate shift value out of range");
5959     // If <ShiftTy> #0, turn it into a no_shift.
5960     if (Imm == 0)
5961       St = ARM_AM::lsl;
5962     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5963     if (Imm == 32)
5964       Imm = 0;
5965     Amount = Imm;
5966   }
5967 
5968   return false;
5969 }
5970 
5971 /// parseFPImm - A floating point immediate expression operand.
5972 OperandMatchResultTy
5973 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5974   MCAsmParser &Parser = getParser();
5975   // Anything that can accept a floating point constant as an operand
5976   // needs to go through here, as the regular parseExpression is
5977   // integer only.
5978   //
5979   // This routine still creates a generic Immediate operand, containing
5980   // a bitcast of the 64-bit floating point value. The various operands
5981   // that accept floats can check whether the value is valid for them
5982   // via the standard is*() predicates.
5983 
5984   SMLoc S = Parser.getTok().getLoc();
5985 
5986   if (Parser.getTok().isNot(AsmToken::Hash) &&
5987       Parser.getTok().isNot(AsmToken::Dollar))
5988     return MatchOperand_NoMatch;
5989 
5990   // Disambiguate the VMOV forms that can accept an FP immediate.
5991   // vmov.f32 <sreg>, #imm
5992   // vmov.f64 <dreg>, #imm
5993   // vmov.f32 <dreg>, #imm  @ vector f32x2
5994   // vmov.f32 <qreg>, #imm  @ vector f32x4
5995   //
5996   // There are also the NEON VMOV instructions which expect an
5997   // integer constant. Make sure we don't try to parse an FPImm
5998   // for these:
5999   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
6000   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
6001   bool isVmovf = TyOp.isToken() &&
6002                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
6003                   TyOp.getToken() == ".f16");
6004   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
6005   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
6006                                          Mnemonic.getToken() == "fconsts");
6007   if (!(isVmovf || isFconst))
6008     return MatchOperand_NoMatch;
6009 
6010   Parser.Lex(); // Eat '#' or '$'.
6011 
6012   // Handle negation, as that still comes through as a separate token.
6013   bool isNegative = false;
6014   if (Parser.getTok().is(AsmToken::Minus)) {
6015     isNegative = true;
6016     Parser.Lex();
6017   }
6018   const AsmToken &Tok = Parser.getTok();
6019   SMLoc Loc = Tok.getLoc();
6020   if (Tok.is(AsmToken::Real) && isVmovf) {
6021     APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
6022     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
6023     // If we had a '-' in front, toggle the sign bit.
6024     IntVal ^= (uint64_t)isNegative << 31;
6025     Parser.Lex(); // Eat the token.
6026     Operands.push_back(ARMOperand::CreateImm(
6027           MCConstantExpr::create(IntVal, getContext()),
6028           S, Parser.getTok().getLoc()));
6029     return MatchOperand_Success;
6030   }
6031   // Also handle plain integers. Instructions which allow floating point
6032   // immediates also allow a raw encoded 8-bit value.
6033   if (Tok.is(AsmToken::Integer) && isFconst) {
6034     int64_t Val = Tok.getIntVal();
6035     Parser.Lex(); // Eat the token.
6036     if (Val > 255 || Val < 0) {
6037       Error(Loc, "encoded floating point value out of range");
6038       return MatchOperand_ParseFail;
6039     }
6040     float RealVal = ARM_AM::getFPImmFloat(Val);
6041     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
6042 
6043     Operands.push_back(ARMOperand::CreateImm(
6044         MCConstantExpr::create(Val, getContext()), S,
6045         Parser.getTok().getLoc()));
6046     return MatchOperand_Success;
6047   }
6048 
6049   Error(Loc, "invalid floating point immediate");
6050   return MatchOperand_ParseFail;
6051 }
6052 
6053 /// Parse a arm instruction operand.  For now this parses the operand regardless
6054 /// of the mnemonic.
6055 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
6056   MCAsmParser &Parser = getParser();
6057   SMLoc S, E;
6058 
6059   // Check if the current operand has a custom associated parser, if so, try to
6060   // custom parse the operand, or fallback to the general approach.
6061   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
6062   if (ResTy == MatchOperand_Success)
6063     return false;
6064   // If there wasn't a custom match, try the generic matcher below. Otherwise,
6065   // there was a match, but an error occurred, in which case, just return that
6066   // the operand parsing failed.
6067   if (ResTy == MatchOperand_ParseFail)
6068     return true;
6069 
6070   switch (getLexer().getKind()) {
6071   default:
6072     Error(Parser.getTok().getLoc(), "unexpected token in operand");
6073     return true;
6074   case AsmToken::Identifier: {
6075     // If we've seen a branch mnemonic, the next operand must be a label.  This
6076     // is true even if the label is a register name.  So "br r1" means branch to
6077     // label "r1".
6078     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
6079     if (!ExpectLabel) {
6080       if (!tryParseRegisterWithWriteBack(Operands))
6081         return false;
6082       int Res = tryParseShiftRegister(Operands);
6083       if (Res == 0) // success
6084         return false;
6085       else if (Res == -1) // irrecoverable error
6086         return true;
6087       // If this is VMRS, check for the apsr_nzcv operand.
6088       if (Mnemonic == "vmrs" &&
6089           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
6090         S = Parser.getTok().getLoc();
6091         Parser.Lex();
6092         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
6093         return false;
6094       }
6095     }
6096 
6097     // Fall though for the Identifier case that is not a register or a
6098     // special name.
6099     LLVM_FALLTHROUGH;
6100   }
6101   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
6102   case AsmToken::Integer: // things like 1f and 2b as a branch targets
6103   case AsmToken::String:  // quoted label names.
6104   case AsmToken::Dot: {   // . as a branch target
6105     // This was not a register so parse other operands that start with an
6106     // identifier (like labels) as expressions and create them as immediates.
6107     const MCExpr *IdVal;
6108     S = Parser.getTok().getLoc();
6109     if (getParser().parseExpression(IdVal))
6110       return true;
6111     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6112     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
6113     return false;
6114   }
6115   case AsmToken::LBrac:
6116     return parseMemory(Operands);
6117   case AsmToken::LCurly:
6118     return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
6119   case AsmToken::Dollar:
6120   case AsmToken::Hash: {
6121     // #42 -> immediate
6122     // $ 42 -> immediate
6123     // $foo -> symbol name
6124     // $42 -> symbol name
6125     S = Parser.getTok().getLoc();
6126 
6127     // Favor the interpretation of $-prefixed operands as symbol names.
6128     // Cases where immediates are explicitly expected are handled by their
6129     // specific ParseMethod implementations.
6130     auto AdjacentToken = getLexer().peekTok(/*ShouldSkipSpace=*/false);
6131     bool ExpectIdentifier = Parser.getTok().is(AsmToken::Dollar) &&
6132                             (AdjacentToken.is(AsmToken::Identifier) ||
6133                              AdjacentToken.is(AsmToken::Integer));
6134     if (!ExpectIdentifier) {
6135       // Token is not part of identifier. Drop leading $ or # before parsing
6136       // expression.
6137       Parser.Lex();
6138     }
6139 
6140     if (Parser.getTok().isNot(AsmToken::Colon)) {
6141       bool IsNegative = Parser.getTok().is(AsmToken::Minus);
6142       const MCExpr *ImmVal;
6143       if (getParser().parseExpression(ImmVal))
6144         return true;
6145       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
6146       if (CE) {
6147         int32_t Val = CE->getValue();
6148         if (IsNegative && Val == 0)
6149           ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
6150                                           getContext());
6151       }
6152       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6153       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
6154 
6155       // There can be a trailing '!' on operands that we want as a separate
6156       // '!' Token operand. Handle that here. For example, the compatibility
6157       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
6158       if (Parser.getTok().is(AsmToken::Exclaim)) {
6159         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
6160                                                    Parser.getTok().getLoc()));
6161         Parser.Lex(); // Eat exclaim token
6162       }
6163       return false;
6164     }
6165     // w/ a ':' after the '#', it's just like a plain ':'.
6166     LLVM_FALLTHROUGH;
6167   }
6168   case AsmToken::Colon: {
6169     S = Parser.getTok().getLoc();
6170     // ":lower16:" and ":upper16:" expression prefixes
6171     // FIXME: Check it's an expression prefix,
6172     // e.g. (FOO - :lower16:BAR) isn't legal.
6173     ARMMCExpr::VariantKind RefKind;
6174     if (parsePrefix(RefKind))
6175       return true;
6176 
6177     const MCExpr *SubExprVal;
6178     if (getParser().parseExpression(SubExprVal))
6179       return true;
6180 
6181     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
6182                                               getContext());
6183     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6184     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
6185     return false;
6186   }
6187   case AsmToken::Equal: {
6188     S = Parser.getTok().getLoc();
6189     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
6190       return Error(S, "unexpected token in operand");
6191     Parser.Lex(); // Eat '='
6192     const MCExpr *SubExprVal;
6193     if (getParser().parseExpression(SubExprVal))
6194       return true;
6195     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6196 
6197     // execute-only: we assume that assembly programmers know what they are
6198     // doing and allow literal pool creation here
6199     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
6200     return false;
6201   }
6202   }
6203 }
6204 
6205 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
6206 //  :lower16: and :upper16:.
6207 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
6208   MCAsmParser &Parser = getParser();
6209   RefKind = ARMMCExpr::VK_ARM_None;
6210 
6211   // consume an optional '#' (GNU compatibility)
6212   if (getLexer().is(AsmToken::Hash))
6213     Parser.Lex();
6214 
6215   // :lower16: and :upper16: modifiers
6216   assert(getLexer().is(AsmToken::Colon) && "expected a :");
6217   Parser.Lex(); // Eat ':'
6218 
6219   if (getLexer().isNot(AsmToken::Identifier)) {
6220     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
6221     return true;
6222   }
6223 
6224   enum {
6225     COFF = (1 << MCObjectFileInfo::IsCOFF),
6226     ELF = (1 << MCObjectFileInfo::IsELF),
6227     MACHO = (1 << MCObjectFileInfo::IsMachO),
6228     WASM = (1 << MCObjectFileInfo::IsWasm),
6229   };
6230   static const struct PrefixEntry {
6231     const char *Spelling;
6232     ARMMCExpr::VariantKind VariantKind;
6233     uint8_t SupportedFormats;
6234   } PrefixEntries[] = {
6235     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
6236     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
6237   };
6238 
6239   StringRef IDVal = Parser.getTok().getIdentifier();
6240 
6241   const auto &Prefix =
6242       llvm::find_if(PrefixEntries, [&IDVal](const PrefixEntry &PE) {
6243         return PE.Spelling == IDVal;
6244       });
6245   if (Prefix == std::end(PrefixEntries)) {
6246     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
6247     return true;
6248   }
6249 
6250   uint8_t CurrentFormat;
6251   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
6252   case MCObjectFileInfo::IsMachO:
6253     CurrentFormat = MACHO;
6254     break;
6255   case MCObjectFileInfo::IsELF:
6256     CurrentFormat = ELF;
6257     break;
6258   case MCObjectFileInfo::IsCOFF:
6259     CurrentFormat = COFF;
6260     break;
6261   case MCObjectFileInfo::IsWasm:
6262     CurrentFormat = WASM;
6263     break;
6264   case MCObjectFileInfo::IsXCOFF:
6265     llvm_unreachable("unexpected object format");
6266     break;
6267   }
6268 
6269   if (~Prefix->SupportedFormats & CurrentFormat) {
6270     Error(Parser.getTok().getLoc(),
6271           "cannot represent relocation in the current file format");
6272     return true;
6273   }
6274 
6275   RefKind = Prefix->VariantKind;
6276   Parser.Lex();
6277 
6278   if (getLexer().isNot(AsmToken::Colon)) {
6279     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
6280     return true;
6281   }
6282   Parser.Lex(); // Eat the last ':'
6283 
6284   return false;
6285 }
6286 
6287 /// Given a mnemonic, split out possible predication code and carry
6288 /// setting letters to form a canonical mnemonic and flags.
6289 //
6290 // FIXME: Would be nice to autogen this.
6291 // FIXME: This is a bit of a maze of special cases.
6292 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
6293                                       StringRef ExtraToken,
6294                                       unsigned &PredicationCode,
6295                                       unsigned &VPTPredicationCode,
6296                                       bool &CarrySetting,
6297                                       unsigned &ProcessorIMod,
6298                                       StringRef &ITMask) {
6299   PredicationCode = ARMCC::AL;
6300   VPTPredicationCode = ARMVCC::None;
6301   CarrySetting = false;
6302   ProcessorIMod = 0;
6303 
6304   // Ignore some mnemonics we know aren't predicated forms.
6305   //
6306   // FIXME: Would be nice to autogen this.
6307   if ((Mnemonic == "movs" && isThumb()) ||
6308       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
6309       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
6310       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
6311       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
6312       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
6313       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
6314       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
6315       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
6316       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
6317       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
6318       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
6319       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
6320       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
6321       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
6322       Mnemonic == "vdot"  || Mnemonic == "vmmla"  ||
6323       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6324       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6325       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6326       Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6327       Mnemonic == "csel" || Mnemonic == "csinc" ||
6328       Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6329       Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6330       Mnemonic == "csetm")
6331     return Mnemonic;
6332 
6333   // First, split out any predication code. Ignore mnemonics we know aren't
6334   // predicated but do have a carry-set and so weren't caught above.
6335   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
6336       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
6337       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
6338       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
6339       !(hasMVE() &&
6340         (Mnemonic == "vmine" ||
6341          Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
6342          Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
6343          Mnemonic == "vmvne" || Mnemonic == "vorne" ||
6344          Mnemonic == "vnege" || Mnemonic == "vnegt" ||
6345          Mnemonic == "vmule" || Mnemonic == "vmult" ||
6346          Mnemonic == "vrintne" ||
6347          Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6348          Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
6349          Mnemonic.startswith("vq")))) {
6350     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
6351     if (CC != ~0U) {
6352       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6353       PredicationCode = CC;
6354     }
6355   }
6356 
6357   // Next, determine if we have a carry setting bit. We explicitly ignore all
6358   // the instructions we know end in 's'.
6359   if (Mnemonic.endswith("s") &&
6360       !(Mnemonic == "cps" || Mnemonic == "mls" ||
6361         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
6362         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
6363         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
6364         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
6365         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
6366         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
6367         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
6368         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
6369         Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6370         Mnemonic == "vmlas" ||
6371         (Mnemonic == "movs" && isThumb()))) {
6372     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6373     CarrySetting = true;
6374   }
6375 
6376   // The "cps" instruction can have a interrupt mode operand which is glued into
6377   // the mnemonic. Check if this is the case, split it and parse the imod op
6378   if (Mnemonic.startswith("cps")) {
6379     // Split out any imod code.
6380     unsigned IMod =
6381       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
6382       .Case("ie", ARM_PROC::IE)
6383       .Case("id", ARM_PROC::ID)
6384       .Default(~0U);
6385     if (IMod != ~0U) {
6386       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6387       ProcessorIMod = IMod;
6388     }
6389   }
6390 
6391   if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
6392       Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
6393       Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6394       Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6395       Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6396       Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6397       Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6398     unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
6399     if (CC != ~0U) {
6400       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6401       VPTPredicationCode = CC;
6402     }
6403     return Mnemonic;
6404   }
6405 
6406   // The "it" instruction has the condition mask on the end of the mnemonic.
6407   if (Mnemonic.startswith("it")) {
6408     ITMask = Mnemonic.slice(2, Mnemonic.size());
6409     Mnemonic = Mnemonic.slice(0, 2);
6410   }
6411 
6412   if (Mnemonic.startswith("vpst")) {
6413     ITMask = Mnemonic.slice(4, Mnemonic.size());
6414     Mnemonic = Mnemonic.slice(0, 4);
6415   }
6416   else if (Mnemonic.startswith("vpt")) {
6417     ITMask = Mnemonic.slice(3, Mnemonic.size());
6418     Mnemonic = Mnemonic.slice(0, 3);
6419   }
6420 
6421   return Mnemonic;
6422 }
6423 
6424 /// Given a canonical mnemonic, determine if the instruction ever allows
6425 /// inclusion of carry set or predication code operands.
6426 //
6427 // FIXME: It would be nice to autogen this.
6428 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
6429                                          StringRef ExtraToken,
6430                                          StringRef FullInst,
6431                                          bool &CanAcceptCarrySet,
6432                                          bool &CanAcceptPredicationCode,
6433                                          bool &CanAcceptVPTPredicationCode) {
6434   CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
6435 
6436   CanAcceptCarrySet =
6437       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6438       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
6439       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
6440       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
6441       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
6442       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
6443       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
6444       (!isThumb() &&
6445        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
6446         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
6447 
6448   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
6449       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
6450       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
6451       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
6452       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
6453       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
6454       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
6455       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
6456       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
6457       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
6458       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
6459       Mnemonic == "vmovx" || Mnemonic == "vins" ||
6460       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6461       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6462       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6463       Mnemonic == "vfmat" || Mnemonic == "vfmab" ||
6464       Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
6465       Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
6466       Mnemonic == "pssbb" || Mnemonic == "vsmmla" ||
6467       Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
6468       Mnemonic == "vusdot" || Mnemonic == "vsudot" ||
6469       Mnemonic == "bfcsel" || Mnemonic == "wls" ||
6470       Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
6471       Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
6472       Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
6473       Mnemonic == "cset" || Mnemonic == "csetm" ||
6474       Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6475       (hasCDE() && MS.isCDEInstr(Mnemonic) &&
6476        !MS.isITPredicableCDEInstr(Mnemonic)) ||
6477       (hasMVE() &&
6478        (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6479         Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6480         Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6481         Mnemonic.startswith("letp")))) {
6482     // These mnemonics are never predicable
6483     CanAcceptPredicationCode = false;
6484   } else if (!isThumb()) {
6485     // Some instructions are only predicable in Thumb mode
6486     CanAcceptPredicationCode =
6487         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
6488         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
6489         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
6490         Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
6491         Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
6492         Mnemonic != "stc2" && Mnemonic != "stc2l" &&
6493         Mnemonic != "tsb" &&
6494         !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
6495   } else if (isThumbOne()) {
6496     if (hasV6MOps())
6497       CanAcceptPredicationCode = Mnemonic != "movs";
6498     else
6499       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
6500   } else
6501     CanAcceptPredicationCode = true;
6502 }
6503 
6504 // Some Thumb instructions have two operand forms that are not
6505 // available as three operand, convert to two operand form if possible.
6506 //
6507 // FIXME: We would really like to be able to tablegen'erate this.
6508 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
6509                                                  bool CarrySetting,
6510                                                  OperandVector &Operands) {
6511   if (Operands.size() != 6)
6512     return;
6513 
6514   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6515         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6516   if (!Op3.isReg() || !Op4.isReg())
6517     return;
6518 
6519   auto Op3Reg = Op3.getReg();
6520   auto Op4Reg = Op4.getReg();
6521 
6522   // For most Thumb2 cases we just generate the 3 operand form and reduce
6523   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
6524   // won't accept SP or PC so we do the transformation here taking care
6525   // with immediate range in the 'add sp, sp #imm' case.
6526   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6527   if (isThumbTwo()) {
6528     if (Mnemonic != "add")
6529       return;
6530     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
6531                         (Op5.isReg() && Op5.getReg() == ARM::PC);
6532     if (!TryTransform) {
6533       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6534                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6535                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6536                        Op5.isImm() && !Op5.isImm0_508s4());
6537     }
6538     if (!TryTransform)
6539       return;
6540   } else if (!isThumbOne())
6541     return;
6542 
6543   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
6544         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6545         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
6546         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
6547     return;
6548 
6549   // If first 2 operands of a 3 operand instruction are the same
6550   // then transform to 2 operand version of the same instruction
6551   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
6552   bool Transform = Op3Reg == Op4Reg;
6553 
6554   // For communtative operations, we might be able to transform if we swap
6555   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
6556   // as tADDrsp.
6557   const ARMOperand *LastOp = &Op5;
6558   bool Swap = false;
6559   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6560       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6561        Mnemonic == "and" || Mnemonic == "eor" ||
6562        Mnemonic == "adc" || Mnemonic == "orr")) {
6563     Swap = true;
6564     LastOp = &Op4;
6565     Transform = true;
6566   }
6567 
6568   // If both registers are the same then remove one of them from
6569   // the operand list, with certain exceptions.
6570   if (Transform) {
6571     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
6572     // 2 operand forms don't exist.
6573     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
6574         LastOp->isReg())
6575       Transform = false;
6576 
6577     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
6578     // 3-bits because the ARMARM says not to.
6579     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
6580       Transform = false;
6581   }
6582 
6583   if (Transform) {
6584     if (Swap)
6585       std::swap(Op4, Op5);
6586     Operands.erase(Operands.begin() + 3);
6587   }
6588 }
6589 
6590 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6591                                           OperandVector &Operands) {
6592   // FIXME: This is all horribly hacky. We really need a better way to deal
6593   // with optional operands like this in the matcher table.
6594 
6595   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
6596   // another does not. Specifically, the MOVW instruction does not. So we
6597   // special case it here and remove the defaulted (non-setting) cc_out
6598   // operand if that's the instruction we're trying to match.
6599   //
6600   // We do this as post-processing of the explicit operands rather than just
6601   // conditionally adding the cc_out in the first place because we need
6602   // to check the type of the parsed immediate operand.
6603   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
6604       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
6605       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
6606       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6607     return true;
6608 
6609   // Register-register 'add' for thumb does not have a cc_out operand
6610   // when there are only two register operands.
6611   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
6612       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6613       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6614       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6615     return true;
6616   // Register-register 'add' for thumb does not have a cc_out operand
6617   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
6618   // have to check the immediate range here since Thumb2 has a variant
6619   // that can handle a different range and has a cc_out operand.
6620   if (((isThumb() && Mnemonic == "add") ||
6621        (isThumbTwo() && Mnemonic == "sub")) &&
6622       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6623       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6624       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6625       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6626       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6627        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
6628     return true;
6629   // For Thumb2, add/sub immediate does not have a cc_out operand for the
6630   // imm0_4095 variant. That's the least-preferred variant when
6631   // selecting via the generic "add" mnemonic, so to know that we
6632   // should remove the cc_out operand, we have to explicitly check that
6633   // it's not one of the other variants. Ugh.
6634   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6635       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6636       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6637       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6638     // Nest conditions rather than one big 'if' statement for readability.
6639     //
6640     // If both registers are low, we're in an IT block, and the immediate is
6641     // in range, we should use encoding T1 instead, which has a cc_out.
6642     if (inITBlock() &&
6643         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
6644         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
6645         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
6646       return false;
6647     // Check against T3. If the second register is the PC, this is an
6648     // alternate form of ADR, which uses encoding T4, so check for that too.
6649     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
6650         (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() ||
6651          static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg()))
6652       return false;
6653 
6654     // Otherwise, we use encoding T4, which does not have a cc_out
6655     // operand.
6656     return true;
6657   }
6658 
6659   // The thumb2 multiply instruction doesn't have a CCOut register, so
6660   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
6661   // use the 16-bit encoding or not.
6662   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
6663       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6664       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6665       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6666       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6667       // If the registers aren't low regs, the destination reg isn't the
6668       // same as one of the source regs, or the cc_out operand is zero
6669       // outside of an IT block, we have to use the 32-bit encoding, so
6670       // remove the cc_out operand.
6671       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6672        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6673        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
6674        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6675                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
6676                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6677                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
6678     return true;
6679 
6680   // Also check the 'mul' syntax variant that doesn't specify an explicit
6681   // destination register.
6682   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
6683       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6684       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6685       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6686       // If the registers aren't low regs  or the cc_out operand is zero
6687       // outside of an IT block, we have to use the 32-bit encoding, so
6688       // remove the cc_out operand.
6689       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6690        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6691        !inITBlock()))
6692     return true;
6693 
6694   // Register-register 'add/sub' for thumb does not have a cc_out operand
6695   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
6696   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6697   // right, this will result in better diagnostics (which operand is off)
6698   // anyway.
6699   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
6700       (Operands.size() == 5 || Operands.size() == 6) &&
6701       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6702       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6703       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6704       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
6705        (Operands.size() == 6 &&
6706         static_cast<ARMOperand &>(*Operands[5]).isImm()))) {
6707     // Thumb2 (add|sub){s}{p}.w GPRnopc, sp, #{T2SOImm} has cc_out
6708     return (!(isThumbTwo() &&
6709               (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() ||
6710                static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg())));
6711   }
6712   // Fixme: Should join all the thumb+thumb2 (add|sub) in a single if case
6713   // Thumb2 ADD r0, #4095 -> ADDW r0, r0, #4095 (T4)
6714   // Thumb2 SUB r0, #4095 -> SUBW r0, r0, #4095
6715   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6716       (Operands.size() == 5) &&
6717       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6718       static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP &&
6719       static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC &&
6720       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6721       static_cast<ARMOperand &>(*Operands[4]).isImm()) {
6722     const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]);
6723     if (IMM.isT2SOImm() || IMM.isT2SOImmNeg())
6724       return false; // add.w / sub.w
6725     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IMM.getImm())) {
6726       const int64_t Value = CE->getValue();
6727       // Thumb1 imm8 sub / add
6728       if ((Value < ((1 << 7) - 1) << 2) && inITBlock() && (!(Value & 3)) &&
6729           isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()))
6730         return false;
6731       return true; // Thumb2 T4 addw / subw
6732     }
6733   }
6734   return false;
6735 }
6736 
6737 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
6738                                               OperandVector &Operands) {
6739   // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
6740   unsigned RegIdx = 3;
6741   if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6742       Mnemonic == "vrintr") &&
6743       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
6744        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
6745     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6746         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
6747          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
6748       RegIdx = 4;
6749 
6750     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6751         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6752              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6753          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6754              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
6755       return true;
6756   }
6757   return false;
6758 }
6759 
6760 bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
6761                                                     OperandVector &Operands) {
6762   if (!hasMVE() || Operands.size() < 3)
6763     return true;
6764 
6765   if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6766       Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
6767     return true;
6768 
6769   if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
6770     return false;
6771 
6772   if (Mnemonic.startswith("vmov") &&
6773       !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6774         Mnemonic.startswith("vmovx"))) {
6775     for (auto &Operand : Operands) {
6776       if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6777           ((*Operand).isReg() &&
6778            (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6779              (*Operand).getReg()) ||
6780             ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6781               (*Operand).getReg())))) {
6782         return true;
6783       }
6784     }
6785     return false;
6786   } else {
6787     for (auto &Operand : Operands) {
6788       // We check the larger class QPR instead of just the legal class
6789       // MQPR, to more accurately report errors when using Q registers
6790       // outside of the allowed range.
6791       if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6792           (Operand->isReg() &&
6793            (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6794              Operand->getReg()))))
6795         return false;
6796     }
6797     return true;
6798   }
6799 }
6800 
6801 static bool isDataTypeToken(StringRef Tok) {
6802   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
6803     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
6804     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6805     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6806     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6807     Tok == ".f" || Tok == ".d";
6808 }
6809 
6810 // FIXME: This bit should probably be handled via an explicit match class
6811 // in the .td files that matches the suffix instead of having it be
6812 // a literal string token the way it is now.
6813 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6814   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6815 }
6816 
6817 static void applyMnemonicAliases(StringRef &Mnemonic,
6818                                  const FeatureBitset &Features,
6819                                  unsigned VariantID);
6820 
6821 // The GNU assembler has aliases of ldrd and strd with the second register
6822 // omitted. We don't have a way to do that in tablegen, so fix it up here.
6823 //
6824 // We have to be careful to not emit an invalid Rt2 here, because the rest of
6825 // the assembly parser could then generate confusing diagnostics refering to
6826 // it. If we do find anything that prevents us from doing the transformation we
6827 // bail out, and let the assembly parser report an error on the instruction as
6828 // it is written.
6829 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6830                                      OperandVector &Operands) {
6831   if (Mnemonic != "ldrd" && Mnemonic != "strd")
6832     return;
6833   if (Operands.size() < 4)
6834     return;
6835 
6836   ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6837   ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6838 
6839   if (!Op2.isReg())
6840     return;
6841   if (!Op3.isGPRMem())
6842     return;
6843 
6844   const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6845   if (!GPR.contains(Op2.getReg()))
6846     return;
6847 
6848   unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6849   if (!isThumb() && (RtEncoding & 1)) {
6850     // In ARM mode, the registers must be from an aligned pair, this
6851     // restriction does not apply in Thumb mode.
6852     return;
6853   }
6854   if (Op2.getReg() == ARM::PC)
6855     return;
6856   unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6857   if (!PairedReg || PairedReg == ARM::PC ||
6858       (PairedReg == ARM::SP && !hasV8Ops()))
6859     return;
6860 
6861   Operands.insert(
6862       Operands.begin() + 3,
6863       ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6864 }
6865 
6866 // Dual-register instruction have the following syntax:
6867 // <mnemonic> <predicate>? <coproc>, <Rdest>, <Rdest+1>, <Rsrc>, ..., #imm
6868 // This function tries to remove <Rdest+1> and replace <Rdest> with a pair
6869 // operand. If the conversion fails an error is diagnosed, and the function
6870 // returns true.
6871 bool ARMAsmParser::CDEConvertDualRegOperand(StringRef Mnemonic,
6872                                             OperandVector &Operands) {
6873   assert(MS.isCDEDualRegInstr(Mnemonic));
6874   bool isPredicable =
6875       Mnemonic == "cx1da" || Mnemonic == "cx2da" || Mnemonic == "cx3da";
6876   size_t NumPredOps = isPredicable ? 1 : 0;
6877 
6878   if (Operands.size() <= 3 + NumPredOps)
6879     return false;
6880 
6881   StringRef Op2Diag(
6882       "operand must be an even-numbered register in the range [r0, r10]");
6883 
6884   const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps];
6885   if (!Op2.isReg())
6886     return Error(Op2.getStartLoc(), Op2Diag);
6887 
6888   unsigned RNext;
6889   unsigned RPair;
6890   switch (Op2.getReg()) {
6891   default:
6892     return Error(Op2.getStartLoc(), Op2Diag);
6893   case ARM::R0:
6894     RNext = ARM::R1;
6895     RPair = ARM::R0_R1;
6896     break;
6897   case ARM::R2:
6898     RNext = ARM::R3;
6899     RPair = ARM::R2_R3;
6900     break;
6901   case ARM::R4:
6902     RNext = ARM::R5;
6903     RPair = ARM::R4_R5;
6904     break;
6905   case ARM::R6:
6906     RNext = ARM::R7;
6907     RPair = ARM::R6_R7;
6908     break;
6909   case ARM::R8:
6910     RNext = ARM::R9;
6911     RPair = ARM::R8_R9;
6912     break;
6913   case ARM::R10:
6914     RNext = ARM::R11;
6915     RPair = ARM::R10_R11;
6916     break;
6917   }
6918 
6919   const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps];
6920   if (!Op3.isReg() || Op3.getReg() != RNext)
6921     return Error(Op3.getStartLoc(), "operand must be a consecutive register");
6922 
6923   Operands.erase(Operands.begin() + 3 + NumPredOps);
6924   Operands[2 + NumPredOps] =
6925       ARMOperand::CreateReg(RPair, Op2.getStartLoc(), Op2.getEndLoc());
6926   return false;
6927 }
6928 
6929 /// Parse an arm instruction mnemonic followed by its operands.
6930 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6931                                     SMLoc NameLoc, OperandVector &Operands) {
6932   MCAsmParser &Parser = getParser();
6933 
6934   // Apply mnemonic aliases before doing anything else, as the destination
6935   // mnemonic may include suffices and we want to handle them normally.
6936   // The generic tblgen'erated code does this later, at the start of
6937   // MatchInstructionImpl(), but that's too late for aliases that include
6938   // any sort of suffix.
6939   const FeatureBitset &AvailableFeatures = getAvailableFeatures();
6940   unsigned AssemblerDialect = getParser().getAssemblerDialect();
6941   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6942 
6943   // First check for the ARM-specific .req directive.
6944   if (Parser.getTok().is(AsmToken::Identifier) &&
6945       Parser.getTok().getIdentifier().lower() == ".req") {
6946     parseDirectiveReq(Name, NameLoc);
6947     // We always return 'error' for this, as we're done with this
6948     // statement and don't need to match the 'instruction."
6949     return true;
6950   }
6951 
6952   // Create the leading tokens for the mnemonic, split by '.' characters.
6953   size_t Start = 0, Next = Name.find('.');
6954   StringRef Mnemonic = Name.slice(Start, Next);
6955   StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
6956 
6957   // Split out the predication code and carry setting flag from the mnemonic.
6958   unsigned PredicationCode;
6959   unsigned VPTPredicationCode;
6960   unsigned ProcessorIMod;
6961   bool CarrySetting;
6962   StringRef ITMask;
6963   Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
6964                            CarrySetting, ProcessorIMod, ITMask);
6965 
6966   // In Thumb1, only the branch (B) instruction can be predicated.
6967   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6968     return Error(NameLoc, "conditional execution not supported in Thumb1");
6969   }
6970 
6971   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6972 
6973   // Handle the mask for IT and VPT instructions. In ARMOperand and
6974   // MCOperand, this is stored in a format independent of the
6975   // condition code: the lowest set bit indicates the end of the
6976   // encoding, and above that, a 1 bit indicates 'else', and an 0
6977   // indicates 'then'. E.g.
6978   //    IT    -> 1000
6979   //    ITx   -> x100    (ITT -> 0100, ITE -> 1100)
6980   //    ITxy  -> xy10    (e.g. ITET -> 1010)
6981   //    ITxyz -> xyz1    (e.g. ITEET -> 1101)
6982   // Note: See the ARM::PredBlockMask enum in
6983   //   /lib/Target/ARM/Utils/ARMBaseInfo.h
6984   if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
6985       Mnemonic.startswith("vpst")) {
6986     SMLoc Loc = Mnemonic == "it"  ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
6987                 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
6988                                     SMLoc::getFromPointer(NameLoc.getPointer() + 4);
6989     if (ITMask.size() > 3) {
6990       if (Mnemonic == "it")
6991         return Error(Loc, "too many conditions on IT instruction");
6992       return Error(Loc, "too many conditions on VPT instruction");
6993     }
6994     unsigned Mask = 8;
6995     for (unsigned i = ITMask.size(); i != 0; --i) {
6996       char pos = ITMask[i - 1];
6997       if (pos != 't' && pos != 'e') {
6998         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6999       }
7000       Mask >>= 1;
7001       if (ITMask[i - 1] == 'e')
7002         Mask |= 8;
7003     }
7004     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
7005   }
7006 
7007   // FIXME: This is all a pretty gross hack. We should automatically handle
7008   // optional operands like this via tblgen.
7009 
7010   // Next, add the CCOut and ConditionCode operands, if needed.
7011   //
7012   // For mnemonics which can ever incorporate a carry setting bit or predication
7013   // code, our matching model involves us always generating CCOut and
7014   // ConditionCode operands to match the mnemonic "as written" and then we let
7015   // the matcher deal with finding the right instruction or generating an
7016   // appropriate error.
7017   bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
7018   getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
7019                         CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
7020 
7021   // If we had a carry-set on an instruction that can't do that, issue an
7022   // error.
7023   if (!CanAcceptCarrySet && CarrySetting) {
7024     return Error(NameLoc, "instruction '" + Mnemonic +
7025                  "' can not set flags, but 's' suffix specified");
7026   }
7027   // If we had a predication code on an instruction that can't do that, issue an
7028   // error.
7029   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
7030     return Error(NameLoc, "instruction '" + Mnemonic +
7031                  "' is not predicable, but condition code specified");
7032   }
7033 
7034   // If we had a VPT predication code on an instruction that can't do that, issue an
7035   // error.
7036   if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
7037     return Error(NameLoc, "instruction '" + Mnemonic +
7038                  "' is not VPT predicable, but VPT code T/E is specified");
7039   }
7040 
7041   // Add the carry setting operand, if necessary.
7042   if (CanAcceptCarrySet) {
7043     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
7044     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
7045                                                Loc));
7046   }
7047 
7048   // Add the predication code operand, if necessary.
7049   if (CanAcceptPredicationCode) {
7050     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7051                                       CarrySetting);
7052     Operands.push_back(ARMOperand::CreateCondCode(
7053                        ARMCC::CondCodes(PredicationCode), Loc));
7054   }
7055 
7056   // Add the VPT predication code operand, if necessary.
7057   // FIXME: We don't add them for the instructions filtered below as these can
7058   // have custom operands which need special parsing.  This parsing requires
7059   // the operand to be in the same place in the OperandVector as their
7060   // definition in tblgen.  Since these instructions may also have the
7061   // scalar predication operand we do not add the vector one and leave until
7062   // now to fix it up.
7063   if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
7064       !Mnemonic.startswith("vcmp") &&
7065       !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
7066         Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
7067     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
7068                                       CarrySetting);
7069     Operands.push_back(ARMOperand::CreateVPTPred(
7070                          ARMVCC::VPTCodes(VPTPredicationCode), Loc));
7071   }
7072 
7073   // Add the processor imod operand, if necessary.
7074   if (ProcessorIMod) {
7075     Operands.push_back(ARMOperand::CreateImm(
7076           MCConstantExpr::create(ProcessorIMod, getContext()),
7077                                  NameLoc, NameLoc));
7078   } else if (Mnemonic == "cps" && isMClass()) {
7079     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
7080   }
7081 
7082   // Add the remaining tokens in the mnemonic.
7083   while (Next != StringRef::npos) {
7084     Start = Next;
7085     Next = Name.find('.', Start + 1);
7086     ExtraToken = Name.slice(Start, Next);
7087 
7088     // Some NEON instructions have an optional datatype suffix that is
7089     // completely ignored. Check for that.
7090     if (isDataTypeToken(ExtraToken) &&
7091         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
7092       continue;
7093 
7094     // For for ARM mode generate an error if the .n qualifier is used.
7095     if (ExtraToken == ".n" && !isThumb()) {
7096       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7097       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
7098                    "arm mode");
7099     }
7100 
7101     // The .n qualifier is always discarded as that is what the tables
7102     // and matcher expect.  In ARM mode the .w qualifier has no effect,
7103     // so discard it to avoid errors that can be caused by the matcher.
7104     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
7105       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
7106       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
7107     }
7108   }
7109 
7110   // Read the remaining operands.
7111   if (getLexer().isNot(AsmToken::EndOfStatement)) {
7112     // Read the first operand.
7113     if (parseOperand(Operands, Mnemonic)) {
7114       return true;
7115     }
7116 
7117     while (parseOptionalToken(AsmToken::Comma)) {
7118       // Parse and remember the operand.
7119       if (parseOperand(Operands, Mnemonic)) {
7120         return true;
7121       }
7122     }
7123   }
7124 
7125   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
7126     return true;
7127 
7128   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
7129 
7130   if (hasCDE() && MS.isCDEInstr(Mnemonic)) {
7131     // Dual-register instructions use even-odd register pairs as their
7132     // destination operand, in assembly such pair is spelled as two
7133     // consecutive registers, without any special syntax. ConvertDualRegOperand
7134     // tries to convert such operand into register pair, e.g. r2, r3 -> r2_r3.
7135     // It returns true, if an error message has been emitted. If the function
7136     // returns false, the function either succeeded or an error (e.g. missing
7137     // operand) will be diagnosed elsewhere.
7138     if (MS.isCDEDualRegInstr(Mnemonic)) {
7139       bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands);
7140       if (GotError)
7141         return GotError;
7142     }
7143   }
7144 
7145   // Some instructions, mostly Thumb, have forms for the same mnemonic that
7146   // do and don't have a cc_out optional-def operand. With some spot-checks
7147   // of the operand list, we can figure out which variant we're trying to
7148   // parse and adjust accordingly before actually matching. We shouldn't ever
7149   // try to remove a cc_out operand that was explicitly set on the
7150   // mnemonic, of course (CarrySetting == true). Reason number #317 the
7151   // table driven matcher doesn't fit well with the ARM instruction set.
7152   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
7153     Operands.erase(Operands.begin() + 1);
7154 
7155   // Some instructions have the same mnemonic, but don't always
7156   // have a predicate. Distinguish them here and delete the
7157   // appropriate predicate if needed.  This could be either the scalar
7158   // predication code or the vector predication code.
7159   if (PredicationCode == ARMCC::AL &&
7160       shouldOmitPredicateOperand(Mnemonic, Operands))
7161     Operands.erase(Operands.begin() + 1);
7162 
7163 
7164   if (hasMVE()) {
7165     if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
7166         Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
7167       // Very nasty hack to deal with the vector predicated variant of vmovlt
7168       // the scalar predicated vmov with condition 'lt'.  We can not tell them
7169       // apart until we have parsed their operands.
7170       Operands.erase(Operands.begin() + 1);
7171       Operands.erase(Operands.begin());
7172       SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7173       SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7174                                          Mnemonic.size() - 1 + CarrySetting);
7175       Operands.insert(Operands.begin(),
7176                       ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
7177       Operands.insert(Operands.begin(),
7178                       ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
7179     } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
7180                !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7181       // Another nasty hack to deal with the ambiguity between vcvt with scalar
7182       // predication 'ne' and vcvtn with vector predication 'e'.  As above we
7183       // can only distinguish between the two after we have parsed their
7184       // operands.
7185       Operands.erase(Operands.begin() + 1);
7186       Operands.erase(Operands.begin());
7187       SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7188       SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7189                                          Mnemonic.size() - 1 + CarrySetting);
7190       Operands.insert(Operands.begin(),
7191                       ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
7192       Operands.insert(Operands.begin(),
7193                       ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
7194     } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
7195                !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7196       // Another hack, this time to distinguish between scalar predicated vmul
7197       // with 'lt' predication code and the vector instruction vmullt with
7198       // vector predication code "none"
7199       Operands.erase(Operands.begin() + 1);
7200       Operands.erase(Operands.begin());
7201       SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7202       Operands.insert(Operands.begin(),
7203                       ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
7204     }
7205     // For vmov and vcmp, as mentioned earlier, we did not add the vector
7206     // predication code, since these may contain operands that require
7207     // special parsing.  So now we have to see if they require vector
7208     // predication and replace the scalar one with the vector predication
7209     // operand if that is the case.
7210     else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
7211              (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
7212               !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
7213               !Mnemonic.startswith("vcvtm"))) {
7214       if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7215         // We could not split the vector predicate off vcvt because it might
7216         // have been the scalar vcvtt instruction.  Now we know its a vector
7217         // instruction, we still need to check whether its the vector
7218         // predicated vcvt with 'Then' predication or the vector vcvtt.  We can
7219         // distinguish the two based on the suffixes, if it is any of
7220         // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
7221         if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
7222           auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
7223           auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
7224           if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
7225               Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
7226             Operands.erase(Operands.begin());
7227             SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7228             VPTPredicationCode = ARMVCC::Then;
7229 
7230             Mnemonic = Mnemonic.substr(0, 4);
7231             Operands.insert(Operands.begin(),
7232                             ARMOperand::CreateToken(Mnemonic, MLoc));
7233           }
7234         }
7235         Operands.erase(Operands.begin() + 1);
7236         SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7237                                           Mnemonic.size() + CarrySetting);
7238         Operands.insert(Operands.begin() + 1,
7239                         ARMOperand::CreateVPTPred(
7240                             ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
7241       }
7242     } else if (CanAcceptVPTPredicationCode) {
7243       // For all other instructions, make sure only one of the two
7244       // predication operands is left behind, depending on whether we should
7245       // use the vector predication.
7246       if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7247         if (CanAcceptPredicationCode)
7248           Operands.erase(Operands.begin() + 2);
7249         else
7250           Operands.erase(Operands.begin() + 1);
7251       } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
7252         Operands.erase(Operands.begin() + 1);
7253       }
7254     }
7255   }
7256 
7257   if (VPTPredicationCode != ARMVCC::None) {
7258     bool usedVPTPredicationCode = false;
7259     for (unsigned I = 1; I < Operands.size(); ++I)
7260       if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7261         usedVPTPredicationCode = true;
7262     if (!usedVPTPredicationCode) {
7263       // If we have a VPT predication code and we haven't just turned it
7264       // into an operand, then it was a mistake for splitMnemonic to
7265       // separate it from the rest of the mnemonic in the first place,
7266       // and this may lead to wrong disassembly (e.g. scalar floating
7267       // point VCMPE is actually a different instruction from VCMP, so
7268       // we mustn't treat them the same). In that situation, glue it
7269       // back on.
7270       Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7271       Operands.erase(Operands.begin());
7272       Operands.insert(Operands.begin(),
7273                       ARMOperand::CreateToken(Mnemonic, NameLoc));
7274     }
7275   }
7276 
7277     // ARM mode 'blx' need special handling, as the register operand version
7278     // is predicable, but the label operand version is not. So, we can't rely
7279     // on the Mnemonic based checking to correctly figure out when to put
7280     // a k_CondCode operand in the list. If we're trying to match the label
7281     // version, remove the k_CondCode operand here.
7282     if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
7283         static_cast<ARMOperand &>(*Operands[2]).isImm())
7284       Operands.erase(Operands.begin() + 1);
7285 
7286     // Adjust operands of ldrexd/strexd to MCK_GPRPair.
7287     // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7288     // a single GPRPair reg operand is used in the .td file to replace the two
7289     // GPRs. However, when parsing from asm, the two GRPs cannot be
7290     // automatically
7291     // expressed as a GPRPair, so we have to manually merge them.
7292     // FIXME: We would really like to be able to tablegen'erate this.
7293     if (!isThumb() && Operands.size() > 4 &&
7294         (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
7295          Mnemonic == "stlexd")) {
7296       bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
7297       unsigned Idx = isLoad ? 2 : 3;
7298       ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7299       ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7300 
7301       const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
7302       // Adjust only if Op1 and Op2 are GPRs.
7303       if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7304           MRC.contains(Op2.getReg())) {
7305         unsigned Reg1 = Op1.getReg();
7306         unsigned Reg2 = Op2.getReg();
7307         unsigned Rt = MRI->getEncodingValue(Reg1);
7308         unsigned Rt2 = MRI->getEncodingValue(Reg2);
7309 
7310         // Rt2 must be Rt + 1 and Rt must be even.
7311         if (Rt + 1 != Rt2 || (Rt & 1)) {
7312           return Error(Op2.getStartLoc(),
7313                        isLoad ? "destination operands must be sequential"
7314                               : "source operands must be sequential");
7315         }
7316         unsigned NewReg = MRI->getMatchingSuperReg(
7317             Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
7318         Operands[Idx] =
7319             ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
7320         Operands.erase(Operands.begin() + Idx + 1);
7321       }
7322   }
7323 
7324   // GNU Assembler extension (compatibility).
7325   fixupGNULDRDAlias(Mnemonic, Operands);
7326 
7327   // FIXME: As said above, this is all a pretty gross hack.  This instruction
7328   // does not fit with other "subs" and tblgen.
7329   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
7330   // so the Mnemonic is the original name "subs" and delete the predicate
7331   // operand so it will match the table entry.
7332   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
7333       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7334       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
7335       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
7336       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7337       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
7338     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
7339     Operands.erase(Operands.begin() + 1);
7340   }
7341   return false;
7342 }
7343 
7344 // Validate context-sensitive operand constraints.
7345 
7346 // return 'true' if register list contains non-low GPR registers,
7347 // 'false' otherwise. If Reg is in the register list or is HiReg, set
7348 // 'containsReg' to true.
7349 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7350                                  unsigned Reg, unsigned HiReg,
7351                                  bool &containsReg) {
7352   containsReg = false;
7353   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7354     unsigned OpReg = Inst.getOperand(i).getReg();
7355     if (OpReg == Reg)
7356       containsReg = true;
7357     // Anything other than a low register isn't legal here.
7358     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7359       return true;
7360   }
7361   return false;
7362 }
7363 
7364 // Check if the specified regisgter is in the register list of the inst,
7365 // starting at the indicated operand number.
7366 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7367   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
7368     unsigned OpReg = Inst.getOperand(i).getReg();
7369     if (OpReg == Reg)
7370       return true;
7371   }
7372   return false;
7373 }
7374 
7375 // Return true if instruction has the interesting property of being
7376 // allowed in IT blocks, but not being predicable.
7377 static bool instIsBreakpoint(const MCInst &Inst) {
7378     return Inst.getOpcode() == ARM::tBKPT ||
7379            Inst.getOpcode() == ARM::BKPT ||
7380            Inst.getOpcode() == ARM::tHLT ||
7381            Inst.getOpcode() == ARM::HLT;
7382 }
7383 
7384 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7385                                        const OperandVector &Operands,
7386                                        unsigned ListNo, bool IsARPop) {
7387   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7388   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7389 
7390   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7391   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7392   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7393 
7394   if (!IsARPop && ListContainsSP)
7395     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7396                  "SP may not be in the register list");
7397   else if (ListContainsPC && ListContainsLR)
7398     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7399                  "PC and LR may not be in the register list simultaneously");
7400   return false;
7401 }
7402 
7403 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7404                                        const OperandVector &Operands,
7405                                        unsigned ListNo) {
7406   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7407   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7408 
7409   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7410   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7411 
7412   if (ListContainsSP && ListContainsPC)
7413     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7414                  "SP and PC may not be in the register list");
7415   else if (ListContainsSP)
7416     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7417                  "SP may not be in the register list");
7418   else if (ListContainsPC)
7419     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7420                  "PC may not be in the register list");
7421   return false;
7422 }
7423 
7424 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7425                                     const OperandVector &Operands,
7426                                     bool Load, bool ARMMode, bool Writeback) {
7427   unsigned RtIndex = Load || !Writeback ? 0 : 1;
7428   unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7429   unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7430 
7431   if (ARMMode) {
7432     // Rt can't be R14.
7433     if (Rt == 14)
7434       return Error(Operands[3]->getStartLoc(),
7435                   "Rt can't be R14");
7436 
7437     // Rt must be even-numbered.
7438     if ((Rt & 1) == 1)
7439       return Error(Operands[3]->getStartLoc(),
7440                    "Rt must be even-numbered");
7441 
7442     // Rt2 must be Rt + 1.
7443     if (Rt2 != Rt + 1) {
7444       if (Load)
7445         return Error(Operands[3]->getStartLoc(),
7446                      "destination operands must be sequential");
7447       else
7448         return Error(Operands[3]->getStartLoc(),
7449                      "source operands must be sequential");
7450     }
7451 
7452     // FIXME: Diagnose m == 15
7453     // FIXME: Diagnose ldrd with m == t || m == t2.
7454   }
7455 
7456   if (!ARMMode && Load) {
7457     if (Rt2 == Rt)
7458       return Error(Operands[3]->getStartLoc(),
7459                    "destination operands can't be identical");
7460   }
7461 
7462   if (Writeback) {
7463     unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7464 
7465     if (Rn == Rt || Rn == Rt2) {
7466       if (Load)
7467         return Error(Operands[3]->getStartLoc(),
7468                      "base register needs to be different from destination "
7469                      "registers");
7470       else
7471         return Error(Operands[3]->getStartLoc(),
7472                      "source register and base register can't be identical");
7473     }
7474 
7475     // FIXME: Diagnose ldrd/strd with writeback and n == 15.
7476     // (Except the immediate form of ldrd?)
7477   }
7478 
7479   return false;
7480 }
7481 
7482 static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7483   for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7484     if (ARM::isVpred(MCID.OpInfo[i].OperandType))
7485       return i;
7486   }
7487   return -1;
7488 }
7489 
7490 static bool isVectorPredicable(const MCInstrDesc &MCID) {
7491   return findFirstVectorPredOperandIdx(MCID) != -1;
7492 }
7493 
7494 // FIXME: We would really like to be able to tablegen'erate this.
7495 bool ARMAsmParser::validateInstruction(MCInst &Inst,
7496                                        const OperandVector &Operands) {
7497   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7498   SMLoc Loc = Operands[0]->getStartLoc();
7499 
7500   // Check the IT block state first.
7501   // NOTE: BKPT and HLT instructions have the interesting property of being
7502   // allowed in IT blocks, but not being predicable. They just always execute.
7503   if (inITBlock() && !instIsBreakpoint(Inst)) {
7504     // The instruction must be predicable.
7505     if (!MCID.isPredicable())
7506       return Error(Loc, "instructions in IT block must be predicable");
7507     ARMCC::CondCodes Cond = ARMCC::CondCodes(
7508         Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
7509     if (Cond != currentITCond()) {
7510       // Find the condition code Operand to get its SMLoc information.
7511       SMLoc CondLoc;
7512       for (unsigned I = 1; I < Operands.size(); ++I)
7513         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7514           CondLoc = Operands[I]->getStartLoc();
7515       return Error(CondLoc, "incorrect condition in IT block; got '" +
7516                                 StringRef(ARMCondCodeToString(Cond)) +
7517                                 "', but expected '" +
7518                                 ARMCondCodeToString(currentITCond()) + "'");
7519     }
7520   // Check for non-'al' condition codes outside of the IT block.
7521   } else if (isThumbTwo() && MCID.isPredicable() &&
7522              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7523              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7524              Inst.getOpcode() != ARM::t2Bcc &&
7525              Inst.getOpcode() != ARM::t2BFic) {
7526     return Error(Loc, "predicated instructions must be in IT block");
7527   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7528              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7529                  ARMCC::AL) {
7530     return Warning(Loc, "predicated instructions should be in IT block");
7531   } else if (!MCID.isPredicable()) {
7532     // Check the instruction doesn't have a predicate operand anyway
7533     // that it's not allowed to use. Sometimes this happens in order
7534     // to keep instructions the same shape even though one cannot
7535     // legally be predicated, e.g. vmul.f16 vs vmul.f32.
7536     for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7537       if (MCID.OpInfo[i].isPredicate()) {
7538         if (Inst.getOperand(i).getImm() != ARMCC::AL)
7539           return Error(Loc, "instruction is not predicable");
7540         break;
7541       }
7542     }
7543   }
7544 
7545   // PC-setting instructions in an IT block, but not the last instruction of
7546   // the block, are UNPREDICTABLE.
7547   if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
7548     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
7549   }
7550 
7551   if (inVPTBlock() && !instIsBreakpoint(Inst)) {
7552     unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition);
7553     if (!isVectorPredicable(MCID))
7554       return Error(Loc, "instruction in VPT block must be predicable");
7555     unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
7556     unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
7557     if (Pred != VPTPred) {
7558       SMLoc PredLoc;
7559       for (unsigned I = 1; I < Operands.size(); ++I)
7560         if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7561           PredLoc = Operands[I]->getStartLoc();
7562       return Error(PredLoc, "incorrect predication in VPT block; got '" +
7563                    StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
7564                    "', but expected '" +
7565                    ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
7566     }
7567   }
7568   else if (isVectorPredicable(MCID) &&
7569            Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
7570            ARMVCC::None)
7571     return Error(Loc, "VPT predicated instructions must be in VPT block");
7572 
7573   const unsigned Opcode = Inst.getOpcode();
7574   switch (Opcode) {
7575   case ARM::t2IT: {
7576     // Encoding is unpredictable if it ever results in a notional 'NV'
7577     // predicate. Since we don't parse 'NV' directly this means an 'AL'
7578     // predicate with an "else" mask bit.
7579     unsigned Cond = Inst.getOperand(0).getImm();
7580     unsigned Mask = Inst.getOperand(1).getImm();
7581 
7582     // Conditions only allowing a 't' are those with no set bit except
7583     // the lowest-order one that indicates the end of the sequence. In
7584     // other words, powers of 2.
7585     if (Cond == ARMCC::AL && countPopulation(Mask) != 1)
7586       return Error(Loc, "unpredictable IT predicate sequence");
7587     break;
7588   }
7589   case ARM::LDRD:
7590     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7591                          /*Writeback*/false))
7592       return true;
7593     break;
7594   case ARM::LDRD_PRE:
7595   case ARM::LDRD_POST:
7596     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7597                          /*Writeback*/true))
7598       return true;
7599     break;
7600   case ARM::t2LDRDi8:
7601     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7602                          /*Writeback*/false))
7603       return true;
7604     break;
7605   case ARM::t2LDRD_PRE:
7606   case ARM::t2LDRD_POST:
7607     if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7608                          /*Writeback*/true))
7609       return true;
7610     break;
7611   case ARM::t2BXJ: {
7612     const unsigned RmReg = Inst.getOperand(0).getReg();
7613     // Rm = SP is no longer unpredictable in v8-A
7614     if (RmReg == ARM::SP && !hasV8Ops())
7615       return Error(Operands[2]->getStartLoc(),
7616                    "r13 (SP) is an unpredictable operand to BXJ");
7617     return false;
7618   }
7619   case ARM::STRD:
7620     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7621                          /*Writeback*/false))
7622       return true;
7623     break;
7624   case ARM::STRD_PRE:
7625   case ARM::STRD_POST:
7626     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7627                          /*Writeback*/true))
7628       return true;
7629     break;
7630   case ARM::t2STRD_PRE:
7631   case ARM::t2STRD_POST:
7632     if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
7633                          /*Writeback*/true))
7634       return true;
7635     break;
7636   case ARM::STR_PRE_IMM:
7637   case ARM::STR_PRE_REG:
7638   case ARM::t2STR_PRE:
7639   case ARM::STR_POST_IMM:
7640   case ARM::STR_POST_REG:
7641   case ARM::t2STR_POST:
7642   case ARM::STRH_PRE:
7643   case ARM::t2STRH_PRE:
7644   case ARM::STRH_POST:
7645   case ARM::t2STRH_POST:
7646   case ARM::STRB_PRE_IMM:
7647   case ARM::STRB_PRE_REG:
7648   case ARM::t2STRB_PRE:
7649   case ARM::STRB_POST_IMM:
7650   case ARM::STRB_POST_REG:
7651   case ARM::t2STRB_POST: {
7652     // Rt must be different from Rn.
7653     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7654     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7655 
7656     if (Rt == Rn)
7657       return Error(Operands[3]->getStartLoc(),
7658                    "source register and base register can't be identical");
7659     return false;
7660   }
7661   case ARM::LDR_PRE_IMM:
7662   case ARM::LDR_PRE_REG:
7663   case ARM::t2LDR_PRE:
7664   case ARM::LDR_POST_IMM:
7665   case ARM::LDR_POST_REG:
7666   case ARM::t2LDR_POST:
7667   case ARM::LDRH_PRE:
7668   case ARM::t2LDRH_PRE:
7669   case ARM::LDRH_POST:
7670   case ARM::t2LDRH_POST:
7671   case ARM::LDRSH_PRE:
7672   case ARM::t2LDRSH_PRE:
7673   case ARM::LDRSH_POST:
7674   case ARM::t2LDRSH_POST:
7675   case ARM::LDRB_PRE_IMM:
7676   case ARM::LDRB_PRE_REG:
7677   case ARM::t2LDRB_PRE:
7678   case ARM::LDRB_POST_IMM:
7679   case ARM::LDRB_POST_REG:
7680   case ARM::t2LDRB_POST:
7681   case ARM::LDRSB_PRE:
7682   case ARM::t2LDRSB_PRE:
7683   case ARM::LDRSB_POST:
7684   case ARM::t2LDRSB_POST: {
7685     // Rt must be different from Rn.
7686     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7687     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7688 
7689     if (Rt == Rn)
7690       return Error(Operands[3]->getStartLoc(),
7691                    "destination register and base register can't be identical");
7692     return false;
7693   }
7694 
7695   case ARM::MVE_VLDRBU8_rq:
7696   case ARM::MVE_VLDRBU16_rq:
7697   case ARM::MVE_VLDRBS16_rq:
7698   case ARM::MVE_VLDRBU32_rq:
7699   case ARM::MVE_VLDRBS32_rq:
7700   case ARM::MVE_VLDRHU16_rq:
7701   case ARM::MVE_VLDRHU16_rq_u:
7702   case ARM::MVE_VLDRHU32_rq:
7703   case ARM::MVE_VLDRHU32_rq_u:
7704   case ARM::MVE_VLDRHS32_rq:
7705   case ARM::MVE_VLDRHS32_rq_u:
7706   case ARM::MVE_VLDRWU32_rq:
7707   case ARM::MVE_VLDRWU32_rq_u:
7708   case ARM::MVE_VLDRDU64_rq:
7709   case ARM::MVE_VLDRDU64_rq_u:
7710   case ARM::MVE_VLDRWU32_qi:
7711   case ARM::MVE_VLDRWU32_qi_pre:
7712   case ARM::MVE_VLDRDU64_qi:
7713   case ARM::MVE_VLDRDU64_qi_pre: {
7714     // Qd must be different from Qm.
7715     unsigned QdIdx = 0, QmIdx = 2;
7716     bool QmIsPointer = false;
7717     switch (Opcode) {
7718     case ARM::MVE_VLDRWU32_qi:
7719     case ARM::MVE_VLDRDU64_qi:
7720       QmIdx = 1;
7721       QmIsPointer = true;
7722       break;
7723     case ARM::MVE_VLDRWU32_qi_pre:
7724     case ARM::MVE_VLDRDU64_qi_pre:
7725       QdIdx = 1;
7726       QmIsPointer = true;
7727       break;
7728     }
7729 
7730     const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7731     const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7732 
7733     if (Qd == Qm) {
7734       return Error(Operands[3]->getStartLoc(),
7735                    Twine("destination vector register and vector ") +
7736                    (QmIsPointer ? "pointer" : "offset") +
7737                    " register can't be identical");
7738     }
7739     return false;
7740   }
7741 
7742   case ARM::SBFX:
7743   case ARM::t2SBFX:
7744   case ARM::UBFX:
7745   case ARM::t2UBFX: {
7746     // Width must be in range [1, 32-lsb].
7747     unsigned LSB = Inst.getOperand(2).getImm();
7748     unsigned Widthm1 = Inst.getOperand(3).getImm();
7749     if (Widthm1 >= 32 - LSB)
7750       return Error(Operands[5]->getStartLoc(),
7751                    "bitfield width must be in range [1,32-lsb]");
7752     return false;
7753   }
7754   // Notionally handles ARM::tLDMIA_UPD too.
7755   case ARM::tLDMIA: {
7756     // If we're parsing Thumb2, the .w variant is available and handles
7757     // most cases that are normally illegal for a Thumb1 LDM instruction.
7758     // We'll make the transformation in processInstruction() if necessary.
7759     //
7760     // Thumb LDM instructions are writeback iff the base register is not
7761     // in the register list.
7762     unsigned Rn = Inst.getOperand(0).getReg();
7763     bool HasWritebackToken =
7764         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7765          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7766     bool ListContainsBase;
7767     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
7768       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
7769                    "registers must be in range r0-r7");
7770     // If we should have writeback, then there should be a '!' token.
7771     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
7772       return Error(Operands[2]->getStartLoc(),
7773                    "writeback operator '!' expected");
7774     // If we should not have writeback, there must not be a '!'. This is
7775     // true even for the 32-bit wide encodings.
7776     if (ListContainsBase && HasWritebackToken)
7777       return Error(Operands[3]->getStartLoc(),
7778                    "writeback operator '!' not allowed when base register "
7779                    "in register list");
7780 
7781     if (validatetLDMRegList(Inst, Operands, 3))
7782       return true;
7783     break;
7784   }
7785   case ARM::LDMIA_UPD:
7786   case ARM::LDMDB_UPD:
7787   case ARM::LDMIB_UPD:
7788   case ARM::LDMDA_UPD:
7789     // ARM variants loading and updating the same register are only officially
7790     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
7791     if (!hasV7Ops())
7792       break;
7793     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7794       return Error(Operands.back()->getStartLoc(),
7795                    "writeback register not allowed in register list");
7796     break;
7797   case ARM::t2LDMIA:
7798   case ARM::t2LDMDB:
7799     if (validatetLDMRegList(Inst, Operands, 3))
7800       return true;
7801     break;
7802   case ARM::t2STMIA:
7803   case ARM::t2STMDB:
7804     if (validatetSTMRegList(Inst, Operands, 3))
7805       return true;
7806     break;
7807   case ARM::t2LDMIA_UPD:
7808   case ARM::t2LDMDB_UPD:
7809   case ARM::t2STMIA_UPD:
7810   case ARM::t2STMDB_UPD:
7811     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7812       return Error(Operands.back()->getStartLoc(),
7813                    "writeback register not allowed in register list");
7814 
7815     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
7816       if (validatetLDMRegList(Inst, Operands, 3))
7817         return true;
7818     } else {
7819       if (validatetSTMRegList(Inst, Operands, 3))
7820         return true;
7821     }
7822     break;
7823 
7824   case ARM::sysLDMIA_UPD:
7825   case ARM::sysLDMDA_UPD:
7826   case ARM::sysLDMDB_UPD:
7827   case ARM::sysLDMIB_UPD:
7828     if (!listContainsReg(Inst, 3, ARM::PC))
7829       return Error(Operands[4]->getStartLoc(),
7830                    "writeback register only allowed on system LDM "
7831                    "if PC in register-list");
7832     break;
7833   case ARM::sysSTMIA_UPD:
7834   case ARM::sysSTMDA_UPD:
7835   case ARM::sysSTMDB_UPD:
7836   case ARM::sysSTMIB_UPD:
7837     return Error(Operands[2]->getStartLoc(),
7838                  "system STM cannot have writeback register");
7839   case ARM::tMUL:
7840     // The second source operand must be the same register as the destination
7841     // operand.
7842     //
7843     // In this case, we must directly check the parsed operands because the
7844     // cvtThumbMultiply() function is written in such a way that it guarantees
7845     // this first statement is always true for the new Inst.  Essentially, the
7846     // destination is unconditionally copied into the second source operand
7847     // without checking to see if it matches what we actually parsed.
7848     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
7849                                  ((ARMOperand &)*Operands[5]).getReg()) &&
7850         (((ARMOperand &)*Operands[3]).getReg() !=
7851          ((ARMOperand &)*Operands[4]).getReg())) {
7852       return Error(Operands[3]->getStartLoc(),
7853                    "destination register must match source register");
7854     }
7855     break;
7856 
7857   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
7858   // so only issue a diagnostic for thumb1. The instructions will be
7859   // switched to the t2 encodings in processInstruction() if necessary.
7860   case ARM::tPOP: {
7861     bool ListContainsBase;
7862     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
7863         !isThumbTwo())
7864       return Error(Operands[2]->getStartLoc(),
7865                    "registers must be in range r0-r7 or pc");
7866     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
7867       return true;
7868     break;
7869   }
7870   case ARM::tPUSH: {
7871     bool ListContainsBase;
7872     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
7873         !isThumbTwo())
7874       return Error(Operands[2]->getStartLoc(),
7875                    "registers must be in range r0-r7 or lr");
7876     if (validatetSTMRegList(Inst, Operands, 2))
7877       return true;
7878     break;
7879   }
7880   case ARM::tSTMIA_UPD: {
7881     bool ListContainsBase, InvalidLowList;
7882     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
7883                                           0, ListContainsBase);
7884     if (InvalidLowList && !isThumbTwo())
7885       return Error(Operands[4]->getStartLoc(),
7886                    "registers must be in range r0-r7");
7887 
7888     // This would be converted to a 32-bit stm, but that's not valid if the
7889     // writeback register is in the list.
7890     if (InvalidLowList && ListContainsBase)
7891       return Error(Operands[4]->getStartLoc(),
7892                    "writeback operator '!' not allowed when base register "
7893                    "in register list");
7894 
7895     if (validatetSTMRegList(Inst, Operands, 4))
7896       return true;
7897     break;
7898   }
7899   case ARM::tADDrSP:
7900     // If the non-SP source operand and the destination operand are not the
7901     // same, we need thumb2 (for the wide encoding), or we have an error.
7902     if (!isThumbTwo() &&
7903         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7904       return Error(Operands[4]->getStartLoc(),
7905                    "source register must be the same as destination");
7906     }
7907     break;
7908 
7909   case ARM::t2ADDrr:
7910   case ARM::t2ADDrs:
7911   case ARM::t2SUBrr:
7912   case ARM::t2SUBrs:
7913     if (Inst.getOperand(0).getReg() == ARM::SP &&
7914         Inst.getOperand(1).getReg() != ARM::SP)
7915       return Error(Operands[4]->getStartLoc(),
7916                    "source register must be sp if destination is sp");
7917     break;
7918 
7919   // Final range checking for Thumb unconditional branch instructions.
7920   case ARM::tB:
7921     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
7922       return Error(Operands[2]->getStartLoc(), "branch target out of range");
7923     break;
7924   case ARM::t2B: {
7925     int op = (Operands[2]->isImm()) ? 2 : 3;
7926     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
7927       return Error(Operands[op]->getStartLoc(), "branch target out of range");
7928     break;
7929   }
7930   // Final range checking for Thumb conditional branch instructions.
7931   case ARM::tBcc:
7932     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
7933       return Error(Operands[2]->getStartLoc(), "branch target out of range");
7934     break;
7935   case ARM::t2Bcc: {
7936     int Op = (Operands[2]->isImm()) ? 2 : 3;
7937     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
7938       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
7939     break;
7940   }
7941   case ARM::tCBZ:
7942   case ARM::tCBNZ: {
7943     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
7944       return Error(Operands[2]->getStartLoc(), "branch target out of range");
7945     break;
7946   }
7947   case ARM::MOVi16:
7948   case ARM::MOVTi16:
7949   case ARM::t2MOVi16:
7950   case ARM::t2MOVTi16:
7951     {
7952     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
7953     // especially when we turn it into a movw and the expression <symbol> does
7954     // not have a :lower16: or :upper16 as part of the expression.  We don't
7955     // want the behavior of silently truncating, which can be unexpected and
7956     // lead to bugs that are difficult to find since this is an easy mistake
7957     // to make.
7958     int i = (Operands[3]->isImm()) ? 3 : 4;
7959     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
7960     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
7961     if (CE) break;
7962     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
7963     if (!E) break;
7964     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
7965     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
7966                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
7967       return Error(
7968           Op.getStartLoc(),
7969           "immediate expression for mov requires :lower16: or :upper16");
7970     break;
7971   }
7972   case ARM::HINT:
7973   case ARM::t2HINT: {
7974     unsigned Imm8 = Inst.getOperand(0).getImm();
7975     unsigned Pred = Inst.getOperand(1).getImm();
7976     // ESB is not predicable (pred must be AL). Without the RAS extension, this
7977     // behaves as any other unallocated hint.
7978     if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
7979       return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
7980                                                "predicable, but condition "
7981                                                "code specified");
7982     if (Imm8 == 0x14 && Pred != ARMCC::AL)
7983       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
7984                                                "predicable, but condition "
7985                                                "code specified");
7986     break;
7987   }
7988   case ARM::t2BFi:
7989   case ARM::t2BFr:
7990   case ARM::t2BFLi:
7991   case ARM::t2BFLr: {
7992     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
7993         (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7994       return Error(Operands[2]->getStartLoc(),
7995                    "branch location out of range or not a multiple of 2");
7996 
7997     if (Opcode == ARM::t2BFi) {
7998       if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
7999         return Error(Operands[3]->getStartLoc(),
8000                      "branch target out of range or not a multiple of 2");
8001     } else if (Opcode == ARM::t2BFLi) {
8002       if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
8003         return Error(Operands[3]->getStartLoc(),
8004                      "branch target out of range or not a multiple of 2");
8005     }
8006     break;
8007   }
8008   case ARM::t2BFic: {
8009     if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
8010         (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
8011       return Error(Operands[1]->getStartLoc(),
8012                    "branch location out of range or not a multiple of 2");
8013 
8014     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
8015       return Error(Operands[2]->getStartLoc(),
8016                    "branch target out of range or not a multiple of 2");
8017 
8018     assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
8019            "branch location and else branch target should either both be "
8020            "immediates or both labels");
8021 
8022     if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
8023       int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
8024       if (Diff != 4 && Diff != 2)
8025         return Error(
8026             Operands[3]->getStartLoc(),
8027             "else branch target must be 2 or 4 greater than the branch location");
8028     }
8029     break;
8030   }
8031   case ARM::t2CLRM: {
8032     for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
8033       if (Inst.getOperand(i).isReg() &&
8034           !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
8035               Inst.getOperand(i).getReg())) {
8036         return Error(Operands[2]->getStartLoc(),
8037                      "invalid register in register list. Valid registers are "
8038                      "r0-r12, lr/r14 and APSR.");
8039       }
8040     }
8041     break;
8042   }
8043   case ARM::DSB:
8044   case ARM::t2DSB: {
8045 
8046     if (Inst.getNumOperands() < 2)
8047       break;
8048 
8049     unsigned Option = Inst.getOperand(0).getImm();
8050     unsigned Pred = Inst.getOperand(1).getImm();
8051 
8052     // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
8053     if (Option == 0 && Pred != ARMCC::AL)
8054       return Error(Operands[1]->getStartLoc(),
8055                    "instruction 'ssbb' is not predicable, but condition code "
8056                    "specified");
8057     if (Option == 4 && Pred != ARMCC::AL)
8058       return Error(Operands[1]->getStartLoc(),
8059                    "instruction 'pssbb' is not predicable, but condition code "
8060                    "specified");
8061     break;
8062   }
8063   case ARM::VMOVRRS: {
8064     // Source registers must be sequential.
8065     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
8066     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
8067     if (Sm1 != Sm + 1)
8068       return Error(Operands[5]->getStartLoc(),
8069                    "source operands must be sequential");
8070     break;
8071   }
8072   case ARM::VMOVSRR: {
8073     // Destination registers must be sequential.
8074     const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
8075     const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
8076     if (Sm1 != Sm + 1)
8077       return Error(Operands[3]->getStartLoc(),
8078                    "destination operands must be sequential");
8079     break;
8080   }
8081   case ARM::VLDMDIA:
8082   case ARM::VSTMDIA: {
8083     ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
8084     auto &RegList = Op.getRegList();
8085     if (RegList.size() < 1 || RegList.size() > 16)
8086       return Error(Operands[3]->getStartLoc(),
8087                    "list of registers must be at least 1 and at most 16");
8088     break;
8089   }
8090   case ARM::MVE_VQDMULLs32bh:
8091   case ARM::MVE_VQDMULLs32th:
8092   case ARM::MVE_VCMULf32:
8093   case ARM::MVE_VMULLBs32:
8094   case ARM::MVE_VMULLTs32:
8095   case ARM::MVE_VMULLBu32:
8096   case ARM::MVE_VMULLTu32: {
8097     if (Operands[3]->getReg() == Operands[4]->getReg()) {
8098       return Error (Operands[3]->getStartLoc(),
8099                     "Qd register and Qn register can't be identical");
8100     }
8101     if (Operands[3]->getReg() == Operands[5]->getReg()) {
8102       return Error (Operands[3]->getStartLoc(),
8103                     "Qd register and Qm register can't be identical");
8104     }
8105     break;
8106   }
8107   case ARM::MVE_VMOV_rr_q: {
8108     if (Operands[4]->getReg() != Operands[6]->getReg())
8109       return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
8110     if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
8111         static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
8112       return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8113     break;
8114   }
8115   case ARM::MVE_VMOV_q_rr: {
8116     if (Operands[2]->getReg() != Operands[4]->getReg())
8117       return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
8118     if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
8119         static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
8120       return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
8121     break;
8122   }
8123   case ARM::UMAAL:
8124   case ARM::UMLAL:
8125   case ARM::UMULL:
8126   case ARM::t2UMAAL:
8127   case ARM::t2UMLAL:
8128   case ARM::t2UMULL:
8129   case ARM::SMLAL:
8130   case ARM::SMLALBB:
8131   case ARM::SMLALBT:
8132   case ARM::SMLALD:
8133   case ARM::SMLALDX:
8134   case ARM::SMLALTB:
8135   case ARM::SMLALTT:
8136   case ARM::SMLSLD:
8137   case ARM::SMLSLDX:
8138   case ARM::SMULL:
8139   case ARM::t2SMLAL:
8140   case ARM::t2SMLALBB:
8141   case ARM::t2SMLALBT:
8142   case ARM::t2SMLALD:
8143   case ARM::t2SMLALDX:
8144   case ARM::t2SMLALTB:
8145   case ARM::t2SMLALTT:
8146   case ARM::t2SMLSLD:
8147   case ARM::t2SMLSLDX:
8148   case ARM::t2SMULL: {
8149     unsigned RdHi = Inst.getOperand(0).getReg();
8150     unsigned RdLo = Inst.getOperand(1).getReg();
8151     if(RdHi == RdLo) {
8152       return Error(Loc,
8153                    "unpredictable instruction, RdHi and RdLo must be different");
8154     }
8155     break;
8156   }
8157 
8158   case ARM::CDE_CX1:
8159   case ARM::CDE_CX1A:
8160   case ARM::CDE_CX1D:
8161   case ARM::CDE_CX1DA:
8162   case ARM::CDE_CX2:
8163   case ARM::CDE_CX2A:
8164   case ARM::CDE_CX2D:
8165   case ARM::CDE_CX2DA:
8166   case ARM::CDE_CX3:
8167   case ARM::CDE_CX3A:
8168   case ARM::CDE_CX3D:
8169   case ARM::CDE_CX3DA:
8170   case ARM::CDE_VCX1_vec:
8171   case ARM::CDE_VCX1_fpsp:
8172   case ARM::CDE_VCX1_fpdp:
8173   case ARM::CDE_VCX1A_vec:
8174   case ARM::CDE_VCX1A_fpsp:
8175   case ARM::CDE_VCX1A_fpdp:
8176   case ARM::CDE_VCX2_vec:
8177   case ARM::CDE_VCX2_fpsp:
8178   case ARM::CDE_VCX2_fpdp:
8179   case ARM::CDE_VCX2A_vec:
8180   case ARM::CDE_VCX2A_fpsp:
8181   case ARM::CDE_VCX2A_fpdp:
8182   case ARM::CDE_VCX3_vec:
8183   case ARM::CDE_VCX3_fpsp:
8184   case ARM::CDE_VCX3_fpdp:
8185   case ARM::CDE_VCX3A_vec:
8186   case ARM::CDE_VCX3A_fpsp:
8187   case ARM::CDE_VCX3A_fpdp: {
8188     assert(Inst.getOperand(1).isImm() &&
8189            "CDE operand 1 must be a coprocessor ID");
8190     int64_t Coproc = Inst.getOperand(1).getImm();
8191     if (Coproc < 8 && !ARM::isCDECoproc(Coproc, *STI))
8192       return Error(Operands[1]->getStartLoc(),
8193                    "coprocessor must be configured as CDE");
8194     else if (Coproc >= 8)
8195       return Error(Operands[1]->getStartLoc(),
8196                    "coprocessor must be in the range [p0, p7]");
8197     break;
8198   }
8199 
8200   case ARM::t2CDP:
8201   case ARM::t2CDP2:
8202   case ARM::t2LDC2L_OFFSET:
8203   case ARM::t2LDC2L_OPTION:
8204   case ARM::t2LDC2L_POST:
8205   case ARM::t2LDC2L_PRE:
8206   case ARM::t2LDC2_OFFSET:
8207   case ARM::t2LDC2_OPTION:
8208   case ARM::t2LDC2_POST:
8209   case ARM::t2LDC2_PRE:
8210   case ARM::t2LDCL_OFFSET:
8211   case ARM::t2LDCL_OPTION:
8212   case ARM::t2LDCL_POST:
8213   case ARM::t2LDCL_PRE:
8214   case ARM::t2LDC_OFFSET:
8215   case ARM::t2LDC_OPTION:
8216   case ARM::t2LDC_POST:
8217   case ARM::t2LDC_PRE:
8218   case ARM::t2MCR:
8219   case ARM::t2MCR2:
8220   case ARM::t2MCRR:
8221   case ARM::t2MCRR2:
8222   case ARM::t2MRC:
8223   case ARM::t2MRC2:
8224   case ARM::t2MRRC:
8225   case ARM::t2MRRC2:
8226   case ARM::t2STC2L_OFFSET:
8227   case ARM::t2STC2L_OPTION:
8228   case ARM::t2STC2L_POST:
8229   case ARM::t2STC2L_PRE:
8230   case ARM::t2STC2_OFFSET:
8231   case ARM::t2STC2_OPTION:
8232   case ARM::t2STC2_POST:
8233   case ARM::t2STC2_PRE:
8234   case ARM::t2STCL_OFFSET:
8235   case ARM::t2STCL_OPTION:
8236   case ARM::t2STCL_POST:
8237   case ARM::t2STCL_PRE:
8238   case ARM::t2STC_OFFSET:
8239   case ARM::t2STC_OPTION:
8240   case ARM::t2STC_POST:
8241   case ARM::t2STC_PRE: {
8242     unsigned Opcode = Inst.getOpcode();
8243     // Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags,
8244     // CopInd is the index of the coprocessor operand.
8245     size_t CopInd = 0;
8246     if (Opcode == ARM::t2MRRC || Opcode == ARM::t2MRRC2)
8247       CopInd = 2;
8248     else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2)
8249       CopInd = 1;
8250     assert(Inst.getOperand(CopInd).isImm() &&
8251            "Operand must be a coprocessor ID");
8252     int64_t Coproc = Inst.getOperand(CopInd).getImm();
8253     // Operands[2] is the coprocessor operand at syntactic level
8254     if (ARM::isCDECoproc(Coproc, *STI))
8255       return Error(Operands[2]->getStartLoc(),
8256                    "coprocessor must be configured as GCP");
8257     break;
8258   }
8259   }
8260 
8261   return false;
8262 }
8263 
8264 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
8265   switch(Opc) {
8266   default: llvm_unreachable("unexpected opcode!");
8267   // VST1LN
8268   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
8269   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8270   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8271   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
8272   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
8273   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
8274   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
8275   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
8276   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
8277 
8278   // VST2LN
8279   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
8280   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8281   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8282   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8283   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8284 
8285   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
8286   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
8287   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
8288   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
8289   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
8290 
8291   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
8292   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
8293   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
8294   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
8295   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
8296 
8297   // VST3LN
8298   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
8299   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8300   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8301   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
8302   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8303   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
8304   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
8305   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
8306   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
8307   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
8308   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
8309   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
8310   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
8311   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
8312   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
8313 
8314   // VST3
8315   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
8316   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8317   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8318   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
8319   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8320   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8321   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
8322   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
8323   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
8324   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
8325   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
8326   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
8327   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
8328   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
8329   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
8330   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
8331   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
8332   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
8333 
8334   // VST4LN
8335   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
8336   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8337   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8338   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
8339   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8340   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
8341   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8342   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8343   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
8344   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8345   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
8346   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
8347   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
8348   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
8349   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
8350 
8351   // VST4
8352   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
8353   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8354   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8355   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
8356   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8357   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8358   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
8359   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8360   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8361   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
8362   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8363   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8364   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
8365   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
8366   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
8367   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
8368   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
8369   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
8370   }
8371 }
8372 
8373 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
8374   switch(Opc) {
8375   default: llvm_unreachable("unexpected opcode!");
8376   // VLD1LN
8377   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
8378   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8379   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8380   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
8381   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8382   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8383   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
8384   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
8385   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
8386 
8387   // VLD2LN
8388   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
8389   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8390   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8391   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
8392   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8393   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
8394   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8395   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8396   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
8397   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8398   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
8399   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
8400   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
8401   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
8402   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
8403 
8404   // VLD3DUP
8405   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
8406   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8407   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8408   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
8409   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8410   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8411   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
8412   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8413   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8414   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
8415   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8416   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8417   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
8418   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
8419   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
8420   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
8421   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
8422   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
8423 
8424   // VLD3LN
8425   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
8426   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8427   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8428   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
8429   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8430   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
8431   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8432   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8433   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
8434   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8435   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
8436   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
8437   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
8438   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
8439   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
8440 
8441   // VLD3
8442   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
8443   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8444   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8445   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
8446   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8447   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8448   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
8449   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8450   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8451   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
8452   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8453   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8454   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
8455   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
8456   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
8457   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
8458   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
8459   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
8460 
8461   // VLD4LN
8462   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
8463   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8464   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8465   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8466   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8467   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
8468   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8469   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8470   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8471   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8472   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
8473   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
8474   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
8475   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
8476   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
8477 
8478   // VLD4DUP
8479   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
8480   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8481   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8482   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
8483   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
8484   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8485   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
8486   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8487   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8488   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
8489   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
8490   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8491   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
8492   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
8493   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
8494   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
8495   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
8496   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
8497 
8498   // VLD4
8499   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
8500   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8501   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8502   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
8503   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8504   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8505   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
8506   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8507   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8508   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
8509   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8510   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8511   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
8512   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
8513   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
8514   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
8515   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
8516   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
8517   }
8518 }
8519 
8520 bool ARMAsmParser::processInstruction(MCInst &Inst,
8521                                       const OperandVector &Operands,
8522                                       MCStreamer &Out) {
8523   // Check if we have the wide qualifier, because if it's present we
8524   // must avoid selecting a 16-bit thumb instruction.
8525   bool HasWideQualifier = false;
8526   for (auto &Op : Operands) {
8527     ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
8528     if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
8529       HasWideQualifier = true;
8530       break;
8531     }
8532   }
8533 
8534   switch (Inst.getOpcode()) {
8535   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
8536   case ARM::LDRT_POST:
8537   case ARM::LDRBT_POST: {
8538     const unsigned Opcode =
8539       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8540                                            : ARM::LDRBT_POST_IMM;
8541     MCInst TmpInst;
8542     TmpInst.setOpcode(Opcode);
8543     TmpInst.addOperand(Inst.getOperand(0));
8544     TmpInst.addOperand(Inst.getOperand(1));
8545     TmpInst.addOperand(Inst.getOperand(1));
8546     TmpInst.addOperand(MCOperand::createReg(0));
8547     TmpInst.addOperand(MCOperand::createImm(0));
8548     TmpInst.addOperand(Inst.getOperand(2));
8549     TmpInst.addOperand(Inst.getOperand(3));
8550     Inst = TmpInst;
8551     return true;
8552   }
8553   // Alias for 'ldr{sb,h,sh}t Rt, [Rn] {, #imm}' for ommitted immediate.
8554   case ARM::LDRSBTii:
8555   case ARM::LDRHTii:
8556   case ARM::LDRSHTii: {
8557     MCInst TmpInst;
8558 
8559     if (Inst.getOpcode() == ARM::LDRSBTii)
8560       TmpInst.setOpcode(ARM::LDRSBTi);
8561     else if (Inst.getOpcode() == ARM::LDRHTii)
8562       TmpInst.setOpcode(ARM::LDRHTi);
8563     else if (Inst.getOpcode() == ARM::LDRSHTii)
8564       TmpInst.setOpcode(ARM::LDRSHTi);
8565     TmpInst.addOperand(Inst.getOperand(0));
8566     TmpInst.addOperand(Inst.getOperand(1));
8567     TmpInst.addOperand(Inst.getOperand(1));
8568     TmpInst.addOperand(MCOperand::createImm(256));
8569     TmpInst.addOperand(Inst.getOperand(2));
8570     Inst = TmpInst;
8571     return true;
8572   }
8573   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
8574   case ARM::STRT_POST:
8575   case ARM::STRBT_POST: {
8576     const unsigned Opcode =
8577       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8578                                            : ARM::STRBT_POST_IMM;
8579     MCInst TmpInst;
8580     TmpInst.setOpcode(Opcode);
8581     TmpInst.addOperand(Inst.getOperand(1));
8582     TmpInst.addOperand(Inst.getOperand(0));
8583     TmpInst.addOperand(Inst.getOperand(1));
8584     TmpInst.addOperand(MCOperand::createReg(0));
8585     TmpInst.addOperand(MCOperand::createImm(0));
8586     TmpInst.addOperand(Inst.getOperand(2));
8587     TmpInst.addOperand(Inst.getOperand(3));
8588     Inst = TmpInst;
8589     return true;
8590   }
8591   // Alias for alternate form of 'ADR Rd, #imm' instruction.
8592   case ARM::ADDri: {
8593     if (Inst.getOperand(1).getReg() != ARM::PC ||
8594         Inst.getOperand(5).getReg() != 0 ||
8595         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
8596       return false;
8597     MCInst TmpInst;
8598     TmpInst.setOpcode(ARM::ADR);
8599     TmpInst.addOperand(Inst.getOperand(0));
8600     if (Inst.getOperand(2).isImm()) {
8601       // Immediate (mod_imm) will be in its encoded form, we must unencode it
8602       // before passing it to the ADR instruction.
8603       unsigned Enc = Inst.getOperand(2).getImm();
8604       TmpInst.addOperand(MCOperand::createImm(
8605         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8606     } else {
8607       // Turn PC-relative expression into absolute expression.
8608       // Reading PC provides the start of the current instruction + 8 and
8609       // the transform to adr is biased by that.
8610       MCSymbol *Dot = getContext().createTempSymbol();
8611       Out.emitLabel(Dot);
8612       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
8613       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
8614                                                      MCSymbolRefExpr::VK_None,
8615                                                      getContext());
8616       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
8617       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
8618                                                      getContext());
8619       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
8620                                                         getContext());
8621       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
8622     }
8623     TmpInst.addOperand(Inst.getOperand(3));
8624     TmpInst.addOperand(Inst.getOperand(4));
8625     Inst = TmpInst;
8626     return true;
8627   }
8628   // Aliases for alternate PC+imm syntax of LDR instructions.
8629   case ARM::t2LDRpcrel:
8630     // Select the narrow version if the immediate will fit.
8631     if (Inst.getOperand(1).getImm() > 0 &&
8632         Inst.getOperand(1).getImm() <= 0xff &&
8633         !HasWideQualifier)
8634       Inst.setOpcode(ARM::tLDRpci);
8635     else
8636       Inst.setOpcode(ARM::t2LDRpci);
8637     return true;
8638   case ARM::t2LDRBpcrel:
8639     Inst.setOpcode(ARM::t2LDRBpci);
8640     return true;
8641   case ARM::t2LDRHpcrel:
8642     Inst.setOpcode(ARM::t2LDRHpci);
8643     return true;
8644   case ARM::t2LDRSBpcrel:
8645     Inst.setOpcode(ARM::t2LDRSBpci);
8646     return true;
8647   case ARM::t2LDRSHpcrel:
8648     Inst.setOpcode(ARM::t2LDRSHpci);
8649     return true;
8650   case ARM::LDRConstPool:
8651   case ARM::tLDRConstPool:
8652   case ARM::t2LDRConstPool: {
8653     // Pseudo instruction ldr rt, =immediate is converted to a
8654     // MOV rt, immediate if immediate is known and representable
8655     // otherwise we create a constant pool entry that we load from.
8656     MCInst TmpInst;
8657     if (Inst.getOpcode() == ARM::LDRConstPool)
8658       TmpInst.setOpcode(ARM::LDRi12);
8659     else if (Inst.getOpcode() == ARM::tLDRConstPool)
8660       TmpInst.setOpcode(ARM::tLDRpci);
8661     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8662       TmpInst.setOpcode(ARM::t2LDRpci);
8663     const ARMOperand &PoolOperand =
8664       (HasWideQualifier ?
8665        static_cast<ARMOperand &>(*Operands[4]) :
8666        static_cast<ARMOperand &>(*Operands[3]));
8667     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
8668     // If SubExprVal is a constant we may be able to use a MOV
8669     if (isa<MCConstantExpr>(SubExprVal) &&
8670         Inst.getOperand(0).getReg() != ARM::PC &&
8671         Inst.getOperand(0).getReg() != ARM::SP) {
8672       int64_t Value =
8673         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
8674       bool UseMov  = true;
8675       bool MovHasS = true;
8676       if (Inst.getOpcode() == ARM::LDRConstPool) {
8677         // ARM Constant
8678         if (ARM_AM::getSOImmVal(Value) != -1) {
8679           Value = ARM_AM::getSOImmVal(Value);
8680           TmpInst.setOpcode(ARM::MOVi);
8681         }
8682         else if (ARM_AM::getSOImmVal(~Value) != -1) {
8683           Value = ARM_AM::getSOImmVal(~Value);
8684           TmpInst.setOpcode(ARM::MVNi);
8685         }
8686         else if (hasV6T2Ops() &&
8687                  Value >=0 && Value < 65536) {
8688           TmpInst.setOpcode(ARM::MOVi16);
8689           MovHasS = false;
8690         }
8691         else
8692           UseMov = false;
8693       }
8694       else {
8695         // Thumb/Thumb2 Constant
8696         if (hasThumb2() &&
8697             ARM_AM::getT2SOImmVal(Value) != -1)
8698           TmpInst.setOpcode(ARM::t2MOVi);
8699         else if (hasThumb2() &&
8700                  ARM_AM::getT2SOImmVal(~Value) != -1) {
8701           TmpInst.setOpcode(ARM::t2MVNi);
8702           Value = ~Value;
8703         }
8704         else if (hasV8MBaseline() &&
8705                  Value >=0 && Value < 65536) {
8706           TmpInst.setOpcode(ARM::t2MOVi16);
8707           MovHasS = false;
8708         }
8709         else
8710           UseMov = false;
8711       }
8712       if (UseMov) {
8713         TmpInst.addOperand(Inst.getOperand(0));           // Rt
8714         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
8715         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
8716         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
8717         if (MovHasS)
8718           TmpInst.addOperand(MCOperand::createReg(0));    // S
8719         Inst = TmpInst;
8720         return true;
8721       }
8722     }
8723     // No opportunity to use MOV/MVN create constant pool
8724     const MCExpr *CPLoc =
8725       getTargetStreamer().addConstantPoolEntry(SubExprVal,
8726                                                PoolOperand.getStartLoc());
8727     TmpInst.addOperand(Inst.getOperand(0));           // Rt
8728     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
8729     if (TmpInst.getOpcode() == ARM::LDRi12)
8730       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
8731     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
8732     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
8733     Inst = TmpInst;
8734     return true;
8735   }
8736   // Handle NEON VST complex aliases.
8737   case ARM::VST1LNdWB_register_Asm_8:
8738   case ARM::VST1LNdWB_register_Asm_16:
8739   case ARM::VST1LNdWB_register_Asm_32: {
8740     MCInst TmpInst;
8741     // Shuffle the operands around so the lane index operand is in the
8742     // right place.
8743     unsigned Spacing;
8744     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8745     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8746     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8747     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8748     TmpInst.addOperand(Inst.getOperand(4)); // Rm
8749     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8750     TmpInst.addOperand(Inst.getOperand(1)); // lane
8751     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8752     TmpInst.addOperand(Inst.getOperand(6));
8753     Inst = TmpInst;
8754     return true;
8755   }
8756 
8757   case ARM::VST2LNdWB_register_Asm_8:
8758   case ARM::VST2LNdWB_register_Asm_16:
8759   case ARM::VST2LNdWB_register_Asm_32:
8760   case ARM::VST2LNqWB_register_Asm_16:
8761   case ARM::VST2LNqWB_register_Asm_32: {
8762     MCInst TmpInst;
8763     // Shuffle the operands around so the lane index operand is in the
8764     // right place.
8765     unsigned Spacing;
8766     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8767     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8768     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8769     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8770     TmpInst.addOperand(Inst.getOperand(4)); // Rm
8771     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8772     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8773                                             Spacing));
8774     TmpInst.addOperand(Inst.getOperand(1)); // lane
8775     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8776     TmpInst.addOperand(Inst.getOperand(6));
8777     Inst = TmpInst;
8778     return true;
8779   }
8780 
8781   case ARM::VST3LNdWB_register_Asm_8:
8782   case ARM::VST3LNdWB_register_Asm_16:
8783   case ARM::VST3LNdWB_register_Asm_32:
8784   case ARM::VST3LNqWB_register_Asm_16:
8785   case ARM::VST3LNqWB_register_Asm_32: {
8786     MCInst TmpInst;
8787     // Shuffle the operands around so the lane index operand is in the
8788     // right place.
8789     unsigned Spacing;
8790     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8791     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8792     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8793     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8794     TmpInst.addOperand(Inst.getOperand(4)); // Rm
8795     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8796     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8797                                             Spacing));
8798     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8799                                             Spacing * 2));
8800     TmpInst.addOperand(Inst.getOperand(1)); // lane
8801     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8802     TmpInst.addOperand(Inst.getOperand(6));
8803     Inst = TmpInst;
8804     return true;
8805   }
8806 
8807   case ARM::VST4LNdWB_register_Asm_8:
8808   case ARM::VST4LNdWB_register_Asm_16:
8809   case ARM::VST4LNdWB_register_Asm_32:
8810   case ARM::VST4LNqWB_register_Asm_16:
8811   case ARM::VST4LNqWB_register_Asm_32: {
8812     MCInst TmpInst;
8813     // Shuffle the operands around so the lane index operand is in the
8814     // right place.
8815     unsigned Spacing;
8816     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8817     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8818     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8819     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8820     TmpInst.addOperand(Inst.getOperand(4)); // Rm
8821     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8822     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8823                                             Spacing));
8824     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8825                                             Spacing * 2));
8826     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8827                                             Spacing * 3));
8828     TmpInst.addOperand(Inst.getOperand(1)); // lane
8829     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8830     TmpInst.addOperand(Inst.getOperand(6));
8831     Inst = TmpInst;
8832     return true;
8833   }
8834 
8835   case ARM::VST1LNdWB_fixed_Asm_8:
8836   case ARM::VST1LNdWB_fixed_Asm_16:
8837   case ARM::VST1LNdWB_fixed_Asm_32: {
8838     MCInst TmpInst;
8839     // Shuffle the operands around so the lane index operand is in the
8840     // right place.
8841     unsigned Spacing;
8842     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8843     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8844     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8845     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8846     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8847     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8848     TmpInst.addOperand(Inst.getOperand(1)); // lane
8849     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8850     TmpInst.addOperand(Inst.getOperand(5));
8851     Inst = TmpInst;
8852     return true;
8853   }
8854 
8855   case ARM::VST2LNdWB_fixed_Asm_8:
8856   case ARM::VST2LNdWB_fixed_Asm_16:
8857   case ARM::VST2LNdWB_fixed_Asm_32:
8858   case ARM::VST2LNqWB_fixed_Asm_16:
8859   case ARM::VST2LNqWB_fixed_Asm_32: {
8860     MCInst TmpInst;
8861     // Shuffle the operands around so the lane index operand is in the
8862     // right place.
8863     unsigned Spacing;
8864     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8865     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8866     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8867     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8868     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8869     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8870     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8871                                             Spacing));
8872     TmpInst.addOperand(Inst.getOperand(1)); // lane
8873     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8874     TmpInst.addOperand(Inst.getOperand(5));
8875     Inst = TmpInst;
8876     return true;
8877   }
8878 
8879   case ARM::VST3LNdWB_fixed_Asm_8:
8880   case ARM::VST3LNdWB_fixed_Asm_16:
8881   case ARM::VST3LNdWB_fixed_Asm_32:
8882   case ARM::VST3LNqWB_fixed_Asm_16:
8883   case ARM::VST3LNqWB_fixed_Asm_32: {
8884     MCInst TmpInst;
8885     // Shuffle the operands around so the lane index operand is in the
8886     // right place.
8887     unsigned Spacing;
8888     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8889     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8890     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8891     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8892     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8893     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8894     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8895                                             Spacing));
8896     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8897                                             Spacing * 2));
8898     TmpInst.addOperand(Inst.getOperand(1)); // lane
8899     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8900     TmpInst.addOperand(Inst.getOperand(5));
8901     Inst = TmpInst;
8902     return true;
8903   }
8904 
8905   case ARM::VST4LNdWB_fixed_Asm_8:
8906   case ARM::VST4LNdWB_fixed_Asm_16:
8907   case ARM::VST4LNdWB_fixed_Asm_32:
8908   case ARM::VST4LNqWB_fixed_Asm_16:
8909   case ARM::VST4LNqWB_fixed_Asm_32: {
8910     MCInst TmpInst;
8911     // Shuffle the operands around so the lane index operand is in the
8912     // right place.
8913     unsigned Spacing;
8914     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8915     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8916     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8917     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8918     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8919     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8920     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8921                                             Spacing));
8922     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8923                                             Spacing * 2));
8924     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8925                                             Spacing * 3));
8926     TmpInst.addOperand(Inst.getOperand(1)); // lane
8927     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8928     TmpInst.addOperand(Inst.getOperand(5));
8929     Inst = TmpInst;
8930     return true;
8931   }
8932 
8933   case ARM::VST1LNdAsm_8:
8934   case ARM::VST1LNdAsm_16:
8935   case ARM::VST1LNdAsm_32: {
8936     MCInst TmpInst;
8937     // Shuffle the operands around so the lane index operand is in the
8938     // right place.
8939     unsigned Spacing;
8940     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8941     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8942     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8943     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8944     TmpInst.addOperand(Inst.getOperand(1)); // lane
8945     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8946     TmpInst.addOperand(Inst.getOperand(5));
8947     Inst = TmpInst;
8948     return true;
8949   }
8950 
8951   case ARM::VST2LNdAsm_8:
8952   case ARM::VST2LNdAsm_16:
8953   case ARM::VST2LNdAsm_32:
8954   case ARM::VST2LNqAsm_16:
8955   case ARM::VST2LNqAsm_32: {
8956     MCInst TmpInst;
8957     // Shuffle the operands around so the lane index operand is in the
8958     // right place.
8959     unsigned Spacing;
8960     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8961     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8962     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8963     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8964     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8965                                             Spacing));
8966     TmpInst.addOperand(Inst.getOperand(1)); // lane
8967     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8968     TmpInst.addOperand(Inst.getOperand(5));
8969     Inst = TmpInst;
8970     return true;
8971   }
8972 
8973   case ARM::VST3LNdAsm_8:
8974   case ARM::VST3LNdAsm_16:
8975   case ARM::VST3LNdAsm_32:
8976   case ARM::VST3LNqAsm_16:
8977   case ARM::VST3LNqAsm_32: {
8978     MCInst TmpInst;
8979     // Shuffle the operands around so the lane index operand is in the
8980     // right place.
8981     unsigned Spacing;
8982     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8983     TmpInst.addOperand(Inst.getOperand(2)); // Rn
8984     TmpInst.addOperand(Inst.getOperand(3)); // alignment
8985     TmpInst.addOperand(Inst.getOperand(0)); // Vd
8986     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8987                                             Spacing));
8988     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8989                                             Spacing * 2));
8990     TmpInst.addOperand(Inst.getOperand(1)); // lane
8991     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8992     TmpInst.addOperand(Inst.getOperand(5));
8993     Inst = TmpInst;
8994     return true;
8995   }
8996 
8997   case ARM::VST4LNdAsm_8:
8998   case ARM::VST4LNdAsm_16:
8999   case ARM::VST4LNdAsm_32:
9000   case ARM::VST4LNqAsm_16:
9001   case ARM::VST4LNqAsm_32: {
9002     MCInst TmpInst;
9003     // Shuffle the operands around so the lane index operand is in the
9004     // right place.
9005     unsigned Spacing;
9006     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9007     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9008     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9009     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9010     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9011                                             Spacing));
9012     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9013                                             Spacing * 2));
9014     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9015                                             Spacing * 3));
9016     TmpInst.addOperand(Inst.getOperand(1)); // lane
9017     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9018     TmpInst.addOperand(Inst.getOperand(5));
9019     Inst = TmpInst;
9020     return true;
9021   }
9022 
9023   // Handle NEON VLD complex aliases.
9024   case ARM::VLD1LNdWB_register_Asm_8:
9025   case ARM::VLD1LNdWB_register_Asm_16:
9026   case ARM::VLD1LNdWB_register_Asm_32: {
9027     MCInst TmpInst;
9028     // Shuffle the operands around so the lane index operand is in the
9029     // right place.
9030     unsigned Spacing;
9031     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9032     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9033     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9034     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9035     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9036     TmpInst.addOperand(Inst.getOperand(4)); // Rm
9037     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9038     TmpInst.addOperand(Inst.getOperand(1)); // lane
9039     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9040     TmpInst.addOperand(Inst.getOperand(6));
9041     Inst = TmpInst;
9042     return true;
9043   }
9044 
9045   case ARM::VLD2LNdWB_register_Asm_8:
9046   case ARM::VLD2LNdWB_register_Asm_16:
9047   case ARM::VLD2LNdWB_register_Asm_32:
9048   case ARM::VLD2LNqWB_register_Asm_16:
9049   case ARM::VLD2LNqWB_register_Asm_32: {
9050     MCInst TmpInst;
9051     // Shuffle the operands around so the lane index operand is in the
9052     // right place.
9053     unsigned Spacing;
9054     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9055     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9056     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9057                                             Spacing));
9058     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9059     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9060     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9061     TmpInst.addOperand(Inst.getOperand(4)); // Rm
9062     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9063     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9064                                             Spacing));
9065     TmpInst.addOperand(Inst.getOperand(1)); // lane
9066     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9067     TmpInst.addOperand(Inst.getOperand(6));
9068     Inst = TmpInst;
9069     return true;
9070   }
9071 
9072   case ARM::VLD3LNdWB_register_Asm_8:
9073   case ARM::VLD3LNdWB_register_Asm_16:
9074   case ARM::VLD3LNdWB_register_Asm_32:
9075   case ARM::VLD3LNqWB_register_Asm_16:
9076   case ARM::VLD3LNqWB_register_Asm_32: {
9077     MCInst TmpInst;
9078     // Shuffle the operands around so the lane index operand is in the
9079     // right place.
9080     unsigned Spacing;
9081     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9082     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9083     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9084                                             Spacing));
9085     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9086                                             Spacing * 2));
9087     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9088     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9089     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9090     TmpInst.addOperand(Inst.getOperand(4)); // Rm
9091     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9092     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9093                                             Spacing));
9094     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9095                                             Spacing * 2));
9096     TmpInst.addOperand(Inst.getOperand(1)); // lane
9097     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9098     TmpInst.addOperand(Inst.getOperand(6));
9099     Inst = TmpInst;
9100     return true;
9101   }
9102 
9103   case ARM::VLD4LNdWB_register_Asm_8:
9104   case ARM::VLD4LNdWB_register_Asm_16:
9105   case ARM::VLD4LNdWB_register_Asm_32:
9106   case ARM::VLD4LNqWB_register_Asm_16:
9107   case ARM::VLD4LNqWB_register_Asm_32: {
9108     MCInst TmpInst;
9109     // Shuffle the operands around so the lane index operand is in the
9110     // right place.
9111     unsigned Spacing;
9112     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9113     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9114     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9115                                             Spacing));
9116     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9117                                             Spacing * 2));
9118     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9119                                             Spacing * 3));
9120     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9121     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9122     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9123     TmpInst.addOperand(Inst.getOperand(4)); // Rm
9124     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9125     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9126                                             Spacing));
9127     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9128                                             Spacing * 2));
9129     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9130                                             Spacing * 3));
9131     TmpInst.addOperand(Inst.getOperand(1)); // lane
9132     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
9133     TmpInst.addOperand(Inst.getOperand(6));
9134     Inst = TmpInst;
9135     return true;
9136   }
9137 
9138   case ARM::VLD1LNdWB_fixed_Asm_8:
9139   case ARM::VLD1LNdWB_fixed_Asm_16:
9140   case ARM::VLD1LNdWB_fixed_Asm_32: {
9141     MCInst TmpInst;
9142     // Shuffle the operands around so the lane index operand is in the
9143     // right place.
9144     unsigned Spacing;
9145     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9146     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9147     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9148     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9149     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9150     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9151     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9152     TmpInst.addOperand(Inst.getOperand(1)); // lane
9153     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9154     TmpInst.addOperand(Inst.getOperand(5));
9155     Inst = TmpInst;
9156     return true;
9157   }
9158 
9159   case ARM::VLD2LNdWB_fixed_Asm_8:
9160   case ARM::VLD2LNdWB_fixed_Asm_16:
9161   case ARM::VLD2LNdWB_fixed_Asm_32:
9162   case ARM::VLD2LNqWB_fixed_Asm_16:
9163   case ARM::VLD2LNqWB_fixed_Asm_32: {
9164     MCInst TmpInst;
9165     // Shuffle the operands around so the lane index operand is in the
9166     // right place.
9167     unsigned Spacing;
9168     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9169     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9170     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9171                                             Spacing));
9172     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9173     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9174     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9175     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9176     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9177     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9178                                             Spacing));
9179     TmpInst.addOperand(Inst.getOperand(1)); // lane
9180     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9181     TmpInst.addOperand(Inst.getOperand(5));
9182     Inst = TmpInst;
9183     return true;
9184   }
9185 
9186   case ARM::VLD3LNdWB_fixed_Asm_8:
9187   case ARM::VLD3LNdWB_fixed_Asm_16:
9188   case ARM::VLD3LNdWB_fixed_Asm_32:
9189   case ARM::VLD3LNqWB_fixed_Asm_16:
9190   case ARM::VLD3LNqWB_fixed_Asm_32: {
9191     MCInst TmpInst;
9192     // Shuffle the operands around so the lane index operand is in the
9193     // right place.
9194     unsigned Spacing;
9195     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9196     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9197     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9198                                             Spacing));
9199     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9200                                             Spacing * 2));
9201     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9202     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9203     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9204     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9205     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9206     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9207                                             Spacing));
9208     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9209                                             Spacing * 2));
9210     TmpInst.addOperand(Inst.getOperand(1)); // lane
9211     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9212     TmpInst.addOperand(Inst.getOperand(5));
9213     Inst = TmpInst;
9214     return true;
9215   }
9216 
9217   case ARM::VLD4LNdWB_fixed_Asm_8:
9218   case ARM::VLD4LNdWB_fixed_Asm_16:
9219   case ARM::VLD4LNdWB_fixed_Asm_32:
9220   case ARM::VLD4LNqWB_fixed_Asm_16:
9221   case ARM::VLD4LNqWB_fixed_Asm_32: {
9222     MCInst TmpInst;
9223     // Shuffle the operands around so the lane index operand is in the
9224     // right place.
9225     unsigned Spacing;
9226     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9227     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9228     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9229                                             Spacing));
9230     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9231                                             Spacing * 2));
9232     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9233                                             Spacing * 3));
9234     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
9235     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9236     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9237     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9238     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9239     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9240                                             Spacing));
9241     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9242                                             Spacing * 2));
9243     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9244                                             Spacing * 3));
9245     TmpInst.addOperand(Inst.getOperand(1)); // lane
9246     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9247     TmpInst.addOperand(Inst.getOperand(5));
9248     Inst = TmpInst;
9249     return true;
9250   }
9251 
9252   case ARM::VLD1LNdAsm_8:
9253   case ARM::VLD1LNdAsm_16:
9254   case ARM::VLD1LNdAsm_32: {
9255     MCInst TmpInst;
9256     // Shuffle the operands around so the lane index operand is in the
9257     // right place.
9258     unsigned Spacing;
9259     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9260     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9261     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9262     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9263     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9264     TmpInst.addOperand(Inst.getOperand(1)); // lane
9265     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9266     TmpInst.addOperand(Inst.getOperand(5));
9267     Inst = TmpInst;
9268     return true;
9269   }
9270 
9271   case ARM::VLD2LNdAsm_8:
9272   case ARM::VLD2LNdAsm_16:
9273   case ARM::VLD2LNdAsm_32:
9274   case ARM::VLD2LNqAsm_16:
9275   case ARM::VLD2LNqAsm_32: {
9276     MCInst TmpInst;
9277     // Shuffle the operands around so the lane index operand is in the
9278     // right place.
9279     unsigned Spacing;
9280     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9281     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9282     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9283                                             Spacing));
9284     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9285     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9286     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9287     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9288                                             Spacing));
9289     TmpInst.addOperand(Inst.getOperand(1)); // lane
9290     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9291     TmpInst.addOperand(Inst.getOperand(5));
9292     Inst = TmpInst;
9293     return true;
9294   }
9295 
9296   case ARM::VLD3LNdAsm_8:
9297   case ARM::VLD3LNdAsm_16:
9298   case ARM::VLD3LNdAsm_32:
9299   case ARM::VLD3LNqAsm_16:
9300   case ARM::VLD3LNqAsm_32: {
9301     MCInst TmpInst;
9302     // Shuffle the operands around so the lane index operand is in the
9303     // right place.
9304     unsigned Spacing;
9305     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9306     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9307     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9308                                             Spacing));
9309     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9310                                             Spacing * 2));
9311     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9312     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9313     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9314     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9315                                             Spacing));
9316     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9317                                             Spacing * 2));
9318     TmpInst.addOperand(Inst.getOperand(1)); // lane
9319     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9320     TmpInst.addOperand(Inst.getOperand(5));
9321     Inst = TmpInst;
9322     return true;
9323   }
9324 
9325   case ARM::VLD4LNdAsm_8:
9326   case ARM::VLD4LNdAsm_16:
9327   case ARM::VLD4LNdAsm_32:
9328   case ARM::VLD4LNqAsm_16:
9329   case ARM::VLD4LNqAsm_32: {
9330     MCInst TmpInst;
9331     // Shuffle the operands around so the lane index operand is in the
9332     // right place.
9333     unsigned Spacing;
9334     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9335     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9336     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9337                                             Spacing));
9338     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9339                                             Spacing * 2));
9340     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9341                                             Spacing * 3));
9342     TmpInst.addOperand(Inst.getOperand(2)); // Rn
9343     TmpInst.addOperand(Inst.getOperand(3)); // alignment
9344     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9345     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9346                                             Spacing));
9347     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9348                                             Spacing * 2));
9349     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9350                                             Spacing * 3));
9351     TmpInst.addOperand(Inst.getOperand(1)); // lane
9352     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9353     TmpInst.addOperand(Inst.getOperand(5));
9354     Inst = TmpInst;
9355     return true;
9356   }
9357 
9358   // VLD3DUP single 3-element structure to all lanes instructions.
9359   case ARM::VLD3DUPdAsm_8:
9360   case ARM::VLD3DUPdAsm_16:
9361   case ARM::VLD3DUPdAsm_32:
9362   case ARM::VLD3DUPqAsm_8:
9363   case ARM::VLD3DUPqAsm_16:
9364   case ARM::VLD3DUPqAsm_32: {
9365     MCInst TmpInst;
9366     unsigned Spacing;
9367     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9368     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9369     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9370                                             Spacing));
9371     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9372                                             Spacing * 2));
9373     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9374     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9375     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9376     TmpInst.addOperand(Inst.getOperand(4));
9377     Inst = TmpInst;
9378     return true;
9379   }
9380 
9381   case ARM::VLD3DUPdWB_fixed_Asm_8:
9382   case ARM::VLD3DUPdWB_fixed_Asm_16:
9383   case ARM::VLD3DUPdWB_fixed_Asm_32:
9384   case ARM::VLD3DUPqWB_fixed_Asm_8:
9385   case ARM::VLD3DUPqWB_fixed_Asm_16:
9386   case ARM::VLD3DUPqWB_fixed_Asm_32: {
9387     MCInst TmpInst;
9388     unsigned Spacing;
9389     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9390     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9391     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9392                                             Spacing));
9393     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9394                                             Spacing * 2));
9395     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9396     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9397     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9398     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9399     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9400     TmpInst.addOperand(Inst.getOperand(4));
9401     Inst = TmpInst;
9402     return true;
9403   }
9404 
9405   case ARM::VLD3DUPdWB_register_Asm_8:
9406   case ARM::VLD3DUPdWB_register_Asm_16:
9407   case ARM::VLD3DUPdWB_register_Asm_32:
9408   case ARM::VLD3DUPqWB_register_Asm_8:
9409   case ARM::VLD3DUPqWB_register_Asm_16:
9410   case ARM::VLD3DUPqWB_register_Asm_32: {
9411     MCInst TmpInst;
9412     unsigned Spacing;
9413     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9414     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9415     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9416                                             Spacing));
9417     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9418                                             Spacing * 2));
9419     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9420     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9421     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9422     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9423     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9424     TmpInst.addOperand(Inst.getOperand(5));
9425     Inst = TmpInst;
9426     return true;
9427   }
9428 
9429   // VLD3 multiple 3-element structure instructions.
9430   case ARM::VLD3dAsm_8:
9431   case ARM::VLD3dAsm_16:
9432   case ARM::VLD3dAsm_32:
9433   case ARM::VLD3qAsm_8:
9434   case ARM::VLD3qAsm_16:
9435   case ARM::VLD3qAsm_32: {
9436     MCInst TmpInst;
9437     unsigned Spacing;
9438     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9439     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9440     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9441                                             Spacing));
9442     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9443                                             Spacing * 2));
9444     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9445     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9446     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9447     TmpInst.addOperand(Inst.getOperand(4));
9448     Inst = TmpInst;
9449     return true;
9450   }
9451 
9452   case ARM::VLD3dWB_fixed_Asm_8:
9453   case ARM::VLD3dWB_fixed_Asm_16:
9454   case ARM::VLD3dWB_fixed_Asm_32:
9455   case ARM::VLD3qWB_fixed_Asm_8:
9456   case ARM::VLD3qWB_fixed_Asm_16:
9457   case ARM::VLD3qWB_fixed_Asm_32: {
9458     MCInst TmpInst;
9459     unsigned Spacing;
9460     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9461     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9462     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9463                                             Spacing));
9464     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9465                                             Spacing * 2));
9466     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9467     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9468     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9469     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9470     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9471     TmpInst.addOperand(Inst.getOperand(4));
9472     Inst = TmpInst;
9473     return true;
9474   }
9475 
9476   case ARM::VLD3dWB_register_Asm_8:
9477   case ARM::VLD3dWB_register_Asm_16:
9478   case ARM::VLD3dWB_register_Asm_32:
9479   case ARM::VLD3qWB_register_Asm_8:
9480   case ARM::VLD3qWB_register_Asm_16:
9481   case ARM::VLD3qWB_register_Asm_32: {
9482     MCInst TmpInst;
9483     unsigned Spacing;
9484     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9485     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9486     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9487                                             Spacing));
9488     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9489                                             Spacing * 2));
9490     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9491     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9492     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9493     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9494     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9495     TmpInst.addOperand(Inst.getOperand(5));
9496     Inst = TmpInst;
9497     return true;
9498   }
9499 
9500   // VLD4DUP single 3-element structure to all lanes instructions.
9501   case ARM::VLD4DUPdAsm_8:
9502   case ARM::VLD4DUPdAsm_16:
9503   case ARM::VLD4DUPdAsm_32:
9504   case ARM::VLD4DUPqAsm_8:
9505   case ARM::VLD4DUPqAsm_16:
9506   case ARM::VLD4DUPqAsm_32: {
9507     MCInst TmpInst;
9508     unsigned Spacing;
9509     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9510     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9511     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9512                                             Spacing));
9513     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9514                                             Spacing * 2));
9515     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9516                                             Spacing * 3));
9517     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9518     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9519     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9520     TmpInst.addOperand(Inst.getOperand(4));
9521     Inst = TmpInst;
9522     return true;
9523   }
9524 
9525   case ARM::VLD4DUPdWB_fixed_Asm_8:
9526   case ARM::VLD4DUPdWB_fixed_Asm_16:
9527   case ARM::VLD4DUPdWB_fixed_Asm_32:
9528   case ARM::VLD4DUPqWB_fixed_Asm_8:
9529   case ARM::VLD4DUPqWB_fixed_Asm_16:
9530   case ARM::VLD4DUPqWB_fixed_Asm_32: {
9531     MCInst TmpInst;
9532     unsigned Spacing;
9533     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9534     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9535     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9536                                             Spacing));
9537     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9538                                             Spacing * 2));
9539     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9540                                             Spacing * 3));
9541     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9542     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9543     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9544     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9545     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9546     TmpInst.addOperand(Inst.getOperand(4));
9547     Inst = TmpInst;
9548     return true;
9549   }
9550 
9551   case ARM::VLD4DUPdWB_register_Asm_8:
9552   case ARM::VLD4DUPdWB_register_Asm_16:
9553   case ARM::VLD4DUPdWB_register_Asm_32:
9554   case ARM::VLD4DUPqWB_register_Asm_8:
9555   case ARM::VLD4DUPqWB_register_Asm_16:
9556   case ARM::VLD4DUPqWB_register_Asm_32: {
9557     MCInst TmpInst;
9558     unsigned Spacing;
9559     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9560     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9561     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9562                                             Spacing));
9563     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9564                                             Spacing * 2));
9565     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9566                                             Spacing * 3));
9567     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9568     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9569     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9570     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9571     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9572     TmpInst.addOperand(Inst.getOperand(5));
9573     Inst = TmpInst;
9574     return true;
9575   }
9576 
9577   // VLD4 multiple 4-element structure instructions.
9578   case ARM::VLD4dAsm_8:
9579   case ARM::VLD4dAsm_16:
9580   case ARM::VLD4dAsm_32:
9581   case ARM::VLD4qAsm_8:
9582   case ARM::VLD4qAsm_16:
9583   case ARM::VLD4qAsm_32: {
9584     MCInst TmpInst;
9585     unsigned Spacing;
9586     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9587     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9588     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9589                                             Spacing));
9590     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9591                                             Spacing * 2));
9592     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9593                                             Spacing * 3));
9594     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9595     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9596     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9597     TmpInst.addOperand(Inst.getOperand(4));
9598     Inst = TmpInst;
9599     return true;
9600   }
9601 
9602   case ARM::VLD4dWB_fixed_Asm_8:
9603   case ARM::VLD4dWB_fixed_Asm_16:
9604   case ARM::VLD4dWB_fixed_Asm_32:
9605   case ARM::VLD4qWB_fixed_Asm_8:
9606   case ARM::VLD4qWB_fixed_Asm_16:
9607   case ARM::VLD4qWB_fixed_Asm_32: {
9608     MCInst TmpInst;
9609     unsigned Spacing;
9610     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9611     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9612     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9613                                             Spacing));
9614     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9615                                             Spacing * 2));
9616     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9617                                             Spacing * 3));
9618     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9619     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9620     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9621     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9622     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9623     TmpInst.addOperand(Inst.getOperand(4));
9624     Inst = TmpInst;
9625     return true;
9626   }
9627 
9628   case ARM::VLD4dWB_register_Asm_8:
9629   case ARM::VLD4dWB_register_Asm_16:
9630   case ARM::VLD4dWB_register_Asm_32:
9631   case ARM::VLD4qWB_register_Asm_8:
9632   case ARM::VLD4qWB_register_Asm_16:
9633   case ARM::VLD4qWB_register_Asm_32: {
9634     MCInst TmpInst;
9635     unsigned Spacing;
9636     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9637     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9638     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9639                                             Spacing));
9640     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9641                                             Spacing * 2));
9642     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9643                                             Spacing * 3));
9644     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9645     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9646     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9647     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9648     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9649     TmpInst.addOperand(Inst.getOperand(5));
9650     Inst = TmpInst;
9651     return true;
9652   }
9653 
9654   // VST3 multiple 3-element structure instructions.
9655   case ARM::VST3dAsm_8:
9656   case ARM::VST3dAsm_16:
9657   case ARM::VST3dAsm_32:
9658   case ARM::VST3qAsm_8:
9659   case ARM::VST3qAsm_16:
9660   case ARM::VST3qAsm_32: {
9661     MCInst TmpInst;
9662     unsigned Spacing;
9663     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9664     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9665     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9666     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9667     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9668                                             Spacing));
9669     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9670                                             Spacing * 2));
9671     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9672     TmpInst.addOperand(Inst.getOperand(4));
9673     Inst = TmpInst;
9674     return true;
9675   }
9676 
9677   case ARM::VST3dWB_fixed_Asm_8:
9678   case ARM::VST3dWB_fixed_Asm_16:
9679   case ARM::VST3dWB_fixed_Asm_32:
9680   case ARM::VST3qWB_fixed_Asm_8:
9681   case ARM::VST3qWB_fixed_Asm_16:
9682   case ARM::VST3qWB_fixed_Asm_32: {
9683     MCInst TmpInst;
9684     unsigned Spacing;
9685     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9686     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9687     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9688     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9689     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9690     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9691     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9692                                             Spacing));
9693     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9694                                             Spacing * 2));
9695     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9696     TmpInst.addOperand(Inst.getOperand(4));
9697     Inst = TmpInst;
9698     return true;
9699   }
9700 
9701   case ARM::VST3dWB_register_Asm_8:
9702   case ARM::VST3dWB_register_Asm_16:
9703   case ARM::VST3dWB_register_Asm_32:
9704   case ARM::VST3qWB_register_Asm_8:
9705   case ARM::VST3qWB_register_Asm_16:
9706   case ARM::VST3qWB_register_Asm_32: {
9707     MCInst TmpInst;
9708     unsigned Spacing;
9709     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9710     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9711     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9712     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9713     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9714     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9715     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9716                                             Spacing));
9717     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9718                                             Spacing * 2));
9719     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9720     TmpInst.addOperand(Inst.getOperand(5));
9721     Inst = TmpInst;
9722     return true;
9723   }
9724 
9725   // VST4 multiple 3-element structure instructions.
9726   case ARM::VST4dAsm_8:
9727   case ARM::VST4dAsm_16:
9728   case ARM::VST4dAsm_32:
9729   case ARM::VST4qAsm_8:
9730   case ARM::VST4qAsm_16:
9731   case ARM::VST4qAsm_32: {
9732     MCInst TmpInst;
9733     unsigned Spacing;
9734     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9735     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9736     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9737     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9738     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9739                                             Spacing));
9740     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9741                                             Spacing * 2));
9742     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9743                                             Spacing * 3));
9744     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9745     TmpInst.addOperand(Inst.getOperand(4));
9746     Inst = TmpInst;
9747     return true;
9748   }
9749 
9750   case ARM::VST4dWB_fixed_Asm_8:
9751   case ARM::VST4dWB_fixed_Asm_16:
9752   case ARM::VST4dWB_fixed_Asm_32:
9753   case ARM::VST4qWB_fixed_Asm_8:
9754   case ARM::VST4qWB_fixed_Asm_16:
9755   case ARM::VST4qWB_fixed_Asm_32: {
9756     MCInst TmpInst;
9757     unsigned Spacing;
9758     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9759     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9760     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9761     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9762     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9763     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9764     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9765                                             Spacing));
9766     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9767                                             Spacing * 2));
9768     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9769                                             Spacing * 3));
9770     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9771     TmpInst.addOperand(Inst.getOperand(4));
9772     Inst = TmpInst;
9773     return true;
9774   }
9775 
9776   case ARM::VST4dWB_register_Asm_8:
9777   case ARM::VST4dWB_register_Asm_16:
9778   case ARM::VST4dWB_register_Asm_32:
9779   case ARM::VST4qWB_register_Asm_8:
9780   case ARM::VST4qWB_register_Asm_16:
9781   case ARM::VST4qWB_register_Asm_32: {
9782     MCInst TmpInst;
9783     unsigned Spacing;
9784     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9785     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9786     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9787     TmpInst.addOperand(Inst.getOperand(2)); // alignment
9788     TmpInst.addOperand(Inst.getOperand(3)); // Rm
9789     TmpInst.addOperand(Inst.getOperand(0)); // Vd
9790     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9791                                             Spacing));
9792     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9793                                             Spacing * 2));
9794     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9795                                             Spacing * 3));
9796     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9797     TmpInst.addOperand(Inst.getOperand(5));
9798     Inst = TmpInst;
9799     return true;
9800   }
9801 
9802   // Handle encoding choice for the shift-immediate instructions.
9803   case ARM::t2LSLri:
9804   case ARM::t2LSRri:
9805   case ARM::t2ASRri:
9806     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9807         isARMLowRegister(Inst.getOperand(1).getReg()) &&
9808         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9809         !HasWideQualifier) {
9810       unsigned NewOpc;
9811       switch (Inst.getOpcode()) {
9812       default: llvm_unreachable("unexpected opcode");
9813       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9814       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
9815       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
9816       }
9817       // The Thumb1 operands aren't in the same order. Awesome, eh?
9818       MCInst TmpInst;
9819       TmpInst.setOpcode(NewOpc);
9820       TmpInst.addOperand(Inst.getOperand(0));
9821       TmpInst.addOperand(Inst.getOperand(5));
9822       TmpInst.addOperand(Inst.getOperand(1));
9823       TmpInst.addOperand(Inst.getOperand(2));
9824       TmpInst.addOperand(Inst.getOperand(3));
9825       TmpInst.addOperand(Inst.getOperand(4));
9826       Inst = TmpInst;
9827       return true;
9828     }
9829     return false;
9830 
9831   // Handle the Thumb2 mode MOV complex aliases.
9832   case ARM::t2MOVsr:
9833   case ARM::t2MOVSsr: {
9834     // Which instruction to expand to depends on the CCOut operand and
9835     // whether we're in an IT block if the register operands are low
9836     // registers.
9837     bool isNarrow = false;
9838     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9839         isARMLowRegister(Inst.getOperand(1).getReg()) &&
9840         isARMLowRegister(Inst.getOperand(2).getReg()) &&
9841         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
9842         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
9843         !HasWideQualifier)
9844       isNarrow = true;
9845     MCInst TmpInst;
9846     unsigned newOpc;
9847     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
9848     default: llvm_unreachable("unexpected opcode!");
9849     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
9850     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
9851     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
9852     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
9853     }
9854     TmpInst.setOpcode(newOpc);
9855     TmpInst.addOperand(Inst.getOperand(0)); // Rd
9856     if (isNarrow)
9857       TmpInst.addOperand(MCOperand::createReg(
9858           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9859     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9860     TmpInst.addOperand(Inst.getOperand(2)); // Rm
9861     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9862     TmpInst.addOperand(Inst.getOperand(5));
9863     if (!isNarrow)
9864       TmpInst.addOperand(MCOperand::createReg(
9865           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9866     Inst = TmpInst;
9867     return true;
9868   }
9869   case ARM::t2MOVsi:
9870   case ARM::t2MOVSsi: {
9871     // Which instruction to expand to depends on the CCOut operand and
9872     // whether we're in an IT block if the register operands are low
9873     // registers.
9874     bool isNarrow = false;
9875     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9876         isARMLowRegister(Inst.getOperand(1).getReg()) &&
9877         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
9878         !HasWideQualifier)
9879       isNarrow = true;
9880     MCInst TmpInst;
9881     unsigned newOpc;
9882     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
9883     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
9884     bool isMov = false;
9885     // MOV rd, rm, LSL #0 is actually a MOV instruction
9886     if (Shift == ARM_AM::lsl && Amount == 0) {
9887       isMov = true;
9888       // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
9889       // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
9890       // unpredictable in an IT block so the 32-bit encoding T3 has to be used
9891       // instead.
9892       if (inITBlock()) {
9893         isNarrow = false;
9894       }
9895       newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
9896     } else {
9897       switch(Shift) {
9898       default: llvm_unreachable("unexpected opcode!");
9899       case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
9900       case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
9901       case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
9902       case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
9903       case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
9904       }
9905     }
9906     if (Amount == 32) Amount = 0;
9907     TmpInst.setOpcode(newOpc);
9908     TmpInst.addOperand(Inst.getOperand(0)); // Rd
9909     if (isNarrow && !isMov)
9910       TmpInst.addOperand(MCOperand::createReg(
9911           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9912     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9913     if (newOpc != ARM::t2RRX && !isMov)
9914       TmpInst.addOperand(MCOperand::createImm(Amount));
9915     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9916     TmpInst.addOperand(Inst.getOperand(4));
9917     if (!isNarrow)
9918       TmpInst.addOperand(MCOperand::createReg(
9919           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9920     Inst = TmpInst;
9921     return true;
9922   }
9923   // Handle the ARM mode MOV complex aliases.
9924   case ARM::ASRr:
9925   case ARM::LSRr:
9926   case ARM::LSLr:
9927   case ARM::RORr: {
9928     ARM_AM::ShiftOpc ShiftTy;
9929     switch(Inst.getOpcode()) {
9930     default: llvm_unreachable("unexpected opcode!");
9931     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
9932     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
9933     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
9934     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
9935     }
9936     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
9937     MCInst TmpInst;
9938     TmpInst.setOpcode(ARM::MOVsr);
9939     TmpInst.addOperand(Inst.getOperand(0)); // Rd
9940     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9941     TmpInst.addOperand(Inst.getOperand(2)); // Rm
9942     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9943     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9944     TmpInst.addOperand(Inst.getOperand(4));
9945     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9946     Inst = TmpInst;
9947     return true;
9948   }
9949   case ARM::ASRi:
9950   case ARM::LSRi:
9951   case ARM::LSLi:
9952   case ARM::RORi: {
9953     ARM_AM::ShiftOpc ShiftTy;
9954     switch(Inst.getOpcode()) {
9955     default: llvm_unreachable("unexpected opcode!");
9956     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
9957     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
9958     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
9959     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
9960     }
9961     // A shift by zero is a plain MOVr, not a MOVsi.
9962     unsigned Amt = Inst.getOperand(2).getImm();
9963     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
9964     // A shift by 32 should be encoded as 0 when permitted
9965     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
9966       Amt = 0;
9967     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
9968     MCInst TmpInst;
9969     TmpInst.setOpcode(Opc);
9970     TmpInst.addOperand(Inst.getOperand(0)); // Rd
9971     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9972     if (Opc == ARM::MOVsi)
9973       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9974     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9975     TmpInst.addOperand(Inst.getOperand(4));
9976     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9977     Inst = TmpInst;
9978     return true;
9979   }
9980   case ARM::RRXi: {
9981     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
9982     MCInst TmpInst;
9983     TmpInst.setOpcode(ARM::MOVsi);
9984     TmpInst.addOperand(Inst.getOperand(0)); // Rd
9985     TmpInst.addOperand(Inst.getOperand(1)); // Rn
9986     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9987     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9988     TmpInst.addOperand(Inst.getOperand(3));
9989     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
9990     Inst = TmpInst;
9991     return true;
9992   }
9993   case ARM::t2LDMIA_UPD: {
9994     // If this is a load of a single register, then we should use
9995     // a post-indexed LDR instruction instead, per the ARM ARM.
9996     if (Inst.getNumOperands() != 5)
9997       return false;
9998     MCInst TmpInst;
9999     TmpInst.setOpcode(ARM::t2LDR_POST);
10000     TmpInst.addOperand(Inst.getOperand(4)); // Rt
10001     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10002     TmpInst.addOperand(Inst.getOperand(1)); // Rn
10003     TmpInst.addOperand(MCOperand::createImm(4));
10004     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10005     TmpInst.addOperand(Inst.getOperand(3));
10006     Inst = TmpInst;
10007     return true;
10008   }
10009   case ARM::t2STMDB_UPD: {
10010     // If this is a store of a single register, then we should use
10011     // a pre-indexed STR instruction instead, per the ARM ARM.
10012     if (Inst.getNumOperands() != 5)
10013       return false;
10014     MCInst TmpInst;
10015     TmpInst.setOpcode(ARM::t2STR_PRE);
10016     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10017     TmpInst.addOperand(Inst.getOperand(4)); // Rt
10018     TmpInst.addOperand(Inst.getOperand(1)); // Rn
10019     TmpInst.addOperand(MCOperand::createImm(-4));
10020     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10021     TmpInst.addOperand(Inst.getOperand(3));
10022     Inst = TmpInst;
10023     return true;
10024   }
10025   case ARM::LDMIA_UPD:
10026     // If this is a load of a single register via a 'pop', then we should use
10027     // a post-indexed LDR instruction instead, per the ARM ARM.
10028     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
10029         Inst.getNumOperands() == 5) {
10030       MCInst TmpInst;
10031       TmpInst.setOpcode(ARM::LDR_POST_IMM);
10032       TmpInst.addOperand(Inst.getOperand(4)); // Rt
10033       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10034       TmpInst.addOperand(Inst.getOperand(1)); // Rn
10035       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
10036       TmpInst.addOperand(MCOperand::createImm(4));
10037       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10038       TmpInst.addOperand(Inst.getOperand(3));
10039       Inst = TmpInst;
10040       return true;
10041     }
10042     break;
10043   case ARM::STMDB_UPD:
10044     // If this is a store of a single register via a 'push', then we should use
10045     // a pre-indexed STR instruction instead, per the ARM ARM.
10046     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
10047         Inst.getNumOperands() == 5) {
10048       MCInst TmpInst;
10049       TmpInst.setOpcode(ARM::STR_PRE_IMM);
10050       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
10051       TmpInst.addOperand(Inst.getOperand(4)); // Rt
10052       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
10053       TmpInst.addOperand(MCOperand::createImm(-4));
10054       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
10055       TmpInst.addOperand(Inst.getOperand(3));
10056       Inst = TmpInst;
10057     }
10058     break;
10059   case ARM::t2ADDri12:
10060   case ARM::t2SUBri12:
10061   case ARM::t2ADDspImm12:
10062   case ARM::t2SUBspImm12: {
10063     // If the immediate fits for encoding T3 and the generic
10064     // mnemonic was used, encoding T3 is preferred.
10065     const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken();
10066     if ((Token != "add" && Token != "sub") ||
10067         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
10068       break;
10069     switch (Inst.getOpcode()) {
10070     case ARM::t2ADDri12:
10071       Inst.setOpcode(ARM::t2ADDri);
10072       break;
10073     case ARM::t2SUBri12:
10074       Inst.setOpcode(ARM::t2SUBri);
10075       break;
10076     case ARM::t2ADDspImm12:
10077       Inst.setOpcode(ARM::t2ADDspImm);
10078       break;
10079     case ARM::t2SUBspImm12:
10080       Inst.setOpcode(ARM::t2SUBspImm);
10081       break;
10082     }
10083 
10084     Inst.addOperand(MCOperand::createReg(0)); // cc_out
10085     return true;
10086   }
10087   case ARM::tADDi8:
10088     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10089     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10090     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10091     // to encoding T1 if <Rd> is omitted."
10092     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10093       Inst.setOpcode(ARM::tADDi3);
10094       return true;
10095     }
10096     break;
10097   case ARM::tSUBi8:
10098     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
10099     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
10100     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
10101     // to encoding T1 if <Rd> is omitted."
10102     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
10103       Inst.setOpcode(ARM::tSUBi3);
10104       return true;
10105     }
10106     break;
10107   case ARM::t2ADDri:
10108   case ARM::t2SUBri: {
10109     // If the destination and first source operand are the same, and
10110     // the flags are compatible with the current IT status, use encoding T2
10111     // instead of T3. For compatibility with the system 'as'. Make sure the
10112     // wide encoding wasn't explicit.
10113     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
10114         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
10115         (Inst.getOperand(2).isImm() &&
10116          (unsigned)Inst.getOperand(2).getImm() > 255) ||
10117         Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
10118         HasWideQualifier)
10119       break;
10120     MCInst TmpInst;
10121     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
10122                       ARM::tADDi8 : ARM::tSUBi8);
10123     TmpInst.addOperand(Inst.getOperand(0));
10124     TmpInst.addOperand(Inst.getOperand(5));
10125     TmpInst.addOperand(Inst.getOperand(0));
10126     TmpInst.addOperand(Inst.getOperand(2));
10127     TmpInst.addOperand(Inst.getOperand(3));
10128     TmpInst.addOperand(Inst.getOperand(4));
10129     Inst = TmpInst;
10130     return true;
10131   }
10132   case ARM::t2ADDspImm:
10133   case ARM::t2SUBspImm: {
10134     // Prefer T1 encoding if possible
10135     if (Inst.getOperand(5).getReg() != 0 || HasWideQualifier)
10136       break;
10137     unsigned V = Inst.getOperand(2).getImm();
10138     if (V & 3 || V > ((1 << 7) - 1) << 2)
10139       break;
10140     MCInst TmpInst;
10141     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDspImm ? ARM::tADDspi
10142                                                           : ARM::tSUBspi);
10143     TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // destination reg
10144     TmpInst.addOperand(MCOperand::createReg(ARM::SP)); // source reg
10145     TmpInst.addOperand(MCOperand::createImm(V / 4));   // immediate
10146     TmpInst.addOperand(Inst.getOperand(3));            // pred
10147     TmpInst.addOperand(Inst.getOperand(4));
10148     Inst = TmpInst;
10149     return true;
10150   }
10151   case ARM::t2ADDrr: {
10152     // If the destination and first source operand are the same, and
10153     // there's no setting of the flags, use encoding T2 instead of T3.
10154     // Note that this is only for ADD, not SUB. This mirrors the system
10155     // 'as' behaviour.  Also take advantage of ADD being commutative.
10156     // Make sure the wide encoding wasn't explicit.
10157     bool Swap = false;
10158     auto DestReg = Inst.getOperand(0).getReg();
10159     bool Transform = DestReg == Inst.getOperand(1).getReg();
10160     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
10161       Transform = true;
10162       Swap = true;
10163     }
10164     if (!Transform ||
10165         Inst.getOperand(5).getReg() != 0 ||
10166         HasWideQualifier)
10167       break;
10168     MCInst TmpInst;
10169     TmpInst.setOpcode(ARM::tADDhirr);
10170     TmpInst.addOperand(Inst.getOperand(0));
10171     TmpInst.addOperand(Inst.getOperand(0));
10172     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
10173     TmpInst.addOperand(Inst.getOperand(3));
10174     TmpInst.addOperand(Inst.getOperand(4));
10175     Inst = TmpInst;
10176     return true;
10177   }
10178   case ARM::tADDrSP:
10179     // If the non-SP source operand and the destination operand are not the
10180     // same, we need to use the 32-bit encoding if it's available.
10181     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
10182       Inst.setOpcode(ARM::t2ADDrr);
10183       Inst.addOperand(MCOperand::createReg(0)); // cc_out
10184       return true;
10185     }
10186     break;
10187   case ARM::tB:
10188     // A Thumb conditional branch outside of an IT block is a tBcc.
10189     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
10190       Inst.setOpcode(ARM::tBcc);
10191       return true;
10192     }
10193     break;
10194   case ARM::t2B:
10195     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
10196     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
10197       Inst.setOpcode(ARM::t2Bcc);
10198       return true;
10199     }
10200     break;
10201   case ARM::t2Bcc:
10202     // If the conditional is AL or we're in an IT block, we really want t2B.
10203     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
10204       Inst.setOpcode(ARM::t2B);
10205       return true;
10206     }
10207     break;
10208   case ARM::tBcc:
10209     // If the conditional is AL, we really want tB.
10210     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
10211       Inst.setOpcode(ARM::tB);
10212       return true;
10213     }
10214     break;
10215   case ARM::tLDMIA: {
10216     // If the register list contains any high registers, or if the writeback
10217     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
10218     // instead if we're in Thumb2. Otherwise, this should have generated
10219     // an error in validateInstruction().
10220     unsigned Rn = Inst.getOperand(0).getReg();
10221     bool hasWritebackToken =
10222         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
10223          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
10224     bool listContainsBase;
10225     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
10226         (!listContainsBase && !hasWritebackToken) ||
10227         (listContainsBase && hasWritebackToken)) {
10228       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10229       assert(isThumbTwo());
10230       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
10231       // If we're switching to the updating version, we need to insert
10232       // the writeback tied operand.
10233       if (hasWritebackToken)
10234         Inst.insert(Inst.begin(),
10235                     MCOperand::createReg(Inst.getOperand(0).getReg()));
10236       return true;
10237     }
10238     break;
10239   }
10240   case ARM::tSTMIA_UPD: {
10241     // If the register list contains any high registers, we need to use
10242     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10243     // should have generated an error in validateInstruction().
10244     unsigned Rn = Inst.getOperand(0).getReg();
10245     bool listContainsBase;
10246     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
10247       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
10248       assert(isThumbTwo());
10249       Inst.setOpcode(ARM::t2STMIA_UPD);
10250       return true;
10251     }
10252     break;
10253   }
10254   case ARM::tPOP: {
10255     bool listContainsBase;
10256     // If the register list contains any high registers, we need to use
10257     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
10258     // should have generated an error in validateInstruction().
10259     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
10260       return false;
10261     assert(isThumbTwo());
10262     Inst.setOpcode(ARM::t2LDMIA_UPD);
10263     // Add the base register and writeback operands.
10264     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10265     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10266     return true;
10267   }
10268   case ARM::tPUSH: {
10269     bool listContainsBase;
10270     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
10271       return false;
10272     assert(isThumbTwo());
10273     Inst.setOpcode(ARM::t2STMDB_UPD);
10274     // Add the base register and writeback operands.
10275     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10276     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10277     return true;
10278   }
10279   case ARM::t2MOVi:
10280     // If we can use the 16-bit encoding and the user didn't explicitly
10281     // request the 32-bit variant, transform it here.
10282     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10283         (Inst.getOperand(1).isImm() &&
10284          (unsigned)Inst.getOperand(1).getImm() <= 255) &&
10285         Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10286         !HasWideQualifier) {
10287       // The operands aren't in the same order for tMOVi8...
10288       MCInst TmpInst;
10289       TmpInst.setOpcode(ARM::tMOVi8);
10290       TmpInst.addOperand(Inst.getOperand(0));
10291       TmpInst.addOperand(Inst.getOperand(4));
10292       TmpInst.addOperand(Inst.getOperand(1));
10293       TmpInst.addOperand(Inst.getOperand(2));
10294       TmpInst.addOperand(Inst.getOperand(3));
10295       Inst = TmpInst;
10296       return true;
10297     }
10298     break;
10299 
10300   case ARM::t2MOVr:
10301     // If we can use the 16-bit encoding and the user didn't explicitly
10302     // request the 32-bit variant, transform it here.
10303     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10304         isARMLowRegister(Inst.getOperand(1).getReg()) &&
10305         Inst.getOperand(2).getImm() == ARMCC::AL &&
10306         Inst.getOperand(4).getReg() == ARM::CPSR &&
10307         !HasWideQualifier) {
10308       // The operands aren't the same for tMOV[S]r... (no cc_out)
10309       MCInst TmpInst;
10310       unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
10311       TmpInst.setOpcode(Op);
10312       TmpInst.addOperand(Inst.getOperand(0));
10313       TmpInst.addOperand(Inst.getOperand(1));
10314       if (Op == ARM::tMOVr) {
10315         TmpInst.addOperand(Inst.getOperand(2));
10316         TmpInst.addOperand(Inst.getOperand(3));
10317       }
10318       Inst = TmpInst;
10319       return true;
10320     }
10321     break;
10322 
10323   case ARM::t2SXTH:
10324   case ARM::t2SXTB:
10325   case ARM::t2UXTH:
10326   case ARM::t2UXTB:
10327     // If we can use the 16-bit encoding and the user didn't explicitly
10328     // request the 32-bit variant, transform it here.
10329     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
10330         isARMLowRegister(Inst.getOperand(1).getReg()) &&
10331         Inst.getOperand(2).getImm() == 0 &&
10332         !HasWideQualifier) {
10333       unsigned NewOpc;
10334       switch (Inst.getOpcode()) {
10335       default: llvm_unreachable("Illegal opcode!");
10336       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
10337       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
10338       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
10339       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
10340       }
10341       // The operands aren't the same for thumb1 (no rotate operand).
10342       MCInst TmpInst;
10343       TmpInst.setOpcode(NewOpc);
10344       TmpInst.addOperand(Inst.getOperand(0));
10345       TmpInst.addOperand(Inst.getOperand(1));
10346       TmpInst.addOperand(Inst.getOperand(3));
10347       TmpInst.addOperand(Inst.getOperand(4));
10348       Inst = TmpInst;
10349       return true;
10350     }
10351     break;
10352 
10353   case ARM::MOVsi: {
10354     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10355     // rrx shifts and asr/lsr of #32 is encoded as 0
10356     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10357       return false;
10358     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10359       // Shifting by zero is accepted as a vanilla 'MOVr'
10360       MCInst TmpInst;
10361       TmpInst.setOpcode(ARM::MOVr);
10362       TmpInst.addOperand(Inst.getOperand(0));
10363       TmpInst.addOperand(Inst.getOperand(1));
10364       TmpInst.addOperand(Inst.getOperand(3));
10365       TmpInst.addOperand(Inst.getOperand(4));
10366       TmpInst.addOperand(Inst.getOperand(5));
10367       Inst = TmpInst;
10368       return true;
10369     }
10370     return false;
10371   }
10372   case ARM::ANDrsi:
10373   case ARM::ORRrsi:
10374   case ARM::EORrsi:
10375   case ARM::BICrsi:
10376   case ARM::SUBrsi:
10377   case ARM::ADDrsi: {
10378     unsigned newOpc;
10379     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10380     if (SOpc == ARM_AM::rrx) return false;
10381     switch (Inst.getOpcode()) {
10382     default: llvm_unreachable("unexpected opcode!");
10383     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
10384     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
10385     case ARM::EORrsi: newOpc = ARM::EORrr; break;
10386     case ARM::BICrsi: newOpc = ARM::BICrr; break;
10387     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
10388     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
10389     }
10390     // If the shift is by zero, use the non-shifted instruction definition.
10391     // The exception is for right shifts, where 0 == 32
10392     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10393         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
10394       MCInst TmpInst;
10395       TmpInst.setOpcode(newOpc);
10396       TmpInst.addOperand(Inst.getOperand(0));
10397       TmpInst.addOperand(Inst.getOperand(1));
10398       TmpInst.addOperand(Inst.getOperand(2));
10399       TmpInst.addOperand(Inst.getOperand(4));
10400       TmpInst.addOperand(Inst.getOperand(5));
10401       TmpInst.addOperand(Inst.getOperand(6));
10402       Inst = TmpInst;
10403       return true;
10404     }
10405     return false;
10406   }
10407   case ARM::ITasm:
10408   case ARM::t2IT: {
10409     // Set up the IT block state according to the IT instruction we just
10410     // matched.
10411     assert(!inITBlock() && "nested IT blocks?!");
10412     startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
10413                          Inst.getOperand(1).getImm());
10414     break;
10415   }
10416   case ARM::t2LSLrr:
10417   case ARM::t2LSRrr:
10418   case ARM::t2ASRrr:
10419   case ARM::t2SBCrr:
10420   case ARM::t2RORrr:
10421   case ARM::t2BICrr:
10422     // Assemblers should use the narrow encodings of these instructions when permissible.
10423     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10424          isARMLowRegister(Inst.getOperand(2).getReg())) &&
10425         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10426         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10427         !HasWideQualifier) {
10428       unsigned NewOpc;
10429       switch (Inst.getOpcode()) {
10430         default: llvm_unreachable("unexpected opcode");
10431         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
10432         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
10433         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
10434         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
10435         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
10436         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
10437       }
10438       MCInst TmpInst;
10439       TmpInst.setOpcode(NewOpc);
10440       TmpInst.addOperand(Inst.getOperand(0));
10441       TmpInst.addOperand(Inst.getOperand(5));
10442       TmpInst.addOperand(Inst.getOperand(1));
10443       TmpInst.addOperand(Inst.getOperand(2));
10444       TmpInst.addOperand(Inst.getOperand(3));
10445       TmpInst.addOperand(Inst.getOperand(4));
10446       Inst = TmpInst;
10447       return true;
10448     }
10449     return false;
10450 
10451   case ARM::t2ANDrr:
10452   case ARM::t2EORrr:
10453   case ARM::t2ADCrr:
10454   case ARM::t2ORRrr:
10455     // Assemblers should use the narrow encodings of these instructions when permissible.
10456     // These instructions are special in that they are commutable, so shorter encodings
10457     // are available more often.
10458     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10459          isARMLowRegister(Inst.getOperand(2).getReg())) &&
10460         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
10461          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
10462         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10463         !HasWideQualifier) {
10464       unsigned NewOpc;
10465       switch (Inst.getOpcode()) {
10466         default: llvm_unreachable("unexpected opcode");
10467         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
10468         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
10469         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
10470         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
10471       }
10472       MCInst TmpInst;
10473       TmpInst.setOpcode(NewOpc);
10474       TmpInst.addOperand(Inst.getOperand(0));
10475       TmpInst.addOperand(Inst.getOperand(5));
10476       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
10477         TmpInst.addOperand(Inst.getOperand(1));
10478         TmpInst.addOperand(Inst.getOperand(2));
10479       } else {
10480         TmpInst.addOperand(Inst.getOperand(2));
10481         TmpInst.addOperand(Inst.getOperand(1));
10482       }
10483       TmpInst.addOperand(Inst.getOperand(3));
10484       TmpInst.addOperand(Inst.getOperand(4));
10485       Inst = TmpInst;
10486       return true;
10487     }
10488     return false;
10489   case ARM::MVE_VPST:
10490   case ARM::MVE_VPTv16i8:
10491   case ARM::MVE_VPTv8i16:
10492   case ARM::MVE_VPTv4i32:
10493   case ARM::MVE_VPTv16u8:
10494   case ARM::MVE_VPTv8u16:
10495   case ARM::MVE_VPTv4u32:
10496   case ARM::MVE_VPTv16s8:
10497   case ARM::MVE_VPTv8s16:
10498   case ARM::MVE_VPTv4s32:
10499   case ARM::MVE_VPTv4f32:
10500   case ARM::MVE_VPTv8f16:
10501   case ARM::MVE_VPTv16i8r:
10502   case ARM::MVE_VPTv8i16r:
10503   case ARM::MVE_VPTv4i32r:
10504   case ARM::MVE_VPTv16u8r:
10505   case ARM::MVE_VPTv8u16r:
10506   case ARM::MVE_VPTv4u32r:
10507   case ARM::MVE_VPTv16s8r:
10508   case ARM::MVE_VPTv8s16r:
10509   case ARM::MVE_VPTv4s32r:
10510   case ARM::MVE_VPTv4f32r:
10511   case ARM::MVE_VPTv8f16r: {
10512     assert(!inVPTBlock() && "Nested VPT blocks are not allowed");
10513     MCOperand &MO = Inst.getOperand(0);
10514     VPTState.Mask = MO.getImm();
10515     VPTState.CurPosition = 0;
10516     break;
10517   }
10518   }
10519   return false;
10520 }
10521 
10522 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10523   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
10524   // suffix depending on whether they're in an IT block or not.
10525   unsigned Opc = Inst.getOpcode();
10526   const MCInstrDesc &MCID = MII.get(Opc);
10527   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
10528     assert(MCID.hasOptionalDef() &&
10529            "optionally flag setting instruction missing optional def operand");
10530     assert(MCID.NumOperands == Inst.getNumOperands() &&
10531            "operand count mismatch!");
10532     // Find the optional-def operand (cc_out).
10533     unsigned OpNo;
10534     for (OpNo = 0;
10535          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10536          ++OpNo)
10537       ;
10538     // If we're parsing Thumb1, reject it completely.
10539     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10540       return Match_RequiresFlagSetting;
10541     // If we're parsing Thumb2, which form is legal depends on whether we're
10542     // in an IT block.
10543     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10544         !inITBlock())
10545       return Match_RequiresITBlock;
10546     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10547         inITBlock())
10548       return Match_RequiresNotITBlock;
10549     // LSL with zero immediate is not allowed in an IT block
10550     if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
10551       return Match_RequiresNotITBlock;
10552   } else if (isThumbOne()) {
10553     // Some high-register supporting Thumb1 encodings only allow both registers
10554     // to be from r0-r7 when in Thumb2.
10555     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
10556         isARMLowRegister(Inst.getOperand(1).getReg()) &&
10557         isARMLowRegister(Inst.getOperand(2).getReg()))
10558       return Match_RequiresThumb2;
10559     // Others only require ARMv6 or later.
10560     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
10561              isARMLowRegister(Inst.getOperand(0).getReg()) &&
10562              isARMLowRegister(Inst.getOperand(1).getReg()))
10563       return Match_RequiresV6;
10564   }
10565 
10566   // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
10567   // than the loop below can handle, so it uses the GPRnopc register class and
10568   // we do SP handling here.
10569   if (Opc == ARM::t2MOVr && !hasV8Ops())
10570   {
10571     // SP as both source and destination is not allowed
10572     if (Inst.getOperand(0).getReg() == ARM::SP &&
10573         Inst.getOperand(1).getReg() == ARM::SP)
10574       return Match_RequiresV8;
10575     // When flags-setting SP as either source or destination is not allowed
10576     if (Inst.getOperand(4).getReg() == ARM::CPSR &&
10577         (Inst.getOperand(0).getReg() == ARM::SP ||
10578          Inst.getOperand(1).getReg() == ARM::SP))
10579       return Match_RequiresV8;
10580   }
10581 
10582   switch (Inst.getOpcode()) {
10583   case ARM::VMRS:
10584   case ARM::VMSR:
10585   case ARM::VMRS_FPCXTS:
10586   case ARM::VMRS_FPCXTNS:
10587   case ARM::VMSR_FPCXTS:
10588   case ARM::VMSR_FPCXTNS:
10589   case ARM::VMRS_FPSCR_NZCVQC:
10590   case ARM::VMSR_FPSCR_NZCVQC:
10591   case ARM::FMSTAT:
10592   case ARM::VMRS_VPR:
10593   case ARM::VMRS_P0:
10594   case ARM::VMSR_VPR:
10595   case ARM::VMSR_P0:
10596     // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
10597     // ARMv8-A.
10598     if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10599         (isThumb() && !hasV8Ops()))
10600       return Match_InvalidOperand;
10601     break;
10602   case ARM::t2TBB:
10603   case ARM::t2TBH:
10604     // Rn = sp is only allowed with ARMv8-A
10605     if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
10606       return Match_RequiresV8;
10607     break;
10608   default:
10609     break;
10610   }
10611 
10612   for (unsigned I = 0; I < MCID.NumOperands; ++I)
10613     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
10614       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10615       const auto &Op = Inst.getOperand(I);
10616       if (!Op.isReg()) {
10617         // This can happen in awkward cases with tied operands, e.g. a
10618         // writeback load/store with a complex addressing mode in
10619         // which there's an output operand corresponding to the
10620         // updated written-back base register: the Tablegen-generated
10621         // AsmMatcher will have written a placeholder operand to that
10622         // slot in the form of an immediate 0, because it can't
10623         // generate the register part of the complex addressing-mode
10624         // operand ahead of time.
10625         continue;
10626       }
10627 
10628       unsigned Reg = Op.getReg();
10629       if ((Reg == ARM::SP) && !hasV8Ops())
10630         return Match_RequiresV8;
10631       else if (Reg == ARM::PC)
10632         return Match_InvalidOperand;
10633     }
10634 
10635   return Match_Success;
10636 }
10637 
10638 namespace llvm {
10639 
10640 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10641   return true; // In an assembly source, no need to second-guess
10642 }
10643 
10644 } // end namespace llvm
10645 
10646 // Returns true if Inst is unpredictable if it is in and IT block, but is not
10647 // the last instruction in the block.
10648 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10649   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10650 
10651   // All branch & call instructions terminate IT blocks with the exception of
10652   // SVC.
10653   if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10654       MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
10655     return true;
10656 
10657   // Any arithmetic instruction which writes to the PC also terminates the IT
10658   // block.
10659   if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
10660     return true;
10661 
10662   return false;
10663 }
10664 
10665 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10666                                           SmallVectorImpl<NearMissInfo> &NearMisses,
10667                                           bool MatchingInlineAsm,
10668                                           bool &EmitInITBlock,
10669                                           MCStreamer &Out) {
10670   // If we can't use an implicit IT block here, just match as normal.
10671   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
10672     return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10673 
10674   // Try to match the instruction in an extension of the current IT block (if
10675   // there is one).
10676   if (inImplicitITBlock()) {
10677     extendImplicitITBlock(ITState.Cond);
10678     if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10679             Match_Success) {
10680       // The match succeded, but we still have to check that the instruction is
10681       // valid in this implicit IT block.
10682       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10683       if (MCID.isPredicable()) {
10684         ARMCC::CondCodes InstCond =
10685             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10686                 .getImm();
10687         ARMCC::CondCodes ITCond = currentITCond();
10688         if (InstCond == ITCond) {
10689           EmitInITBlock = true;
10690           return Match_Success;
10691         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
10692           invertCurrentITCondition();
10693           EmitInITBlock = true;
10694           return Match_Success;
10695         }
10696       }
10697     }
10698     rewindImplicitITPosition();
10699   }
10700 
10701   // Finish the current IT block, and try to match outside any IT block.
10702   flushPendingInstructions(Out);
10703   unsigned PlainMatchResult =
10704       MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10705   if (PlainMatchResult == Match_Success) {
10706     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10707     if (MCID.isPredicable()) {
10708       ARMCC::CondCodes InstCond =
10709           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10710               .getImm();
10711       // Some forms of the branch instruction have their own condition code
10712       // fields, so can be conditionally executed without an IT block.
10713       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10714         EmitInITBlock = false;
10715         return Match_Success;
10716       }
10717       if (InstCond == ARMCC::AL) {
10718         EmitInITBlock = false;
10719         return Match_Success;
10720       }
10721     } else {
10722       EmitInITBlock = false;
10723       return Match_Success;
10724     }
10725   }
10726 
10727   // Try to match in a new IT block. The matcher doesn't check the actual
10728   // condition, so we create an IT block with a dummy condition, and fix it up
10729   // once we know the actual condition.
10730   startImplicitITBlock();
10731   if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10732       Match_Success) {
10733     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10734     if (MCID.isPredicable()) {
10735       ITState.Cond =
10736           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10737               .getImm();
10738       EmitInITBlock = true;
10739       return Match_Success;
10740     }
10741   }
10742   discardImplicitITBlock();
10743 
10744   // If none of these succeed, return the error we got when trying to match
10745   // outside any IT blocks.
10746   EmitInITBlock = false;
10747   return PlainMatchResult;
10748 }
10749 
10750 static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
10751                                          unsigned VariantID = 0);
10752 
10753 static const char *getSubtargetFeatureName(uint64_t Val);
10754 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
10755                                            OperandVector &Operands,
10756                                            MCStreamer &Out, uint64_t &ErrorInfo,
10757                                            bool MatchingInlineAsm) {
10758   MCInst Inst;
10759   unsigned MatchResult;
10760   bool PendConditionalInstruction = false;
10761 
10762   SmallVector<NearMissInfo, 4> NearMisses;
10763   MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
10764                                  PendConditionalInstruction, Out);
10765 
10766   switch (MatchResult) {
10767   case Match_Success:
10768     LLVM_DEBUG(dbgs() << "Parsed as: ";
10769                Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10770                dbgs() << "\n");
10771 
10772     // Context sensitive operand constraints aren't handled by the matcher,
10773     // so check them here.
10774     if (validateInstruction(Inst, Operands)) {
10775       // Still progress the IT block, otherwise one wrong condition causes
10776       // nasty cascading errors.
10777       forwardITPosition();
10778       forwardVPTPosition();
10779       return true;
10780     }
10781 
10782     { // processInstruction() updates inITBlock state, we need to save it away
10783       bool wasInITBlock = inITBlock();
10784 
10785       // Some instructions need post-processing to, for example, tweak which
10786       // encoding is selected. Loop on it while changes happen so the
10787       // individual transformations can chain off each other. E.g.,
10788       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
10789       while (processInstruction(Inst, Operands, Out))
10790         LLVM_DEBUG(dbgs() << "Changed to: ";
10791                    Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10792                    dbgs() << "\n");
10793 
10794       // Only after the instruction is fully processed, we can validate it
10795       if (wasInITBlock && hasV8Ops() && isThumb() &&
10796           !isV8EligibleForIT(&Inst)) {
10797         Warning(IDLoc, "deprecated instruction in IT block");
10798       }
10799     }
10800 
10801     // Only move forward at the very end so that everything in validate
10802     // and process gets a consistent answer about whether we're in an IT
10803     // block.
10804     forwardITPosition();
10805     forwardVPTPosition();
10806 
10807     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
10808     // doesn't actually encode.
10809     if (Inst.getOpcode() == ARM::ITasm)
10810       return false;
10811 
10812     Inst.setLoc(IDLoc);
10813     if (PendConditionalInstruction) {
10814       PendingConditionalInsts.push_back(Inst);
10815       if (isITBlockFull() || isITBlockTerminator(Inst))
10816         flushPendingInstructions(Out);
10817     } else {
10818       Out.emitInstruction(Inst, getSTI());
10819     }
10820     return false;
10821   case Match_NearMisses:
10822     ReportNearMisses(NearMisses, IDLoc, Operands);
10823     return true;
10824   case Match_MnemonicFail: {
10825     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
10826     std::string Suggestion = ARMMnemonicSpellCheck(
10827       ((ARMOperand &)*Operands[0]).getToken(), FBS);
10828     return Error(IDLoc, "invalid instruction" + Suggestion,
10829                  ((ARMOperand &)*Operands[0]).getLocRange());
10830   }
10831   }
10832 
10833   llvm_unreachable("Implement any new match types added!");
10834 }
10835 
10836 /// parseDirective parses the arm specific directives
10837 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
10838   const MCObjectFileInfo::Environment Format =
10839     getContext().getObjectFileInfo()->getObjectFileType();
10840   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10841   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
10842 
10843   std::string IDVal = DirectiveID.getIdentifier().lower();
10844   if (IDVal == ".word")
10845     parseLiteralValues(4, DirectiveID.getLoc());
10846   else if (IDVal == ".short" || IDVal == ".hword")
10847     parseLiteralValues(2, DirectiveID.getLoc());
10848   else if (IDVal == ".thumb")
10849     parseDirectiveThumb(DirectiveID.getLoc());
10850   else if (IDVal == ".arm")
10851     parseDirectiveARM(DirectiveID.getLoc());
10852   else if (IDVal == ".thumb_func")
10853     parseDirectiveThumbFunc(DirectiveID.getLoc());
10854   else if (IDVal == ".code")
10855     parseDirectiveCode(DirectiveID.getLoc());
10856   else if (IDVal == ".syntax")
10857     parseDirectiveSyntax(DirectiveID.getLoc());
10858   else if (IDVal == ".unreq")
10859     parseDirectiveUnreq(DirectiveID.getLoc());
10860   else if (IDVal == ".fnend")
10861     parseDirectiveFnEnd(DirectiveID.getLoc());
10862   else if (IDVal == ".cantunwind")
10863     parseDirectiveCantUnwind(DirectiveID.getLoc());
10864   else if (IDVal == ".personality")
10865     parseDirectivePersonality(DirectiveID.getLoc());
10866   else if (IDVal == ".handlerdata")
10867     parseDirectiveHandlerData(DirectiveID.getLoc());
10868   else if (IDVal == ".setfp")
10869     parseDirectiveSetFP(DirectiveID.getLoc());
10870   else if (IDVal == ".pad")
10871     parseDirectivePad(DirectiveID.getLoc());
10872   else if (IDVal == ".save")
10873     parseDirectiveRegSave(DirectiveID.getLoc(), false);
10874   else if (IDVal == ".vsave")
10875     parseDirectiveRegSave(DirectiveID.getLoc(), true);
10876   else if (IDVal == ".ltorg" || IDVal == ".pool")
10877     parseDirectiveLtorg(DirectiveID.getLoc());
10878   else if (IDVal == ".even")
10879     parseDirectiveEven(DirectiveID.getLoc());
10880   else if (IDVal == ".personalityindex")
10881     parseDirectivePersonalityIndex(DirectiveID.getLoc());
10882   else if (IDVal == ".unwind_raw")
10883     parseDirectiveUnwindRaw(DirectiveID.getLoc());
10884   else if (IDVal == ".movsp")
10885     parseDirectiveMovSP(DirectiveID.getLoc());
10886   else if (IDVal == ".arch_extension")
10887     parseDirectiveArchExtension(DirectiveID.getLoc());
10888   else if (IDVal == ".align")
10889     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
10890   else if (IDVal == ".thumb_set")
10891     parseDirectiveThumbSet(DirectiveID.getLoc());
10892   else if (IDVal == ".inst")
10893     parseDirectiveInst(DirectiveID.getLoc());
10894   else if (IDVal == ".inst.n")
10895     parseDirectiveInst(DirectiveID.getLoc(), 'n');
10896   else if (IDVal == ".inst.w")
10897     parseDirectiveInst(DirectiveID.getLoc(), 'w');
10898   else if (!IsMachO && !IsCOFF) {
10899     if (IDVal == ".arch")
10900       parseDirectiveArch(DirectiveID.getLoc());
10901     else if (IDVal == ".cpu")
10902       parseDirectiveCPU(DirectiveID.getLoc());
10903     else if (IDVal == ".eabi_attribute")
10904       parseDirectiveEabiAttr(DirectiveID.getLoc());
10905     else if (IDVal == ".fpu")
10906       parseDirectiveFPU(DirectiveID.getLoc());
10907     else if (IDVal == ".fnstart")
10908       parseDirectiveFnStart(DirectiveID.getLoc());
10909     else if (IDVal == ".object_arch")
10910       parseDirectiveObjectArch(DirectiveID.getLoc());
10911     else if (IDVal == ".tlsdescseq")
10912       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
10913     else
10914       return true;
10915   } else
10916     return true;
10917   return false;
10918 }
10919 
10920 /// parseLiteralValues
10921 ///  ::= .hword expression [, expression]*
10922 ///  ::= .short expression [, expression]*
10923 ///  ::= .word expression [, expression]*
10924 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
10925   auto parseOne = [&]() -> bool {
10926     const MCExpr *Value;
10927     if (getParser().parseExpression(Value))
10928       return true;
10929     getParser().getStreamer().emitValue(Value, Size, L);
10930     return false;
10931   };
10932   return (parseMany(parseOne));
10933 }
10934 
10935 /// parseDirectiveThumb
10936 ///  ::= .thumb
10937 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
10938   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10939       check(!hasThumb(), L, "target does not support Thumb mode"))
10940     return true;
10941 
10942   if (!isThumb())
10943     SwitchMode();
10944 
10945   getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
10946   return false;
10947 }
10948 
10949 /// parseDirectiveARM
10950 ///  ::= .arm
10951 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
10952   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10953       check(!hasARM(), L, "target does not support ARM mode"))
10954     return true;
10955 
10956   if (isThumb())
10957     SwitchMode();
10958   getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
10959   return false;
10960 }
10961 
10962 void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) {
10963   // We need to flush the current implicit IT block on a label, because it is
10964   // not legal to branch into an IT block.
10965   flushPendingInstructions(getStreamer());
10966 }
10967 
10968 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
10969   if (NextSymbolIsThumb) {
10970     getParser().getStreamer().emitThumbFunc(Symbol);
10971     NextSymbolIsThumb = false;
10972   }
10973 }
10974 
10975 /// parseDirectiveThumbFunc
10976 ///  ::= .thumbfunc symbol_name
10977 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
10978   MCAsmParser &Parser = getParser();
10979   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
10980   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10981 
10982   // Darwin asm has (optionally) function name after .thumb_func direction
10983   // ELF doesn't
10984 
10985   if (IsMachO) {
10986     if (Parser.getTok().is(AsmToken::Identifier) ||
10987         Parser.getTok().is(AsmToken::String)) {
10988       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
10989           Parser.getTok().getIdentifier());
10990       getParser().getStreamer().emitThumbFunc(Func);
10991       Parser.Lex();
10992       if (parseToken(AsmToken::EndOfStatement,
10993                      "unexpected token in '.thumb_func' directive"))
10994         return true;
10995       return false;
10996     }
10997   }
10998 
10999   if (parseToken(AsmToken::EndOfStatement,
11000                  "unexpected token in '.thumb_func' directive"))
11001     return true;
11002 
11003   NextSymbolIsThumb = true;
11004   return false;
11005 }
11006 
11007 /// parseDirectiveSyntax
11008 ///  ::= .syntax unified | divided
11009 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
11010   MCAsmParser &Parser = getParser();
11011   const AsmToken &Tok = Parser.getTok();
11012   if (Tok.isNot(AsmToken::Identifier)) {
11013     Error(L, "unexpected token in .syntax directive");
11014     return false;
11015   }
11016 
11017   StringRef Mode = Tok.getString();
11018   Parser.Lex();
11019   if (check(Mode == "divided" || Mode == "DIVIDED", L,
11020             "'.syntax divided' arm assembly not supported") ||
11021       check(Mode != "unified" && Mode != "UNIFIED", L,
11022             "unrecognized syntax mode in .syntax directive") ||
11023       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11024     return true;
11025 
11026   // TODO tell the MC streamer the mode
11027   // getParser().getStreamer().Emit???();
11028   return false;
11029 }
11030 
11031 /// parseDirectiveCode
11032 ///  ::= .code 16 | 32
11033 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
11034   MCAsmParser &Parser = getParser();
11035   const AsmToken &Tok = Parser.getTok();
11036   if (Tok.isNot(AsmToken::Integer))
11037     return Error(L, "unexpected token in .code directive");
11038   int64_t Val = Parser.getTok().getIntVal();
11039   if (Val != 16 && Val != 32) {
11040     Error(L, "invalid operand to .code directive");
11041     return false;
11042   }
11043   Parser.Lex();
11044 
11045   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11046     return true;
11047 
11048   if (Val == 16) {
11049     if (!hasThumb())
11050       return Error(L, "target does not support Thumb mode");
11051 
11052     if (!isThumb())
11053       SwitchMode();
11054     getParser().getStreamer().emitAssemblerFlag(MCAF_Code16);
11055   } else {
11056     if (!hasARM())
11057       return Error(L, "target does not support ARM mode");
11058 
11059     if (isThumb())
11060       SwitchMode();
11061     getParser().getStreamer().emitAssemblerFlag(MCAF_Code32);
11062   }
11063 
11064   return false;
11065 }
11066 
11067 /// parseDirectiveReq
11068 ///  ::= name .req registername
11069 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
11070   MCAsmParser &Parser = getParser();
11071   Parser.Lex(); // Eat the '.req' token.
11072   unsigned Reg;
11073   SMLoc SRegLoc, ERegLoc;
11074   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
11075             "register name expected") ||
11076       parseToken(AsmToken::EndOfStatement,
11077                  "unexpected input in .req directive."))
11078     return true;
11079 
11080   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
11081     return Error(SRegLoc,
11082                  "redefinition of '" + Name + "' does not match original.");
11083 
11084   return false;
11085 }
11086 
11087 /// parseDirectiveUneq
11088 ///  ::= .unreq registername
11089 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
11090   MCAsmParser &Parser = getParser();
11091   if (Parser.getTok().isNot(AsmToken::Identifier))
11092     return Error(L, "unexpected input in .unreq directive.");
11093   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
11094   Parser.Lex(); // Eat the identifier.
11095   if (parseToken(AsmToken::EndOfStatement,
11096                  "unexpected input in '.unreq' directive"))
11097     return true;
11098   return false;
11099 }
11100 
11101 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
11102 // before, if supported by the new target, or emit mapping symbols for the mode
11103 // switch.
11104 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
11105   if (WasThumb != isThumb()) {
11106     if (WasThumb && hasThumb()) {
11107       // Stay in Thumb mode
11108       SwitchMode();
11109     } else if (!WasThumb && hasARM()) {
11110       // Stay in ARM mode
11111       SwitchMode();
11112     } else {
11113       // Mode switch forced, because the new arch doesn't support the old mode.
11114       getParser().getStreamer().emitAssemblerFlag(isThumb() ? MCAF_Code16
11115                                                             : MCAF_Code32);
11116       // Warn about the implcit mode switch. GAS does not switch modes here,
11117       // but instead stays in the old mode, reporting an error on any following
11118       // instructions as the mode does not exist on the target.
11119       Warning(Loc, Twine("new target does not support ") +
11120                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
11121                        (!WasThumb ? "thumb" : "arm") + " mode");
11122     }
11123   }
11124 }
11125 
11126 /// parseDirectiveArch
11127 ///  ::= .arch token
11128 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
11129   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
11130   ARM::ArchKind ID = ARM::parseArch(Arch);
11131 
11132   if (ID == ARM::ArchKind::INVALID)
11133     return Error(L, "Unknown arch name");
11134 
11135   bool WasThumb = isThumb();
11136   Triple T;
11137   MCSubtargetInfo &STI = copySTI();
11138   STI.setDefaultFeatures("", /*TuneCPU*/ "",
11139                          ("+" + ARM::getArchName(ID)).str());
11140   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11141   FixModeAfterArchChange(WasThumb, L);
11142 
11143   getTargetStreamer().emitArch(ID);
11144   return false;
11145 }
11146 
11147 /// parseDirectiveEabiAttr
11148 ///  ::= .eabi_attribute int, int [, "str"]
11149 ///  ::= .eabi_attribute Tag_name, int [, "str"]
11150 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
11151   MCAsmParser &Parser = getParser();
11152   int64_t Tag;
11153   SMLoc TagLoc;
11154   TagLoc = Parser.getTok().getLoc();
11155   if (Parser.getTok().is(AsmToken::Identifier)) {
11156     StringRef Name = Parser.getTok().getIdentifier();
11157     Optional<unsigned> Ret =
11158         ELFAttrs::attrTypeFromString(Name, ARMBuildAttrs::ARMAttributeTags);
11159     if (!Ret.hasValue()) {
11160       Error(TagLoc, "attribute name not recognised: " + Name);
11161       return false;
11162     }
11163     Tag = Ret.getValue();
11164     Parser.Lex();
11165   } else {
11166     const MCExpr *AttrExpr;
11167 
11168     TagLoc = Parser.getTok().getLoc();
11169     if (Parser.parseExpression(AttrExpr))
11170       return true;
11171 
11172     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
11173     if (check(!CE, TagLoc, "expected numeric constant"))
11174       return true;
11175 
11176     Tag = CE->getValue();
11177   }
11178 
11179   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11180     return true;
11181 
11182   StringRef StringValue = "";
11183   bool IsStringValue = false;
11184 
11185   int64_t IntegerValue = 0;
11186   bool IsIntegerValue = false;
11187 
11188   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
11189     IsStringValue = true;
11190   else if (Tag == ARMBuildAttrs::compatibility) {
11191     IsStringValue = true;
11192     IsIntegerValue = true;
11193   } else if (Tag < 32 || Tag % 2 == 0)
11194     IsIntegerValue = true;
11195   else if (Tag % 2 == 1)
11196     IsStringValue = true;
11197   else
11198     llvm_unreachable("invalid tag type");
11199 
11200   if (IsIntegerValue) {
11201     const MCExpr *ValueExpr;
11202     SMLoc ValueExprLoc = Parser.getTok().getLoc();
11203     if (Parser.parseExpression(ValueExpr))
11204       return true;
11205 
11206     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
11207     if (!CE)
11208       return Error(ValueExprLoc, "expected numeric constant");
11209     IntegerValue = CE->getValue();
11210   }
11211 
11212   if (Tag == ARMBuildAttrs::compatibility) {
11213     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
11214       return true;
11215   }
11216 
11217   if (IsStringValue) {
11218     if (Parser.getTok().isNot(AsmToken::String))
11219       return Error(Parser.getTok().getLoc(), "bad string constant");
11220 
11221     StringValue = Parser.getTok().getStringContents();
11222     Parser.Lex();
11223   }
11224 
11225   if (Parser.parseToken(AsmToken::EndOfStatement,
11226                         "unexpected token in '.eabi_attribute' directive"))
11227     return true;
11228 
11229   if (IsIntegerValue && IsStringValue) {
11230     assert(Tag == ARMBuildAttrs::compatibility);
11231     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
11232   } else if (IsIntegerValue)
11233     getTargetStreamer().emitAttribute(Tag, IntegerValue);
11234   else if (IsStringValue)
11235     getTargetStreamer().emitTextAttribute(Tag, StringValue);
11236   return false;
11237 }
11238 
11239 /// parseDirectiveCPU
11240 ///  ::= .cpu str
11241 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
11242   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
11243   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
11244 
11245   // FIXME: This is using table-gen data, but should be moved to
11246   // ARMTargetParser once that is table-gen'd.
11247   if (!getSTI().isCPUStringValid(CPU))
11248     return Error(L, "Unknown CPU name");
11249 
11250   bool WasThumb = isThumb();
11251   MCSubtargetInfo &STI = copySTI();
11252   STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
11253   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11254   FixModeAfterArchChange(WasThumb, L);
11255 
11256   return false;
11257 }
11258 
11259 /// parseDirectiveFPU
11260 ///  ::= .fpu str
11261 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
11262   SMLoc FPUNameLoc = getTok().getLoc();
11263   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
11264 
11265   unsigned ID = ARM::parseFPU(FPU);
11266   std::vector<StringRef> Features;
11267   if (!ARM::getFPUFeatures(ID, Features))
11268     return Error(FPUNameLoc, "Unknown FPU name");
11269 
11270   MCSubtargetInfo &STI = copySTI();
11271   for (auto Feature : Features)
11272     STI.ApplyFeatureFlag(Feature);
11273   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
11274 
11275   getTargetStreamer().emitFPU(ID);
11276   return false;
11277 }
11278 
11279 /// parseDirectiveFnStart
11280 ///  ::= .fnstart
11281 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
11282   if (parseToken(AsmToken::EndOfStatement,
11283                  "unexpected token in '.fnstart' directive"))
11284     return true;
11285 
11286   if (UC.hasFnStart()) {
11287     Error(L, ".fnstart starts before the end of previous one");
11288     UC.emitFnStartLocNotes();
11289     return true;
11290   }
11291 
11292   // Reset the unwind directives parser state
11293   UC.reset();
11294 
11295   getTargetStreamer().emitFnStart();
11296 
11297   UC.recordFnStart(L);
11298   return false;
11299 }
11300 
11301 /// parseDirectiveFnEnd
11302 ///  ::= .fnend
11303 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
11304   if (parseToken(AsmToken::EndOfStatement,
11305                  "unexpected token in '.fnend' directive"))
11306     return true;
11307   // Check the ordering of unwind directives
11308   if (!UC.hasFnStart())
11309     return Error(L, ".fnstart must precede .fnend directive");
11310 
11311   // Reset the unwind directives parser state
11312   getTargetStreamer().emitFnEnd();
11313 
11314   UC.reset();
11315   return false;
11316 }
11317 
11318 /// parseDirectiveCantUnwind
11319 ///  ::= .cantunwind
11320 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
11321   if (parseToken(AsmToken::EndOfStatement,
11322                  "unexpected token in '.cantunwind' directive"))
11323     return true;
11324 
11325   UC.recordCantUnwind(L);
11326   // Check the ordering of unwind directives
11327   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
11328     return true;
11329 
11330   if (UC.hasHandlerData()) {
11331     Error(L, ".cantunwind can't be used with .handlerdata directive");
11332     UC.emitHandlerDataLocNotes();
11333     return true;
11334   }
11335   if (UC.hasPersonality()) {
11336     Error(L, ".cantunwind can't be used with .personality directive");
11337     UC.emitPersonalityLocNotes();
11338     return true;
11339   }
11340 
11341   getTargetStreamer().emitCantUnwind();
11342   return false;
11343 }
11344 
11345 /// parseDirectivePersonality
11346 ///  ::= .personality name
11347 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
11348   MCAsmParser &Parser = getParser();
11349   bool HasExistingPersonality = UC.hasPersonality();
11350 
11351   // Parse the name of the personality routine
11352   if (Parser.getTok().isNot(AsmToken::Identifier))
11353     return Error(L, "unexpected input in .personality directive.");
11354   StringRef Name(Parser.getTok().getIdentifier());
11355   Parser.Lex();
11356 
11357   if (parseToken(AsmToken::EndOfStatement,
11358                  "unexpected token in '.personality' directive"))
11359     return true;
11360 
11361   UC.recordPersonality(L);
11362 
11363   // Check the ordering of unwind directives
11364   if (!UC.hasFnStart())
11365     return Error(L, ".fnstart must precede .personality directive");
11366   if (UC.cantUnwind()) {
11367     Error(L, ".personality can't be used with .cantunwind directive");
11368     UC.emitCantUnwindLocNotes();
11369     return true;
11370   }
11371   if (UC.hasHandlerData()) {
11372     Error(L, ".personality must precede .handlerdata directive");
11373     UC.emitHandlerDataLocNotes();
11374     return true;
11375   }
11376   if (HasExistingPersonality) {
11377     Error(L, "multiple personality directives");
11378     UC.emitPersonalityLocNotes();
11379     return true;
11380   }
11381 
11382   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
11383   getTargetStreamer().emitPersonality(PR);
11384   return false;
11385 }
11386 
11387 /// parseDirectiveHandlerData
11388 ///  ::= .handlerdata
11389 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
11390   if (parseToken(AsmToken::EndOfStatement,
11391                  "unexpected token in '.handlerdata' directive"))
11392     return true;
11393 
11394   UC.recordHandlerData(L);
11395   // Check the ordering of unwind directives
11396   if (!UC.hasFnStart())
11397     return Error(L, ".fnstart must precede .personality directive");
11398   if (UC.cantUnwind()) {
11399     Error(L, ".handlerdata can't be used with .cantunwind directive");
11400     UC.emitCantUnwindLocNotes();
11401     return true;
11402   }
11403 
11404   getTargetStreamer().emitHandlerData();
11405   return false;
11406 }
11407 
11408 /// parseDirectiveSetFP
11409 ///  ::= .setfp fpreg, spreg [, offset]
11410 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
11411   MCAsmParser &Parser = getParser();
11412   // Check the ordering of unwind directives
11413   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
11414       check(UC.hasHandlerData(), L,
11415             ".setfp must precede .handlerdata directive"))
11416     return true;
11417 
11418   // Parse fpreg
11419   SMLoc FPRegLoc = Parser.getTok().getLoc();
11420   int FPReg = tryParseRegister();
11421 
11422   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
11423       Parser.parseToken(AsmToken::Comma, "comma expected"))
11424     return true;
11425 
11426   // Parse spreg
11427   SMLoc SPRegLoc = Parser.getTok().getLoc();
11428   int SPReg = tryParseRegister();
11429   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11430       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11431             "register should be either $sp or the latest fp register"))
11432     return true;
11433 
11434   // Update the frame pointer register
11435   UC.saveFPReg(FPReg);
11436 
11437   // Parse offset
11438   int64_t Offset = 0;
11439   if (Parser.parseOptionalToken(AsmToken::Comma)) {
11440     if (Parser.getTok().isNot(AsmToken::Hash) &&
11441         Parser.getTok().isNot(AsmToken::Dollar))
11442       return Error(Parser.getTok().getLoc(), "'#' expected");
11443     Parser.Lex(); // skip hash token.
11444 
11445     const MCExpr *OffsetExpr;
11446     SMLoc ExLoc = Parser.getTok().getLoc();
11447     SMLoc EndLoc;
11448     if (getParser().parseExpression(OffsetExpr, EndLoc))
11449       return Error(ExLoc, "malformed setfp offset");
11450     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11451     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
11452       return true;
11453     Offset = CE->getValue();
11454   }
11455 
11456   if (Parser.parseToken(AsmToken::EndOfStatement))
11457     return true;
11458 
11459   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
11460                                 static_cast<unsigned>(SPReg), Offset);
11461   return false;
11462 }
11463 
11464 /// parseDirective
11465 ///  ::= .pad offset
11466 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
11467   MCAsmParser &Parser = getParser();
11468   // Check the ordering of unwind directives
11469   if (!UC.hasFnStart())
11470     return Error(L, ".fnstart must precede .pad directive");
11471   if (UC.hasHandlerData())
11472     return Error(L, ".pad must precede .handlerdata directive");
11473 
11474   // Parse the offset
11475   if (Parser.getTok().isNot(AsmToken::Hash) &&
11476       Parser.getTok().isNot(AsmToken::Dollar))
11477     return Error(Parser.getTok().getLoc(), "'#' expected");
11478   Parser.Lex(); // skip hash token.
11479 
11480   const MCExpr *OffsetExpr;
11481   SMLoc ExLoc = Parser.getTok().getLoc();
11482   SMLoc EndLoc;
11483   if (getParser().parseExpression(OffsetExpr, EndLoc))
11484     return Error(ExLoc, "malformed pad offset");
11485   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11486   if (!CE)
11487     return Error(ExLoc, "pad offset must be an immediate");
11488 
11489   if (parseToken(AsmToken::EndOfStatement,
11490                  "unexpected token in '.pad' directive"))
11491     return true;
11492 
11493   getTargetStreamer().emitPad(CE->getValue());
11494   return false;
11495 }
11496 
11497 /// parseDirectiveRegSave
11498 ///  ::= .save  { registers }
11499 ///  ::= .vsave { registers }
11500 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11501   // Check the ordering of unwind directives
11502   if (!UC.hasFnStart())
11503     return Error(L, ".fnstart must precede .save or .vsave directives");
11504   if (UC.hasHandlerData())
11505     return Error(L, ".save or .vsave must precede .handlerdata directive");
11506 
11507   // RAII object to make sure parsed operands are deleted.
11508   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
11509 
11510   // Parse the register list
11511   if (parseRegisterList(Operands) ||
11512       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11513     return true;
11514   ARMOperand &Op = (ARMOperand &)*Operands[0];
11515   if (!IsVector && !Op.isRegList())
11516     return Error(L, ".save expects GPR registers");
11517   if (IsVector && !Op.isDPRRegList())
11518     return Error(L, ".vsave expects DPR registers");
11519 
11520   getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
11521   return false;
11522 }
11523 
11524 /// parseDirectiveInst
11525 ///  ::= .inst opcode [, ...]
11526 ///  ::= .inst.n opcode [, ...]
11527 ///  ::= .inst.w opcode [, ...]
11528 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
11529   int Width = 4;
11530 
11531   if (isThumb()) {
11532     switch (Suffix) {
11533     case 'n':
11534       Width = 2;
11535       break;
11536     case 'w':
11537       break;
11538     default:
11539       Width = 0;
11540       break;
11541     }
11542   } else {
11543     if (Suffix)
11544       return Error(Loc, "width suffixes are invalid in ARM mode");
11545   }
11546 
11547   auto parseOne = [&]() -> bool {
11548     const MCExpr *Expr;
11549     if (getParser().parseExpression(Expr))
11550       return true;
11551     const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
11552     if (!Value) {
11553       return Error(Loc, "expected constant expression");
11554     }
11555 
11556     char CurSuffix = Suffix;
11557     switch (Width) {
11558     case 2:
11559       if (Value->getValue() > 0xffff)
11560         return Error(Loc, "inst.n operand is too big, use inst.w instead");
11561       break;
11562     case 4:
11563       if (Value->getValue() > 0xffffffff)
11564         return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
11565                               " operand is too big");
11566       break;
11567     case 0:
11568       // Thumb mode, no width indicated. Guess from the opcode, if possible.
11569       if (Value->getValue() < 0xe800)
11570         CurSuffix = 'n';
11571       else if (Value->getValue() >= 0xe8000000)
11572         CurSuffix = 'w';
11573       else
11574         return Error(Loc, "cannot determine Thumb instruction size, "
11575                           "use inst.n/inst.w instead");
11576       break;
11577     default:
11578       llvm_unreachable("only supported widths are 2 and 4");
11579     }
11580 
11581     getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
11582     return false;
11583   };
11584 
11585   if (parseOptionalToken(AsmToken::EndOfStatement))
11586     return Error(Loc, "expected expression following directive");
11587   if (parseMany(parseOne))
11588     return true;
11589   return false;
11590 }
11591 
11592 /// parseDirectiveLtorg
11593 ///  ::= .ltorg | .pool
11594 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
11595   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11596     return true;
11597   getTargetStreamer().emitCurrentConstantPool();
11598   return false;
11599 }
11600 
11601 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
11602   const MCSection *Section = getStreamer().getCurrentSectionOnly();
11603 
11604   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11605     return true;
11606 
11607   if (!Section) {
11608     getStreamer().InitSections(false);
11609     Section = getStreamer().getCurrentSectionOnly();
11610   }
11611 
11612   assert(Section && "must have section to emit alignment");
11613   if (Section->UseCodeAlign())
11614     getStreamer().emitCodeAlignment(2);
11615   else
11616     getStreamer().emitValueToAlignment(2);
11617 
11618   return false;
11619 }
11620 
11621 /// parseDirectivePersonalityIndex
11622 ///   ::= .personalityindex index
11623 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
11624   MCAsmParser &Parser = getParser();
11625   bool HasExistingPersonality = UC.hasPersonality();
11626 
11627   const MCExpr *IndexExpression;
11628   SMLoc IndexLoc = Parser.getTok().getLoc();
11629   if (Parser.parseExpression(IndexExpression) ||
11630       parseToken(AsmToken::EndOfStatement,
11631                  "unexpected token in '.personalityindex' directive")) {
11632     return true;
11633   }
11634 
11635   UC.recordPersonalityIndex(L);
11636 
11637   if (!UC.hasFnStart()) {
11638     return Error(L, ".fnstart must precede .personalityindex directive");
11639   }
11640   if (UC.cantUnwind()) {
11641     Error(L, ".personalityindex cannot be used with .cantunwind");
11642     UC.emitCantUnwindLocNotes();
11643     return true;
11644   }
11645   if (UC.hasHandlerData()) {
11646     Error(L, ".personalityindex must precede .handlerdata directive");
11647     UC.emitHandlerDataLocNotes();
11648     return true;
11649   }
11650   if (HasExistingPersonality) {
11651     Error(L, "multiple personality directives");
11652     UC.emitPersonalityLocNotes();
11653     return true;
11654   }
11655 
11656   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
11657   if (!CE)
11658     return Error(IndexLoc, "index must be a constant number");
11659   if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
11660     return Error(IndexLoc,
11661                  "personality routine index should be in range [0-3]");
11662 
11663   getTargetStreamer().emitPersonalityIndex(CE->getValue());
11664   return false;
11665 }
11666 
11667 /// parseDirectiveUnwindRaw
11668 ///   ::= .unwind_raw offset, opcode [, opcode...]
11669 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
11670   MCAsmParser &Parser = getParser();
11671   int64_t StackOffset;
11672   const MCExpr *OffsetExpr;
11673   SMLoc OffsetLoc = getLexer().getLoc();
11674 
11675   if (!UC.hasFnStart())
11676     return Error(L, ".fnstart must precede .unwind_raw directives");
11677   if (getParser().parseExpression(OffsetExpr))
11678     return Error(OffsetLoc, "expected expression");
11679 
11680   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11681   if (!CE)
11682     return Error(OffsetLoc, "offset must be a constant");
11683 
11684   StackOffset = CE->getValue();
11685 
11686   if (Parser.parseToken(AsmToken::Comma, "expected comma"))
11687     return true;
11688 
11689   SmallVector<uint8_t, 16> Opcodes;
11690 
11691   auto parseOne = [&]() -> bool {
11692     const MCExpr *OE = nullptr;
11693     SMLoc OpcodeLoc = getLexer().getLoc();
11694     if (check(getLexer().is(AsmToken::EndOfStatement) ||
11695                   Parser.parseExpression(OE),
11696               OpcodeLoc, "expected opcode expression"))
11697       return true;
11698     const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
11699     if (!OC)
11700       return Error(OpcodeLoc, "opcode value must be a constant");
11701     const int64_t Opcode = OC->getValue();
11702     if (Opcode & ~0xff)
11703       return Error(OpcodeLoc, "invalid opcode");
11704     Opcodes.push_back(uint8_t(Opcode));
11705     return false;
11706   };
11707 
11708   // Must have at least 1 element
11709   SMLoc OpcodeLoc = getLexer().getLoc();
11710   if (parseOptionalToken(AsmToken::EndOfStatement))
11711     return Error(OpcodeLoc, "expected opcode expression");
11712   if (parseMany(parseOne))
11713     return true;
11714 
11715   getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
11716   return false;
11717 }
11718 
11719 /// parseDirectiveTLSDescSeq
11720 ///   ::= .tlsdescseq tls-variable
11721 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
11722   MCAsmParser &Parser = getParser();
11723 
11724   if (getLexer().isNot(AsmToken::Identifier))
11725     return TokError("expected variable after '.tlsdescseq' directive");
11726 
11727   const MCSymbolRefExpr *SRE =
11728     MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
11729                             MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
11730   Lex();
11731 
11732   if (parseToken(AsmToken::EndOfStatement,
11733                  "unexpected token in '.tlsdescseq' directive"))
11734     return true;
11735 
11736   getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
11737   return false;
11738 }
11739 
11740 /// parseDirectiveMovSP
11741 ///  ::= .movsp reg [, #offset]
11742 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
11743   MCAsmParser &Parser = getParser();
11744   if (!UC.hasFnStart())
11745     return Error(L, ".fnstart must precede .movsp directives");
11746   if (UC.getFPReg() != ARM::SP)
11747     return Error(L, "unexpected .movsp directive");
11748 
11749   SMLoc SPRegLoc = Parser.getTok().getLoc();
11750   int SPReg = tryParseRegister();
11751   if (SPReg == -1)
11752     return Error(SPRegLoc, "register expected");
11753   if (SPReg == ARM::SP || SPReg == ARM::PC)
11754     return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
11755 
11756   int64_t Offset = 0;
11757   if (Parser.parseOptionalToken(AsmToken::Comma)) {
11758     if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
11759       return true;
11760 
11761     const MCExpr *OffsetExpr;
11762     SMLoc OffsetLoc = Parser.getTok().getLoc();
11763 
11764     if (Parser.parseExpression(OffsetExpr))
11765       return Error(OffsetLoc, "malformed offset expression");
11766 
11767     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11768     if (!CE)
11769       return Error(OffsetLoc, "offset must be an immediate constant");
11770 
11771     Offset = CE->getValue();
11772   }
11773 
11774   if (parseToken(AsmToken::EndOfStatement,
11775                  "unexpected token in '.movsp' directive"))
11776     return true;
11777 
11778   getTargetStreamer().emitMovSP(SPReg, Offset);
11779   UC.saveFPReg(SPReg);
11780 
11781   return false;
11782 }
11783 
11784 /// parseDirectiveObjectArch
11785 ///   ::= .object_arch name
11786 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
11787   MCAsmParser &Parser = getParser();
11788   if (getLexer().isNot(AsmToken::Identifier))
11789     return Error(getLexer().getLoc(), "unexpected token");
11790 
11791   StringRef Arch = Parser.getTok().getString();
11792   SMLoc ArchLoc = Parser.getTok().getLoc();
11793   Lex();
11794 
11795   ARM::ArchKind ID = ARM::parseArch(Arch);
11796 
11797   if (ID == ARM::ArchKind::INVALID)
11798     return Error(ArchLoc, "unknown architecture '" + Arch + "'");
11799   if (parseToken(AsmToken::EndOfStatement))
11800     return true;
11801 
11802   getTargetStreamer().emitObjectArch(ID);
11803   return false;
11804 }
11805 
11806 /// parseDirectiveAlign
11807 ///   ::= .align
11808 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
11809   // NOTE: if this is not the end of the statement, fall back to the target
11810   // agnostic handling for this directive which will correctly handle this.
11811   if (parseOptionalToken(AsmToken::EndOfStatement)) {
11812     // '.align' is target specifically handled to mean 2**2 byte alignment.
11813     const MCSection *Section = getStreamer().getCurrentSectionOnly();
11814     assert(Section && "must have section to emit alignment");
11815     if (Section->UseCodeAlign())
11816       getStreamer().emitCodeAlignment(4, 0);
11817     else
11818       getStreamer().emitValueToAlignment(4, 0, 1, 0);
11819     return false;
11820   }
11821   return true;
11822 }
11823 
11824 /// parseDirectiveThumbSet
11825 ///  ::= .thumb_set name, value
11826 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
11827   MCAsmParser &Parser = getParser();
11828 
11829   StringRef Name;
11830   if (check(Parser.parseIdentifier(Name),
11831             "expected identifier after '.thumb_set'") ||
11832       parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
11833     return true;
11834 
11835   MCSymbol *Sym;
11836   const MCExpr *Value;
11837   if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
11838                                                Parser, Sym, Value))
11839     return true;
11840 
11841   getTargetStreamer().emitThumbSet(Sym, Value);
11842   return false;
11843 }
11844 
11845 /// Force static initialization.
11846 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmParser() {
11847   RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
11848   RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
11849   RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
11850   RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
11851 }
11852 
11853 #define GET_REGISTER_MATCHER
11854 #define GET_SUBTARGET_FEATURE_NAME
11855 #define GET_MATCHER_IMPLEMENTATION
11856 #define GET_MNEMONIC_SPELL_CHECKER
11857 #include "ARMGenAsmMatcher.inc"
11858 
11859 // Some diagnostics need to vary with subtarget features, so they are handled
11860 // here. For example, the DPR class has either 16 or 32 registers, depending
11861 // on the FPU available.
11862 const char *
11863 ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
11864   switch (MatchError) {
11865   // rGPR contains sp starting with ARMv8.
11866   case Match_rGPR:
11867     return hasV8Ops() ? "operand must be a register in range [r0, r14]"
11868                       : "operand must be a register in range [r0, r12] or r14";
11869   // DPR contains 16 registers for some FPUs, and 32 for others.
11870   case Match_DPR:
11871     return hasD32() ? "operand must be a register in range [d0, d31]"
11872                     : "operand must be a register in range [d0, d15]";
11873   case Match_DPR_RegList:
11874     return hasD32() ? "operand must be a list of registers in range [d0, d31]"
11875                     : "operand must be a list of registers in range [d0, d15]";
11876 
11877   // For all other diags, use the static string from tablegen.
11878   default:
11879     return getMatchKindDiag(MatchError);
11880   }
11881 }
11882 
11883 // Process the list of near-misses, throwing away ones we don't want to report
11884 // to the user, and converting the rest to a source location and string that
11885 // should be reported.
11886 void
11887 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
11888                                SmallVectorImpl<NearMissMessage> &NearMissesOut,
11889                                SMLoc IDLoc, OperandVector &Operands) {
11890   // TODO: If operand didn't match, sub in a dummy one and run target
11891   // predicate, so that we can avoid reporting near-misses that are invalid?
11892   // TODO: Many operand types dont have SuperClasses set, so we report
11893   // redundant ones.
11894   // TODO: Some operands are superclasses of registers (e.g.
11895   // MCK_RegShiftedImm), we don't have any way to represent that currently.
11896   // TODO: This is not all ARM-specific, can some of it be factored out?
11897 
11898   // Record some information about near-misses that we have already seen, so
11899   // that we can avoid reporting redundant ones. For example, if there are
11900   // variants of an instruction that take 8- and 16-bit immediates, we want
11901   // to only report the widest one.
11902   std::multimap<unsigned, unsigned> OperandMissesSeen;
11903   SmallSet<FeatureBitset, 4> FeatureMissesSeen;
11904   bool ReportedTooFewOperands = false;
11905 
11906   // Process the near-misses in reverse order, so that we see more general ones
11907   // first, and so can avoid emitting more specific ones.
11908   for (NearMissInfo &I : reverse(NearMissesIn)) {
11909     switch (I.getKind()) {
11910     case NearMissInfo::NearMissOperand: {
11911       SMLoc OperandLoc =
11912           ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
11913       const char *OperandDiag =
11914           getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
11915 
11916       // If we have already emitted a message for a superclass, don't also report
11917       // the sub-class. We consider all operand classes that we don't have a
11918       // specialised diagnostic for to be equal for the propose of this check,
11919       // so that we don't report the generic error multiple times on the same
11920       // operand.
11921       unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
11922       auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
11923       if (std::any_of(PrevReports.first, PrevReports.second,
11924                       [DupCheckMatchClass](
11925                           const std::pair<unsigned, unsigned> Pair) {
11926             if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
11927               return Pair.second == DupCheckMatchClass;
11928             else
11929               return isSubclass((MatchClassKind)DupCheckMatchClass,
11930                                 (MatchClassKind)Pair.second);
11931           }))
11932         break;
11933       OperandMissesSeen.insert(
11934           std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
11935 
11936       NearMissMessage Message;
11937       Message.Loc = OperandLoc;
11938       if (OperandDiag) {
11939         Message.Message = OperandDiag;
11940       } else if (I.getOperandClass() == InvalidMatchClass) {
11941         Message.Message = "too many operands for instruction";
11942       } else {
11943         Message.Message = "invalid operand for instruction";
11944         LLVM_DEBUG(
11945             dbgs() << "Missing diagnostic string for operand class "
11946                    << getMatchClassName((MatchClassKind)I.getOperandClass())
11947                    << I.getOperandClass() << ", error " << I.getOperandError()
11948                    << ", opcode " << MII.getName(I.getOpcode()) << "\n");
11949       }
11950       NearMissesOut.emplace_back(Message);
11951       break;
11952     }
11953     case NearMissInfo::NearMissFeature: {
11954       const FeatureBitset &MissingFeatures = I.getFeatures();
11955       // Don't report the same set of features twice.
11956       if (FeatureMissesSeen.count(MissingFeatures))
11957         break;
11958       FeatureMissesSeen.insert(MissingFeatures);
11959 
11960       // Special case: don't report a feature set which includes arm-mode for
11961       // targets that don't have ARM mode.
11962       if (MissingFeatures.test(Feature_IsARMBit) && !hasARM())
11963         break;
11964       // Don't report any near-misses that both require switching instruction
11965       // set, and adding other subtarget features.
11966       if (isThumb() && MissingFeatures.test(Feature_IsARMBit) &&
11967           MissingFeatures.count() > 1)
11968         break;
11969       if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) &&
11970           MissingFeatures.count() > 1)
11971         break;
11972       if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) &&
11973           (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit,
11974                                              Feature_IsThumbBit})).any())
11975         break;
11976       if (isMClass() && MissingFeatures.test(Feature_HasNEONBit))
11977         break;
11978 
11979       NearMissMessage Message;
11980       Message.Loc = IDLoc;
11981       raw_svector_ostream OS(Message.Message);
11982 
11983       OS << "instruction requires:";
11984       for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
11985         if (MissingFeatures.test(i))
11986           OS << ' ' << getSubtargetFeatureName(i);
11987 
11988       NearMissesOut.emplace_back(Message);
11989 
11990       break;
11991     }
11992     case NearMissInfo::NearMissPredicate: {
11993       NearMissMessage Message;
11994       Message.Loc = IDLoc;
11995       switch (I.getPredicateError()) {
11996       case Match_RequiresNotITBlock:
11997         Message.Message = "flag setting instruction only valid outside IT block";
11998         break;
11999       case Match_RequiresITBlock:
12000         Message.Message = "instruction only valid inside IT block";
12001         break;
12002       case Match_RequiresV6:
12003         Message.Message = "instruction variant requires ARMv6 or later";
12004         break;
12005       case Match_RequiresThumb2:
12006         Message.Message = "instruction variant requires Thumb2";
12007         break;
12008       case Match_RequiresV8:
12009         Message.Message = "instruction variant requires ARMv8 or later";
12010         break;
12011       case Match_RequiresFlagSetting:
12012         Message.Message = "no flag-preserving variant of this instruction available";
12013         break;
12014       case Match_InvalidOperand:
12015         Message.Message = "invalid operand for instruction";
12016         break;
12017       default:
12018         llvm_unreachable("Unhandled target predicate error");
12019         break;
12020       }
12021       NearMissesOut.emplace_back(Message);
12022       break;
12023     }
12024     case NearMissInfo::NearMissTooFewOperands: {
12025       if (!ReportedTooFewOperands) {
12026         SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
12027         NearMissesOut.emplace_back(NearMissMessage{
12028             EndLoc, StringRef("too few operands for instruction")});
12029         ReportedTooFewOperands = true;
12030       }
12031       break;
12032     }
12033     case NearMissInfo::NoNearMiss:
12034       // This should never leave the matcher.
12035       llvm_unreachable("not a near-miss");
12036       break;
12037     }
12038   }
12039 }
12040 
12041 void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
12042                                     SMLoc IDLoc, OperandVector &Operands) {
12043   SmallVector<NearMissMessage, 4> Messages;
12044   FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
12045 
12046   if (Messages.size() == 0) {
12047     // No near-misses were found, so the best we can do is "invalid
12048     // instruction".
12049     Error(IDLoc, "invalid instruction");
12050   } else if (Messages.size() == 1) {
12051     // One near miss was found, report it as the sole error.
12052     Error(Messages[0].Loc, Messages[0].Message);
12053   } else {
12054     // More than one near miss, so report a generic "invalid instruction"
12055     // error, followed by notes for each of the near-misses.
12056     Error(IDLoc, "invalid instruction, any one of the following would fix this:");
12057     for (auto &M : Messages) {
12058       Note(M.Loc, M.Message);
12059     }
12060   }
12061 }
12062 
12063 /// parseDirectiveArchExtension
12064 ///   ::= .arch_extension [no]feature
12065 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
12066   // FIXME: This structure should be moved inside ARMTargetParser
12067   // when we start to table-generate them, and we can use the ARM
12068   // flags below, that were generated by table-gen.
12069   static const struct {
12070     const uint64_t Kind;
12071     const FeatureBitset ArchCheck;
12072     const FeatureBitset Features;
12073   } Extensions[] = {
12074     { ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC} },
12075     { ARM::AEK_CRYPTO,  {Feature_HasV8Bit},
12076       {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
12077     { ARM::AEK_FP, {Feature_HasV8Bit},
12078       {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
12079     { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
12080       {Feature_HasV7Bit, Feature_IsNotMClassBit},
12081       {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
12082     { ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit},
12083       {ARM::FeatureMP} },
12084     { ARM::AEK_SIMD, {Feature_HasV8Bit},
12085       {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
12086     { ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} },
12087     // FIXME: Only available in A-class, isel not predicated
12088     { ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} },
12089     { ARM::AEK_FP16, {Feature_HasV8_2aBit},
12090       {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
12091     { ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS} },
12092     { ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB} },
12093     // FIXME: Unsupported extensions.
12094     { ARM::AEK_OS, {}, {} },
12095     { ARM::AEK_IWMMXT, {}, {} },
12096     { ARM::AEK_IWMMXT2, {}, {} },
12097     { ARM::AEK_MAVERICK, {}, {} },
12098     { ARM::AEK_XSCALE, {}, {} },
12099   };
12100 
12101   MCAsmParser &Parser = getParser();
12102 
12103   if (getLexer().isNot(AsmToken::Identifier))
12104     return Error(getLexer().getLoc(), "expected architecture extension name");
12105 
12106   StringRef Name = Parser.getTok().getString();
12107   SMLoc ExtLoc = Parser.getTok().getLoc();
12108   Lex();
12109 
12110   if (parseToken(AsmToken::EndOfStatement,
12111                  "unexpected token in '.arch_extension' directive"))
12112     return true;
12113 
12114   bool EnableFeature = true;
12115   if (Name.startswith_lower("no")) {
12116     EnableFeature = false;
12117     Name = Name.substr(2);
12118   }
12119   uint64_t FeatureKind = ARM::parseArchExt(Name);
12120   if (FeatureKind == ARM::AEK_INVALID)
12121     return Error(ExtLoc, "unknown architectural extension: " + Name);
12122 
12123   for (const auto &Extension : Extensions) {
12124     if (Extension.Kind != FeatureKind)
12125       continue;
12126 
12127     if (Extension.Features.none())
12128       return Error(ExtLoc, "unsupported architectural extension: " + Name);
12129 
12130     if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
12131       return Error(ExtLoc, "architectural extension '" + Name +
12132                                "' is not "
12133                                "allowed for the current base architecture");
12134 
12135     MCSubtargetInfo &STI = copySTI();
12136     if (EnableFeature) {
12137       STI.SetFeatureBitsTransitively(Extension.Features);
12138     } else {
12139       STI.ClearFeatureBitsTransitively(Extension.Features);
12140     }
12141     FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
12142     setAvailableFeatures(Features);
12143     return false;
12144   }
12145 
12146   return Error(ExtLoc, "unknown architectural extension: " + Name);
12147 }
12148 
12149 // Define this matcher function after the auto-generated include so we
12150 // have the match class enum definitions.
12151 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
12152                                                   unsigned Kind) {
12153   ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
12154   // If the kind is a token for a literal immediate, check if our asm
12155   // operand matches. This is for InstAliases which have a fixed-value
12156   // immediate in the syntax.
12157   switch (Kind) {
12158   default: break;
12159   case MCK__HASH_0:
12160     if (Op.isImm())
12161       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12162         if (CE->getValue() == 0)
12163           return Match_Success;
12164     break;
12165   case MCK__HASH_8:
12166     if (Op.isImm())
12167       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12168         if (CE->getValue() == 8)
12169           return Match_Success;
12170     break;
12171   case MCK__HASH_16:
12172     if (Op.isImm())
12173       if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
12174         if (CE->getValue() == 16)
12175           return Match_Success;
12176     break;
12177   case MCK_ModImm:
12178     if (Op.isImm()) {
12179       const MCExpr *SOExpr = Op.getImm();
12180       int64_t Value;
12181       if (!SOExpr->evaluateAsAbsolute(Value))
12182         return Match_Success;
12183       assert((Value >= std::numeric_limits<int32_t>::min() &&
12184               Value <= std::numeric_limits<uint32_t>::max()) &&
12185              "expression value must be representable in 32 bits");
12186     }
12187     break;
12188   case MCK_rGPR:
12189     if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
12190       return Match_Success;
12191     return Match_rGPR;
12192   case MCK_GPRPair:
12193     if (Op.isReg() &&
12194         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
12195       return Match_Success;
12196     break;
12197   }
12198   return Match_InvalidOperand;
12199 }
12200 
12201 bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
12202                                            StringRef ExtraToken) {
12203   if (!hasMVE())
12204     return false;
12205 
12206   return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
12207          Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
12208          Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
12209          Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
12210          Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
12211          Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
12212          Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
12213          Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
12214          Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
12215          Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
12216          Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
12217          Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
12218          Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
12219          Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
12220          Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
12221          Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
12222          Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
12223          Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
12224          Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
12225          Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
12226          Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
12227          Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
12228          Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
12229          Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
12230          Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
12231          Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
12232          Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
12233          Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
12234          Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
12235          Mnemonic.startswith("vqabs") ||
12236          (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
12237          Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
12238          Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
12239          Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
12240          Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
12241          Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
12242          Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
12243          Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
12244          Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
12245          Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
12246          Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
12247          Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
12248          Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
12249          Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
12250          Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
12251          Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
12252          Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
12253          Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
12254          Mnemonic.startswith("vldrb") ||
12255          (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
12256          (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
12257          Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
12258          Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
12259          Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
12260          Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
12261          Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
12262          Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
12263          Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
12264          Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
12265          Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
12266          Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
12267          Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
12268          Mnemonic.startswith("vcvt") ||
12269          MS.isVPTPredicableCDEInstr(Mnemonic) ||
12270          (Mnemonic.startswith("vmov") &&
12271           !(ExtraToken == ".f16" || ExtraToken == ".32" ||
12272             ExtraToken == ".16" || ExtraToken == ".8"));
12273 }
12274