1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the ARM specific subclass of TargetMachine. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 14 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 15 16 #include "ARMSubtarget.h" 17 #include "llvm/ADT/StringMap.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/Support/CodeGen.h" 21 #include "llvm/Target/TargetMachine.h" 22 #include <memory> 23 #include <optional> 24 25 namespace llvm { 26 27 class ARMBaseTargetMachine : public LLVMTargetMachine { 28 public: 29 enum ARMABI { 30 ARM_ABI_UNKNOWN, 31 ARM_ABI_APCS, 32 ARM_ABI_AAPCS, // ARM EABI 33 ARM_ABI_AAPCS16 34 } TargetABI; 35 36 protected: 37 std::unique_ptr<TargetLoweringObjectFile> TLOF; 38 bool isLittle; 39 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap; 40 41 public: 42 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 43 StringRef FS, const TargetOptions &Options, 44 std::optional<Reloc::Model> RM, 45 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, 46 bool isLittle); 47 ~ARMBaseTargetMachine() override; 48 49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override; 50 // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget, 51 // subtargets are per-function entities based on the target-specific 52 // attributes of each function. 53 const ARMSubtarget *getSubtargetImpl() const = delete; 54 bool isLittleEndian() const { return isLittle; } 55 56 TargetTransformInfo getTargetTransformInfo(const Function &F) const override; 57 58 // Pass Pipeline Configuration 59 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 60 61 TargetLoweringObjectFile *getObjFileLowering() const override { 62 return TLOF.get(); 63 } 64 65 bool isTargetHardFloat() const { 66 return TargetTriple.getEnvironment() == Triple::GNUEABIHF || 67 TargetTriple.getEnvironment() == Triple::GNUEABIHFT64 || 68 TargetTriple.getEnvironment() == Triple::MuslEABIHF || 69 TargetTriple.getEnvironment() == Triple::EABIHF || 70 (TargetTriple.isOSBinFormatMachO() && 71 TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) || 72 TargetTriple.isOSWindows() || 73 TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; 74 } 75 76 bool targetSchedulesPostRAScheduling() const override { return true; }; 77 78 MachineFunctionInfo * 79 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, 80 const TargetSubtargetInfo *STI) const override; 81 82 /// Returns true if a cast between SrcAS and DestAS is a noop. 83 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 84 // Addrspacecasts are always noops. 85 return true; 86 } 87 88 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; 89 yaml::MachineFunctionInfo * 90 convertFuncInfoToYAML(const MachineFunction &MF) const override; 91 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, 92 PerFunctionMIParsingState &PFS, 93 SMDiagnostic &Error, 94 SMRange &SourceRange) const override; 95 }; 96 97 /// ARM/Thumb little endian target machine. 98 /// 99 class ARMLETargetMachine : public ARMBaseTargetMachine { 100 public: 101 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 102 StringRef FS, const TargetOptions &Options, 103 std::optional<Reloc::Model> RM, 104 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, 105 bool JIT); 106 }; 107 108 /// ARM/Thumb big endian target machine. 109 /// 110 class ARMBETargetMachine : public ARMBaseTargetMachine { 111 public: 112 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 113 StringRef FS, const TargetOptions &Options, 114 std::optional<Reloc::Model> RM, 115 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, 116 bool JIT); 117 }; 118 119 } // end namespace llvm 120 121 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 122