1*0b57cec5SDimitry Andric //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file declares the ARM specific subclass of TargetMachine. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "ARMSubtarget.h" 17*0b57cec5SDimitry Andric #include "llvm/ADT/Optional.h" 18*0b57cec5SDimitry Andric #include "llvm/ADT/StringMap.h" 19*0b57cec5SDimitry Andric #include "llvm/ADT/StringRef.h" 20*0b57cec5SDimitry Andric #include "llvm/Analysis/TargetTransformInfo.h" 21*0b57cec5SDimitry Andric #include "llvm/Support/CodeGen.h" 22*0b57cec5SDimitry Andric #include "llvm/Target/TargetMachine.h" 23*0b57cec5SDimitry Andric #include <memory> 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andric namespace llvm { 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric class ARMBaseTargetMachine : public LLVMTargetMachine { 28*0b57cec5SDimitry Andric public: 29*0b57cec5SDimitry Andric enum ARMABI { 30*0b57cec5SDimitry Andric ARM_ABI_UNKNOWN, 31*0b57cec5SDimitry Andric ARM_ABI_APCS, 32*0b57cec5SDimitry Andric ARM_ABI_AAPCS, // ARM EABI 33*0b57cec5SDimitry Andric ARM_ABI_AAPCS16 34*0b57cec5SDimitry Andric } TargetABI; 35*0b57cec5SDimitry Andric 36*0b57cec5SDimitry Andric protected: 37*0b57cec5SDimitry Andric std::unique_ptr<TargetLoweringObjectFile> TLOF; 38*0b57cec5SDimitry Andric bool isLittle; 39*0b57cec5SDimitry Andric mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap; 40*0b57cec5SDimitry Andric 41*0b57cec5SDimitry Andric public: 42*0b57cec5SDimitry Andric ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 43*0b57cec5SDimitry Andric StringRef FS, const TargetOptions &Options, 44*0b57cec5SDimitry Andric Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 45*0b57cec5SDimitry Andric CodeGenOpt::Level OL, bool isLittle); 46*0b57cec5SDimitry Andric ~ARMBaseTargetMachine() override; 47*0b57cec5SDimitry Andric 48*0b57cec5SDimitry Andric const ARMSubtarget *getSubtargetImpl(const Function &F) const override; 49*0b57cec5SDimitry Andric // DO NOT IMPLEMENT: There is no such thing as a valid default subtarget, 50*0b57cec5SDimitry Andric // subtargets are per-function entities based on the target-specific 51*0b57cec5SDimitry Andric // attributes of each function. 52*0b57cec5SDimitry Andric const ARMSubtarget *getSubtargetImpl() const = delete; 53*0b57cec5SDimitry Andric bool isLittleEndian() const { return isLittle; } 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric TargetTransformInfo getTargetTransformInfo(const Function &F) override; 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric // Pass Pipeline Configuration 58*0b57cec5SDimitry Andric TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andric TargetLoweringObjectFile *getObjFileLowering() const override { 61*0b57cec5SDimitry Andric return TLOF.get(); 62*0b57cec5SDimitry Andric } 63*0b57cec5SDimitry Andric 64*0b57cec5SDimitry Andric bool isTargetHardFloat() const { 65*0b57cec5SDimitry Andric return TargetTriple.getEnvironment() == Triple::GNUEABIHF || 66*0b57cec5SDimitry Andric TargetTriple.getEnvironment() == Triple::MuslEABIHF || 67*0b57cec5SDimitry Andric TargetTriple.getEnvironment() == Triple::EABIHF || 68*0b57cec5SDimitry Andric (TargetTriple.isOSBinFormatMachO() && 69*0b57cec5SDimitry Andric TargetTriple.getSubArch() == Triple::ARMSubArch_v7em) || 70*0b57cec5SDimitry Andric TargetTriple.isOSWindows() || 71*0b57cec5SDimitry Andric TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; 72*0b57cec5SDimitry Andric } 73*0b57cec5SDimitry Andric }; 74*0b57cec5SDimitry Andric 75*0b57cec5SDimitry Andric /// ARM/Thumb little endian target machine. 76*0b57cec5SDimitry Andric /// 77*0b57cec5SDimitry Andric class ARMLETargetMachine : public ARMBaseTargetMachine { 78*0b57cec5SDimitry Andric public: 79*0b57cec5SDimitry Andric ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 80*0b57cec5SDimitry Andric StringRef FS, const TargetOptions &Options, 81*0b57cec5SDimitry Andric Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 82*0b57cec5SDimitry Andric CodeGenOpt::Level OL, bool JIT); 83*0b57cec5SDimitry Andric }; 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andric /// ARM/Thumb big endian target machine. 86*0b57cec5SDimitry Andric /// 87*0b57cec5SDimitry Andric class ARMBETargetMachine : public ARMBaseTargetMachine { 88*0b57cec5SDimitry Andric public: 89*0b57cec5SDimitry Andric ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 90*0b57cec5SDimitry Andric StringRef FS, const TargetOptions &Options, 91*0b57cec5SDimitry Andric Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, 92*0b57cec5SDimitry Andric CodeGenOpt::Level OL, bool JIT); 93*0b57cec5SDimitry Andric }; 94*0b57cec5SDimitry Andric 95*0b57cec5SDimitry Andric } // end namespace llvm 96*0b57cec5SDimitry Andric 97*0b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 98