xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARMTargetMachine.cpp (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMachineFunctionInfo.h"
15 #include "ARMMacroFusion.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetObjectFile.h"
18 #include "ARMTargetTransformInfo.h"
19 #include "MCTargetDesc/ARMMCTargetDesc.h"
20 #include "TargetInfo/ARMTargetInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/Analysis/TargetTransformInfo.h"
24 #include "llvm/CodeGen/ExecutionDomainFix.h"
25 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineScheduler.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/RegisterBankInfo.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/TargetRegistry.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/TargetParser/ARMTargetParser.h"
49 #include "llvm/TargetParser/TargetParser.h"
50 #include "llvm/TargetParser/Triple.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include "llvm/Transforms/IPO.h"
53 #include "llvm/Transforms/Scalar.h"
54 #include <cassert>
55 #include <memory>
56 #include <optional>
57 #include <string>
58 
59 using namespace llvm;
60 
61 static cl::opt<bool>
62 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
63                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
64                    cl::init(false));
65 
66 static cl::opt<bool>
67 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
68                  cl::desc("Run SimplifyCFG after expanding atomic operations"
69                           " to make use of cmpxchg flow-based information"),
70                  cl::init(true));
71 
72 static cl::opt<bool>
73 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
74                       cl::desc("Enable ARM load/store optimization pass"),
75                       cl::init(true));
76 
77 // FIXME: Unify control over GlobalMerge.
78 static cl::opt<cl::boolOrDefault>
79 EnableGlobalMerge("arm-global-merge", cl::Hidden,
80                   cl::desc("Enable the global merge pass"));
81 
82 namespace llvm {
83   void initializeARMExecutionDomainFixPass(PassRegistry&);
84 }
85 
86 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
87   // Register the target.
88   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
89   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
90   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
91   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
92 
93   PassRegistry &Registry = *PassRegistry::getPassRegistry();
94   initializeGlobalISel(Registry);
95   initializeARMLoadStoreOptPass(Registry);
96   initializeARMPreAllocLoadStoreOptPass(Registry);
97   initializeARMParallelDSPPass(Registry);
98   initializeARMBranchTargetsPass(Registry);
99   initializeARMConstantIslandsPass(Registry);
100   initializeARMExecutionDomainFixPass(Registry);
101   initializeARMExpandPseudoPass(Registry);
102   initializeThumb2SizeReducePass(Registry);
103   initializeMVEVPTBlockPass(Registry);
104   initializeMVETPAndVPTOptimisationsPass(Registry);
105   initializeMVETailPredicationPass(Registry);
106   initializeARMLowOverheadLoopsPass(Registry);
107   initializeARMBlockPlacementPass(Registry);
108   initializeMVEGatherScatterLoweringPass(Registry);
109   initializeARMSLSHardeningPass(Registry);
110   initializeMVELaneInterleavingPass(Registry);
111   initializeARMFixCortexA57AES1742098Pass(Registry);
112   initializeARMDAGToDAGISelPass(Registry);
113 }
114 
115 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
116   if (TT.isOSBinFormatMachO())
117     return std::make_unique<TargetLoweringObjectFileMachO>();
118   if (TT.isOSWindows())
119     return std::make_unique<TargetLoweringObjectFileCOFF>();
120   return std::make_unique<ARMElfTargetObjectFile>();
121 }
122 
123 static ARMBaseTargetMachine::ARMABI
124 computeTargetABI(const Triple &TT, StringRef CPU,
125                  const TargetOptions &Options) {
126   StringRef ABIName = Options.MCOptions.getABIName();
127 
128   if (ABIName.empty())
129     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
130 
131   if (ABIName == "aapcs16")
132     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
133   else if (ABIName.startswith("aapcs"))
134     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
135   else if (ABIName.startswith("apcs"))
136     return ARMBaseTargetMachine::ARM_ABI_APCS;
137 
138   llvm_unreachable("Unhandled/unknown ABI Name!");
139   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
140 }
141 
142 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
143                                      const TargetOptions &Options,
144                                      bool isLittle) {
145   auto ABI = computeTargetABI(TT, CPU, Options);
146   std::string Ret;
147 
148   if (isLittle)
149     // Little endian.
150     Ret += "e";
151   else
152     // Big endian.
153     Ret += "E";
154 
155   Ret += DataLayout::getManglingComponent(TT);
156 
157   // Pointers are 32 bits and aligned to 32 bits.
158   Ret += "-p:32:32";
159 
160   // Function pointers are aligned to 8 bits (because the LSB stores the
161   // ARM/Thumb state).
162   Ret += "-Fi8";
163 
164   // ABIs other than APCS have 64 bit integers with natural alignment.
165   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
166     Ret += "-i64:64";
167 
168   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
169   // bits, others to 64 bits. We always try to align to 64 bits.
170   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
171     Ret += "-f64:32:64";
172 
173   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
174   // to 64. We always ty to give them natural alignment.
175   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
176     Ret += "-v64:32:64-v128:32:128";
177   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
178     Ret += "-v128:64:128";
179 
180   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
181   // particular hardware support on 32-bit ARM).
182   Ret += "-a:0:32";
183 
184   // Integer registers are 32 bits.
185   Ret += "-n32";
186 
187   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
188   // aligned everywhere else.
189   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
190     Ret += "-S128";
191   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
192     Ret += "-S64";
193   else
194     Ret += "-S32";
195 
196   return Ret;
197 }
198 
199 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
200                                            std::optional<Reloc::Model> RM) {
201   if (!RM)
202     // Default relocation model on Darwin is PIC.
203     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
204 
205   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
206     assert(TT.isOSBinFormatELF() &&
207            "ROPI/RWPI currently only supported for ELF");
208 
209   // DynamicNoPIC is only used on darwin.
210   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
211     return Reloc::Static;
212 
213   return *RM;
214 }
215 
216 /// Create an ARM architecture model.
217 ///
218 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
219                                            StringRef CPU, StringRef FS,
220                                            const TargetOptions &Options,
221                                            std::optional<Reloc::Model> RM,
222                                            std::optional<CodeModel::Model> CM,
223                                            CodeGenOpt::Level OL, bool isLittle)
224     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
225                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
226                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
227       TargetABI(computeTargetABI(TT, CPU, Options)),
228       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
229 
230   // Default to triple-appropriate float ABI
231   if (Options.FloatABIType == FloatABI::Default) {
232     if (isTargetHardFloat())
233       this->Options.FloatABIType = FloatABI::Hard;
234     else
235       this->Options.FloatABIType = FloatABI::Soft;
236   }
237 
238   // Default to triple-appropriate EABI
239   if (Options.EABIVersion == EABI::Default ||
240       Options.EABIVersion == EABI::Unknown) {
241     // musl is compatible with glibc with regard to EABI version
242     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
243          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
244          TargetTriple.getEnvironment() == Triple::MuslEABI ||
245          TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
246          TargetTriple.getEnvironment() == Triple::OpenHOS) &&
247         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
248       this->Options.EABIVersion = EABI::GNU;
249     else
250       this->Options.EABIVersion = EABI::EABI5;
251   }
252 
253   if (TT.isOSBinFormatMachO()) {
254     this->Options.TrapUnreachable = true;
255     this->Options.NoTrapAfterNoreturn = true;
256   }
257 
258   // ARM supports the debug entry values.
259   setSupportsDebugEntryValues(true);
260 
261   initAsmInfo();
262 
263   // ARM supports the MachineOutliner.
264   setMachineOutliner(true);
265   setSupportsDefaultOutlining(true);
266 }
267 
268 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
269 
270 MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
271     BumpPtrAllocator &Allocator, const Function &F,
272     const TargetSubtargetInfo *STI) const {
273   return ARMFunctionInfo::create<ARMFunctionInfo>(
274       Allocator, F, static_cast<const ARMSubtarget *>(STI));
275 }
276 
277 const ARMSubtarget *
278 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
279   Attribute CPUAttr = F.getFnAttribute("target-cpu");
280   Attribute FSAttr = F.getFnAttribute("target-features");
281 
282   std::string CPU =
283       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
284   std::string FS =
285       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
286 
287   // FIXME: This is related to the code below to reset the target options,
288   // we need to know whether or not the soft float flag is set on the
289   // function before we can generate a subtarget. We also need to use
290   // it as a key for the subtarget since that can be the only difference
291   // between two functions.
292   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
293   // If the soft float attribute is set on the function turn on the soft float
294   // subtarget feature.
295   if (SoftFloat)
296     FS += FS.empty() ? "+soft-float" : ",+soft-float";
297 
298   // Use the optminsize to identify the subtarget, but don't use it in the
299   // feature string.
300   std::string Key = CPU + FS;
301   if (F.hasMinSize())
302     Key += "+minsize";
303 
304   auto &I = SubtargetMap[Key];
305   if (!I) {
306     // This needs to be done before we create a new subtarget since any
307     // creation will depend on the TM and the code generation flags on the
308     // function that reside in TargetOptions.
309     resetTargetOptions(F);
310     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
311                                         F.hasMinSize());
312 
313     if (!I->isThumb() && !I->hasARMOps())
314       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
315           "instructions, but the target does not support ARM mode execution.");
316   }
317 
318   return I.get();
319 }
320 
321 TargetTransformInfo
322 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
323   return TargetTransformInfo(ARMTTIImpl(this, F));
324 }
325 
326 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
327                                        StringRef CPU, StringRef FS,
328                                        const TargetOptions &Options,
329                                        std::optional<Reloc::Model> RM,
330                                        std::optional<CodeModel::Model> CM,
331                                        CodeGenOpt::Level OL, bool JIT)
332     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
333 
334 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
335                                        StringRef CPU, StringRef FS,
336                                        const TargetOptions &Options,
337                                        std::optional<Reloc::Model> RM,
338                                        std::optional<CodeModel::Model> CM,
339                                        CodeGenOpt::Level OL, bool JIT)
340     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
341 
342 namespace {
343 
344 /// ARM Code Generator Pass Configuration Options.
345 class ARMPassConfig : public TargetPassConfig {
346 public:
347   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
348       : TargetPassConfig(TM, PM) {}
349 
350   ARMBaseTargetMachine &getARMTargetMachine() const {
351     return getTM<ARMBaseTargetMachine>();
352   }
353 
354   ScheduleDAGInstrs *
355   createMachineScheduler(MachineSchedContext *C) const override {
356     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
357     // add DAG Mutations here.
358     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
359     if (ST.hasFusion())
360       DAG->addMutation(createARMMacroFusionDAGMutation());
361     return DAG;
362   }
363 
364   ScheduleDAGInstrs *
365   createPostMachineScheduler(MachineSchedContext *C) const override {
366     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
367     // add DAG Mutations here.
368     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
369     if (ST.hasFusion())
370       DAG->addMutation(createARMMacroFusionDAGMutation());
371     return DAG;
372   }
373 
374   void addIRPasses() override;
375   void addCodeGenPrepare() override;
376   bool addPreISel() override;
377   bool addInstSelector() override;
378   bool addIRTranslator() override;
379   bool addLegalizeMachineIR() override;
380   bool addRegBankSelect() override;
381   bool addGlobalInstructionSelect() override;
382   void addPreRegAlloc() override;
383   void addPreSched2() override;
384   void addPreEmitPass() override;
385   void addPreEmitPass2() override;
386 
387   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
388 };
389 
390 class ARMExecutionDomainFix : public ExecutionDomainFix {
391 public:
392   static char ID;
393   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
394   StringRef getPassName() const override {
395     return "ARM Execution Domain Fix";
396   }
397 };
398 char ARMExecutionDomainFix::ID;
399 
400 } // end anonymous namespace
401 
402 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
403   "ARM Execution Domain Fix", false, false)
404 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
405 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
406   "ARM Execution Domain Fix", false, false)
407 
408 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
409   return new ARMPassConfig(*this, PM);
410 }
411 
412 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
413   return getStandardCSEConfigForOpt(TM->getOptLevel());
414 }
415 
416 void ARMPassConfig::addIRPasses() {
417   if (TM->Options.ThreadModel == ThreadModel::Single)
418     addPass(createLowerAtomicPass());
419   else
420     addPass(createAtomicExpandPass());
421 
422   // Cmpxchg instructions are often used with a subsequent comparison to
423   // determine whether it succeeded. We can exploit existing control-flow in
424   // ldrex/strex loops to simplify this, but it needs tidying up.
425   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
426     addPass(createCFGSimplificationPass(
427         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
428         [this](const Function &F) {
429           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
430           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
431         }));
432 
433   addPass(createMVEGatherScatterLoweringPass());
434   addPass(createMVELaneInterleavingPass());
435 
436   TargetPassConfig::addIRPasses();
437 
438   // Run the parallel DSP pass.
439   if (getOptLevel() == CodeGenOpt::Aggressive)
440     addPass(createARMParallelDSPPass());
441 
442   // Match complex arithmetic patterns
443   if (TM->getOptLevel() >= CodeGenOpt::Default)
444     addPass(createComplexDeinterleavingPass(TM));
445 
446   // Match interleaved memory accesses to ldN/stN intrinsics.
447   if (TM->getOptLevel() != CodeGenOpt::None)
448     addPass(createInterleavedAccessPass());
449 
450   // Add Control Flow Guard checks.
451   if (TM->getTargetTriple().isOSWindows())
452     addPass(createCFGuardCheckPass());
453 
454   if (TM->Options.JMCInstrument)
455     addPass(createJMCInstrumenterPass());
456 }
457 
458 void ARMPassConfig::addCodeGenPrepare() {
459   if (getOptLevel() != CodeGenOpt::None)
460     addPass(createTypePromotionLegacyPass());
461   TargetPassConfig::addCodeGenPrepare();
462 }
463 
464 bool ARMPassConfig::addPreISel() {
465   if ((TM->getOptLevel() != CodeGenOpt::None &&
466        EnableGlobalMerge == cl::BOU_UNSET) ||
467       EnableGlobalMerge == cl::BOU_TRUE) {
468     // FIXME: This is using the thumb1 only constant value for
469     // maximal global offset for merging globals. We may want
470     // to look into using the old value for non-thumb1 code of
471     // 4095 based on the TargetMachine, but this starts to become
472     // tricky when doing code gen per function.
473     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
474                                (EnableGlobalMerge == cl::BOU_UNSET);
475     // Merging of extern globals is enabled by default on non-Mach-O as we
476     // expect it to be generally either beneficial or harmless. On Mach-O it
477     // is disabled as we emit the .subsections_via_symbols directive which
478     // means that merging extern globals is not safe.
479     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
480     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
481                                   MergeExternalByDefault));
482   }
483 
484   if (TM->getOptLevel() != CodeGenOpt::None) {
485     addPass(createHardwareLoopsLegacyPass());
486     addPass(createMVETailPredicationPass());
487     // FIXME: IR passes can delete address-taken basic blocks, deleting
488     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
489     // address-taken basic blocks which can be invalidated if the function
490     // containing the blockaddress has already been codegen'd and the basic
491     // block is removed. Work around this by forcing all IR passes to run before
492     // any ISel takes place. We should have a more principled way of handling
493     // this. See D99707 for more details.
494     addPass(createBarrierNoopPass());
495   }
496 
497   return false;
498 }
499 
500 bool ARMPassConfig::addInstSelector() {
501   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
502   return false;
503 }
504 
505 bool ARMPassConfig::addIRTranslator() {
506   addPass(new IRTranslator(getOptLevel()));
507   return false;
508 }
509 
510 bool ARMPassConfig::addLegalizeMachineIR() {
511   addPass(new Legalizer());
512   return false;
513 }
514 
515 bool ARMPassConfig::addRegBankSelect() {
516   addPass(new RegBankSelect());
517   return false;
518 }
519 
520 bool ARMPassConfig::addGlobalInstructionSelect() {
521   addPass(new InstructionSelect(getOptLevel()));
522   return false;
523 }
524 
525 void ARMPassConfig::addPreRegAlloc() {
526   if (getOptLevel() != CodeGenOpt::None) {
527     if (getOptLevel() == CodeGenOpt::Aggressive)
528       addPass(&MachinePipelinerID);
529 
530     addPass(createMVETPAndVPTOptimisationsPass());
531 
532     addPass(createMLxExpansionPass());
533 
534     if (EnableARMLoadStoreOpt)
535       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
536 
537     if (!DisableA15SDOptimization)
538       addPass(createA15SDOptimizerPass());
539   }
540 }
541 
542 void ARMPassConfig::addPreSched2() {
543   if (getOptLevel() != CodeGenOpt::None) {
544     if (EnableARMLoadStoreOpt)
545       addPass(createARMLoadStoreOptimizationPass());
546 
547     addPass(new ARMExecutionDomainFix());
548     addPass(createBreakFalseDeps());
549   }
550 
551   // Expand some pseudo instructions into multiple instructions to allow
552   // proper scheduling.
553   addPass(createARMExpandPseudoPass());
554 
555   if (getOptLevel() != CodeGenOpt::None) {
556     // When optimising for size, always run the Thumb2SizeReduction pass before
557     // IfConversion. Otherwise, check whether IT blocks are restricted
558     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
559     addPass(createThumb2SizeReductionPass([this](const Function &F) {
560       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
561              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
562     }));
563 
564     addPass(createIfConverter([](const MachineFunction &MF) {
565       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
566     }));
567   }
568   addPass(createThumb2ITBlockPass());
569 
570   // Add both scheduling passes to give the subtarget an opportunity to pick
571   // between them.
572   if (getOptLevel() != CodeGenOpt::None) {
573     addPass(&PostMachineSchedulerID);
574     addPass(&PostRASchedulerID);
575   }
576 
577   addPass(createMVEVPTBlockPass());
578   addPass(createARMIndirectThunks());
579   addPass(createARMSLSHardeningPass());
580 }
581 
582 void ARMPassConfig::addPreEmitPass() {
583   addPass(createThumb2SizeReductionPass());
584 
585   // Constant island pass work on unbundled instructions.
586   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
587     return MF.getSubtarget<ARMSubtarget>().isThumb2();
588   }));
589 
590   // Don't optimize barriers or block placement at -O0.
591   if (getOptLevel() != CodeGenOpt::None) {
592     addPass(createARMBlockPlacementPass());
593     addPass(createARMOptimizeBarriersPass());
594   }
595 }
596 
597 void ARMPassConfig::addPreEmitPass2() {
598   // Inserts fixup instructions before unsafe AES operations. Instructions may
599   // be inserted at the start of blocks and at within blocks so this pass has to
600   // come before those below.
601   addPass(createARMFixCortexA57AES1742098Pass());
602   // Inserts BTIs at the start of functions and indirectly-called basic blocks,
603   // so passes cannot add to the start of basic blocks once this has run.
604   addPass(createARMBranchTargetsPass());
605   // Inserts Constant Islands. Block sizes cannot be increased after this point,
606   // as this may push the branch ranges and load offsets of accessing constant
607   // pools out of range..
608   addPass(createARMConstantIslandPass());
609   // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
610   // instructions, but the pseudos all have conservative sizes so that block
611   // sizes will only be decreased by this pass.
612   addPass(createARMLowOverheadLoopsPass());
613 
614   if (TM->getTargetTriple().isOSWindows()) {
615     // Identify valid longjmp targets for Windows Control Flow Guard.
616     addPass(createCFGuardLongjmpPass());
617     // Identify valid eh continuation targets for Windows EHCont Guard.
618     addPass(createEHContGuardCatchretPass());
619   }
620 }
621