1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "ARMTargetMachine.h" 13 #include "ARM.h" 14 #include "ARMMacroFusion.h" 15 #include "ARMSubtarget.h" 16 #include "ARMTargetObjectFile.h" 17 #include "ARMTargetTransformInfo.h" 18 #include "MCTargetDesc/ARMMCTargetDesc.h" 19 #include "TargetInfo/ARMTargetInfo.h" 20 #include "llvm/ADT/Optional.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/StringRef.h" 23 #include "llvm/ADT/Triple.h" 24 #include "llvm/Analysis/TargetTransformInfo.h" 25 #include "llvm/CodeGen/ExecutionDomainFix.h" 26 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 30 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 34 #include "llvm/CodeGen/MachineFunction.h" 35 #include "llvm/CodeGen/MachineScheduler.h" 36 #include "llvm/CodeGen/Passes.h" 37 #include "llvm/CodeGen/TargetPassConfig.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/DataLayout.h" 40 #include "llvm/IR/Function.h" 41 #include "llvm/Pass.h" 42 #include "llvm/Support/CodeGen.h" 43 #include "llvm/Support/CommandLine.h" 44 #include "llvm/Support/ErrorHandling.h" 45 #include "llvm/Support/TargetParser.h" 46 #include "llvm/Support/TargetRegistry.h" 47 #include "llvm/Target/TargetLoweringObjectFile.h" 48 #include "llvm/Target/TargetOptions.h" 49 #include "llvm/Transforms/Scalar.h" 50 #include <cassert> 51 #include <memory> 52 #include <string> 53 54 using namespace llvm; 55 56 static cl::opt<bool> 57 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, 58 cl::desc("Inhibit optimization of S->D register accesses on A15"), 59 cl::init(false)); 60 61 static cl::opt<bool> 62 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, 63 cl::desc("Run SimplifyCFG after expanding atomic operations" 64 " to make use of cmpxchg flow-based information"), 65 cl::init(true)); 66 67 static cl::opt<bool> 68 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, 69 cl::desc("Enable ARM load/store optimization pass"), 70 cl::init(true)); 71 72 // FIXME: Unify control over GlobalMerge. 73 static cl::opt<cl::boolOrDefault> 74 EnableGlobalMerge("arm-global-merge", cl::Hidden, 75 cl::desc("Enable the global merge pass")); 76 77 namespace llvm { 78 void initializeARMExecutionDomainFixPass(PassRegistry&); 79 } 80 81 extern "C" void LLVMInitializeARMTarget() { 82 // Register the target. 83 RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget()); 84 RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget()); 85 RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget()); 86 RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget()); 87 88 PassRegistry &Registry = *PassRegistry::getPassRegistry(); 89 initializeGlobalISel(Registry); 90 initializeARMLoadStoreOptPass(Registry); 91 initializeARMPreAllocLoadStoreOptPass(Registry); 92 initializeARMParallelDSPPass(Registry); 93 initializeARMCodeGenPreparePass(Registry); 94 initializeARMConstantIslandsPass(Registry); 95 initializeARMExecutionDomainFixPass(Registry); 96 initializeARMExpandPseudoPass(Registry); 97 initializeThumb2SizeReducePass(Registry); 98 initializeMVEVPTBlockPass(Registry); 99 initializeMVETailPredicationPass(Registry); 100 initializeARMLowOverheadLoopsPass(Registry); 101 } 102 103 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 104 if (TT.isOSBinFormatMachO()) 105 return std::make_unique<TargetLoweringObjectFileMachO>(); 106 if (TT.isOSWindows()) 107 return std::make_unique<TargetLoweringObjectFileCOFF>(); 108 return std::make_unique<ARMElfTargetObjectFile>(); 109 } 110 111 static ARMBaseTargetMachine::ARMABI 112 computeTargetABI(const Triple &TT, StringRef CPU, 113 const TargetOptions &Options) { 114 StringRef ABIName = Options.MCOptions.getABIName(); 115 116 if (ABIName.empty()) 117 ABIName = ARM::computeDefaultTargetABI(TT, CPU); 118 119 if (ABIName == "aapcs16") 120 return ARMBaseTargetMachine::ARM_ABI_AAPCS16; 121 else if (ABIName.startswith("aapcs")) 122 return ARMBaseTargetMachine::ARM_ABI_AAPCS; 123 else if (ABIName.startswith("apcs")) 124 return ARMBaseTargetMachine::ARM_ABI_APCS; 125 126 llvm_unreachable("Unhandled/unknown ABI Name!"); 127 return ARMBaseTargetMachine::ARM_ABI_UNKNOWN; 128 } 129 130 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 131 const TargetOptions &Options, 132 bool isLittle) { 133 auto ABI = computeTargetABI(TT, CPU, Options); 134 std::string Ret; 135 136 if (isLittle) 137 // Little endian. 138 Ret += "e"; 139 else 140 // Big endian. 141 Ret += "E"; 142 143 Ret += DataLayout::getManglingComponent(TT); 144 145 // Pointers are 32 bits and aligned to 32 bits. 146 Ret += "-p:32:32"; 147 148 // Function pointers are aligned to 8 bits (because the LSB stores the 149 // ARM/Thumb state). 150 Ret += "-Fi8"; 151 152 // ABIs other than APCS have 64 bit integers with natural alignment. 153 if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS) 154 Ret += "-i64:64"; 155 156 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32 157 // bits, others to 64 bits. We always try to align to 64 bits. 158 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS) 159 Ret += "-f64:32:64"; 160 161 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others 162 // to 64. We always ty to give them natural alignment. 163 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS) 164 Ret += "-v64:32:64-v128:32:128"; 165 else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16) 166 Ret += "-v128:64:128"; 167 168 // Try to align aggregates to 32 bits (the default is 64 bits, which has no 169 // particular hardware support on 32-bit ARM). 170 Ret += "-a:0:32"; 171 172 // Integer registers are 32 bits. 173 Ret += "-n32"; 174 175 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit 176 // aligned everywhere else. 177 if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16) 178 Ret += "-S128"; 179 else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS) 180 Ret += "-S64"; 181 else 182 Ret += "-S32"; 183 184 return Ret; 185 } 186 187 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 188 Optional<Reloc::Model> RM) { 189 if (!RM.hasValue()) 190 // Default relocation model on Darwin is PIC. 191 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static; 192 193 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI) 194 assert(TT.isOSBinFormatELF() && 195 "ROPI/RWPI currently only supported for ELF"); 196 197 // DynamicNoPIC is only used on darwin. 198 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin()) 199 return Reloc::Static; 200 201 return *RM; 202 } 203 204 /// Create an ARM architecture model. 205 /// 206 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, 207 StringRef CPU, StringRef FS, 208 const TargetOptions &Options, 209 Optional<Reloc::Model> RM, 210 Optional<CodeModel::Model> CM, 211 CodeGenOpt::Level OL, bool isLittle) 212 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 213 CPU, FS, Options, getEffectiveRelocModel(TT, RM), 214 getEffectiveCodeModel(CM, CodeModel::Small), OL), 215 TargetABI(computeTargetABI(TT, CPU, Options)), 216 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) { 217 218 // Default to triple-appropriate float ABI 219 if (Options.FloatABIType == FloatABI::Default) { 220 if (isTargetHardFloat()) 221 this->Options.FloatABIType = FloatABI::Hard; 222 else 223 this->Options.FloatABIType = FloatABI::Soft; 224 } 225 226 // Default to triple-appropriate EABI 227 if (Options.EABIVersion == EABI::Default || 228 Options.EABIVersion == EABI::Unknown) { 229 // musl is compatible with glibc with regard to EABI version 230 if ((TargetTriple.getEnvironment() == Triple::GNUEABI || 231 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 232 TargetTriple.getEnvironment() == Triple::MuslEABI || 233 TargetTriple.getEnvironment() == Triple::MuslEABIHF) && 234 !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin())) 235 this->Options.EABIVersion = EABI::GNU; 236 else 237 this->Options.EABIVersion = EABI::EABI5; 238 } 239 240 if (TT.isOSBinFormatMachO()) { 241 this->Options.TrapUnreachable = true; 242 this->Options.NoTrapAfterNoreturn = true; 243 } 244 245 initAsmInfo(); 246 } 247 248 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default; 249 250 const ARMSubtarget * 251 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const { 252 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 253 Attribute FSAttr = F.getFnAttribute("target-features"); 254 255 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 256 ? CPUAttr.getValueAsString().str() 257 : TargetCPU; 258 std::string FS = !FSAttr.hasAttribute(Attribute::None) 259 ? FSAttr.getValueAsString().str() 260 : TargetFS; 261 262 // FIXME: This is related to the code below to reset the target options, 263 // we need to know whether or not the soft float flag is set on the 264 // function before we can generate a subtarget. We also need to use 265 // it as a key for the subtarget since that can be the only difference 266 // between two functions. 267 bool SoftFloat = 268 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 269 // If the soft float attribute is set on the function turn on the soft float 270 // subtarget feature. 271 if (SoftFloat) 272 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 273 274 // Use the optminsize to identify the subtarget, but don't use it in the 275 // feature string. 276 std::string Key = CPU + FS; 277 if (F.hasMinSize()) 278 Key += "+minsize"; 279 280 auto &I = SubtargetMap[Key]; 281 if (!I) { 282 // This needs to be done before we create a new subtarget since any 283 // creation will depend on the TM and the code generation flags on the 284 // function that reside in TargetOptions. 285 resetTargetOptions(F); 286 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle, 287 F.hasMinSize()); 288 289 if (!I->isThumb() && !I->hasARMOps()) 290 F.getContext().emitError("Function '" + F.getName() + "' uses ARM " 291 "instructions, but the target does not support ARM mode execution."); 292 } 293 294 return I.get(); 295 } 296 297 TargetTransformInfo 298 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) { 299 return TargetTransformInfo(ARMTTIImpl(this, F)); 300 } 301 302 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT, 303 StringRef CPU, StringRef FS, 304 const TargetOptions &Options, 305 Optional<Reloc::Model> RM, 306 Optional<CodeModel::Model> CM, 307 CodeGenOpt::Level OL, bool JIT) 308 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 309 310 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT, 311 StringRef CPU, StringRef FS, 312 const TargetOptions &Options, 313 Optional<Reloc::Model> RM, 314 Optional<CodeModel::Model> CM, 315 CodeGenOpt::Level OL, bool JIT) 316 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 317 318 namespace { 319 320 /// ARM Code Generator Pass Configuration Options. 321 class ARMPassConfig : public TargetPassConfig { 322 public: 323 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM) 324 : TargetPassConfig(TM, PM) { 325 if (TM.getOptLevel() != CodeGenOpt::None) { 326 ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(), 327 TM.getTargetFeatureString()); 328 if (STI.hasFeature(ARM::FeatureUseMISched)) 329 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); 330 } 331 } 332 333 ARMBaseTargetMachine &getARMTargetMachine() const { 334 return getTM<ARMBaseTargetMachine>(); 335 } 336 337 ScheduleDAGInstrs * 338 createMachineScheduler(MachineSchedContext *C) const override { 339 ScheduleDAGMILive *DAG = createGenericSchedLive(C); 340 // add DAG Mutations here. 341 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); 342 if (ST.hasFusion()) 343 DAG->addMutation(createARMMacroFusionDAGMutation()); 344 return DAG; 345 } 346 347 ScheduleDAGInstrs * 348 createPostMachineScheduler(MachineSchedContext *C) const override { 349 ScheduleDAGMI *DAG = createGenericSchedPostRA(C); 350 // add DAG Mutations here. 351 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); 352 if (ST.hasFusion()) 353 DAG->addMutation(createARMMacroFusionDAGMutation()); 354 return DAG; 355 } 356 357 void addIRPasses() override; 358 void addCodeGenPrepare() override; 359 bool addPreISel() override; 360 bool addInstSelector() override; 361 bool addIRTranslator() override; 362 bool addLegalizeMachineIR() override; 363 bool addRegBankSelect() override; 364 bool addGlobalInstructionSelect() override; 365 void addPreRegAlloc() override; 366 void addPreSched2() override; 367 void addPreEmitPass() override; 368 369 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 370 }; 371 372 class ARMExecutionDomainFix : public ExecutionDomainFix { 373 public: 374 static char ID; 375 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {} 376 StringRef getPassName() const override { 377 return "ARM Execution Domain Fix"; 378 } 379 }; 380 char ARMExecutionDomainFix::ID; 381 382 } // end anonymous namespace 383 384 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", 385 "ARM Execution Domain Fix", false, false) 386 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis) 387 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix", 388 "ARM Execution Domain Fix", false, false) 389 390 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) { 391 return new ARMPassConfig(*this, PM); 392 } 393 394 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const { 395 return getStandardCSEConfigForOpt(TM->getOptLevel()); 396 } 397 398 void ARMPassConfig::addIRPasses() { 399 if (TM->Options.ThreadModel == ThreadModel::Single) 400 addPass(createLowerAtomicPass()); 401 else 402 addPass(createAtomicExpandPass()); 403 404 // Cmpxchg instructions are often used with a subsequent comparison to 405 // determine whether it succeeded. We can exploit existing control-flow in 406 // ldrex/strex loops to simplify this, but it needs tidying up. 407 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) 408 addPass(createCFGSimplificationPass( 409 1, false, false, true, true, [this](const Function &F) { 410 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F); 411 return ST.hasAnyDataBarrier() && !ST.isThumb1Only(); 412 })); 413 414 TargetPassConfig::addIRPasses(); 415 416 // Run the parallel DSP pass. 417 if (getOptLevel() == CodeGenOpt::Aggressive) 418 addPass(createARMParallelDSPPass()); 419 420 // Match interleaved memory accesses to ldN/stN intrinsics. 421 if (TM->getOptLevel() != CodeGenOpt::None) 422 addPass(createInterleavedAccessPass()); 423 } 424 425 void ARMPassConfig::addCodeGenPrepare() { 426 if (getOptLevel() != CodeGenOpt::None) 427 addPass(createARMCodeGenPreparePass()); 428 TargetPassConfig::addCodeGenPrepare(); 429 } 430 431 bool ARMPassConfig::addPreISel() { 432 if ((TM->getOptLevel() != CodeGenOpt::None && 433 EnableGlobalMerge == cl::BOU_UNSET) || 434 EnableGlobalMerge == cl::BOU_TRUE) { 435 // FIXME: This is using the thumb1 only constant value for 436 // maximal global offset for merging globals. We may want 437 // to look into using the old value for non-thumb1 code of 438 // 4095 based on the TargetMachine, but this starts to become 439 // tricky when doing code gen per function. 440 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && 441 (EnableGlobalMerge == cl::BOU_UNSET); 442 // Merging of extern globals is enabled by default on non-Mach-O as we 443 // expect it to be generally either beneficial or harmless. On Mach-O it 444 // is disabled as we emit the .subsections_via_symbols directive which 445 // means that merging extern globals is not safe. 446 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO(); 447 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize, 448 MergeExternalByDefault)); 449 } 450 451 if (TM->getOptLevel() != CodeGenOpt::None) { 452 addPass(createHardwareLoopsPass()); 453 addPass(createMVETailPredicationPass()); 454 } 455 456 return false; 457 } 458 459 bool ARMPassConfig::addInstSelector() { 460 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel())); 461 return false; 462 } 463 464 bool ARMPassConfig::addIRTranslator() { 465 addPass(new IRTranslator()); 466 return false; 467 } 468 469 bool ARMPassConfig::addLegalizeMachineIR() { 470 addPass(new Legalizer()); 471 return false; 472 } 473 474 bool ARMPassConfig::addRegBankSelect() { 475 addPass(new RegBankSelect()); 476 return false; 477 } 478 479 bool ARMPassConfig::addGlobalInstructionSelect() { 480 addPass(new InstructionSelect()); 481 return false; 482 } 483 484 void ARMPassConfig::addPreRegAlloc() { 485 if (getOptLevel() != CodeGenOpt::None) { 486 addPass(createMLxExpansionPass()); 487 488 if (EnableARMLoadStoreOpt) 489 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true)); 490 491 if (!DisableA15SDOptimization) 492 addPass(createA15SDOptimizerPass()); 493 } 494 } 495 496 void ARMPassConfig::addPreSched2() { 497 if (getOptLevel() != CodeGenOpt::None) { 498 if (EnableARMLoadStoreOpt) 499 addPass(createARMLoadStoreOptimizationPass()); 500 501 addPass(new ARMExecutionDomainFix()); 502 addPass(createBreakFalseDeps()); 503 } 504 505 // Expand some pseudo instructions into multiple instructions to allow 506 // proper scheduling. 507 addPass(createARMExpandPseudoPass()); 508 509 if (getOptLevel() != CodeGenOpt::None) { 510 // in v8, IfConversion depends on Thumb instruction widths 511 addPass(createThumb2SizeReductionPass([this](const Function &F) { 512 return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT(); 513 })); 514 515 addPass(createIfConverter([](const MachineFunction &MF) { 516 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only(); 517 })); 518 } 519 addPass(createMVEVPTBlockPass()); 520 addPass(createThumb2ITBlockPass()); 521 } 522 523 void ARMPassConfig::addPreEmitPass() { 524 addPass(createThumb2SizeReductionPass()); 525 526 // Constant island pass work on unbundled instructions. 527 addPass(createUnpackMachineBundles([](const MachineFunction &MF) { 528 return MF.getSubtarget<ARMSubtarget>().isThumb2(); 529 })); 530 531 // Don't optimize barriers at -O0. 532 if (getOptLevel() != CodeGenOpt::None) 533 addPass(createARMOptimizeBarriersPass()); 534 535 addPass(createARMConstantIslandPass()); 536 addPass(createARMLowOverheadLoopsPass()); 537 } 538