xref: /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ARMTargetMachine.cpp (revision 1165fc9a526630487a1feb63daef65c5aee1a583) 
1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "MCTargetDesc/ARMMCTargetDesc.h"
19 #include "TargetInfo/ARMTargetInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/Analysis/TargetTransformInfo.h"
25 #include "llvm/CodeGen/ExecutionDomainFix.h"
26 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
27 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
28 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
29 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
30 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
31 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
32 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
33 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/TargetRegistry.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/ARMTargetParser.h"
47 #include "llvm/Support/TargetParser.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include "llvm/Transforms/CFGuard.h"
51 #include "llvm/Transforms/IPO.h"
52 #include "llvm/Transforms/Scalar.h"
53 #include <cassert>
54 #include <memory>
55 #include <string>
56 
57 using namespace llvm;
58 
59 static cl::opt<bool>
60 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
61                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
62                    cl::init(false));
63 
64 static cl::opt<bool>
65 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
66                  cl::desc("Run SimplifyCFG after expanding atomic operations"
67                           " to make use of cmpxchg flow-based information"),
68                  cl::init(true));
69 
70 static cl::opt<bool>
71 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
72                       cl::desc("Enable ARM load/store optimization pass"),
73                       cl::init(true));
74 
75 // FIXME: Unify control over GlobalMerge.
76 static cl::opt<cl::boolOrDefault>
77 EnableGlobalMerge("arm-global-merge", cl::Hidden,
78                   cl::desc("Enable the global merge pass"));
79 
80 namespace llvm {
81   void initializeARMExecutionDomainFixPass(PassRegistry&);
82 }
83 
84 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
85   // Register the target.
86   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
87   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
88   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
89   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
90 
91   PassRegistry &Registry = *PassRegistry::getPassRegistry();
92   initializeGlobalISel(Registry);
93   initializeARMLoadStoreOptPass(Registry);
94   initializeARMPreAllocLoadStoreOptPass(Registry);
95   initializeARMParallelDSPPass(Registry);
96   initializeARMBranchTargetsPass(Registry);
97   initializeARMConstantIslandsPass(Registry);
98   initializeARMExecutionDomainFixPass(Registry);
99   initializeARMExpandPseudoPass(Registry);
100   initializeThumb2SizeReducePass(Registry);
101   initializeMVEVPTBlockPass(Registry);
102   initializeMVETPAndVPTOptimisationsPass(Registry);
103   initializeMVETailPredicationPass(Registry);
104   initializeARMLowOverheadLoopsPass(Registry);
105   initializeARMBlockPlacementPass(Registry);
106   initializeMVEGatherScatterLoweringPass(Registry);
107   initializeARMSLSHardeningPass(Registry);
108   initializeMVELaneInterleavingPass(Registry);
109 }
110 
111 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
112   if (TT.isOSBinFormatMachO())
113     return std::make_unique<TargetLoweringObjectFileMachO>();
114   if (TT.isOSWindows())
115     return std::make_unique<TargetLoweringObjectFileCOFF>();
116   return std::make_unique<ARMElfTargetObjectFile>();
117 }
118 
119 static ARMBaseTargetMachine::ARMABI
120 computeTargetABI(const Triple &TT, StringRef CPU,
121                  const TargetOptions &Options) {
122   StringRef ABIName = Options.MCOptions.getABIName();
123 
124   if (ABIName.empty())
125     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
126 
127   if (ABIName == "aapcs16")
128     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
129   else if (ABIName.startswith("aapcs"))
130     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
131   else if (ABIName.startswith("apcs"))
132     return ARMBaseTargetMachine::ARM_ABI_APCS;
133 
134   llvm_unreachable("Unhandled/unknown ABI Name!");
135   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
136 }
137 
138 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
139                                      const TargetOptions &Options,
140                                      bool isLittle) {
141   auto ABI = computeTargetABI(TT, CPU, Options);
142   std::string Ret;
143 
144   if (isLittle)
145     // Little endian.
146     Ret += "e";
147   else
148     // Big endian.
149     Ret += "E";
150 
151   Ret += DataLayout::getManglingComponent(TT);
152 
153   // Pointers are 32 bits and aligned to 32 bits.
154   Ret += "-p:32:32";
155 
156   // Function pointers are aligned to 8 bits (because the LSB stores the
157   // ARM/Thumb state).
158   Ret += "-Fi8";
159 
160   // ABIs other than APCS have 64 bit integers with natural alignment.
161   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
162     Ret += "-i64:64";
163 
164   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
165   // bits, others to 64 bits. We always try to align to 64 bits.
166   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
167     Ret += "-f64:32:64";
168 
169   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
170   // to 64. We always ty to give them natural alignment.
171   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
172     Ret += "-v64:32:64-v128:32:128";
173   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
174     Ret += "-v128:64:128";
175 
176   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
177   // particular hardware support on 32-bit ARM).
178   Ret += "-a:0:32";
179 
180   // Integer registers are 32 bits.
181   Ret += "-n32";
182 
183   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
184   // aligned everywhere else.
185   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
186     Ret += "-S128";
187   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
188     Ret += "-S64";
189   else
190     Ret += "-S32";
191 
192   return Ret;
193 }
194 
195 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
196                                            Optional<Reloc::Model> RM) {
197   if (!RM.hasValue())
198     // Default relocation model on Darwin is PIC.
199     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
200 
201   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
202     assert(TT.isOSBinFormatELF() &&
203            "ROPI/RWPI currently only supported for ELF");
204 
205   // DynamicNoPIC is only used on darwin.
206   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
207     return Reloc::Static;
208 
209   return *RM;
210 }
211 
212 /// Create an ARM architecture model.
213 ///
214 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
215                                            StringRef CPU, StringRef FS,
216                                            const TargetOptions &Options,
217                                            Optional<Reloc::Model> RM,
218                                            Optional<CodeModel::Model> CM,
219                                            CodeGenOpt::Level OL, bool isLittle)
220     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
221                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
222                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
223       TargetABI(computeTargetABI(TT, CPU, Options)),
224       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
225 
226   // Default to triple-appropriate float ABI
227   if (Options.FloatABIType == FloatABI::Default) {
228     if (isTargetHardFloat())
229       this->Options.FloatABIType = FloatABI::Hard;
230     else
231       this->Options.FloatABIType = FloatABI::Soft;
232   }
233 
234   // Default to triple-appropriate EABI
235   if (Options.EABIVersion == EABI::Default ||
236       Options.EABIVersion == EABI::Unknown) {
237     // musl is compatible with glibc with regard to EABI version
238     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
239          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
240          TargetTriple.getEnvironment() == Triple::MuslEABI ||
241          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
242         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
243       this->Options.EABIVersion = EABI::GNU;
244     else
245       this->Options.EABIVersion = EABI::EABI5;
246   }
247 
248   if (TT.isOSBinFormatMachO()) {
249     this->Options.TrapUnreachable = true;
250     this->Options.NoTrapAfterNoreturn = true;
251   }
252 
253   // ARM supports the debug entry values.
254   setSupportsDebugEntryValues(true);
255 
256   initAsmInfo();
257 
258   // ARM supports the MachineOutliner.
259   setMachineOutliner(true);
260   setSupportsDefaultOutlining(true);
261 }
262 
263 ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
264 
265 const ARMSubtarget *
266 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
267   Attribute CPUAttr = F.getFnAttribute("target-cpu");
268   Attribute FSAttr = F.getFnAttribute("target-features");
269 
270   std::string CPU =
271       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
272   std::string FS =
273       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
274 
275   // FIXME: This is related to the code below to reset the target options,
276   // we need to know whether or not the soft float flag is set on the
277   // function before we can generate a subtarget. We also need to use
278   // it as a key for the subtarget since that can be the only difference
279   // between two functions.
280   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
281   // If the soft float attribute is set on the function turn on the soft float
282   // subtarget feature.
283   if (SoftFloat)
284     FS += FS.empty() ? "+soft-float" : ",+soft-float";
285 
286   // Use the optminsize to identify the subtarget, but don't use it in the
287   // feature string.
288   std::string Key = CPU + FS;
289   if (F.hasMinSize())
290     Key += "+minsize";
291 
292   auto &I = SubtargetMap[Key];
293   if (!I) {
294     // This needs to be done before we create a new subtarget since any
295     // creation will depend on the TM and the code generation flags on the
296     // function that reside in TargetOptions.
297     resetTargetOptions(F);
298     I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
299                                         F.hasMinSize());
300 
301     if (!I->isThumb() && !I->hasARMOps())
302       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
303           "instructions, but the target does not support ARM mode execution.");
304   }
305 
306   return I.get();
307 }
308 
309 TargetTransformInfo
310 ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
311   return TargetTransformInfo(ARMTTIImpl(this, F));
312 }
313 
314 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
315                                        StringRef CPU, StringRef FS,
316                                        const TargetOptions &Options,
317                                        Optional<Reloc::Model> RM,
318                                        Optional<CodeModel::Model> CM,
319                                        CodeGenOpt::Level OL, bool JIT)
320     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
321 
322 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
323                                        StringRef CPU, StringRef FS,
324                                        const TargetOptions &Options,
325                                        Optional<Reloc::Model> RM,
326                                        Optional<CodeModel::Model> CM,
327                                        CodeGenOpt::Level OL, bool JIT)
328     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
329 
330 namespace {
331 
332 /// ARM Code Generator Pass Configuration Options.
333 class ARMPassConfig : public TargetPassConfig {
334 public:
335   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
336       : TargetPassConfig(TM, PM) {}
337 
338   ARMBaseTargetMachine &getARMTargetMachine() const {
339     return getTM<ARMBaseTargetMachine>();
340   }
341 
342   ScheduleDAGInstrs *
343   createMachineScheduler(MachineSchedContext *C) const override {
344     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
345     // add DAG Mutations here.
346     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
347     if (ST.hasFusion())
348       DAG->addMutation(createARMMacroFusionDAGMutation());
349     return DAG;
350   }
351 
352   ScheduleDAGInstrs *
353   createPostMachineScheduler(MachineSchedContext *C) const override {
354     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
355     // add DAG Mutations here.
356     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
357     if (ST.hasFusion())
358       DAG->addMutation(createARMMacroFusionDAGMutation());
359     return DAG;
360   }
361 
362   void addIRPasses() override;
363   void addCodeGenPrepare() override;
364   bool addPreISel() override;
365   bool addInstSelector() override;
366   bool addIRTranslator() override;
367   bool addLegalizeMachineIR() override;
368   bool addRegBankSelect() override;
369   bool addGlobalInstructionSelect() override;
370   void addPreRegAlloc() override;
371   void addPreSched2() override;
372   void addPreEmitPass() override;
373   void addPreEmitPass2() override;
374 
375   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
376 };
377 
378 class ARMExecutionDomainFix : public ExecutionDomainFix {
379 public:
380   static char ID;
381   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
382   StringRef getPassName() const override {
383     return "ARM Execution Domain Fix";
384   }
385 };
386 char ARMExecutionDomainFix::ID;
387 
388 } // end anonymous namespace
389 
390 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
391   "ARM Execution Domain Fix", false, false)
392 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
393 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
394   "ARM Execution Domain Fix", false, false)
395 
396 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
397   return new ARMPassConfig(*this, PM);
398 }
399 
400 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
401   return getStandardCSEConfigForOpt(TM->getOptLevel());
402 }
403 
404 void ARMPassConfig::addIRPasses() {
405   if (TM->Options.ThreadModel == ThreadModel::Single)
406     addPass(createLowerAtomicPass());
407   else
408     addPass(createAtomicExpandPass());
409 
410   // Cmpxchg instructions are often used with a subsequent comparison to
411   // determine whether it succeeded. We can exploit existing control-flow in
412   // ldrex/strex loops to simplify this, but it needs tidying up.
413   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
414     addPass(createCFGSimplificationPass(
415         SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
416         [this](const Function &F) {
417           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
418           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
419         }));
420 
421   addPass(createMVEGatherScatterLoweringPass());
422   addPass(createMVELaneInterleavingPass());
423 
424   TargetPassConfig::addIRPasses();
425 
426   // Run the parallel DSP pass.
427   if (getOptLevel() == CodeGenOpt::Aggressive)
428     addPass(createARMParallelDSPPass());
429 
430   // Match interleaved memory accesses to ldN/stN intrinsics.
431   if (TM->getOptLevel() != CodeGenOpt::None)
432     addPass(createInterleavedAccessPass());
433 
434   // Add Control Flow Guard checks.
435   if (TM->getTargetTriple().isOSWindows())
436     addPass(createCFGuardCheckPass());
437 }
438 
439 void ARMPassConfig::addCodeGenPrepare() {
440   if (getOptLevel() != CodeGenOpt::None)
441     addPass(createTypePromotionPass());
442   TargetPassConfig::addCodeGenPrepare();
443 }
444 
445 bool ARMPassConfig::addPreISel() {
446   if ((TM->getOptLevel() != CodeGenOpt::None &&
447        EnableGlobalMerge == cl::BOU_UNSET) ||
448       EnableGlobalMerge == cl::BOU_TRUE) {
449     // FIXME: This is using the thumb1 only constant value for
450     // maximal global offset for merging globals. We may want
451     // to look into using the old value for non-thumb1 code of
452     // 4095 based on the TargetMachine, but this starts to become
453     // tricky when doing code gen per function.
454     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
455                                (EnableGlobalMerge == cl::BOU_UNSET);
456     // Merging of extern globals is enabled by default on non-Mach-O as we
457     // expect it to be generally either beneficial or harmless. On Mach-O it
458     // is disabled as we emit the .subsections_via_symbols directive which
459     // means that merging extern globals is not safe.
460     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
461     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
462                                   MergeExternalByDefault));
463   }
464 
465   if (TM->getOptLevel() != CodeGenOpt::None) {
466     addPass(createHardwareLoopsPass());
467     addPass(createMVETailPredicationPass());
468     // FIXME: IR passes can delete address-taken basic blocks, deleting
469     // corresponding blockaddresses. ARMConstantPoolConstant holds references to
470     // address-taken basic blocks which can be invalidated if the function
471     // containing the blockaddress has already been codegen'd and the basic
472     // block is removed. Work around this by forcing all IR passes to run before
473     // any ISel takes place. We should have a more principled way of handling
474     // this. See D99707 for more details.
475     addPass(createBarrierNoopPass());
476   }
477 
478   return false;
479 }
480 
481 bool ARMPassConfig::addInstSelector() {
482   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
483   return false;
484 }
485 
486 bool ARMPassConfig::addIRTranslator() {
487   addPass(new IRTranslator(getOptLevel()));
488   return false;
489 }
490 
491 bool ARMPassConfig::addLegalizeMachineIR() {
492   addPass(new Legalizer());
493   return false;
494 }
495 
496 bool ARMPassConfig::addRegBankSelect() {
497   addPass(new RegBankSelect());
498   return false;
499 }
500 
501 bool ARMPassConfig::addGlobalInstructionSelect() {
502   addPass(new InstructionSelect(getOptLevel()));
503   return false;
504 }
505 
506 void ARMPassConfig::addPreRegAlloc() {
507   if (getOptLevel() != CodeGenOpt::None) {
508     addPass(createMVETPAndVPTOptimisationsPass());
509 
510     addPass(createMLxExpansionPass());
511 
512     if (EnableARMLoadStoreOpt)
513       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
514 
515     if (!DisableA15SDOptimization)
516       addPass(createA15SDOptimizerPass());
517   }
518 }
519 
520 void ARMPassConfig::addPreSched2() {
521   if (getOptLevel() != CodeGenOpt::None) {
522     if (EnableARMLoadStoreOpt)
523       addPass(createARMLoadStoreOptimizationPass());
524 
525     addPass(new ARMExecutionDomainFix());
526     addPass(createBreakFalseDeps());
527   }
528 
529   // Expand some pseudo instructions into multiple instructions to allow
530   // proper scheduling.
531   addPass(createARMExpandPseudoPass());
532 
533   if (getOptLevel() != CodeGenOpt::None) {
534     // When optimising for size, always run the Thumb2SizeReduction pass before
535     // IfConversion. Otherwise, check whether IT blocks are restricted
536     // (e.g. in v8, IfConversion depends on Thumb instruction widths)
537     addPass(createThumb2SizeReductionPass([this](const Function &F) {
538       return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
539              this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
540     }));
541 
542     addPass(createIfConverter([](const MachineFunction &MF) {
543       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
544     }));
545   }
546   addPass(createThumb2ITBlockPass());
547 
548   // Add both scheduling passes to give the subtarget an opportunity to pick
549   // between them.
550   if (getOptLevel() != CodeGenOpt::None) {
551     addPass(&PostMachineSchedulerID);
552     addPass(&PostRASchedulerID);
553   }
554 
555   addPass(createMVEVPTBlockPass());
556   addPass(createARMIndirectThunks());
557   addPass(createARMSLSHardeningPass());
558 }
559 
560 void ARMPassConfig::addPreEmitPass() {
561   addPass(createThumb2SizeReductionPass());
562 
563   // Constant island pass work on unbundled instructions.
564   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
565     return MF.getSubtarget<ARMSubtarget>().isThumb2();
566   }));
567 
568   // Don't optimize barriers or block placement at -O0.
569   if (getOptLevel() != CodeGenOpt::None) {
570     addPass(createARMBlockPlacementPass());
571     addPass(createARMOptimizeBarriersPass());
572   }
573 }
574 
575 void ARMPassConfig::addPreEmitPass2() {
576   addPass(createARMBranchTargetsPass());
577   addPass(createARMConstantIslandPass());
578   addPass(createARMLowOverheadLoopsPass());
579 
580   if (TM->getTargetTriple().isOSWindows()) {
581     // Identify valid longjmp targets for Windows Control Flow Guard.
582     addPass(createCFGuardLongjmpPass());
583     // Identify valid eh continuation targets for Windows EHCont Guard.
584     addPass(createEHContGuardCatchretPass());
585   }
586 }
587