1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the ARM specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "ARM.h" 14 15 #include "ARMCallLowering.h" 16 #include "ARMLegalizerInfo.h" 17 #include "ARMRegisterBankInfo.h" 18 #include "ARMSubtarget.h" 19 #include "ARMFrameLowering.h" 20 #include "ARMInstrInfo.h" 21 #include "ARMSubtarget.h" 22 #include "ARMTargetMachine.h" 23 #include "MCTargetDesc/ARMMCTargetDesc.h" 24 #include "Thumb1FrameLowering.h" 25 #include "Thumb1InstrInfo.h" 26 #include "Thumb2InstrInfo.h" 27 #include "llvm/ADT/StringRef.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/ADT/Twine.h" 30 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/GlobalValue.h" 34 #include "llvm/MC/MCAsmInfo.h" 35 #include "llvm/MC/MCTargetOptions.h" 36 #include "llvm/Support/CodeGen.h" 37 #include "llvm/Support/CommandLine.h" 38 #include "llvm/Support/TargetParser.h" 39 #include "llvm/Target/TargetOptions.h" 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "arm-subtarget" 44 45 #define GET_SUBTARGETINFO_TARGET_DESC 46 #define GET_SUBTARGETINFO_CTOR 47 #include "ARMGenSubtargetInfo.inc" 48 49 static cl::opt<bool> 50 UseFusedMulOps("arm-use-mulops", 51 cl::init(true), cl::Hidden); 52 53 enum ITMode { 54 DefaultIT, 55 RestrictedIT, 56 NoRestrictedIT 57 }; 58 59 static cl::opt<ITMode> 60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), 61 cl::ZeroOrMore, 62 cl::values(clEnumValN(DefaultIT, "arm-default-it", 63 "Generate IT block based on arch"), 64 clEnumValN(RestrictedIT, "arm-restrict-it", 65 "Disallow deprecated IT based on ARMv8"), 66 clEnumValN(NoRestrictedIT, "arm-no-restrict-it", 67 "Allow IT blocks based on ARMv7"))); 68 69 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not 70 /// currently supported (for testing only). 71 static cl::opt<bool> 72 ForceFastISel("arm-force-fast-isel", 73 cl::init(false), cl::Hidden); 74 75 static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness", 76 cl::init(false), cl::Hidden); 77 78 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 79 /// so that we can use initializer lists for subtarget initialization. 80 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU, 81 StringRef FS) { 82 initializeEnvironment(); 83 initSubtargetFeatures(CPU, FS); 84 return *this; 85 } 86 87 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU, 88 StringRef FS) { 89 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS); 90 if (STI.isThumb1Only()) 91 return (ARMFrameLowering *)new Thumb1FrameLowering(STI); 92 93 return new ARMFrameLowering(STI); 94 } 95 96 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, 97 const std::string &FS, 98 const ARMBaseTargetMachine &TM, bool IsLittle, 99 bool MinSize) 100 : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), 101 UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize), 102 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM), 103 FrameLowering(initializeFrameLowering(CPU, FS)), 104 // At this point initializeSubtargetDependencies has been called so 105 // we can query directly. 106 InstrInfo(isThumb1Only() 107 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this) 108 : !isThumb() 109 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this) 110 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)), 111 TLInfo(TM, *this) { 112 113 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering())); 114 Legalizer.reset(new ARMLegalizerInfo(*this)); 115 116 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo()); 117 118 // FIXME: At this point, we can't rely on Subtarget having RBI. 119 // It's awkward to mix passing RBI and the Subtarget; should we pass 120 // TII/TRI as well? 121 InstSelector.reset(createARMInstructionSelector( 122 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI)); 123 124 RegBankInfo.reset(RBI); 125 } 126 127 const CallLowering *ARMSubtarget::getCallLowering() const { 128 return CallLoweringInfo.get(); 129 } 130 131 InstructionSelector *ARMSubtarget::getInstructionSelector() const { 132 return InstSelector.get(); 133 } 134 135 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const { 136 return Legalizer.get(); 137 } 138 139 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const { 140 return RegBankInfo.get(); 141 } 142 143 bool ARMSubtarget::isXRaySupported() const { 144 // We don't currently suppport Thumb, but Windows requires Thumb. 145 return hasV6Ops() && hasARMOps() && !isTargetWindows(); 146 } 147 148 void ARMSubtarget::initializeEnvironment() { 149 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this 150 // directly from it, but we can try to make sure they're consistent when both 151 // available. 152 UseSjLjEH = (isTargetDarwin() && !isTargetWatchABI() && 153 Options.ExceptionModel == ExceptionHandling::None) || 154 Options.ExceptionModel == ExceptionHandling::SjLj; 155 assert((!TM.getMCAsmInfo() || 156 (TM.getMCAsmInfo()->getExceptionHandlingType() == 157 ExceptionHandling::SjLj) == UseSjLjEH) && 158 "inconsistent sjlj choice between CodeGen and MC"); 159 } 160 161 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 162 if (CPUString.empty()) { 163 CPUString = "generic"; 164 165 if (isTargetDarwin()) { 166 StringRef ArchName = TargetTriple.getArchName(); 167 ARM::ArchKind AK = ARM::parseArch(ArchName); 168 if (AK == ARM::ArchKind::ARMV7S) 169 // Default to the Swift CPU when targeting armv7s/thumbv7s. 170 CPUString = "swift"; 171 else if (AK == ARM::ArchKind::ARMV7K) 172 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k. 173 // ARMv7k does not use SjLj exception handling. 174 CPUString = "cortex-a7"; 175 } 176 } 177 178 // Insert the architecture feature derived from the target triple into the 179 // feature string. This is important for setting features that are implied 180 // based on the architecture version. 181 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString); 182 if (!FS.empty()) { 183 if (!ArchFS.empty()) 184 ArchFS = (Twine(ArchFS) + "," + FS).str(); 185 else 186 ArchFS = std::string(FS); 187 } 188 ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS); 189 190 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode. 191 // Assert this for now to make the change obvious. 192 assert(hasV6T2Ops() || !hasThumb2()); 193 194 // Execute only support requires movt support 195 if (genExecuteOnly()) { 196 NoMovt = false; 197 assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target"); 198 } 199 200 // Keep a pointer to static instruction cost data for the specified CPU. 201 SchedModel = getSchedModelForCPU(CPUString); 202 203 // Initialize scheduling itinerary for the specified CPU. 204 InstrItins = getInstrItineraryForCPU(CPUString); 205 206 // FIXME: this is invalid for WindowsCE 207 if (isTargetWindows()) 208 NoARM = true; 209 210 if (isAAPCS_ABI()) 211 stackAlignment = Align(8); 212 if (isTargetNaCl() || isAAPCS16_ABI()) 213 stackAlignment = Align(16); 214 215 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo:: 216 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 217 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 218 // support in the assembler and linker to be used. This would need to be 219 // fixed to fully support tail calls in Thumb1. 220 // 221 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M 222 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This 223 // means if we need to reload LR, it takes extra instructions, which outweighs 224 // the value of the tail call; but here we don't know yet whether LR is going 225 // to be used. We take the optimistic approach of generating the tail call and 226 // perhaps taking a hit if we need to restore the LR. 227 228 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 229 // but we need to make sure there are enough registers; the only valid 230 // registers are the 4 used for parameters. We don't currently do this 231 // case. 232 233 SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps(); 234 235 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0)) 236 SupportsTailCall = false; 237 238 switch (IT) { 239 case DefaultIT: 240 RestrictIT = hasV8Ops() && !hasMinSize(); 241 break; 242 case RestrictedIT: 243 RestrictIT = true; 244 break; 245 case NoRestrictedIT: 246 RestrictIT = false; 247 break; 248 } 249 250 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default. 251 const FeatureBitset &Bits = getFeatureBits(); 252 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters 253 (Options.UnsafeFPMath || isTargetDarwin())) 254 UseNEONForSinglePrecisionFP = true; 255 256 if (isRWPI()) 257 ReserveR9 = true; 258 259 // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2 260 if (MVEVectorCostFactor == 0) 261 MVEVectorCostFactor = 2; 262 263 // FIXME: Teach TableGen to deal with these instead of doing it manually here. 264 switch (ARMProcFamily) { 265 case Others: 266 case CortexA5: 267 break; 268 case CortexA7: 269 LdStMultipleTiming = DoubleIssue; 270 break; 271 case CortexA8: 272 LdStMultipleTiming = DoubleIssue; 273 break; 274 case CortexA9: 275 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess; 276 PreISelOperandLatencyAdjustment = 1; 277 break; 278 case CortexA12: 279 break; 280 case CortexA15: 281 MaxInterleaveFactor = 2; 282 PreISelOperandLatencyAdjustment = 1; 283 PartialUpdateClearance = 12; 284 break; 285 case CortexA17: 286 case CortexA32: 287 case CortexA35: 288 case CortexA53: 289 case CortexA55: 290 case CortexA57: 291 case CortexA72: 292 case CortexA73: 293 case CortexA75: 294 case CortexA76: 295 case CortexA77: 296 case CortexA78: 297 case CortexA78C: 298 case CortexA710: 299 case CortexR4: 300 case CortexR4F: 301 case CortexR5: 302 case CortexR7: 303 case CortexM3: 304 case CortexM7: 305 case CortexR52: 306 case CortexX1: 307 break; 308 case Exynos: 309 LdStMultipleTiming = SingleIssuePlusExtras; 310 MaxInterleaveFactor = 4; 311 if (!isThumb()) 312 PrefLoopLogAlignment = 3; 313 break; 314 case Kryo: 315 break; 316 case Krait: 317 PreISelOperandLatencyAdjustment = 1; 318 break; 319 case NeoverseN1: 320 case NeoverseN2: 321 case NeoverseV1: 322 break; 323 case Swift: 324 MaxInterleaveFactor = 2; 325 LdStMultipleTiming = SingleIssuePlusExtras; 326 PreISelOperandLatencyAdjustment = 1; 327 PartialUpdateClearance = 12; 328 break; 329 } 330 } 331 332 bool ARMSubtarget::isTargetHardFloat() const { return TM.isTargetHardFloat(); } 333 334 bool ARMSubtarget::isAPCS_ABI() const { 335 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN); 336 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS; 337 } 338 bool ARMSubtarget::isAAPCS_ABI() const { 339 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN); 340 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS || 341 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; 342 } 343 bool ARMSubtarget::isAAPCS16_ABI() const { 344 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN); 345 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16; 346 } 347 348 bool ARMSubtarget::isROPI() const { 349 return TM.getRelocationModel() == Reloc::ROPI || 350 TM.getRelocationModel() == Reloc::ROPI_RWPI; 351 } 352 bool ARMSubtarget::isRWPI() const { 353 return TM.getRelocationModel() == Reloc::RWPI || 354 TM.getRelocationModel() == Reloc::ROPI_RWPI; 355 } 356 357 bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { 358 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) 359 return true; 360 361 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in 362 // the section that is being relocated. This means we have to use o load even 363 // for GVs that are known to be local to the dso. 364 if (isTargetMachO() && TM.isPositionIndependent() && 365 (GV->isDeclarationForLinker() || GV->hasCommonLinkage())) 366 return true; 367 368 return false; 369 } 370 371 bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const { 372 return isTargetELF() && TM.isPositionIndependent() && 373 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV); 374 } 375 376 unsigned ARMSubtarget::getMispredictionPenalty() const { 377 return SchedModel.MispredictPenalty; 378 } 379 380 bool ARMSubtarget::enableMachineScheduler() const { 381 // The MachineScheduler can increase register usage, so we use more high 382 // registers and end up with more T2 instructions that cannot be converted to 383 // T1 instructions. At least until we do better at converting to thumb1 384 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the 385 // Machine scheduler, relying on the DAG register pressure scheduler instead. 386 if (isMClass() && hasMinSize()) 387 return false; 388 // Enable the MachineScheduler before register allocation for subtargets 389 // with the use-misched feature. 390 return useMachineScheduler(); 391 } 392 393 bool ARMSubtarget::enableSubRegLiveness() const { 394 if (EnableSubRegLiveness.getNumOccurrences()) 395 return EnableSubRegLiveness; 396 // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs 397 // and q subregs for qqqqpr regs. 398 return hasMVEIntegerOps(); 399 } 400 401 // This overrides the PostRAScheduler bit in the SchedModel for any CPU. 402 bool ARMSubtarget::enablePostRAScheduler() const { 403 if (enableMachineScheduler()) 404 return false; 405 if (disablePostRAScheduler()) 406 return false; 407 // Thumb1 cores will generally not benefit from post-ra scheduling 408 return !isThumb1Only(); 409 } 410 411 bool ARMSubtarget::enablePostRAMachineScheduler() const { 412 if (!enableMachineScheduler()) 413 return false; 414 if (disablePostRAScheduler()) 415 return false; 416 return !isThumb1Only(); 417 } 418 419 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); } 420 421 bool ARMSubtarget::useStride4VFPs() const { 422 // For general targets, the prologue can grow when VFPs are allocated with 423 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind 424 // format which it's more important to get right. 425 return isTargetWatchABI() || 426 (useWideStrideVFP() && !OptMinSize); 427 } 428 429 bool ARMSubtarget::useMovt() const { 430 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit 431 // immediates as it is inherently position independent, and may be out of 432 // range otherwise. 433 return !NoMovt && hasV8MBaselineOps() && 434 (isTargetWindows() || !OptMinSize || genExecuteOnly()); 435 } 436 437 bool ARMSubtarget::useFastISel() const { 438 // Enable fast-isel for any target, for testing only. 439 if (ForceFastISel) 440 return true; 441 442 // Limit fast-isel to the targets that are or have been tested. 443 if (!hasV6Ops()) 444 return false; 445 446 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl. 447 return TM.Options.EnableFastISel && 448 ((isTargetMachO() && !isThumb1Only()) || 449 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb())); 450 } 451 452 unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const { 453 // The GPR register class has multiple possible allocation orders, with 454 // tradeoffs preferred by different sub-architectures and optimisation goals. 455 // The allocation orders are: 456 // 0: (the default tablegen order, not used) 457 // 1: r14, r0-r13 458 // 2: r0-r7 459 // 3: r0-r7, r12, lr, r8-r11 460 // Note that the register allocator will change this order so that 461 // callee-saved registers are used later, as they require extra work in the 462 // prologue/epilogue (though we sometimes override that). 463 464 // For thumb1-only targets, only the low registers are allocatable. 465 if (isThumb1Only()) 466 return 2; 467 468 // Allocate low registers first, so we can select more 16-bit instructions. 469 // We also (in ignoreCSRForAllocationOrder) override the default behaviour 470 // with regards to callee-saved registers, because pushing extra registers is 471 // much cheaper (in terms of code size) than using high registers. After 472 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we 473 // can return with the pop, don't need an extra "bx lr") and then the rest of 474 // the high registers. 475 if (isThumb2() && MF.getFunction().hasMinSize()) 476 return 3; 477 478 // Otherwise, allocate in the default order, using LR first because saving it 479 // allows a shorter epilogue sequence. 480 return 1; 481 } 482 483 bool ARMSubtarget::ignoreCSRForAllocationOrder(const MachineFunction &MF, 484 unsigned PhysReg) const { 485 // To minimize code size in Thumb2, we prefer the usage of low regs (lower 486 // cost per use) so we can use narrow encoding. By default, caller-saved 487 // registers (e.g. lr, r12) are always allocated first, regardless of 488 // their cost per use. When optForMinSize, we prefer the low regs even if 489 // they are CSR because usually push/pop can be folded into existing ones. 490 return isThumb2() && MF.getFunction().hasMinSize() && 491 ARM::GPRRegClass.contains(PhysReg); 492 } 493