1*0b57cec5SDimitry Andric //===- ARMMacroFusion.cpp - ARM Macro Fusion ----------------------===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric /// \file This file contains the ARM implementation of the DAG scheduling 10*0b57cec5SDimitry Andric /// mutation to pair instructions back to back. 11*0b57cec5SDimitry Andric // 12*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 13*0b57cec5SDimitry Andric 14*0b57cec5SDimitry Andric #include "ARMMacroFusion.h" 15*0b57cec5SDimitry Andric #include "ARMSubtarget.h" 16*0b57cec5SDimitry Andric #include "llvm/CodeGen/MacroFusion.h" 17*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric namespace llvm { 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric // Fuse AES crypto encoding or decoding. 22*0b57cec5SDimitry Andric static bool isAESPair(const MachineInstr *FirstMI, 23*0b57cec5SDimitry Andric const MachineInstr &SecondMI) { 24*0b57cec5SDimitry Andric // Assume the 1st instr to be a wildcard if it is unspecified. 25*0b57cec5SDimitry Andric switch(SecondMI.getOpcode()) { 26*0b57cec5SDimitry Andric // AES encode. 27*0b57cec5SDimitry Andric case ARM::AESMC : 28*0b57cec5SDimitry Andric return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESE; 29*0b57cec5SDimitry Andric // AES decode. 30*0b57cec5SDimitry Andric case ARM::AESIMC: 31*0b57cec5SDimitry Andric return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESD; 32*0b57cec5SDimitry Andric } 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric return false; 35*0b57cec5SDimitry Andric } 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andric // Fuse literal generation. 38*0b57cec5SDimitry Andric static bool isLiteralsPair(const MachineInstr *FirstMI, 39*0b57cec5SDimitry Andric const MachineInstr &SecondMI) { 40*0b57cec5SDimitry Andric // Assume the 1st instr to be a wildcard if it is unspecified. 41*0b57cec5SDimitry Andric if ((FirstMI == nullptr || FirstMI->getOpcode() == ARM::MOVi16) && 42*0b57cec5SDimitry Andric SecondMI.getOpcode() == ARM::MOVTi16) 43*0b57cec5SDimitry Andric return true; 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric return false; 46*0b57cec5SDimitry Andric } 47*0b57cec5SDimitry Andric 48*0b57cec5SDimitry Andric /// Check if the instr pair, FirstMI and SecondMI, should be fused 49*0b57cec5SDimitry Andric /// together. Given SecondMI, when FirstMI is unspecified, then check if 50*0b57cec5SDimitry Andric /// SecondMI may be part of a fused pair at all. 51*0b57cec5SDimitry Andric static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, 52*0b57cec5SDimitry Andric const TargetSubtargetInfo &TSI, 53*0b57cec5SDimitry Andric const MachineInstr *FirstMI, 54*0b57cec5SDimitry Andric const MachineInstr &SecondMI) { 55*0b57cec5SDimitry Andric const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(TSI); 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric if (ST.hasFuseAES() && isAESPair(FirstMI, SecondMI)) 58*0b57cec5SDimitry Andric return true; 59*0b57cec5SDimitry Andric if (ST.hasFuseLiterals() && isLiteralsPair(FirstMI, SecondMI)) 60*0b57cec5SDimitry Andric return true; 61*0b57cec5SDimitry Andric 62*0b57cec5SDimitry Andric return false; 63*0b57cec5SDimitry Andric } 64*0b57cec5SDimitry Andric 65*0b57cec5SDimitry Andric std::unique_ptr<ScheduleDAGMutation> createARMMacroFusionDAGMutation () { 66*0b57cec5SDimitry Andric return createMacroFusionDAGMutation(shouldScheduleAdjacent); 67*0b57cec5SDimitry Andric } 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric } // end namespace llvm 70