1*700637cbSDimitry Andric //===- ARMLatencyMutations.h - ARM Latency Mutations ----------------------===// 2*700637cbSDimitry Andric // 3*700637cbSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*700637cbSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*700637cbSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*700637cbSDimitry Andric // 7*700637cbSDimitry Andric //===----------------------------------------------------------------------===// 8*700637cbSDimitry Andric // 9*700637cbSDimitry Andric /// \file This file contains the ARM definition DAG scheduling mutations which 10*700637cbSDimitry Andric /// change inter-instruction latencies 11*700637cbSDimitry Andric // 12*700637cbSDimitry Andric //===----------------------------------------------------------------------===// 13*700637cbSDimitry Andric 14*700637cbSDimitry Andric #ifndef LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H 15*700637cbSDimitry Andric #define LLVM_LIB_TARGET_ARM_LATENCYMUTATIONS_H 16*700637cbSDimitry Andric 17*700637cbSDimitry Andric #include "llvm/CodeGen/MachineScheduler.h" 18*700637cbSDimitry Andric #include "llvm/CodeGen/ScheduleDAGMutation.h" 19*700637cbSDimitry Andric 20*700637cbSDimitry Andric namespace llvm { 21*700637cbSDimitry Andric 22*700637cbSDimitry Andric class AAResults; 23*700637cbSDimitry Andric class ARMBaseInstrInfo; 24*700637cbSDimitry Andric 25*700637cbSDimitry Andric /// Post-process the DAG to create cluster edges between instrs that may 26*700637cbSDimitry Andric /// be fused by the processor into a single operation. 27*700637cbSDimitry Andric class ARMOverrideBypasses : public ScheduleDAGMutation { 28*700637cbSDimitry Andric public: ARMOverrideBypasses(const ARMBaseInstrInfo * t,AAResults * a)29*700637cbSDimitry Andric ARMOverrideBypasses(const ARMBaseInstrInfo *t, AAResults *a) 30*700637cbSDimitry Andric : ScheduleDAGMutation(), TII(t), AA(a) {} 31*700637cbSDimitry Andric 32*700637cbSDimitry Andric void apply(ScheduleDAGInstrs *DAGInstrs) override; 33*700637cbSDimitry Andric 34*700637cbSDimitry Andric private: 35*700637cbSDimitry Andric virtual void modifyBypasses(SUnit &) = 0; 36*700637cbSDimitry Andric 37*700637cbSDimitry Andric protected: 38*700637cbSDimitry Andric const ARMBaseInstrInfo *TII; 39*700637cbSDimitry Andric AAResults *AA; 40*700637cbSDimitry Andric ScheduleDAGInstrs *DAG = nullptr; 41*700637cbSDimitry Andric 42*700637cbSDimitry Andric static void setBidirLatencies(SUnit &SrcSU, SDep &SrcDep, unsigned latency); 43*700637cbSDimitry Andric static bool zeroOutputDependences(SUnit &ISU, SDep &Dep); 44*700637cbSDimitry Andric unsigned makeBundleAssumptions(SUnit &ISU, SDep &Dep); 45*700637cbSDimitry Andric bool memoryRAWHazard(SUnit &ISU, SDep &Dep, unsigned latency); 46*700637cbSDimitry Andric }; 47*700637cbSDimitry Andric 48*700637cbSDimitry Andric /// Note that you have to add: 49*700637cbSDimitry Andric /// DAG.addMutation(createARMLatencyMutation(ST, AA)); 50*700637cbSDimitry Andric /// to ARMTargetMachine::createMachineScheduler() to have an effect. 51*700637cbSDimitry Andric std::unique_ptr<ScheduleDAGMutation> 52*700637cbSDimitry Andric createARMLatencyMutations(const class ARMSubtarget &, AAResults *AA); 53*700637cbSDimitry Andric 54*700637cbSDimitry Andric } // namespace llvm 55*700637cbSDimitry Andric 56*700637cbSDimitry Andric #endif 57