1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM VFP instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 14def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 15 SDTCisSameAs<1, 2>]>; 16def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 17 SDTCisVT<2, f64>]>; 18 19def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>; 20 21def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 22def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 23def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 24def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>; 25def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>; 26def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 27def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>; 28def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>; 29 30def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >; 31def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >; 32def arm_vmovhr : SDNode<"ARMISD::VMOVhr", SDT_VMOVhr>; 33def arm_vmovrh : SDNode<"ARMISD::VMOVrh", SDT_VMOVrh>; 34 35//===----------------------------------------------------------------------===// 36// Operand Definitions. 37// 38 39// 8-bit floating-point immediate encodings. 40def FPImmOperand : AsmOperandClass { 41 let Name = "FPImm"; 42 let ParserMethod = "parseFPImm"; 43} 44 45def vfp_f16imm : Operand<f16>, 46 PatLeaf<(f16 fpimm), [{ 47 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1; 48 }], SDNodeXForm<fpimm, [{ 49 APFloat InVal = N->getValueAPF(); 50 uint32_t enc = ARM_AM::getFP16Imm(InVal); 51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 52 }]>> { 53 let PrintMethod = "printFPImmOperand"; 54 let ParserMatchClass = FPImmOperand; 55} 56 57def vfp_f32imm_xform : SDNodeXForm<fpimm, [{ 58 APFloat InVal = N->getValueAPF(); 59 uint32_t enc = ARM_AM::getFP32Imm(InVal); 60 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 61 }]>; 62 63def gi_vfp_f32imm : GICustomOperandRenderer<"renderVFPF32Imm">, 64 GISDNodeXFormEquiv<vfp_f32imm_xform>; 65 66def vfp_f32imm : Operand<f32>, 67 PatLeaf<(f32 fpimm), [{ 68 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 69 }], vfp_f32imm_xform> { 70 let PrintMethod = "printFPImmOperand"; 71 let ParserMatchClass = FPImmOperand; 72 let GISelPredicateCode = [{ 73 const auto &MO = MI.getOperand(1); 74 if (!MO.isFPImm()) 75 return false; 76 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; 77 }]; 78} 79 80def vfp_f64imm_xform : SDNodeXForm<fpimm, [{ 81 APFloat InVal = N->getValueAPF(); 82 uint32_t enc = ARM_AM::getFP64Imm(InVal); 83 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 84 }]>; 85 86def gi_vfp_f64imm : GICustomOperandRenderer<"renderVFPF64Imm">, 87 GISDNodeXFormEquiv<vfp_f64imm_xform>; 88 89def vfp_f64imm : Operand<f64>, 90 PatLeaf<(f64 fpimm), [{ 91 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 92 }], vfp_f64imm_xform> { 93 let PrintMethod = "printFPImmOperand"; 94 let ParserMatchClass = FPImmOperand; 95 let GISelPredicateCode = [{ 96 const auto &MO = MI.getOperand(1); 97 if (!MO.isFPImm()) 98 return false; 99 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; 100 }]; 101} 102 103def alignedload16 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 104 return cast<LoadSDNode>(N)->getAlignment() >= 2; 105}]>; 106 107def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 108 return cast<LoadSDNode>(N)->getAlignment() >= 4; 109}]>; 110 111def alignedstore16 : PatFrag<(ops node:$val, node:$ptr), 112 (store node:$val, node:$ptr), [{ 113 return cast<StoreSDNode>(N)->getAlignment() >= 2; 114}]>; 115 116def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 117 (store node:$val, node:$ptr), [{ 118 return cast<StoreSDNode>(N)->getAlignment() >= 4; 119}]>; 120 121// The VCVT to/from fixed-point instructions encode the 'fbits' operand 122// (the number of fixed bits) differently than it appears in the assembly 123// source. It's encoded as "Size - fbits" where Size is the size of the 124// fixed-point representation (32 or 16) and fbits is the value appearing 125// in the assembly source, an integer in [0,16] or (0,32], depending on size. 126def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 127def fbits32 : Operand<i32> { 128 let PrintMethod = "printFBits32"; 129 let ParserMatchClass = fbits32_asm_operand; 130} 131 132def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 133def fbits16 : Operand<i32> { 134 let PrintMethod = "printFBits16"; 135 let ParserMatchClass = fbits16_asm_operand; 136} 137 138//===----------------------------------------------------------------------===// 139// Load / store Instructions. 140// 141 142let canFoldAsLoad = 1, isReMaterializable = 1 in { 143 144def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 145 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 146 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>, 147 Requires<[HasFPRegs]>; 148 149def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 150 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 151 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 152 Requires<[HasFPRegs]> { 153 // Some single precision VFP instructions may be executed on both NEON and VFP 154 // pipelines. 155 let D = VFPNeonDomain; 156} 157 158let isUnpredicable = 1 in 159def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr), 160 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr", 161 [(set HPR:$Sd, (alignedload16 addrmode5fp16:$addr))]>, 162 Requires<[HasFPRegs16]>; 163 164} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 165 166def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 167 IIC_fpStore64, "vstr", "\t$Dd, $addr", 168 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>, 169 Requires<[HasFPRegs]>; 170 171def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 172 IIC_fpStore32, "vstr", "\t$Sd, $addr", 173 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 174 Requires<[HasFPRegs]> { 175 // Some single precision VFP instructions may be executed on both NEON and VFP 176 // pipelines. 177 let D = VFPNeonDomain; 178} 179 180let isUnpredicable = 1 in 181def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr), 182 IIC_fpStore16, "vstr", ".16\t$Sd, $addr", 183 [(alignedstore16 HPR:$Sd, addrmode5fp16:$addr)]>, 184 Requires<[HasFPRegs16]>; 185 186//===----------------------------------------------------------------------===// 187// Load / store multiple Instructions. 188// 189 190multiclass vfp_ldst_mult<string asm, bit L_bit, 191 InstrItinClass itin, InstrItinClass itin_upd> { 192 let Predicates = [HasFPRegs] in { 193 // Double Precision 194 def DIA : 195 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 196 IndexModeNone, itin, 197 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 198 let Inst{24-23} = 0b01; // Increment After 199 let Inst{21} = 0; // No writeback 200 let Inst{20} = L_bit; 201 } 202 def DIA_UPD : 203 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 204 variable_ops), 205 IndexModeUpd, itin_upd, 206 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 207 let Inst{24-23} = 0b01; // Increment After 208 let Inst{21} = 1; // Writeback 209 let Inst{20} = L_bit; 210 } 211 def DDB_UPD : 212 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 213 variable_ops), 214 IndexModeUpd, itin_upd, 215 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 216 let Inst{24-23} = 0b10; // Decrement Before 217 let Inst{21} = 1; // Writeback 218 let Inst{20} = L_bit; 219 } 220 221 // Single Precision 222 def SIA : 223 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 224 IndexModeNone, itin, 225 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 226 let Inst{24-23} = 0b01; // Increment After 227 let Inst{21} = 0; // No writeback 228 let Inst{20} = L_bit; 229 230 // Some single precision VFP instructions may be executed on both NEON and 231 // VFP pipelines. 232 let D = VFPNeonDomain; 233 } 234 def SIA_UPD : 235 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 236 variable_ops), 237 IndexModeUpd, itin_upd, 238 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 239 let Inst{24-23} = 0b01; // Increment After 240 let Inst{21} = 1; // Writeback 241 let Inst{20} = L_bit; 242 243 // Some single precision VFP instructions may be executed on both NEON and 244 // VFP pipelines. 245 let D = VFPNeonDomain; 246 } 247 def SDB_UPD : 248 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 249 variable_ops), 250 IndexModeUpd, itin_upd, 251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 252 let Inst{24-23} = 0b10; // Decrement Before 253 let Inst{21} = 1; // Writeback 254 let Inst{20} = L_bit; 255 256 // Some single precision VFP instructions may be executed on both NEON and 257 // VFP pipelines. 258 let D = VFPNeonDomain; 259 } 260 } 261} 262 263let hasSideEffects = 0 in { 264 265let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 266defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 267 268let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 269defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 270 271} // hasSideEffects 272 273def : MnemonicAlias<"vldm", "vldmia">; 274def : MnemonicAlias<"vstm", "vstmia">; 275 276 277//===----------------------------------------------------------------------===// 278// Lazy load / store multiple Instructions 279// 280let mayLoad = 1 in 281def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 282 NoItinerary, "vlldm${p}\t$Rn", "", []>, 283 Requires<[HasV8MMainline, Has8MSecExt]> { 284 let Inst{24-23} = 0b00; 285 let Inst{22} = 0; 286 let Inst{21} = 1; 287 let Inst{20} = 1; 288 let Inst{15-12} = 0; 289 let Inst{7-0} = 0; 290 let mayLoad = 1; 291} 292 293let mayStore = 1 in 294def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 295 NoItinerary, "vlstm${p}\t$Rn", "", []>, 296 Requires<[HasV8MMainline, Has8MSecExt]> { 297 let Inst{24-23} = 0b00; 298 let Inst{22} = 0; 299 let Inst{21} = 1; 300 let Inst{20} = 0; 301 let Inst{15-12} = 0; 302 let Inst{7-0} = 0; 303 let mayStore = 1; 304} 305 306def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>, 307 Requires<[HasFPRegs]>; 308def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>, 309 Requires<[HasFPRegs]>; 310def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>, 311 Requires<[HasFPRegs]>; 312def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>, 313 Requires<[HasFPRegs]>; 314defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 315 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 316defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 317 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 318defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 319 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 320defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 321 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 322 323// FLDMX, FSTMX - Load and store multiple unknown precision registers for 324// pre-armv6 cores. 325// These instruction are deprecated so we don't want them to get selected. 326// However, there is no UAL syntax for them, so we keep them around for 327// (dis)assembly only. 328multiclass vfp_ldstx_mult<string asm, bit L_bit> { 329 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in { 330 // Unknown precision 331 def XIA : 332 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 333 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 334 let Inst{24-23} = 0b01; // Increment After 335 let Inst{21} = 0; // No writeback 336 let Inst{20} = L_bit; 337 } 338 def XIA_UPD : 339 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 340 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 341 let Inst{24-23} = 0b01; // Increment After 342 let Inst{21} = 1; // Writeback 343 let Inst{20} = L_bit; 344 } 345 def XDB_UPD : 346 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 347 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 348 let Inst{24-23} = 0b10; // Decrement Before 349 let Inst{21} = 1; // Writeback 350 let Inst{20} = L_bit; 351 } 352 } 353} 354 355defm FLDM : vfp_ldstx_mult<"fldm", 1>; 356defm FSTM : vfp_ldstx_mult<"fstm", 0>; 357 358def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 359def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 360 361def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 362def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 363 364//===----------------------------------------------------------------------===// 365// FP Binary Operations. 366// 367 368let TwoOperandAliasConstraint = "$Dn = $Dd" in 369def VADDD : ADbI<0b11100, 0b11, 0, 0, 370 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 371 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 372 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, 373 Sched<[WriteFPALU64]>; 374 375let TwoOperandAliasConstraint = "$Sn = $Sd" in 376def VADDS : ASbIn<0b11100, 0b11, 0, 0, 377 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 378 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 379 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 380 Sched<[WriteFPALU32]> { 381 // Some single precision VFP instructions may be executed on both NEON and 382 // VFP pipelines on A8. 383 let D = VFPNeonA8Domain; 384} 385 386let TwoOperandAliasConstraint = "$Sn = $Sd" in 387def VADDH : AHbI<0b11100, 0b11, 0, 0, 388 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 389 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", 390 [(set HPR:$Sd, (fadd HPR:$Sn, HPR:$Sm))]>, 391 Sched<[WriteFPALU32]>; 392 393let TwoOperandAliasConstraint = "$Dn = $Dd" in 394def VSUBD : ADbI<0b11100, 0b11, 1, 0, 395 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 396 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 397 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, 398 Sched<[WriteFPALU64]>; 399 400let TwoOperandAliasConstraint = "$Sn = $Sd" in 401def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 402 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 403 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 404 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 405 Sched<[WriteFPALU32]>{ 406 // Some single precision VFP instructions may be executed on both NEON and 407 // VFP pipelines on A8. 408 let D = VFPNeonA8Domain; 409} 410 411let TwoOperandAliasConstraint = "$Sn = $Sd" in 412def VSUBH : AHbI<0b11100, 0b11, 1, 0, 413 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 414 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm", 415 [(set HPR:$Sd, (fsub HPR:$Sn, HPR:$Sm))]>, 416 Sched<[WriteFPALU32]>; 417 418let TwoOperandAliasConstraint = "$Dn = $Dd" in 419def VDIVD : ADbI<0b11101, 0b00, 0, 0, 420 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 421 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 422 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, 423 Sched<[WriteFPDIV64]>; 424 425let TwoOperandAliasConstraint = "$Sn = $Sd" in 426def VDIVS : ASbI<0b11101, 0b00, 0, 0, 427 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 428 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 429 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, 430 Sched<[WriteFPDIV32]>; 431 432let TwoOperandAliasConstraint = "$Sn = $Sd" in 433def VDIVH : AHbI<0b11101, 0b00, 0, 0, 434 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 435 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", 436 [(set HPR:$Sd, (fdiv HPR:$Sn, HPR:$Sm))]>, 437 Sched<[WriteFPDIV32]>; 438 439let TwoOperandAliasConstraint = "$Dn = $Dd" in 440def VMULD : ADbI<0b11100, 0b10, 0, 0, 441 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 442 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 443 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>, 444 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 445 446let TwoOperandAliasConstraint = "$Sn = $Sd" in 447def VMULS : ASbIn<0b11100, 0b10, 0, 0, 448 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 449 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 450 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>, 451 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 452 // Some single precision VFP instructions may be executed on both NEON and 453 // VFP pipelines on A8. 454 let D = VFPNeonA8Domain; 455} 456 457let TwoOperandAliasConstraint = "$Sn = $Sd" in 458def VMULH : AHbI<0b11100, 0b10, 0, 0, 459 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 460 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", 461 [(set HPR:$Sd, (fmul HPR:$Sn, HPR:$Sm))]>, 462 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 463 464def VNMULD : ADbI<0b11100, 0b10, 1, 0, 465 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 466 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 467 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, 468 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 469 470def VNMULS : ASbI<0b11100, 0b10, 1, 0, 471 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 472 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 473 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>, 474 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 475 // Some single precision VFP instructions may be executed on both NEON and 476 // VFP pipelines on A8. 477 let D = VFPNeonA8Domain; 478} 479 480def VNMULH : AHbI<0b11100, 0b10, 1, 0, 481 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 482 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", 483 [(set HPR:$Sd, (fneg (fmul HPR:$Sn, HPR:$Sm)))]>, 484 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 485 486multiclass vsel_inst<string op, bits<2> opc, int CC> { 487 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 488 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in { 489 def H : AHbInp<0b11100, opc, 0, 490 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 491 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), 492 [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, CC))]>, 493 Requires<[HasFullFP16]>; 494 495 def S : ASbInp<0b11100, opc, 0, 496 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 497 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 498 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 499 Requires<[HasFPARMv8]>; 500 501 def D : ADbInp<0b11100, opc, 0, 502 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 503 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 504 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 505 Requires<[HasFPARMv8, HasDPVFP]>; 506 } 507} 508 509// The CC constants here match ARMCC::CondCodes. 510defm VSELGT : vsel_inst<"gt", 0b11, 12>; 511defm VSELGE : vsel_inst<"ge", 0b10, 10>; 512defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 513defm VSELVS : vsel_inst<"vs", 0b01, 6>; 514 515multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 516 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 517 isUnpredicable = 1 in { 518 def H : AHbInp<0b11101, 0b00, opc, 519 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 520 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), 521 [(set HPR:$Sd, (SD HPR:$Sn, HPR:$Sm))]>, 522 Requires<[HasFullFP16]>; 523 524 def S : ASbInp<0b11101, 0b00, opc, 525 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 526 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 527 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 528 Requires<[HasFPARMv8]>; 529 530 def D : ADbInp<0b11101, 0b00, opc, 531 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 532 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 533 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 534 Requires<[HasFPARMv8, HasDPVFP]>; 535 } 536} 537 538defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; 539defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; 540 541// Match reassociated forms only if not sign dependent rounding. 542def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 543 (VNMULD DPR:$a, DPR:$b)>, 544 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 545def : Pat<(fmul (fneg SPR:$a), SPR:$b), 546 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 547 548// These are encoded as unary instructions. 549let Defs = [FPSCR_NZCV] in { 550def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 551 (outs), (ins DPR:$Dd, DPR:$Dm), 552 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 553 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>; 554 555def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 556 (outs), (ins SPR:$Sd, SPR:$Sm), 557 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 558 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> { 559 // Some single precision VFP instructions may be executed on both NEON and 560 // VFP pipelines on A8. 561 let D = VFPNeonA8Domain; 562} 563 564def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0, 565 (outs), (ins HPR:$Sd, HPR:$Sm), 566 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm", 567 [(arm_cmpfpe HPR:$Sd, HPR:$Sm)]>; 568 569def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 570 (outs), (ins DPR:$Dd, DPR:$Dm), 571 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 572 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 573 574def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 575 (outs), (ins SPR:$Sd, SPR:$Sm), 576 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 577 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 578 // Some single precision VFP instructions may be executed on both NEON and 579 // VFP pipelines on A8. 580 let D = VFPNeonA8Domain; 581} 582 583def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0, 584 (outs), (ins HPR:$Sd, HPR:$Sm), 585 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm", 586 [(arm_cmpfp HPR:$Sd, HPR:$Sm)]>; 587} // Defs = [FPSCR_NZCV] 588 589//===----------------------------------------------------------------------===// 590// FP Unary Operations. 591// 592 593def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 594 (outs DPR:$Dd), (ins DPR:$Dm), 595 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 596 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 597 598def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 599 (outs SPR:$Sd), (ins SPR:$Sm), 600 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 601 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 602 // Some single precision VFP instructions may be executed on both NEON and 603 // VFP pipelines on A8. 604 let D = VFPNeonA8Domain; 605} 606 607def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0, 608 (outs HPR:$Sd), (ins HPR:$Sm), 609 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm", 610 [(set HPR:$Sd, (fabs (f16 HPR:$Sm)))]>; 611 612let Defs = [FPSCR_NZCV] in { 613def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 614 (outs), (ins DPR:$Dd), 615 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 616 [(arm_cmpfpe0 (f64 DPR:$Dd))]> { 617 let Inst{3-0} = 0b0000; 618 let Inst{5} = 0; 619} 620 621def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 622 (outs), (ins SPR:$Sd), 623 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 624 [(arm_cmpfpe0 SPR:$Sd)]> { 625 let Inst{3-0} = 0b0000; 626 let Inst{5} = 0; 627 628 // Some single precision VFP instructions may be executed on both NEON and 629 // VFP pipelines on A8. 630 let D = VFPNeonA8Domain; 631} 632 633def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, 634 (outs), (ins HPR:$Sd), 635 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0", 636 [(arm_cmpfpe0 HPR:$Sd)]> { 637 let Inst{3-0} = 0b0000; 638 let Inst{5} = 0; 639} 640 641def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 642 (outs), (ins DPR:$Dd), 643 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 644 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 645 let Inst{3-0} = 0b0000; 646 let Inst{5} = 0; 647} 648 649def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 650 (outs), (ins SPR:$Sd), 651 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 652 [(arm_cmpfp0 SPR:$Sd)]> { 653 let Inst{3-0} = 0b0000; 654 let Inst{5} = 0; 655 656 // Some single precision VFP instructions may be executed on both NEON and 657 // VFP pipelines on A8. 658 let D = VFPNeonA8Domain; 659} 660 661def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, 662 (outs), (ins HPR:$Sd), 663 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0", 664 [(arm_cmpfp0 HPR:$Sd)]> { 665 let Inst{3-0} = 0b0000; 666 let Inst{5} = 0; 667} 668} // Defs = [FPSCR_NZCV] 669 670def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 671 (outs DPR:$Dd), (ins SPR:$Sm), 672 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 673 [(set DPR:$Dd, (fpextend SPR:$Sm))]>, 674 Sched<[WriteFPCVT]> { 675 // Instruction operands. 676 bits<5> Dd; 677 bits<5> Sm; 678 679 // Encode instruction operands. 680 let Inst{3-0} = Sm{4-1}; 681 let Inst{5} = Sm{0}; 682 let Inst{15-12} = Dd{3-0}; 683 let Inst{22} = Dd{4}; 684 685 let Predicates = [HasVFP2, HasDPVFP]; 686} 687 688// Special case encoding: bits 11-8 is 0b1011. 689def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 690 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 691 [(set SPR:$Sd, (fpround DPR:$Dm))]>, 692 Sched<[WriteFPCVT]> { 693 // Instruction operands. 694 bits<5> Sd; 695 bits<5> Dm; 696 697 // Encode instruction operands. 698 let Inst{3-0} = Dm{3-0}; 699 let Inst{5} = Dm{4}; 700 let Inst{15-12} = Sd{4-1}; 701 let Inst{22} = Sd{0}; 702 703 let Inst{27-23} = 0b11101; 704 let Inst{21-16} = 0b110111; 705 let Inst{11-8} = 0b1011; 706 let Inst{7-6} = 0b11; 707 let Inst{4} = 0; 708 709 let Predicates = [HasVFP2, HasDPVFP]; 710} 711 712// Between half, single and double-precision. 713def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 714 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 715 [/* Intentionally left blank, see patterns below */]>, 716 Requires<[HasFP16]>, 717 Sched<[WriteFPCVT]>; 718 719def : FP16Pat<(f32 (fpextend HPR:$Sm)), 720 (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>; 721def : FP16Pat<(f16_to_fp GPR:$a), 722 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 723 724def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 725 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 726 [/* Intentionally left blank, see patterns below */]>, 727 Requires<[HasFP16]>, 728 Sched<[WriteFPCVT]>; 729 730def : FP16Pat<(f16 (fpround SPR:$Sm)), 731 (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>; 732def : FP16Pat<(fp_to_f16 SPR:$a), 733 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 734 735def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 736 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 737 [/* For disassembly only; pattern left blank */]>, 738 Requires<[HasFP16]>, 739 Sched<[WriteFPCVT]>; 740 741def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 742 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 743 [/* For disassembly only; pattern left blank */]>, 744 Requires<[HasFP16]>, 745 Sched<[WriteFPCVT]>; 746 747def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 748 (outs DPR:$Dd), (ins SPR:$Sm), 749 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 750 [/* Intentionally left blank, see patterns below */]>, 751 Requires<[HasFPARMv8, HasDPVFP]>, 752 Sched<[WriteFPCVT]> { 753 // Instruction operands. 754 bits<5> Sm; 755 756 // Encode instruction operands. 757 let Inst{3-0} = Sm{4-1}; 758 let Inst{5} = Sm{0}; 759} 760 761def : FullFP16Pat<(f64 (fpextend HPR:$Sm)), 762 (VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>, 763 Requires<[HasFPARMv8, HasDPVFP]>; 764def : FP16Pat<(f64 (f16_to_fp GPR:$a)), 765 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>, 766 Requires<[HasFPARMv8, HasDPVFP]>; 767 768def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 769 (outs SPR:$Sd), (ins DPR:$Dm), 770 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 771 [/* Intentionally left blank, see patterns below */]>, 772 Requires<[HasFPARMv8, HasDPVFP]> { 773 // Instruction operands. 774 bits<5> Sd; 775 bits<5> Dm; 776 777 // Encode instruction operands. 778 let Inst{3-0} = Dm{3-0}; 779 let Inst{5} = Dm{4}; 780 let Inst{15-12} = Sd{4-1}; 781 let Inst{22} = Sd{0}; 782} 783 784def : FullFP16Pat<(f16 (fpround DPR:$Dm)), 785 (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>, 786 Requires<[HasFPARMv8, HasDPVFP]>; 787def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), 788 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>, 789 Requires<[HasFPARMv8, HasDPVFP]>; 790 791def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 792 (outs DPR:$Dd), (ins SPR:$Sm), 793 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 794 []>, Requires<[HasFPARMv8, HasDPVFP]> { 795 // Instruction operands. 796 bits<5> Sm; 797 798 // Encode instruction operands. 799 let Inst{3-0} = Sm{4-1}; 800 let Inst{5} = Sm{0}; 801} 802 803def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 804 (outs SPR:$Sd), (ins DPR:$Dm), 805 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 806 []>, Requires<[HasFPARMv8, HasDPVFP]> { 807 // Instruction operands. 808 bits<5> Sd; 809 bits<5> Dm; 810 811 // Encode instruction operands. 812 let Inst{15-12} = Sd{4-1}; 813 let Inst{22} = Sd{0}; 814 let Inst{3-0} = Dm{3-0}; 815 let Inst{5} = Dm{4}; 816} 817 818multiclass vcvt_inst<string opc, bits<2> rm, 819 SDPatternOperator node = null_frag> { 820 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in { 821 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0, 822 (outs SPR:$Sd), (ins HPR:$Sm), 823 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"), 824 []>, 825 Requires<[HasFullFP16]> { 826 let Inst{17-16} = rm; 827 } 828 829 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0, 830 (outs SPR:$Sd), (ins HPR:$Sm), 831 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"), 832 []>, 833 Requires<[HasFullFP16]> { 834 let Inst{17-16} = rm; 835 } 836 837 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 838 (outs SPR:$Sd), (ins SPR:$Sm), 839 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 840 []>, 841 Requires<[HasFPARMv8]> { 842 let Inst{17-16} = rm; 843 } 844 845 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 846 (outs SPR:$Sd), (ins SPR:$Sm), 847 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 848 []>, 849 Requires<[HasFPARMv8]> { 850 let Inst{17-16} = rm; 851 } 852 853 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 854 (outs SPR:$Sd), (ins DPR:$Dm), 855 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 856 []>, 857 Requires<[HasFPARMv8, HasDPVFP]> { 858 bits<5> Dm; 859 860 let Inst{17-16} = rm; 861 862 // Encode instruction operands. 863 let Inst{3-0} = Dm{3-0}; 864 let Inst{5} = Dm{4}; 865 let Inst{8} = 1; 866 } 867 868 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 869 (outs SPR:$Sd), (ins DPR:$Dm), 870 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 871 []>, 872 Requires<[HasFPARMv8, HasDPVFP]> { 873 bits<5> Dm; 874 875 let Inst{17-16} = rm; 876 877 // Encode instruction operands 878 let Inst{3-0} = Dm{3-0}; 879 let Inst{5} = Dm{4}; 880 let Inst{8} = 1; 881 } 882 } 883 884 let Predicates = [HasFPARMv8] in { 885 let Predicates = [HasFullFP16] in { 886 def : Pat<(i32 (fp_to_sint (node HPR:$a))), 887 (COPY_TO_REGCLASS 888 (!cast<Instruction>(NAME#"SH") HPR:$a), 889 GPR)>; 890 891 def : Pat<(i32 (fp_to_uint (node HPR:$a))), 892 (COPY_TO_REGCLASS 893 (!cast<Instruction>(NAME#"UH") HPR:$a), 894 GPR)>; 895 } 896 def : Pat<(i32 (fp_to_sint (node SPR:$a))), 897 (COPY_TO_REGCLASS 898 (!cast<Instruction>(NAME#"SS") SPR:$a), 899 GPR)>; 900 def : Pat<(i32 (fp_to_uint (node SPR:$a))), 901 (COPY_TO_REGCLASS 902 (!cast<Instruction>(NAME#"US") SPR:$a), 903 GPR)>; 904 } 905 let Predicates = [HasFPARMv8, HasDPVFP] in { 906 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))), 907 (COPY_TO_REGCLASS 908 (!cast<Instruction>(NAME#"SD") DPR:$a), 909 GPR)>; 910 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))), 911 (COPY_TO_REGCLASS 912 (!cast<Instruction>(NAME#"UD") DPR:$a), 913 GPR)>; 914 } 915} 916 917defm VCVTA : vcvt_inst<"a", 0b00, fround>; 918defm VCVTN : vcvt_inst<"n", 0b01>; 919defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 920defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 921 922def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 923 (outs DPR:$Dd), (ins DPR:$Dm), 924 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 925 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 926 927def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 928 (outs SPR:$Sd), (ins SPR:$Sm), 929 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 930 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 931 // Some single precision VFP instructions may be executed on both NEON and 932 // VFP pipelines on A8. 933 let D = VFPNeonA8Domain; 934} 935 936def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0, 937 (outs HPR:$Sd), (ins HPR:$Sm), 938 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm", 939 [(set HPR:$Sd, (fneg HPR:$Sm))]>; 940 941multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 942 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0, 943 (outs HPR:$Sd), (ins HPR:$Sm), 944 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm", 945 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 946 Requires<[HasFullFP16]> { 947 let Inst{7} = op2; 948 let Inst{16} = op; 949 } 950 951 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 952 (outs SPR:$Sd), (ins SPR:$Sm), 953 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 954 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 955 Requires<[HasFPARMv8]> { 956 let Inst{7} = op2; 957 let Inst{16} = op; 958 } 959 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 960 (outs DPR:$Dd), (ins DPR:$Dm), 961 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 962 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 963 Requires<[HasFPARMv8, HasDPVFP]> { 964 let Inst{7} = op2; 965 let Inst{16} = op; 966 } 967 968 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"), 969 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 970 Requires<[HasFullFP16]>; 971 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 972 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 973 Requires<[HasFPARMv8]>; 974 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 975 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>, 976 Requires<[HasFPARMv8,HasDPVFP]>; 977} 978 979defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 980defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 981defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 982 983multiclass vrint_inst_anpm<string opc, bits<2> rm, 984 SDPatternOperator node = null_frag> { 985 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", 986 isUnpredicable = 1 in { 987 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0, 988 (outs HPR:$Sd), (ins HPR:$Sm), 989 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"), 990 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 991 Requires<[HasFullFP16]> { 992 let Inst{17-16} = rm; 993 } 994 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 995 (outs SPR:$Sd), (ins SPR:$Sm), 996 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 997 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 998 Requires<[HasFPARMv8]> { 999 let Inst{17-16} = rm; 1000 } 1001 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1002 (outs DPR:$Dd), (ins DPR:$Dm), 1003 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 1004 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1005 Requires<[HasFPARMv8, HasDPVFP]> { 1006 let Inst{17-16} = rm; 1007 } 1008 } 1009 1010 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 1011 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>, 1012 Requires<[HasFPARMv8]>; 1013 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 1014 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>, 1015 Requires<[HasFPARMv8,HasDPVFP]>; 1016} 1017 1018defm VRINTA : vrint_inst_anpm<"a", 0b00, fround>; 1019defm VRINTN : vrint_inst_anpm<"n", 0b01, int_arm_neon_vrintn>; 1020defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 1021defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 1022 1023def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 1024 (outs DPR:$Dd), (ins DPR:$Dm), 1025 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 1026 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>, 1027 Sched<[WriteFPSQRT64]>; 1028 1029def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 1030 (outs SPR:$Sd), (ins SPR:$Sm), 1031 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 1032 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>, 1033 Sched<[WriteFPSQRT32]>; 1034 1035def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0, 1036 (outs HPR:$Sd), (ins HPR:$Sm), 1037 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm", 1038 [(set HPR:$Sd, (fsqrt (f16 HPR:$Sm)))]>; 1039 1040let hasSideEffects = 0 in { 1041let isMoveReg = 1 in { 1042def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 1043 (outs DPR:$Dd), (ins DPR:$Dm), 1044 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>, 1045 Requires<[HasFPRegs64]>; 1046 1047def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 1048 (outs SPR:$Sd), (ins SPR:$Sm), 1049 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>, 1050 Requires<[HasFPRegs]>; 1051} // isMoveReg 1052 1053let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in { 1054def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0, 1055 (outs SPR:$Sd), (ins SPR:$Sm), 1056 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>, 1057 Requires<[HasFullFP16]>; 1058 1059def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0, 1060 (outs SPR:$Sd), (ins SPR:$Sm), 1061 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>, 1062 Requires<[HasFullFP16]>; 1063} // PostEncoderMethod 1064} // hasSideEffects 1065 1066//===----------------------------------------------------------------------===// 1067// FP <-> GPR Copies. Int <-> FP Conversions. 1068// 1069 1070let isMoveReg = 1 in { 1071def VMOVRS : AVConv2I<0b11100001, 0b1010, 1072 (outs GPR:$Rt), (ins SPR:$Sn), 1073 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 1074 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>, 1075 Requires<[HasFPRegs]>, 1076 Sched<[WriteFPMOV]> { 1077 // Instruction operands. 1078 bits<4> Rt; 1079 bits<5> Sn; 1080 1081 // Encode instruction operands. 1082 let Inst{19-16} = Sn{4-1}; 1083 let Inst{7} = Sn{0}; 1084 let Inst{15-12} = Rt; 1085 1086 let Inst{6-5} = 0b00; 1087 let Inst{3-0} = 0b0000; 1088 1089 // Some single precision VFP instructions may be executed on both NEON and VFP 1090 // pipelines. 1091 let D = VFPNeonDomain; 1092} 1093 1094// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 1095def VMOVSR : AVConv4I<0b11100000, 0b1010, 1096 (outs SPR:$Sn), (ins GPR:$Rt), 1097 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 1098 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 1099 Requires<[HasFPRegs, UseVMOVSR]>, 1100 Sched<[WriteFPMOV]> { 1101 // Instruction operands. 1102 bits<5> Sn; 1103 bits<4> Rt; 1104 1105 // Encode instruction operands. 1106 let Inst{19-16} = Sn{4-1}; 1107 let Inst{7} = Sn{0}; 1108 let Inst{15-12} = Rt; 1109 1110 let Inst{6-5} = 0b00; 1111 let Inst{3-0} = 0b0000; 1112 1113 // Some single precision VFP instructions may be executed on both NEON and VFP 1114 // pipelines. 1115 let D = VFPNeonDomain; 1116} 1117} // isMoveReg 1118def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>; 1119 1120let hasSideEffects = 0 in { 1121def VMOVRRD : AVConv3I<0b11000101, 0b1011, 1122 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 1123 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 1124 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>, 1125 Requires<[HasFPRegs]>, 1126 Sched<[WriteFPMOV]> { 1127 // Instruction operands. 1128 bits<5> Dm; 1129 bits<4> Rt; 1130 bits<4> Rt2; 1131 1132 // Encode instruction operands. 1133 let Inst{3-0} = Dm{3-0}; 1134 let Inst{5} = Dm{4}; 1135 let Inst{15-12} = Rt; 1136 let Inst{19-16} = Rt2; 1137 1138 let Inst{7-6} = 0b00; 1139 1140 // Some single precision VFP instructions may be executed on both NEON and VFP 1141 // pipelines. 1142 let D = VFPNeonDomain; 1143 1144 // This instruction is equivalent to 1145 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 1146 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 1147 let isExtractSubreg = 1; 1148} 1149 1150def VMOVRRS : AVConv3I<0b11000101, 0b1010, 1151 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 1152 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 1153 [/* For disassembly only; pattern left blank */]>, 1154 Requires<[HasFPRegs]>, 1155 Sched<[WriteFPMOV]> { 1156 bits<5> src1; 1157 bits<4> Rt; 1158 bits<4> Rt2; 1159 1160 // Encode instruction operands. 1161 let Inst{3-0} = src1{4-1}; 1162 let Inst{5} = src1{0}; 1163 let Inst{15-12} = Rt; 1164 let Inst{19-16} = Rt2; 1165 1166 let Inst{7-6} = 0b00; 1167 1168 // Some single precision VFP instructions may be executed on both NEON and VFP 1169 // pipelines. 1170 let D = VFPNeonDomain; 1171 let DecoderMethod = "DecodeVMOVRRS"; 1172} 1173} // hasSideEffects 1174 1175// FMDHR: GPR -> SPR 1176// FMDLR: GPR -> SPR 1177 1178def VMOVDRR : AVConv5I<0b11000100, 0b1011, 1179 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 1180 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 1181 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>, 1182 Requires<[HasFPRegs]>, 1183 Sched<[WriteFPMOV]> { 1184 // Instruction operands. 1185 bits<5> Dm; 1186 bits<4> Rt; 1187 bits<4> Rt2; 1188 1189 // Encode instruction operands. 1190 let Inst{3-0} = Dm{3-0}; 1191 let Inst{5} = Dm{4}; 1192 let Inst{15-12} = Rt; 1193 let Inst{19-16} = Rt2; 1194 1195 let Inst{7-6} = 0b00; 1196 1197 // Some single precision VFP instructions may be executed on both NEON and VFP 1198 // pipelines. 1199 let D = VFPNeonDomain; 1200 1201 // This instruction is equivalent to 1202 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 1203 let isRegSequence = 1; 1204} 1205 1206// Hoist an fabs or a fneg of a value coming from integer registers 1207// and do the fabs/fneg on the integer value. This is never a lose 1208// and could enable the conversion to float to be removed completely. 1209def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1210 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1211 Requires<[IsARM, HasV6T2]>; 1212def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1213 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1214 Requires<[IsThumb2, HasV6T2]>; 1215def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1216 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>, 1217 Requires<[IsARM]>; 1218def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1219 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>, 1220 Requires<[IsThumb2]>; 1221 1222let hasSideEffects = 0 in 1223def VMOVSRR : AVConv5I<0b11000100, 0b1010, 1224 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 1225 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 1226 [/* For disassembly only; pattern left blank */]>, 1227 Requires<[HasFPRegs]>, 1228 Sched<[WriteFPMOV]> { 1229 // Instruction operands. 1230 bits<5> dst1; 1231 bits<4> src1; 1232 bits<4> src2; 1233 1234 // Encode instruction operands. 1235 let Inst{3-0} = dst1{4-1}; 1236 let Inst{5} = dst1{0}; 1237 let Inst{15-12} = src1; 1238 let Inst{19-16} = src2; 1239 1240 let Inst{7-6} = 0b00; 1241 1242 // Some single precision VFP instructions may be executed on both NEON and VFP 1243 // pipelines. 1244 let D = VFPNeonDomain; 1245 1246 let DecoderMethod = "DecodeVMOVSRR"; 1247} 1248 1249// Move H->R, clearing top 16 bits 1250def VMOVRH : AVConv2I<0b11100001, 0b1001, 1251 (outs rGPR:$Rt), (ins HPR:$Sn), 1252 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn", 1253 [(set rGPR:$Rt, (arm_vmovrh HPR:$Sn))]>, 1254 Requires<[HasFPRegs16]>, 1255 Sched<[WriteFPMOV]> { 1256 // Instruction operands. 1257 bits<4> Rt; 1258 bits<5> Sn; 1259 1260 // Encode instruction operands. 1261 let Inst{19-16} = Sn{4-1}; 1262 let Inst{7} = Sn{0}; 1263 let Inst{15-12} = Rt; 1264 1265 let Inst{6-5} = 0b00; 1266 let Inst{3-0} = 0b0000; 1267 1268 let isUnpredicable = 1; 1269} 1270 1271// Move R->H, clearing top 16 bits 1272def VMOVHR : AVConv4I<0b11100000, 0b1001, 1273 (outs HPR:$Sn), (ins rGPR:$Rt), 1274 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt", 1275 [(set HPR:$Sn, (arm_vmovhr rGPR:$Rt))]>, 1276 Requires<[HasFPRegs16]>, 1277 Sched<[WriteFPMOV]> { 1278 // Instruction operands. 1279 bits<5> Sn; 1280 bits<4> Rt; 1281 1282 // Encode instruction operands. 1283 let Inst{19-16} = Sn{4-1}; 1284 let Inst{7} = Sn{0}; 1285 let Inst{15-12} = Rt; 1286 1287 let Inst{6-5} = 0b00; 1288 let Inst{3-0} = 0b0000; 1289 1290 let isUnpredicable = 1; 1291} 1292 1293// FMRDH: SPR -> GPR 1294// FMRDL: SPR -> GPR 1295// FMRRS: SPR -> GPR 1296// FMRX: SPR system reg -> GPR 1297// FMSRR: GPR -> SPR 1298// FMXR: GPR -> VFP system reg 1299 1300 1301// Int -> FP: 1302 1303class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1304 bits<4> opcod4, dag oops, dag iops, 1305 InstrItinClass itin, string opc, string asm, 1306 list<dag> pattern> 1307 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1308 pattern> { 1309 // Instruction operands. 1310 bits<5> Dd; 1311 bits<5> Sm; 1312 1313 // Encode instruction operands. 1314 let Inst{3-0} = Sm{4-1}; 1315 let Inst{5} = Sm{0}; 1316 let Inst{15-12} = Dd{3-0}; 1317 let Inst{22} = Dd{4}; 1318 1319 let Predicates = [HasVFP2, HasDPVFP]; 1320} 1321 1322class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1323 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 1324 string opc, string asm, list<dag> pattern> 1325 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1326 pattern> { 1327 // Instruction operands. 1328 bits<5> Sd; 1329 bits<5> Sm; 1330 1331 // Encode instruction operands. 1332 let Inst{3-0} = Sm{4-1}; 1333 let Inst{5} = Sm{0}; 1334 let Inst{15-12} = Sd{4-1}; 1335 let Inst{22} = Sd{0}; 1336} 1337 1338class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1339 bits<4> opcod4, dag oops, dag iops, 1340 InstrItinClass itin, string opc, string asm, 1341 list<dag> pattern> 1342 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1343 pattern> { 1344 // Instruction operands. 1345 bits<5> Sd; 1346 bits<5> Sm; 1347 1348 // Encode instruction operands. 1349 let Inst{3-0} = Sm{4-1}; 1350 let Inst{5} = Sm{0}; 1351 let Inst{15-12} = Sd{4-1}; 1352 let Inst{22} = Sd{0}; 1353 1354 let Predicates = [HasFullFP16]; 1355} 1356 1357def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1358 (outs DPR:$Dd), (ins SPR:$Sm), 1359 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 1360 []>, 1361 Sched<[WriteFPCVT]> { 1362 let Inst{7} = 1; // s32 1363} 1364 1365let Predicates=[HasVFP2, HasDPVFP] in { 1366 def : VFPPat<(f64 (sint_to_fp GPR:$a)), 1367 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1368 1369 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1370 (VSITOD (VLDRS addrmode5:$a))>; 1371} 1372 1373def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1374 (outs SPR:$Sd),(ins SPR:$Sm), 1375 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 1376 []>, 1377 Sched<[WriteFPCVT]> { 1378 let Inst{7} = 1; // s32 1379 1380 // Some single precision VFP instructions may be executed on both NEON and 1381 // VFP pipelines on A8. 1382 let D = VFPNeonA8Domain; 1383} 1384 1385def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), 1386 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1387 1388def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1389 (VSITOS (VLDRS addrmode5:$a))>; 1390 1391def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1392 (outs HPR:$Sd), (ins SPR:$Sm), 1393 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm", 1394 []>, 1395 Sched<[WriteFPCVT]> { 1396 let Inst{7} = 1; // s32 1397 let isUnpredicable = 1; 1398} 1399 1400def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)), 1401 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1402 1403def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1404 (outs DPR:$Dd), (ins SPR:$Sm), 1405 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1406 []>, 1407 Sched<[WriteFPCVT]> { 1408 let Inst{7} = 0; // u32 1409} 1410 1411let Predicates=[HasVFP2, HasDPVFP] in { 1412 def : VFPPat<(f64 (uint_to_fp GPR:$a)), 1413 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1414 1415 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1416 (VUITOD (VLDRS addrmode5:$a))>; 1417} 1418 1419def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1420 (outs SPR:$Sd), (ins SPR:$Sm), 1421 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1422 []>, 1423 Sched<[WriteFPCVT]> { 1424 let Inst{7} = 0; // u32 1425 1426 // Some single precision VFP instructions may be executed on both NEON and 1427 // VFP pipelines on A8. 1428 let D = VFPNeonA8Domain; 1429} 1430 1431def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), 1432 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1433 1434def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1435 (VUITOS (VLDRS addrmode5:$a))>; 1436 1437def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1438 (outs HPR:$Sd), (ins SPR:$Sm), 1439 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm", 1440 []>, 1441 Sched<[WriteFPCVT]> { 1442 let Inst{7} = 0; // u32 1443 let isUnpredicable = 1; 1444} 1445 1446def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)), 1447 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1448 1449// FP -> Int: 1450 1451class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1452 bits<4> opcod4, dag oops, dag iops, 1453 InstrItinClass itin, string opc, string asm, 1454 list<dag> pattern> 1455 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1456 pattern> { 1457 // Instruction operands. 1458 bits<5> Sd; 1459 bits<5> Dm; 1460 1461 // Encode instruction operands. 1462 let Inst{3-0} = Dm{3-0}; 1463 let Inst{5} = Dm{4}; 1464 let Inst{15-12} = Sd{4-1}; 1465 let Inst{22} = Sd{0}; 1466 1467 let Predicates = [HasVFP2, HasDPVFP]; 1468} 1469 1470class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1471 bits<4> opcod4, dag oops, dag iops, 1472 InstrItinClass itin, string opc, string asm, 1473 list<dag> pattern> 1474 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1475 pattern> { 1476 // Instruction operands. 1477 bits<5> Sd; 1478 bits<5> Sm; 1479 1480 // Encode instruction operands. 1481 let Inst{3-0} = Sm{4-1}; 1482 let Inst{5} = Sm{0}; 1483 let Inst{15-12} = Sd{4-1}; 1484 let Inst{22} = Sd{0}; 1485} 1486 1487class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1488 bits<4> opcod4, dag oops, dag iops, 1489 InstrItinClass itin, string opc, string asm, 1490 list<dag> pattern> 1491 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1492 pattern> { 1493 // Instruction operands. 1494 bits<5> Sd; 1495 bits<5> Sm; 1496 1497 // Encode instruction operands. 1498 let Inst{3-0} = Sm{4-1}; 1499 let Inst{5} = Sm{0}; 1500 let Inst{15-12} = Sd{4-1}; 1501 let Inst{22} = Sd{0}; 1502 1503 let Predicates = [HasFullFP16]; 1504} 1505 1506// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1507def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1508 (outs SPR:$Sd), (ins DPR:$Dm), 1509 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1510 []>, 1511 Sched<[WriteFPCVT]> { 1512 let Inst{7} = 1; // Z bit 1513} 1514 1515let Predicates=[HasVFP2, HasDPVFP] in { 1516 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), 1517 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1518 1519 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), 1520 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1521} 1522 1523def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1524 (outs SPR:$Sd), (ins SPR:$Sm), 1525 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1526 []>, 1527 Sched<[WriteFPCVT]> { 1528 let Inst{7} = 1; // Z bit 1529 1530 // Some single precision VFP instructions may be executed on both NEON and 1531 // VFP pipelines on A8. 1532 let D = VFPNeonA8Domain; 1533} 1534 1535def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), 1536 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1537 1538def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), 1539 addrmode5:$ptr), 1540 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1541 1542def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1543 (outs SPR:$Sd), (ins HPR:$Sm), 1544 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", 1545 []>, 1546 Sched<[WriteFPCVT]> { 1547 let Inst{7} = 1; // Z bit 1548 let isUnpredicable = 1; 1549} 1550 1551def : VFPNoNEONPat<(i32 (fp_to_sint HPR:$a)), 1552 (COPY_TO_REGCLASS (VTOSIZH HPR:$a), GPR)>; 1553 1554def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1555 (outs SPR:$Sd), (ins DPR:$Dm), 1556 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1557 []>, 1558 Sched<[WriteFPCVT]> { 1559 let Inst{7} = 1; // Z bit 1560} 1561 1562let Predicates=[HasVFP2, HasDPVFP] in { 1563 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), 1564 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1565 1566 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), 1567 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1568} 1569 1570def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1571 (outs SPR:$Sd), (ins SPR:$Sm), 1572 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1573 []>, 1574 Sched<[WriteFPCVT]> { 1575 let Inst{7} = 1; // Z bit 1576 1577 // Some single precision VFP instructions may be executed on both NEON and 1578 // VFP pipelines on A8. 1579 let D = VFPNeonA8Domain; 1580} 1581 1582def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), 1583 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1584 1585def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), 1586 addrmode5:$ptr), 1587 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1588 1589def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1590 (outs SPR:$Sd), (ins HPR:$Sm), 1591 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", 1592 []>, 1593 Sched<[WriteFPCVT]> { 1594 let Inst{7} = 1; // Z bit 1595 let isUnpredicable = 1; 1596} 1597 1598def : VFPNoNEONPat<(i32 (fp_to_uint HPR:$a)), 1599 (COPY_TO_REGCLASS (VTOUIZH HPR:$a), GPR)>; 1600 1601// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1602let Uses = [FPSCR] in { 1603def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1604 (outs SPR:$Sd), (ins DPR:$Dm), 1605 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1606 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>, 1607 Sched<[WriteFPCVT]> { 1608 let Inst{7} = 0; // Z bit 1609} 1610 1611def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1612 (outs SPR:$Sd), (ins SPR:$Sm), 1613 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1614 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>, 1615 Sched<[WriteFPCVT]> { 1616 let Inst{7} = 0; // Z bit 1617} 1618 1619def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1620 (outs SPR:$Sd), (ins SPR:$Sm), 1621 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm", 1622 []>, 1623 Sched<[WriteFPCVT]> { 1624 let Inst{7} = 0; // Z bit 1625 let isUnpredicable = 1; 1626} 1627 1628def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1629 (outs SPR:$Sd), (ins DPR:$Dm), 1630 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1631 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>, 1632 Sched<[WriteFPCVT]> { 1633 let Inst{7} = 0; // Z bit 1634} 1635 1636def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1637 (outs SPR:$Sd), (ins SPR:$Sm), 1638 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1639 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>, 1640 Sched<[WriteFPCVT]> { 1641 let Inst{7} = 0; // Z bit 1642} 1643 1644def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1645 (outs SPR:$Sd), (ins SPR:$Sm), 1646 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm", 1647 []>, 1648 Sched<[WriteFPCVT]> { 1649 let Inst{7} = 0; // Z bit 1650 let isUnpredicable = 1; 1651} 1652} 1653 1654// v8.3-a Javascript Convert to Signed fixed-point 1655def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, 1656 (outs SPR:$Sd), (ins DPR:$Dm), 1657 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm", 1658 []>, 1659 Requires<[HasFPARMv8, HasV8_3a]> { 1660 let Inst{7} = 1; // Z bit 1661} 1662 1663// Convert between floating-point and fixed-point 1664// Data type for fixed-point naming convention: 1665// S16 (U=0, sx=0) -> SH 1666// U16 (U=1, sx=0) -> UH 1667// S32 (U=0, sx=1) -> SL 1668// U32 (U=1, sx=1) -> UL 1669 1670let Constraints = "$a = $dst" in { 1671 1672// FP to Fixed-Point: 1673 1674// Single Precision register 1675class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1676 bit op5, dag oops, dag iops, InstrItinClass itin, 1677 string opc, string asm, list<dag> pattern> 1678 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1679 bits<5> dst; 1680 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1681 let Inst{22} = dst{0}; 1682 let Inst{15-12} = dst{4-1}; 1683} 1684 1685// Double Precision register 1686class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1687 bit op5, dag oops, dag iops, InstrItinClass itin, 1688 string opc, string asm, list<dag> pattern> 1689 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1690 bits<5> dst; 1691 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1692 let Inst{22} = dst{4}; 1693 let Inst{15-12} = dst{3-0}; 1694 1695 let Predicates = [HasVFP2, HasDPVFP]; 1696} 1697 1698let isUnpredicable = 1 in { 1699 1700def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1701 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1702 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>, 1703 Requires<[HasFullFP16]>, 1704 Sched<[WriteFPCVT]>; 1705 1706def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0, 1707 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1708 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>, 1709 Requires<[HasFullFP16]>, 1710 Sched<[WriteFPCVT]>; 1711 1712def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1713 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1714 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>, 1715 Requires<[HasFullFP16]>, 1716 Sched<[WriteFPCVT]>; 1717 1718def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1, 1719 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1720 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>, 1721 Requires<[HasFullFP16]>, 1722 Sched<[WriteFPCVT]>; 1723 1724} // End of 'let isUnpredicable = 1 in' 1725 1726def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1727 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1728 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>, 1729 Sched<[WriteFPCVT]> { 1730 // Some single precision VFP instructions may be executed on both NEON and 1731 // VFP pipelines on A8. 1732 let D = VFPNeonA8Domain; 1733} 1734 1735def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1736 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1737 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []>, 1738 Sched<[WriteFPCVT]> { 1739 // Some single precision VFP instructions may be executed on both NEON and 1740 // VFP pipelines on A8. 1741 let D = VFPNeonA8Domain; 1742} 1743 1744def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1745 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1746 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []>, 1747 Sched<[WriteFPCVT]> { 1748 // Some single precision VFP instructions may be executed on both NEON and 1749 // VFP pipelines on A8. 1750 let D = VFPNeonA8Domain; 1751} 1752 1753def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1754 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1755 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []>, 1756 Sched<[WriteFPCVT]> { 1757 // Some single precision VFP instructions may be executed on both NEON and 1758 // VFP pipelines on A8. 1759 let D = VFPNeonA8Domain; 1760} 1761 1762def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1763 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1764 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>, 1765 Sched<[WriteFPCVT]>; 1766 1767def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1768 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1769 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>, 1770 Sched<[WriteFPCVT]>; 1771 1772def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1773 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1774 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>, 1775 Sched<[WriteFPCVT]>; 1776 1777def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1778 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1779 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>, 1780 Sched<[WriteFPCVT]>; 1781 1782// Fixed-Point to FP: 1783 1784let isUnpredicable = 1 in { 1785 1786def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0, 1787 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1788 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>, 1789 Requires<[HasFullFP16]>, 1790 Sched<[WriteFPCVT]>; 1791 1792def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0, 1793 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1794 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>, 1795 Requires<[HasFullFP16]>, 1796 Sched<[WriteFPCVT]>; 1797 1798def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1, 1799 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1800 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>, 1801 Requires<[HasFullFP16]>, 1802 Sched<[WriteFPCVT]>; 1803 1804def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1, 1805 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1806 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>, 1807 Requires<[HasFullFP16]>, 1808 Sched<[WriteFPCVT]>; 1809 1810} // End of 'let isUnpredicable = 1 in' 1811 1812def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1813 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1814 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []>, 1815 Sched<[WriteFPCVT]> { 1816 // Some single precision VFP instructions may be executed on both NEON and 1817 // VFP pipelines on A8. 1818 let D = VFPNeonA8Domain; 1819} 1820 1821def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1822 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1823 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []>, 1824 Sched<[WriteFPCVT]> { 1825 // Some single precision VFP instructions may be executed on both NEON and 1826 // VFP pipelines on A8. 1827 let D = VFPNeonA8Domain; 1828} 1829 1830def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1831 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1832 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []>, 1833 Sched<[WriteFPCVT]> { 1834 // Some single precision VFP instructions may be executed on both NEON and 1835 // VFP pipelines on A8. 1836 let D = VFPNeonA8Domain; 1837} 1838 1839def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1840 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1841 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []>, 1842 Sched<[WriteFPCVT]> { 1843 // Some single precision VFP instructions may be executed on both NEON and 1844 // VFP pipelines on A8. 1845 let D = VFPNeonA8Domain; 1846} 1847 1848def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1849 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1850 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>, 1851 Sched<[WriteFPCVT]>; 1852 1853def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1854 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1855 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>, 1856 Sched<[WriteFPCVT]>; 1857 1858def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1859 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1860 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>, 1861 Sched<[WriteFPCVT]>; 1862 1863def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1864 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1865 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>, 1866 Sched<[WriteFPCVT]>; 1867 1868} // End of 'let Constraints = "$a = $dst" in' 1869 1870//===----------------------------------------------------------------------===// 1871// FP Multiply-Accumulate Operations. 1872// 1873 1874def VMLAD : ADbI<0b11100, 0b00, 0, 0, 1875 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1876 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 1877 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 1878 (f64 DPR:$Ddin)))]>, 1879 RegConstraint<"$Ddin = $Dd">, 1880 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 1881 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 1882 1883def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 1884 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1885 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 1886 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 1887 SPR:$Sdin))]>, 1888 RegConstraint<"$Sdin = $Sd">, 1889 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 1890 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 1891 // Some single precision VFP instructions may be executed on both NEON and 1892 // VFP pipelines on A8. 1893 let D = VFPNeonA8Domain; 1894} 1895 1896def VMLAH : AHbI<0b11100, 0b00, 0, 0, 1897 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 1898 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm", 1899 [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm), 1900 HPR:$Sdin))]>, 1901 RegConstraint<"$Sdin = $Sd">, 1902 Requires<[HasFullFP16,UseFPVMLx]>; 1903 1904def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1905 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1906 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 1907def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1908 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1909 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; 1910def : Pat<(fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)), 1911 (VMLAH HPR:$dstin, HPR:$a, HPR:$b)>, 1912 Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>; 1913 1914 1915def VMLSD : ADbI<0b11100, 0b00, 1, 0, 1916 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1917 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 1918 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1919 (f64 DPR:$Ddin)))]>, 1920 RegConstraint<"$Ddin = $Dd">, 1921 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 1922 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 1923 1924def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 1925 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1926 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 1927 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1928 SPR:$Sdin))]>, 1929 RegConstraint<"$Sdin = $Sd">, 1930 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 1931 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 1932 // Some single precision VFP instructions may be executed on both NEON and 1933 // VFP pipelines on A8. 1934 let D = VFPNeonA8Domain; 1935} 1936 1937def VMLSH : AHbI<0b11100, 0b00, 1, 0, 1938 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 1939 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm", 1940 [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), 1941 HPR:$Sdin))]>, 1942 RegConstraint<"$Sdin = $Sd">, 1943 Requires<[HasFullFP16,UseFPVMLx]>; 1944 1945def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 1946 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 1947 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 1948def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 1949 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 1950 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 1951def : Pat<(fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)), 1952 (VMLSH HPR:$dstin, HPR:$a, HPR:$b)>, 1953 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 1954 1955def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 1956 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 1957 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 1958 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 1959 (f64 DPR:$Ddin)))]>, 1960 RegConstraint<"$Ddin = $Dd">, 1961 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 1962 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 1963 1964def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 1965 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 1966 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 1967 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 1968 SPR:$Sdin))]>, 1969 RegConstraint<"$Sdin = $Sd">, 1970 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 1971 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 1972 // Some single precision VFP instructions may be executed on both NEON and 1973 // VFP pipelines on A8. 1974 let D = VFPNeonA8Domain; 1975} 1976 1977def VNMLAH : AHbI<0b11100, 0b01, 1, 0, 1978 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 1979 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm", 1980 [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), 1981 HPR:$Sdin))]>, 1982 RegConstraint<"$Sdin = $Sd">, 1983 Requires<[HasFullFP16,UseFPVMLx]>; 1984 1985// (-(a * b) - dst) -> -(dst + (a * b)) 1986def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 1987 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1988 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 1989def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 1990 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 1991 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 1992def : Pat<(fsub_mlx (fneg (fmul_su HPR:$a, HPR:$b)), HPR:$dstin), 1993 (VNMLAH HPR:$dstin, HPR:$a, HPR:$b)>, 1994 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 1995 1996// (-dst - (a * b)) -> -(dst + (a * b)) 1997def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))), 1998 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 1999 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2000def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)), 2001 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2002 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2003def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su HPR:$a, HPR:$b)), 2004 (VNMLAH HPR:$dstin, HPR:$a, HPR:$b)>, 2005 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2006 2007def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 2008 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2009 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 2010 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2011 (f64 DPR:$Ddin)))]>, 2012 RegConstraint<"$Ddin = $Dd">, 2013 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2014 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2015 2016def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 2017 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2018 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 2019 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2020 RegConstraint<"$Sdin = $Sd">, 2021 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2022 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2023 // Some single precision VFP instructions may be executed on both NEON and 2024 // VFP pipelines on A8. 2025 let D = VFPNeonA8Domain; 2026} 2027 2028def VNMLSH : AHbI<0b11100, 0b01, 0, 0, 2029 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2030 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm", 2031 [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))]>, 2032 RegConstraint<"$Sdin = $Sd">, 2033 Requires<[HasFullFP16,UseFPVMLx]>; 2034 2035def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2036 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2037 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2038def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2039 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2040 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2041def : Pat<(fsub_mlx (fmul_su HPR:$a, HPR:$b), HPR:$dstin), 2042 (VNMLSH HPR:$dstin, HPR:$a, HPR:$b)>, 2043 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2044 2045//===----------------------------------------------------------------------===// 2046// Fused FP Multiply-Accumulate Operations. 2047// 2048def VFMAD : ADbI<0b11101, 0b10, 0, 0, 2049 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2050 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 2051 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2052 (f64 DPR:$Ddin)))]>, 2053 RegConstraint<"$Ddin = $Dd">, 2054 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2055 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2056 2057def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 2058 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2059 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 2060 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2061 SPR:$Sdin))]>, 2062 RegConstraint<"$Sdin = $Sd">, 2063 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2064 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2065 // Some single precision VFP instructions may be executed on both NEON and 2066 // VFP pipelines. 2067} 2068 2069def VFMAH : AHbI<0b11101, 0b10, 0, 0, 2070 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2071 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm", 2072 [(set HPR:$Sd, (fadd_mlx (fmul_su HPR:$Sn, HPR:$Sm), 2073 HPR:$Sdin))]>, 2074 RegConstraint<"$Sdin = $Sd">, 2075 Requires<[HasFullFP16,UseFusedMAC]>, 2076 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2077 2078def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2079 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2080 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2081def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2082 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2083 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2084def : Pat<(fadd_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)), 2085 (VFMAH HPR:$dstin, HPR:$a, HPR:$b)>, 2086 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2087 2088// Match @llvm.fma.* intrinsics 2089// (fma x, y, z) -> (vfms z, x, y) 2090def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 2091 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2092 Requires<[HasVFP4,HasDPVFP]>; 2093def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 2094 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2095 Requires<[HasVFP4]>; 2096def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, HPR:$Sdin)), 2097 (VFMAH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2098 Requires<[HasFullFP16]>; 2099 2100def VFMSD : ADbI<0b11101, 0b10, 1, 0, 2101 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2102 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 2103 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2104 (f64 DPR:$Ddin)))]>, 2105 RegConstraint<"$Ddin = $Dd">, 2106 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2107 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2108 2109def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 2110 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2111 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 2112 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2113 SPR:$Sdin))]>, 2114 RegConstraint<"$Sdin = $Sd">, 2115 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2116 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2117 // Some single precision VFP instructions may be executed on both NEON and 2118 // VFP pipelines. 2119} 2120 2121def VFMSH : AHbI<0b11101, 0b10, 1, 0, 2122 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2123 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm", 2124 [(set HPR:$Sd, (fadd_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), 2125 HPR:$Sdin))]>, 2126 RegConstraint<"$Sdin = $Sd">, 2127 Requires<[HasFullFP16,UseFusedMAC]>, 2128 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2129 2130def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2131 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2132 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2133def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2134 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2135 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2136def : Pat<(fsub_mlx HPR:$dstin, (fmul_su HPR:$a, HPR:$b)), 2137 (VFMSH HPR:$dstin, HPR:$a, HPR:$b)>, 2138 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2139 2140// Match @llvm.fma.* intrinsics 2141// (fma (fneg x), y, z) -> (vfms z, x, y) 2142def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 2143 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2144 Requires<[HasVFP4,HasDPVFP]>; 2145def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 2146 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2147 Requires<[HasVFP4]>; 2148def : Pat<(f16 (fma (fneg HPR:$Sn), HPR:$Sm, HPR:$Sdin)), 2149 (VFMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2150 Requires<[HasFullFP16]>; 2151// (fma x, (fneg y), z) -> (vfms z, x, y) 2152def : Pat<(f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin)), 2153 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2154 Requires<[HasVFP4,HasDPVFP]>; 2155def : Pat<(f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin)), 2156 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2157 Requires<[HasVFP4]>; 2158def : Pat<(f16 (fma HPR:$Sn, (fneg HPR:$Sm), HPR:$Sdin)), 2159 (VFMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2160 Requires<[HasFullFP16]>; 2161 2162def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 2163 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2164 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 2165 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2166 (f64 DPR:$Ddin)))]>, 2167 RegConstraint<"$Ddin = $Dd">, 2168 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2169 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2170 2171def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 2172 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2173 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 2174 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2175 SPR:$Sdin))]>, 2176 RegConstraint<"$Sdin = $Sd">, 2177 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2178 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2179 // Some single precision VFP instructions may be executed on both NEON and 2180 // VFP pipelines. 2181} 2182 2183def VFNMAH : AHbI<0b11101, 0b01, 1, 0, 2184 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2185 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm", 2186 [(set HPR:$Sd, (fsub_mlx (fneg (fmul_su HPR:$Sn, HPR:$Sm)), 2187 HPR:$Sdin))]>, 2188 RegConstraint<"$Sdin = $Sd">, 2189 Requires<[HasFullFP16,UseFusedMAC]>, 2190 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2191 2192def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2193 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2194 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2195def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2196 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2197 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2198 2199// Match @llvm.fma.* intrinsics 2200// (fneg (fma x, y, z)) -> (vfnma z, x, y) 2201def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 2202 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2203 Requires<[HasVFP4,HasDPVFP]>; 2204def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 2205 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2206 Requires<[HasVFP4]>; 2207def : Pat<(fneg (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (f16 HPR:$Sdin))), 2208 (VFNMAH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2209 Requires<[HasFullFP16]>; 2210// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 2211def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 2212 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2213 Requires<[HasVFP4,HasDPVFP]>; 2214def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 2215 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2216 Requires<[HasVFP4]>; 2217def : Pat<(f16 (fma (fneg HPR:$Sn), HPR:$Sm, (fneg HPR:$Sdin))), 2218 (VFNMAH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2219 Requires<[HasFullFP16]>; 2220 2221def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 2222 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2223 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 2224 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2225 (f64 DPR:$Ddin)))]>, 2226 RegConstraint<"$Ddin = $Dd">, 2227 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2228 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2229 2230def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 2231 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2232 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 2233 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2234 RegConstraint<"$Sdin = $Sd">, 2235 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2236 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2237 // Some single precision VFP instructions may be executed on both NEON and 2238 // VFP pipelines. 2239} 2240 2241def VFNMSH : AHbI<0b11101, 0b01, 0, 0, 2242 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2243 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm", 2244 [(set HPR:$Sd, (fsub_mlx (fmul_su HPR:$Sn, HPR:$Sm), HPR:$Sdin))]>, 2245 RegConstraint<"$Sdin = $Sd">, 2246 Requires<[HasFullFP16,UseFusedMAC]>, 2247 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2248 2249def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2250 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2251 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2252def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2253 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2254 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2255 2256// Match @llvm.fma.* intrinsics 2257 2258// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 2259def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 2260 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2261 Requires<[HasVFP4,HasDPVFP]>; 2262def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 2263 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2264 Requires<[HasVFP4]>; 2265def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, (fneg HPR:$Sdin))), 2266 (VFNMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2267 Requires<[HasFullFP16]>; 2268// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 2269def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 2270 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2271 Requires<[HasVFP4,HasDPVFP]>; 2272def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 2273 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2274 Requires<[HasVFP4]>; 2275def : Pat<(fneg (f16 (fma (fneg HPR:$Sn), HPR:$Sm, HPR:$Sdin))), 2276 (VFNMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2277 Requires<[HasFullFP16]>; 2278// (fneg (fma x, (fneg y), z) -> (vfnms z, x, y) 2279def : Pat<(fneg (f64 (fma DPR:$Dn, (fneg DPR:$Dm), DPR:$Ddin))), 2280 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2281 Requires<[HasVFP4,HasDPVFP]>; 2282def : Pat<(fneg (f32 (fma SPR:$Sn, (fneg SPR:$Sm), SPR:$Sdin))), 2283 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2284 Requires<[HasVFP4]>; 2285def : Pat<(fneg (f16 (fma HPR:$Sn, (fneg HPR:$Sm), HPR:$Sdin))), 2286 (VFNMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>, 2287 Requires<[HasFullFP16]>; 2288 2289//===----------------------------------------------------------------------===// 2290// FP Conditional moves. 2291// 2292 2293let hasSideEffects = 0 in { 2294def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 2295 IIC_fpUNA64, 2296 [(set (f64 DPR:$Dd), 2297 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 2298 RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>; 2299 2300def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 2301 IIC_fpUNA32, 2302 [(set (f32 SPR:$Sd), 2303 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 2304 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>; 2305 2306def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p), 2307 IIC_fpUNA16, 2308 [(set (f16 HPR:$Sd), 2309 (ARMcmov HPR:$Sn, HPR:$Sm, cmovpred:$p))]>, 2310 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>; 2311} // hasSideEffects 2312 2313//===----------------------------------------------------------------------===// 2314// Move from VFP System Register to ARM core register. 2315// 2316 2317class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2318 list<dag> pattern>: 2319 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2320 2321 // Instruction operand. 2322 bits<4> Rt; 2323 2324 let Inst{27-20} = 0b11101111; 2325 let Inst{19-16} = opc19_16; 2326 let Inst{15-12} = Rt; 2327 let Inst{11-8} = 0b1010; 2328 let Inst{7} = 0; 2329 let Inst{6-5} = 0b00; 2330 let Inst{4} = 1; 2331 let Inst{3-0} = 0b0000; 2332 let Unpredictable{7-5} = 0b111; 2333 let Unpredictable{3-0} = 0b1111; 2334} 2335 2336let DecoderMethod = "DecodeForVMRSandVMSR" in { 2337 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 2338 // to APSR. 2339 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs], 2340 Rt = 0b1111 /* apsr_nzcv */ in 2341 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 2342 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 2343 2344 // Application level FPSCR -> GPR 2345 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in 2346 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins), 2347 "vmrs", "\t$Rt, fpscr", 2348 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>; 2349 2350 // System level FPEXC, FPSID -> GPR 2351 let Uses = [FPSCR] in { 2352 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins), 2353 "vmrs", "\t$Rt, fpexc", []>; 2354 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins), 2355 "vmrs", "\t$Rt, fpsid", []>; 2356 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins), 2357 "vmrs", "\t$Rt, mvfr0", []>; 2358 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins), 2359 "vmrs", "\t$Rt, mvfr1", []>; 2360 let Predicates = [HasFPARMv8] in { 2361 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins), 2362 "vmrs", "\t$Rt, mvfr2", []>; 2363 } 2364 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins), 2365 "vmrs", "\t$Rt, fpinst", []>; 2366 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt), 2367 (ins), "vmrs", "\t$Rt, fpinst2", []>; 2368 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2369 // System level FPSCR_NZCVQC -> GPR 2370 def VMRS_FPSCR_NZCVQC 2371 : MovFromVFP<0b0010 /* fpscr_nzcvqc */, 2372 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in), 2373 "vmrs", "\t$Rt, fpscr_nzcvqc", []>; 2374 } 2375 } 2376 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2377 // System level FPSCR -> GPR, with context saving for security extensions 2378 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2379 "vmrs", "\t$Rt, fpcxtns", []>; 2380 } 2381 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2382 // System level FPSCR -> GPR, with context saving for security extensions 2383 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins), 2384 "vmrs", "\t$Rt, fpcxts", []>; 2385 } 2386 2387 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2388 // System level VPR/P0 -> GPR 2389 let Uses = [VPR] in 2390 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins), 2391 "vmrs", "\t$Rt, vpr", []>; 2392 2393 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond), 2394 "vmrs", "\t$Rt, p0", []>; 2395 } 2396} 2397 2398//===----------------------------------------------------------------------===// 2399// Move from ARM core register to VFP System Register. 2400// 2401 2402class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2403 list<dag> pattern>: 2404 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2405 2406 // Instruction operand. 2407 bits<4> Rt; 2408 2409 let Inst{27-20} = 0b11101110; 2410 let Inst{19-16} = opc19_16; 2411 let Inst{15-12} = Rt; 2412 let Inst{11-8} = 0b1010; 2413 let Inst{7} = 0; 2414 let Inst{6-5} = 0b00; 2415 let Inst{4} = 1; 2416 let Inst{3-0} = 0b0000; 2417 let Predicates = [HasVFP2]; 2418 let Unpredictable{7-5} = 0b111; 2419 let Unpredictable{3-0} = 0b1111; 2420} 2421 2422let DecoderMethod = "DecodeForVMRSandVMSR" in { 2423 let Defs = [FPSCR] in { 2424 let Predicates = [HasFPRegs] in 2425 // Application level GPR -> FPSCR 2426 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt), 2427 "vmsr", "\tfpscr, $Rt", 2428 [(int_arm_set_fpscr GPRnopc:$Rt)]>; 2429 // System level GPR -> FPEXC 2430 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt), 2431 "vmsr", "\tfpexc, $Rt", []>; 2432 // System level GPR -> FPSID 2433 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt), 2434 "vmsr", "\tfpsid, $Rt", []>; 2435 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt), 2436 "vmsr", "\tfpinst, $Rt", []>; 2437 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt), 2438 "vmsr", "\tfpinst2, $Rt", []>; 2439 } 2440 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2441 // System level GPR -> FPSCR with context saving for security extensions 2442 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2443 "vmsr", "\tfpcxtns, $Rt", []>; 2444 } 2445 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2446 // System level GPR -> FPSCR with context saving for security extensions 2447 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt), 2448 "vmsr", "\tfpcxts, $Rt", []>; 2449 } 2450 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2451 // System level GPR -> FPSCR_NZCVQC 2452 def VMSR_FPSCR_NZCVQC 2453 : MovToVFP<0b0010 /* fpscr_nzcvqc */, 2454 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt), 2455 "vmsr", "\tfpscr_nzcvqc, $Rt", []>; 2456 } 2457 2458 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2459 // System level GPR -> VPR/P0 2460 let Defs = [VPR] in 2461 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt), 2462 "vmsr", "\tvpr, $Rt", []>; 2463 2464 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt), 2465 "vmsr", "\tp0, $Rt", []>; 2466 } 2467} 2468 2469//===----------------------------------------------------------------------===// 2470// Misc. 2471// 2472 2473// Materialize FP immediates. VFP3 only. 2474let isReMaterializable = 1 in { 2475def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 2476 VFPMiscFrm, IIC_fpUNA64, 2477 "vmov", ".f64\t$Dd, $imm", 2478 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 2479 Requires<[HasVFP3,HasDPVFP]> { 2480 bits<5> Dd; 2481 bits<8> imm; 2482 2483 let Inst{27-23} = 0b11101; 2484 let Inst{22} = Dd{4}; 2485 let Inst{21-20} = 0b11; 2486 let Inst{19-16} = imm{7-4}; 2487 let Inst{15-12} = Dd{3-0}; 2488 let Inst{11-9} = 0b101; 2489 let Inst{8} = 1; // Double precision. 2490 let Inst{7-4} = 0b0000; 2491 let Inst{3-0} = imm{3-0}; 2492} 2493 2494def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 2495 VFPMiscFrm, IIC_fpUNA32, 2496 "vmov", ".f32\t$Sd, $imm", 2497 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 2498 bits<5> Sd; 2499 bits<8> imm; 2500 2501 let Inst{27-23} = 0b11101; 2502 let Inst{22} = Sd{0}; 2503 let Inst{21-20} = 0b11; 2504 let Inst{19-16} = imm{7-4}; 2505 let Inst{15-12} = Sd{4-1}; 2506 let Inst{11-9} = 0b101; 2507 let Inst{8} = 0; // Single precision. 2508 let Inst{7-4} = 0b0000; 2509 let Inst{3-0} = imm{3-0}; 2510} 2511 2512def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm), 2513 VFPMiscFrm, IIC_fpUNA16, 2514 "vmov", ".f16\t$Sd, $imm", 2515 [(set HPR:$Sd, vfp_f16imm:$imm)]>, 2516 Requires<[HasFullFP16]> { 2517 bits<5> Sd; 2518 bits<8> imm; 2519 2520 let Inst{27-23} = 0b11101; 2521 let Inst{22} = Sd{0}; 2522 let Inst{21-20} = 0b11; 2523 let Inst{19-16} = imm{7-4}; 2524 let Inst{15-12} = Sd{4-1}; 2525 let Inst{11-8} = 0b1001; // Half precision 2526 let Inst{7-4} = 0b0000; 2527 let Inst{3-0} = imm{3-0}; 2528 2529 let isUnpredicable = 1; 2530} 2531} 2532 2533//===----------------------------------------------------------------------===// 2534// Assembler aliases. 2535// 2536// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 2537// support them all, but supporting at least some of the basics is 2538// good to be friendly. 2539def : VFP2MnemonicAlias<"flds", "vldr">; 2540def : VFP2MnemonicAlias<"fldd", "vldr">; 2541def : VFP2MnemonicAlias<"fmrs", "vmov">; 2542def : VFP2MnemonicAlias<"fmsr", "vmov">; 2543def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 2544def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 2545def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 2546def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 2547def : VFP2MnemonicAlias<"fmrdd", "vmov">; 2548def : VFP2MnemonicAlias<"fmrds", "vmov">; 2549def : VFP2MnemonicAlias<"fmrrd", "vmov">; 2550def : VFP2MnemonicAlias<"fmdrr", "vmov">; 2551def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 2552def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 2553def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 2554def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 2555def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 2556def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 2557def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 2558def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 2559def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 2560def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 2561def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 2562def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 2563def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 2564def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 2565def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 2566def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 2567def : VFP2MnemonicAlias<"fsts", "vstr">; 2568def : VFP2MnemonicAlias<"fstd", "vstr">; 2569def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 2570def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 2571def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 2572def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 2573def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 2574def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 2575def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 2576def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 2577def : VFP2MnemonicAlias<"fmrx", "vmrs">; 2578def : VFP2MnemonicAlias<"fmxr", "vmsr">; 2579 2580// Be friendly and accept the old form of zero-compare 2581def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 2582def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 2583 2584 2585def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>; 2586def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 2587 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2588def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 2589 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2590def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 2591 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2592def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 2593 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2594 2595// No need for the size suffix on VSQRT. It's implied by the register classes. 2596def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 2597def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 2598 2599// VLDR/VSTR accept an optional type suffix. 2600def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 2601 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2602def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 2603 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2604def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 2605 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2606def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 2607 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2608 2609// VMOV can accept optional 32-bit or less data type suffix suffix. 2610def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 2611 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2612def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 2613 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2614def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 2615 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2616def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 2617 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2618def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 2619 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2620def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 2621 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2622 2623def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 2624 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 2625def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 2626 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 2627 2628// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 2629// VMOVD does. 2630def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 2631 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 2632 2633// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 2634// These aliases provide added functionality over vmov.f instructions by 2635// allowing users to write assembly containing encoded floating point constants 2636// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 2637// assembler to accept encoded fp constants (but the equivalent fp-literal is 2638// accepted directly by vmovf). 2639def : VFP3InstAlias<"fconstd${p} $Dd, $val", 2640 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 2641def : VFP3InstAlias<"fconsts${p} $Sd, $val", 2642 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 2643 2644def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops), 2645 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2646 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2647 bits<13> regs; 2648 let Inst{31-23} = 0b111011001; 2649 let Inst{22} = regs{12}; 2650 let Inst{21-16} = 0b011111; 2651 let Inst{15-12} = regs{11-8}; 2652 let Inst{11-8} = 0b1011; 2653 let Inst{7-1} = regs{7-1}; 2654 let Inst{0} = 0; 2655 2656 let DecoderMethod = "DecodeVSCCLRM"; 2657 2658 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2659} 2660 2661def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops), 2662 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2663 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2664 bits<13> regs; 2665 let Inst{31-23} = 0b111011001; 2666 let Inst{22} = regs{8}; 2667 let Inst{21-16} = 0b011111; 2668 let Inst{15-12} = regs{12-9}; 2669 let Inst{11-8} = 0b1010; 2670 let Inst{7-0} = regs{7-0}; 2671 2672 let DecoderMethod = "DecodeVSCCLRM"; 2673 2674 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2675} 2676 2677//===----------------------------------------------------------------------===// 2678// Store VFP System Register to memory. 2679// 2680 2681class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg, 2682 dag oops, dag iops, IndexMode im, string Dest, string cstr> 2683 : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT, 2684 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>, 2685 Sched<[]> { 2686 bits<12> addr; 2687 let Inst{27-25} = 0b110; 2688 let Inst{24} = P; 2689 let Inst{23} = addr{7}; 2690 let Inst{22} = SysReg{3}; 2691 let Inst{21} = W; 2692 let Inst{20} = opc; 2693 let Inst{19-16} = addr{11-8}; 2694 let Inst{15-13} = SysReg{2-0}; 2695 let Inst{12-7} = 0b011111; 2696 let Inst{6-0} = addr{6-0}; 2697 list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline]; 2698 let mayLoad = opc; 2699 let mayStore = !if(opc, 0b0, 0b1); 2700 let hasSideEffects = 1; 2701} 2702 2703multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg, 2704 dag oops=(outs), dag iops=(ins)> { 2705 def _off : 2706 vfp_vstrldr<opc, 1, 0, SysReg, sysreg, 2707 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)), 2708 IndexModePost, "$addr", "" > { 2709 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<false>"; 2710 } 2711 2712 def _pre : 2713 vfp_vstrldr<opc, 1, 1, SysReg, sysreg, 2714 !con(oops, (outs GPRnopc:$wb)), 2715 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)), 2716 IndexModePre, "$addr!", "$addr.base = $wb"> { 2717 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2718 } 2719 2720 def _post : 2721 vfp_vstrldr<opc, 0, 1, SysReg, sysreg, 2722 !con(oops, (outs GPRnopc:$wb)), 2723 !con(iops, (ins t2_addr_offset_none:$Rn, 2724 t2am_imm7s4_offset:$addr)), 2725 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> { 2726 bits<4> Rn; 2727 let Inst{19-16} = Rn{3-0}; 2728 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2729 } 2730} 2731 2732let Defs = [FPSCR] in { 2733 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">; 2734 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">; 2735 2736 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2737 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2738 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">; 2739 } 2740} 2741 2742let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2743 let Uses = [VPR] in { 2744 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">; 2745 } 2746 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0", 2747 (outs), (ins VCCR:$P0)>; 2748} 2749 2750let Uses = [FPSCR] in { 2751 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">; 2752 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">; 2753 2754 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2755 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">; 2756 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">; 2757 } 2758} 2759 2760let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2761 let Defs = [VPR] in { 2762 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; 2763 } 2764 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", 2765 (outs VCCR:$P0), (ins)>; 2766} 2767