1//===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the ARM VFP instruction set. 10// 11//===----------------------------------------------------------------------===// 12 13def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 14def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, 15 SDTCisSameAs<1, 2>]>; 16def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 17 SDTCisVT<2, f64>]>; 18 19def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>; 20 21def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>; 22def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>; 23def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>; 24def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>; 25def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>; 26def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>; 27def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>; 28def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>; 29 30def SDT_VMOVhr : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, i32>] >; 31def SDT_VMOVrh : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisFP<1>] >; 32def arm_vmovhr : SDNode<"ARMISD::VMOVhr", SDT_VMOVhr>; 33def arm_vmovrh : SDNode<"ARMISD::VMOVrh", SDT_VMOVrh>; 34 35//===----------------------------------------------------------------------===// 36// Operand Definitions. 37// 38 39// 8-bit floating-point immediate encodings. 40def FPImmOperand : AsmOperandClass { 41 let Name = "FPImm"; 42 let ParserMethod = "parseFPImm"; 43} 44 45def vfp_f16imm : Operand<f16>, 46 PatLeaf<(f16 fpimm), [{ 47 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1; 48 }], SDNodeXForm<fpimm, [{ 49 APFloat InVal = N->getValueAPF(); 50 uint32_t enc = ARM_AM::getFP16Imm(InVal); 51 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 52 }]>> { 53 let PrintMethod = "printFPImmOperand"; 54 let ParserMatchClass = FPImmOperand; 55} 56 57def vfp_f32f16imm_xform : SDNodeXForm<fpimm, [{ 58 APFloat InVal = N->getValueAPF(); 59 uint32_t enc = ARM_AM::getFP32FP16Imm(InVal); 60 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 61 }]>; 62 63def vfp_f32f16imm : PatLeaf<(f32 fpimm), [{ 64 return ARM_AM::getFP32FP16Imm(N->getValueAPF()) != -1; 65 }], vfp_f32f16imm_xform>; 66 67def vfp_f32imm_xform : SDNodeXForm<fpimm, [{ 68 APFloat InVal = N->getValueAPF(); 69 uint32_t enc = ARM_AM::getFP32Imm(InVal); 70 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 71 }]>; 72 73def gi_vfp_f32imm : GICustomOperandRenderer<"renderVFPF32Imm">, 74 GISDNodeXFormEquiv<vfp_f32imm_xform>; 75 76def vfp_f32imm : Operand<f32>, 77 PatLeaf<(f32 fpimm), [{ 78 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1; 79 }], vfp_f32imm_xform> { 80 let PrintMethod = "printFPImmOperand"; 81 let ParserMatchClass = FPImmOperand; 82 let GISelPredicateCode = [{ 83 const auto &MO = MI.getOperand(1); 84 if (!MO.isFPImm()) 85 return false; 86 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; 87 }]; 88} 89 90def vfp_f64imm_xform : SDNodeXForm<fpimm, [{ 91 APFloat InVal = N->getValueAPF(); 92 uint32_t enc = ARM_AM::getFP64Imm(InVal); 93 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32); 94 }]>; 95 96def gi_vfp_f64imm : GICustomOperandRenderer<"renderVFPF64Imm">, 97 GISDNodeXFormEquiv<vfp_f64imm_xform>; 98 99def vfp_f64imm : Operand<f64>, 100 PatLeaf<(f64 fpimm), [{ 101 return ARM_AM::getFP64Imm(N->getValueAPF()) != -1; 102 }], vfp_f64imm_xform> { 103 let PrintMethod = "printFPImmOperand"; 104 let ParserMatchClass = FPImmOperand; 105 let GISelPredicateCode = [{ 106 const auto &MO = MI.getOperand(1); 107 if (!MO.isFPImm()) 108 return false; 109 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; 110 }]; 111} 112 113def alignedload16 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 114 return cast<LoadSDNode>(N)->getAlignment() >= 2; 115}]>; 116 117def alignedload32 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 118 return cast<LoadSDNode>(N)->getAlignment() >= 4; 119}]>; 120 121def alignedstore16 : PatFrag<(ops node:$val, node:$ptr), 122 (store node:$val, node:$ptr), [{ 123 return cast<StoreSDNode>(N)->getAlignment() >= 2; 124}]>; 125 126def alignedstore32 : PatFrag<(ops node:$val, node:$ptr), 127 (store node:$val, node:$ptr), [{ 128 return cast<StoreSDNode>(N)->getAlignment() >= 4; 129}]>; 130 131// The VCVT to/from fixed-point instructions encode the 'fbits' operand 132// (the number of fixed bits) differently than it appears in the assembly 133// source. It's encoded as "Size - fbits" where Size is the size of the 134// fixed-point representation (32 or 16) and fbits is the value appearing 135// in the assembly source, an integer in [0,16] or (0,32], depending on size. 136def fbits32_asm_operand : AsmOperandClass { let Name = "FBits32"; } 137def fbits32 : Operand<i32> { 138 let PrintMethod = "printFBits32"; 139 let ParserMatchClass = fbits32_asm_operand; 140} 141 142def fbits16_asm_operand : AsmOperandClass { let Name = "FBits16"; } 143def fbits16 : Operand<i32> { 144 let PrintMethod = "printFBits16"; 145 let ParserMatchClass = fbits16_asm_operand; 146} 147 148//===----------------------------------------------------------------------===// 149// Load / store Instructions. 150// 151 152let canFoldAsLoad = 1, isReMaterializable = 1 in { 153 154def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr), 155 IIC_fpLoad64, "vldr", "\t$Dd, $addr", 156 [(set DPR:$Dd, (f64 (alignedload32 addrmode5:$addr)))]>, 157 Requires<[HasFPRegs]>; 158 159def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr), 160 IIC_fpLoad32, "vldr", "\t$Sd, $addr", 161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>, 162 Requires<[HasFPRegs]> { 163 // Some single precision VFP instructions may be executed on both NEON and VFP 164 // pipelines. 165 let D = VFPNeonDomain; 166} 167 168let isUnpredicable = 1 in 169def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr), 170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr", 171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>, 172 Requires<[HasFPRegs16]>; 173 174} // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in' 175 176def : Pat<(bf16 (alignedload16 addrmode5fp16:$addr)), 177 (VLDRH addrmode5fp16:$addr)> { 178 let Predicates = [HasFPRegs16]; 179} 180def : Pat<(bf16 (alignedload16 addrmode3:$addr)), 181 (COPY_TO_REGCLASS (LDRH addrmode3:$addr), HPR)> { 182 let Predicates = [HasNoFPRegs16, IsARM]; 183} 184def : Pat<(bf16 (alignedload16 t2addrmode_imm12:$addr)), 185 (COPY_TO_REGCLASS (t2LDRHi12 t2addrmode_imm12:$addr), HPR)> { 186 let Predicates = [HasNoFPRegs16, IsThumb]; 187} 188 189def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr), 190 IIC_fpStore64, "vstr", "\t$Dd, $addr", 191 [(alignedstore32 (f64 DPR:$Dd), addrmode5:$addr)]>, 192 Requires<[HasFPRegs]>; 193 194def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr), 195 IIC_fpStore32, "vstr", "\t$Sd, $addr", 196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>, 197 Requires<[HasFPRegs]> { 198 // Some single precision VFP instructions may be executed on both NEON and VFP 199 // pipelines. 200 let D = VFPNeonDomain; 201} 202 203let isUnpredicable = 1 in 204def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr), 205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr", 206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>, 207 Requires<[HasFPRegs16]>; 208 209def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr), 210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> { 211 let Predicates = [HasFPRegs16]; 212} 213def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr), 214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> { 215 let Predicates = [HasNoFPRegs16, IsARM]; 216} 217def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr), 218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> { 219 let Predicates = [HasNoFPRegs16, IsThumb]; 220} 221 222//===----------------------------------------------------------------------===// 223// Load / store multiple Instructions. 224// 225 226multiclass vfp_ldst_mult<string asm, bit L_bit, 227 InstrItinClass itin, InstrItinClass itin_upd> { 228 let Predicates = [HasFPRegs] in { 229 // Double Precision 230 def DIA : 231 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 232 IndexModeNone, itin, 233 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 234 let Inst{24-23} = 0b01; // Increment After 235 let Inst{21} = 0; // No writeback 236 let Inst{20} = L_bit; 237 } 238 def DIA_UPD : 239 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 240 variable_ops), 241 IndexModeUpd, itin_upd, 242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 243 let Inst{24-23} = 0b01; // Increment After 244 let Inst{21} = 1; // Writeback 245 let Inst{20} = L_bit; 246 } 247 def DDB_UPD : 248 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, 249 variable_ops), 250 IndexModeUpd, itin_upd, 251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 252 let Inst{24-23} = 0b10; // Decrement Before 253 let Inst{21} = 1; // Writeback 254 let Inst{20} = L_bit; 255 } 256 257 // Single Precision 258 def SIA : 259 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops), 260 IndexModeNone, itin, 261 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> { 262 let Inst{24-23} = 0b01; // Increment After 263 let Inst{21} = 0; // No writeback 264 let Inst{20} = L_bit; 265 266 // Some single precision VFP instructions may be executed on both NEON and 267 // VFP pipelines. 268 let D = VFPNeonDomain; 269 } 270 def SIA_UPD : 271 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 272 variable_ops), 273 IndexModeUpd, itin_upd, 274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 275 let Inst{24-23} = 0b01; // Increment After 276 let Inst{21} = 1; // Writeback 277 let Inst{20} = L_bit; 278 279 // Some single precision VFP instructions may be executed on both NEON and 280 // VFP pipelines. 281 let D = VFPNeonDomain; 282 } 283 def SDB_UPD : 284 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, 285 variable_ops), 286 IndexModeUpd, itin_upd, 287 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 288 let Inst{24-23} = 0b10; // Decrement Before 289 let Inst{21} = 1; // Writeback 290 let Inst{20} = L_bit; 291 292 // Some single precision VFP instructions may be executed on both NEON and 293 // VFP pipelines. 294 let D = VFPNeonDomain; 295 } 296 } 297} 298 299let hasSideEffects = 0 in { 300 301let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 302defm VLDM : vfp_ldst_mult<"vldm", 1, IIC_fpLoad_m, IIC_fpLoad_mu>; 303 304let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 305defm VSTM : vfp_ldst_mult<"vstm", 0, IIC_fpStore_m, IIC_fpStore_mu>; 306 307} // hasSideEffects 308 309def : MnemonicAlias<"vldm", "vldmia">; 310def : MnemonicAlias<"vstm", "vstmia">; 311 312 313//===----------------------------------------------------------------------===// 314// Lazy load / store multiple Instructions 315// 316def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 317 NoItinerary, "vlldm${p}\t$Rn", "", []>, 318 Requires<[HasV8MMainline, Has8MSecExt]> { 319 let Inst{24-23} = 0b00; 320 let Inst{22} = 0; 321 let Inst{21} = 1; 322 let Inst{20} = 1; 323 let Inst{15-12} = 0; 324 let Inst{7-0} = 0; 325 let mayLoad = 1; 326 let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV]; 327} 328 329def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone, 330 NoItinerary, "vlstm${p}\t$Rn", "", []>, 331 Requires<[HasV8MMainline, Has8MSecExt]> { 332 let Inst{24-23} = 0b00; 333 let Inst{22} = 0; 334 let Inst{21} = 1; 335 let Inst{20} = 0; 336 let Inst{15-12} = 0; 337 let Inst{7-0} = 0; 338 let mayStore = 1; 339} 340 341def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>, 342 Requires<[HasFPRegs]>; 343def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>, 344 Requires<[HasFPRegs]>; 345def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>, 346 Requires<[HasFPRegs]>; 347def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>, 348 Requires<[HasFPRegs]>; 349defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 350 (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>; 351defm : VFPDTAnyInstAlias<"vpush${p}", "$r", 352 (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>; 353defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 354 (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>; 355defm : VFPDTAnyInstAlias<"vpop${p}", "$r", 356 (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>; 357 358// FLDMX, FSTMX - Load and store multiple unknown precision registers for 359// pre-armv6 cores. 360// These instruction are deprecated so we don't want them to get selected. 361// However, there is no UAL syntax for them, so we keep them around for 362// (dis)assembly only. 363multiclass vfp_ldstx_mult<string asm, bit L_bit> { 364 let Predicates = [HasFPRegs], hasNoSchedulingInfo = 1 in { 365 // Unknown precision 366 def XIA : 367 AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 368 IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> { 369 let Inst{24-23} = 0b01; // Increment After 370 let Inst{21} = 0; // No writeback 371 let Inst{20} = L_bit; 372 } 373 def XIA_UPD : 374 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 375 IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 376 let Inst{24-23} = 0b01; // Increment After 377 let Inst{21} = 1; // Writeback 378 let Inst{20} = L_bit; 379 } 380 def XDB_UPD : 381 AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops), 382 IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 383 let Inst{24-23} = 0b10; // Decrement Before 384 let Inst{21} = 1; // Writeback 385 let Inst{20} = L_bit; 386 } 387 } 388} 389 390defm FLDM : vfp_ldstx_mult<"fldm", 1>; 391defm FSTM : vfp_ldstx_mult<"fstm", 0>; 392 393def : VFP2MnemonicAlias<"fldmeax", "fldmdbx">; 394def : VFP2MnemonicAlias<"fldmfdx", "fldmiax">; 395 396def : VFP2MnemonicAlias<"fstmeax", "fstmiax">; 397def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; 398 399//===----------------------------------------------------------------------===// 400// FP Binary Operations. 401// 402 403let TwoOperandAliasConstraint = "$Dn = $Dd" in 404def VADDD : ADbI<0b11100, 0b11, 0, 0, 405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 406 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", 407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, 408 Sched<[WriteFPALU64]>; 409 410let TwoOperandAliasConstraint = "$Sn = $Sd" in 411def VADDS : ASbIn<0b11100, 0b11, 0, 0, 412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 413 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 415 Sched<[WriteFPALU32]> { 416 // Some single precision VFP instructions may be executed on both NEON and 417 // VFP pipelines on A8. 418 let D = VFPNeonA8Domain; 419} 420 421let TwoOperandAliasConstraint = "$Sn = $Sd" in 422def VADDH : AHbI<0b11100, 0b11, 0, 0, 423 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 424 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", 425 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 426 Sched<[WriteFPALU32]>; 427 428let TwoOperandAliasConstraint = "$Dn = $Dd" in 429def VSUBD : ADbI<0b11100, 0b11, 1, 0, 430 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 431 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 432 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, 433 Sched<[WriteFPALU64]>; 434 435let TwoOperandAliasConstraint = "$Sn = $Sd" in 436def VSUBS : ASbIn<0b11100, 0b11, 1, 0, 437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>, 440 Sched<[WriteFPALU32]>{ 441 // Some single precision VFP instructions may be executed on both NEON and 442 // VFP pipelines on A8. 443 let D = VFPNeonA8Domain; 444} 445 446let TwoOperandAliasConstraint = "$Sn = $Sd" in 447def VSUBH : AHbI<0b11100, 0b11, 1, 0, 448 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 449 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm", 450 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 451 Sched<[WriteFPALU32]>; 452 453let TwoOperandAliasConstraint = "$Dn = $Dd" in 454def VDIVD : ADbI<0b11101, 0b00, 0, 0, 455 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 456 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", 457 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, 458 Sched<[WriteFPDIV64]>; 459 460let TwoOperandAliasConstraint = "$Sn = $Sd" in 461def VDIVS : ASbI<0b11101, 0b00, 0, 0, 462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 463 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", 464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, 465 Sched<[WriteFPDIV32]>; 466 467let TwoOperandAliasConstraint = "$Sn = $Sd" in 468def VDIVH : AHbI<0b11101, 0b00, 0, 0, 469 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 470 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", 471 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 472 Sched<[WriteFPDIV32]>; 473 474let TwoOperandAliasConstraint = "$Dn = $Dd" in 475def VMULD : ADbI<0b11100, 0b10, 0, 0, 476 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 477 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", 478 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>, 479 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 480 481let TwoOperandAliasConstraint = "$Sn = $Sd" in 482def VMULS : ASbIn<0b11100, 0b10, 0, 0, 483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 484 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", 485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>, 486 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 487 // Some single precision VFP instructions may be executed on both NEON and 488 // VFP pipelines on A8. 489 let D = VFPNeonA8Domain; 490} 491 492let TwoOperandAliasConstraint = "$Sn = $Sd" in 493def VMULH : AHbI<0b11100, 0b10, 0, 0, 494 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 495 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", 496 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 497 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 498 499def VNMULD : ADbI<0b11100, 0b10, 1, 0, 500 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 501 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", 502 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, 503 Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; 504 505def VNMULS : ASbI<0b11100, 0b10, 1, 0, 506 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 507 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", 508 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>, 509 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]> { 510 // Some single precision VFP instructions may be executed on both NEON and 511 // VFP pipelines on A8. 512 let D = VFPNeonA8Domain; 513} 514 515def VNMULH : AHbI<0b11100, 0b10, 1, 0, 516 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 517 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", 518 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>, 519 Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; 520 521multiclass vsel_inst<string op, bits<2> opc, int CC> { 522 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 523 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in { 524 def H : AHbInp<0b11100, opc, 0, 525 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 526 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), 527 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>, 528 Requires<[HasFullFP16]>; 529 530 def S : ASbInp<0b11100, opc, 0, 531 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 532 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"), 533 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>, 534 Requires<[HasFPARMv8]>; 535 536 def D : ADbInp<0b11100, opc, 0, 537 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 538 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"), 539 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>, 540 Requires<[HasFPARMv8, HasDPVFP]>; 541 } 542} 543 544// The CC constants here match ARMCC::CondCodes. 545defm VSELGT : vsel_inst<"gt", 0b11, 12>; 546defm VSELGE : vsel_inst<"ge", 0b10, 10>; 547defm VSELEQ : vsel_inst<"eq", 0b00, 0>; 548defm VSELVS : vsel_inst<"vs", 0b01, 6>; 549 550multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { 551 let DecoderNamespace = "VFPV8", PostEncoderMethod = "", 552 isUnpredicable = 1 in { 553 def H : AHbInp<0b11101, 0b00, opc, 554 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 555 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), 556 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 557 Requires<[HasFullFP16]>; 558 559 def S : ASbInp<0b11101, 0b00, opc, 560 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 561 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"), 562 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>, 563 Requires<[HasFPARMv8]>; 564 565 def D : ADbInp<0b11101, 0b00, opc, 566 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), 567 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"), 568 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>, 569 Requires<[HasFPARMv8, HasDPVFP]>; 570 } 571} 572 573defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; 574defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; 575 576// Match reassociated forms only if not sign dependent rounding. 577def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), 578 (VNMULD DPR:$a, DPR:$b)>, 579 Requires<[NoHonorSignDependentRounding,HasDPVFP]>; 580def : Pat<(fmul (fneg SPR:$a), SPR:$b), 581 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; 582 583// These are encoded as unary instructions. 584let Defs = [FPSCR_NZCV] in { 585def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, 586 (outs), (ins DPR:$Dd, DPR:$Dm), 587 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", 588 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>; 589 590def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0, 591 (outs), (ins SPR:$Sd, SPR:$Sm), 592 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", 593 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> { 594 // Some single precision VFP instructions may be executed on both NEON and 595 // VFP pipelines on A8. 596 let D = VFPNeonA8Domain; 597} 598 599def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0, 600 (outs), (ins HPR:$Sd, HPR:$Sm), 601 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm", 602 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 603 604def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, 605 (outs), (ins DPR:$Dd, DPR:$Dm), 606 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", 607 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>; 608 609def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, 610 (outs), (ins SPR:$Sd, SPR:$Sm), 611 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", 612 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> { 613 // Some single precision VFP instructions may be executed on both NEON and 614 // VFP pipelines on A8. 615 let D = VFPNeonA8Domain; 616} 617 618def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0, 619 (outs), (ins HPR:$Sd, HPR:$Sm), 620 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm", 621 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>; 622} // Defs = [FPSCR_NZCV] 623 624//===----------------------------------------------------------------------===// 625// FP Unary Operations. 626// 627 628def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, 629 (outs DPR:$Dd), (ins DPR:$Dm), 630 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm", 631 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>; 632 633def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0, 634 (outs SPR:$Sd), (ins SPR:$Sm), 635 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm", 636 [(set SPR:$Sd, (fabs SPR:$Sm))]> { 637 // Some single precision VFP instructions may be executed on both NEON and 638 // VFP pipelines on A8. 639 let D = VFPNeonA8Domain; 640} 641 642def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0, 643 (outs HPR:$Sd), (ins HPR:$Sm), 644 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm", 645 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>; 646 647let Defs = [FPSCR_NZCV] in { 648def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, 649 (outs), (ins DPR:$Dd), 650 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", 651 [(arm_cmpfpe0 (f64 DPR:$Dd))]> { 652 let Inst{3-0} = 0b0000; 653 let Inst{5} = 0; 654} 655 656def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, 657 (outs), (ins SPR:$Sd), 658 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", 659 [(arm_cmpfpe0 SPR:$Sd)]> { 660 let Inst{3-0} = 0b0000; 661 let Inst{5} = 0; 662 663 // Some single precision VFP instructions may be executed on both NEON and 664 // VFP pipelines on A8. 665 let D = VFPNeonA8Domain; 666} 667 668def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, 669 (outs), (ins HPR:$Sd), 670 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0", 671 [(arm_cmpfpe0 (f16 HPR:$Sd))]> { 672 let Inst{3-0} = 0b0000; 673 let Inst{5} = 0; 674} 675 676def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, 677 (outs), (ins DPR:$Dd), 678 IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", 679 [(arm_cmpfp0 (f64 DPR:$Dd))]> { 680 let Inst{3-0} = 0b0000; 681 let Inst{5} = 0; 682} 683 684def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, 685 (outs), (ins SPR:$Sd), 686 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", 687 [(arm_cmpfp0 SPR:$Sd)]> { 688 let Inst{3-0} = 0b0000; 689 let Inst{5} = 0; 690 691 // Some single precision VFP instructions may be executed on both NEON and 692 // VFP pipelines on A8. 693 let D = VFPNeonA8Domain; 694} 695 696def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, 697 (outs), (ins HPR:$Sd), 698 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0", 699 [(arm_cmpfp0 (f16 HPR:$Sd))]> { 700 let Inst{3-0} = 0b0000; 701 let Inst{5} = 0; 702} 703} // Defs = [FPSCR_NZCV] 704 705def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, 706 (outs DPR:$Dd), (ins SPR:$Sm), 707 IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", 708 [(set DPR:$Dd, (fpextend SPR:$Sm))]>, 709 Sched<[WriteFPCVT]> { 710 // Instruction operands. 711 bits<5> Dd; 712 bits<5> Sm; 713 714 // Encode instruction operands. 715 let Inst{3-0} = Sm{4-1}; 716 let Inst{5} = Sm{0}; 717 let Inst{15-12} = Dd{3-0}; 718 let Inst{22} = Dd{4}; 719 720 let Predicates = [HasVFP2, HasDPVFP]; 721 let hasSideEffects = 0; 722} 723 724// Special case encoding: bits 11-8 is 0b1011. 725def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, 726 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", 727 [(set SPR:$Sd, (fpround DPR:$Dm))]>, 728 Sched<[WriteFPCVT]> { 729 // Instruction operands. 730 bits<5> Sd; 731 bits<5> Dm; 732 733 // Encode instruction operands. 734 let Inst{3-0} = Dm{3-0}; 735 let Inst{5} = Dm{4}; 736 let Inst{15-12} = Sd{4-1}; 737 let Inst{22} = Sd{0}; 738 739 let Inst{27-23} = 0b11101; 740 let Inst{21-16} = 0b110111; 741 let Inst{11-8} = 0b1011; 742 let Inst{7-6} = 0b11; 743 let Inst{4} = 0; 744 745 let Predicates = [HasVFP2, HasDPVFP]; 746 let hasSideEffects = 0; 747} 748 749// Between half, single and double-precision. 750let hasSideEffects = 0 in 751def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 752 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", 753 [/* Intentionally left blank, see patterns below */]>, 754 Requires<[HasFP16]>, 755 Sched<[WriteFPCVT]>; 756 757def : FP16Pat<(f32 (fpextend (f16 HPR:$Sm))), 758 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>; 759def : FP16Pat<(f16_to_fp GPR:$a), 760 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; 761 762let hasSideEffects = 0 in 763def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), 764 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", 765 [/* Intentionally left blank, see patterns below */]>, 766 Requires<[HasFP16]>, 767 Sched<[WriteFPCVT]>; 768 769def : FP16Pat<(f16 (fpround SPR:$Sm)), 770 (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>; 771def : FP16Pat<(fp_to_f16 SPR:$a), 772 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; 773def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 774 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2), 775 (SSubReg_f16_reg imm:$lane)))>; 776def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane), 777 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2), 778 (SSubReg_f16_reg imm:$lane)))>; 779 780let hasSideEffects = 0 in 781def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 782 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", 783 [/* Intentionally left blank, see patterns below */]>, 784 Requires<[HasFP16]>, 785 Sched<[WriteFPCVT]>; 786 787def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))), 788 (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>; 789def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))), 790 (VCVTTHS (EXTRACT_SUBREG 791 (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)), 792 (SSubReg_f16_reg imm_odd:$lane)))>; 793 794let hasSideEffects = 0 in 795def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), 796 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", 797 [/* Intentionally left blank, see patterns below */]>, 798 Requires<[HasFP16]>, 799 Sched<[WriteFPCVT]>; 800 801def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 802 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2), 803 (SSubReg_f16_reg imm:$lane)))>; 804def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane), 805 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2), 806 (SSubReg_f16_reg imm:$lane)))>; 807 808def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, 809 (outs DPR:$Dd), (ins SPR:$Sm), 810 NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", 811 [/* Intentionally left blank, see patterns below */]>, 812 Requires<[HasFPARMv8, HasDPVFP]>, 813 Sched<[WriteFPCVT]> { 814 // Instruction operands. 815 bits<5> Sm; 816 817 // Encode instruction operands. 818 let Inst{3-0} = Sm{4-1}; 819 let Inst{5} = Sm{0}; 820 821 let hasSideEffects = 0; 822} 823 824def : FullFP16Pat<(f64 (fpextend (f16 HPR:$Sm))), 825 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>, 826 Requires<[HasFPARMv8, HasDPVFP]>; 827def : FP16Pat<(f64 (f16_to_fp GPR:$a)), 828 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>, 829 Requires<[HasFPARMv8, HasDPVFP]>; 830 831def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, 832 (outs SPR:$Sd), (ins DPR:$Dm), 833 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", 834 [/* Intentionally left blank, see patterns below */]>, 835 Requires<[HasFPARMv8, HasDPVFP]> { 836 // Instruction operands. 837 bits<5> Sd; 838 bits<5> Dm; 839 840 // Encode instruction operands. 841 let Inst{3-0} = Dm{3-0}; 842 let Inst{5} = Dm{4}; 843 let Inst{15-12} = Sd{4-1}; 844 let Inst{22} = Sd{0}; 845 846 let hasSideEffects = 0; 847} 848 849def : FullFP16Pat<(f16 (fpround DPR:$Dm)), 850 (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>, 851 Requires<[HasFPARMv8, HasDPVFP]>; 852def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), 853 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>, 854 Requires<[HasFPARMv8, HasDPVFP]>; 855 856def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, 857 (outs DPR:$Dd), (ins SPR:$Sm), 858 NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", 859 []>, Requires<[HasFPARMv8, HasDPVFP]> { 860 // Instruction operands. 861 bits<5> Sm; 862 863 // Encode instruction operands. 864 let Inst{3-0} = Sm{4-1}; 865 let Inst{5} = Sm{0}; 866 867 let hasSideEffects = 0; 868} 869 870def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, 871 (outs SPR:$Sd), (ins DPR:$Dm), 872 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", 873 []>, Requires<[HasFPARMv8, HasDPVFP]> { 874 // Instruction operands. 875 bits<5> Sd; 876 bits<5> Dm; 877 878 // Encode instruction operands. 879 let Inst{15-12} = Sd{4-1}; 880 let Inst{22} = Sd{0}; 881 let Inst{3-0} = Dm{3-0}; 882 let Inst{5} = Dm{4}; 883 884 let hasSideEffects = 0; 885} 886 887multiclass vcvt_inst<string opc, bits<2> rm, 888 SDPatternOperator node = null_frag> { 889 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0 in { 890 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0, 891 (outs SPR:$Sd), (ins HPR:$Sm), 892 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"), 893 []>, 894 Requires<[HasFullFP16]> { 895 let Inst{17-16} = rm; 896 } 897 898 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0, 899 (outs SPR:$Sd), (ins HPR:$Sm), 900 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"), 901 []>, 902 Requires<[HasFullFP16]> { 903 let Inst{17-16} = rm; 904 } 905 906 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 907 (outs SPR:$Sd), (ins SPR:$Sm), 908 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"), 909 []>, 910 Requires<[HasFPARMv8]> { 911 let Inst{17-16} = rm; 912 } 913 914 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 915 (outs SPR:$Sd), (ins SPR:$Sm), 916 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"), 917 []>, 918 Requires<[HasFPARMv8]> { 919 let Inst{17-16} = rm; 920 } 921 922 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0, 923 (outs SPR:$Sd), (ins DPR:$Dm), 924 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"), 925 []>, 926 Requires<[HasFPARMv8, HasDPVFP]> { 927 bits<5> Dm; 928 929 let Inst{17-16} = rm; 930 931 // Encode instruction operands. 932 let Inst{3-0} = Dm{3-0}; 933 let Inst{5} = Dm{4}; 934 let Inst{8} = 1; 935 } 936 937 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0, 938 (outs SPR:$Sd), (ins DPR:$Dm), 939 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"), 940 []>, 941 Requires<[HasFPARMv8, HasDPVFP]> { 942 bits<5> Dm; 943 944 let Inst{17-16} = rm; 945 946 // Encode instruction operands 947 let Inst{3-0} = Dm{3-0}; 948 let Inst{5} = Dm{4}; 949 let Inst{8} = 1; 950 } 951 } 952 953 let Predicates = [HasFPARMv8] in { 954 let Predicates = [HasFullFP16] in { 955 def : Pat<(i32 (fp_to_sint (node (f16 HPR:$a)))), 956 (COPY_TO_REGCLASS 957 (!cast<Instruction>(NAME#"SH") (f16 HPR:$a)), 958 GPR)>; 959 960 def : Pat<(i32 (fp_to_uint (node (f16 HPR:$a)))), 961 (COPY_TO_REGCLASS 962 (!cast<Instruction>(NAME#"UH") (f16 HPR:$a)), 963 GPR)>; 964 } 965 def : Pat<(i32 (fp_to_sint (node SPR:$a))), 966 (COPY_TO_REGCLASS 967 (!cast<Instruction>(NAME#"SS") SPR:$a), 968 GPR)>; 969 def : Pat<(i32 (fp_to_uint (node SPR:$a))), 970 (COPY_TO_REGCLASS 971 (!cast<Instruction>(NAME#"US") SPR:$a), 972 GPR)>; 973 } 974 let Predicates = [HasFPARMv8, HasDPVFP] in { 975 def : Pat<(i32 (fp_to_sint (node (f64 DPR:$a)))), 976 (COPY_TO_REGCLASS 977 (!cast<Instruction>(NAME#"SD") DPR:$a), 978 GPR)>; 979 def : Pat<(i32 (fp_to_uint (node (f64 DPR:$a)))), 980 (COPY_TO_REGCLASS 981 (!cast<Instruction>(NAME#"UD") DPR:$a), 982 GPR)>; 983 } 984} 985 986defm VCVTA : vcvt_inst<"a", 0b00, fround>; 987defm VCVTN : vcvt_inst<"n", 0b01>; 988defm VCVTP : vcvt_inst<"p", 0b10, fceil>; 989defm VCVTM : vcvt_inst<"m", 0b11, ffloor>; 990 991def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, 992 (outs DPR:$Dd), (ins DPR:$Dm), 993 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", 994 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>; 995 996def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0, 997 (outs SPR:$Sd), (ins SPR:$Sm), 998 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm", 999 [(set SPR:$Sd, (fneg SPR:$Sm))]> { 1000 // Some single precision VFP instructions may be executed on both NEON and 1001 // VFP pipelines on A8. 1002 let D = VFPNeonA8Domain; 1003} 1004 1005def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0, 1006 (outs HPR:$Sd), (ins HPR:$Sm), 1007 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm", 1008 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>; 1009 1010multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { 1011 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0, 1012 (outs HPR:$Sd), (ins HPR:$Sm), 1013 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm", 1014 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1015 Requires<[HasFullFP16]> { 1016 let Inst{7} = op2; 1017 let Inst{16} = op; 1018 } 1019 1020 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0, 1021 (outs SPR:$Sd), (ins SPR:$Sm), 1022 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", 1023 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1024 Requires<[HasFPARMv8]> { 1025 let Inst{7} = op2; 1026 let Inst{16} = op; 1027 } 1028 def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0, 1029 (outs DPR:$Dd), (ins DPR:$Dm), 1030 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm", 1031 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1032 Requires<[HasFPARMv8, HasDPVFP]> { 1033 let Inst{7} = op2; 1034 let Inst{16} = op; 1035 } 1036 1037 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"), 1038 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1039 Requires<[HasFullFP16]>; 1040 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"), 1041 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>, 1042 Requires<[HasFPARMv8]>; 1043 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"), 1044 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>, 1045 Requires<[HasFPARMv8,HasDPVFP]>; 1046} 1047 1048defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; 1049defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; 1050defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; 1051 1052multiclass vrint_inst_anpm<string opc, bits<2> rm, 1053 SDPatternOperator node = null_frag> { 1054 let PostEncoderMethod = "", DecoderNamespace = "VFPV8", 1055 isUnpredicable = 1 in { 1056 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1057 (outs HPR:$Sd), (ins HPR:$Sm), 1058 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"), 1059 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>, 1060 Requires<[HasFullFP16]> { 1061 let Inst{17-16} = rm; 1062 } 1063 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1064 (outs SPR:$Sd), (ins SPR:$Sm), 1065 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"), 1066 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>, 1067 Requires<[HasFPARMv8]> { 1068 let Inst{17-16} = rm; 1069 } 1070 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0, 1071 (outs DPR:$Dd), (ins DPR:$Dm), 1072 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"), 1073 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>, 1074 Requires<[HasFPARMv8, HasDPVFP]> { 1075 let Inst{17-16} = rm; 1076 } 1077 } 1078 1079 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"), 1080 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>, 1081 Requires<[HasFullFP16]>; 1082 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"), 1083 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>, 1084 Requires<[HasFPARMv8]>; 1085 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"), 1086 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>, 1087 Requires<[HasFPARMv8,HasDPVFP]>; 1088} 1089 1090defm VRINTA : vrint_inst_anpm<"a", 0b00, fround>; 1091defm VRINTN : vrint_inst_anpm<"n", 0b01, int_arm_neon_vrintn>; 1092defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; 1093defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; 1094 1095def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, 1096 (outs DPR:$Dd), (ins DPR:$Dm), 1097 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", 1098 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>, 1099 Sched<[WriteFPSQRT64]>; 1100 1101def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, 1102 (outs SPR:$Sd), (ins SPR:$Sm), 1103 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", 1104 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>, 1105 Sched<[WriteFPSQRT32]>; 1106 1107def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0, 1108 (outs HPR:$Sd), (ins HPR:$Sm), 1109 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm", 1110 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>; 1111 1112let hasSideEffects = 0 in { 1113let isMoveReg = 1 in { 1114def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0, 1115 (outs DPR:$Dd), (ins DPR:$Dm), 1116 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>, 1117 Requires<[HasFPRegs64]>; 1118 1119def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0, 1120 (outs SPR:$Sd), (ins SPR:$Sm), 1121 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>, 1122 Requires<[HasFPRegs]>; 1123} // isMoveReg 1124 1125let PostEncoderMethod = "", DecoderNamespace = "VFPV8", isUnpredicable = 1 in { 1126def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0, 1127 (outs SPR:$Sd), (ins SPR:$Sm), 1128 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>, 1129 Requires<[HasFullFP16]>; 1130 1131def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0, 1132 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), 1133 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>, 1134 Requires<[HasFullFP16]> { 1135 let Constraints = "$Sd = $Sda"; 1136} 1137 1138} // PostEncoderMethod 1139} // hasSideEffects 1140 1141//===----------------------------------------------------------------------===// 1142// FP <-> GPR Copies. Int <-> FP Conversions. 1143// 1144 1145let isMoveReg = 1 in { 1146def VMOVRS : AVConv2I<0b11100001, 0b1010, 1147 (outs GPR:$Rt), (ins SPR:$Sn), 1148 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn", 1149 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>, 1150 Requires<[HasFPRegs]>, 1151 Sched<[WriteFPMOV]> { 1152 // Instruction operands. 1153 bits<4> Rt; 1154 bits<5> Sn; 1155 1156 // Encode instruction operands. 1157 let Inst{19-16} = Sn{4-1}; 1158 let Inst{7} = Sn{0}; 1159 let Inst{15-12} = Rt; 1160 1161 let Inst{6-5} = 0b00; 1162 let Inst{3-0} = 0b0000; 1163 1164 // Some single precision VFP instructions may be executed on both NEON and VFP 1165 // pipelines. 1166 let D = VFPNeonDomain; 1167} 1168 1169// Bitcast i32 -> f32. NEON prefers to use VMOVDRR. 1170def VMOVSR : AVConv4I<0b11100000, 0b1010, 1171 (outs SPR:$Sn), (ins GPR:$Rt), 1172 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt", 1173 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>, 1174 Requires<[HasFPRegs, UseVMOVSR]>, 1175 Sched<[WriteFPMOV]> { 1176 // Instruction operands. 1177 bits<5> Sn; 1178 bits<4> Rt; 1179 1180 // Encode instruction operands. 1181 let Inst{19-16} = Sn{4-1}; 1182 let Inst{7} = Sn{0}; 1183 let Inst{15-12} = Rt; 1184 1185 let Inst{6-5} = 0b00; 1186 let Inst{3-0} = 0b0000; 1187 1188 // Some single precision VFP instructions may be executed on both NEON and VFP 1189 // pipelines. 1190 let D = VFPNeonDomain; 1191} 1192} // isMoveReg 1193def : Pat<(arm_vmovsr GPR:$Rt), (VMOVSR GPR:$Rt)>, Requires<[HasVFP2, UseVMOVSR]>; 1194 1195let hasSideEffects = 0 in { 1196def VMOVRRD : AVConv3I<0b11000101, 0b1011, 1197 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm), 1198 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm", 1199 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>, 1200 Requires<[HasFPRegs]>, 1201 Sched<[WriteFPMOV]> { 1202 // Instruction operands. 1203 bits<5> Dm; 1204 bits<4> Rt; 1205 bits<4> Rt2; 1206 1207 // Encode instruction operands. 1208 let Inst{3-0} = Dm{3-0}; 1209 let Inst{5} = Dm{4}; 1210 let Inst{15-12} = Rt; 1211 let Inst{19-16} = Rt2; 1212 1213 let Inst{7-6} = 0b00; 1214 1215 // Some single precision VFP instructions may be executed on both NEON and VFP 1216 // pipelines. 1217 let D = VFPNeonDomain; 1218 1219 // This instruction is equivalent to 1220 // $Rt = EXTRACT_SUBREG $Dm, ssub_0 1221 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1 1222 let isExtractSubreg = 1; 1223} 1224 1225def VMOVRRS : AVConv3I<0b11000101, 0b1010, 1226 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2), 1227 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2", 1228 [/* For disassembly only; pattern left blank */]>, 1229 Requires<[HasFPRegs]>, 1230 Sched<[WriteFPMOV]> { 1231 bits<5> src1; 1232 bits<4> Rt; 1233 bits<4> Rt2; 1234 1235 // Encode instruction operands. 1236 let Inst{3-0} = src1{4-1}; 1237 let Inst{5} = src1{0}; 1238 let Inst{15-12} = Rt; 1239 let Inst{19-16} = Rt2; 1240 1241 let Inst{7-6} = 0b00; 1242 1243 // Some single precision VFP instructions may be executed on both NEON and VFP 1244 // pipelines. 1245 let D = VFPNeonDomain; 1246 let DecoderMethod = "DecodeVMOVRRS"; 1247} 1248} // hasSideEffects 1249 1250// FMDHR: GPR -> SPR 1251// FMDLR: GPR -> SPR 1252 1253def VMOVDRR : AVConv5I<0b11000100, 0b1011, 1254 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2), 1255 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2", 1256 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>, 1257 Requires<[HasFPRegs]>, 1258 Sched<[WriteFPMOV]> { 1259 // Instruction operands. 1260 bits<5> Dm; 1261 bits<4> Rt; 1262 bits<4> Rt2; 1263 1264 // Encode instruction operands. 1265 let Inst{3-0} = Dm{3-0}; 1266 let Inst{5} = Dm{4}; 1267 let Inst{15-12} = Rt; 1268 let Inst{19-16} = Rt2; 1269 1270 let Inst{7-6} = 0b00; 1271 1272 // Some single precision VFP instructions may be executed on both NEON and VFP 1273 // pipelines. 1274 let D = VFPNeonDomain; 1275 1276 // This instruction is equivalent to 1277 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1 1278 let isRegSequence = 1; 1279} 1280 1281// Hoist an fabs or a fneg of a value coming from integer registers 1282// and do the fabs/fneg on the integer value. This is never a lose 1283// and could enable the conversion to float to be removed completely. 1284def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1285 (VMOVDRR GPR:$Rl, (BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1286 Requires<[IsARM, HasV6T2]>; 1287def : Pat<(fabs (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1288 (VMOVDRR GPR:$Rl, (t2BFC GPR:$Rh, (i32 0x7FFFFFFF)))>, 1289 Requires<[IsThumb2, HasV6T2]>; 1290def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1291 (VMOVDRR GPR:$Rl, (EORri GPR:$Rh, (i32 0x80000000)))>, 1292 Requires<[IsARM]>; 1293def : Pat<(fneg (arm_fmdrr GPR:$Rl, GPR:$Rh)), 1294 (VMOVDRR GPR:$Rl, (t2EORri GPR:$Rh, (i32 0x80000000)))>, 1295 Requires<[IsThumb2]>; 1296 1297let hasSideEffects = 0 in 1298def VMOVSRR : AVConv5I<0b11000100, 0b1010, 1299 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2), 1300 IIC_fpMOVID, "vmov", "\t$dst1, $dst2, $src1, $src2", 1301 [/* For disassembly only; pattern left blank */]>, 1302 Requires<[HasFPRegs]>, 1303 Sched<[WriteFPMOV]> { 1304 // Instruction operands. 1305 bits<5> dst1; 1306 bits<4> src1; 1307 bits<4> src2; 1308 1309 // Encode instruction operands. 1310 let Inst{3-0} = dst1{4-1}; 1311 let Inst{5} = dst1{0}; 1312 let Inst{15-12} = src1; 1313 let Inst{19-16} = src2; 1314 1315 let Inst{7-6} = 0b00; 1316 1317 // Some single precision VFP instructions may be executed on both NEON and VFP 1318 // pipelines. 1319 let D = VFPNeonDomain; 1320 1321 let DecoderMethod = "DecodeVMOVSRR"; 1322} 1323 1324// Move H->R, clearing top 16 bits 1325def VMOVRH : AVConv2I<0b11100001, 0b1001, 1326 (outs rGPR:$Rt), (ins HPR:$Sn), 1327 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn", 1328 []>, 1329 Requires<[HasFPRegs16]>, 1330 Sched<[WriteFPMOV]> { 1331 // Instruction operands. 1332 bits<4> Rt; 1333 bits<5> Sn; 1334 1335 // Encode instruction operands. 1336 let Inst{19-16} = Sn{4-1}; 1337 let Inst{7} = Sn{0}; 1338 let Inst{15-12} = Rt; 1339 1340 let Inst{6-5} = 0b00; 1341 let Inst{3-0} = 0b0000; 1342 1343 let isUnpredicable = 1; 1344} 1345 1346// Move R->H, clearing top 16 bits 1347def VMOVHR : AVConv4I<0b11100000, 0b1001, 1348 (outs HPR:$Sn), (ins rGPR:$Rt), 1349 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt", 1350 []>, 1351 Requires<[HasFPRegs16]>, 1352 Sched<[WriteFPMOV]> { 1353 // Instruction operands. 1354 bits<5> Sn; 1355 bits<4> Rt; 1356 1357 // Encode instruction operands. 1358 let Inst{19-16} = Sn{4-1}; 1359 let Inst{7} = Sn{0}; 1360 let Inst{15-12} = Rt; 1361 1362 let Inst{6-5} = 0b00; 1363 let Inst{3-0} = 0b0000; 1364 1365 let isUnpredicable = 1; 1366} 1367 1368def : FPRegs16Pat<(arm_vmovrh (f16 HPR:$Sn)), (VMOVRH (f16 HPR:$Sn))>; 1369def : FPRegs16Pat<(arm_vmovrh (bf16 HPR:$Sn)), (VMOVRH (bf16 HPR:$Sn))>; 1370def : FPRegs16Pat<(f16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1371def : FPRegs16Pat<(bf16 (arm_vmovhr rGPR:$Rt)), (VMOVHR rGPR:$Rt)>; 1372 1373// FMRDH: SPR -> GPR 1374// FMRDL: SPR -> GPR 1375// FMRRS: SPR -> GPR 1376// FMRX: SPR system reg -> GPR 1377// FMSRR: GPR -> SPR 1378// FMXR: GPR -> VFP system reg 1379 1380 1381// Int -> FP: 1382 1383class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1384 bits<4> opcod4, dag oops, dag iops, 1385 InstrItinClass itin, string opc, string asm, 1386 list<dag> pattern> 1387 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1388 pattern> { 1389 // Instruction operands. 1390 bits<5> Dd; 1391 bits<5> Sm; 1392 1393 // Encode instruction operands. 1394 let Inst{3-0} = Sm{4-1}; 1395 let Inst{5} = Sm{0}; 1396 let Inst{15-12} = Dd{3-0}; 1397 let Inst{22} = Dd{4}; 1398 1399 let Predicates = [HasVFP2, HasDPVFP]; 1400 let hasSideEffects = 0; 1401} 1402 1403class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1404 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin, 1405 string opc, string asm, list<dag> pattern> 1406 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1407 pattern> { 1408 // Instruction operands. 1409 bits<5> Sd; 1410 bits<5> Sm; 1411 1412 // Encode instruction operands. 1413 let Inst{3-0} = Sm{4-1}; 1414 let Inst{5} = Sm{0}; 1415 let Inst{15-12} = Sd{4-1}; 1416 let Inst{22} = Sd{0}; 1417 1418 let hasSideEffects = 0; 1419} 1420 1421class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1422 bits<4> opcod4, dag oops, dag iops, 1423 InstrItinClass itin, string opc, string asm, 1424 list<dag> pattern> 1425 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1426 pattern> { 1427 // Instruction operands. 1428 bits<5> Sd; 1429 bits<5> Sm; 1430 1431 // Encode instruction operands. 1432 let Inst{3-0} = Sm{4-1}; 1433 let Inst{5} = Sm{0}; 1434 let Inst{15-12} = Sd{4-1}; 1435 let Inst{22} = Sd{0}; 1436 1437 let Predicates = [HasFullFP16]; 1438 let hasSideEffects = 0; 1439} 1440 1441def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1442 (outs DPR:$Dd), (ins SPR:$Sm), 1443 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", 1444 []>, 1445 Sched<[WriteFPCVT]> { 1446 let Inst{7} = 1; // s32 1447} 1448 1449let Predicates=[HasVFP2, HasDPVFP] in { 1450 def : VFPPat<(f64 (sint_to_fp GPR:$a)), 1451 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1452 1453 def : VFPPat<(f64 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1454 (VSITOD (VLDRS addrmode5:$a))>; 1455} 1456 1457def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1458 (outs SPR:$Sd),(ins SPR:$Sm), 1459 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", 1460 []>, 1461 Sched<[WriteFPCVT]> { 1462 let Inst{7} = 1; // s32 1463 1464 // Some single precision VFP instructions may be executed on both NEON and 1465 // VFP pipelines on A8. 1466 let D = VFPNeonA8Domain; 1467} 1468 1469def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), 1470 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1471 1472def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1473 (VSITOS (VLDRS addrmode5:$a))>; 1474 1475def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1476 (outs HPR:$Sd), (ins SPR:$Sm), 1477 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm", 1478 []>, 1479 Sched<[WriteFPCVT]> { 1480 let Inst{7} = 1; // s32 1481 let isUnpredicable = 1; 1482} 1483 1484def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)), 1485 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1486 1487def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, 1488 (outs DPR:$Dd), (ins SPR:$Sm), 1489 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", 1490 []>, 1491 Sched<[WriteFPCVT]> { 1492 let Inst{7} = 0; // u32 1493} 1494 1495let Predicates=[HasVFP2, HasDPVFP] in { 1496 def : VFPPat<(f64 (uint_to_fp GPR:$a)), 1497 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>; 1498 1499 def : VFPPat<(f64 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1500 (VUITOD (VLDRS addrmode5:$a))>; 1501} 1502 1503def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, 1504 (outs SPR:$Sd), (ins SPR:$Sm), 1505 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", 1506 []>, 1507 Sched<[WriteFPCVT]> { 1508 let Inst{7} = 0; // u32 1509 1510 // Some single precision VFP instructions may be executed on both NEON and 1511 // VFP pipelines on A8. 1512 let D = VFPNeonA8Domain; 1513} 1514 1515def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), 1516 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>; 1517 1518def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), 1519 (VUITOS (VLDRS addrmode5:$a))>; 1520 1521def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, 1522 (outs HPR:$Sd), (ins SPR:$Sm), 1523 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm", 1524 []>, 1525 Sched<[WriteFPCVT]> { 1526 let Inst{7} = 0; // u32 1527 let isUnpredicable = 1; 1528} 1529 1530def : VFPNoNEONPat<(f16 (uint_to_fp GPR:$a)), 1531 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; 1532 1533// FP -> Int: 1534 1535class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1536 bits<4> opcod4, dag oops, dag iops, 1537 InstrItinClass itin, string opc, string asm, 1538 list<dag> pattern> 1539 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1540 pattern> { 1541 // Instruction operands. 1542 bits<5> Sd; 1543 bits<5> Dm; 1544 1545 // Encode instruction operands. 1546 let Inst{3-0} = Dm{3-0}; 1547 let Inst{5} = Dm{4}; 1548 let Inst{15-12} = Sd{4-1}; 1549 let Inst{22} = Sd{0}; 1550 1551 let Predicates = [HasVFP2, HasDPVFP]; 1552 let hasSideEffects = 0; 1553} 1554 1555class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1556 bits<4> opcod4, dag oops, dag iops, 1557 InstrItinClass itin, string opc, string asm, 1558 list<dag> pattern> 1559 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1560 pattern> { 1561 // Instruction operands. 1562 bits<5> Sd; 1563 bits<5> Sm; 1564 1565 // Encode instruction operands. 1566 let Inst{3-0} = Sm{4-1}; 1567 let Inst{5} = Sm{0}; 1568 let Inst{15-12} = Sd{4-1}; 1569 let Inst{22} = Sd{0}; 1570 1571 let hasSideEffects = 0; 1572} 1573 1574class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, 1575 bits<4> opcod4, dag oops, dag iops, 1576 InstrItinClass itin, string opc, string asm, 1577 list<dag> pattern> 1578 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm, 1579 pattern> { 1580 // Instruction operands. 1581 bits<5> Sd; 1582 bits<5> Sm; 1583 1584 // Encode instruction operands. 1585 let Inst{3-0} = Sm{4-1}; 1586 let Inst{5} = Sm{0}; 1587 let Inst{15-12} = Sd{4-1}; 1588 let Inst{22} = Sd{0}; 1589 1590 let Predicates = [HasFullFP16]; 1591 let hasSideEffects = 0; 1592} 1593 1594// Always set Z bit in the instruction, i.e. "round towards zero" variants. 1595def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1596 (outs SPR:$Sd), (ins DPR:$Dm), 1597 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", 1598 []>, 1599 Sched<[WriteFPCVT]> { 1600 let Inst{7} = 1; // Z bit 1601} 1602 1603let Predicates=[HasVFP2, HasDPVFP] in { 1604 def : VFPPat<(i32 (fp_to_sint (f64 DPR:$a))), 1605 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1606 def : VFPPat<(i32 (fp_to_sint_sat (f64 DPR:$a), i32)), 1607 (COPY_TO_REGCLASS (VTOSIZD DPR:$a), GPR)>; 1608 1609 def : VFPPat<(alignedstore32 (i32 (fp_to_sint (f64 DPR:$a))), addrmode5:$ptr), 1610 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1611 def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f64 DPR:$a), i32)), addrmode5:$ptr), 1612 (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; 1613} 1614 1615def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1616 (outs SPR:$Sd), (ins SPR:$Sm), 1617 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", 1618 []>, 1619 Sched<[WriteFPCVT]> { 1620 let Inst{7} = 1; // Z bit 1621 1622 // Some single precision VFP instructions may be executed on both NEON and 1623 // VFP pipelines on A8. 1624 let D = VFPNeonA8Domain; 1625} 1626 1627def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), 1628 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1629def : VFPPat<(i32 (fp_to_sint_sat SPR:$a, i32)), 1630 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; 1631 1632def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), 1633 addrmode5:$ptr), 1634 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1635def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)), 1636 addrmode5:$ptr), 1637 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; 1638 1639def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1640 (outs SPR:$Sd), (ins HPR:$Sm), 1641 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", 1642 []>, 1643 Sched<[WriteFPCVT]> { 1644 let Inst{7} = 1; // Z bit 1645 let isUnpredicable = 1; 1646} 1647 1648def : VFPNoNEONPat<(i32 (fp_to_sint (f16 HPR:$a))), 1649 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; 1650def : VFPPat<(i32 (fp_to_sint_sat (f16 HPR:$a), i32)), 1651 (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; 1652 1653def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1654 (outs SPR:$Sd), (ins DPR:$Dm), 1655 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", 1656 []>, 1657 Sched<[WriteFPCVT]> { 1658 let Inst{7} = 1; // Z bit 1659} 1660 1661let Predicates=[HasVFP2, HasDPVFP] in { 1662 def : VFPPat<(i32 (fp_to_uint (f64 DPR:$a))), 1663 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1664 def : VFPPat<(i32 (fp_to_uint_sat (f64 DPR:$a), i32)), 1665 (COPY_TO_REGCLASS (VTOUIZD DPR:$a), GPR)>; 1666 1667 def : VFPPat<(alignedstore32 (i32 (fp_to_uint (f64 DPR:$a))), addrmode5:$ptr), 1668 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1669 def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f64 DPR:$a), i32)), addrmode5:$ptr), 1670 (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; 1671} 1672 1673def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1674 (outs SPR:$Sd), (ins SPR:$Sm), 1675 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", 1676 []>, 1677 Sched<[WriteFPCVT]> { 1678 let Inst{7} = 1; // Z bit 1679 1680 // Some single precision VFP instructions may be executed on both NEON and 1681 // VFP pipelines on A8. 1682 let D = VFPNeonA8Domain; 1683} 1684 1685def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), 1686 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1687def : VFPPat<(i32 (fp_to_uint_sat SPR:$a, i32)), 1688 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; 1689 1690def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), 1691 addrmode5:$ptr), 1692 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1693def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)), 1694 addrmode5:$ptr), 1695 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; 1696 1697def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1698 (outs SPR:$Sd), (ins HPR:$Sm), 1699 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", 1700 []>, 1701 Sched<[WriteFPCVT]> { 1702 let Inst{7} = 1; // Z bit 1703 let isUnpredicable = 1; 1704} 1705 1706def : VFPNoNEONPat<(i32 (fp_to_uint (f16 HPR:$a))), 1707 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; 1708def : VFPPat<(i32 (fp_to_uint_sat (f16 HPR:$a), i32)), 1709 (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; 1710 1711// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. 1712let Uses = [FPSCR] in { 1713def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, 1714 (outs SPR:$Sd), (ins DPR:$Dm), 1715 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", 1716 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>, 1717 Sched<[WriteFPCVT]> { 1718 let Inst{7} = 0; // Z bit 1719} 1720 1721def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, 1722 (outs SPR:$Sd), (ins SPR:$Sm), 1723 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm", 1724 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>, 1725 Sched<[WriteFPCVT]> { 1726 let Inst{7} = 0; // Z bit 1727} 1728 1729def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, 1730 (outs SPR:$Sd), (ins SPR:$Sm), 1731 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm", 1732 []>, 1733 Sched<[WriteFPCVT]> { 1734 let Inst{7} = 0; // Z bit 1735 let isUnpredicable = 1; 1736} 1737 1738def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, 1739 (outs SPR:$Sd), (ins DPR:$Dm), 1740 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm", 1741 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>, 1742 Sched<[WriteFPCVT]> { 1743 let Inst{7} = 0; // Z bit 1744} 1745 1746def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, 1747 (outs SPR:$Sd), (ins SPR:$Sm), 1748 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm", 1749 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>, 1750 Sched<[WriteFPCVT]> { 1751 let Inst{7} = 0; // Z bit 1752} 1753 1754def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, 1755 (outs SPR:$Sd), (ins SPR:$Sm), 1756 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm", 1757 []>, 1758 Sched<[WriteFPCVT]> { 1759 let Inst{7} = 0; // Z bit 1760 let isUnpredicable = 1; 1761} 1762} 1763 1764// v8.3-a Javascript Convert to Signed fixed-point 1765def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, 1766 (outs SPR:$Sd), (ins DPR:$Dm), 1767 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm", 1768 []>, 1769 Requires<[HasFPARMv8, HasV8_3a]> { 1770 let Inst{7} = 1; // Z bit 1771} 1772 1773// Convert between floating-point and fixed-point 1774// Data type for fixed-point naming convention: 1775// S16 (U=0, sx=0) -> SH 1776// U16 (U=1, sx=0) -> UH 1777// S32 (U=0, sx=1) -> SL 1778// U32 (U=1, sx=1) -> UL 1779 1780let Constraints = "$a = $dst" in { 1781 1782// FP to Fixed-Point: 1783 1784// Single Precision register 1785class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1786 bit op5, dag oops, dag iops, InstrItinClass itin, 1787 string opc, string asm, list<dag> pattern> 1788 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1789 bits<5> dst; 1790 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1791 let Inst{22} = dst{0}; 1792 let Inst{15-12} = dst{4-1}; 1793 1794 let hasSideEffects = 0; 1795} 1796 1797// Double Precision register 1798class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, 1799 bit op5, dag oops, dag iops, InstrItinClass itin, 1800 string opc, string asm, list<dag> pattern> 1801 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> { 1802 bits<5> dst; 1803 // if dp_operation then UInt(D:Vd) else UInt(Vd:D); 1804 let Inst{22} = dst{4}; 1805 let Inst{15-12} = dst{3-0}; 1806 1807 let hasSideEffects = 0; 1808 let Predicates = [HasVFP2, HasDPVFP]; 1809} 1810 1811let isUnpredicable = 1 in { 1812 1813def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1814 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1815 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>, 1816 Requires<[HasFullFP16]>, 1817 Sched<[WriteFPCVT]>; 1818 1819def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0, 1820 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1821 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>, 1822 Requires<[HasFullFP16]>, 1823 Sched<[WriteFPCVT]>; 1824 1825def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1826 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1827 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>, 1828 Requires<[HasFullFP16]>, 1829 Sched<[WriteFPCVT]>; 1830 1831def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1, 1832 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1833 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>, 1834 Requires<[HasFullFP16]>, 1835 Sched<[WriteFPCVT]>; 1836 1837} // End of 'let isUnpredicable = 1 in' 1838 1839def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1840 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1841 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []>, 1842 Sched<[WriteFPCVT]> { 1843 // Some single precision VFP instructions may be executed on both NEON and 1844 // VFP pipelines on A8. 1845 let D = VFPNeonA8Domain; 1846} 1847 1848def VTOUHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 0, 1849 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1850 IIC_fpCVTSI, "vcvt", ".u16.f32\t$dst, $a, $fbits", []>, 1851 Sched<[WriteFPCVT]> { 1852 // Some single precision VFP instructions may be executed on both NEON and 1853 // VFP pipelines on A8. 1854 let D = VFPNeonA8Domain; 1855} 1856 1857def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1858 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1859 IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a, $fbits", []>, 1860 Sched<[WriteFPCVT]> { 1861 // Some single precision VFP instructions may be executed on both NEON and 1862 // VFP pipelines on A8. 1863 let D = VFPNeonA8Domain; 1864} 1865 1866def VTOULS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1010, 1, 1867 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1868 IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a, $fbits", []>, 1869 Sched<[WriteFPCVT]> { 1870 // Some single precision VFP instructions may be executed on both NEON and 1871 // VFP pipelines on A8. 1872 let D = VFPNeonA8Domain; 1873} 1874 1875def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1876 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1877 IIC_fpCVTDI, "vcvt", ".s16.f64\t$dst, $a, $fbits", []>, 1878 Sched<[WriteFPCVT]>; 1879 1880def VTOUHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 0, 1881 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1882 IIC_fpCVTDI, "vcvt", ".u16.f64\t$dst, $a, $fbits", []>, 1883 Sched<[WriteFPCVT]>; 1884 1885def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 1886 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1887 IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a, $fbits", []>, 1888 Sched<[WriteFPCVT]>; 1889 1890def VTOULD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1111, 0b1011, 1, 1891 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1892 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>, 1893 Sched<[WriteFPCVT]>; 1894 1895// Fixed-Point to FP: 1896 1897let isUnpredicable = 1 in { 1898 1899def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0, 1900 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1901 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>, 1902 Requires<[HasFullFP16]>, 1903 Sched<[WriteFPCVT]>; 1904 1905def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0, 1906 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1907 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>, 1908 Requires<[HasFullFP16]>, 1909 Sched<[WriteFPCVT]>; 1910 1911def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1, 1912 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1913 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>, 1914 Requires<[HasFullFP16]>, 1915 Sched<[WriteFPCVT]>; 1916 1917def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1, 1918 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1919 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>, 1920 Requires<[HasFullFP16]>, 1921 Sched<[WriteFPCVT]>; 1922 1923} // End of 'let isUnpredicable = 1 in' 1924 1925def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0, 1926 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1927 IIC_fpCVTIS, "vcvt", ".f32.s16\t$dst, $a, $fbits", []>, 1928 Sched<[WriteFPCVT]> { 1929 // Some single precision VFP instructions may be executed on both NEON and 1930 // VFP pipelines on A8. 1931 let D = VFPNeonA8Domain; 1932} 1933 1934def VUHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 0, 1935 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits), 1936 IIC_fpCVTIS, "vcvt", ".f32.u16\t$dst, $a, $fbits", []>, 1937 Sched<[WriteFPCVT]> { 1938 // Some single precision VFP instructions may be executed on both NEON and 1939 // VFP pipelines on A8. 1940 let D = VFPNeonA8Domain; 1941} 1942 1943def VSLTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 1, 1944 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1945 IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a, $fbits", []>, 1946 Sched<[WriteFPCVT]> { 1947 // Some single precision VFP instructions may be executed on both NEON and 1948 // VFP pipelines on A8. 1949 let D = VFPNeonA8Domain; 1950} 1951 1952def VULTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1010, 1, 1953 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits), 1954 IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a, $fbits", []>, 1955 Sched<[WriteFPCVT]> { 1956 // Some single precision VFP instructions may be executed on both NEON and 1957 // VFP pipelines on A8. 1958 let D = VFPNeonA8Domain; 1959} 1960 1961def VSHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 0, 1962 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1963 IIC_fpCVTID, "vcvt", ".f64.s16\t$dst, $a, $fbits", []>, 1964 Sched<[WriteFPCVT]>; 1965 1966def VUHTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 0, 1967 (outs DPR:$dst), (ins DPR:$a, fbits16:$fbits), 1968 IIC_fpCVTID, "vcvt", ".f64.u16\t$dst, $a, $fbits", []>, 1969 Sched<[WriteFPCVT]>; 1970 1971def VSLTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1010, 0b1011, 1, 1972 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1973 IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a, $fbits", []>, 1974 Sched<[WriteFPCVT]>; 1975 1976def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, 1977 (outs DPR:$dst), (ins DPR:$a, fbits32:$fbits), 1978 IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>, 1979 Sched<[WriteFPCVT]>; 1980 1981} // End of 'let Constraints = "$a = $dst" in' 1982 1983// BFloat16 - Single precision, unary, predicated 1984class BF16_VCVT<string opc, bits<2> op7_6> 1985 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm), 1986 VFPUnaryFrm, NoItinerary, 1987 opc, ".bf16.f32\t$Sd, $Sm", []>, 1988 RegConstraint<"$dst = $Sd">, 1989 Requires<[HasBF16]>, 1990 Sched<[]> { 1991 bits<5> Sd; 1992 bits<5> Sm; 1993 1994 // Encode instruction operands. 1995 let Inst{3-0} = Sm{4-1}; 1996 let Inst{5} = Sm{0}; 1997 let Inst{15-12} = Sd{4-1}; 1998 let Inst{22} = Sd{0}; 1999 2000 let Inst{27-23} = 0b11101; // opcode1 2001 let Inst{21-20} = 0b11; // opcode2 2002 let Inst{19-16} = 0b0011; // opcode3 2003 let Inst{11-8} = 0b1001; 2004 let Inst{7-6} = op7_6; 2005 let Inst{4} = 0; 2006 2007 let DecoderNamespace = "VFPV8"; 2008 let hasSideEffects = 0; 2009} 2010 2011def BF16_VCVTB : BF16_VCVT<"vcvtb", 0b01>; 2012def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>; 2013 2014//===----------------------------------------------------------------------===// 2015// FP Multiply-Accumulate Operations. 2016// 2017 2018def VMLAD : ADbI<0b11100, 0b00, 0, 0, 2019 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2020 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", 2021 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2022 (f64 DPR:$Ddin)))]>, 2023 RegConstraint<"$Ddin = $Dd">, 2024 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2025 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2026 2027def VMLAS : ASbIn<0b11100, 0b00, 0, 0, 2028 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2029 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", 2030 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2031 SPR:$Sdin))]>, 2032 RegConstraint<"$Sdin = $Sd">, 2033 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2034 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2035 // Some single precision VFP instructions may be executed on both NEON and 2036 // VFP pipelines on A8. 2037 let D = VFPNeonA8Domain; 2038} 2039 2040def VMLAH : AHbI<0b11100, 0b00, 0, 0, 2041 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2042 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm", 2043 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2044 (f16 HPR:$Sdin)))]>, 2045 RegConstraint<"$Sdin = $Sd">, 2046 Requires<[HasFullFP16,UseFPVMLx]>; 2047 2048def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2049 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2050 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2051def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2052 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2053 Requires<[HasVFP2,DontUseNEONForFP, UseFPVMLx]>; 2054def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2055 (VMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2056 Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>; 2057 2058 2059def VMLSD : ADbI<0b11100, 0b00, 1, 0, 2060 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2061 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", 2062 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2063 (f64 DPR:$Ddin)))]>, 2064 RegConstraint<"$Ddin = $Dd">, 2065 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2066 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2067 2068def VMLSS : ASbIn<0b11100, 0b00, 1, 0, 2069 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2070 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", 2071 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2072 SPR:$Sdin))]>, 2073 RegConstraint<"$Sdin = $Sd">, 2074 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2075 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2076 // Some single precision VFP instructions may be executed on both NEON and 2077 // VFP pipelines on A8. 2078 let D = VFPNeonA8Domain; 2079} 2080 2081def VMLSH : AHbI<0b11100, 0b00, 1, 0, 2082 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2083 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm", 2084 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2085 (f16 HPR:$Sdin)))]>, 2086 RegConstraint<"$Sdin = $Sd">, 2087 Requires<[HasFullFP16,UseFPVMLx]>; 2088 2089def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2090 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2091 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2092def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2093 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2094 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2095def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2096 (VMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2097 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2098 2099def VNMLAD : ADbI<0b11100, 0b01, 1, 0, 2100 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2101 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", 2102 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2103 (f64 DPR:$Ddin)))]>, 2104 RegConstraint<"$Ddin = $Dd">, 2105 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2106 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2107 2108def VNMLAS : ASbI<0b11100, 0b01, 1, 0, 2109 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2110 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", 2111 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2112 SPR:$Sdin))]>, 2113 RegConstraint<"$Sdin = $Sd">, 2114 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2115 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2116 // Some single precision VFP instructions may be executed on both NEON and 2117 // VFP pipelines on A8. 2118 let D = VFPNeonA8Domain; 2119} 2120 2121def VNMLAH : AHbI<0b11100, 0b01, 1, 0, 2122 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2123 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm", 2124 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2125 (f16 HPR:$Sdin)))]>, 2126 RegConstraint<"$Sdin = $Sd">, 2127 Requires<[HasFullFP16,UseFPVMLx]>; 2128 2129// (-(a * b) - dst) -> -(dst + (a * b)) 2130def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2131 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2132 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2133def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2134 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2135 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2136def : Pat<(fsub_mlx (fneg (fmul_su (f16 HPR:$a), HPR:$b)), HPR:$dstin), 2137 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2138 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2139 2140// (-dst - (a * b)) -> -(dst + (a * b)) 2141def : Pat<(fsub_mlx (fneg DPR:$dstin), (fmul_su DPR:$a, (f64 DPR:$b))), 2142 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>, 2143 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2144def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)), 2145 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>, 2146 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2147def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su (f16 HPR:$a), HPR:$b)), 2148 (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2149 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2150 2151def VNMLSD : ADbI<0b11100, 0b01, 0, 0, 2152 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2153 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", 2154 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2155 (f64 DPR:$Ddin)))]>, 2156 RegConstraint<"$Ddin = $Dd">, 2157 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, 2158 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2159 2160def VNMLSS : ASbI<0b11100, 0b01, 0, 0, 2161 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2162 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", 2163 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2164 RegConstraint<"$Sdin = $Sd">, 2165 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>, 2166 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2167 // Some single precision VFP instructions may be executed on both NEON and 2168 // VFP pipelines on A8. 2169 let D = VFPNeonA8Domain; 2170} 2171 2172def VNMLSH : AHbI<0b11100, 0b01, 0, 0, 2173 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2174 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm", 2175 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2176 RegConstraint<"$Sdin = $Sd">, 2177 Requires<[HasFullFP16,UseFPVMLx]>; 2178 2179def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2180 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>, 2181 Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>; 2182def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2183 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>, 2184 Requires<[HasVFP2,DontUseNEONForFP,UseFPVMLx]>; 2185def : Pat<(fsub_mlx (fmul_su (f16 HPR:$a), HPR:$b), HPR:$dstin), 2186 (VNMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2187 Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; 2188 2189//===----------------------------------------------------------------------===// 2190// Fused FP Multiply-Accumulate Operations. 2191// 2192def VFMAD : ADbI<0b11101, 0b10, 0, 0, 2193 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2194 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", 2195 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2196 (f64 DPR:$Ddin)))]>, 2197 RegConstraint<"$Ddin = $Dd">, 2198 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2199 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2200 2201def VFMAS : ASbIn<0b11101, 0b10, 0, 0, 2202 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2203 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", 2204 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm), 2205 SPR:$Sdin))]>, 2206 RegConstraint<"$Sdin = $Sd">, 2207 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2208 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2209 // Some single precision VFP instructions may be executed on both NEON and 2210 // VFP pipelines. 2211} 2212 2213def VFMAH : AHbI<0b11101, 0b10, 0, 0, 2214 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2215 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm", 2216 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), 2217 (f16 HPR:$Sdin)))]>, 2218 RegConstraint<"$Sdin = $Sd">, 2219 Requires<[HasFullFP16,UseFusedMAC]>, 2220 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2221 2222def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2223 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2224 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2225def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2226 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2227 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2228def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2229 (VFMAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2230 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2231 2232// Match @llvm.fma.* intrinsics 2233// (fma x, y, z) -> (vfms z, x, y) 2234def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)), 2235 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2236 Requires<[HasVFP4,HasDPVFP]>; 2237def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)), 2238 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2239 Requires<[HasVFP4]>; 2240def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, (f16 HPR:$Sdin))), 2241 (VFMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2242 Requires<[HasFullFP16]>; 2243 2244def VFMSD : ADbI<0b11101, 0b10, 1, 0, 2245 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2246 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", 2247 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2248 (f64 DPR:$Ddin)))]>, 2249 RegConstraint<"$Ddin = $Dd">, 2250 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2251 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2252 2253def VFMSS : ASbIn<0b11101, 0b10, 1, 0, 2254 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2255 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", 2256 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2257 SPR:$Sdin))]>, 2258 RegConstraint<"$Sdin = $Sd">, 2259 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2260 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2261 // Some single precision VFP instructions may be executed on both NEON and 2262 // VFP pipelines. 2263} 2264 2265def VFMSH : AHbI<0b11101, 0b10, 1, 0, 2266 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2267 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm", 2268 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2269 (f16 HPR:$Sdin)))]>, 2270 RegConstraint<"$Sdin = $Sd">, 2271 Requires<[HasFullFP16,UseFusedMAC]>, 2272 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2273 2274def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))), 2275 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2276 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2277def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)), 2278 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2279 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2280def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), 2281 (VFMSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, 2282 Requires<[HasFullFP16,DontUseNEONForFP,UseFusedMAC]>; 2283 2284// Match @llvm.fma.* intrinsics 2285// (fma (fneg x), y, z) -> (vfms z, x, y) 2286def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)), 2287 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2288 Requires<[HasVFP4,HasDPVFP]>; 2289def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)), 2290 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2291 Requires<[HasVFP4]>; 2292def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), 2293 (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2294 Requires<[HasFullFP16]>; 2295 2296def VFNMAD : ADbI<0b11101, 0b01, 1, 0, 2297 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2298 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", 2299 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)), 2300 (f64 DPR:$Ddin)))]>, 2301 RegConstraint<"$Ddin = $Dd">, 2302 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2303 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2304 2305def VFNMAS : ASbI<0b11101, 0b01, 1, 0, 2306 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2307 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", 2308 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)), 2309 SPR:$Sdin))]>, 2310 RegConstraint<"$Sdin = $Sd">, 2311 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2312 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2313 // Some single precision VFP instructions may be executed on both NEON and 2314 // VFP pipelines. 2315} 2316 2317def VFNMAH : AHbI<0b11101, 0b01, 1, 0, 2318 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2319 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm", 2320 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))), 2321 (f16 HPR:$Sdin)))]>, 2322 RegConstraint<"$Sdin = $Sd">, 2323 Requires<[HasFullFP16,UseFusedMAC]>, 2324 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2325 2326def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin), 2327 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>, 2328 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2329def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin), 2330 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>, 2331 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2332 2333// Match @llvm.fma.* intrinsics 2334// (fneg (fma x, y, z)) -> (vfnma z, x, y) 2335def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))), 2336 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2337 Requires<[HasVFP4,HasDPVFP]>; 2338def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))), 2339 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2340 Requires<[HasVFP4]>; 2341def : Pat<(fneg (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (f16 (f16 HPR:$Sdin)))), 2342 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2343 Requires<[HasFullFP16]>; 2344// (fma (fneg x), y, (fneg z)) -> (vfnma z, x, y) 2345def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))), 2346 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2347 Requires<[HasVFP4,HasDPVFP]>; 2348def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))), 2349 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2350 Requires<[HasVFP4]>; 2351def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2352 (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2353 Requires<[HasFullFP16]>; 2354 2355def VFNMSD : ADbI<0b11101, 0b01, 0, 0, 2356 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), 2357 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", 2358 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm), 2359 (f64 DPR:$Ddin)))]>, 2360 RegConstraint<"$Ddin = $Dd">, 2361 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, 2362 Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2363 2364def VFNMSS : ASbI<0b11101, 0b01, 0, 0, 2365 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), 2366 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", 2367 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>, 2368 RegConstraint<"$Sdin = $Sd">, 2369 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>, 2370 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]> { 2371 // Some single precision VFP instructions may be executed on both NEON and 2372 // VFP pipelines. 2373} 2374 2375def VFNMSH : AHbI<0b11101, 0b01, 0, 0, 2376 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), 2377 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm", 2378 [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>, 2379 RegConstraint<"$Sdin = $Sd">, 2380 Requires<[HasFullFP16,UseFusedMAC]>, 2381 Sched<[WriteFPMAC32, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; 2382 2383def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin), 2384 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>, 2385 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>; 2386def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin), 2387 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>, 2388 Requires<[HasVFP4,DontUseNEONForFP,UseFusedMAC]>; 2389 2390// Match @llvm.fma.* intrinsics 2391 2392// (fma x, y, (fneg z)) -> (vfnms z, x, y)) 2393def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))), 2394 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2395 Requires<[HasVFP4,HasDPVFP]>; 2396def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))), 2397 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2398 Requires<[HasVFP4]>; 2399def : Pat<(f16 (fma (f16 HPR:$Sn), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin)))), 2400 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2401 Requires<[HasFullFP16]>; 2402// (fneg (fma (fneg x), y, z)) -> (vfnms z, x, y) 2403def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))), 2404 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>, 2405 Requires<[HasVFP4,HasDPVFP]>; 2406def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))), 2407 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>, 2408 Requires<[HasVFP4]>; 2409def : Pat<(fneg (f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin)))), 2410 (VFNMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, 2411 Requires<[HasFullFP16]>; 2412 2413//===----------------------------------------------------------------------===// 2414// FP Conditional moves. 2415// 2416 2417let hasSideEffects = 0 in { 2418def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p), 2419 IIC_fpUNA64, 2420 [(set (f64 DPR:$Dd), 2421 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>, 2422 RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>; 2423 2424def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p), 2425 IIC_fpUNA32, 2426 [(set (f32 SPR:$Sd), 2427 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>, 2428 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>; 2429 2430def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p), 2431 IIC_fpUNA16, 2432 [(set (f16 HPR:$Sd), 2433 (ARMcmov (f16 HPR:$Sn), (f16 HPR:$Sm), cmovpred:$p))]>, 2434 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>; 2435} // hasSideEffects 2436 2437//===----------------------------------------------------------------------===// 2438// Move from VFP System Register to ARM core register. 2439// 2440 2441class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2442 list<dag> pattern>: 2443 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2444 2445 // Instruction operand. 2446 bits<4> Rt; 2447 2448 let Inst{27-20} = 0b11101111; 2449 let Inst{19-16} = opc19_16; 2450 let Inst{15-12} = Rt; 2451 let Inst{11-8} = 0b1010; 2452 let Inst{7} = 0; 2453 let Inst{6-5} = 0b00; 2454 let Inst{4} = 1; 2455 let Inst{3-0} = 0b0000; 2456 let Unpredictable{7-5} = 0b111; 2457 let Unpredictable{3-0} = 0b1111; 2458} 2459 2460let DecoderMethod = "DecodeForVMRSandVMSR" in { 2461 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags 2462 // to APSR. 2463 let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs], 2464 Rt = 0b1111 /* apsr_nzcv */ in 2465 def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins), 2466 "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>; 2467 2468 // Application level FPSCR -> GPR 2469 let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in 2470 def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPRnopc:$Rt), (ins), 2471 "vmrs", "\t$Rt, fpscr", 2472 [(set GPRnopc:$Rt, (int_arm_get_fpscr))]>; 2473 2474 // System level FPEXC, FPSID -> GPR 2475 let Uses = [FPSCR] in { 2476 def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPRnopc:$Rt), (ins), 2477 "vmrs", "\t$Rt, fpexc", []>; 2478 def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPRnopc:$Rt), (ins), 2479 "vmrs", "\t$Rt, fpsid", []>; 2480 def VMRS_MVFR0 : MovFromVFP<0b0111 /* mvfr0 */, (outs GPRnopc:$Rt), (ins), 2481 "vmrs", "\t$Rt, mvfr0", []>; 2482 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPRnopc:$Rt), (ins), 2483 "vmrs", "\t$Rt, mvfr1", []>; 2484 let Predicates = [HasFPARMv8] in { 2485 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins), 2486 "vmrs", "\t$Rt, mvfr2", []>; 2487 } 2488 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPRnopc:$Rt), (ins), 2489 "vmrs", "\t$Rt, fpinst", []>; 2490 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPRnopc:$Rt), 2491 (ins), "vmrs", "\t$Rt, fpinst2", []>; 2492 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2493 // System level FPSCR_NZCVQC -> GPR 2494 def VMRS_FPSCR_NZCVQC 2495 : MovFromVFP<0b0010 /* fpscr_nzcvqc */, 2496 (outs GPR:$Rt), (ins cl_FPSCR_NZCV:$fpscr_in), 2497 "vmrs", "\t$Rt, fpscr_nzcvqc", []>; 2498 } 2499 } 2500 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2501 // System level FPSCR -> GPR, with context saving for security extensions 2502 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2503 "vmrs", "\t$Rt, fpcxtns", []>; 2504 } 2505 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2506 // System level FPSCR -> GPR, with context saving for security extensions 2507 def VMRS_FPCXTS : MovFromVFP<0b1111 /* fpcxts */, (outs GPR:$Rt), (ins), 2508 "vmrs", "\t$Rt, fpcxts", []>; 2509 } 2510 2511 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2512 // System level VPR/P0 -> GPR 2513 let Uses = [VPR] in 2514 def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins), 2515 "vmrs", "\t$Rt, vpr", []>; 2516 2517 def VMRS_P0 : MovFromVFP<0b1101 /* p0 */, (outs GPR:$Rt), (ins VCCR:$cond), 2518 "vmrs", "\t$Rt, p0", []>; 2519 } 2520} 2521 2522//===----------------------------------------------------------------------===// 2523// Move from ARM core register to VFP System Register. 2524// 2525 2526class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm, 2527 list<dag> pattern>: 2528 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> { 2529 2530 // Instruction operand. 2531 bits<4> Rt; 2532 2533 let Inst{27-20} = 0b11101110; 2534 let Inst{19-16} = opc19_16; 2535 let Inst{15-12} = Rt; 2536 let Inst{11-8} = 0b1010; 2537 let Inst{7} = 0; 2538 let Inst{6-5} = 0b00; 2539 let Inst{4} = 1; 2540 let Inst{3-0} = 0b0000; 2541 let Predicates = [HasVFP2]; 2542 let Unpredictable{7-5} = 0b111; 2543 let Unpredictable{3-0} = 0b1111; 2544} 2545 2546let DecoderMethod = "DecodeForVMRSandVMSR" in { 2547 let Defs = [FPSCR] in { 2548 let Predicates = [HasFPRegs] in 2549 // Application level GPR -> FPSCR 2550 def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPRnopc:$Rt), 2551 "vmsr", "\tfpscr, $Rt", 2552 [(int_arm_set_fpscr GPRnopc:$Rt)]>; 2553 // System level GPR -> FPEXC 2554 def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPRnopc:$Rt), 2555 "vmsr", "\tfpexc, $Rt", []>; 2556 // System level GPR -> FPSID 2557 def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPRnopc:$Rt), 2558 "vmsr", "\tfpsid, $Rt", []>; 2559 def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPRnopc:$Rt), 2560 "vmsr", "\tfpinst, $Rt", []>; 2561 def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPRnopc:$Rt), 2562 "vmsr", "\tfpinst2, $Rt", []>; 2563 } 2564 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2565 // System level GPR -> FPSCR with context saving for security extensions 2566 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2567 "vmsr", "\tfpcxtns, $Rt", []>; 2568 } 2569 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2570 // System level GPR -> FPSCR with context saving for security extensions 2571 def VMSR_FPCXTS : MovToVFP<0b1111 /* fpcxts */, (outs), (ins GPR:$Rt), 2572 "vmsr", "\tfpcxts, $Rt", []>; 2573 } 2574 let Predicates = [HasV8_1MMainline, HasFPRegs] in { 2575 // System level GPR -> FPSCR_NZCVQC 2576 def VMSR_FPSCR_NZCVQC 2577 : MovToVFP<0b0010 /* fpscr_nzcvqc */, 2578 (outs cl_FPSCR_NZCV:$fpscr_out), (ins GPR:$Rt), 2579 "vmsr", "\tfpscr_nzcvqc, $Rt", []>; 2580 } 2581 2582 let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2583 // System level GPR -> VPR/P0 2584 let Defs = [VPR] in 2585 def VMSR_VPR : MovToVFP<0b1100 /* vpr */, (outs), (ins GPR:$Rt), 2586 "vmsr", "\tvpr, $Rt", []>; 2587 2588 def VMSR_P0 : MovToVFP<0b1101 /* p0 */, (outs VCCR:$cond), (ins GPR:$Rt), 2589 "vmsr", "\tp0, $Rt", []>; 2590 } 2591} 2592 2593//===----------------------------------------------------------------------===// 2594// Misc. 2595// 2596 2597// Materialize FP immediates. VFP3 only. 2598let isReMaterializable = 1 in { 2599def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm), 2600 VFPMiscFrm, IIC_fpUNA64, 2601 "vmov", ".f64\t$Dd, $imm", 2602 [(set DPR:$Dd, vfp_f64imm:$imm)]>, 2603 Requires<[HasVFP3,HasDPVFP]> { 2604 bits<5> Dd; 2605 bits<8> imm; 2606 2607 let Inst{27-23} = 0b11101; 2608 let Inst{22} = Dd{4}; 2609 let Inst{21-20} = 0b11; 2610 let Inst{19-16} = imm{7-4}; 2611 let Inst{15-12} = Dd{3-0}; 2612 let Inst{11-9} = 0b101; 2613 let Inst{8} = 1; // Double precision. 2614 let Inst{7-4} = 0b0000; 2615 let Inst{3-0} = imm{3-0}; 2616} 2617 2618def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm), 2619 VFPMiscFrm, IIC_fpUNA32, 2620 "vmov", ".f32\t$Sd, $imm", 2621 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> { 2622 bits<5> Sd; 2623 bits<8> imm; 2624 2625 let Inst{27-23} = 0b11101; 2626 let Inst{22} = Sd{0}; 2627 let Inst{21-20} = 0b11; 2628 let Inst{19-16} = imm{7-4}; 2629 let Inst{15-12} = Sd{4-1}; 2630 let Inst{11-9} = 0b101; 2631 let Inst{8} = 0; // Single precision. 2632 let Inst{7-4} = 0b0000; 2633 let Inst{3-0} = imm{3-0}; 2634} 2635 2636def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm), 2637 VFPMiscFrm, IIC_fpUNA16, 2638 "vmov", ".f16\t$Sd, $imm", 2639 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>, 2640 Requires<[HasFullFP16]> { 2641 bits<5> Sd; 2642 bits<8> imm; 2643 2644 let Inst{27-23} = 0b11101; 2645 let Inst{22} = Sd{0}; 2646 let Inst{21-20} = 0b11; 2647 let Inst{19-16} = imm{7-4}; 2648 let Inst{15-12} = Sd{4-1}; 2649 let Inst{11-8} = 0b1001; // Half precision 2650 let Inst{7-4} = 0b0000; 2651 let Inst{3-0} = imm{3-0}; 2652 2653 let isUnpredicable = 1; 2654} 2655} 2656 2657def : Pat<(f32 (vfp_f32f16imm:$imm)), 2658 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> { 2659 let Predicates = [HasFullFP16]; 2660} 2661 2662//===----------------------------------------------------------------------===// 2663// Assembler aliases. 2664// 2665// A few mnemonic aliases for pre-unifixed syntax. We don't guarantee to 2666// support them all, but supporting at least some of the basics is 2667// good to be friendly. 2668def : VFP2MnemonicAlias<"flds", "vldr">; 2669def : VFP2MnemonicAlias<"fldd", "vldr">; 2670def : VFP2MnemonicAlias<"fmrs", "vmov">; 2671def : VFP2MnemonicAlias<"fmsr", "vmov">; 2672def : VFP2MnemonicAlias<"fsqrts", "vsqrt">; 2673def : VFP2MnemonicAlias<"fsqrtd", "vsqrt">; 2674def : VFP2MnemonicAlias<"fadds", "vadd.f32">; 2675def : VFP2MnemonicAlias<"faddd", "vadd.f64">; 2676def : VFP2MnemonicAlias<"fmrdd", "vmov">; 2677def : VFP2MnemonicAlias<"fmrds", "vmov">; 2678def : VFP2MnemonicAlias<"fmrrd", "vmov">; 2679def : VFP2MnemonicAlias<"fmdrr", "vmov">; 2680def : VFP2MnemonicAlias<"fmuls", "vmul.f32">; 2681def : VFP2MnemonicAlias<"fmuld", "vmul.f64">; 2682def : VFP2MnemonicAlias<"fnegs", "vneg.f32">; 2683def : VFP2MnemonicAlias<"fnegd", "vneg.f64">; 2684def : VFP2MnemonicAlias<"ftosizd", "vcvt.s32.f64">; 2685def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">; 2686def : VFP2MnemonicAlias<"ftosizs", "vcvt.s32.f32">; 2687def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">; 2688def : VFP2MnemonicAlias<"ftouizd", "vcvt.u32.f64">; 2689def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">; 2690def : VFP2MnemonicAlias<"ftouizs", "vcvt.u32.f32">; 2691def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">; 2692def : VFP2MnemonicAlias<"fsitod", "vcvt.f64.s32">; 2693def : VFP2MnemonicAlias<"fsitos", "vcvt.f32.s32">; 2694def : VFP2MnemonicAlias<"fuitod", "vcvt.f64.u32">; 2695def : VFP2MnemonicAlias<"fuitos", "vcvt.f32.u32">; 2696def : VFP2MnemonicAlias<"fsts", "vstr">; 2697def : VFP2MnemonicAlias<"fstd", "vstr">; 2698def : VFP2MnemonicAlias<"fmacd", "vmla.f64">; 2699def : VFP2MnemonicAlias<"fmacs", "vmla.f32">; 2700def : VFP2MnemonicAlias<"fcpys", "vmov.f32">; 2701def : VFP2MnemonicAlias<"fcpyd", "vmov.f64">; 2702def : VFP2MnemonicAlias<"fcmps", "vcmp.f32">; 2703def : VFP2MnemonicAlias<"fcmpd", "vcmp.f64">; 2704def : VFP2MnemonicAlias<"fdivs", "vdiv.f32">; 2705def : VFP2MnemonicAlias<"fdivd", "vdiv.f64">; 2706def : VFP2MnemonicAlias<"fmrx", "vmrs">; 2707def : VFP2MnemonicAlias<"fmxr", "vmsr">; 2708 2709// Be friendly and accept the old form of zero-compare 2710def : VFP2DPInstAlias<"fcmpzd${p} $val", (VCMPZD DPR:$val, pred:$p)>; 2711def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>; 2712 2713 2714def : InstAlias<"fmstat${p}", (FMSTAT pred:$p), 0>, Requires<[HasFPRegs]>; 2715def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm", 2716 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2717def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm", 2718 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2719def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm", 2720 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>; 2721def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm", 2722 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>; 2723 2724// No need for the size suffix on VSQRT. It's implied by the register classes. 2725def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>; 2726def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>; 2727 2728// VLDR/VSTR accept an optional type suffix. 2729def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr", 2730 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2731def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr", 2732 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>; 2733def : VFP2InstAlias<"vldr${p}.64 $Dd, $addr", 2734 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2735def : VFP2InstAlias<"vstr${p}.64 $Dd, $addr", 2736 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>; 2737 2738// VMOV can accept optional 32-bit or less data type suffix suffix. 2739def : VFP2InstAlias<"vmov${p}.8 $Rt, $Sn", 2740 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2741def : VFP2InstAlias<"vmov${p}.16 $Rt, $Sn", 2742 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2743def : VFP2InstAlias<"vmov${p}.32 $Rt, $Sn", 2744 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; 2745def : VFP2InstAlias<"vmov${p}.8 $Sn, $Rt", 2746 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2747def : VFP2InstAlias<"vmov${p}.16 $Sn, $Rt", 2748 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2749def : VFP2InstAlias<"vmov${p}.32 $Sn, $Rt", 2750 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; 2751 2752def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", 2753 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; 2754def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", 2755 (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; 2756 2757// VMOVS doesn't need the .f32 to disambiguate from the NEON encoding the way 2758// VMOVD does. 2759def : VFP2InstAlias<"vmov${p} $Sd, $Sm", 2760 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>; 2761 2762// FCONSTD/FCONSTS alias for vmov.f64/vmov.f32 2763// These aliases provide added functionality over vmov.f instructions by 2764// allowing users to write assembly containing encoded floating point constants 2765// (e.g. #0x70 vs #1.0). Without these alises there is no way for the 2766// assembler to accept encoded fp constants (but the equivalent fp-literal is 2767// accepted directly by vmovf). 2768def : VFP3InstAlias<"fconstd${p} $Dd, $val", 2769 (FCONSTD DPR:$Dd, vfp_f64imm:$val, pred:$p)>; 2770def : VFP3InstAlias<"fconsts${p} $Sd, $val", 2771 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>; 2772 2773def VSCCLRMD : VFPXI<(outs), (ins pred:$p, fp_dreglist_with_vpr:$regs, variable_ops), 2774 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2775 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2776 bits<13> regs; 2777 let Inst{31-23} = 0b111011001; 2778 let Inst{22} = regs{12}; 2779 let Inst{21-16} = 0b011111; 2780 let Inst{15-12} = regs{11-8}; 2781 let Inst{11-8} = 0b1011; 2782 let Inst{7-1} = regs{7-1}; 2783 let Inst{0} = 0; 2784 2785 let DecoderMethod = "DecodeVSCCLRM"; 2786 2787 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2788} 2789 2790def VSCCLRMS : VFPXI<(outs), (ins pred:$p, fp_sreglist_with_vpr:$regs, variable_ops), 2791 AddrModeNone, 4, IndexModeNone, VFPMiscFrm, NoItinerary, 2792 "vscclrm{$p}\t$regs", "", []>, Sched<[]> { 2793 bits<13> regs; 2794 let Inst{31-23} = 0b111011001; 2795 let Inst{22} = regs{8}; 2796 let Inst{21-16} = 0b011111; 2797 let Inst{15-12} = regs{12-9}; 2798 let Inst{11-8} = 0b1010; 2799 let Inst{7-0} = regs{7-0}; 2800 2801 let DecoderMethod = "DecodeVSCCLRM"; 2802 2803 list<Predicate> Predicates = [HasV8_1MMainline, Has8MSecExt]; 2804} 2805 2806//===----------------------------------------------------------------------===// 2807// Store VFP System Register to memory. 2808// 2809 2810class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg, 2811 dag oops, dag iops, IndexMode im, string Dest, string cstr> 2812 : VFPI<oops, iops, AddrModeT2_i7s4, 4, im, VFPLdStFrm, IIC_fpSTAT, 2813 !if(opc,"vldr","vstr"), !strconcat("\t", sysreg, ", ", Dest), cstr, []>, 2814 Sched<[]> { 2815 bits<12> addr; 2816 let Inst{27-25} = 0b110; 2817 let Inst{24} = P; 2818 let Inst{23} = addr{7}; 2819 let Inst{22} = SysReg{3}; 2820 let Inst{21} = W; 2821 let Inst{20} = opc; 2822 let Inst{19-16} = addr{11-8}; 2823 let Inst{15-13} = SysReg{2-0}; 2824 let Inst{12-7} = 0b011111; 2825 let Inst{6-0} = addr{6-0}; 2826 list<Predicate> Predicates = [HasFPRegs, HasV8_1MMainline]; 2827 let mayLoad = opc; 2828 let mayStore = !if(opc, 0b0, 0b1); 2829 let hasSideEffects = 1; 2830} 2831 2832multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg, 2833 dag oops=(outs), dag iops=(ins)> { 2834 def _off : 2835 vfp_vstrldr<opc, 1, 0, SysReg, sysreg, 2836 oops, !con(iops, (ins t2addrmode_imm7s4:$addr)), 2837 IndexModePost, "$addr", "" > { 2838 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<false>"; 2839 } 2840 2841 def _pre : 2842 vfp_vstrldr<opc, 1, 1, SysReg, sysreg, 2843 !con(oops, (outs GPRnopc:$wb)), 2844 !con(iops, (ins t2addrmode_imm7s4_pre:$addr)), 2845 IndexModePre, "$addr!", "$addr.base = $wb"> { 2846 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2847 } 2848 2849 def _post : 2850 vfp_vstrldr<opc, 0, 1, SysReg, sysreg, 2851 !con(oops, (outs GPRnopc:$wb)), 2852 !con(iops, (ins t2_addr_offset_none:$Rn, 2853 t2am_imm7s4_offset:$addr)), 2854 IndexModePost, "$Rn$addr", "$Rn.base = $wb"> { 2855 bits<4> Rn; 2856 let Inst{19-16} = Rn{3-0}; 2857 let DecoderMethod = "DecodeVSTRVLDR_SYSREG<true>"; 2858 } 2859} 2860 2861let Defs = [FPSCR] in { 2862 defm VSTR_FPSCR : vfp_vstrldr_sysreg<0b0,0b0001, "fpscr">; 2863 defm VSTR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b0,0b0010, "fpscr_nzcvqc">; 2864 2865 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2866 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2867 defm VSTR_FPCXTS : vfp_vstrldr_sysreg<0b0,0b1111, "fpcxts">; 2868 } 2869} 2870 2871let Predicates = [HasV8_1MMainline, HasMVEInt] in { 2872 let Uses = [VPR] in { 2873 defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">; 2874 } 2875 defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0", 2876 (outs), (ins VCCR:$P0)>; 2877 2878 let Defs = [VPR] in { 2879 defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; 2880 } 2881 defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", 2882 (outs VCCR:$P0), (ins)>; 2883} 2884 2885let Uses = [FPSCR] in { 2886 defm VLDR_FPSCR : vfp_vstrldr_sysreg<0b1,0b0001, "fpscr">; 2887 defm VLDR_FPSCR_NZCVQC : vfp_vstrldr_sysreg<0b1,0b0010, "fpscr_nzcvqc">; 2888 2889 let Predicates = [HasV8_1MMainline, Has8MSecExt] in { 2890 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">; 2891 defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">; 2892 } 2893} 2894